1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
11 #include <sys/queue.h>
14 #include <rte_bus_pci.h>
15 #include <rte_ethdev_driver.h>
16 #include <rte_memory.h>
17 #include <rte_lcore.h>
18 #include <rte_spinlock.h>
22 #include "bnxt_util.h"
25 #define PCI_VENDOR_ID_BROADCOM 0x14E4
28 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
29 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
30 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
31 #define BROADCOM_DEV_ID_57414_VF 0x16c1
32 #define BROADCOM_DEV_ID_57301 0x16c8
33 #define BROADCOM_DEV_ID_57302 0x16c9
34 #define BROADCOM_DEV_ID_57304_PF 0x16ca
35 #define BROADCOM_DEV_ID_57304_VF 0x16cb
36 #define BROADCOM_DEV_ID_57417_MF 0x16cc
37 #define BROADCOM_DEV_ID_NS2 0x16cd
38 #define BROADCOM_DEV_ID_57311 0x16ce
39 #define BROADCOM_DEV_ID_57312 0x16cf
40 #define BROADCOM_DEV_ID_57402 0x16d0
41 #define BROADCOM_DEV_ID_57404 0x16d1
42 #define BROADCOM_DEV_ID_57406_PF 0x16d2
43 #define BROADCOM_DEV_ID_57406_VF 0x16d3
44 #define BROADCOM_DEV_ID_57402_MF 0x16d4
45 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
46 #define BROADCOM_DEV_ID_57412 0x16d6
47 #define BROADCOM_DEV_ID_57414 0x16d7
48 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
49 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
50 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
51 #define BROADCOM_DEV_ID_57412_MF 0x16de
52 #define BROADCOM_DEV_ID_57314 0x16df
53 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
54 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
55 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
56 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
57 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
58 #define BROADCOM_DEV_ID_57404_MF 0x16e7
59 #define BROADCOM_DEV_ID_57406_MF 0x16e8
60 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
61 #define BROADCOM_DEV_ID_57407_MF 0x16ea
62 #define BROADCOM_DEV_ID_57414_MF 0x16ec
63 #define BROADCOM_DEV_ID_57416_MF 0x16ee
64 #define BROADCOM_DEV_ID_57508 0x1750
65 #define BROADCOM_DEV_ID_57504 0x1751
66 #define BROADCOM_DEV_ID_57502 0x1752
67 #define BROADCOM_DEV_ID_57508_MF1 0x1800
68 #define BROADCOM_DEV_ID_57504_MF1 0x1801
69 #define BROADCOM_DEV_ID_57502_MF1 0x1802
70 #define BROADCOM_DEV_ID_57508_MF2 0x1803
71 #define BROADCOM_DEV_ID_57504_MF2 0x1804
72 #define BROADCOM_DEV_ID_57502_MF2 0x1805
73 #define BROADCOM_DEV_ID_57500_VF1 0x1806
74 #define BROADCOM_DEV_ID_57500_VF2 0x1807
75 #define BROADCOM_DEV_ID_58802 0xd802
76 #define BROADCOM_DEV_ID_58804 0xd804
77 #define BROADCOM_DEV_ID_58808 0x16f0
78 #define BROADCOM_DEV_ID_58802_VF 0xd800
80 #define BNXT_MAX_MTU 9574
81 #define VLAN_TAG_SIZE 4
82 #define BNXT_NUM_VLANS 2
83 #define BNXT_MAX_PKT_LEN (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\
85 (BNXT_NUM_VLANS * VLAN_TAG_SIZE))
86 /* FW adds extra 4 bytes for FCS */
87 #define BNXT_VNIC_MRU(mtu)\
88 ((mtu) + RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE * BNXT_NUM_VLANS)
89 #define BNXT_VF_RSV_NUM_RSS_CTX 1
90 #define BNXT_VF_RSV_NUM_L2_CTX 4
91 /* TODO: For now, do not support VMDq/RFS on VFs. */
92 #define BNXT_VF_RSV_NUM_VNIC 1
93 #define BNXT_MAX_LED 4
94 #define BNXT_MIN_RING_DESC 16
95 #define BNXT_MAX_TX_RING_DESC 4096
96 #define BNXT_MAX_RX_RING_DESC 8192
97 #define BNXT_DB_SIZE 0x80
99 #define TPA_MAX_AGGS 64
100 #define TPA_MAX_AGGS_TH 1024
102 #define TPA_MAX_NUM_SEGS 32
103 #define TPA_MAX_SEGS_TH 8 /* 32 segments in 4-segment units */
104 #define TPA_MAX_SEGS 5 /* 32 segments in log2 units */
106 #define BNXT_TPA_MAX_AGGS(bp) \
107 (BNXT_CHIP_THOR(bp) ? TPA_MAX_AGGS_TH : \
110 #define BNXT_TPA_MAX_SEGS(bp) \
111 (BNXT_CHIP_THOR(bp) ? TPA_MAX_SEGS_TH : \
114 #ifdef RTE_ARCH_ARM64
115 #define BNXT_NUM_ASYNC_CPR(bp) (BNXT_STINGRAY(bp) ? 0 : 1)
117 #define BNXT_NUM_ASYNC_CPR(bp) 1
120 #define BNXT_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
121 #define BNXT_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
123 /* Chimp Communication Channel */
124 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET 0x0
125 #define GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
126 /* Kong Communication Channel */
127 #define GRCPF_REG_KONG_CHANNEL_OFFSET 0xA00
128 #define GRCPF_REG_KONG_COMM_TRIGGER 0xB00
130 #define BNXT_INT_LAT_TMR_MIN 75
131 #define BNXT_INT_LAT_TMR_MAX 150
132 #define BNXT_NUM_CMPL_AGGR_INT 36
133 #define BNXT_CMPL_AGGR_DMA_TMR 37
134 #define BNXT_NUM_CMPL_DMA_AGGR 36
135 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT 50
136 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT 12
138 struct bnxt_led_info {
141 uint8_t led_group_id;
143 uint16_t led_state_caps;
144 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
145 rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
147 uint16_t led_color_caps;
150 struct bnxt_led_cfg {
155 uint16_t led_blink_on;
156 uint16_t led_blink_off;
157 uint8_t led_group_id;
161 #define BNXT_LED_DFLT_ENA \
162 (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID | \
163 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE | \
164 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON | \
165 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF | \
166 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
168 #define BNXT_LED_DFLT_ENA_SHIFT 6
170 #define BNXT_LED_DFLT_ENABLES(x) \
171 rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
173 enum bnxt_hw_context {
175 HW_CONTEXT_IS_RSS = 1,
176 HW_CONTEXT_IS_COS = 2,
177 HW_CONTEXT_IS_LB = 3,
180 struct bnxt_vlan_table_entry {
183 } __attribute__((packed));
185 struct bnxt_vlan_antispoof_table_entry {
189 } __attribute__((packed));
191 struct bnxt_child_vf_info {
193 struct bnxt_vlan_table_entry *vlan_table;
194 struct bnxt_vlan_antispoof_table_entry *vlan_as_table;
195 STAILQ_HEAD(, bnxt_filter_info) filter;
196 uint32_t func_cfg_flags;
199 uint16_t max_tx_rate;
202 uint8_t mac_spoof_en;
203 uint8_t vlan_spoof_en;
208 struct bnxt_pf_info {
209 #define BNXT_FIRST_PF_FID 1
210 #define BNXT_MAX_VFS(bp) (bp->pf.max_vfs)
211 #define BNXT_TOTAL_VFS(bp) ((bp)->pf.total_vfs)
212 #define BNXT_FIRST_VF_FID 128
213 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp)
214 #define BNXT_PF_RINGS_AVAIL(bp) (bp->pf.max_cp_rings - BNXT_PF_RINGS_USED(bp))
216 uint16_t first_vf_id;
219 uint16_t total_vfs; /* Total VFs possible.
220 * Not necessarily enabled.
222 uint32_t func_cfg_flags;
224 rte_iova_t vf_req_buf_dma_addr;
225 uint32_t vf_req_fwd[8];
226 uint16_t total_vnics;
227 struct bnxt_child_vf_info *vf_info;
228 #define BNXT_EVB_MODE_NONE 0
229 #define BNXT_EVB_MODE_VEB 1
230 #define BNXT_EVB_MODE_VEPA 2
234 /* Max wait time is 10 * 100ms = 1s */
235 #define BNXT_LINK_WAIT_CNT 10
236 #define BNXT_LINK_WAIT_INTERVAL 100
237 struct bnxt_link_info {
240 uint8_t phy_link_status;
248 #define PHY_VER_LEN 3
249 uint8_t phy_ver[PHY_VER_LEN];
251 uint16_t support_speeds;
252 uint16_t auto_link_speed;
253 uint16_t force_link_speed;
254 uint16_t auto_link_speed_mask;
255 uint32_t preemphasis;
260 #define BNXT_COS_QUEUE_COUNT 8
261 struct bnxt_cos_queue_info {
267 STAILQ_ENTRY(rte_flow) next;
268 struct bnxt_filter_info *filter;
269 struct bnxt_vnic_info *vnic;
272 #define BNXT_PTP_FLAGS_PATH_TX 0x0
273 #define BNXT_PTP_FLAGS_PATH_RX 0x1
274 #define BNXT_PTP_FLAGS_CURRENT_TIME 0x2
276 struct bnxt_ptp_cfg {
277 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
278 #define BNXT_GRCPF_REG_SYNC_TIME 0x480
279 #define BNXT_CYCLECOUNTER_MASK 0xffffffffffffffffULL
280 struct rte_timecounter tc;
281 struct rte_timecounter tx_tstamp_tc;
282 struct rte_timecounter rx_tstamp_tc;
284 #define BNXT_MAX_TX_TS 1
286 #define BNXT_PTP_MSG_SYNC BIT(0)
287 #define BNXT_PTP_MSG_DELAY_REQ BIT(1)
288 #define BNXT_PTP_MSG_PDELAY_REQ BIT(2)
289 #define BNXT_PTP_MSG_PDELAY_RESP BIT(3)
290 #define BNXT_PTP_MSG_FOLLOW_UP BIT(8)
291 #define BNXT_PTP_MSG_DELAY_RESP BIT(9)
292 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP BIT(10)
293 #define BNXT_PTP_MSG_ANNOUNCE BIT(11)
294 #define BNXT_PTP_MSG_SIGNALING BIT(12)
295 #define BNXT_PTP_MSG_MANAGEMENT BIT(13)
296 #define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \
297 BNXT_PTP_MSG_DELAY_REQ | \
298 BNXT_PTP_MSG_PDELAY_REQ | \
299 BNXT_PTP_MSG_PDELAY_RESP)
300 uint8_t tx_tstamp_en:1;
303 #define BNXT_PTP_RX_TS_L 0
304 #define BNXT_PTP_RX_TS_H 1
305 #define BNXT_PTP_RX_SEQ 2
306 #define BNXT_PTP_RX_FIFO 3
307 #define BNXT_PTP_RX_FIFO_PENDING 0x1
308 #define BNXT_PTP_RX_FIFO_ADV 4
309 #define BNXT_PTP_RX_REGS 5
311 #define BNXT_PTP_TX_TS_L 0
312 #define BNXT_PTP_TX_TS_H 1
313 #define BNXT_PTP_TX_SEQ 2
314 #define BNXT_PTP_TX_FIFO 3
315 #define BNXT_PTP_TX_FIFO_EMPTY 0x2
316 #define BNXT_PTP_TX_REGS 4
317 uint32_t rx_regs[BNXT_PTP_RX_REGS];
318 uint32_t rx_mapped_regs[BNXT_PTP_RX_REGS];
319 uint32_t tx_regs[BNXT_PTP_TX_REGS];
320 uint32_t tx_mapped_regs[BNXT_PTP_TX_REGS];
322 /* On Thor, the Rx timestamp is present in the Rx completion record */
323 uint64_t rx_timestamp;
327 uint16_t num_cmpl_aggr_int;
328 uint16_t num_cmpl_dma_aggr;
329 uint16_t num_cmpl_dma_aggr_during_int;
330 uint16_t int_lat_tmr_max;
331 uint16_t int_lat_tmr_min;
332 uint16_t cmpl_aggr_dma_tmr;
333 uint16_t cmpl_aggr_dma_tmr_during_int;
336 /* 64-bit doorbell */
337 #define DBR_XID_SFT 32
338 #define DBR_PATH_L2 (0x1ULL << 56)
339 #define DBR_TYPE_SQ (0x0ULL << 60)
340 #define DBR_TYPE_SRQ (0x2ULL << 60)
341 #define DBR_TYPE_CQ (0x4ULL << 60)
342 #define DBR_TYPE_NQ (0xaULL << 60)
343 #define DBR_TYPE_NQ_ARM (0xbULL << 60)
345 #define BNXT_RSS_TBL_SIZE_THOR 512
346 #define BNXT_RSS_ENTRIES_PER_CTX_THOR 64
347 #define BNXT_MAX_RSS_CTXTS_THOR \
348 (BNXT_RSS_TBL_SIZE_THOR / BNXT_RSS_ENTRIES_PER_CTX_THOR)
350 #define BNXT_MAX_TC 8
351 #define BNXT_MAX_QUEUE 8
352 #define BNXT_MAX_TC_Q (BNXT_MAX_TC + 1)
353 #define BNXT_MAX_Q (bp->max_q + 1)
354 #define BNXT_PAGE_SHFT 12
355 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT)
356 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
358 #define PTU_PTE_VALID 0x1UL
359 #define PTU_PTE_LAST 0x2UL
360 #define PTU_PTE_NEXT_TO_LAST 0x4UL
362 struct bnxt_ring_mem_info {
366 #define BNXT_RMEM_VALID_PTE_FLAG 1
367 #define BNXT_RMEM_RING_PTE_FLAG 2
371 const struct rte_memzone *mz;
374 rte_iova_t pg_tbl_map;
375 const struct rte_memzone *pg_tbl_mz;
381 struct bnxt_ctx_pg_info {
383 void *ctx_pg_arr[MAX_CTX_PAGES];
384 rte_iova_t ctx_dma_arr[MAX_CTX_PAGES];
385 struct bnxt_ring_mem_info ring_mem;
388 struct bnxt_ctx_mem_info {
389 uint32_t qp_max_entries;
390 uint16_t qp_min_qp1_entries;
391 uint16_t qp_max_l2_entries;
392 uint16_t qp_entry_size;
393 uint16_t srq_max_l2_entries;
394 uint32_t srq_max_entries;
395 uint16_t srq_entry_size;
396 uint16_t cq_max_l2_entries;
397 uint32_t cq_max_entries;
398 uint16_t cq_entry_size;
399 uint16_t vnic_max_vnic_entries;
400 uint16_t vnic_max_ring_table_entries;
401 uint16_t vnic_entry_size;
402 uint32_t stat_max_entries;
403 uint16_t stat_entry_size;
404 uint16_t tqm_entry_size;
405 uint32_t tqm_min_entries_per_ring;
406 uint32_t tqm_max_entries_per_ring;
407 uint32_t mrav_max_entries;
408 uint16_t mrav_entry_size;
409 uint16_t tim_entry_size;
410 uint32_t tim_max_entries;
411 uint8_t tqm_entries_multiple;
414 #define BNXT_CTX_FLAG_INITED 0x01
416 struct bnxt_ctx_pg_info qp_mem;
417 struct bnxt_ctx_pg_info srq_mem;
418 struct bnxt_ctx_pg_info cq_mem;
419 struct bnxt_ctx_pg_info vnic_mem;
420 struct bnxt_ctx_pg_info stat_mem;
421 struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q];
424 /* Maximum Firmware Reset bail out value in milliseconds */
425 #define BNXT_MAX_FW_RESET_TIMEOUT 6000
426 /* Minimum time required for the firmware readiness in milliseconds */
427 #define BNXT_MIN_FW_READY_TIMEOUT 2000
428 /* Frequency for the firmware readiness check in milliseconds */
429 #define BNXT_FW_READY_WAIT_INTERVAL 100
431 #define US_PER_MS 1000
432 #define NS_PER_US 1000
434 struct bnxt_error_recovery_info {
435 /* All units in milliseconds */
436 uint32_t driver_polling_freq;
437 uint32_t master_func_wait_period;
438 uint32_t normal_func_wait_period;
439 uint32_t master_func_wait_period_after_reset;
440 uint32_t max_bailout_time_after_reset;
441 #define BNXT_FW_STATUS_REG 0
442 #define BNXT_FW_HEARTBEAT_CNT_REG 1
443 #define BNXT_FW_RECOVERY_CNT_REG 2
444 #define BNXT_FW_RESET_INPROG_REG 3
445 #define BNXT_FW_STATUS_REG_CNT 4
446 uint32_t status_regs[BNXT_FW_STATUS_REG_CNT];
447 uint32_t mapped_status_regs[BNXT_FW_STATUS_REG_CNT];
448 uint32_t reset_inprogress_reg_mask;
449 #define BNXT_NUM_RESET_REG 16
450 uint8_t reg_array_cnt;
451 uint32_t reset_reg[BNXT_NUM_RESET_REG];
452 uint32_t reset_reg_val[BNXT_NUM_RESET_REG];
453 uint8_t delay_after_reset[BNXT_NUM_RESET_REG];
454 #define BNXT_FLAG_ERROR_RECOVERY_HOST BIT(0)
455 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1)
456 #define BNXT_FLAG_MASTER_FUNC BIT(2)
457 #define BNXT_FLAG_RECOVERY_ENABLED BIT(3)
460 uint32_t last_heart_beat;
461 uint32_t last_reset_counter;
464 /* address space location of register */
465 #define BNXT_FW_STATUS_REG_TYPE_MASK 3
466 /* register is located in PCIe config space */
467 #define BNXT_FW_STATUS_REG_TYPE_CFG 0
468 /* register is located in GRC address space */
469 #define BNXT_FW_STATUS_REG_TYPE_GRC 1
470 /* register is located in BAR0 */
471 #define BNXT_FW_STATUS_REG_TYPE_BAR0 2
472 /* register is located in BAR1 */
473 #define BNXT_FW_STATUS_REG_TYPE_BAR1 3
475 #define BNXT_FW_STATUS_REG_TYPE(reg) ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK)
476 #define BNXT_FW_STATUS_REG_OFF(reg) ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK)
478 #define BNXT_GRCP_WINDOW_2_BASE 0x2000
479 #define BNXT_GRCP_WINDOW_3_BASE 0x3000
481 #define BNXT_FW_STATUS_SHUTDOWN 0x100000
483 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input)
487 struct rte_eth_dev *eth_dev;
488 struct rte_eth_rss_conf rss_conf;
489 struct rte_pci_device *pdev;
493 #define BNXT_FLAG_REGISTERED BIT(0)
494 #define BNXT_FLAG_VF BIT(1)
495 #define BNXT_FLAG_PORT_STATS BIT(2)
496 #define BNXT_FLAG_JUMBO BIT(3)
497 #define BNXT_FLAG_SHORT_CMD BIT(4)
498 #define BNXT_FLAG_UPDATE_HASH BIT(5)
499 #define BNXT_FLAG_PTP_SUPPORTED BIT(6)
500 #define BNXT_FLAG_MULTI_HOST BIT(7)
501 #define BNXT_FLAG_EXT_RX_PORT_STATS BIT(8)
502 #define BNXT_FLAG_EXT_TX_PORT_STATS BIT(9)
503 #define BNXT_FLAG_KONG_MB_EN BIT(10)
504 #define BNXT_FLAG_TRUSTED_VF_EN BIT(11)
505 #define BNXT_FLAG_DFLT_VNIC_SET BIT(12)
506 #define BNXT_FLAG_THOR_CHIP BIT(13)
507 #define BNXT_FLAG_STINGRAY BIT(14)
508 #define BNXT_FLAG_FW_RESET BIT(15)
509 #define BNXT_FLAG_FATAL_ERROR BIT(16)
510 #define BNXT_FLAG_FW_CAP_IF_CHANGE BIT(17)
511 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE BIT(18)
512 #define BNXT_FLAG_FW_CAP_ERROR_RECOVERY BIT(19)
513 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED BIT(20)
514 #define BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD BIT(21)
515 #define BNXT_FLAG_EXT_STATS_SUPPORTED BIT(22)
516 #define BNXT_FLAG_NEW_RM BIT(23)
517 #define BNXT_FLAG_INIT_DONE BIT(24)
518 #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS BIT(25)
519 #define BNXT_FLAG_ADV_FLOW_MGMT BIT(26)
520 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
521 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
522 #define BNXT_NPAR(bp) ((bp)->port_partition_type)
523 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
524 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
525 #define BNXT_USE_CHIMP_MB 0 //For non-CFA commands, everything uses Chimp.
526 #define BNXT_USE_KONG(bp) ((bp)->flags & BNXT_FLAG_KONG_MB_EN)
527 #define BNXT_VF_IS_TRUSTED(bp) ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN)
528 #define BNXT_CHIP_THOR(bp) ((bp)->flags & BNXT_FLAG_THOR_CHIP)
529 #define BNXT_STINGRAY(bp) ((bp)->flags & BNXT_FLAG_STINGRAY)
530 #define BNXT_HAS_NQ(bp) BNXT_CHIP_THOR(bp)
531 #define BNXT_HAS_RING_GRPS(bp) (!BNXT_CHIP_THOR(bp))
534 #define BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN BIT(0)
535 pthread_mutex_t flow_lock;
537 uint32_t vnic_cap_flags;
538 #define BNXT_VNIC_CAP_COS_CLASSIFY BIT(0)
539 unsigned int rx_nr_rings;
540 unsigned int rx_cp_nr_rings;
541 unsigned int rx_num_qs_per_vnic;
542 struct bnxt_rx_queue **rx_queues;
543 const void *rx_mem_zone;
544 struct rx_port_stats *hw_rx_port_stats;
545 rte_iova_t hw_rx_port_stats_map;
546 struct rx_port_stats_ext *hw_rx_port_stats_ext;
547 rte_iova_t hw_rx_port_stats_ext_map;
548 uint16_t fw_rx_port_stats_ext_size;
550 unsigned int tx_nr_rings;
551 unsigned int tx_cp_nr_rings;
552 struct bnxt_tx_queue **tx_queues;
553 const void *tx_mem_zone;
554 struct tx_port_stats *hw_tx_port_stats;
555 rte_iova_t hw_tx_port_stats_map;
556 struct tx_port_stats_ext *hw_tx_port_stats_ext;
557 rte_iova_t hw_tx_port_stats_ext_map;
558 uint16_t fw_tx_port_stats_ext_size;
560 /* Default completion ring */
561 struct bnxt_cp_ring_info *async_cp_ring;
562 struct bnxt_cp_ring_info *rxtx_nq_ring;
563 uint32_t max_ring_grps;
564 struct bnxt_ring_grp_info *grp_info;
566 unsigned int nr_vnics;
568 #define BNXT_GET_DEFAULT_VNIC(bp) (&(bp)->vnic_info[0])
569 struct bnxt_vnic_info *vnic_info;
570 STAILQ_HEAD(, bnxt_vnic_info) free_vnic_list;
572 struct bnxt_filter_info *filter_info;
573 STAILQ_HEAD(, bnxt_filter_info) free_filter_list;
575 struct bnxt_irq *irq_tbl;
577 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
579 uint16_t hwrm_cmd_seq;
580 uint16_t kong_cmd_seq;
581 void *hwrm_cmd_resp_addr;
582 rte_iova_t hwrm_cmd_resp_dma_addr;
583 void *hwrm_short_cmd_req_addr;
584 rte_iova_t hwrm_short_cmd_req_dma_addr;
585 rte_spinlock_t hwrm_lock;
586 pthread_mutex_t def_cp_lock;
587 uint16_t max_req_len;
588 uint16_t max_resp_len;
589 uint16_t hwrm_max_ext_req_len;
591 /* default command timeout value of 50ms */
592 #define HWRM_CMD_TIMEOUT 50000
593 /* default HWRM request timeout value */
594 uint32_t hwrm_cmd_timeout;
596 struct bnxt_link_info link_info;
597 struct bnxt_cos_queue_info rx_cos_queue[BNXT_COS_QUEUE_COUNT];
598 struct bnxt_cos_queue_info tx_cos_queue[BNXT_COS_QUEUE_COUNT];
599 uint8_t tx_cosq_id[BNXT_COS_QUEUE_COUNT];
606 uint8_t dflt_mac_addr[RTE_ETHER_ADDR_LEN];
607 uint16_t max_rsscos_ctx;
608 uint16_t max_cp_rings;
609 uint16_t max_tx_rings;
610 uint16_t max_rx_rings;
611 #define MAX_STINGRAY_RINGS 128U
612 #define BNXT_MAX_RINGS(bp) \
613 (BNXT_STINGRAY(bp) ? RTE_MIN(RTE_MIN(bp->max_rx_rings, \
614 MAX_STINGRAY_RINGS), \
615 bp->max_stat_ctx) : \
616 RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx))
618 uint16_t max_nq_rings;
620 uint16_t max_rx_em_flows;
622 uint16_t max_stat_ctx;
624 uint16_t first_vf_id;
626 #define BNXT_OUTER_TPID_MASK 0x0000ffff
627 #define BNXT_OUTER_TPID_BD_MASK 0xffff0000
628 #define BNXT_OUTER_TPID_BD_SHFT 16
629 uint32_t outer_tpid_bd;
630 struct bnxt_pf_info pf;
631 uint8_t port_partition_type;
633 uint8_t vxlan_port_cnt;
634 uint8_t geneve_port_cnt;
636 uint16_t geneve_port;
637 uint16_t vxlan_fw_dst_port_id;
638 uint16_t geneve_fw_dst_port_id;
640 uint32_t hwrm_spec_code;
642 struct bnxt_led_info leds[BNXT_MAX_LED];
644 struct bnxt_ptp_cfg *ptp_cfg;
645 uint16_t vf_resv_strategy;
646 struct bnxt_ctx_mem_info *ctx;
648 uint16_t fw_reset_min_msecs;
649 uint16_t fw_reset_max_msecs;
651 /* Struct to hold adapter error recovery related info */
652 struct bnxt_error_recovery_info *recovery_info;
655 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
656 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete);
657 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
658 int is_bnxt_in_error(struct bnxt *bp);
659 uint16_t bnxt_rss_ctxts(const struct bnxt *bp);
661 int bnxt_map_fw_health_status_regs(struct bnxt *bp);
662 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index);
663 void bnxt_schedule_fw_health_check(struct bnxt *bp);
665 bool is_bnxt_supported(struct rte_eth_dev *dev);
666 bool bnxt_stratus_device(struct bnxt *bp);
667 extern const struct rte_flow_ops bnxt_flow_ops;
668 #define bnxt_acquire_flow_lock(bp) \
669 pthread_mutex_lock(&(bp)->flow_lock)
671 #define bnxt_release_flow_lock(bp) \
672 pthread_mutex_unlock(&(bp)->flow_lock)
674 extern int bnxt_logtype_driver;
675 #define PMD_DRV_LOG_RAW(level, fmt, args...) \
676 rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \
679 #define PMD_DRV_LOG(level, fmt, args...) \
680 PMD_DRV_LOG_RAW(level, fmt, ## args)