1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
11 #include <sys/queue.h>
14 #include <rte_bus_pci.h>
15 #include <rte_ethdev_driver.h>
16 #include <rte_memory.h>
17 #include <rte_lcore.h>
18 #include <rte_spinlock.h>
22 #include "bnxt_util.h"
25 #define PCI_VENDOR_ID_BROADCOM 0x14E4
28 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
29 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
30 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
31 #define BROADCOM_DEV_ID_57414_VF 0x16c1
32 #define BROADCOM_DEV_ID_57301 0x16c8
33 #define BROADCOM_DEV_ID_57302 0x16c9
34 #define BROADCOM_DEV_ID_57304_PF 0x16ca
35 #define BROADCOM_DEV_ID_57304_VF 0x16cb
36 #define BROADCOM_DEV_ID_57417_MF 0x16cc
37 #define BROADCOM_DEV_ID_NS2 0x16cd
38 #define BROADCOM_DEV_ID_57311 0x16ce
39 #define BROADCOM_DEV_ID_57312 0x16cf
40 #define BROADCOM_DEV_ID_57402 0x16d0
41 #define BROADCOM_DEV_ID_57404 0x16d1
42 #define BROADCOM_DEV_ID_57406_PF 0x16d2
43 #define BROADCOM_DEV_ID_57406_VF 0x16d3
44 #define BROADCOM_DEV_ID_57402_MF 0x16d4
45 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
46 #define BROADCOM_DEV_ID_57412 0x16d6
47 #define BROADCOM_DEV_ID_57414 0x16d7
48 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
49 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
50 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
51 #define BROADCOM_DEV_ID_57412_MF 0x16de
52 #define BROADCOM_DEV_ID_57314 0x16df
53 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
54 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
55 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
56 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
57 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
58 #define BROADCOM_DEV_ID_57404_MF 0x16e7
59 #define BROADCOM_DEV_ID_57406_MF 0x16e8
60 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
61 #define BROADCOM_DEV_ID_57407_MF 0x16ea
62 #define BROADCOM_DEV_ID_57414_MF 0x16ec
63 #define BROADCOM_DEV_ID_57416_MF 0x16ee
64 #define BROADCOM_DEV_ID_57508 0x1750
65 #define BROADCOM_DEV_ID_57504 0x1751
66 #define BROADCOM_DEV_ID_57502 0x1752
67 #define BROADCOM_DEV_ID_57500_VF1 0x1806
68 #define BROADCOM_DEV_ID_57500_VF2 0x1807
69 #define BROADCOM_DEV_ID_58802 0xd802
70 #define BROADCOM_DEV_ID_58804 0xd804
71 #define BROADCOM_DEV_ID_58808 0x16f0
72 #define BROADCOM_DEV_ID_58802_VF 0xd800
74 #define BNXT_MAX_MTU 9574
75 #define VLAN_TAG_SIZE 4
76 #define BNXT_NUM_VLANS 2
77 #define BNXT_MAX_PKT_LEN (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\
79 (BNXT_NUM_VLANS * VLAN_TAG_SIZE))
80 #define BNXT_VF_RSV_NUM_RSS_CTX 1
81 #define BNXT_VF_RSV_NUM_L2_CTX 4
82 /* TODO: For now, do not support VMDq/RFS on VFs. */
83 #define BNXT_VF_RSV_NUM_VNIC 1
84 #define BNXT_MAX_LED 4
85 #define BNXT_MIN_RING_DESC 16
86 #define BNXT_MAX_TX_RING_DESC 4096
87 #define BNXT_MAX_RX_RING_DESC 8192
88 #define BNXT_DB_SIZE 0x80
90 #define TPA_MAX_AGGS 64
91 #define TPA_MAX_AGGS_TH 1024
93 #define TPA_MAX_NUM_SEGS 32
94 #define TPA_MAX_SEGS_TH 8 /* 32 segments in 4-segment units */
95 #define TPA_MAX_SEGS 5 /* 32 segments in log2 units */
97 #define BNXT_TPA_MAX_AGGS(bp) \
98 (BNXT_CHIP_THOR(bp) ? TPA_MAX_AGGS_TH : \
101 #define BNXT_TPA_MAX_SEGS(bp) \
102 (BNXT_CHIP_THOR(bp) ? TPA_MAX_SEGS_TH : \
105 #ifdef RTE_ARCH_ARM64
106 #define BNXT_NUM_ASYNC_CPR(bp) (BNXT_STINGRAY(bp) ? 0 : 1)
108 #define BNXT_NUM_ASYNC_CPR(bp) 1
111 #define BNXT_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
112 #define BNXT_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
114 /* Chimp Communication Channel */
115 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET 0x0
116 #define GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
117 /* Kong Communication Channel */
118 #define GRCPF_REG_KONG_CHANNEL_OFFSET 0xA00
119 #define GRCPF_REG_KONG_COMM_TRIGGER 0xB00
121 #define BNXT_INT_LAT_TMR_MIN 75
122 #define BNXT_INT_LAT_TMR_MAX 150
123 #define BNXT_NUM_CMPL_AGGR_INT 36
124 #define BNXT_CMPL_AGGR_DMA_TMR 37
125 #define BNXT_NUM_CMPL_DMA_AGGR 36
126 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT 50
127 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT 12
129 struct bnxt_led_info {
132 uint8_t led_group_id;
134 uint16_t led_state_caps;
135 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
136 rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
138 uint16_t led_color_caps;
141 struct bnxt_led_cfg {
146 uint16_t led_blink_on;
147 uint16_t led_blink_off;
148 uint8_t led_group_id;
152 #define BNXT_LED_DFLT_ENA \
153 (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID | \
154 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE | \
155 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON | \
156 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF | \
157 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
159 #define BNXT_LED_DFLT_ENA_SHIFT 6
161 #define BNXT_LED_DFLT_ENABLES(x) \
162 rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
164 enum bnxt_hw_context {
166 HW_CONTEXT_IS_RSS = 1,
167 HW_CONTEXT_IS_COS = 2,
168 HW_CONTEXT_IS_LB = 3,
171 struct bnxt_vlan_table_entry {
174 } __attribute__((packed));
176 struct bnxt_vlan_antispoof_table_entry {
180 } __attribute__((packed));
182 struct bnxt_child_vf_info {
184 struct bnxt_vlan_table_entry *vlan_table;
185 struct bnxt_vlan_antispoof_table_entry *vlan_as_table;
186 STAILQ_HEAD(, bnxt_filter_info) filter;
187 uint32_t func_cfg_flags;
190 uint16_t max_tx_rate;
193 uint8_t mac_spoof_en;
194 uint8_t vlan_spoof_en;
199 struct bnxt_pf_info {
200 #define BNXT_FIRST_PF_FID 1
201 #define BNXT_MAX_VFS(bp) (bp->pf.max_vfs)
202 #define BNXT_TOTAL_VFS(bp) ((bp)->pf.total_vfs)
203 #define BNXT_FIRST_VF_FID 128
204 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp)
205 #define BNXT_PF_RINGS_AVAIL(bp) (bp->pf.max_cp_rings - BNXT_PF_RINGS_USED(bp))
207 uint16_t first_vf_id;
210 uint16_t total_vfs; /* Total VFs possible.
211 * Not necessarily enabled.
213 uint32_t func_cfg_flags;
215 rte_iova_t vf_req_buf_dma_addr;
216 uint32_t vf_req_fwd[8];
217 uint16_t total_vnics;
218 struct bnxt_child_vf_info *vf_info;
219 #define BNXT_EVB_MODE_NONE 0
220 #define BNXT_EVB_MODE_VEB 1
221 #define BNXT_EVB_MODE_VEPA 2
225 /* Max wait time is 10 * 100ms = 1s */
226 #define BNXT_LINK_WAIT_CNT 10
227 #define BNXT_LINK_WAIT_INTERVAL 100
228 struct bnxt_link_info {
231 uint8_t phy_link_status;
239 #define PHY_VER_LEN 3
240 uint8_t phy_ver[PHY_VER_LEN];
242 uint16_t support_speeds;
243 uint16_t auto_link_speed;
244 uint16_t force_link_speed;
245 uint16_t auto_link_speed_mask;
246 uint32_t preemphasis;
251 #define BNXT_COS_QUEUE_COUNT 8
252 struct bnxt_cos_queue_info {
258 STAILQ_ENTRY(rte_flow) next;
259 struct bnxt_filter_info *filter;
260 struct bnxt_vnic_info *vnic;
263 #define BNXT_PTP_FLAGS_PATH_TX 0x0
264 #define BNXT_PTP_FLAGS_PATH_RX 0x1
265 #define BNXT_PTP_FLAGS_CURRENT_TIME 0x2
267 struct bnxt_ptp_cfg {
268 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
269 #define BNXT_GRCPF_REG_SYNC_TIME 0x480
270 #define BNXT_CYCLECOUNTER_MASK 0xffffffffffffffffULL
271 struct rte_timecounter tc;
272 struct rte_timecounter tx_tstamp_tc;
273 struct rte_timecounter rx_tstamp_tc;
275 #define BNXT_MAX_TX_TS 1
277 #define BNXT_PTP_MSG_SYNC BIT(0)
278 #define BNXT_PTP_MSG_DELAY_REQ BIT(1)
279 #define BNXT_PTP_MSG_PDELAY_REQ BIT(2)
280 #define BNXT_PTP_MSG_PDELAY_RESP BIT(3)
281 #define BNXT_PTP_MSG_FOLLOW_UP BIT(8)
282 #define BNXT_PTP_MSG_DELAY_RESP BIT(9)
283 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP BIT(10)
284 #define BNXT_PTP_MSG_ANNOUNCE BIT(11)
285 #define BNXT_PTP_MSG_SIGNALING BIT(12)
286 #define BNXT_PTP_MSG_MANAGEMENT BIT(13)
287 #define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \
288 BNXT_PTP_MSG_DELAY_REQ | \
289 BNXT_PTP_MSG_PDELAY_REQ | \
290 BNXT_PTP_MSG_PDELAY_RESP)
291 uint8_t tx_tstamp_en:1;
294 #define BNXT_PTP_RX_TS_L 0
295 #define BNXT_PTP_RX_TS_H 1
296 #define BNXT_PTP_RX_SEQ 2
297 #define BNXT_PTP_RX_FIFO 3
298 #define BNXT_PTP_RX_FIFO_PENDING 0x1
299 #define BNXT_PTP_RX_FIFO_ADV 4
300 #define BNXT_PTP_RX_REGS 5
302 #define BNXT_PTP_TX_TS_L 0
303 #define BNXT_PTP_TX_TS_H 1
304 #define BNXT_PTP_TX_SEQ 2
305 #define BNXT_PTP_TX_FIFO 3
306 #define BNXT_PTP_TX_FIFO_EMPTY 0x2
307 #define BNXT_PTP_TX_REGS 4
308 uint32_t rx_regs[BNXT_PTP_RX_REGS];
309 uint32_t rx_mapped_regs[BNXT_PTP_RX_REGS];
310 uint32_t tx_regs[BNXT_PTP_TX_REGS];
311 uint32_t tx_mapped_regs[BNXT_PTP_TX_REGS];
313 /* On Thor, the Rx timestamp is present in the Rx completion record */
314 uint64_t rx_timestamp;
318 uint16_t num_cmpl_aggr_int;
319 uint16_t num_cmpl_dma_aggr;
320 uint16_t num_cmpl_dma_aggr_during_int;
321 uint16_t int_lat_tmr_max;
322 uint16_t int_lat_tmr_min;
323 uint16_t cmpl_aggr_dma_tmr;
324 uint16_t cmpl_aggr_dma_tmr_during_int;
327 /* 64-bit doorbell */
328 #define DBR_XID_SFT 32
329 #define DBR_PATH_L2 (0x1ULL << 56)
330 #define DBR_TYPE_SQ (0x0ULL << 60)
331 #define DBR_TYPE_SRQ (0x2ULL << 60)
332 #define DBR_TYPE_CQ (0x4ULL << 60)
333 #define DBR_TYPE_NQ (0xaULL << 60)
334 #define DBR_TYPE_NQ_ARM (0xbULL << 60)
336 #define BNXT_RSS_TBL_SIZE_THOR 512
337 #define BNXT_RSS_ENTRIES_PER_CTX_THOR 64
338 #define BNXT_MAX_RSS_CTXTS_THOR \
339 (BNXT_RSS_TBL_SIZE_THOR / BNXT_RSS_ENTRIES_PER_CTX_THOR)
341 #define BNXT_MAX_TC 8
342 #define BNXT_MAX_QUEUE 8
343 #define BNXT_MAX_TC_Q (BNXT_MAX_TC + 1)
344 #define BNXT_MAX_Q (bp->max_q + 1)
345 #define BNXT_PAGE_SHFT 12
346 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT)
347 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
349 #define PTU_PTE_VALID 0x1UL
350 #define PTU_PTE_LAST 0x2UL
351 #define PTU_PTE_NEXT_TO_LAST 0x4UL
353 struct bnxt_ring_mem_info {
357 #define BNXT_RMEM_VALID_PTE_FLAG 1
358 #define BNXT_RMEM_RING_PTE_FLAG 2
362 const struct rte_memzone *mz;
365 rte_iova_t pg_tbl_map;
366 const struct rte_memzone *pg_tbl_mz;
372 struct bnxt_ctx_pg_info {
374 void *ctx_pg_arr[MAX_CTX_PAGES];
375 rte_iova_t ctx_dma_arr[MAX_CTX_PAGES];
376 struct bnxt_ring_mem_info ring_mem;
379 struct bnxt_ctx_mem_info {
380 uint32_t qp_max_entries;
381 uint16_t qp_min_qp1_entries;
382 uint16_t qp_max_l2_entries;
383 uint16_t qp_entry_size;
384 uint16_t srq_max_l2_entries;
385 uint32_t srq_max_entries;
386 uint16_t srq_entry_size;
387 uint16_t cq_max_l2_entries;
388 uint32_t cq_max_entries;
389 uint16_t cq_entry_size;
390 uint16_t vnic_max_vnic_entries;
391 uint16_t vnic_max_ring_table_entries;
392 uint16_t vnic_entry_size;
393 uint32_t stat_max_entries;
394 uint16_t stat_entry_size;
395 uint16_t tqm_entry_size;
396 uint32_t tqm_min_entries_per_ring;
397 uint32_t tqm_max_entries_per_ring;
398 uint32_t mrav_max_entries;
399 uint16_t mrav_entry_size;
400 uint16_t tim_entry_size;
401 uint32_t tim_max_entries;
402 uint8_t tqm_entries_multiple;
405 #define BNXT_CTX_FLAG_INITED 0x01
407 struct bnxt_ctx_pg_info qp_mem;
408 struct bnxt_ctx_pg_info srq_mem;
409 struct bnxt_ctx_pg_info cq_mem;
410 struct bnxt_ctx_pg_info vnic_mem;
411 struct bnxt_ctx_pg_info stat_mem;
412 struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q];
415 /* Maximum Firmware Reset bail out value in milliseconds */
416 #define BNXT_MAX_FW_RESET_TIMEOUT 6000
417 /* Minimum time required for the firmware readiness in milliseconds */
418 #define BNXT_MIN_FW_READY_TIMEOUT 2000
419 /* Frequency for the firmware readiness check in milliseconds */
420 #define BNXT_FW_READY_WAIT_INTERVAL 100
422 #define US_PER_MS 1000
423 #define NS_PER_US 1000
425 struct bnxt_error_recovery_info {
426 /* All units in milliseconds */
427 uint32_t driver_polling_freq;
428 uint32_t master_func_wait_period;
429 uint32_t normal_func_wait_period;
430 uint32_t master_func_wait_period_after_reset;
431 uint32_t max_bailout_time_after_reset;
432 #define BNXT_FW_STATUS_REG 0
433 #define BNXT_FW_HEARTBEAT_CNT_REG 1
434 #define BNXT_FW_RECOVERY_CNT_REG 2
435 #define BNXT_FW_RESET_INPROG_REG 3
436 #define BNXT_FW_STATUS_REG_CNT 4
437 uint32_t status_regs[BNXT_FW_STATUS_REG_CNT];
438 uint32_t mapped_status_regs[BNXT_FW_STATUS_REG_CNT];
439 uint32_t reset_inprogress_reg_mask;
440 #define BNXT_NUM_RESET_REG 16
441 uint8_t reg_array_cnt;
442 uint32_t reset_reg[BNXT_NUM_RESET_REG];
443 uint32_t reset_reg_val[BNXT_NUM_RESET_REG];
444 uint8_t delay_after_reset[BNXT_NUM_RESET_REG];
445 #define BNXT_FLAG_ERROR_RECOVERY_HOST BIT(0)
446 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1)
447 #define BNXT_FLAG_MASTER_FUNC BIT(2)
448 #define BNXT_FLAG_RECOVERY_ENABLED BIT(3)
451 uint32_t last_heart_beat;
452 uint32_t last_reset_counter;
455 /* address space location of register */
456 #define BNXT_FW_STATUS_REG_TYPE_MASK 3
457 /* register is located in PCIe config space */
458 #define BNXT_FW_STATUS_REG_TYPE_CFG 0
459 /* register is located in GRC address space */
460 #define BNXT_FW_STATUS_REG_TYPE_GRC 1
461 /* register is located in BAR0 */
462 #define BNXT_FW_STATUS_REG_TYPE_BAR0 2
463 /* register is located in BAR1 */
464 #define BNXT_FW_STATUS_REG_TYPE_BAR1 3
466 #define BNXT_FW_STATUS_REG_TYPE(reg) ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK)
467 #define BNXT_FW_STATUS_REG_OFF(reg) ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK)
469 #define BNXT_GRCP_WINDOW_2_BASE 0x2000
470 #define BNXT_GRCP_WINDOW_3_BASE 0x3000
472 #define BNXT_FW_STATUS_SHUTDOWN 0x100000
474 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input)
478 struct rte_eth_dev *eth_dev;
479 struct rte_eth_rss_conf rss_conf;
480 struct rte_pci_device *pdev;
484 #define BNXT_FLAG_REGISTERED BIT(0)
485 #define BNXT_FLAG_VF BIT(1)
486 #define BNXT_FLAG_PORT_STATS BIT(2)
487 #define BNXT_FLAG_JUMBO BIT(3)
488 #define BNXT_FLAG_SHORT_CMD BIT(4)
489 #define BNXT_FLAG_UPDATE_HASH BIT(5)
490 #define BNXT_FLAG_PTP_SUPPORTED BIT(6)
491 #define BNXT_FLAG_MULTI_HOST BIT(7)
492 #define BNXT_FLAG_EXT_RX_PORT_STATS BIT(8)
493 #define BNXT_FLAG_EXT_TX_PORT_STATS BIT(9)
494 #define BNXT_FLAG_KONG_MB_EN BIT(10)
495 #define BNXT_FLAG_TRUSTED_VF_EN BIT(11)
496 #define BNXT_FLAG_DFLT_VNIC_SET BIT(12)
497 #define BNXT_FLAG_THOR_CHIP BIT(13)
498 #define BNXT_FLAG_STINGRAY BIT(14)
499 #define BNXT_FLAG_FW_RESET BIT(15)
500 #define BNXT_FLAG_FATAL_ERROR BIT(16)
501 #define BNXT_FLAG_FW_CAP_IF_CHANGE BIT(17)
502 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE BIT(18)
503 #define BNXT_FLAG_FW_CAP_ERROR_RECOVERY BIT(19)
504 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED BIT(20)
505 #define BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD BIT(21)
506 #define BNXT_FLAG_EXT_STATS_SUPPORTED BIT(22)
507 #define BNXT_FLAG_NEW_RM BIT(23)
508 #define BNXT_FLAG_INIT_DONE BIT(24)
509 #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS BIT(25)
510 #define BNXT_FLAG_ADV_FLOW_MGMT BIT(26)
511 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
512 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
513 #define BNXT_NPAR(bp) ((bp)->port_partition_type)
514 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
515 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
516 #define BNXT_USE_CHIMP_MB 0 //For non-CFA commands, everything uses Chimp.
517 #define BNXT_USE_KONG(bp) ((bp)->flags & BNXT_FLAG_KONG_MB_EN)
518 #define BNXT_VF_IS_TRUSTED(bp) ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN)
519 #define BNXT_CHIP_THOR(bp) ((bp)->flags & BNXT_FLAG_THOR_CHIP)
520 #define BNXT_STINGRAY(bp) ((bp)->flags & BNXT_FLAG_STINGRAY)
521 #define BNXT_HAS_NQ(bp) BNXT_CHIP_THOR(bp)
522 #define BNXT_HAS_RING_GRPS(bp) (!BNXT_CHIP_THOR(bp))
525 #define BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN BIT(0)
526 pthread_mutex_t flow_lock;
528 uint32_t vnic_cap_flags;
529 #define BNXT_VNIC_CAP_COS_CLASSIFY BIT(0)
530 unsigned int rx_nr_rings;
531 unsigned int rx_cp_nr_rings;
532 unsigned int rx_num_qs_per_vnic;
533 struct bnxt_rx_queue **rx_queues;
534 const void *rx_mem_zone;
535 struct rx_port_stats *hw_rx_port_stats;
536 rte_iova_t hw_rx_port_stats_map;
537 struct rx_port_stats_ext *hw_rx_port_stats_ext;
538 rte_iova_t hw_rx_port_stats_ext_map;
539 uint16_t fw_rx_port_stats_ext_size;
541 unsigned int tx_nr_rings;
542 unsigned int tx_cp_nr_rings;
543 struct bnxt_tx_queue **tx_queues;
544 const void *tx_mem_zone;
545 struct tx_port_stats *hw_tx_port_stats;
546 rte_iova_t hw_tx_port_stats_map;
547 struct tx_port_stats_ext *hw_tx_port_stats_ext;
548 rte_iova_t hw_tx_port_stats_ext_map;
549 uint16_t fw_tx_port_stats_ext_size;
551 /* Default completion ring */
552 struct bnxt_cp_ring_info *async_cp_ring;
553 struct bnxt_cp_ring_info *rxtx_nq_ring;
554 uint32_t max_ring_grps;
555 struct bnxt_ring_grp_info *grp_info;
557 unsigned int nr_vnics;
559 #define BNXT_GET_DEFAULT_VNIC(bp) (&(bp)->vnic_info[0])
560 struct bnxt_vnic_info *vnic_info;
561 STAILQ_HEAD(, bnxt_vnic_info) free_vnic_list;
563 struct bnxt_filter_info *filter_info;
564 STAILQ_HEAD(, bnxt_filter_info) free_filter_list;
566 struct bnxt_irq *irq_tbl;
568 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
570 uint16_t hwrm_cmd_seq;
571 uint16_t kong_cmd_seq;
572 void *hwrm_cmd_resp_addr;
573 rte_iova_t hwrm_cmd_resp_dma_addr;
574 void *hwrm_short_cmd_req_addr;
575 rte_iova_t hwrm_short_cmd_req_dma_addr;
576 rte_spinlock_t hwrm_lock;
577 pthread_mutex_t def_cp_lock;
578 uint16_t max_req_len;
579 uint16_t max_resp_len;
580 uint16_t hwrm_max_ext_req_len;
582 /* default command timeout value of 50ms */
583 #define HWRM_CMD_TIMEOUT 50000
584 /* default HWRM request timeout value */
585 uint32_t hwrm_cmd_timeout;
587 struct bnxt_link_info link_info;
588 struct bnxt_cos_queue_info rx_cos_queue[BNXT_COS_QUEUE_COUNT];
589 struct bnxt_cos_queue_info tx_cos_queue[BNXT_COS_QUEUE_COUNT];
590 uint8_t tx_cosq_id[BNXT_COS_QUEUE_COUNT];
597 uint8_t dflt_mac_addr[RTE_ETHER_ADDR_LEN];
598 uint16_t max_rsscos_ctx;
599 uint16_t max_cp_rings;
600 uint16_t max_tx_rings;
601 uint16_t max_rx_rings;
602 uint16_t max_nq_rings;
604 uint16_t max_rx_em_flows;
606 uint16_t max_stat_ctx;
608 uint16_t first_vf_id;
610 #define BNXT_OUTER_TPID_MASK 0x0000ffff
611 #define BNXT_OUTER_TPID_BD_MASK 0xffff0000
612 #define BNXT_OUTER_TPID_BD_SHFT 16
613 uint32_t outer_tpid_bd;
614 struct bnxt_pf_info pf;
615 uint8_t port_partition_type;
617 uint8_t vxlan_port_cnt;
618 uint8_t geneve_port_cnt;
620 uint16_t geneve_port;
621 uint16_t vxlan_fw_dst_port_id;
622 uint16_t geneve_fw_dst_port_id;
624 uint32_t hwrm_spec_code;
626 struct bnxt_led_info leds[BNXT_MAX_LED];
628 struct bnxt_ptp_cfg *ptp_cfg;
629 uint16_t vf_resv_strategy;
630 struct bnxt_ctx_mem_info *ctx;
632 uint16_t fw_reset_min_msecs;
633 uint16_t fw_reset_max_msecs;
635 /* Struct to hold adapter error recovery related info */
636 struct bnxt_error_recovery_info *recovery_info;
639 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete);
640 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
641 int is_bnxt_in_error(struct bnxt *bp);
642 uint16_t bnxt_rss_ctxts(const struct bnxt *bp);
644 int bnxt_map_fw_health_status_regs(struct bnxt *bp);
645 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index);
646 void bnxt_schedule_fw_health_check(struct bnxt *bp);
648 bool is_bnxt_supported(struct rte_eth_dev *dev);
649 bool bnxt_stratus_device(struct bnxt *bp);
650 extern const struct rte_flow_ops bnxt_flow_ops;
651 #define bnxt_acquire_flow_lock(bp) \
652 pthread_mutex_lock(&(bp)->flow_lock)
654 #define bnxt_release_flow_lock(bp) \
655 pthread_mutex_unlock(&(bp)->flow_lock)
657 extern int bnxt_logtype_driver;
658 #define PMD_DRV_LOG_RAW(level, fmt, args...) \
659 rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \
662 #define PMD_DRV_LOG(level, fmt, args...) \
663 PMD_DRV_LOG_RAW(level, fmt, ## args)