drivers/net/bnxt/bnxt.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _BNXT_H_
   7 #define _BNXT_H_
   8
   9 #include <inttypes.h>
  10 #include <stdbool.h>
  11 #include <sys/queue.h>
  12
  13 #include <rte_pci.h>
  14 #include <rte_bus_pci.h>
  15 #include <ethdev_driver.h>
  16 #include <rte_memory.h>
  17 #include <rte_lcore.h>
  18 #include <rte_spinlock.h>
  19 #include <rte_time.h>
  20
  21 #include "bnxt_cpr.h"
  22 #include "bnxt_util.h"
  23
  24 #include "tf_core.h"
  25 #include "bnxt_ulp.h"
  26 #include "bnxt_tf_common.h"
  27
  28 /* Vendor ID */
  29 #define PCI_VENDOR_ID_BROADCOM          0x14E4
  30
  31 /* Device IDs */
  32 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  33 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  34 #define BROADCOM_DEV_ID_STRATUS_NIC     0x1614
  35 #define BROADCOM_DEV_ID_57414_VF        0x16c1
  36 #define BROADCOM_DEV_ID_57304_VF        0x16cb
  37 #define BROADCOM_DEV_ID_57417_MF        0x16cc
  38 #define BROADCOM_DEV_ID_NS2             0x16cd
  39 #define BROADCOM_DEV_ID_57406_VF        0x16d3
  40 #define BROADCOM_DEV_ID_57412           0x16d6
  41 #define BROADCOM_DEV_ID_57414           0x16d7
  42 #define BROADCOM_DEV_ID_57416_RJ45      0x16d8
  43 #define BROADCOM_DEV_ID_57417_RJ45      0x16d9
  44 #define BROADCOM_DEV_ID_5741X_VF        0x16dc
  45 #define BROADCOM_DEV_ID_57412_MF        0x16de
  46 #define BROADCOM_DEV_ID_57317_RJ45      0x16e0
  47 #define BROADCOM_DEV_ID_5731X_VF        0x16e1
  48 #define BROADCOM_DEV_ID_57417_SFP       0x16e2
  49 #define BROADCOM_DEV_ID_57416_SFP       0x16e3
  50 #define BROADCOM_DEV_ID_57317_SFP       0x16e4
  51 #define BROADCOM_DEV_ID_57407_MF        0x16ea
  52 #define BROADCOM_DEV_ID_57414_MF        0x16ec
  53 #define BROADCOM_DEV_ID_57416_MF        0x16ee
  54 #define BROADCOM_DEV_ID_57508           0x1750
  55 #define BROADCOM_DEV_ID_57504           0x1751
  56 #define BROADCOM_DEV_ID_57502           0x1752
  57 #define BROADCOM_DEV_ID_57508_MF1       0x1800
  58 #define BROADCOM_DEV_ID_57504_MF1       0x1801
  59 #define BROADCOM_DEV_ID_57502_MF1       0x1802
  60 #define BROADCOM_DEV_ID_57508_MF2       0x1803
  61 #define BROADCOM_DEV_ID_57504_MF2       0x1804
  62 #define BROADCOM_DEV_ID_57502_MF2       0x1805
  63 #define BROADCOM_DEV_ID_57500_VF1       0x1806
  64 #define BROADCOM_DEV_ID_57500_VF2       0x1807
  65 #define BROADCOM_DEV_ID_58802           0xd802
  66 #define BROADCOM_DEV_ID_58804           0xd804
  67 #define BROADCOM_DEV_ID_58808           0x16f0
  68 #define BROADCOM_DEV_ID_58802_VF        0xd800
  69 #define BROADCOM_DEV_ID_58812           0xd812
  70 #define BROADCOM_DEV_ID_58814           0xd814
  71 #define BROADCOM_DEV_ID_58818           0xd818
  72 #define BROADCOM_DEV_ID_58818_VF        0xd82e
  73
  74 #define BROADCOM_DEV_957508_N2100       0x5208
  75 #define BROADCOM_DEV_957414_N225        0x4145
  76
  77 #define BNXT_MAX_MTU            9574
  78 #define BNXT_NUM_VLANS          2
  79 #define BNXT_MAX_PKT_LEN        (BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +\
  80                                  RTE_ETHER_CRC_LEN +\
  81                                  (BNXT_NUM_VLANS * RTE_VLAN_HLEN))
  82 /* FW adds extra 4 bytes for FCS */
  83 #define BNXT_VNIC_MRU(mtu)\
  84         ((mtu) + RTE_ETHER_HDR_LEN + RTE_VLAN_HLEN * BNXT_NUM_VLANS)
  85 #define BNXT_VF_RSV_NUM_RSS_CTX 1
  86 #define BNXT_VF_RSV_NUM_L2_CTX  4
  87 /* TODO: For now, do not support VMDq/RFS on VFs. */
  88 #define BNXT_VF_RSV_NUM_VNIC    1
  89 #define BNXT_MAX_LED            4
  90 #define BNXT_MIN_RING_DESC      16
  91 #define BNXT_MAX_TX_RING_DESC   4096
  92 #define BNXT_MAX_RX_RING_DESC   8192
  93 #define BNXT_DB_SIZE            0x80
  94
  95 #define TPA_MAX_AGGS            64
  96 #define TPA_MAX_AGGS_TH         1024
  97
  98 #define TPA_MAX_NUM_SEGS        32
  99 #define TPA_MAX_SEGS_TH         8 /* 32 segments in 4-segment units */
 100 #define TPA_MAX_SEGS            5 /* 32 segments in log2 units */
 101
 102 #define BNXT_TPA_MAX_AGGS(bp) \
 103         (BNXT_CHIP_P5(bp) ? TPA_MAX_AGGS_TH : \
 104                              TPA_MAX_AGGS)
 105
 106 #define BNXT_TPA_MAX_SEGS(bp) \
 107         (BNXT_CHIP_P5(bp) ? TPA_MAX_SEGS_TH : \
 108                               TPA_MAX_SEGS)
 109
 110 /*
 111  * Define the number of async completion rings to be used. Set to zero for
 112  * configurations in which the maximum number of packet completion rings
 113  * for packet completions is desired or when async completion handling
 114  * cannot be interrupt-driven.
 115  */
 116 #ifdef RTE_EXEC_ENV_FREEBSD
 117 /* In FreeBSD OS, nic_uio driver does not support interrupts */
 118 #define BNXT_NUM_ASYNC_CPR(bp) 0U
 119 #else
 120 #define BNXT_NUM_ASYNC_CPR(bp) 1U
 121 #endif
 122
 123 #define BNXT_MISC_VEC_ID               RTE_INTR_VEC_ZERO_OFFSET
 124 #define BNXT_RX_VEC_START              RTE_INTR_VEC_RXTX_OFFSET
 125
 126 /* Chimp Communication Channel */
 127 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET          0x0
 128 #define GRCPF_REG_CHIMP_COMM_TRIGGER            0x100
 129 /* Kong Communication Channel */
 130 #define GRCPF_REG_KONG_CHANNEL_OFFSET           0xA00
 131 #define GRCPF_REG_KONG_COMM_TRIGGER             0xB00
 132
 133 #define BNXT_INT_LAT_TMR_MIN                    75
 134 #define BNXT_INT_LAT_TMR_MAX                    150
 135 #define BNXT_NUM_CMPL_AGGR_INT                  36
 136 #define BNXT_CMPL_AGGR_DMA_TMR                  37
 137 #define BNXT_NUM_CMPL_DMA_AGGR                  36
 138 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT       50
 139 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT       12
 140
 141 #define BNXT_DEFAULT_VNIC_STATE_MASK                    \
 142         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK
 143 #define BNXT_DEFAULT_VNIC_STATE_SFT                     \
 144         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT
 145 #define BNXT_DEFAULT_VNIC_ALLOC                         \
 146         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC
 147 #define BNXT_DEFAULT_VNIC_FREE                          \
 148         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
 149 #define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_MASK             \
 150         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK
 151 #define BNXT_DEFAULT_VNIC_CHANGE_PF_ID_SFT              \
 152         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT
 153 #define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_MASK             \
 154         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK
 155 #define BNXT_DEFAULT_VNIC_CHANGE_VF_ID_SFT              \
 156         HWRM_ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT
 157
 158 #define BNXT_EVENT_ERROR_REPORT_TYPE(data1)                             \
 159         (((data1) &                                                     \
 160           HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK)  >>\
 161          HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT)
 162
 163 #define BNXT_HWRM_CMD_TO_FORWARD(cmd)   \
 164                 (bp->pf->vf_req_fwd[(cmd) / 32] |= (1 << ((cmd) % 32)))
 165
 166 struct bnxt_led_info {
 167         uint8_t      num_leds;
 168         uint8_t      led_id;
 169         uint8_t      led_type;
 170         uint8_t      led_group_id;
 171         uint8_t      unused;
 172         uint16_t  led_state_caps;
 173 #define BNXT_LED_ALT_BLINK_CAP(x)       ((x) &  \
 174         rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
 175
 176         uint16_t  led_color_caps;
 177 };
 178
 179 struct bnxt_led_cfg {
 180         uint8_t led_id;
 181         uint8_t led_state;
 182         uint8_t led_color;
 183         uint8_t unused;
 184         uint16_t led_blink_on;
 185         uint16_t led_blink_off;
 186         uint8_t led_group_id;
 187         uint8_t rsvd;
 188 };
 189
 190 #define BNXT_LED_DFLT_ENA                               \
 191         (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID |             \
 192          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE |          \
 193          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON |       \
 194          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF |      \
 195          HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
 196
 197 #define BNXT_LED_DFLT_ENA_SHIFT         6
 198
 199 #define BNXT_LED_DFLT_ENABLES(x)                        \
 200         rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
 201
 202 struct bnxt_vlan_table_entry {
 203         uint16_t                tpid;
 204         uint16_t                vid;
 205 } __rte_packed;
 206
 207 struct bnxt_vlan_antispoof_table_entry {
 208         uint16_t                tpid;
 209         uint16_t                vid;
 210         uint16_t                mask;
 211 } __rte_packed;
 212
 213 struct bnxt_child_vf_info {
 214         void                    *req_buf;
 215         struct bnxt_vlan_table_entry    *vlan_table;
 216         struct bnxt_vlan_antispoof_table_entry  *vlan_as_table;
 217         STAILQ_HEAD(, bnxt_filter_info) filter;
 218         uint32_t                func_cfg_flags;
 219         uint32_t                l2_rx_mask;
 220         uint16_t                fid;
 221         uint16_t                max_tx_rate;
 222         uint16_t                dflt_vlan;
 223         uint16_t                vlan_count;
 224         uint8_t                 mac_spoof_en;
 225         uint8_t                 vlan_spoof_en;
 226         bool                    random_mac;
 227         bool                    persist_stats;
 228 };
 229
 230 struct bnxt_parent_info {
 231 #define BNXT_PF_FID_INVALID     0xFFFF
 232         uint16_t                fid;
 233         uint16_t                vnic;
 234         uint16_t                port_id;
 235         uint8_t                 mac_addr[RTE_ETHER_ADDR_LEN];
 236 };
 237
 238 struct bnxt_pf_info {
 239 #define BNXT_FIRST_PF_FID       1
 240 #define BNXT_MAX_VFS(bp)        ((bp)->pf->max_vfs)
 241 #define BNXT_MAX_VF_REPS_WH     64
 242 #define BNXT_MAX_VF_REPS_TH     256
 243 #define BNXT_MAX_VF_REPS(bp) \
 244                                 (BNXT_CHIP_P5(bp) ? BNXT_MAX_VF_REPS_TH : \
 245                                 BNXT_MAX_VF_REPS_WH)
 246 #define BNXT_TOTAL_VFS(bp)      ((bp)->pf->total_vfs)
 247 #define BNXT_FIRST_VF_FID       128
 248 #define BNXT_PF_RINGS_USED(bp)  bnxt_get_num_queues(bp)
 249 #define BNXT_PF_RINGS_AVAIL(bp) ((bp)->pf->max_cp_rings - \
 250                                  BNXT_PF_RINGS_USED(bp))
 251         uint16_t                port_id;
 252         uint16_t                first_vf_id;
 253         uint16_t                active_vfs;
 254         uint16_t                max_vfs;
 255         uint16_t                total_vfs; /* Total VFs possible.
 256                                             * Not necessarily enabled.
 257                                             */
 258         uint32_t                func_cfg_flags;
 259         void                    *vf_req_buf;
 260         rte_iova_t              vf_req_buf_dma_addr;
 261         uint32_t                vf_req_fwd[8];
 262         uint16_t                total_vnics;
 263         struct bnxt_child_vf_info       *vf_info;
 264 #define BNXT_EVB_MODE_NONE      0
 265 #define BNXT_EVB_MODE_VEB       1
 266 #define BNXT_EVB_MODE_VEPA      2
 267         uint8_t                 evb_mode;
 268 };
 269
 270 /* Max wait time for link up is 10s and link down is 500ms */
 271 #define BNXT_MAX_LINK_WAIT_CNT  200
 272 #define BNXT_MIN_LINK_WAIT_CNT  10
 273 #define BNXT_LINK_WAIT_INTERVAL 50
 274 struct bnxt_link_info {
 275         uint32_t                phy_flags;
 276         uint8_t                 mac_type;
 277         uint8_t                 phy_link_status;
 278         uint8_t                 loop_back;
 279         uint8_t                 link_up;
 280         uint8_t                 duplex;
 281         uint8_t                 pause;
 282         uint8_t                 force_pause;
 283         uint8_t                 auto_pause;
 284         uint8_t                 auto_mode;
 285 #define PHY_VER_LEN             3
 286         uint8_t                 phy_ver[PHY_VER_LEN];
 287         uint16_t                link_speed;
 288         uint16_t                support_speeds;
 289         uint16_t                auto_link_speed;
 290         uint16_t                force_link_speed;
 291         uint16_t                auto_link_speed_mask;
 292         uint32_t                preemphasis;
 293         uint8_t                 phy_type;
 294         uint8_t                 media_type;
 295         uint16_t                support_auto_speeds;
 296         uint8_t                 link_signal_mode;
 297         uint16_t                force_pam4_link_speed;
 298         uint16_t                support_pam4_speeds;
 299         uint16_t                auto_pam4_link_speed_mask;
 300         uint16_t                support_pam4_auto_speeds;
 301         uint8_t                 req_signal_mode;
 302         uint8_t                 module_status;
 303 };
 304
 305 #define BNXT_COS_QUEUE_COUNT    8
 306 struct bnxt_cos_queue_info {
 307         uint8_t id;
 308         uint8_t profile;
 309 };
 310
 311 struct rte_flow {
 312         STAILQ_ENTRY(rte_flow) next;
 313         struct bnxt_filter_info *filter;
 314         struct bnxt_vnic_info   *vnic;
 315 };
 316
 317 #define BNXT_PTP_RX_PND_CNT             10
 318 #define BNXT_PTP_FLAGS_PATH_TX          0x0
 319 #define BNXT_PTP_FLAGS_PATH_RX          0x1
 320 #define BNXT_PTP_FLAGS_CURRENT_TIME     0x2
 321 #define BNXT_PTP_CURRENT_TIME_MASK      0xFFFF00000000ULL
 322
 323 struct bnxt_ptp_cfg {
 324 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT  0x400
 325 #define BNXT_GRCPF_REG_SYNC_TIME        0x480
 326 #define BNXT_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 327         struct rte_timecounter      tc;
 328         struct rte_timecounter      tx_tstamp_tc;
 329         struct rte_timecounter      rx_tstamp_tc;
 330         struct bnxt             *bp;
 331 #define BNXT_MAX_TX_TS  1
 332         uint16_t                        rxctl;
 333 #define BNXT_PTP_MSG_SYNC                       BIT(0)
 334 #define BNXT_PTP_MSG_DELAY_REQ                  BIT(1)
 335 #define BNXT_PTP_MSG_PDELAY_REQ                 BIT(2)
 336 #define BNXT_PTP_MSG_PDELAY_RESP                BIT(3)
 337 #define BNXT_PTP_MSG_FOLLOW_UP                  BIT(8)
 338 #define BNXT_PTP_MSG_DELAY_RESP                 BIT(9)
 339 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP      BIT(10)
 340 #define BNXT_PTP_MSG_ANNOUNCE                   BIT(11)
 341 #define BNXT_PTP_MSG_SIGNALING                  BIT(12)
 342 #define BNXT_PTP_MSG_MANAGEMENT                 BIT(13)
 343 #define BNXT_PTP_MSG_EVENTS             (BNXT_PTP_MSG_SYNC |            \
 344                                          BNXT_PTP_MSG_DELAY_REQ |       \
 345                                          BNXT_PTP_MSG_PDELAY_REQ |      \
 346                                          BNXT_PTP_MSG_PDELAY_RESP)
 347         uint8_t                 tx_tstamp_en:1;
 348         int                     rx_filter;
 349
 350 #define BNXT_PTP_RX_TS_L        0
 351 #define BNXT_PTP_RX_TS_H        1
 352 #define BNXT_PTP_RX_SEQ         2
 353 #define BNXT_PTP_RX_FIFO        3
 354 #define BNXT_PTP_RX_FIFO_PENDING 0x1
 355 #define BNXT_PTP_RX_FIFO_ADV    4
 356 #define BNXT_PTP_RX_REGS        5
 357
 358 #define BNXT_PTP_TX_TS_L        0
 359 #define BNXT_PTP_TX_TS_H        1
 360 #define BNXT_PTP_TX_SEQ         2
 361 #define BNXT_PTP_TX_FIFO        3
 362 #define BNXT_PTP_TX_FIFO_EMPTY   0x2
 363 #define BNXT_PTP_TX_REGS        4
 364         uint32_t                        rx_regs[BNXT_PTP_RX_REGS];
 365         uint32_t                        rx_mapped_regs[BNXT_PTP_RX_REGS];
 366         uint32_t                        tx_regs[BNXT_PTP_TX_REGS];
 367         uint32_t                        tx_mapped_regs[BNXT_PTP_TX_REGS];
 368
 369         /* On Thor, the Rx timestamp is present in the Rx completion record */
 370         uint64_t                        rx_timestamp;
 371         uint64_t                        current_time;
 372 };
 373
 374 struct bnxt_coal {
 375         uint16_t                        num_cmpl_aggr_int;
 376         uint16_t                        num_cmpl_dma_aggr;
 377         uint16_t                        num_cmpl_dma_aggr_during_int;
 378         uint16_t                        int_lat_tmr_max;
 379         uint16_t                        int_lat_tmr_min;
 380         uint16_t                        cmpl_aggr_dma_tmr;
 381         uint16_t                        cmpl_aggr_dma_tmr_during_int;
 382 };
 383
 384 /* 64-bit doorbell */
 385 #define DBR_EPOCH_MASK                          0x01000000UL
 386 #define DBR_EPOCH_SFT                           24
 387 #define DBR_XID_SFT                             32
 388 #define DBR_PATH_L2                             (0x1ULL << 56)
 389 #define DBR_VALID                               (0x1ULL << 58)
 390 #define DBR_TYPE_SQ                             (0x0ULL << 60)
 391 #define DBR_TYPE_SRQ                            (0x2ULL << 60)
 392 #define DBR_TYPE_CQ                             (0x4ULL << 60)
 393 #define DBR_TYPE_NQ                             (0xaULL << 60)
 394 #define DBR_TYPE_NQ_ARM                         (0xbULL << 60)
 395
 396 #define DB_PF_OFFSET                    0x10000
 397 #define DB_VF_OFFSET                    0x4000
 398
 399 #define BNXT_RSS_TBL_SIZE_P5            512U
 400 #define BNXT_RSS_ENTRIES_PER_CTX_P5     64
 401 #define BNXT_MAX_RSS_CTXTS_P5 \
 402         (BNXT_RSS_TBL_SIZE_P5 / BNXT_RSS_ENTRIES_PER_CTX_P5)
 403
 404 #define BNXT_MAX_QUEUE                  8
 405 #define BNXT_MAX_TQM_SP_RINGS           1
 406 #define BNXT_MAX_TQM_FP_LEGACY_RINGS    8
 407 #define BNXT_MAX_TQM_FP_RINGS           9
 408 #define BNXT_MAX_TQM_LEGACY_RINGS       \
 409         (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_LEGACY_RINGS)
 410 #define BNXT_MAX_TQM_RINGS              \
 411         (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS)
 412 #define BNXT_BACKING_STORE_CFG_LEGACY_LEN       256
 413 #define BNXT_BACKING_STORE_CFG_LEN      \
 414         sizeof(struct hwrm_func_backing_store_cfg_input)
 415 #define BNXT_PAGE_SHFT 12
 416 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT)
 417 #define MAX_CTX_PAGES  (BNXT_PAGE_SIZE / 8)
 418
 419 #define PTU_PTE_VALID             0x1UL
 420 #define PTU_PTE_LAST              0x2UL
 421 #define PTU_PTE_NEXT_TO_LAST      0x4UL
 422
 423 struct bnxt_ring_mem_info {
 424         int                             nr_pages;
 425         int                             page_size;
 426         uint32_t                        flags;
 427 #define BNXT_RMEM_VALID_PTE_FLAG        1
 428 #define BNXT_RMEM_RING_PTE_FLAG         2
 429
 430         void                            **pg_arr;
 431         rte_iova_t                      *dma_arr;
 432         const struct rte_memzone        *mz;
 433
 434         uint64_t                        *pg_tbl;
 435         rte_iova_t                      pg_tbl_map;
 436         const struct rte_memzone        *pg_tbl_mz;
 437
 438         int                             vmem_size;
 439         void                            **vmem;
 440 };
 441
 442 struct bnxt_ctx_pg_info {
 443         uint32_t        entries;
 444         void            *ctx_pg_arr[MAX_CTX_PAGES];
 445         rte_iova_t      ctx_dma_arr[MAX_CTX_PAGES];
 446         struct bnxt_ring_mem_info ring_mem;
 447 };
 448
 449 struct bnxt_ctx_mem_info {
 450         uint32_t        qp_max_entries;
 451         uint16_t        qp_min_qp1_entries;
 452         uint16_t        qp_max_l2_entries;
 453         uint16_t        qp_entry_size;
 454         uint16_t        srq_max_l2_entries;
 455         uint32_t        srq_max_entries;
 456         uint16_t        srq_entry_size;
 457         uint16_t        cq_max_l2_entries;
 458         uint32_t        cq_max_entries;
 459         uint16_t        cq_entry_size;
 460         uint16_t        vnic_max_vnic_entries;
 461         uint16_t        vnic_max_ring_table_entries;
 462         uint16_t        vnic_entry_size;
 463         uint32_t        stat_max_entries;
 464         uint16_t        stat_entry_size;
 465         uint16_t        tqm_entry_size;
 466         uint32_t        tqm_min_entries_per_ring;
 467         uint32_t        tqm_max_entries_per_ring;
 468         uint32_t        mrav_max_entries;
 469         uint16_t        mrav_entry_size;
 470         uint16_t        tim_entry_size;
 471         uint32_t        tim_max_entries;
 472         uint8_t         tqm_entries_multiple;
 473         uint8_t         tqm_fp_rings_count;
 474
 475         uint32_t        flags;
 476 #define BNXT_CTX_FLAG_INITED    0x01
 477
 478         struct bnxt_ctx_pg_info qp_mem;
 479         struct bnxt_ctx_pg_info srq_mem;
 480         struct bnxt_ctx_pg_info cq_mem;
 481         struct bnxt_ctx_pg_info vnic_mem;
 482         struct bnxt_ctx_pg_info stat_mem;
 483         struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TQM_RINGS];
 484 };
 485
 486 struct bnxt_ctx_mem_buf_info {
 487         void            *va;
 488         rte_iova_t      dma;
 489         uint16_t        ctx_id;
 490         size_t          size;
 491 };
 492
 493 /* Maximum Firmware Reset bail out value in milliseconds */
 494 #define BNXT_MAX_FW_RESET_TIMEOUT       6000
 495 /* Minimum time required for the firmware readiness in milliseconds */
 496 #define BNXT_MIN_FW_READY_TIMEOUT       2000
 497 /* Frequency for the firmware readiness check in milliseconds */
 498 #define BNXT_FW_READY_WAIT_INTERVAL     100
 499
 500 #define US_PER_MS                       1000
 501 #define NS_PER_US                       1000
 502
 503 struct bnxt_error_recovery_info {
 504         /* All units in milliseconds */
 505         uint32_t        driver_polling_freq;
 506         uint32_t        primary_func_wait_period;
 507         uint32_t        normal_func_wait_period;
 508         uint32_t        primary_func_wait_period_after_reset;
 509         uint32_t        max_bailout_time_after_reset;
 510 #define BNXT_FW_STATUS_REG              0
 511 #define BNXT_FW_HEARTBEAT_CNT_REG       1
 512 #define BNXT_FW_RECOVERY_CNT_REG        2
 513 #define BNXT_FW_RESET_INPROG_REG        3
 514 #define BNXT_FW_STATUS_REG_CNT          4
 515         uint32_t        status_regs[BNXT_FW_STATUS_REG_CNT];
 516         uint32_t        mapped_status_regs[BNXT_FW_STATUS_REG_CNT];
 517         uint32_t        reset_inprogress_reg_mask;
 518 #define BNXT_NUM_RESET_REG      16
 519         uint8_t         reg_array_cnt;
 520         uint32_t        reset_reg[BNXT_NUM_RESET_REG];
 521         uint32_t        reset_reg_val[BNXT_NUM_RESET_REG];
 522         uint8_t         delay_after_reset[BNXT_NUM_RESET_REG];
 523 #define BNXT_FLAG_ERROR_RECOVERY_HOST   BIT(0)
 524 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1)
 525 #define BNXT_FLAG_PRIMARY_FUNC          BIT(2)
 526 #define BNXT_FLAG_RECOVERY_ENABLED      BIT(3)
 527         uint32_t        flags;
 528
 529         uint32_t        last_heart_beat;
 530         uint32_t        last_reset_counter;
 531 };
 532
 533 /* Frequency for the FUNC_DRV_IF_CHANGE retry in milliseconds */
 534 #define BNXT_IF_CHANGE_RETRY_INTERVAL   50
 535 /* Maximum retry count for FUNC_DRV_IF_CHANGE */
 536 #define BNXT_IF_CHANGE_RETRY_COUNT      40
 537
 538 struct bnxt_mark_info {
 539         uint32_t        mark_id;
 540         bool            valid;
 541 };
 542
 543 struct bnxt_rep_info {
 544         struct rte_eth_dev      *vfr_eth_dev;
 545         pthread_mutex_t         vfr_lock;
 546         pthread_mutex_t         vfr_start_lock;
 547         bool                    conduit_valid;
 548 };
 549
 550 /* address space location of register */
 551 #define BNXT_FW_STATUS_REG_TYPE_MASK    3
 552 /* register is located in PCIe config space */
 553 #define BNXT_FW_STATUS_REG_TYPE_CFG     0
 554 /* register is located in GRC address space */
 555 #define BNXT_FW_STATUS_REG_TYPE_GRC     1
 556 /* register is located in BAR0  */
 557 #define BNXT_FW_STATUS_REG_TYPE_BAR0    2
 558 /* register is located in BAR1  */
 559 #define BNXT_FW_STATUS_REG_TYPE_BAR1    3
 560
 561 #define BNXT_FW_STATUS_REG_TYPE(reg)    ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK)
 562 #define BNXT_FW_STATUS_REG_OFF(reg)     ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK)
 563
 564 #define BNXT_GRCP_WINDOW_2_BASE         0x2000
 565 #define BNXT_GRCP_WINDOW_3_BASE         0x3000
 566
 567 #define BNXT_GRCP_BASE_MASK             0xfffff000
 568 #define BNXT_GRCP_OFFSET_MASK           0x00000ffc
 569
 570 #define BNXT_FW_STATUS_HEALTHY          0x8000
 571 #define BNXT_FW_STATUS_SHUTDOWN         0x100000
 572
 573 #define BNXT_ETH_RSS_SUPPORT (  \
 574         RTE_ETH_RSS_IPV4 |              \
 575         RTE_ETH_RSS_NONFRAG_IPV4_TCP |  \
 576         RTE_ETH_RSS_NONFRAG_IPV4_UDP |  \
 577         RTE_ETH_RSS_IPV6 |              \
 578         RTE_ETH_RSS_NONFRAG_IPV6_TCP |  \
 579         RTE_ETH_RSS_NONFRAG_IPV6_UDP |  \
 580         RTE_ETH_RSS_LEVEL_MASK)
 581
 582 #define BNXT_HWRM_SHORT_REQ_LEN         sizeof(struct hwrm_short_input)
 583
 584 struct bnxt_flow_stat_info {
 585         uint16_t                max_fc;
 586         uint16_t                flow_count;
 587         struct bnxt_ctx_mem_buf_info rx_fc_in_tbl;
 588         struct bnxt_ctx_mem_buf_info rx_fc_out_tbl;
 589         struct bnxt_ctx_mem_buf_info tx_fc_in_tbl;
 590         struct bnxt_ctx_mem_buf_info tx_fc_out_tbl;
 591 };
 592
 593 struct bnxt_ring_stats {
 594         /* Number of transmitted unicast packets */
 595         uint64_t        tx_ucast_pkts;
 596         /* Number of transmitted multicast packets */
 597         uint64_t        tx_mcast_pkts;
 598         /* Number of transmitted broadcast packets */
 599         uint64_t        tx_bcast_pkts;
 600         /* Number of packets discarded in transmit path */
 601         uint64_t        tx_discard_pkts;
 602         /* Number of packets in transmit path with error */
 603         uint64_t        tx_error_pkts;
 604         /* Number of transmitted bytes for unicast traffic */
 605         uint64_t        tx_ucast_bytes;
 606         /* Number of transmitted bytes for multicast traffic */
 607         uint64_t        tx_mcast_bytes;
 608         /* Number of transmitted bytes for broadcast traffic */
 609         uint64_t        tx_bcast_bytes;
 610         /* Number of received unicast packets */
 611         uint64_t        rx_ucast_pkts;
 612         /* Number of received multicast packets */
 613         uint64_t        rx_mcast_pkts;
 614         /* Number of received broadcast packets */
 615         uint64_t        rx_bcast_pkts;
 616         /* Number of packets discarded in receive path */
 617         uint64_t        rx_discard_pkts;
 618         /* Number of packets in receive path with errors */
 619         uint64_t        rx_error_pkts;
 620         /* Number of received bytes for unicast traffic */
 621         uint64_t        rx_ucast_bytes;
 622         /* Number of received bytes for multicast traffic */
 623         uint64_t        rx_mcast_bytes;
 624         /* Number of received bytes for broadcast traffic */
 625         uint64_t        rx_bcast_bytes;
 626         /* Number of aggregated unicast packets */
 627         uint64_t        rx_agg_pkts;
 628         /* Number of aggregated unicast bytes */
 629         uint64_t        rx_agg_bytes;
 630         /* Number of aggregation events */
 631         uint64_t        rx_agg_events;
 632         /* Number of aborted aggregations */
 633         uint64_t        rx_agg_aborts;
 634 };
 635
 636 struct bnxt {
 637         void                            *bar0;
 638
 639         struct rte_eth_dev              *eth_dev;
 640         struct rte_pci_device           *pdev;
 641         void                            *doorbell_base;
 642         int                             legacy_db_size;
 643
 644         uint32_t                flags;
 645 #define BNXT_FLAG_REGISTERED            BIT(0)
 646 #define BNXT_FLAG_VF                    BIT(1)
 647 #define BNXT_FLAG_PORT_STATS            BIT(2)
 648 #define BNXT_FLAG_JUMBO                 BIT(3)
 649 #define BNXT_FLAG_SHORT_CMD             BIT(4)
 650 #define BNXT_FLAG_PTP_SUPPORTED         BIT(6)
 651 #define BNXT_FLAG_MULTI_HOST            BIT(7)
 652 #define BNXT_FLAG_EXT_RX_PORT_STATS     BIT(8)
 653 #define BNXT_FLAG_EXT_TX_PORT_STATS     BIT(9)
 654 #define BNXT_FLAG_KONG_MB_EN            BIT(10)
 655 #define BNXT_FLAG_TRUSTED_VF_EN         BIT(11)
 656 #define BNXT_FLAG_DFLT_VNIC_SET         BIT(12)
 657 #define BNXT_FLAG_CHIP_P5               BIT(13)
 658 #define BNXT_FLAG_STINGRAY              BIT(14)
 659 #define BNXT_FLAG_FW_RESET              BIT(15)
 660 #define BNXT_FLAG_FATAL_ERROR           BIT(16)
 661 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE   BIT(17)
 662 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED     BIT(18)
 663 #define BNXT_FLAG_EXT_STATS_SUPPORTED           BIT(19)
 664 #define BNXT_FLAG_NEW_RM                        BIT(20)
 665 #define BNXT_FLAG_NPAR_PF                       BIT(21)
 666 #define BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS         BIT(22)
 667 #define BNXT_FLAG_FC_THREAD                     BIT(23)
 668 #define BNXT_FLAG_RX_VECTOR_PKT_MODE            BIT(24)
 669 #define BNXT_FLAG_FLOW_XSTATS_EN                BIT(25)
 670 #define BNXT_FLAG_DFLT_MAC_SET                  BIT(26)
 671 #define BNXT_FLAG_GFID_ENABLE                   BIT(27)
 672 #define BNXT_PF(bp)             (!((bp)->flags & BNXT_FLAG_VF))
 673 #define BNXT_VF(bp)             ((bp)->flags & BNXT_FLAG_VF)
 674 #define BNXT_NPAR(bp)           ((bp)->flags & BNXT_FLAG_NPAR_PF)
 675 #define BNXT_MH(bp)             ((bp)->flags & BNXT_FLAG_MULTI_HOST)
 676 #define BNXT_SINGLE_PF(bp)      (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
 677 #define BNXT_USE_CHIMP_MB       0 //For non-CFA commands, everything uses Chimp.
 678 #define BNXT_USE_KONG(bp)       ((bp)->flags & BNXT_FLAG_KONG_MB_EN)
 679 #define BNXT_VF_IS_TRUSTED(bp)  ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN)
 680 #define BNXT_CHIP_P5(bp)        ((bp)->flags & BNXT_FLAG_CHIP_P5)
 681 #define BNXT_STINGRAY(bp)       ((bp)->flags & BNXT_FLAG_STINGRAY)
 682 #define BNXT_HAS_NQ(bp)         BNXT_CHIP_P5(bp)
 683 #define BNXT_HAS_RING_GRPS(bp)  (!BNXT_CHIP_P5(bp))
 684 #define BNXT_FLOW_XSTATS_EN(bp) ((bp)->flags & BNXT_FLAG_FLOW_XSTATS_EN)
 685 #define BNXT_HAS_DFLT_MAC_SET(bp)      ((bp)->flags & BNXT_FLAG_DFLT_MAC_SET)
 686 #define BNXT_GFID_ENABLED(bp)   ((bp)->flags & BNXT_FLAG_GFID_ENABLE)
 687
 688         uint32_t                        flags2;
 689 #define BNXT_FLAGS2_PTP_TIMESYNC_ENABLED        BIT(0)
 690 #define BNXT_FLAGS2_PTP_ALARM_SCHEDULED         BIT(1)
 691 #define BNXT_P5_PTP_TIMESYNC_ENABLED(bp)        \
 692         ((bp)->flags2 & BNXT_FLAGS2_PTP_TIMESYNC_ENABLED)
 693
 694         uint16_t                chip_num;
 695 #define CHIP_NUM_58818          0xd818
 696 #define BNXT_CHIP_SR2(bp)       ((bp)->chip_num == CHIP_NUM_58818)
 697 #define BNXT_FLAGS2_MULTIROOT_EN                BIT(4)
 698 #define BNXT_MULTIROOT_EN(bp)                   \
 699         ((bp)->flags2 & BNXT_FLAGS2_MULTIROOT_EN)
 700
 701         uint32_t                fw_cap;
 702 #define BNXT_FW_CAP_HOT_RESET           BIT(0)
 703 #define BNXT_FW_CAP_IF_CHANGE           BIT(1)
 704 #define BNXT_FW_CAP_ERROR_RECOVERY      BIT(2)
 705 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD  BIT(3)
 706 #define BNXT_FW_CAP_HCOMM_FW_STATUS     BIT(4)
 707 #define BNXT_FW_CAP_ADV_FLOW_MGMT       BIT(5)
 708 #define BNXT_FW_CAP_ADV_FLOW_COUNTERS   BIT(6)
 709 #define BNXT_FW_CAP_LINK_ADMIN          BIT(7)
 710 #define BNXT_FW_CAP_TRUFLOW_EN          BIT(8)
 711 #define BNXT_FW_CAP_VLAN_TX_INSERT      BIT(9)
 712 #define BNXT_TRUFLOW_EN(bp)     ((bp)->fw_cap & BNXT_FW_CAP_TRUFLOW_EN)
 713
 714         pthread_mutex_t         flow_lock;
 715
 716         uint32_t                vnic_cap_flags;
 717 #define BNXT_VNIC_CAP_COS_CLASSIFY      BIT(0)
 718 #define BNXT_VNIC_CAP_OUTER_RSS         BIT(1)
 719 #define BNXT_VNIC_CAP_RX_CMPL_V2        BIT(2)
 720 #define BNXT_VNIC_CAP_VLAN_RX_STRIP     BIT(3)
 721 #define BNXT_RX_VLAN_STRIP_EN(bp)       ((bp)->vnic_cap_flags & BNXT_VNIC_CAP_VLAN_RX_STRIP)
 722         unsigned int            rx_nr_rings;
 723         unsigned int            rx_cp_nr_rings;
 724         unsigned int            rx_num_qs_per_vnic;
 725         struct bnxt_rx_queue **rx_queues;
 726         const void              *rx_mem_zone;
 727         struct rx_port_stats    *hw_rx_port_stats;
 728         rte_iova_t              hw_rx_port_stats_map;
 729         struct rx_port_stats_ext    *hw_rx_port_stats_ext;
 730         rte_iova_t              hw_rx_port_stats_ext_map;
 731         uint16_t                fw_rx_port_stats_ext_size;
 732
 733         unsigned int            tx_nr_rings;
 734         unsigned int            tx_cp_nr_rings;
 735         struct bnxt_tx_queue **tx_queues;
 736         const void              *tx_mem_zone;
 737         struct tx_port_stats    *hw_tx_port_stats;
 738         rte_iova_t              hw_tx_port_stats_map;
 739         struct tx_port_stats_ext    *hw_tx_port_stats_ext;
 740         rte_iova_t              hw_tx_port_stats_ext_map;
 741         uint16_t                fw_tx_port_stats_ext_size;
 742
 743         /* Default completion ring */
 744         struct bnxt_cp_ring_info        *async_cp_ring;
 745         struct bnxt_cp_ring_info        *rxtx_nq_ring;
 746         uint32_t                max_ring_grps;
 747         struct bnxt_ring_grp_info       *grp_info;
 748
 749         uint16_t                        nr_vnics;
 750
 751 #define BNXT_GET_DEFAULT_VNIC(bp)       (&(bp)->vnic_info[0])
 752         struct bnxt_vnic_info   *vnic_info;
 753         STAILQ_HEAD(, bnxt_vnic_info)   free_vnic_list;
 754
 755         struct bnxt_filter_info *filter_info;
 756         STAILQ_HEAD(, bnxt_filter_info) free_filter_list;
 757
 758         struct bnxt_irq         *irq_tbl;
 759
 760         uint8_t                 mac_addr[RTE_ETHER_ADDR_LEN];
 761
 762         uint16_t                        chimp_cmd_seq;
 763         uint16_t                        kong_cmd_seq;
 764         void                            *hwrm_cmd_resp_addr;
 765         rte_iova_t                      hwrm_cmd_resp_dma_addr;
 766         void                            *hwrm_short_cmd_req_addr;
 767         rte_iova_t                      hwrm_short_cmd_req_dma_addr;
 768         rte_spinlock_t                  hwrm_lock;
 769         /* synchronize between dev_configure_op and int handler */
 770         pthread_mutex_t                 def_cp_lock;
 771         /* synchronize between dev_start_op and async evt handler
 772          * Locking sequence in async evt handler will be
 773          * def_cp_lock
 774          * health_check_lock
 775          */
 776         pthread_mutex_t                 health_check_lock;
 777         /* synchronize between dev_stop/dev_close_op and
 778          * error recovery thread triggered as part of
 779          * HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY
 780          */
 781         pthread_mutex_t                 err_recovery_lock;
 782         uint16_t                        max_req_len;
 783         uint16_t                        max_resp_len;
 784         uint16_t                        hwrm_max_ext_req_len;
 785
 786          /* default command timeout value of 500ms */
 787 #define DFLT_HWRM_CMD_TIMEOUT           500000
 788          /* short command timeout value of 50ms */
 789 #define SHORT_HWRM_CMD_TIMEOUT          50000
 790         /* default HWRM request timeout value */
 791         uint32_t                        hwrm_cmd_timeout;
 792
 793         struct bnxt_link_info           *link_info;
 794         struct bnxt_cos_queue_info      *rx_cos_queue;
 795         struct bnxt_cos_queue_info      *tx_cos_queue;
 796         uint8_t                 tx_cosq_id[BNXT_COS_QUEUE_COUNT];
 797         uint8_t                 rx_cosq_cnt;
 798         uint8_t                 max_tc;
 799         uint8_t                 max_lltc;
 800         uint8_t                 max_q;
 801
 802         uint16_t                fw_fid;
 803         uint16_t                max_rsscos_ctx;
 804         uint16_t                max_cp_rings;
 805         uint16_t                max_tx_rings;
 806         uint16_t                max_rx_rings;
 807 #define MAX_STINGRAY_RINGS              236U
 808 #define BNXT_MAX_VF_REP_RINGS   8U
 809
 810         uint16_t                max_nq_rings;
 811         uint16_t                max_l2_ctx;
 812         uint16_t                max_rx_em_flows;
 813         uint16_t                max_vnics;
 814         uint16_t                max_stat_ctx;
 815         uint16_t                max_tpa_v2;
 816         uint16_t                first_vf_id;
 817         uint16_t                vlan;
 818 #define BNXT_OUTER_TPID_MASK    0x0000ffff
 819 #define BNXT_OUTER_TPID_BD_MASK 0xffff0000
 820 #define BNXT_OUTER_TPID_BD_SHFT 16
 821         uint32_t                outer_tpid_bd;
 822         struct bnxt_pf_info     *pf;
 823         struct bnxt_parent_info *parent;
 824         uint8_t                 port_cnt;
 825         uint8_t                 vxlan_port_cnt;
 826         uint8_t                 geneve_port_cnt;
 827         uint16_t                vxlan_port;
 828         uint16_t                geneve_port;
 829         uint16_t                vxlan_fw_dst_port_id;
 830         uint16_t                geneve_fw_dst_port_id;
 831         uint32_t                fw_ver;
 832         uint32_t                hwrm_spec_code;
 833
 834         struct bnxt_led_info    *leds;
 835         struct bnxt_ptp_cfg     *ptp_cfg;
 836         uint16_t                vf_resv_strategy;
 837         struct bnxt_ctx_mem_info        *ctx;
 838
 839         uint16_t                fw_reset_min_msecs;
 840         uint16_t                fw_reset_max_msecs;
 841         uint16_t                switch_domain_id;
 842         uint16_t                num_reps;
 843         struct bnxt_rep_info    *rep_info;
 844         uint16_t                *cfa_code_map;
 845         /* Struct to hold adapter error recovery related info */
 846         struct bnxt_error_recovery_info *recovery_info;
 847 #define BNXT_MARK_TABLE_SZ      (sizeof(struct bnxt_mark_info)  * 64 * 1024)
 848 /* TCAM and EM should be 16-bit only. Other modes not supported. */
 849 #define BNXT_FLOW_ID_MASK       0x0000ffff
 850         struct bnxt_mark_info   *mark_table;
 851
 852 #define BNXT_SVIF_INVALID       0xFFFF
 853         uint16_t                func_svif;
 854         uint16_t                port_svif;
 855
 856         struct tf               tfp;
 857         struct tf               tfp_shared;
 858         struct bnxt_ulp_context *ulp_ctx;
 859         struct bnxt_flow_stat_info *flow_stat;
 860         uint16_t                max_num_kflows;
 861         uint8_t                 app_id;
 862         uint16_t                tx_cfa_action;
 863         struct bnxt_ring_stats  *prev_rx_ring_stats;
 864         struct bnxt_ring_stats  *prev_tx_ring_stats;
 865
 866 #define BNXT_MAX_MC_ADDRS       ((bp)->max_mcast_addr)
 867         struct rte_ether_addr   *mcast_addr_list;
 868         rte_iova_t              mc_list_dma_addr;
 869         uint32_t                nb_mc_addr;
 870         uint32_t                max_mcast_addr; /* maximum number of mcast filters supported */
 871
 872         struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
 873         uint16_t                tunnel_disable_flag; /* tunnel stateless offloads status */
 874 };
 875
 876 static
 877 inline uint16_t bnxt_max_rings(struct bnxt *bp)
 878 {
 879         uint16_t max_tx_rings = bp->max_tx_rings;
 880         uint16_t max_rx_rings = bp->max_rx_rings;
 881         uint16_t max_cp_rings = bp->max_cp_rings;
 882         uint16_t max_rings;
 883
 884         /* For the sake of symmetry:
 885          * max Tx rings == max Rx rings, one stat ctx for each.
 886          */
 887         if (BNXT_STINGRAY(bp)) {
 888                 max_rx_rings = RTE_MIN(RTE_MIN(max_rx_rings / 2U,
 889                                                MAX_STINGRAY_RINGS),
 890                                        bp->max_stat_ctx / 2U);
 891         } else {
 892                 max_rx_rings = RTE_MIN(max_rx_rings / 2U,
 893                                        bp->max_stat_ctx / 2U);
 894         }
 895
 896         /*
 897          * RSS table size in Thor is 512.
 898          * Cap max Rx rings to the same value for RSS.
 899          */
 900         if (BNXT_CHIP_P5(bp))
 901                 max_rx_rings = RTE_MIN(max_rx_rings, BNXT_RSS_TBL_SIZE_P5);
 902
 903         max_tx_rings = RTE_MIN(max_tx_rings, max_rx_rings);
 904         if (max_cp_rings > BNXT_NUM_ASYNC_CPR(bp))
 905                 max_cp_rings -= BNXT_NUM_ASYNC_CPR(bp);
 906         max_rings = RTE_MIN(max_cp_rings / 2U, max_tx_rings);
 907
 908         return max_rings;
 909 }
 910
 911 #define BNXT_FC_TIMER   1 /* Timer freq in Sec Flow Counters */
 912
 913 /**
 914  * Structure to store private data for each VF representor instance
 915  */
 916 struct bnxt_representor {
 917         uint16_t                switch_domain_id;
 918         uint16_t                vf_id;
 919 #define BNXT_REP_IS_PF          BIT(0)
 920 #define BNXT_REP_Q_R2F_VALID            BIT(1)
 921 #define BNXT_REP_Q_F2R_VALID            BIT(2)
 922 #define BNXT_REP_FC_R2F_VALID           BIT(3)
 923 #define BNXT_REP_FC_F2R_VALID           BIT(4)
 924 #define BNXT_REP_BASED_PF_VALID         BIT(5)
 925         uint32_t                flags;
 926         uint16_t                fw_fid;
 927 #define BNXT_DFLT_VNIC_ID_INVALID       0xFFFF
 928         uint16_t                dflt_vnic_id;
 929         uint16_t                svif;
 930         uint16_t                vfr_tx_cfa_action;
 931         uint8_t                 parent_pf_idx; /* Logical PF index */
 932         uint32_t                dpdk_port_id;
 933         uint32_t                rep_based_pf;
 934         uint8_t                 rep_q_r2f;
 935         uint8_t                 rep_q_f2r;
 936         uint8_t                 rep_fc_r2f;
 937         uint8_t                 rep_fc_f2r;
 938         /* Private data store of associated PF/Trusted VF */
 939         struct rte_eth_dev      *parent_dev;
 940         uint8_t                 mac_addr[RTE_ETHER_ADDR_LEN];
 941         uint8_t                 dflt_mac_addr[RTE_ETHER_ADDR_LEN];
 942         struct bnxt_rx_queue    **rx_queues;
 943         unsigned int            rx_nr_rings;
 944         unsigned int            tx_nr_rings;
 945         uint64_t                tx_pkts[BNXT_MAX_VF_REP_RINGS];
 946         uint64_t                tx_bytes[BNXT_MAX_VF_REP_RINGS];
 947         uint64_t                rx_pkts[BNXT_MAX_VF_REP_RINGS];
 948         uint64_t                rx_bytes[BNXT_MAX_VF_REP_RINGS];
 949         uint64_t                rx_drop_pkts[BNXT_MAX_VF_REP_RINGS];
 950         uint64_t                rx_drop_bytes[BNXT_MAX_VF_REP_RINGS];
 951 };
 952
 953 #define BNXT_REP_PF(vfr_bp)             ((vfr_bp)->flags & BNXT_REP_IS_PF)
 954 #define BNXT_REP_BASED_PF(vfr_bp)       \
 955                 ((vfr_bp)->flags & BNXT_REP_BASED_PF_VALID)
 956
 957 struct bnxt_vf_rep_tx_queue {
 958         struct bnxt_tx_queue *txq;
 959         struct bnxt_representor *bp;
 960 };
 961
 962 #define I2C_DEV_ADDR_A0                 0xa0
 963 #define I2C_DEV_ADDR_A2                 0xa2
 964 #define SFF_DIAG_SUPPORT_OFFSET         0x5c
 965 #define SFF_MODULE_ID_SFP               0x3
 966 #define SFF_MODULE_ID_QSFP              0xc
 967 #define SFF_MODULE_ID_QSFP_PLUS         0xd
 968 #define SFF_MODULE_ID_QSFP28            0x11
 969 #define SFF8636_FLATMEM_OFFSET          0x2
 970 #define SFF8636_FLATMEM_MASK            0x4
 971 #define SFF8636_OPT_PAGES_OFFSET        0xc3
 972 #define SFF8636_PAGE1_MASK              0x40
 973 #define SFF8636_PAGE2_MASK              0x80
 974 #define BNXT_MAX_PHY_I2C_RESP_SIZE      64
 975
 976 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 977 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
 978                      bool exp_link_status);
 979 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
 980 int is_bnxt_in_error(struct bnxt *bp);
 981
 982 int bnxt_map_fw_health_status_regs(struct bnxt *bp);
 983 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index);
 984 void bnxt_schedule_fw_health_check(struct bnxt *bp);
 985
 986 bool is_bnxt_supported(struct rte_eth_dev *dev);
 987 bool bnxt_stratus_device(struct bnxt *bp);
 988 void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 989 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp);
 990 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
 991                         int wait_to_complete);
 992
 993 extern const struct rte_flow_ops bnxt_flow_ops;
 994
 995 #define bnxt_acquire_flow_lock(bp) \
 996         pthread_mutex_lock(&(bp)->flow_lock)
 997
 998 #define bnxt_release_flow_lock(bp) \
 999         pthread_mutex_unlock(&(bp)->flow_lock)
1000
1001 #define BNXT_VALID_VNIC_OR_RET(bp, vnic_id) do { \
1002         if ((vnic_id) >= (bp)->max_vnics) { \
1003                 rte_flow_error_set(error, \
1004                                 EINVAL, \
1005                                 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, \
1006                                 NULL, \
1007                                 "Group id is invalid!"); \
1008                 rc = -rte_errno; \
1009                 goto ret; \
1010         } \
1011 } while (0)
1012
1013 #define BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)    \
1014                 ((eth_dev)->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1015
1016 extern int bnxt_logtype_driver;
1017 #define PMD_DRV_LOG_RAW(level, fmt, args...) \
1018         rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \
1019                 __func__, ## args)
1020
1021 #define PMD_DRV_LOG(level, fmt, args...) \
1022           PMD_DRV_LOG_RAW(level, fmt, ## args)
1023
1024 extern const struct rte_flow_ops bnxt_ulp_rte_flow_ops;
1025 int32_t bnxt_ulp_port_init(struct bnxt *bp);
1026 void bnxt_ulp_port_deinit(struct bnxt *bp);
1027 int32_t bnxt_ulp_create_df_rules(struct bnxt *bp);
1028 void bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global);
1029 int32_t
1030 bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev);
1031 int32_t
1032 bnxt_ulp_delete_vfr_default_rules(struct bnxt_representor *vfr);
1033 int bnxt_rep_dev_start_op(struct rte_eth_dev *eth_dev);
1034
1035 void bnxt_cancel_fc_thread(struct bnxt *bp);
1036 void bnxt_flow_cnt_alarm_cb(void *arg);
1037 int bnxt_flow_stats_req(struct bnxt *bp);
1038 int bnxt_flow_stats_cnt(struct bnxt *bp);
1039 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp);
1040 int bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
1041                          const struct rte_flow_ops **ops);
1042 int bnxt_dev_start_op(struct rte_eth_dev *eth_dev);
1043 int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev);
1044 void bnxt_handle_vf_cfg_change(void *arg);
1045
1046 #endif