1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
11 #include <sys/queue.h>
14 #include <rte_bus_pci.h>
15 #include <rte_ethdev_driver.h>
16 #include <rte_memory.h>
17 #include <rte_lcore.h>
18 #include <rte_spinlock.h>
23 #define BNXT_MAX_MTU 9500
24 #define VLAN_TAG_SIZE 4
25 #define BNXT_MAX_LED 4
26 #define BNXT_NUM_VLANS 2
27 #define BNXT_MIN_RING_DESC 16
28 #define BNXT_MAX_TX_RING_DESC 4096
29 #define BNXT_MAX_RX_RING_DESC 8192
31 #define BNXT_INT_LAT_TMR_MIN 75
32 #define BNXT_INT_LAT_TMR_MAX 150
33 #define BNXT_NUM_CMPL_AGGR_INT 36
34 #define BNXT_CMPL_AGGR_DMA_TMR 37
35 #define BNXT_NUM_CMPL_DMA_AGGR 36
36 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT 50
37 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT 12
39 struct bnxt_led_info {
44 uint16_t led_state_caps;
45 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
46 rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
48 uint16_t led_color_caps;
56 uint16_t led_blink_on;
57 uint16_t led_blink_off;
62 #define BNXT_LED_DFLT_ENA \
63 (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID | \
64 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE | \
65 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON | \
66 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF | \
67 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
69 #define BNXT_LED_DFLT_ENA_SHIFT 6
71 #define BNXT_LED_DFLT_ENABLES(x) \
72 rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
74 enum bnxt_hw_context {
76 HW_CONTEXT_IS_RSS = 1,
77 HW_CONTEXT_IS_COS = 2,
81 struct bnxt_vlan_table_entry {
84 } __attribute__((packed));
86 struct bnxt_vlan_antispoof_table_entry {
90 } __attribute__((packed));
92 struct bnxt_child_vf_info {
94 struct bnxt_vlan_table_entry *vlan_table;
95 struct bnxt_vlan_antispoof_table_entry *vlan_as_table;
96 STAILQ_HEAD(, bnxt_filter_info) filter;
97 uint32_t func_cfg_flags;
100 uint16_t max_tx_rate;
103 uint8_t mac_spoof_en;
104 uint8_t vlan_spoof_en;
109 struct bnxt_pf_info {
110 #define BNXT_FIRST_PF_FID 1
111 #define BNXT_MAX_VFS(bp) (bp->pf.max_vfs)
112 #define BNXT_TOTAL_VFS(bp) ((bp)->pf.total_vfs)
113 #define BNXT_FIRST_VF_FID 128
114 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp)
115 #define BNXT_PF_RINGS_AVAIL(bp) (bp->pf.max_cp_rings - BNXT_PF_RINGS_USED(bp))
117 uint16_t first_vf_id;
120 uint16_t total_vfs; /* Total VFs possible.
121 * Not necessarily enabled.
123 uint32_t func_cfg_flags;
125 rte_iova_t vf_req_buf_dma_addr;
126 uint32_t vf_req_fwd[8];
127 uint16_t total_vnics;
128 struct bnxt_child_vf_info *vf_info;
129 #define BNXT_EVB_MODE_NONE 0
130 #define BNXT_EVB_MODE_VEB 1
131 #define BNXT_EVB_MODE_VEPA 2
135 /* Max wait time is 10 * 100ms = 1s */
136 #define BNXT_LINK_WAIT_CNT 10
137 #define BNXT_LINK_WAIT_INTERVAL 100
138 struct bnxt_link_info {
141 uint8_t phy_link_status;
149 #define PHY_VER_LEN 3
150 uint8_t phy_ver[PHY_VER_LEN];
152 uint16_t support_speeds;
153 uint16_t auto_link_speed;
154 uint16_t force_link_speed;
155 uint16_t auto_link_speed_mask;
156 uint32_t preemphasis;
161 #define BNXT_COS_QUEUE_COUNT 8
162 struct bnxt_cos_queue_info {
168 STAILQ_ENTRY(rte_flow) next;
169 struct bnxt_filter_info *filter;
170 struct bnxt_vnic_info *vnic;
173 struct bnxt_ptp_cfg {
174 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
175 #define BNXT_GRCPF_REG_SYNC_TIME 0x480
176 #define BNXT_CYCLECOUNTER_MASK 0xffffffffffffffffULL
177 struct rte_timecounter tc;
178 struct rte_timecounter tx_tstamp_tc;
179 struct rte_timecounter rx_tstamp_tc;
181 #define BNXT_MAX_TX_TS 1
183 #define BNXT_PTP_MSG_SYNC (1 << 0)
184 #define BNXT_PTP_MSG_DELAY_REQ (1 << 1)
185 #define BNXT_PTP_MSG_PDELAY_REQ (1 << 2)
186 #define BNXT_PTP_MSG_PDELAY_RESP (1 << 3)
187 #define BNXT_PTP_MSG_FOLLOW_UP (1 << 8)
188 #define BNXT_PTP_MSG_DELAY_RESP (1 << 9)
189 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP (1 << 10)
190 #define BNXT_PTP_MSG_ANNOUNCE (1 << 11)
191 #define BNXT_PTP_MSG_SIGNALING (1 << 12)
192 #define BNXT_PTP_MSG_MANAGEMENT (1 << 13)
193 #define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \
194 BNXT_PTP_MSG_DELAY_REQ | \
195 BNXT_PTP_MSG_PDELAY_REQ | \
196 BNXT_PTP_MSG_PDELAY_RESP)
197 uint8_t tx_tstamp_en:1;
200 #define BNXT_PTP_RX_TS_L 0
201 #define BNXT_PTP_RX_TS_H 1
202 #define BNXT_PTP_RX_SEQ 2
203 #define BNXT_PTP_RX_FIFO 3
204 #define BNXT_PTP_RX_FIFO_PENDING 0x1
205 #define BNXT_PTP_RX_FIFO_ADV 4
206 #define BNXT_PTP_RX_REGS 5
208 #define BNXT_PTP_TX_TS_L 0
209 #define BNXT_PTP_TX_TS_H 1
210 #define BNXT_PTP_TX_SEQ 2
211 #define BNXT_PTP_TX_FIFO 3
212 #define BNXT_PTP_TX_FIFO_EMPTY 0x2
213 #define BNXT_PTP_TX_REGS 4
214 uint32_t rx_regs[BNXT_PTP_RX_REGS];
215 uint32_t rx_mapped_regs[BNXT_PTP_RX_REGS];
216 uint32_t tx_regs[BNXT_PTP_TX_REGS];
217 uint32_t tx_mapped_regs[BNXT_PTP_TX_REGS];
221 uint16_t num_cmpl_aggr_int;
222 uint16_t num_cmpl_dma_aggr;
223 uint16_t num_cmpl_dma_aggr_during_int;
224 uint16_t int_lat_tmr_max;
225 uint16_t int_lat_tmr_min;
226 uint16_t cmpl_aggr_dma_tmr;
227 uint16_t cmpl_aggr_dma_tmr_during_int;
230 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input)
234 struct rte_eth_dev *eth_dev;
235 struct rte_eth_rss_conf rss_conf;
236 struct rte_pci_device *pdev;
240 #define BNXT_FLAG_REGISTERED (1 << 0)
241 #define BNXT_FLAG_VF (1 << 1)
242 #define BNXT_FLAG_PORT_STATS (1 << 2)
243 #define BNXT_FLAG_JUMBO (1 << 3)
244 #define BNXT_FLAG_SHORT_CMD (1 << 4)
245 #define BNXT_FLAG_UPDATE_HASH (1 << 5)
246 #define BNXT_FLAG_PTP_SUPPORTED (1 << 6)
247 #define BNXT_FLAG_MULTI_HOST (1 << 7)
248 #define BNXT_FLAG_NEW_RM (1 << 30)
249 #define BNXT_FLAG_INIT_DONE (1 << 31)
250 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
251 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
252 #define BNXT_NPAR(bp) ((bp)->port_partition_type)
253 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
254 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
256 unsigned int rx_nr_rings;
257 unsigned int rx_cp_nr_rings;
258 struct bnxt_rx_queue **rx_queues;
259 const void *rx_mem_zone;
260 struct rx_port_stats *hw_rx_port_stats;
261 rte_iova_t hw_rx_port_stats_map;
263 unsigned int tx_nr_rings;
264 unsigned int tx_cp_nr_rings;
265 struct bnxt_tx_queue **tx_queues;
266 const void *tx_mem_zone;
267 struct tx_port_stats *hw_tx_port_stats;
268 rte_iova_t hw_tx_port_stats_map;
270 /* Default completion ring */
271 struct bnxt_cp_ring_info *def_cp_ring;
272 uint32_t max_ring_grps;
273 struct bnxt_ring_grp_info *grp_info;
275 unsigned int nr_vnics;
277 struct bnxt_vnic_info *vnic_info;
278 STAILQ_HEAD(, bnxt_vnic_info) free_vnic_list;
280 struct bnxt_filter_info *filter_info;
281 STAILQ_HEAD(, bnxt_filter_info) free_filter_list;
283 /* VNIC pointer for flow filter (VMDq) pools */
284 #define MAX_FF_POOLS 256
285 STAILQ_HEAD(, bnxt_vnic_info) ff_pool[MAX_FF_POOLS];
287 struct bnxt_irq *irq_tbl;
289 #define MAX_NUM_MAC_ADDR 32
290 uint8_t mac_addr[ETHER_ADDR_LEN];
292 uint16_t hwrm_cmd_seq;
293 void *hwrm_cmd_resp_addr;
294 rte_iova_t hwrm_cmd_resp_dma_addr;
295 void *hwrm_short_cmd_req_addr;
296 rte_iova_t hwrm_short_cmd_req_dma_addr;
297 rte_spinlock_t hwrm_lock;
298 uint16_t max_req_len;
299 uint16_t max_resp_len;
301 struct bnxt_link_info link_info;
302 struct bnxt_cos_queue_info cos_queue[BNXT_COS_QUEUE_COUNT];
306 uint8_t dflt_mac_addr[ETHER_ADDR_LEN];
307 uint16_t max_rsscos_ctx;
308 uint16_t max_cp_rings;
309 uint16_t max_tx_rings;
310 uint16_t max_rx_rings;
313 uint16_t max_stat_ctx;
315 struct bnxt_pf_info pf;
316 uint8_t port_partition_type;
318 uint8_t vxlan_port_cnt;
319 uint8_t geneve_port_cnt;
321 uint16_t geneve_port;
322 uint16_t vxlan_fw_dst_port_id;
323 uint16_t geneve_fw_dst_port_id;
325 uint32_t hwrm_spec_code;
327 struct bnxt_led_info leds[BNXT_MAX_LED];
329 struct bnxt_ptp_cfg *ptp_cfg;
332 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete);
333 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
335 bool is_bnxt_supported(struct rte_eth_dev *dev);
336 bool bnxt_stratus_device(struct bnxt *bp);
337 extern const struct rte_flow_ops bnxt_flow_ops;
339 extern int bnxt_logtype_driver;
340 #define PMD_DRV_LOG_RAW(level, fmt, args...) \
341 rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \
344 #define PMD_DRV_LOG(level, fmt, args...) \
345 PMD_DRV_LOG_RAW(level, fmt, ## args)