1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
11 #include <sys/queue.h>
14 #include <rte_bus_pci.h>
15 #include <rte_ethdev_driver.h>
16 #include <rte_memory.h>
17 #include <rte_lcore.h>
18 #include <rte_spinlock.h>
22 #include "bnxt_util.h"
24 #define BNXT_MAX_MTU 9574
25 #define VLAN_TAG_SIZE 4
26 #define BNXT_VF_RSV_NUM_RSS_CTX 1
27 #define BNXT_VF_RSV_NUM_L2_CTX 4
28 /* TODO: For now, do not support VMDq/RFS on VFs. */
29 #define BNXT_VF_RSV_NUM_VNIC 1
30 #define BNXT_MAX_LED 4
31 #define BNXT_NUM_VLANS 2
32 #define BNXT_MIN_RING_DESC 16
33 #define BNXT_MAX_TX_RING_DESC 4096
34 #define BNXT_MAX_RX_RING_DESC 8192
35 #define BNXT_DB_SIZE 0x80
38 #define BNXT_NUM_ASYNC_CPR(bp) (BNXT_STINGRAY(bp) ? 0 : 1)
40 #define BNXT_NUM_ASYNC_CPR(bp) 1
43 /* Chimp Communication Channel */
44 #define GRCPF_REG_CHIMP_CHANNEL_OFFSET 0x0
45 #define GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
46 /* Kong Communication Channel */
47 #define GRCPF_REG_KONG_CHANNEL_OFFSET 0xA00
48 #define GRCPF_REG_KONG_COMM_TRIGGER 0xB00
50 #define BNXT_INT_LAT_TMR_MIN 75
51 #define BNXT_INT_LAT_TMR_MAX 150
52 #define BNXT_NUM_CMPL_AGGR_INT 36
53 #define BNXT_CMPL_AGGR_DMA_TMR 37
54 #define BNXT_NUM_CMPL_DMA_AGGR 36
55 #define BNXT_CMPL_AGGR_DMA_TMR_DURING_INT 50
56 #define BNXT_NUM_CMPL_DMA_AGGR_DURING_INT 12
58 struct bnxt_led_info {
63 uint16_t led_state_caps;
64 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
65 rte_cpu_to_le_16(HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_BLINKALT))
67 uint16_t led_color_caps;
75 uint16_t led_blink_on;
76 uint16_t led_blink_off;
81 #define BNXT_LED_DFLT_ENA \
82 (HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID | \
83 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE | \
84 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON | \
85 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF | \
86 HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID)
88 #define BNXT_LED_DFLT_ENA_SHIFT 6
90 #define BNXT_LED_DFLT_ENABLES(x) \
91 rte_cpu_to_le_32(BNXT_LED_DFLT_ENA << (BNXT_LED_DFLT_ENA_SHIFT * (x)))
93 enum bnxt_hw_context {
95 HW_CONTEXT_IS_RSS = 1,
96 HW_CONTEXT_IS_COS = 2,
100 struct bnxt_vlan_table_entry {
103 } __attribute__((packed));
105 struct bnxt_vlan_antispoof_table_entry {
109 } __attribute__((packed));
111 struct bnxt_child_vf_info {
113 struct bnxt_vlan_table_entry *vlan_table;
114 struct bnxt_vlan_antispoof_table_entry *vlan_as_table;
115 STAILQ_HEAD(, bnxt_filter_info) filter;
116 uint32_t func_cfg_flags;
119 uint16_t max_tx_rate;
122 uint8_t mac_spoof_en;
123 uint8_t vlan_spoof_en;
128 struct bnxt_pf_info {
129 #define BNXT_FIRST_PF_FID 1
130 #define BNXT_MAX_VFS(bp) (bp->pf.max_vfs)
131 #define BNXT_TOTAL_VFS(bp) ((bp)->pf.total_vfs)
132 #define BNXT_FIRST_VF_FID 128
133 #define BNXT_PF_RINGS_USED(bp) bnxt_get_num_queues(bp)
134 #define BNXT_PF_RINGS_AVAIL(bp) (bp->pf.max_cp_rings - BNXT_PF_RINGS_USED(bp))
136 uint16_t first_vf_id;
139 uint16_t total_vfs; /* Total VFs possible.
140 * Not necessarily enabled.
142 uint32_t func_cfg_flags;
144 rte_iova_t vf_req_buf_dma_addr;
145 uint32_t vf_req_fwd[8];
146 uint16_t total_vnics;
147 struct bnxt_child_vf_info *vf_info;
148 #define BNXT_EVB_MODE_NONE 0
149 #define BNXT_EVB_MODE_VEB 1
150 #define BNXT_EVB_MODE_VEPA 2
154 /* Max wait time is 10 * 100ms = 1s */
155 #define BNXT_LINK_WAIT_CNT 10
156 #define BNXT_LINK_WAIT_INTERVAL 100
157 struct bnxt_link_info {
160 uint8_t phy_link_status;
168 #define PHY_VER_LEN 3
169 uint8_t phy_ver[PHY_VER_LEN];
171 uint16_t support_speeds;
172 uint16_t auto_link_speed;
173 uint16_t force_link_speed;
174 uint16_t auto_link_speed_mask;
175 uint32_t preemphasis;
180 #define BNXT_COS_QUEUE_COUNT 8
181 struct bnxt_cos_queue_info {
187 STAILQ_ENTRY(rte_flow) next;
188 struct bnxt_filter_info *filter;
189 struct bnxt_vnic_info *vnic;
192 struct bnxt_ptp_cfg {
193 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
194 #define BNXT_GRCPF_REG_SYNC_TIME 0x480
195 #define BNXT_CYCLECOUNTER_MASK 0xffffffffffffffffULL
196 struct rte_timecounter tc;
197 struct rte_timecounter tx_tstamp_tc;
198 struct rte_timecounter rx_tstamp_tc;
200 #define BNXT_MAX_TX_TS 1
202 #define BNXT_PTP_MSG_SYNC BIT(0)
203 #define BNXT_PTP_MSG_DELAY_REQ BIT(1)
204 #define BNXT_PTP_MSG_PDELAY_REQ BIT(2)
205 #define BNXT_PTP_MSG_PDELAY_RESP BIT(3)
206 #define BNXT_PTP_MSG_FOLLOW_UP BIT(8)
207 #define BNXT_PTP_MSG_DELAY_RESP BIT(9)
208 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP BIT(10)
209 #define BNXT_PTP_MSG_ANNOUNCE BIT(11)
210 #define BNXT_PTP_MSG_SIGNALING BIT(12)
211 #define BNXT_PTP_MSG_MANAGEMENT BIT(13)
212 #define BNXT_PTP_MSG_EVENTS (BNXT_PTP_MSG_SYNC | \
213 BNXT_PTP_MSG_DELAY_REQ | \
214 BNXT_PTP_MSG_PDELAY_REQ | \
215 BNXT_PTP_MSG_PDELAY_RESP)
216 uint8_t tx_tstamp_en:1;
219 #define BNXT_PTP_RX_TS_L 0
220 #define BNXT_PTP_RX_TS_H 1
221 #define BNXT_PTP_RX_SEQ 2
222 #define BNXT_PTP_RX_FIFO 3
223 #define BNXT_PTP_RX_FIFO_PENDING 0x1
224 #define BNXT_PTP_RX_FIFO_ADV 4
225 #define BNXT_PTP_RX_REGS 5
227 #define BNXT_PTP_TX_TS_L 0
228 #define BNXT_PTP_TX_TS_H 1
229 #define BNXT_PTP_TX_SEQ 2
230 #define BNXT_PTP_TX_FIFO 3
231 #define BNXT_PTP_TX_FIFO_EMPTY 0x2
232 #define BNXT_PTP_TX_REGS 4
233 uint32_t rx_regs[BNXT_PTP_RX_REGS];
234 uint32_t rx_mapped_regs[BNXT_PTP_RX_REGS];
235 uint32_t tx_regs[BNXT_PTP_TX_REGS];
236 uint32_t tx_mapped_regs[BNXT_PTP_TX_REGS];
240 uint16_t num_cmpl_aggr_int;
241 uint16_t num_cmpl_dma_aggr;
242 uint16_t num_cmpl_dma_aggr_during_int;
243 uint16_t int_lat_tmr_max;
244 uint16_t int_lat_tmr_min;
245 uint16_t cmpl_aggr_dma_tmr;
246 uint16_t cmpl_aggr_dma_tmr_during_int;
249 /* 64-bit doorbell */
250 #define DBR_XID_SFT 32
251 #define DBR_PATH_L2 (0x1ULL << 56)
252 #define DBR_TYPE_SQ (0x0ULL << 60)
253 #define DBR_TYPE_SRQ (0x2ULL << 60)
254 #define DBR_TYPE_CQ (0x4ULL << 60)
255 #define DBR_TYPE_NQ (0xaULL << 60)
256 #define DBR_TYPE_NQ_ARM (0xbULL << 60)
258 #define BNXT_RSS_TBL_SIZE_THOR 512
259 #define BNXT_RSS_ENTRIES_PER_CTX_THOR 64
260 #define BNXT_MAX_RSS_CTXTS_THOR \
261 (BNXT_RSS_TBL_SIZE_THOR / BNXT_RSS_ENTRIES_PER_CTX_THOR)
263 #define BNXT_MAX_TC 8
264 #define BNXT_MAX_QUEUE 8
265 #define BNXT_MAX_TC_Q (BNXT_MAX_TC + 1)
266 #define BNXT_MAX_Q (bp->max_q + 1)
267 #define BNXT_PAGE_SHFT 12
268 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHFT)
269 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
271 #define PTU_PTE_VALID 0x1UL
272 #define PTU_PTE_LAST 0x2UL
273 #define PTU_PTE_NEXT_TO_LAST 0x4UL
275 struct bnxt_ring_mem_info {
279 #define BNXT_RMEM_VALID_PTE_FLAG 1
280 #define BNXT_RMEM_RING_PTE_FLAG 2
284 const struct rte_memzone *mz;
287 rte_iova_t pg_tbl_map;
288 const struct rte_memzone *pg_tbl_mz;
294 struct bnxt_ctx_pg_info {
296 void *ctx_pg_arr[MAX_CTX_PAGES];
297 rte_iova_t ctx_dma_arr[MAX_CTX_PAGES];
298 struct bnxt_ring_mem_info ring_mem;
301 struct bnxt_ctx_mem_info {
302 uint32_t qp_max_entries;
303 uint16_t qp_min_qp1_entries;
304 uint16_t qp_max_l2_entries;
305 uint16_t qp_entry_size;
306 uint16_t srq_max_l2_entries;
307 uint32_t srq_max_entries;
308 uint16_t srq_entry_size;
309 uint16_t cq_max_l2_entries;
310 uint32_t cq_max_entries;
311 uint16_t cq_entry_size;
312 uint16_t vnic_max_vnic_entries;
313 uint16_t vnic_max_ring_table_entries;
314 uint16_t vnic_entry_size;
315 uint32_t stat_max_entries;
316 uint16_t stat_entry_size;
317 uint16_t tqm_entry_size;
318 uint32_t tqm_min_entries_per_ring;
319 uint32_t tqm_max_entries_per_ring;
320 uint32_t mrav_max_entries;
321 uint16_t mrav_entry_size;
322 uint16_t tim_entry_size;
323 uint32_t tim_max_entries;
324 uint8_t tqm_entries_multiple;
327 #define BNXT_CTX_FLAG_INITED 0x01
329 struct bnxt_ctx_pg_info qp_mem;
330 struct bnxt_ctx_pg_info srq_mem;
331 struct bnxt_ctx_pg_info cq_mem;
332 struct bnxt_ctx_pg_info vnic_mem;
333 struct bnxt_ctx_pg_info stat_mem;
334 struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TC_Q];
337 /* Maximum Firmware Reset bail out value in milliseconds */
338 #define BNXT_MAX_FW_RESET_TIMEOUT 6000
339 /* Minimum time required for the firmware readiness in milliseconds */
340 #define BNXT_MIN_FW_READY_TIMEOUT 2000
341 /* Frequency for the firmware readiness check in milliseconds */
342 #define BNXT_FW_READY_WAIT_INTERVAL 100
344 #define US_PER_MS 1000
345 #define NS_PER_US 1000
347 struct bnxt_error_recovery_info {
348 /* All units in milliseconds */
349 uint32_t driver_polling_freq;
350 uint32_t master_func_wait_period;
351 uint32_t normal_func_wait_period;
352 uint32_t master_func_wait_period_after_reset;
353 uint32_t max_bailout_time_after_reset;
354 #define BNXT_FW_STATUS_REG 0
355 #define BNXT_FW_HEARTBEAT_CNT_REG 1
356 #define BNXT_FW_RECOVERY_CNT_REG 2
357 #define BNXT_FW_RESET_INPROG_REG 3
358 #define BNXT_FW_STATUS_REG_CNT 4
359 uint32_t status_regs[BNXT_FW_STATUS_REG_CNT];
360 uint32_t mapped_status_regs[BNXT_FW_STATUS_REG_CNT];
361 uint32_t reset_inprogress_reg_mask;
362 #define BNXT_NUM_RESET_REG 16
363 uint8_t reg_array_cnt;
364 uint32_t reset_reg[BNXT_NUM_RESET_REG];
365 uint32_t reset_reg_val[BNXT_NUM_RESET_REG];
366 uint8_t delay_after_reset[BNXT_NUM_RESET_REG];
367 #define BNXT_FLAG_ERROR_RECOVERY_HOST BIT(0)
368 #define BNXT_FLAG_ERROR_RECOVERY_CO_CPU BIT(1)
369 #define BNXT_FLAG_MASTER_FUNC BIT(2)
370 #define BNXT_FLAG_RECOVERY_ENABLED BIT(3)
373 uint32_t last_heart_beat;
374 uint32_t last_reset_counter;
377 /* address space location of register */
378 #define BNXT_FW_STATUS_REG_TYPE_MASK 3
379 /* register is located in PCIe config space */
380 #define BNXT_FW_STATUS_REG_TYPE_CFG 0
381 /* register is located in GRC address space */
382 #define BNXT_FW_STATUS_REG_TYPE_GRC 1
383 /* register is located in BAR0 */
384 #define BNXT_FW_STATUS_REG_TYPE_BAR0 2
385 /* register is located in BAR1 */
386 #define BNXT_FW_STATUS_REG_TYPE_BAR1 3
388 #define BNXT_FW_STATUS_REG_TYPE(reg) ((reg) & BNXT_FW_STATUS_REG_TYPE_MASK)
389 #define BNXT_FW_STATUS_REG_OFF(reg) ((reg) & ~BNXT_FW_STATUS_REG_TYPE_MASK)
391 #define BNXT_GRCP_WINDOW_2_BASE 0x2000
392 #define BNXT_GRCP_WINDOW_3_BASE 0x3000
394 #define BNXT_FW_STATUS_SHUTDOWN 0x100000
396 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input)
400 struct rte_eth_dev *eth_dev;
401 struct rte_eth_rss_conf rss_conf;
402 struct rte_pci_device *pdev;
406 #define BNXT_FLAG_REGISTERED BIT(0)
407 #define BNXT_FLAG_VF BIT(1)
408 #define BNXT_FLAG_PORT_STATS BIT(2)
409 #define BNXT_FLAG_JUMBO BIT(3)
410 #define BNXT_FLAG_SHORT_CMD BIT(4)
411 #define BNXT_FLAG_UPDATE_HASH BIT(5)
412 #define BNXT_FLAG_PTP_SUPPORTED BIT(6)
413 #define BNXT_FLAG_MULTI_HOST BIT(7)
414 #define BNXT_FLAG_EXT_RX_PORT_STATS BIT(8)
415 #define BNXT_FLAG_EXT_TX_PORT_STATS BIT(9)
416 #define BNXT_FLAG_KONG_MB_EN BIT(10)
417 #define BNXT_FLAG_TRUSTED_VF_EN BIT(11)
418 #define BNXT_FLAG_DFLT_VNIC_SET BIT(12)
419 #define BNXT_FLAG_THOR_CHIP BIT(13)
420 #define BNXT_FLAG_STINGRAY BIT(14)
421 #define BNXT_FLAG_FW_RESET BIT(15)
422 #define BNXT_FLAG_FATAL_ERROR BIT(16)
423 #define BNXT_FLAG_FW_CAP_IF_CHANGE BIT(17)
424 #define BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE BIT(18)
425 #define BNXT_FLAG_FW_CAP_ERROR_RECOVERY BIT(19)
426 #define BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED BIT(20)
427 #define BNXT_FLAG_FW_CAP_ERR_RECOVER_RELOAD BIT(21)
428 #define BNXT_FLAG_EXT_STATS_SUPPORTED BIT(22)
429 #define BNXT_FLAG_NEW_RM BIT(23)
430 #define BNXT_FLAG_INIT_DONE BIT(24)
431 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
432 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
433 #define BNXT_NPAR(bp) ((bp)->port_partition_type)
434 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
435 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
436 #define BNXT_USE_CHIMP_MB 0 //For non-CFA commands, everything uses Chimp.
437 #define BNXT_USE_KONG(bp) ((bp)->flags & BNXT_FLAG_KONG_MB_EN)
438 #define BNXT_VF_IS_TRUSTED(bp) ((bp)->flags & BNXT_FLAG_TRUSTED_VF_EN)
439 #define BNXT_CHIP_THOR(bp) ((bp)->flags & BNXT_FLAG_THOR_CHIP)
440 #define BNXT_STINGRAY(bp) ((bp)->flags & BNXT_FLAG_STINGRAY)
441 #define BNXT_HAS_NQ(bp) BNXT_CHIP_THOR(bp)
442 #define BNXT_HAS_RING_GRPS(bp) (!BNXT_CHIP_THOR(bp))
444 unsigned int rx_nr_rings;
445 unsigned int rx_cp_nr_rings;
446 struct bnxt_rx_queue **rx_queues;
447 const void *rx_mem_zone;
448 struct rx_port_stats *hw_rx_port_stats;
449 rte_iova_t hw_rx_port_stats_map;
450 struct rx_port_stats_ext *hw_rx_port_stats_ext;
451 rte_iova_t hw_rx_port_stats_ext_map;
452 uint16_t fw_rx_port_stats_ext_size;
454 unsigned int tx_nr_rings;
455 unsigned int tx_cp_nr_rings;
456 struct bnxt_tx_queue **tx_queues;
457 const void *tx_mem_zone;
458 struct tx_port_stats *hw_tx_port_stats;
459 rte_iova_t hw_tx_port_stats_map;
460 struct tx_port_stats_ext *hw_tx_port_stats_ext;
461 rte_iova_t hw_tx_port_stats_ext_map;
462 uint16_t fw_tx_port_stats_ext_size;
464 /* Default completion ring */
465 struct bnxt_cp_ring_info *async_cp_ring;
466 uint32_t max_ring_grps;
467 struct bnxt_ring_grp_info *grp_info;
469 unsigned int nr_vnics;
471 #define BNXT_GET_DEFAULT_VNIC(bp) (&(bp)->vnic_info[0])
472 struct bnxt_vnic_info *vnic_info;
473 STAILQ_HEAD(, bnxt_vnic_info) free_vnic_list;
475 struct bnxt_filter_info *filter_info;
476 STAILQ_HEAD(, bnxt_filter_info) free_filter_list;
478 struct bnxt_irq *irq_tbl;
480 #define MAX_NUM_MAC_ADDR 32
481 uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
483 uint16_t hwrm_cmd_seq;
484 uint16_t kong_cmd_seq;
485 void *hwrm_cmd_resp_addr;
486 rte_iova_t hwrm_cmd_resp_dma_addr;
487 void *hwrm_short_cmd_req_addr;
488 rte_iova_t hwrm_short_cmd_req_dma_addr;
489 rte_spinlock_t hwrm_lock;
490 uint16_t max_req_len;
491 uint16_t max_resp_len;
492 uint16_t hwrm_max_ext_req_len;
494 struct bnxt_link_info link_info;
495 struct bnxt_cos_queue_info cos_queue[BNXT_COS_QUEUE_COUNT];
502 uint8_t dflt_mac_addr[RTE_ETHER_ADDR_LEN];
503 uint16_t max_rsscos_ctx;
504 uint16_t max_cp_rings;
505 uint16_t max_tx_rings;
506 uint16_t max_rx_rings;
507 uint16_t max_nq_rings;
509 uint16_t max_rx_em_flows;
511 uint16_t max_stat_ctx;
512 uint16_t first_vf_id;
514 struct bnxt_pf_info pf;
515 uint8_t port_partition_type;
517 uint8_t vxlan_port_cnt;
518 uint8_t geneve_port_cnt;
520 uint16_t geneve_port;
521 uint16_t vxlan_fw_dst_port_id;
522 uint16_t geneve_fw_dst_port_id;
524 uint32_t hwrm_spec_code;
526 struct bnxt_led_info leds[BNXT_MAX_LED];
528 struct bnxt_ptp_cfg *ptp_cfg;
529 uint16_t vf_resv_strategy;
530 struct bnxt_ctx_mem_info *ctx;
532 uint16_t fw_reset_min_msecs;
533 uint16_t fw_reset_max_msecs;
535 /* Struct to hold adapter error recovery related info */
536 struct bnxt_error_recovery_info *recovery_info;
539 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete);
540 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg);
541 int is_bnxt_in_error(struct bnxt *bp);
543 int bnxt_map_fw_health_status_regs(struct bnxt *bp);
544 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index);
545 void bnxt_schedule_fw_health_check(struct bnxt *bp);
547 bool is_bnxt_supported(struct rte_eth_dev *dev);
548 bool bnxt_stratus_device(struct bnxt *bp);
549 extern const struct rte_flow_ops bnxt_flow_ops;
551 extern int bnxt_logtype_driver;
552 #define PMD_DRV_LOG_RAW(level, fmt, args...) \
553 rte_log(RTE_LOG_ ## level, bnxt_logtype_driver, "%s(): " fmt, \
556 #define PMD_DRV_LOG(level, fmt, args...) \
557 PMD_DRV_LOG_RAW(level, fmt, ## args)