1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
18 #include "bnxt_filter.h"
19 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_stats.h"
27 #include "bnxt_vnic.h"
28 #include "hsi_struct_def_dpdk.h"
29 #include "bnxt_nvm_defs.h"
30 #include "bnxt_util.h"
32 #define DRV_MODULE_NAME "bnxt"
33 static const char bnxt_version[] =
34 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
35 int bnxt_logtype_driver;
37 #define PCI_VENDOR_ID_BROADCOM 0x14E4
39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
40 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
41 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
42 #define BROADCOM_DEV_ID_57414_VF 0x16c1
43 #define BROADCOM_DEV_ID_57301 0x16c8
44 #define BROADCOM_DEV_ID_57302 0x16c9
45 #define BROADCOM_DEV_ID_57304_PF 0x16ca
46 #define BROADCOM_DEV_ID_57304_VF 0x16cb
47 #define BROADCOM_DEV_ID_57417_MF 0x16cc
48 #define BROADCOM_DEV_ID_NS2 0x16cd
49 #define BROADCOM_DEV_ID_57311 0x16ce
50 #define BROADCOM_DEV_ID_57312 0x16cf
51 #define BROADCOM_DEV_ID_57402 0x16d0
52 #define BROADCOM_DEV_ID_57404 0x16d1
53 #define BROADCOM_DEV_ID_57406_PF 0x16d2
54 #define BROADCOM_DEV_ID_57406_VF 0x16d3
55 #define BROADCOM_DEV_ID_57402_MF 0x16d4
56 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
57 #define BROADCOM_DEV_ID_57412 0x16d6
58 #define BROADCOM_DEV_ID_57414 0x16d7
59 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
60 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
61 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
62 #define BROADCOM_DEV_ID_57412_MF 0x16de
63 #define BROADCOM_DEV_ID_57314 0x16df
64 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
65 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
66 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
67 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
68 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
69 #define BROADCOM_DEV_ID_57404_MF 0x16e7
70 #define BROADCOM_DEV_ID_57406_MF 0x16e8
71 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
72 #define BROADCOM_DEV_ID_57407_MF 0x16ea
73 #define BROADCOM_DEV_ID_57414_MF 0x16ec
74 #define BROADCOM_DEV_ID_57416_MF 0x16ee
75 #define BROADCOM_DEV_ID_57508 0x1750
76 #define BROADCOM_DEV_ID_57504 0x1751
77 #define BROADCOM_DEV_ID_57502 0x1752
78 #define BROADCOM_DEV_ID_57500_VF1 0x1806
79 #define BROADCOM_DEV_ID_57500_VF2 0x1807
80 #define BROADCOM_DEV_ID_58802 0xd802
81 #define BROADCOM_DEV_ID_58804 0xd804
82 #define BROADCOM_DEV_ID_58808 0x16f0
83 #define BROADCOM_DEV_ID_58802_VF 0xd800
85 static const struct rte_pci_id bnxt_pci_id_map[] = {
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
87 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
89 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
130 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
131 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
132 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
133 { .vendor_id = 0, /* sentinel */ },
136 #define BNXT_ETH_RSS_SUPPORT ( \
138 ETH_RSS_NONFRAG_IPV4_TCP | \
139 ETH_RSS_NONFRAG_IPV4_UDP | \
141 ETH_RSS_NONFRAG_IPV6_TCP | \
142 ETH_RSS_NONFRAG_IPV6_UDP)
144 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
145 DEV_TX_OFFLOAD_IPV4_CKSUM | \
146 DEV_TX_OFFLOAD_TCP_CKSUM | \
147 DEV_TX_OFFLOAD_UDP_CKSUM | \
148 DEV_TX_OFFLOAD_TCP_TSO | \
149 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
150 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
151 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
152 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
153 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
154 DEV_TX_OFFLOAD_MULTI_SEGS)
156 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
157 DEV_RX_OFFLOAD_VLAN_STRIP | \
158 DEV_RX_OFFLOAD_IPV4_CKSUM | \
159 DEV_RX_OFFLOAD_UDP_CKSUM | \
160 DEV_RX_OFFLOAD_TCP_CKSUM | \
161 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
162 DEV_RX_OFFLOAD_JUMBO_FRAME | \
163 DEV_RX_OFFLOAD_KEEP_CRC | \
164 DEV_RX_OFFLOAD_TCP_LRO)
166 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
167 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
168 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
169 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
170 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
171 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
172 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
174 int is_bnxt_in_error(struct bnxt *bp)
176 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
178 if (bp->flags & BNXT_FLAG_FW_RESET)
184 /***********************/
187 * High level utility functions
190 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
192 if (!BNXT_CHIP_THOR(bp))
195 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
196 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
197 BNXT_RSS_ENTRIES_PER_CTX_THOR;
200 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
202 if (!BNXT_CHIP_THOR(bp))
203 return HW_HASH_INDEX_SIZE;
205 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
208 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
210 bnxt_free_filter_mem(bp);
211 bnxt_free_vnic_attributes(bp);
212 bnxt_free_vnic_mem(bp);
214 /* tx/rx rings are configured as part of *_queue_setup callbacks.
215 * If the number of rings change across fw update,
216 * we don't have much choice except to warn the user.
220 bnxt_free_tx_rings(bp);
221 bnxt_free_rx_rings(bp);
223 bnxt_free_async_cp_ring(bp);
226 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
230 rc = bnxt_alloc_ring_grps(bp);
234 rc = bnxt_alloc_async_ring_struct(bp);
238 rc = bnxt_alloc_vnic_mem(bp);
242 rc = bnxt_alloc_vnic_attributes(bp);
246 rc = bnxt_alloc_filter_mem(bp);
250 rc = bnxt_alloc_async_cp_ring(bp);
257 bnxt_free_mem(bp, reconfig);
261 static int bnxt_init_chip(struct bnxt *bp)
263 struct bnxt_rx_queue *rxq;
264 struct rte_eth_link new;
265 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
266 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
267 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
268 uint64_t rx_offloads = dev_conf->rxmode.offloads;
269 uint32_t intr_vector = 0;
270 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
271 uint32_t vec = BNXT_MISC_VEC_ID;
275 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
276 bp->eth_dev->data->dev_conf.rxmode.offloads |=
277 DEV_RX_OFFLOAD_JUMBO_FRAME;
278 bp->flags |= BNXT_FLAG_JUMBO;
280 bp->eth_dev->data->dev_conf.rxmode.offloads &=
281 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
282 bp->flags &= ~BNXT_FLAG_JUMBO;
285 /* THOR does not support ring groups.
286 * But we will use the array to save RSS context IDs.
288 if (BNXT_CHIP_THOR(bp))
289 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
291 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
293 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
297 rc = bnxt_alloc_hwrm_rings(bp);
299 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
303 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
305 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
309 rc = bnxt_mq_rx_configure(bp);
311 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
315 /* VNIC configuration */
316 for (i = 0; i < bp->nr_vnics; i++) {
317 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
318 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
319 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
321 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
322 if (!vnic->fw_grp_ids) {
324 "Failed to alloc %d bytes for group ids\n",
329 memset(vnic->fw_grp_ids, -1, size);
331 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
332 i, vnic, vnic->fw_grp_ids);
334 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
336 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
341 /* Alloc RSS context only if RSS mode is enabled */
342 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
343 int j, nr_ctxs = bnxt_rss_ctxts(bp);
346 for (j = 0; j < nr_ctxs; j++) {
347 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
353 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
357 vnic->num_lb_ctxts = nr_ctxs;
361 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
362 * setting is not available at this time, it will not be
363 * configured correctly in the CFA.
365 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
366 vnic->vlan_strip = true;
368 vnic->vlan_strip = false;
370 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
372 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
377 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
380 "HWRM vnic %d filter failure rc: %x\n",
385 for (j = 0; j < bp->rx_nr_rings; j++) {
386 rxq = bp->eth_dev->data->rx_queues[j];
389 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
390 j, rxq->vnic, rxq->vnic->fw_grp_ids);
392 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
393 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
396 rc = bnxt_vnic_rss_configure(bp, vnic);
399 "HWRM vnic set RSS failure rc: %x\n", rc);
403 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
405 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
406 DEV_RX_OFFLOAD_TCP_LRO)
407 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
409 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
411 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
414 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
418 /* check and configure queue intr-vector mapping */
419 if ((rte_intr_cap_multiple(intr_handle) ||
420 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
421 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
422 intr_vector = bp->eth_dev->data->nb_rx_queues;
423 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
424 if (intr_vector > bp->rx_cp_nr_rings) {
425 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
429 rc = rte_intr_efd_enable(intr_handle, intr_vector);
434 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
435 intr_handle->intr_vec =
436 rte_zmalloc("intr_vec",
437 bp->eth_dev->data->nb_rx_queues *
439 if (intr_handle->intr_vec == NULL) {
440 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
441 " intr_vec", bp->eth_dev->data->nb_rx_queues);
445 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
446 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
447 intr_handle->intr_vec, intr_handle->nb_efd,
448 intr_handle->max_intr);
449 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
451 intr_handle->intr_vec[queue_id] =
452 vec + BNXT_RX_VEC_START;
453 if (vec < base + intr_handle->nb_efd - 1)
458 /* enable uio/vfio intr/eventfd mapping */
459 rc = rte_intr_enable(intr_handle);
463 rc = bnxt_get_hwrm_link_config(bp, &new);
465 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
469 if (!bp->link_info.link_up) {
470 rc = bnxt_set_hwrm_link_config(bp, true);
473 "HWRM link config failure rc: %x\n", rc);
477 bnxt_print_link_info(bp->eth_dev);
482 rte_free(intr_handle->intr_vec);
484 rte_intr_efd_disable(intr_handle);
486 /* Some of the error status returned by FW may not be from errno.h */
493 static int bnxt_shutdown_nic(struct bnxt *bp)
495 bnxt_free_all_hwrm_resources(bp);
496 bnxt_free_all_filters(bp);
497 bnxt_free_all_vnics(bp);
501 static int bnxt_init_nic(struct bnxt *bp)
505 if (BNXT_HAS_RING_GRPS(bp)) {
506 rc = bnxt_init_ring_grps(bp);
512 bnxt_init_filters(bp);
518 * Device configuration and status function
521 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
522 struct rte_eth_dev_info *dev_info)
524 struct bnxt *bp = eth_dev->data->dev_private;
525 uint16_t max_vnics, i, j, vpool, vrxq;
526 unsigned int max_rx_rings;
529 rc = is_bnxt_in_error(bp);
534 dev_info->max_mac_addrs = bp->max_l2_ctx;
535 dev_info->max_hash_mac_addrs = 0;
537 /* PF/VF specifics */
539 dev_info->max_vfs = bp->pdev->max_vfs;
540 max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
541 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
542 dev_info->max_rx_queues = max_rx_rings;
543 dev_info->max_tx_queues = max_rx_rings;
544 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
545 dev_info->hash_key_size = 40;
546 max_vnics = bp->max_vnics;
548 /* Fast path specifics */
549 dev_info->min_rx_bufsize = 1;
550 dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
551 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
553 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
554 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
555 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
556 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
557 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
560 dev_info->default_rxconf = (struct rte_eth_rxconf) {
566 .rx_free_thresh = 32,
567 /* If no descriptors available, pkts are dropped by default */
571 dev_info->default_txconf = (struct rte_eth_txconf) {
577 .tx_free_thresh = 32,
580 eth_dev->data->dev_conf.intr_conf.lsc = 1;
582 eth_dev->data->dev_conf.intr_conf.rxq = 1;
583 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
584 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
585 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
586 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
591 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
592 * need further investigation.
596 vpool = 64; /* ETH_64_POOLS */
597 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
598 for (i = 0; i < 4; vpool >>= 1, i++) {
599 if (max_vnics > vpool) {
600 for (j = 0; j < 5; vrxq >>= 1, j++) {
601 if (dev_info->max_rx_queues > vrxq) {
607 /* Not enough resources to support VMDq */
611 /* Not enough resources to support VMDq */
615 dev_info->max_vmdq_pools = vpool;
616 dev_info->vmdq_queue_num = vrxq;
618 dev_info->vmdq_pool_base = 0;
619 dev_info->vmdq_queue_base = 0;
624 /* Configure the device based on the configuration provided */
625 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
627 struct bnxt *bp = eth_dev->data->dev_private;
628 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
631 bp->rx_queues = (void *)eth_dev->data->rx_queues;
632 bp->tx_queues = (void *)eth_dev->data->tx_queues;
633 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
634 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
636 rc = is_bnxt_in_error(bp);
640 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
641 rc = bnxt_hwrm_check_vf_rings(bp);
643 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
647 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
649 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
653 /* legacy driver needs to get updated values */
654 rc = bnxt_hwrm_func_qcaps(bp);
656 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
661 /* Inherit new configurations */
662 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
663 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
664 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
665 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
666 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
670 if (BNXT_HAS_RING_GRPS(bp) &&
671 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
674 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
675 bp->max_vnics < eth_dev->data->nb_rx_queues)
678 bp->rx_cp_nr_rings = bp->rx_nr_rings;
679 bp->tx_cp_nr_rings = bp->tx_nr_rings;
681 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
683 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
684 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
686 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
692 "Insufficient resources to support requested config\n");
694 "Num Queues Requested: Tx %d, Rx %d\n",
695 eth_dev->data->nb_tx_queues,
696 eth_dev->data->nb_rx_queues);
698 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
699 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
700 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
704 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
706 struct rte_eth_link *link = ð_dev->data->dev_link;
708 if (link->link_status)
709 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
710 eth_dev->data->port_id,
711 (uint32_t)link->link_speed,
712 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
713 ("full-duplex") : ("half-duplex\n"));
715 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
716 eth_dev->data->port_id);
720 * Determine whether the current configuration requires support for scattered
721 * receive; return 1 if scattered receive is required and 0 if not.
723 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
728 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
729 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
731 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
732 RTE_PKTMBUF_HEADROOM);
733 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
739 static eth_rx_burst_t
740 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
743 #ifndef RTE_LIBRTE_IEEE1588
745 * Vector mode receive can be enabled only if scatter rx is not
746 * in use and rx offloads are limited to VLAN stripping and
749 if (!eth_dev->data->scattered_rx &&
750 !(eth_dev->data->dev_conf.rxmode.offloads &
751 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
752 DEV_RX_OFFLOAD_KEEP_CRC |
753 DEV_RX_OFFLOAD_JUMBO_FRAME |
754 DEV_RX_OFFLOAD_IPV4_CKSUM |
755 DEV_RX_OFFLOAD_UDP_CKSUM |
756 DEV_RX_OFFLOAD_TCP_CKSUM |
757 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
758 DEV_RX_OFFLOAD_VLAN_FILTER))) {
759 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
760 eth_dev->data->port_id);
761 return bnxt_recv_pkts_vec;
763 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
764 eth_dev->data->port_id);
766 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
767 eth_dev->data->port_id,
768 eth_dev->data->scattered_rx,
769 eth_dev->data->dev_conf.rxmode.offloads);
772 return bnxt_recv_pkts;
775 static eth_tx_burst_t
776 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
779 #ifndef RTE_LIBRTE_IEEE1588
781 * Vector mode transmit can be enabled only if not using scatter rx
784 if (!eth_dev->data->scattered_rx &&
785 !eth_dev->data->dev_conf.txmode.offloads) {
786 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
787 eth_dev->data->port_id);
788 return bnxt_xmit_pkts_vec;
790 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
791 eth_dev->data->port_id);
793 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
794 eth_dev->data->port_id,
795 eth_dev->data->scattered_rx,
796 eth_dev->data->dev_conf.txmode.offloads);
799 return bnxt_xmit_pkts;
802 static int bnxt_handle_if_change_status(struct bnxt *bp)
806 /* Since fw has undergone a reset and lost all contexts,
807 * set fatal flag to not issue hwrm during cleanup
809 bp->flags |= BNXT_FLAG_FATAL_ERROR;
810 bnxt_uninit_resources(bp, true);
812 /* clear fatal flag so that re-init happens */
813 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
814 rc = bnxt_init_resources(bp, true);
816 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
821 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
823 struct bnxt *bp = eth_dev->data->dev_private;
824 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
828 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
830 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
831 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
834 rc = bnxt_hwrm_if_change(bp, 1);
836 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
837 rc = bnxt_handle_if_change_status(bp);
843 rc = bnxt_init_chip(bp);
847 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
849 bnxt_link_update_op(eth_dev, 1);
851 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
852 vlan_mask |= ETH_VLAN_FILTER_MASK;
853 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
854 vlan_mask |= ETH_VLAN_STRIP_MASK;
855 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
859 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
860 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
863 bp->flags |= BNXT_FLAG_INIT_DONE;
864 eth_dev->data->dev_started = 1;
866 bnxt_schedule_fw_health_check(bp);
870 bnxt_hwrm_if_change(bp, 0);
871 bnxt_shutdown_nic(bp);
872 bnxt_free_tx_mbufs(bp);
873 bnxt_free_rx_mbufs(bp);
877 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
879 struct bnxt *bp = eth_dev->data->dev_private;
882 if (!bp->link_info.link_up)
883 rc = bnxt_set_hwrm_link_config(bp, true);
885 eth_dev->data->dev_link.link_status = 1;
887 bnxt_print_link_info(eth_dev);
891 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
893 struct bnxt *bp = eth_dev->data->dev_private;
895 eth_dev->data->dev_link.link_status = 0;
896 bnxt_set_hwrm_link_config(bp, false);
897 bp->link_info.link_up = 0;
902 /* Unload the driver, release resources */
903 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
905 struct bnxt *bp = eth_dev->data->dev_private;
906 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
907 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
909 eth_dev->data->dev_started = 0;
910 /* Prevent crashes when queues are still in use */
911 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
912 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
914 bnxt_disable_int(bp);
916 /* disable uio/vfio intr/eventfd mapping */
917 rte_intr_disable(intr_handle);
919 bnxt_cancel_fw_health_check(bp);
921 bp->flags &= ~BNXT_FLAG_INIT_DONE;
922 if (bp->eth_dev->data->dev_started) {
923 /* TBD: STOP HW queues DMA */
924 eth_dev->data->dev_link.link_status = 0;
926 bnxt_set_hwrm_link_config(bp, false);
928 /* Clean queue intr-vector mapping */
929 rte_intr_efd_disable(intr_handle);
930 if (intr_handle->intr_vec != NULL) {
931 rte_free(intr_handle->intr_vec);
932 intr_handle->intr_vec = NULL;
935 bnxt_hwrm_port_clr_stats(bp);
936 bnxt_free_tx_mbufs(bp);
937 bnxt_free_rx_mbufs(bp);
938 bnxt_shutdown_nic(bp);
939 bnxt_hwrm_if_change(bp, 0);
943 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
945 struct bnxt *bp = eth_dev->data->dev_private;
947 if (bp->dev_stopped == 0)
948 bnxt_dev_stop_op(eth_dev);
950 if (eth_dev->data->mac_addrs != NULL) {
951 rte_free(eth_dev->data->mac_addrs);
952 eth_dev->data->mac_addrs = NULL;
954 if (bp->grp_info != NULL) {
955 rte_free(bp->grp_info);
959 bnxt_dev_uninit(eth_dev);
962 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
965 struct bnxt *bp = eth_dev->data->dev_private;
966 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
967 struct bnxt_vnic_info *vnic;
968 struct bnxt_filter_info *filter, *temp_filter;
971 if (is_bnxt_in_error(bp))
975 * Loop through all VNICs from the specified filter flow pools to
976 * remove the corresponding MAC addr filter
978 for (i = 0; i < bp->nr_vnics; i++) {
979 if (!(pool_mask & (1ULL << i)))
982 vnic = &bp->vnic_info[i];
983 filter = STAILQ_FIRST(&vnic->filter);
985 temp_filter = STAILQ_NEXT(filter, next);
986 if (filter->mac_index == index) {
987 STAILQ_REMOVE(&vnic->filter, filter,
988 bnxt_filter_info, next);
989 bnxt_hwrm_clear_l2_filter(bp, filter);
990 filter->mac_index = INVALID_MAC_INDEX;
991 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
992 STAILQ_INSERT_TAIL(&bp->free_filter_list,
995 filter = temp_filter;
1000 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1001 struct rte_ether_addr *mac_addr,
1002 uint32_t index, uint32_t pool)
1004 struct bnxt *bp = eth_dev->data->dev_private;
1005 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1006 struct bnxt_filter_info *filter;
1009 rc = is_bnxt_in_error(bp);
1013 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1014 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1019 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1022 /* Attach requested MAC address to the new l2_filter */
1023 STAILQ_FOREACH(filter, &vnic->filter, next) {
1024 if (filter->mac_index == index) {
1026 "MAC addr already existed for pool %d\n", pool);
1030 filter = bnxt_alloc_filter(bp);
1032 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1036 filter->mac_index = index;
1037 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1039 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1041 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1043 filter->mac_index = INVALID_MAC_INDEX;
1044 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1045 bnxt_free_filter(bp, filter);
1051 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1054 struct bnxt *bp = eth_dev->data->dev_private;
1055 struct rte_eth_link new;
1056 unsigned int cnt = BNXT_LINK_WAIT_CNT;
1058 rc = is_bnxt_in_error(bp);
1062 memset(&new, 0, sizeof(new));
1064 /* Retrieve link info from hardware */
1065 rc = bnxt_get_hwrm_link_config(bp, &new);
1067 new.link_speed = ETH_LINK_SPEED_100M;
1068 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1070 "Failed to retrieve link rc = 0x%x!\n", rc);
1074 if (!wait_to_complete || new.link_status)
1077 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1081 /* Timed out or success */
1082 if (new.link_status != eth_dev->data->dev_link.link_status ||
1083 new.link_speed != eth_dev->data->dev_link.link_speed) {
1084 memcpy(ð_dev->data->dev_link, &new,
1085 sizeof(struct rte_eth_link));
1087 _rte_eth_dev_callback_process(eth_dev,
1088 RTE_ETH_EVENT_INTR_LSC,
1091 bnxt_print_link_info(eth_dev);
1097 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1099 struct bnxt *bp = eth_dev->data->dev_private;
1100 struct bnxt_vnic_info *vnic;
1104 rc = is_bnxt_in_error(bp);
1108 if (bp->vnic_info == NULL)
1111 vnic = &bp->vnic_info[0];
1113 old_flags = vnic->flags;
1114 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1115 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1117 vnic->flags = old_flags;
1122 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1124 struct bnxt *bp = eth_dev->data->dev_private;
1125 struct bnxt_vnic_info *vnic;
1129 rc = is_bnxt_in_error(bp);
1133 if (bp->vnic_info == NULL)
1136 vnic = &bp->vnic_info[0];
1138 old_flags = vnic->flags;
1139 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1140 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1142 vnic->flags = old_flags;
1147 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1149 struct bnxt *bp = eth_dev->data->dev_private;
1150 struct bnxt_vnic_info *vnic;
1154 rc = is_bnxt_in_error(bp);
1158 if (bp->vnic_info == NULL)
1161 vnic = &bp->vnic_info[0];
1163 old_flags = vnic->flags;
1164 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1165 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1167 vnic->flags = old_flags;
1172 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1174 struct bnxt *bp = eth_dev->data->dev_private;
1175 struct bnxt_vnic_info *vnic;
1179 rc = is_bnxt_in_error(bp);
1183 if (bp->vnic_info == NULL)
1186 vnic = &bp->vnic_info[0];
1188 old_flags = vnic->flags;
1189 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1190 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1192 vnic->flags = old_flags;
1197 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1198 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1200 if (qid >= bp->rx_nr_rings)
1203 return bp->eth_dev->data->rx_queues[qid];
1206 /* Return rxq corresponding to a given rss table ring/group ID. */
1207 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1209 struct bnxt_rx_queue *rxq;
1212 if (!BNXT_HAS_RING_GRPS(bp)) {
1213 for (i = 0; i < bp->rx_nr_rings; i++) {
1214 rxq = bp->eth_dev->data->rx_queues[i];
1215 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1219 for (i = 0; i < bp->rx_nr_rings; i++) {
1220 if (bp->grp_info[i].fw_grp_id == fwr)
1225 return INVALID_HW_RING_ID;
1228 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1229 struct rte_eth_rss_reta_entry64 *reta_conf,
1232 struct bnxt *bp = eth_dev->data->dev_private;
1233 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1234 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1235 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1239 rc = is_bnxt_in_error(bp);
1243 if (!vnic->rss_table)
1246 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1249 if (reta_size != tbl_size) {
1250 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1251 "(%d) must equal the size supported by the hardware "
1252 "(%d)\n", reta_size, tbl_size);
1256 for (i = 0; i < reta_size; i++) {
1257 struct bnxt_rx_queue *rxq;
1259 idx = i / RTE_RETA_GROUP_SIZE;
1260 sft = i % RTE_RETA_GROUP_SIZE;
1262 if (!(reta_conf[idx].mask & (1ULL << sft)))
1265 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1267 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1271 if (BNXT_CHIP_THOR(bp)) {
1272 vnic->rss_table[i * 2] =
1273 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1274 vnic->rss_table[i * 2 + 1] =
1275 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1277 vnic->rss_table[i] =
1278 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1281 vnic->rss_table[i] =
1282 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1285 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1289 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1290 struct rte_eth_rss_reta_entry64 *reta_conf,
1293 struct bnxt *bp = eth_dev->data->dev_private;
1294 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1295 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1296 uint16_t idx, sft, i;
1299 rc = is_bnxt_in_error(bp);
1303 /* Retrieve from the default VNIC */
1306 if (!vnic->rss_table)
1309 if (reta_size != tbl_size) {
1310 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1311 "(%d) must equal the size supported by the hardware "
1312 "(%d)\n", reta_size, tbl_size);
1316 for (idx = 0, i = 0; i < reta_size; i++) {
1317 idx = i / RTE_RETA_GROUP_SIZE;
1318 sft = i % RTE_RETA_GROUP_SIZE;
1320 if (reta_conf[idx].mask & (1ULL << sft)) {
1323 if (BNXT_CHIP_THOR(bp))
1324 qid = bnxt_rss_to_qid(bp,
1325 vnic->rss_table[i * 2]);
1327 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1329 if (qid == INVALID_HW_RING_ID) {
1330 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1333 reta_conf[idx].reta[sft] = qid;
1340 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1341 struct rte_eth_rss_conf *rss_conf)
1343 struct bnxt *bp = eth_dev->data->dev_private;
1344 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1345 struct bnxt_vnic_info *vnic;
1346 uint16_t hash_type = 0;
1350 rc = is_bnxt_in_error(bp);
1355 * If RSS enablement were different than dev_configure,
1356 * then return -EINVAL
1358 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1359 if (!rss_conf->rss_hf)
1360 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1362 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1366 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1367 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1369 if (rss_conf->rss_hf & ETH_RSS_IPV4)
1370 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1371 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1372 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1373 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1374 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1375 if (rss_conf->rss_hf & ETH_RSS_IPV6)
1376 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1377 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1378 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1379 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1380 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1382 /* Update the RSS VNIC(s) */
1383 for (i = 0; i < bp->nr_vnics; i++) {
1384 vnic = &bp->vnic_info[i];
1385 vnic->hash_type = hash_type;
1388 * Use the supplied key if the key length is
1389 * acceptable and the rss_key is not NULL
1391 if (rss_conf->rss_key &&
1392 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1393 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1394 rss_conf->rss_key_len);
1396 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1401 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1402 struct rte_eth_rss_conf *rss_conf)
1404 struct bnxt *bp = eth_dev->data->dev_private;
1405 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1407 uint32_t hash_types;
1409 rc = is_bnxt_in_error(bp);
1413 /* RSS configuration is the same for all VNICs */
1414 if (vnic && vnic->rss_hash_key) {
1415 if (rss_conf->rss_key) {
1416 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1417 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1418 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1421 hash_types = vnic->hash_type;
1422 rss_conf->rss_hf = 0;
1423 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1424 rss_conf->rss_hf |= ETH_RSS_IPV4;
1425 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1427 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1428 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1430 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1432 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1433 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1435 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1437 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1438 rss_conf->rss_hf |= ETH_RSS_IPV6;
1439 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1441 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1442 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1444 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1446 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1447 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1449 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1453 "Unknwon RSS config from firmware (%08x), RSS disabled",
1458 rss_conf->rss_hf = 0;
1463 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1464 struct rte_eth_fc_conf *fc_conf)
1466 struct bnxt *bp = dev->data->dev_private;
1467 struct rte_eth_link link_info;
1470 rc = is_bnxt_in_error(bp);
1474 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1478 memset(fc_conf, 0, sizeof(*fc_conf));
1479 if (bp->link_info.auto_pause)
1480 fc_conf->autoneg = 1;
1481 switch (bp->link_info.pause) {
1483 fc_conf->mode = RTE_FC_NONE;
1485 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1486 fc_conf->mode = RTE_FC_TX_PAUSE;
1488 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1489 fc_conf->mode = RTE_FC_RX_PAUSE;
1491 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1492 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1493 fc_conf->mode = RTE_FC_FULL;
1499 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1500 struct rte_eth_fc_conf *fc_conf)
1502 struct bnxt *bp = dev->data->dev_private;
1505 rc = is_bnxt_in_error(bp);
1509 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1510 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1514 switch (fc_conf->mode) {
1516 bp->link_info.auto_pause = 0;
1517 bp->link_info.force_pause = 0;
1519 case RTE_FC_RX_PAUSE:
1520 if (fc_conf->autoneg) {
1521 bp->link_info.auto_pause =
1522 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1523 bp->link_info.force_pause = 0;
1525 bp->link_info.auto_pause = 0;
1526 bp->link_info.force_pause =
1527 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1530 case RTE_FC_TX_PAUSE:
1531 if (fc_conf->autoneg) {
1532 bp->link_info.auto_pause =
1533 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1534 bp->link_info.force_pause = 0;
1536 bp->link_info.auto_pause = 0;
1537 bp->link_info.force_pause =
1538 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1542 if (fc_conf->autoneg) {
1543 bp->link_info.auto_pause =
1544 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1545 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1546 bp->link_info.force_pause = 0;
1548 bp->link_info.auto_pause = 0;
1549 bp->link_info.force_pause =
1550 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1551 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1555 return bnxt_set_hwrm_link_config(bp, true);
1558 /* Add UDP tunneling port */
1560 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1561 struct rte_eth_udp_tunnel *udp_tunnel)
1563 struct bnxt *bp = eth_dev->data->dev_private;
1564 uint16_t tunnel_type = 0;
1567 rc = is_bnxt_in_error(bp);
1571 switch (udp_tunnel->prot_type) {
1572 case RTE_TUNNEL_TYPE_VXLAN:
1573 if (bp->vxlan_port_cnt) {
1574 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1575 udp_tunnel->udp_port);
1576 if (bp->vxlan_port != udp_tunnel->udp_port) {
1577 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1580 bp->vxlan_port_cnt++;
1584 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1585 bp->vxlan_port_cnt++;
1587 case RTE_TUNNEL_TYPE_GENEVE:
1588 if (bp->geneve_port_cnt) {
1589 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1590 udp_tunnel->udp_port);
1591 if (bp->geneve_port != udp_tunnel->udp_port) {
1592 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1595 bp->geneve_port_cnt++;
1599 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1600 bp->geneve_port_cnt++;
1603 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1606 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1612 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1613 struct rte_eth_udp_tunnel *udp_tunnel)
1615 struct bnxt *bp = eth_dev->data->dev_private;
1616 uint16_t tunnel_type = 0;
1620 rc = is_bnxt_in_error(bp);
1624 switch (udp_tunnel->prot_type) {
1625 case RTE_TUNNEL_TYPE_VXLAN:
1626 if (!bp->vxlan_port_cnt) {
1627 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1630 if (bp->vxlan_port != udp_tunnel->udp_port) {
1631 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1632 udp_tunnel->udp_port, bp->vxlan_port);
1635 if (--bp->vxlan_port_cnt)
1639 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1640 port = bp->vxlan_fw_dst_port_id;
1642 case RTE_TUNNEL_TYPE_GENEVE:
1643 if (!bp->geneve_port_cnt) {
1644 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1647 if (bp->geneve_port != udp_tunnel->udp_port) {
1648 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1649 udp_tunnel->udp_port, bp->geneve_port);
1652 if (--bp->geneve_port_cnt)
1656 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1657 port = bp->geneve_fw_dst_port_id;
1660 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1664 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1667 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1670 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1671 bp->geneve_port = 0;
1676 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1678 struct bnxt_filter_info *filter;
1679 struct bnxt_vnic_info *vnic;
1681 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1683 /* if VLAN exists && VLAN matches vlan_id
1684 * remove the MAC+VLAN filter
1685 * add a new MAC only filter
1687 * VLAN filter doesn't exist, just skip and continue
1689 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1690 filter = STAILQ_FIRST(&vnic->filter);
1692 /* Search for this matching MAC+VLAN filter */
1693 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1694 !memcmp(filter->l2_addr,
1696 RTE_ETHER_ADDR_LEN)) {
1697 /* Delete the filter */
1698 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1701 STAILQ_REMOVE(&vnic->filter, filter,
1702 bnxt_filter_info, next);
1703 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1706 "Del Vlan filter for %d\n",
1710 filter = STAILQ_NEXT(filter, next);
1715 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1717 struct bnxt_filter_info *filter;
1718 struct bnxt_vnic_info *vnic;
1720 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1721 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1722 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1724 /* Implementation notes on the use of VNIC in this command:
1726 * By default, these filters belong to default vnic for the function.
1727 * Once these filters are set up, only destination VNIC can be modified.
1728 * If the destination VNIC is not specified in this command,
1729 * then the HWRM shall only create an l2 context id.
1732 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1733 filter = STAILQ_FIRST(&vnic->filter);
1734 /* Check if the VLAN has already been added */
1736 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1737 !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN))
1740 filter = STAILQ_NEXT(filter, next);
1743 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1744 * command to create MAC+VLAN filter with the right flags, enables set.
1746 filter = bnxt_alloc_filter(bp);
1749 "MAC/VLAN filter alloc failed\n");
1752 /* MAC + VLAN ID filter */
1753 filter->l2_ivlan = vlan_id;
1754 filter->l2_ivlan_mask = 0x0FFF;
1755 filter->enables |= en;
1756 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1758 /* Free the newly allocated filter as we were
1759 * not able to create the filter in hardware.
1761 filter->fw_l2_filter_id = UINT64_MAX;
1762 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1766 /* Add this new filter to the list */
1767 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1769 "Added Vlan filter for %d\n", vlan_id);
1773 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1774 uint16_t vlan_id, int on)
1776 struct bnxt *bp = eth_dev->data->dev_private;
1779 rc = is_bnxt_in_error(bp);
1783 /* These operations apply to ALL existing MAC/VLAN filters */
1785 return bnxt_add_vlan_filter(bp, vlan_id);
1787 return bnxt_del_vlan_filter(bp, vlan_id);
1791 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1793 struct bnxt *bp = dev->data->dev_private;
1794 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1798 rc = is_bnxt_in_error(bp);
1802 if (mask & ETH_VLAN_FILTER_MASK) {
1803 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1804 /* Remove any VLAN filters programmed */
1805 for (i = 0; i < 4095; i++)
1806 bnxt_del_vlan_filter(bp, i);
1808 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1809 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1812 if (mask & ETH_VLAN_STRIP_MASK) {
1813 /* Enable or disable VLAN stripping */
1814 for (i = 0; i < bp->nr_vnics; i++) {
1815 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1816 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1817 vnic->vlan_strip = true;
1819 vnic->vlan_strip = false;
1820 bnxt_hwrm_vnic_cfg(bp, vnic);
1822 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1823 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1826 if (mask & ETH_VLAN_EXTEND_MASK)
1827 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1833 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1834 struct rte_ether_addr *addr)
1836 struct bnxt *bp = dev->data->dev_private;
1837 /* Default Filter is tied to VNIC 0 */
1838 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1839 struct bnxt_filter_info *filter;
1842 rc = is_bnxt_in_error(bp);
1846 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1849 if (rte_is_zero_ether_addr(addr))
1852 STAILQ_FOREACH(filter, &vnic->filter, next) {
1853 /* Default Filter is at Index 0 */
1854 if (filter->mac_index != 0)
1857 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1858 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1859 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1861 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1862 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1864 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1868 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1869 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1877 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1878 struct rte_ether_addr *mc_addr_set,
1879 uint32_t nb_mc_addr)
1881 struct bnxt *bp = eth_dev->data->dev_private;
1882 char *mc_addr_list = (char *)mc_addr_set;
1883 struct bnxt_vnic_info *vnic;
1884 uint32_t off = 0, i = 0;
1887 rc = is_bnxt_in_error(bp);
1891 vnic = &bp->vnic_info[0];
1893 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1894 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1898 /* TODO Check for Duplicate mcast addresses */
1899 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1900 for (i = 0; i < nb_mc_addr; i++) {
1901 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1902 RTE_ETHER_ADDR_LEN);
1903 off += RTE_ETHER_ADDR_LEN;
1906 vnic->mc_addr_cnt = i;
1909 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1913 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1915 struct bnxt *bp = dev->data->dev_private;
1916 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1917 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1918 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1921 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1922 fw_major, fw_minor, fw_updt);
1924 ret += 1; /* add the size of '\0' */
1925 if (fw_size < (uint32_t)ret)
1932 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1933 struct rte_eth_rxq_info *qinfo)
1935 struct bnxt_rx_queue *rxq;
1937 rxq = dev->data->rx_queues[queue_id];
1939 qinfo->mp = rxq->mb_pool;
1940 qinfo->scattered_rx = dev->data->scattered_rx;
1941 qinfo->nb_desc = rxq->nb_rx_desc;
1943 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1944 qinfo->conf.rx_drop_en = 0;
1945 qinfo->conf.rx_deferred_start = 0;
1949 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1950 struct rte_eth_txq_info *qinfo)
1952 struct bnxt_tx_queue *txq;
1954 txq = dev->data->tx_queues[queue_id];
1956 qinfo->nb_desc = txq->nb_tx_desc;
1958 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1959 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1960 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1962 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1963 qinfo->conf.tx_rs_thresh = 0;
1964 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1967 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1969 struct bnxt *bp = eth_dev->data->dev_private;
1970 struct rte_eth_dev_info dev_info;
1971 uint32_t new_pkt_size;
1975 rc = is_bnxt_in_error(bp);
1979 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1980 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1982 rc = bnxt_dev_info_get_op(eth_dev, &dev_info);
1984 PMD_DRV_LOG(ERR, "Error during getting ethernet device info\n");
1988 if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1989 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1990 RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1996 * If vector-mode tx/rx is active, disallow any MTU change that would
1997 * require scattered receive support.
1999 if (eth_dev->data->dev_started &&
2000 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2001 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2003 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2005 "MTU change would require scattered rx support. ");
2006 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2011 if (new_mtu > RTE_ETHER_MTU) {
2012 bp->flags |= BNXT_FLAG_JUMBO;
2013 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2014 DEV_RX_OFFLOAD_JUMBO_FRAME;
2016 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2017 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2018 bp->flags &= ~BNXT_FLAG_JUMBO;
2021 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2023 eth_dev->data->mtu = new_mtu;
2024 PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
2026 for (i = 0; i < bp->nr_vnics; i++) {
2027 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2030 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
2031 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
2032 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2036 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2037 size -= RTE_PKTMBUF_HEADROOM;
2039 if (size < new_mtu) {
2040 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2050 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2052 struct bnxt *bp = dev->data->dev_private;
2053 uint16_t vlan = bp->vlan;
2056 rc = is_bnxt_in_error(bp);
2060 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2062 "PVID cannot be modified for this function\n");
2065 bp->vlan = on ? pvid : 0;
2067 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2074 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2076 struct bnxt *bp = dev->data->dev_private;
2079 rc = is_bnxt_in_error(bp);
2083 return bnxt_hwrm_port_led_cfg(bp, true);
2087 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2089 struct bnxt *bp = dev->data->dev_private;
2092 rc = is_bnxt_in_error(bp);
2096 return bnxt_hwrm_port_led_cfg(bp, false);
2100 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2102 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2103 uint32_t desc = 0, raw_cons = 0, cons;
2104 struct bnxt_cp_ring_info *cpr;
2105 struct bnxt_rx_queue *rxq;
2106 struct rx_pkt_cmpl *rxcmp;
2112 rc = is_bnxt_in_error(bp);
2116 rxq = dev->data->rx_queues[rx_queue_id];
2120 while (raw_cons < rxq->nb_rx_desc) {
2121 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2122 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2124 if (!CMPL_VALID(rxcmp, valid))
2126 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
2127 cmp_type = CMP_TYPE(rxcmp);
2128 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
2129 cmp = (rte_le_to_cpu_32(
2130 ((struct rx_tpa_end_cmpl *)
2131 (rxcmp))->agg_bufs_v1) &
2132 RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
2133 RX_TPA_END_CMPL_AGG_BUFS_SFT;
2135 } else if (cmp_type == 0x11) {
2137 cmp = (rxcmp->agg_bufs_v1 &
2138 RX_PKT_CMPL_AGG_BUFS_MASK) >>
2139 RX_PKT_CMPL_AGG_BUFS_SFT;
2144 raw_cons += cmp ? cmp : 2;
2151 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2153 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2154 struct bnxt_rx_ring_info *rxr;
2155 struct bnxt_cp_ring_info *cpr;
2156 struct bnxt_sw_rx_bd *rx_buf;
2157 struct rx_pkt_cmpl *rxcmp;
2158 uint32_t cons, cp_cons;
2164 rc = is_bnxt_in_error(rxq->bp);
2171 if (offset >= rxq->nb_rx_desc)
2174 cons = RING_CMP(cpr->cp_ring_struct, offset);
2175 cp_cons = cpr->cp_raw_cons;
2176 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2178 if (cons > cp_cons) {
2179 if (CMPL_VALID(rxcmp, cpr->valid))
2180 return RTE_ETH_RX_DESC_DONE;
2182 if (CMPL_VALID(rxcmp, !cpr->valid))
2183 return RTE_ETH_RX_DESC_DONE;
2185 rx_buf = &rxr->rx_buf_ring[cons];
2186 if (rx_buf->mbuf == NULL)
2187 return RTE_ETH_RX_DESC_UNAVAIL;
2190 return RTE_ETH_RX_DESC_AVAIL;
2194 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2196 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2197 struct bnxt_tx_ring_info *txr;
2198 struct bnxt_cp_ring_info *cpr;
2199 struct bnxt_sw_tx_bd *tx_buf;
2200 struct tx_pkt_cmpl *txcmp;
2201 uint32_t cons, cp_cons;
2207 rc = is_bnxt_in_error(txq->bp);
2214 if (offset >= txq->nb_tx_desc)
2217 cons = RING_CMP(cpr->cp_ring_struct, offset);
2218 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2219 cp_cons = cpr->cp_raw_cons;
2221 if (cons > cp_cons) {
2222 if (CMPL_VALID(txcmp, cpr->valid))
2223 return RTE_ETH_TX_DESC_UNAVAIL;
2225 if (CMPL_VALID(txcmp, !cpr->valid))
2226 return RTE_ETH_TX_DESC_UNAVAIL;
2228 tx_buf = &txr->tx_buf_ring[cons];
2229 if (tx_buf->mbuf == NULL)
2230 return RTE_ETH_TX_DESC_DONE;
2232 return RTE_ETH_TX_DESC_FULL;
2235 static struct bnxt_filter_info *
2236 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2237 struct rte_eth_ethertype_filter *efilter,
2238 struct bnxt_vnic_info *vnic0,
2239 struct bnxt_vnic_info *vnic,
2242 struct bnxt_filter_info *mfilter = NULL;
2246 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2247 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2248 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2249 " ethertype filter.", efilter->ether_type);
2253 if (efilter->queue >= bp->rx_nr_rings) {
2254 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2259 vnic0 = &bp->vnic_info[0];
2260 vnic = &bp->vnic_info[efilter->queue];
2262 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2267 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2268 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2269 if ((!memcmp(efilter->mac_addr.addr_bytes,
2270 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2272 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2273 mfilter->ethertype == efilter->ether_type)) {
2279 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2280 if ((!memcmp(efilter->mac_addr.addr_bytes,
2281 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2282 mfilter->ethertype == efilter->ether_type &&
2284 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2298 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2299 enum rte_filter_op filter_op,
2302 struct bnxt *bp = dev->data->dev_private;
2303 struct rte_eth_ethertype_filter *efilter =
2304 (struct rte_eth_ethertype_filter *)arg;
2305 struct bnxt_filter_info *bfilter, *filter1;
2306 struct bnxt_vnic_info *vnic, *vnic0;
2309 if (filter_op == RTE_ETH_FILTER_NOP)
2313 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2318 vnic0 = &bp->vnic_info[0];
2319 vnic = &bp->vnic_info[efilter->queue];
2321 switch (filter_op) {
2322 case RTE_ETH_FILTER_ADD:
2323 bnxt_match_and_validate_ether_filter(bp, efilter,
2328 bfilter = bnxt_get_unused_filter(bp);
2329 if (bfilter == NULL) {
2331 "Not enough resources for a new filter.\n");
2334 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2335 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2336 RTE_ETHER_ADDR_LEN);
2337 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2338 RTE_ETHER_ADDR_LEN);
2339 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2340 bfilter->ethertype = efilter->ether_type;
2341 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2343 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2344 if (filter1 == NULL) {
2349 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2350 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2352 bfilter->dst_id = vnic->fw_vnic_id;
2354 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2356 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2359 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2362 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2364 case RTE_ETH_FILTER_DELETE:
2365 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2367 if (ret == -EEXIST) {
2368 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2370 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2372 bnxt_free_filter(bp, filter1);
2373 } else if (ret == 0) {
2374 PMD_DRV_LOG(ERR, "No matching filter found\n");
2378 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2384 bnxt_free_filter(bp, bfilter);
2390 parse_ntuple_filter(struct bnxt *bp,
2391 struct rte_eth_ntuple_filter *nfilter,
2392 struct bnxt_filter_info *bfilter)
2396 if (nfilter->queue >= bp->rx_nr_rings) {
2397 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2401 switch (nfilter->dst_port_mask) {
2403 bfilter->dst_port_mask = -1;
2404 bfilter->dst_port = nfilter->dst_port;
2405 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2406 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2409 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2413 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2414 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2416 switch (nfilter->proto_mask) {
2418 if (nfilter->proto == 17) /* IPPROTO_UDP */
2419 bfilter->ip_protocol = 17;
2420 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2421 bfilter->ip_protocol = 6;
2424 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2427 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2431 switch (nfilter->dst_ip_mask) {
2433 bfilter->dst_ipaddr_mask[0] = -1;
2434 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2435 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2436 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2439 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2443 switch (nfilter->src_ip_mask) {
2445 bfilter->src_ipaddr_mask[0] = -1;
2446 bfilter->src_ipaddr[0] = nfilter->src_ip;
2447 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2448 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2451 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2455 switch (nfilter->src_port_mask) {
2457 bfilter->src_port_mask = -1;
2458 bfilter->src_port = nfilter->src_port;
2459 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2460 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2463 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2468 //nfilter->priority = (uint8_t)filter->priority;
2470 bfilter->enables = en;
2474 static struct bnxt_filter_info*
2475 bnxt_match_ntuple_filter(struct bnxt *bp,
2476 struct bnxt_filter_info *bfilter,
2477 struct bnxt_vnic_info **mvnic)
2479 struct bnxt_filter_info *mfilter = NULL;
2482 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2483 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2484 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2485 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2486 bfilter->src_ipaddr_mask[0] ==
2487 mfilter->src_ipaddr_mask[0] &&
2488 bfilter->src_port == mfilter->src_port &&
2489 bfilter->src_port_mask == mfilter->src_port_mask &&
2490 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2491 bfilter->dst_ipaddr_mask[0] ==
2492 mfilter->dst_ipaddr_mask[0] &&
2493 bfilter->dst_port == mfilter->dst_port &&
2494 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2495 bfilter->flags == mfilter->flags &&
2496 bfilter->enables == mfilter->enables) {
2507 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2508 struct rte_eth_ntuple_filter *nfilter,
2509 enum rte_filter_op filter_op)
2511 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2512 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2515 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2516 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2520 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2521 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2525 bfilter = bnxt_get_unused_filter(bp);
2526 if (bfilter == NULL) {
2528 "Not enough resources for a new filter.\n");
2531 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2535 vnic = &bp->vnic_info[nfilter->queue];
2536 vnic0 = &bp->vnic_info[0];
2537 filter1 = STAILQ_FIRST(&vnic0->filter);
2538 if (filter1 == NULL) {
2543 bfilter->dst_id = vnic->fw_vnic_id;
2544 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2546 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2547 bfilter->ethertype = 0x800;
2548 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2550 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2552 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2553 bfilter->dst_id == mfilter->dst_id) {
2554 PMD_DRV_LOG(ERR, "filter exists.\n");
2557 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2558 bfilter->dst_id != mfilter->dst_id) {
2559 mfilter->dst_id = vnic->fw_vnic_id;
2560 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2561 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2562 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2563 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2564 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2567 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2568 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2573 if (filter_op == RTE_ETH_FILTER_ADD) {
2574 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2575 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2578 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2580 if (mfilter == NULL) {
2581 /* This should not happen. But for Coverity! */
2585 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2587 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2588 bnxt_free_filter(bp, mfilter);
2589 mfilter->fw_l2_filter_id = -1;
2590 bnxt_free_filter(bp, bfilter);
2591 bfilter->fw_l2_filter_id = -1;
2596 bfilter->fw_l2_filter_id = -1;
2597 bnxt_free_filter(bp, bfilter);
2602 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2603 enum rte_filter_op filter_op,
2606 struct bnxt *bp = dev->data->dev_private;
2609 if (filter_op == RTE_ETH_FILTER_NOP)
2613 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2618 switch (filter_op) {
2619 case RTE_ETH_FILTER_ADD:
2620 ret = bnxt_cfg_ntuple_filter(bp,
2621 (struct rte_eth_ntuple_filter *)arg,
2624 case RTE_ETH_FILTER_DELETE:
2625 ret = bnxt_cfg_ntuple_filter(bp,
2626 (struct rte_eth_ntuple_filter *)arg,
2630 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2638 bnxt_parse_fdir_filter(struct bnxt *bp,
2639 struct rte_eth_fdir_filter *fdir,
2640 struct bnxt_filter_info *filter)
2642 enum rte_fdir_mode fdir_mode =
2643 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2644 struct bnxt_vnic_info *vnic0, *vnic;
2645 struct bnxt_filter_info *filter1;
2649 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2652 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2653 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2655 switch (fdir->input.flow_type) {
2656 case RTE_ETH_FLOW_IPV4:
2657 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2659 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2660 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2661 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2662 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2663 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2664 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2665 filter->ip_addr_type =
2666 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2667 filter->src_ipaddr_mask[0] = 0xffffffff;
2668 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2669 filter->dst_ipaddr_mask[0] = 0xffffffff;
2670 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2671 filter->ethertype = 0x800;
2672 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2674 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2675 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2676 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2677 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2678 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2679 filter->dst_port_mask = 0xffff;
2680 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2681 filter->src_port_mask = 0xffff;
2682 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2683 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2684 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2685 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2686 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2687 filter->ip_protocol = 6;
2688 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2689 filter->ip_addr_type =
2690 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2691 filter->src_ipaddr_mask[0] = 0xffffffff;
2692 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2693 filter->dst_ipaddr_mask[0] = 0xffffffff;
2694 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2695 filter->ethertype = 0x800;
2696 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2698 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2699 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2700 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2701 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2702 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2703 filter->dst_port_mask = 0xffff;
2704 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2705 filter->src_port_mask = 0xffff;
2706 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2707 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2708 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2709 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2710 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2711 filter->ip_protocol = 17;
2712 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2713 filter->ip_addr_type =
2714 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2715 filter->src_ipaddr_mask[0] = 0xffffffff;
2716 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2717 filter->dst_ipaddr_mask[0] = 0xffffffff;
2718 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2719 filter->ethertype = 0x800;
2720 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2722 case RTE_ETH_FLOW_IPV6:
2723 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2725 filter->ip_addr_type =
2726 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2727 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2728 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2729 rte_memcpy(filter->src_ipaddr,
2730 fdir->input.flow.ipv6_flow.src_ip, 16);
2731 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2732 rte_memcpy(filter->dst_ipaddr,
2733 fdir->input.flow.ipv6_flow.dst_ip, 16);
2734 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2735 memset(filter->dst_ipaddr_mask, 0xff, 16);
2736 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2737 memset(filter->src_ipaddr_mask, 0xff, 16);
2738 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2739 filter->ethertype = 0x86dd;
2740 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2742 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2743 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2744 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2745 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2746 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2747 filter->dst_port_mask = 0xffff;
2748 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2749 filter->src_port_mask = 0xffff;
2750 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2751 filter->ip_addr_type =
2752 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2753 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2754 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2755 rte_memcpy(filter->src_ipaddr,
2756 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2757 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2758 rte_memcpy(filter->dst_ipaddr,
2759 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2760 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2761 memset(filter->dst_ipaddr_mask, 0xff, 16);
2762 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2763 memset(filter->src_ipaddr_mask, 0xff, 16);
2764 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2765 filter->ethertype = 0x86dd;
2766 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2768 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2769 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2770 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2771 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2772 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2773 filter->dst_port_mask = 0xffff;
2774 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2775 filter->src_port_mask = 0xffff;
2776 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2777 filter->ip_addr_type =
2778 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2779 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2780 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2781 rte_memcpy(filter->src_ipaddr,
2782 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2783 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2784 rte_memcpy(filter->dst_ipaddr,
2785 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2786 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2787 memset(filter->dst_ipaddr_mask, 0xff, 16);
2788 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2789 memset(filter->src_ipaddr_mask, 0xff, 16);
2790 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2791 filter->ethertype = 0x86dd;
2792 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2794 case RTE_ETH_FLOW_L2_PAYLOAD:
2795 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2796 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2798 case RTE_ETH_FLOW_VXLAN:
2799 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2801 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2802 filter->tunnel_type =
2803 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2804 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2806 case RTE_ETH_FLOW_NVGRE:
2807 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2809 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2810 filter->tunnel_type =
2811 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2812 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2814 case RTE_ETH_FLOW_UNKNOWN:
2815 case RTE_ETH_FLOW_RAW:
2816 case RTE_ETH_FLOW_FRAG_IPV4:
2817 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2818 case RTE_ETH_FLOW_FRAG_IPV6:
2819 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2820 case RTE_ETH_FLOW_IPV6_EX:
2821 case RTE_ETH_FLOW_IPV6_TCP_EX:
2822 case RTE_ETH_FLOW_IPV6_UDP_EX:
2823 case RTE_ETH_FLOW_GENEVE:
2829 vnic0 = &bp->vnic_info[0];
2830 vnic = &bp->vnic_info[fdir->action.rx_queue];
2832 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2837 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2838 rte_memcpy(filter->dst_macaddr,
2839 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2840 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2843 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2844 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2845 filter1 = STAILQ_FIRST(&vnic0->filter);
2846 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2848 filter->dst_id = vnic->fw_vnic_id;
2849 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2850 if (filter->dst_macaddr[i] == 0x00)
2851 filter1 = STAILQ_FIRST(&vnic0->filter);
2853 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2856 if (filter1 == NULL)
2859 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2860 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2862 filter->enables = en;
2867 static struct bnxt_filter_info *
2868 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2869 struct bnxt_vnic_info **mvnic)
2871 struct bnxt_filter_info *mf = NULL;
2874 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2875 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2877 STAILQ_FOREACH(mf, &vnic->filter, next) {
2878 if (mf->filter_type == nf->filter_type &&
2879 mf->flags == nf->flags &&
2880 mf->src_port == nf->src_port &&
2881 mf->src_port_mask == nf->src_port_mask &&
2882 mf->dst_port == nf->dst_port &&
2883 mf->dst_port_mask == nf->dst_port_mask &&
2884 mf->ip_protocol == nf->ip_protocol &&
2885 mf->ip_addr_type == nf->ip_addr_type &&
2886 mf->ethertype == nf->ethertype &&
2887 mf->vni == nf->vni &&
2888 mf->tunnel_type == nf->tunnel_type &&
2889 mf->l2_ovlan == nf->l2_ovlan &&
2890 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2891 mf->l2_ivlan == nf->l2_ivlan &&
2892 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2893 !memcmp(mf->l2_addr, nf->l2_addr,
2894 RTE_ETHER_ADDR_LEN) &&
2895 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2896 RTE_ETHER_ADDR_LEN) &&
2897 !memcmp(mf->src_macaddr, nf->src_macaddr,
2898 RTE_ETHER_ADDR_LEN) &&
2899 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2900 RTE_ETHER_ADDR_LEN) &&
2901 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2902 sizeof(nf->src_ipaddr)) &&
2903 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2904 sizeof(nf->src_ipaddr_mask)) &&
2905 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2906 sizeof(nf->dst_ipaddr)) &&
2907 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2908 sizeof(nf->dst_ipaddr_mask))) {
2919 bnxt_fdir_filter(struct rte_eth_dev *dev,
2920 enum rte_filter_op filter_op,
2923 struct bnxt *bp = dev->data->dev_private;
2924 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2925 struct bnxt_filter_info *filter, *match;
2926 struct bnxt_vnic_info *vnic, *mvnic;
2929 if (filter_op == RTE_ETH_FILTER_NOP)
2932 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2935 switch (filter_op) {
2936 case RTE_ETH_FILTER_ADD:
2937 case RTE_ETH_FILTER_DELETE:
2939 filter = bnxt_get_unused_filter(bp);
2940 if (filter == NULL) {
2942 "Not enough resources for a new flow.\n");
2946 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2949 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2951 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2952 vnic = &bp->vnic_info[0];
2954 vnic = &bp->vnic_info[fdir->action.rx_queue];
2956 match = bnxt_match_fdir(bp, filter, &mvnic);
2957 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2958 if (match->dst_id == vnic->fw_vnic_id) {
2959 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2963 match->dst_id = vnic->fw_vnic_id;
2964 ret = bnxt_hwrm_set_ntuple_filter(bp,
2967 STAILQ_REMOVE(&mvnic->filter, match,
2968 bnxt_filter_info, next);
2969 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2971 "Filter with matching pattern exist\n");
2973 "Updated it to new destination q\n");
2977 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2978 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2983 if (filter_op == RTE_ETH_FILTER_ADD) {
2984 ret = bnxt_hwrm_set_ntuple_filter(bp,
2989 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2991 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2992 STAILQ_REMOVE(&vnic->filter, match,
2993 bnxt_filter_info, next);
2994 bnxt_free_filter(bp, match);
2995 filter->fw_l2_filter_id = -1;
2996 bnxt_free_filter(bp, filter);
2999 case RTE_ETH_FILTER_FLUSH:
3000 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3001 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3003 STAILQ_FOREACH(filter, &vnic->filter, next) {
3004 if (filter->filter_type ==
3005 HWRM_CFA_NTUPLE_FILTER) {
3007 bnxt_hwrm_clear_ntuple_filter(bp,
3009 STAILQ_REMOVE(&vnic->filter, filter,
3010 bnxt_filter_info, next);
3015 case RTE_ETH_FILTER_UPDATE:
3016 case RTE_ETH_FILTER_STATS:
3017 case RTE_ETH_FILTER_INFO:
3018 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3021 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3028 filter->fw_l2_filter_id = -1;
3029 bnxt_free_filter(bp, filter);
3034 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3035 enum rte_filter_type filter_type,
3036 enum rte_filter_op filter_op, void *arg)
3040 ret = is_bnxt_in_error(dev->data->dev_private);
3044 switch (filter_type) {
3045 case RTE_ETH_FILTER_TUNNEL:
3047 "filter type: %d: To be implemented\n", filter_type);
3049 case RTE_ETH_FILTER_FDIR:
3050 ret = bnxt_fdir_filter(dev, filter_op, arg);
3052 case RTE_ETH_FILTER_NTUPLE:
3053 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3055 case RTE_ETH_FILTER_ETHERTYPE:
3056 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3058 case RTE_ETH_FILTER_GENERIC:
3059 if (filter_op != RTE_ETH_FILTER_GET)
3061 *(const void **)arg = &bnxt_flow_ops;
3065 "Filter type (%d) not supported", filter_type);
3072 static const uint32_t *
3073 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3075 static const uint32_t ptypes[] = {
3076 RTE_PTYPE_L2_ETHER_VLAN,
3077 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3078 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3082 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3083 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3084 RTE_PTYPE_INNER_L4_ICMP,
3085 RTE_PTYPE_INNER_L4_TCP,
3086 RTE_PTYPE_INNER_L4_UDP,
3090 if (!dev->rx_pkt_burst)
3096 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3099 uint32_t reg_base = *reg_arr & 0xfffff000;
3103 for (i = 0; i < count; i++) {
3104 if ((reg_arr[i] & 0xfffff000) != reg_base)
3107 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3108 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3112 static int bnxt_map_ptp_regs(struct bnxt *bp)
3114 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3118 reg_arr = ptp->rx_regs;
3119 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3123 reg_arr = ptp->tx_regs;
3124 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3128 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3129 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3131 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3132 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3137 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3139 rte_write32(0, (uint8_t *)bp->bar0 +
3140 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3141 rte_write32(0, (uint8_t *)bp->bar0 +
3142 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3145 static uint64_t bnxt_cc_read(struct bnxt *bp)
3149 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3150 BNXT_GRCPF_REG_SYNC_TIME));
3151 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3152 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3156 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3158 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3161 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3162 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3163 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3166 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3167 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3168 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3169 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3170 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3171 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3176 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3178 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3179 struct bnxt_pf_info *pf = &bp->pf;
3186 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3187 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3188 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3191 port_id = pf->port_id;
3192 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3193 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3195 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3196 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3197 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3198 /* bnxt_clr_rx_ts(bp); TBD */
3202 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3203 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3204 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3205 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3211 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3214 struct bnxt *bp = dev->data->dev_private;
3215 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3220 ns = rte_timespec_to_ns(ts);
3221 /* Set the timecounters to a new value. */
3228 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3230 struct bnxt *bp = dev->data->dev_private;
3231 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3232 uint64_t ns, systime_cycles = 0;
3238 if (BNXT_CHIP_THOR(bp))
3239 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3242 systime_cycles = bnxt_cc_read(bp);
3244 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3245 *ts = rte_ns_to_timespec(ns);
3250 bnxt_timesync_enable(struct rte_eth_dev *dev)
3252 struct bnxt *bp = dev->data->dev_private;
3253 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3261 ptp->tx_tstamp_en = 1;
3262 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3264 rc = bnxt_hwrm_ptp_cfg(bp);
3268 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3269 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3270 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3272 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3273 ptp->tc.cc_shift = shift;
3274 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3276 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3277 ptp->rx_tstamp_tc.cc_shift = shift;
3278 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3280 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3281 ptp->tx_tstamp_tc.cc_shift = shift;
3282 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3284 if (!BNXT_CHIP_THOR(bp))
3285 bnxt_map_ptp_regs(bp);
3291 bnxt_timesync_disable(struct rte_eth_dev *dev)
3293 struct bnxt *bp = dev->data->dev_private;
3294 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3300 ptp->tx_tstamp_en = 0;
3303 bnxt_hwrm_ptp_cfg(bp);
3305 if (!BNXT_CHIP_THOR(bp))
3306 bnxt_unmap_ptp_regs(bp);
3312 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3313 struct timespec *timestamp,
3314 uint32_t flags __rte_unused)
3316 struct bnxt *bp = dev->data->dev_private;
3317 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3318 uint64_t rx_tstamp_cycles = 0;
3324 if (BNXT_CHIP_THOR(bp))
3325 rx_tstamp_cycles = ptp->rx_timestamp;
3327 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3329 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3330 *timestamp = rte_ns_to_timespec(ns);
3335 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3336 struct timespec *timestamp)
3338 struct bnxt *bp = dev->data->dev_private;
3339 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3340 uint64_t tx_tstamp_cycles = 0;
3347 if (BNXT_CHIP_THOR(bp))
3348 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3351 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3353 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3354 *timestamp = rte_ns_to_timespec(ns);
3360 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3362 struct bnxt *bp = dev->data->dev_private;
3363 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3368 ptp->tc.nsec += delta;
3374 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3376 struct bnxt *bp = dev->data->dev_private;
3378 uint32_t dir_entries;
3379 uint32_t entry_length;
3381 rc = is_bnxt_in_error(bp);
3385 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3386 bp->pdev->addr.domain, bp->pdev->addr.bus,
3387 bp->pdev->addr.devid, bp->pdev->addr.function);
3389 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3393 return dir_entries * entry_length;
3397 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3398 struct rte_dev_eeprom_info *in_eeprom)
3400 struct bnxt *bp = dev->data->dev_private;
3405 rc = is_bnxt_in_error(bp);
3409 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3410 "len = %d\n", bp->pdev->addr.domain,
3411 bp->pdev->addr.bus, bp->pdev->addr.devid,
3412 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3414 if (in_eeprom->offset == 0) /* special offset value to get directory */
3415 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3418 index = in_eeprom->offset >> 24;
3419 offset = in_eeprom->offset & 0xffffff;
3422 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3423 in_eeprom->length, in_eeprom->data);
3428 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3431 case BNX_DIR_TYPE_CHIMP_PATCH:
3432 case BNX_DIR_TYPE_BOOTCODE:
3433 case BNX_DIR_TYPE_BOOTCODE_2:
3434 case BNX_DIR_TYPE_APE_FW:
3435 case BNX_DIR_TYPE_APE_PATCH:
3436 case BNX_DIR_TYPE_KONG_FW:
3437 case BNX_DIR_TYPE_KONG_PATCH:
3438 case BNX_DIR_TYPE_BONO_FW:
3439 case BNX_DIR_TYPE_BONO_PATCH:
3447 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3450 case BNX_DIR_TYPE_AVS:
3451 case BNX_DIR_TYPE_EXP_ROM_MBA:
3452 case BNX_DIR_TYPE_PCIE:
3453 case BNX_DIR_TYPE_TSCF_UCODE:
3454 case BNX_DIR_TYPE_EXT_PHY:
3455 case BNX_DIR_TYPE_CCM:
3456 case BNX_DIR_TYPE_ISCSI_BOOT:
3457 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3458 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3466 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3468 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3469 bnxt_dir_type_is_other_exec_format(dir_type);
3473 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3474 struct rte_dev_eeprom_info *in_eeprom)
3476 struct bnxt *bp = dev->data->dev_private;
3477 uint8_t index, dir_op;
3478 uint16_t type, ext, ordinal, attr;
3481 rc = is_bnxt_in_error(bp);
3485 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3486 "len = %d\n", bp->pdev->addr.domain,
3487 bp->pdev->addr.bus, bp->pdev->addr.devid,
3488 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3491 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3495 type = in_eeprom->magic >> 16;
3497 if (type == 0xffff) { /* special value for directory operations */
3498 index = in_eeprom->magic & 0xff;
3499 dir_op = in_eeprom->magic >> 8;
3503 case 0x0e: /* erase */
3504 if (in_eeprom->offset != ~in_eeprom->magic)
3506 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3512 /* Create or re-write an NVM item: */
3513 if (bnxt_dir_type_is_executable(type) == true)
3515 ext = in_eeprom->magic & 0xffff;
3516 ordinal = in_eeprom->offset >> 16;
3517 attr = in_eeprom->offset & 0xffff;
3519 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3520 in_eeprom->data, in_eeprom->length);
3527 static const struct eth_dev_ops bnxt_dev_ops = {
3528 .dev_infos_get = bnxt_dev_info_get_op,
3529 .dev_close = bnxt_dev_close_op,
3530 .dev_configure = bnxt_dev_configure_op,
3531 .dev_start = bnxt_dev_start_op,
3532 .dev_stop = bnxt_dev_stop_op,
3533 .dev_set_link_up = bnxt_dev_set_link_up_op,
3534 .dev_set_link_down = bnxt_dev_set_link_down_op,
3535 .stats_get = bnxt_stats_get_op,
3536 .stats_reset = bnxt_stats_reset_op,
3537 .rx_queue_setup = bnxt_rx_queue_setup_op,
3538 .rx_queue_release = bnxt_rx_queue_release_op,
3539 .tx_queue_setup = bnxt_tx_queue_setup_op,
3540 .tx_queue_release = bnxt_tx_queue_release_op,
3541 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3542 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3543 .reta_update = bnxt_reta_update_op,
3544 .reta_query = bnxt_reta_query_op,
3545 .rss_hash_update = bnxt_rss_hash_update_op,
3546 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3547 .link_update = bnxt_link_update_op,
3548 .promiscuous_enable = bnxt_promiscuous_enable_op,
3549 .promiscuous_disable = bnxt_promiscuous_disable_op,
3550 .allmulticast_enable = bnxt_allmulticast_enable_op,
3551 .allmulticast_disable = bnxt_allmulticast_disable_op,
3552 .mac_addr_add = bnxt_mac_addr_add_op,
3553 .mac_addr_remove = bnxt_mac_addr_remove_op,
3554 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3555 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3556 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3557 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3558 .vlan_filter_set = bnxt_vlan_filter_set_op,
3559 .vlan_offload_set = bnxt_vlan_offload_set_op,
3560 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3561 .mtu_set = bnxt_mtu_set_op,
3562 .mac_addr_set = bnxt_set_default_mac_addr_op,
3563 .xstats_get = bnxt_dev_xstats_get_op,
3564 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3565 .xstats_reset = bnxt_dev_xstats_reset_op,
3566 .fw_version_get = bnxt_fw_version_get,
3567 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3568 .rxq_info_get = bnxt_rxq_info_get_op,
3569 .txq_info_get = bnxt_txq_info_get_op,
3570 .dev_led_on = bnxt_dev_led_on_op,
3571 .dev_led_off = bnxt_dev_led_off_op,
3572 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3573 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3574 .rx_queue_count = bnxt_rx_queue_count_op,
3575 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3576 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3577 .rx_queue_start = bnxt_rx_queue_start,
3578 .rx_queue_stop = bnxt_rx_queue_stop,
3579 .tx_queue_start = bnxt_tx_queue_start,
3580 .tx_queue_stop = bnxt_tx_queue_stop,
3581 .filter_ctrl = bnxt_filter_ctrl_op,
3582 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3583 .get_eeprom_length = bnxt_get_eeprom_length_op,
3584 .get_eeprom = bnxt_get_eeprom_op,
3585 .set_eeprom = bnxt_set_eeprom_op,
3586 .timesync_enable = bnxt_timesync_enable,
3587 .timesync_disable = bnxt_timesync_disable,
3588 .timesync_read_time = bnxt_timesync_read_time,
3589 .timesync_write_time = bnxt_timesync_write_time,
3590 .timesync_adjust_time = bnxt_timesync_adjust_time,
3591 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3592 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3595 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3599 /* Only pre-map the reset GRC registers using window 3 */
3600 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3601 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3603 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3608 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3610 struct bnxt_error_recovery_info *info = bp->recovery_info;
3611 uint32_t reg_base = 0xffffffff;
3614 /* Only pre-map the monitoring GRC registers using window 2 */
3615 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3616 uint32_t reg = info->status_regs[i];
3618 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3621 if (reg_base == 0xffffffff)
3622 reg_base = reg & 0xfffff000;
3623 if ((reg & 0xfffff000) != reg_base)
3626 /* Use mask 0xffc as the Lower 2 bits indicates
3627 * address space location
3629 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3633 if (reg_base == 0xffffffff)
3636 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3637 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3642 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3644 struct bnxt_error_recovery_info *info = bp->recovery_info;
3645 uint32_t delay = info->delay_after_reset[index];
3646 uint32_t val = info->reset_reg_val[index];
3647 uint32_t reg = info->reset_reg[index];
3648 uint32_t type, offset;
3650 type = BNXT_FW_STATUS_REG_TYPE(reg);
3651 offset = BNXT_FW_STATUS_REG_OFF(reg);
3654 case BNXT_FW_STATUS_REG_TYPE_CFG:
3655 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3657 case BNXT_FW_STATUS_REG_TYPE_GRC:
3658 offset = bnxt_map_reset_regs(bp, offset);
3659 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3661 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3662 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3665 /* wait on a specific interval of time until core reset is complete */
3667 rte_delay_ms(delay);
3670 static void bnxt_dev_cleanup(struct bnxt *bp)
3672 bnxt_set_hwrm_link_config(bp, false);
3673 bp->link_info.link_up = 0;
3674 if (bp->dev_stopped == 0)
3675 bnxt_dev_stop_op(bp->eth_dev);
3677 bnxt_uninit_resources(bp, true);
3680 static int bnxt_restore_filters(struct bnxt *bp)
3682 struct rte_eth_dev *dev = bp->eth_dev;
3685 if (dev->data->all_multicast)
3686 ret = bnxt_allmulticast_enable_op(dev);
3687 if (dev->data->promiscuous)
3688 ret = bnxt_promiscuous_enable_op(dev);
3690 /* TODO restore other filters as well */
3694 static void bnxt_dev_recover(void *arg)
3696 struct bnxt *bp = arg;
3697 int timeout = bp->fw_reset_max_msecs;
3700 /* Clear Error flag so that device re-init should happen */
3701 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3704 rc = bnxt_hwrm_ver_get(bp);
3707 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3708 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3709 } while (rc && timeout);
3712 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3716 rc = bnxt_init_resources(bp, true);
3719 "Failed to initialize resources after reset\n");
3722 /* clear reset flag as the device is initialized now */
3723 bp->flags &= ~BNXT_FLAG_FW_RESET;
3725 rc = bnxt_dev_start_op(bp->eth_dev);
3727 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3731 rc = bnxt_restore_filters(bp);
3735 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3738 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3739 bnxt_uninit_resources(bp, false);
3740 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3743 void bnxt_dev_reset_and_resume(void *arg)
3745 struct bnxt *bp = arg;
3748 bnxt_dev_cleanup(bp);
3750 bnxt_wait_for_device_shutdown(bp);
3752 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3753 bnxt_dev_recover, (void *)bp);
3755 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3758 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3760 struct bnxt_error_recovery_info *info = bp->recovery_info;
3761 uint32_t reg = info->status_regs[index];
3762 uint32_t type, offset, val = 0;
3764 type = BNXT_FW_STATUS_REG_TYPE(reg);
3765 offset = BNXT_FW_STATUS_REG_OFF(reg);
3768 case BNXT_FW_STATUS_REG_TYPE_CFG:
3769 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3771 case BNXT_FW_STATUS_REG_TYPE_GRC:
3772 offset = info->mapped_status_regs[index];
3774 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3775 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3783 static int bnxt_fw_reset_all(struct bnxt *bp)
3785 struct bnxt_error_recovery_info *info = bp->recovery_info;
3789 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3790 /* Reset through master function driver */
3791 for (i = 0; i < info->reg_array_cnt; i++)
3792 bnxt_write_fw_reset_reg(bp, i);
3793 /* Wait for time specified by FW after triggering reset */
3794 rte_delay_ms(info->master_func_wait_period_after_reset);
3795 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3796 /* Reset with the help of Kong processor */
3797 rc = bnxt_hwrm_fw_reset(bp);
3799 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3805 static void bnxt_fw_reset_cb(void *arg)
3807 struct bnxt *bp = arg;
3808 struct bnxt_error_recovery_info *info = bp->recovery_info;
3811 /* Only Master function can do FW reset */
3812 if (bnxt_is_master_func(bp) &&
3813 bnxt_is_recovery_enabled(bp)) {
3814 rc = bnxt_fw_reset_all(bp);
3816 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3821 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3822 * EXCEPTION_FATAL_ASYNC event to all the functions
3823 * (including MASTER FUNC). After receiving this Async, all the active
3824 * drivers should treat this case as FW initiated recovery
3826 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3827 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3828 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3830 /* To recover from error */
3831 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3836 /* Driver should poll FW heartbeat, reset_counter with the frequency
3837 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3838 * When the driver detects heartbeat stop or change in reset_counter,
3839 * it has to trigger a reset to recover from the error condition.
3840 * A “master PF” is the function who will have the privilege to
3841 * initiate the chimp reset. The master PF will be elected by the
3842 * firmware and will be notified through async message.
3844 static void bnxt_check_fw_health(void *arg)
3846 struct bnxt *bp = arg;
3847 struct bnxt_error_recovery_info *info = bp->recovery_info;
3848 uint32_t val = 0, wait_msec;
3850 if (!info || !bnxt_is_recovery_enabled(bp) ||
3851 is_bnxt_in_error(bp))
3854 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3855 if (val == info->last_heart_beat)
3858 info->last_heart_beat = val;
3860 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3861 if (val != info->last_reset_counter)
3864 info->last_reset_counter = val;
3866 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3867 bnxt_check_fw_health, (void *)bp);
3871 /* Stop DMA to/from device */
3872 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3873 bp->flags |= BNXT_FLAG_FW_RESET;
3875 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3877 if (bnxt_is_master_func(bp))
3878 wait_msec = info->master_func_wait_period;
3880 wait_msec = info->normal_func_wait_period;
3882 rte_eal_alarm_set(US_PER_MS * wait_msec,
3883 bnxt_fw_reset_cb, (void *)bp);
3886 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3888 uint32_t polling_freq;
3890 if (!bnxt_is_recovery_enabled(bp))
3893 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
3896 polling_freq = bp->recovery_info->driver_polling_freq;
3898 rte_eal_alarm_set(US_PER_MS * polling_freq,
3899 bnxt_check_fw_health, (void *)bp);
3900 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3903 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
3905 if (!bnxt_is_recovery_enabled(bp))
3908 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
3909 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3912 static bool bnxt_vf_pciid(uint16_t id)
3914 if (id == BROADCOM_DEV_ID_57304_VF ||
3915 id == BROADCOM_DEV_ID_57406_VF ||
3916 id == BROADCOM_DEV_ID_5731X_VF ||
3917 id == BROADCOM_DEV_ID_5741X_VF ||
3918 id == BROADCOM_DEV_ID_57414_VF ||
3919 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3920 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3921 id == BROADCOM_DEV_ID_58802_VF ||
3922 id == BROADCOM_DEV_ID_57500_VF1 ||
3923 id == BROADCOM_DEV_ID_57500_VF2)
3928 bool bnxt_stratus_device(struct bnxt *bp)
3930 uint16_t id = bp->pdev->id.device_id;
3932 if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3933 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3934 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3939 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3941 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3942 struct bnxt *bp = eth_dev->data->dev_private;
3944 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3945 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3946 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3947 if (!bp->bar0 || !bp->doorbell_base) {
3948 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
3952 bp->eth_dev = eth_dev;
3958 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3959 struct bnxt_ctx_pg_info *ctx_pg,
3964 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3965 const struct rte_memzone *mz = NULL;
3966 char mz_name[RTE_MEMZONE_NAMESIZE];
3967 rte_iova_t mz_phys_addr;
3968 uint64_t valid_bits = 0;
3975 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3977 rmem->page_size = BNXT_PAGE_SIZE;
3978 rmem->pg_arr = ctx_pg->ctx_pg_arr;
3979 rmem->dma_arr = ctx_pg->ctx_dma_arr;
3980 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3982 valid_bits = PTU_PTE_VALID;
3984 if (rmem->nr_pages > 1) {
3985 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3986 "bnxt_ctx_pg_tbl%s_%x_%d",
3987 suffix, idx, bp->eth_dev->data->port_id);
3988 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3989 mz = rte_memzone_lookup(mz_name);
3991 mz = rte_memzone_reserve_aligned(mz_name,
3995 RTE_MEMZONE_SIZE_HINT_ONLY |
3996 RTE_MEMZONE_IOVA_CONTIG,
4002 memset(mz->addr, 0, mz->len);
4003 mz_phys_addr = mz->iova;
4004 if ((unsigned long)mz->addr == mz_phys_addr) {
4006 "physical address same as virtual\n");
4007 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4008 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4009 if (mz_phys_addr == RTE_BAD_IOVA) {
4011 "unable to map addr to phys memory\n");
4015 rte_mem_lock_page(((char *)mz->addr));
4017 rmem->pg_tbl = mz->addr;
4018 rmem->pg_tbl_map = mz_phys_addr;
4019 rmem->pg_tbl_mz = mz;
4022 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4023 suffix, idx, bp->eth_dev->data->port_id);
4024 mz = rte_memzone_lookup(mz_name);
4026 mz = rte_memzone_reserve_aligned(mz_name,
4030 RTE_MEMZONE_SIZE_HINT_ONLY |
4031 RTE_MEMZONE_IOVA_CONTIG,
4037 memset(mz->addr, 0, mz->len);
4038 mz_phys_addr = mz->iova;
4039 if ((unsigned long)mz->addr == mz_phys_addr) {
4041 "Memzone physical address same as virtual.\n");
4042 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4043 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4044 rte_mem_lock_page(((char *)mz->addr) + sz);
4045 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4046 if (mz_phys_addr == RTE_BAD_IOVA) {
4048 "unable to map addr to phys memory\n");
4053 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4054 rte_mem_lock_page(((char *)mz->addr) + sz);
4055 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4056 rmem->dma_arr[i] = mz_phys_addr + sz;
4058 if (rmem->nr_pages > 1) {
4059 if (i == rmem->nr_pages - 2 &&
4060 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4061 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4062 else if (i == rmem->nr_pages - 1 &&
4063 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4064 valid_bits |= PTU_PTE_LAST;
4066 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4072 if (rmem->vmem_size)
4073 rmem->vmem = (void **)mz->addr;
4074 rmem->dma_arr[0] = mz_phys_addr;
4078 static void bnxt_free_ctx_mem(struct bnxt *bp)
4082 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4085 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4086 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4087 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4088 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4089 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4090 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4091 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4092 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4093 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4094 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4095 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4097 for (i = 0; i < BNXT_MAX_Q; i++) {
4098 if (bp->ctx->tqm_mem[i])
4099 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4106 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4108 #define min_t(type, x, y) ({ \
4109 type __min1 = (x); \
4110 type __min2 = (y); \
4111 __min1 < __min2 ? __min1 : __min2; })
4113 #define max_t(type, x, y) ({ \
4114 type __max1 = (x); \
4115 type __max2 = (y); \
4116 __max1 > __max2 ? __max1 : __max2; })
4118 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4120 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4122 struct bnxt_ctx_pg_info *ctx_pg;
4123 struct bnxt_ctx_mem_info *ctx;
4124 uint32_t mem_size, ena, entries;
4127 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4129 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4133 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4136 ctx_pg = &ctx->qp_mem;
4137 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4138 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4139 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4143 ctx_pg = &ctx->srq_mem;
4144 ctx_pg->entries = ctx->srq_max_l2_entries;
4145 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4146 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4150 ctx_pg = &ctx->cq_mem;
4151 ctx_pg->entries = ctx->cq_max_l2_entries;
4152 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4153 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4157 ctx_pg = &ctx->vnic_mem;
4158 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4159 ctx->vnic_max_ring_table_entries;
4160 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4161 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4165 ctx_pg = &ctx->stat_mem;
4166 ctx_pg->entries = ctx->stat_max_entries;
4167 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4168 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4172 entries = ctx->qp_max_l2_entries;
4173 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4174 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4175 ctx->tqm_max_entries_per_ring);
4176 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4177 ctx_pg = ctx->tqm_mem[i];
4178 /* use min tqm entries for now. */
4179 ctx_pg->entries = entries;
4180 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4181 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4184 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4187 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4188 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4191 "Failed to configure context mem: rc = %d\n", rc);
4193 ctx->flags |= BNXT_CTX_FLAG_INITED;
4198 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4200 struct rte_pci_device *pci_dev = bp->pdev;
4201 char mz_name[RTE_MEMZONE_NAMESIZE];
4202 const struct rte_memzone *mz = NULL;
4203 uint32_t total_alloc_len;
4204 rte_iova_t mz_phys_addr;
4206 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4209 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4210 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4211 pci_dev->addr.bus, pci_dev->addr.devid,
4212 pci_dev->addr.function, "rx_port_stats");
4213 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4214 mz = rte_memzone_lookup(mz_name);
4216 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4217 sizeof(struct rx_port_stats_ext) + 512);
4219 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4222 RTE_MEMZONE_SIZE_HINT_ONLY |
4223 RTE_MEMZONE_IOVA_CONTIG);
4227 memset(mz->addr, 0, mz->len);
4228 mz_phys_addr = mz->iova;
4229 if ((unsigned long)mz->addr == mz_phys_addr) {
4231 "Memzone physical address same as virtual.\n");
4233 "Using rte_mem_virt2iova()\n");
4234 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4235 if (mz_phys_addr == RTE_BAD_IOVA) {
4237 "Can't map address to physical memory\n");
4242 bp->rx_mem_zone = (const void *)mz;
4243 bp->hw_rx_port_stats = mz->addr;
4244 bp->hw_rx_port_stats_map = mz_phys_addr;
4246 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4247 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4248 pci_dev->addr.bus, pci_dev->addr.devid,
4249 pci_dev->addr.function, "tx_port_stats");
4250 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4251 mz = rte_memzone_lookup(mz_name);
4253 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4254 sizeof(struct tx_port_stats_ext) + 512);
4256 mz = rte_memzone_reserve(mz_name,
4260 RTE_MEMZONE_SIZE_HINT_ONLY |
4261 RTE_MEMZONE_IOVA_CONTIG);
4265 memset(mz->addr, 0, mz->len);
4266 mz_phys_addr = mz->iova;
4267 if ((unsigned long)mz->addr == mz_phys_addr) {
4269 "Memzone physical address same as virtual\n");
4270 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4271 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4272 if (mz_phys_addr == RTE_BAD_IOVA) {
4274 "Can't map address to physical memory\n");
4279 bp->tx_mem_zone = (const void *)mz;
4280 bp->hw_tx_port_stats = mz->addr;
4281 bp->hw_tx_port_stats_map = mz_phys_addr;
4282 bp->flags |= BNXT_FLAG_PORT_STATS;
4284 /* Display extended statistics if FW supports it */
4285 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4286 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4287 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4290 bp->hw_rx_port_stats_ext = (void *)
4291 ((uint8_t *)bp->hw_rx_port_stats +
4292 sizeof(struct rx_port_stats));
4293 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4294 sizeof(struct rx_port_stats);
4295 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4297 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4298 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4299 bp->hw_tx_port_stats_ext = (void *)
4300 ((uint8_t *)bp->hw_tx_port_stats +
4301 sizeof(struct tx_port_stats));
4302 bp->hw_tx_port_stats_ext_map =
4303 bp->hw_tx_port_stats_map +
4304 sizeof(struct tx_port_stats);
4305 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4311 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4313 struct bnxt *bp = eth_dev->data->dev_private;
4316 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4317 RTE_ETHER_ADDR_LEN *
4320 if (eth_dev->data->mac_addrs == NULL) {
4321 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4325 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4329 /* Generate a random MAC address, if none was assigned by PF */
4330 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4331 bnxt_eth_hw_addr_random(bp->mac_addr);
4333 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4334 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4335 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4337 rc = bnxt_hwrm_set_mac(bp);
4339 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4340 RTE_ETHER_ADDR_LEN);
4344 /* Copy the permanent MAC from the FUNC_QCAPS response */
4345 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4346 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4351 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4355 /* MAC is already configured in FW */
4356 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4359 /* Restore the old MAC configured */
4360 rc = bnxt_hwrm_set_mac(bp);
4362 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4367 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4372 #define ALLOW_FUNC(x) \
4374 uint32_t arg = (x); \
4375 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4376 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4379 /* Forward all requests if firmware is new enough */
4380 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4381 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4382 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4383 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4385 PMD_DRV_LOG(WARNING,
4386 "Firmware too old for VF mailbox functionality\n");
4387 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4391 * The following are used for driver cleanup. If we disallow these,
4392 * VF drivers can't clean up cleanly.
4394 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4395 ALLOW_FUNC(HWRM_VNIC_FREE);
4396 ALLOW_FUNC(HWRM_RING_FREE);
4397 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4398 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4399 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4400 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4401 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4402 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4405 static int bnxt_init_fw(struct bnxt *bp)
4410 rc = bnxt_hwrm_ver_get(bp);
4414 rc = bnxt_hwrm_func_reset(bp);
4418 rc = bnxt_hwrm_queue_qportcfg(bp);
4422 /* Get the MAX capabilities for this function */
4423 rc = bnxt_hwrm_func_qcaps(bp);
4427 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4431 /* Get the adapter error recovery support info */
4432 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4434 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4436 if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4437 mtu != bp->eth_dev->data->mtu)
4438 bp->eth_dev->data->mtu = mtu;
4440 bnxt_hwrm_port_led_qcaps(bp);
4445 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4449 rc = bnxt_init_fw(bp);
4453 if (!reconfig_dev) {
4454 rc = bnxt_setup_mac_addr(bp->eth_dev);
4458 rc = bnxt_restore_dflt_mac(bp);
4463 bnxt_config_vf_req_fwd(bp);
4465 rc = bnxt_hwrm_func_driver_register(bp);
4467 PMD_DRV_LOG(ERR, "Failed to register driver");
4472 if (bp->pdev->max_vfs) {
4473 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4475 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4479 rc = bnxt_hwrm_allocate_pf_only(bp);
4482 "Failed to allocate PF resources");
4488 rc = bnxt_alloc_mem(bp, reconfig_dev);
4492 rc = bnxt_setup_int(bp);
4498 rc = bnxt_request_int(bp);
4506 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4508 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4509 static int version_printed;
4513 if (version_printed++ == 0)
4514 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4516 rte_eth_copy_pci_info(eth_dev, pci_dev);
4518 bp = eth_dev->data->dev_private;
4520 bp->dev_stopped = 1;
4522 eth_dev->dev_ops = &bnxt_dev_ops;
4523 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4524 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4527 * For secondary processes, we don't initialise any further
4528 * as primary has already done this work.
4530 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4533 if (bnxt_vf_pciid(pci_dev->id.device_id))
4534 bp->flags |= BNXT_FLAG_VF;
4536 if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4537 pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4538 pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4539 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4540 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4541 bp->flags |= BNXT_FLAG_THOR_CHIP;
4543 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4544 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4545 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4546 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4547 bp->flags |= BNXT_FLAG_STINGRAY;
4549 rc = bnxt_init_board(eth_dev);
4552 "Failed to initialize board rc: %x\n", rc);
4556 rc = bnxt_alloc_hwrm_resources(bp);
4559 "Failed to allocate hwrm resource rc: %x\n", rc);
4562 rc = bnxt_init_resources(bp, false);
4566 rc = bnxt_alloc_stats_mem(bp);
4571 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4572 pci_dev->mem_resource[0].phys_addr,
4573 pci_dev->mem_resource[0].addr);
4578 bnxt_dev_uninit(eth_dev);
4583 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4587 bnxt_disable_int(bp);
4589 bnxt_free_mem(bp, reconfig_dev);
4590 bnxt_hwrm_func_buf_unrgtr(bp);
4591 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4592 bp->flags &= ~BNXT_FLAG_REGISTERED;
4593 bnxt_free_ctx_mem(bp);
4594 if (!reconfig_dev) {
4595 bnxt_free_hwrm_resources(bp);
4597 if (bp->recovery_info != NULL) {
4598 rte_free(bp->recovery_info);
4599 bp->recovery_info = NULL;
4603 rte_free(bp->ptp_cfg);
4609 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4611 struct bnxt *bp = eth_dev->data->dev_private;
4614 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4617 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4619 rc = bnxt_uninit_resources(bp, false);
4621 if (bp->grp_info != NULL) {
4622 rte_free(bp->grp_info);
4623 bp->grp_info = NULL;
4626 if (bp->tx_mem_zone) {
4627 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4628 bp->tx_mem_zone = NULL;
4631 if (bp->rx_mem_zone) {
4632 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4633 bp->rx_mem_zone = NULL;
4636 if (bp->dev_stopped == 0)
4637 bnxt_dev_close_op(eth_dev);
4639 rte_free(bp->pf.vf_info);
4640 eth_dev->dev_ops = NULL;
4641 eth_dev->rx_pkt_burst = NULL;
4642 eth_dev->tx_pkt_burst = NULL;
4647 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4648 struct rte_pci_device *pci_dev)
4650 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4654 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4656 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4657 return rte_eth_dev_pci_generic_remove(pci_dev,
4660 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4663 static struct rte_pci_driver bnxt_rte_pmd = {
4664 .id_table = bnxt_pci_id_map,
4665 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4666 .probe = bnxt_pci_probe,
4667 .remove = bnxt_pci_remove,
4671 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4673 if (strcmp(dev->device->driver->name, drv->driver.name))
4679 bool is_bnxt_supported(struct rte_eth_dev *dev)
4681 return is_device_supported(dev, &bnxt_rte_pmd);
4684 RTE_INIT(bnxt_init_log)
4686 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4687 if (bnxt_logtype_driver >= 0)
4688 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4691 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4692 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4693 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");