1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
19 #include "bnxt_filter.h"
20 #include "bnxt_hwrm.h"
22 #include "bnxt_reps.h"
23 #include "bnxt_ring.h"
26 #include "bnxt_stats.h"
29 #include "bnxt_vnic.h"
30 #include "hsi_struct_def_dpdk.h"
31 #include "bnxt_nvm_defs.h"
32 #include "bnxt_tf_common.h"
33 #include "ulp_flow_db.h"
34 #include "rte_pmd_bnxt.h"
36 #define DRV_MODULE_NAME "bnxt"
37 static const char bnxt_version[] =
38 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
41 * The set of PCI devices this driver supports
43 static const struct rte_pci_id bnxt_pci_id_map[] = {
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
87 { .vendor_id = 0, /* sentinel */ },
90 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
91 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
92 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
93 #define BNXT_DEVARG_REPRESENTOR "representor"
94 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf"
95 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf"
96 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f"
97 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r"
98 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f"
99 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r"
101 static const char *const bnxt_dev_args[] = {
102 BNXT_DEVARG_REPRESENTOR,
104 BNXT_DEVARG_FLOW_XSTAT,
105 BNXT_DEVARG_MAX_NUM_KFLOWS,
106 BNXT_DEVARG_REP_BASED_PF,
107 BNXT_DEVARG_REP_IS_PF,
108 BNXT_DEVARG_REP_Q_R2F,
109 BNXT_DEVARG_REP_Q_F2R,
110 BNXT_DEVARG_REP_FC_R2F,
111 BNXT_DEVARG_REP_FC_F2R,
116 * truflow == false to disable the feature
117 * truflow == true to enable the feature
119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
122 * flow_xstat == false to disable the feature
123 * flow_xstat == true to enable the feature
125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
128 * rep_is_pf == false to indicate VF representor
129 * rep_is_pf == true to indicate PF representor
131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1)
134 * rep_based_pf == Physical index of the PF
136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15)
138 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3)
143 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3)
148 * rep_fc_r2f == Flow control for the representor to endpoint direction
150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1)
153 * rep_fc_f2r == Flow control for the endpoint to representor direction
155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1)
157 int bnxt_cfa_code_dynfield_offset = -1;
160 * max_num_kflows must be >= 32
161 * and must be a power-of-2 supported value
162 * return: 1 -> invalid
165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
167 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
176 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
177 static int bnxt_restore_vlan_filters(struct bnxt *bp);
178 static void bnxt_dev_recover(void *arg);
179 static void bnxt_free_error_recovery_info(struct bnxt *bp);
180 static void bnxt_free_rep_info(struct bnxt *bp);
182 int is_bnxt_in_error(struct bnxt *bp)
184 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
186 if (bp->flags & BNXT_FLAG_FW_RESET)
192 /***********************/
195 * High level utility functions
198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
200 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
201 BNXT_RSS_TBL_SIZE_P5);
203 if (!BNXT_CHIP_P5(bp))
206 return RTE_ALIGN_MUL_CEIL(num_rss_rings,
207 BNXT_RSS_ENTRIES_PER_CTX_P5) /
208 BNXT_RSS_ENTRIES_PER_CTX_P5;
211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
213 if (!BNXT_CHIP_P5(bp))
214 return HW_HASH_INDEX_SIZE;
216 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
219 static void bnxt_free_parent_info(struct bnxt *bp)
221 rte_free(bp->parent);
224 static void bnxt_free_pf_info(struct bnxt *bp)
229 static void bnxt_free_link_info(struct bnxt *bp)
231 rte_free(bp->link_info);
234 static void bnxt_free_leds_info(struct bnxt *bp)
243 static void bnxt_free_flow_stats_info(struct bnxt *bp)
245 rte_free(bp->flow_stat);
246 bp->flow_stat = NULL;
249 static void bnxt_free_cos_queues(struct bnxt *bp)
251 rte_free(bp->rx_cos_queue);
252 rte_free(bp->tx_cos_queue);
255 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
257 bnxt_free_filter_mem(bp);
258 bnxt_free_vnic_attributes(bp);
259 bnxt_free_vnic_mem(bp);
261 /* tx/rx rings are configured as part of *_queue_setup callbacks.
262 * If the number of rings change across fw update,
263 * we don't have much choice except to warn the user.
267 bnxt_free_tx_rings(bp);
268 bnxt_free_rx_rings(bp);
270 bnxt_free_async_cp_ring(bp);
271 bnxt_free_rxtx_nq_ring(bp);
273 rte_free(bp->grp_info);
277 static int bnxt_alloc_parent_info(struct bnxt *bp)
279 bp->parent = rte_zmalloc("bnxt_parent_info",
280 sizeof(struct bnxt_parent_info), 0);
281 if (bp->parent == NULL)
287 static int bnxt_alloc_pf_info(struct bnxt *bp)
289 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
296 static int bnxt_alloc_link_info(struct bnxt *bp)
299 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
300 if (bp->link_info == NULL)
306 static int bnxt_alloc_leds_info(struct bnxt *bp)
311 bp->leds = rte_zmalloc("bnxt_leds",
312 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
314 if (bp->leds == NULL)
320 static int bnxt_alloc_cos_queues(struct bnxt *bp)
323 rte_zmalloc("bnxt_rx_cosq",
324 BNXT_COS_QUEUE_COUNT *
325 sizeof(struct bnxt_cos_queue_info),
327 if (bp->rx_cos_queue == NULL)
331 rte_zmalloc("bnxt_tx_cosq",
332 BNXT_COS_QUEUE_COUNT *
333 sizeof(struct bnxt_cos_queue_info),
335 if (bp->tx_cos_queue == NULL)
341 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
343 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
344 sizeof(struct bnxt_flow_stat_info), 0);
345 if (bp->flow_stat == NULL)
351 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
355 rc = bnxt_alloc_ring_grps(bp);
359 rc = bnxt_alloc_async_ring_struct(bp);
363 rc = bnxt_alloc_vnic_mem(bp);
367 rc = bnxt_alloc_vnic_attributes(bp);
371 rc = bnxt_alloc_filter_mem(bp);
375 rc = bnxt_alloc_async_cp_ring(bp);
379 rc = bnxt_alloc_rxtx_nq_ring(bp);
383 if (BNXT_FLOW_XSTATS_EN(bp)) {
384 rc = bnxt_alloc_flow_stats_info(bp);
392 bnxt_free_mem(bp, reconfig);
396 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
398 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
399 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
400 uint64_t rx_offloads = dev_conf->rxmode.offloads;
401 struct bnxt_rx_queue *rxq;
405 rc = bnxt_vnic_grp_alloc(bp, vnic);
409 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
410 vnic_id, vnic, vnic->fw_grp_ids);
412 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
416 /* Alloc RSS context only if RSS mode is enabled */
417 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
418 int j, nr_ctxs = bnxt_rss_ctxts(bp);
420 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
421 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
422 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
424 "Only queues 0-%d will be in RSS table\n",
425 BNXT_RSS_TBL_SIZE_P5 - 1);
429 for (j = 0; j < nr_ctxs; j++) {
430 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
436 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
440 vnic->num_lb_ctxts = nr_ctxs;
444 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
445 * setting is not available at this time, it will not be
446 * configured correctly in the CFA.
448 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
449 vnic->vlan_strip = true;
451 vnic->vlan_strip = false;
453 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
457 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
461 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
462 rxq = bp->eth_dev->data->rx_queues[j];
465 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
466 j, rxq->vnic, rxq->vnic->fw_grp_ids);
468 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
469 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
471 vnic->rx_queue_cnt++;
474 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
476 rc = bnxt_vnic_rss_configure(bp, vnic);
480 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
482 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
483 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
485 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
489 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
494 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
498 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
499 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
504 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
505 " rx_fc_in_tbl.ctx_id = %d\n",
506 bp->flow_stat->rx_fc_in_tbl.va,
507 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
508 bp->flow_stat->rx_fc_in_tbl.ctx_id);
510 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
511 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
516 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
517 " rx_fc_out_tbl.ctx_id = %d\n",
518 bp->flow_stat->rx_fc_out_tbl.va,
519 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
520 bp->flow_stat->rx_fc_out_tbl.ctx_id);
522 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
523 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
528 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
529 " tx_fc_in_tbl.ctx_id = %d\n",
530 bp->flow_stat->tx_fc_in_tbl.va,
531 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
532 bp->flow_stat->tx_fc_in_tbl.ctx_id);
534 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
535 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
540 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
541 " tx_fc_out_tbl.ctx_id = %d\n",
542 bp->flow_stat->tx_fc_out_tbl.va,
543 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
544 bp->flow_stat->tx_fc_out_tbl.ctx_id);
546 memset(bp->flow_stat->rx_fc_out_tbl.va,
548 bp->flow_stat->rx_fc_out_tbl.size);
549 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
550 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
551 bp->flow_stat->rx_fc_out_tbl.ctx_id,
552 bp->flow_stat->max_fc,
557 memset(bp->flow_stat->tx_fc_out_tbl.va,
559 bp->flow_stat->tx_fc_out_tbl.size);
560 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
561 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
562 bp->flow_stat->tx_fc_out_tbl.ctx_id,
563 bp->flow_stat->max_fc,
569 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
570 struct bnxt_ctx_mem_buf_info *ctx)
575 ctx->va = rte_zmalloc(type, size, 0);
578 rte_mem_lock_page(ctx->va);
580 ctx->dma = rte_mem_virt2iova(ctx->va);
581 if (ctx->dma == RTE_BAD_IOVA)
587 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
589 struct rte_pci_device *pdev = bp->pdev;
590 char type[RTE_MEMZONE_NAMESIZE];
594 max_fc = bp->flow_stat->max_fc;
596 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
597 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
598 /* 4 bytes for each counter-id */
599 rc = bnxt_alloc_ctx_mem_buf(type,
601 &bp->flow_stat->rx_fc_in_tbl);
605 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
606 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
607 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
608 rc = bnxt_alloc_ctx_mem_buf(type,
610 &bp->flow_stat->rx_fc_out_tbl);
614 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
615 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
616 /* 4 bytes for each counter-id */
617 rc = bnxt_alloc_ctx_mem_buf(type,
619 &bp->flow_stat->tx_fc_in_tbl);
623 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
624 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
625 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
626 rc = bnxt_alloc_ctx_mem_buf(type,
628 &bp->flow_stat->tx_fc_out_tbl);
632 rc = bnxt_register_fc_ctx_mem(bp);
637 static int bnxt_init_ctx_mem(struct bnxt *bp)
641 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
642 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
643 !BNXT_FLOW_XSTATS_EN(bp))
646 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
650 rc = bnxt_init_fc_ctx_mem(bp);
655 static int bnxt_update_phy_setting(struct bnxt *bp)
657 struct rte_eth_link new;
660 rc = bnxt_get_hwrm_link_config(bp, &new);
662 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
667 * On BCM957508-N2100 adapters, FW will not allow any user other
668 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
669 * always returns link up. Force phy update always in that case.
671 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
672 rc = bnxt_set_hwrm_link_config(bp, true);
674 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
682 static int bnxt_init_chip(struct bnxt *bp)
684 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
685 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
686 uint32_t intr_vector = 0;
687 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
688 uint32_t vec = BNXT_MISC_VEC_ID;
692 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
693 bp->eth_dev->data->dev_conf.rxmode.offloads |=
694 DEV_RX_OFFLOAD_JUMBO_FRAME;
695 bp->flags |= BNXT_FLAG_JUMBO;
697 bp->eth_dev->data->dev_conf.rxmode.offloads &=
698 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
699 bp->flags &= ~BNXT_FLAG_JUMBO;
702 /* THOR does not support ring groups.
703 * But we will use the array to save RSS context IDs.
705 if (BNXT_CHIP_P5(bp))
706 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
708 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
710 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
714 rc = bnxt_alloc_hwrm_rings(bp);
716 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
720 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
722 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
726 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
729 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
730 if (bp->rx_cos_queue[i].id != 0xff) {
731 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
735 "Num pools more than FW profile\n");
739 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
745 rc = bnxt_mq_rx_configure(bp);
747 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
751 /* VNIC configuration */
752 for (i = 0; i < bp->nr_vnics; i++) {
753 rc = bnxt_setup_one_vnic(bp, i);
758 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
761 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
765 /* check and configure queue intr-vector mapping */
766 if ((rte_intr_cap_multiple(intr_handle) ||
767 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
768 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
769 intr_vector = bp->eth_dev->data->nb_rx_queues;
770 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
771 if (intr_vector > bp->rx_cp_nr_rings) {
772 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
776 rc = rte_intr_efd_enable(intr_handle, intr_vector);
781 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
782 intr_handle->intr_vec =
783 rte_zmalloc("intr_vec",
784 bp->eth_dev->data->nb_rx_queues *
786 if (intr_handle->intr_vec == NULL) {
787 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
788 " intr_vec", bp->eth_dev->data->nb_rx_queues);
792 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
793 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
794 intr_handle->intr_vec, intr_handle->nb_efd,
795 intr_handle->max_intr);
796 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
798 intr_handle->intr_vec[queue_id] =
799 vec + BNXT_RX_VEC_START;
800 if (vec < base + intr_handle->nb_efd - 1)
805 /* enable uio/vfio intr/eventfd mapping */
806 rc = rte_intr_enable(intr_handle);
807 #ifndef RTE_EXEC_ENV_FREEBSD
808 /* In FreeBSD OS, nic_uio driver does not support interrupts */
813 rc = bnxt_update_phy_setting(bp);
817 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
819 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
824 rte_free(intr_handle->intr_vec);
826 rte_intr_efd_disable(intr_handle);
828 /* Some of the error status returned by FW may not be from errno.h */
835 static int bnxt_shutdown_nic(struct bnxt *bp)
837 bnxt_free_all_hwrm_resources(bp);
838 bnxt_free_all_filters(bp);
839 bnxt_free_all_vnics(bp);
844 * Device configuration and status function
847 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
849 uint32_t link_speed = bp->link_info->support_speeds;
850 uint32_t speed_capa = 0;
852 /* If PAM4 is configured, use PAM4 supported speed */
853 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
854 link_speed = bp->link_info->support_pam4_speeds;
856 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
857 speed_capa |= ETH_LINK_SPEED_100M;
858 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
859 speed_capa |= ETH_LINK_SPEED_100M_HD;
860 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
861 speed_capa |= ETH_LINK_SPEED_1G;
862 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
863 speed_capa |= ETH_LINK_SPEED_2_5G;
864 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
865 speed_capa |= ETH_LINK_SPEED_10G;
866 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
867 speed_capa |= ETH_LINK_SPEED_20G;
868 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
869 speed_capa |= ETH_LINK_SPEED_25G;
870 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
871 speed_capa |= ETH_LINK_SPEED_40G;
872 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
873 speed_capa |= ETH_LINK_SPEED_50G;
874 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
875 speed_capa |= ETH_LINK_SPEED_100G;
876 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
877 speed_capa |= ETH_LINK_SPEED_50G;
878 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
879 speed_capa |= ETH_LINK_SPEED_100G;
880 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
881 speed_capa |= ETH_LINK_SPEED_200G;
883 if (bp->link_info->auto_mode ==
884 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
885 speed_capa |= ETH_LINK_SPEED_FIXED;
887 speed_capa |= ETH_LINK_SPEED_AUTONEG;
892 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
893 struct rte_eth_dev_info *dev_info)
895 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
896 struct bnxt *bp = eth_dev->data->dev_private;
897 uint16_t max_vnics, i, j, vpool, vrxq;
898 unsigned int max_rx_rings;
901 rc = is_bnxt_in_error(bp);
906 dev_info->max_mac_addrs = bp->max_l2_ctx;
907 dev_info->max_hash_mac_addrs = 0;
909 /* PF/VF specifics */
911 dev_info->max_vfs = pdev->max_vfs;
913 max_rx_rings = bnxt_max_rings(bp);
914 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
915 dev_info->max_rx_queues = max_rx_rings;
916 dev_info->max_tx_queues = max_rx_rings;
917 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
918 dev_info->hash_key_size = 40;
919 max_vnics = bp->max_vnics;
922 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
923 dev_info->max_mtu = BNXT_MAX_MTU;
925 /* Fast path specifics */
926 dev_info->min_rx_bufsize = 1;
927 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
929 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
930 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
931 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
932 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
933 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
934 dev_info->tx_queue_offload_capa;
935 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
937 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
940 dev_info->default_rxconf = (struct rte_eth_rxconf) {
946 .rx_free_thresh = 32,
947 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
950 dev_info->default_txconf = (struct rte_eth_txconf) {
956 .tx_free_thresh = 32,
959 eth_dev->data->dev_conf.intr_conf.lsc = 1;
961 eth_dev->data->dev_conf.intr_conf.rxq = 1;
962 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
963 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
964 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
965 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
967 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
968 dev_info->switch_info.name = eth_dev->device->name;
969 dev_info->switch_info.domain_id = bp->switch_domain_id;
970 dev_info->switch_info.port_id =
971 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
972 BNXT_SWITCH_PORT_ID_TRUSTED_VF;
978 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
979 * need further investigation.
983 vpool = 64; /* ETH_64_POOLS */
984 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
985 for (i = 0; i < 4; vpool >>= 1, i++) {
986 if (max_vnics > vpool) {
987 for (j = 0; j < 5; vrxq >>= 1, j++) {
988 if (dev_info->max_rx_queues > vrxq) {
994 /* Not enough resources to support VMDq */
998 /* Not enough resources to support VMDq */
1002 dev_info->max_vmdq_pools = vpool;
1003 dev_info->vmdq_queue_num = vrxq;
1005 dev_info->vmdq_pool_base = 0;
1006 dev_info->vmdq_queue_base = 0;
1011 /* Configure the device based on the configuration provided */
1012 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1014 struct bnxt *bp = eth_dev->data->dev_private;
1015 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1018 bp->rx_queues = (void *)eth_dev->data->rx_queues;
1019 bp->tx_queues = (void *)eth_dev->data->tx_queues;
1020 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1021 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1023 rc = is_bnxt_in_error(bp);
1027 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1028 rc = bnxt_hwrm_check_vf_rings(bp);
1030 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1034 /* If a resource has already been allocated - in this case
1035 * it is the async completion ring, free it. Reallocate it after
1036 * resource reservation. This will ensure the resource counts
1037 * are calculated correctly.
1040 pthread_mutex_lock(&bp->def_cp_lock);
1042 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1043 bnxt_disable_int(bp);
1044 bnxt_free_cp_ring(bp, bp->async_cp_ring);
1047 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1049 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1050 pthread_mutex_unlock(&bp->def_cp_lock);
1054 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1055 rc = bnxt_alloc_async_cp_ring(bp);
1057 pthread_mutex_unlock(&bp->def_cp_lock);
1060 bnxt_enable_int(bp);
1063 pthread_mutex_unlock(&bp->def_cp_lock);
1066 /* Inherit new configurations */
1067 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1068 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1069 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1070 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1071 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1073 goto resource_error;
1075 if (BNXT_HAS_RING_GRPS(bp) &&
1076 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1077 goto resource_error;
1079 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1080 bp->max_vnics < eth_dev->data->nb_rx_queues)
1081 goto resource_error;
1083 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1084 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1086 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1087 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1088 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1090 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1091 eth_dev->data->mtu =
1092 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1093 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1095 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1101 "Insufficient resources to support requested config\n");
1103 "Num Queues Requested: Tx %d, Rx %d\n",
1104 eth_dev->data->nb_tx_queues,
1105 eth_dev->data->nb_rx_queues);
1107 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1108 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1109 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1113 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1115 struct rte_eth_link *link = ð_dev->data->dev_link;
1117 if (link->link_status)
1118 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1119 eth_dev->data->port_id,
1120 (uint32_t)link->link_speed,
1121 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1122 ("full-duplex") : ("half-duplex\n"));
1124 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1125 eth_dev->data->port_id);
1129 * Determine whether the current configuration requires support for scattered
1130 * receive; return 1 if scattered receive is required and 0 if not.
1132 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1137 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1140 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1141 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1143 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1144 RTE_PKTMBUF_HEADROOM);
1145 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1151 static eth_rx_burst_t
1152 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1154 struct bnxt *bp = eth_dev->data->dev_private;
1156 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1157 #ifndef RTE_LIBRTE_IEEE1588
1159 * Vector mode receive can be enabled only if scatter rx is not
1160 * in use and rx offloads are limited to VLAN stripping and
1163 if (!eth_dev->data->scattered_rx &&
1164 !(eth_dev->data->dev_conf.rxmode.offloads &
1165 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1166 DEV_RX_OFFLOAD_KEEP_CRC |
1167 DEV_RX_OFFLOAD_JUMBO_FRAME |
1168 DEV_RX_OFFLOAD_IPV4_CKSUM |
1169 DEV_RX_OFFLOAD_UDP_CKSUM |
1170 DEV_RX_OFFLOAD_TCP_CKSUM |
1171 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1172 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1173 DEV_RX_OFFLOAD_RSS_HASH |
1174 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1175 !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) &&
1176 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1177 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1178 eth_dev->data->port_id);
1179 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1180 return bnxt_recv_pkts_vec;
1182 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1183 eth_dev->data->port_id);
1185 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1186 eth_dev->data->port_id,
1187 eth_dev->data->scattered_rx,
1188 eth_dev->data->dev_conf.rxmode.offloads);
1191 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1192 return bnxt_recv_pkts;
1195 static eth_tx_burst_t
1196 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1198 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1199 #ifndef RTE_LIBRTE_IEEE1588
1200 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1201 struct bnxt *bp = eth_dev->data->dev_private;
1204 * Vector mode transmit can be enabled only if not using scatter rx
1207 if (!eth_dev->data->scattered_rx &&
1208 !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1209 !BNXT_TRUFLOW_EN(bp) &&
1210 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1211 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1212 eth_dev->data->port_id);
1213 return bnxt_xmit_pkts_vec;
1215 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1216 eth_dev->data->port_id);
1218 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1219 eth_dev->data->port_id,
1220 eth_dev->data->scattered_rx,
1224 return bnxt_xmit_pkts;
1227 static int bnxt_handle_if_change_status(struct bnxt *bp)
1231 /* Since fw has undergone a reset and lost all contexts,
1232 * set fatal flag to not issue hwrm during cleanup
1234 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1235 bnxt_uninit_resources(bp, true);
1237 /* clear fatal flag so that re-init happens */
1238 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1239 rc = bnxt_init_resources(bp, true);
1241 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1246 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1248 struct bnxt *bp = eth_dev->data->dev_private;
1249 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1251 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1253 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1254 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1258 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1260 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1261 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1264 rc = bnxt_hwrm_if_change(bp, true);
1265 if (rc == 0 || rc != -EAGAIN)
1268 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1269 } while (retry_cnt--);
1274 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1275 rc = bnxt_handle_if_change_status(bp);
1280 bnxt_enable_int(bp);
1282 rc = bnxt_init_chip(bp);
1286 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1287 eth_dev->data->dev_started = 1;
1289 bnxt_link_update_op(eth_dev, 1);
1291 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1292 vlan_mask |= ETH_VLAN_FILTER_MASK;
1293 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1294 vlan_mask |= ETH_VLAN_STRIP_MASK;
1295 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1299 /* Initialize bnxt ULP port details */
1300 rc = bnxt_ulp_port_init(bp);
1304 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1305 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1307 bnxt_schedule_fw_health_check(bp);
1312 bnxt_shutdown_nic(bp);
1313 bnxt_free_tx_mbufs(bp);
1314 bnxt_free_rx_mbufs(bp);
1315 bnxt_hwrm_if_change(bp, false);
1316 eth_dev->data->dev_started = 0;
1320 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1322 struct bnxt *bp = eth_dev->data->dev_private;
1325 if (!bp->link_info->link_up)
1326 rc = bnxt_set_hwrm_link_config(bp, true);
1328 eth_dev->data->dev_link.link_status = 1;
1330 bnxt_print_link_info(eth_dev);
1334 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1336 struct bnxt *bp = eth_dev->data->dev_private;
1338 eth_dev->data->dev_link.link_status = 0;
1339 bnxt_set_hwrm_link_config(bp, false);
1340 bp->link_info->link_up = 0;
1345 static void bnxt_free_switch_domain(struct bnxt *bp)
1349 if (bp->switch_domain_id) {
1350 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1352 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1353 bp->switch_domain_id, rc);
1357 /* Unload the driver, release resources */
1358 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1360 struct bnxt *bp = eth_dev->data->dev_private;
1361 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1362 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1363 struct rte_eth_link link;
1366 eth_dev->data->dev_started = 0;
1367 eth_dev->data->scattered_rx = 0;
1369 /* Prevent crashes when queues are still in use */
1370 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1371 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1373 bnxt_disable_int(bp);
1375 /* disable uio/vfio intr/eventfd mapping */
1376 rte_intr_disable(intr_handle);
1378 /* Stop the child representors for this device */
1379 ret = bnxt_rep_stop_all(bp);
1383 /* delete the bnxt ULP port details */
1384 bnxt_ulp_port_deinit(bp);
1386 bnxt_cancel_fw_health_check(bp);
1388 /* Do not bring link down during reset recovery */
1389 if (!is_bnxt_in_error(bp)) {
1390 bnxt_dev_set_link_down_op(eth_dev);
1391 /* Wait for link to be reset */
1392 if (BNXT_SINGLE_PF(bp))
1394 /* clear the recorded link status */
1395 memset(&link, 0, sizeof(link));
1396 rte_eth_linkstatus_set(eth_dev, &link);
1399 /* Clean queue intr-vector mapping */
1400 rte_intr_efd_disable(intr_handle);
1401 if (intr_handle->intr_vec != NULL) {
1402 rte_free(intr_handle->intr_vec);
1403 intr_handle->intr_vec = NULL;
1406 bnxt_hwrm_port_clr_stats(bp);
1407 bnxt_free_tx_mbufs(bp);
1408 bnxt_free_rx_mbufs(bp);
1409 /* Process any remaining notifications in default completion queue */
1410 bnxt_int_handler(eth_dev);
1411 bnxt_shutdown_nic(bp);
1412 bnxt_hwrm_if_change(bp, false);
1414 rte_free(bp->mark_table);
1415 bp->mark_table = NULL;
1417 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1418 bp->rx_cosq_cnt = 0;
1419 /* All filters are deleted on a port stop. */
1420 if (BNXT_FLOW_XSTATS_EN(bp))
1421 bp->flow_stat->flow_count = 0;
1426 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1428 struct bnxt *bp = eth_dev->data->dev_private;
1431 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1434 /* cancel the recovery handler before remove dev */
1435 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1436 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1437 bnxt_cancel_fc_thread(bp);
1439 if (eth_dev->data->dev_started)
1440 ret = bnxt_dev_stop_op(eth_dev);
1442 bnxt_free_switch_domain(bp);
1444 bnxt_uninit_resources(bp, false);
1446 bnxt_free_leds_info(bp);
1447 bnxt_free_cos_queues(bp);
1448 bnxt_free_link_info(bp);
1449 bnxt_free_pf_info(bp);
1450 bnxt_free_parent_info(bp);
1452 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1453 bp->tx_mem_zone = NULL;
1454 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1455 bp->rx_mem_zone = NULL;
1457 bnxt_hwrm_free_vf_info(bp);
1459 rte_free(bp->grp_info);
1460 bp->grp_info = NULL;
1465 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1468 struct bnxt *bp = eth_dev->data->dev_private;
1469 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1470 struct bnxt_vnic_info *vnic;
1471 struct bnxt_filter_info *filter, *temp_filter;
1474 if (is_bnxt_in_error(bp))
1478 * Loop through all VNICs from the specified filter flow pools to
1479 * remove the corresponding MAC addr filter
1481 for (i = 0; i < bp->nr_vnics; i++) {
1482 if (!(pool_mask & (1ULL << i)))
1485 vnic = &bp->vnic_info[i];
1486 filter = STAILQ_FIRST(&vnic->filter);
1488 temp_filter = STAILQ_NEXT(filter, next);
1489 if (filter->mac_index == index) {
1490 STAILQ_REMOVE(&vnic->filter, filter,
1491 bnxt_filter_info, next);
1492 bnxt_hwrm_clear_l2_filter(bp, filter);
1493 bnxt_free_filter(bp, filter);
1495 filter = temp_filter;
1500 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1501 struct rte_ether_addr *mac_addr, uint32_t index,
1504 struct bnxt_filter_info *filter;
1507 /* Attach requested MAC address to the new l2_filter */
1508 STAILQ_FOREACH(filter, &vnic->filter, next) {
1509 if (filter->mac_index == index) {
1511 "MAC addr already existed for pool %d\n",
1517 filter = bnxt_alloc_filter(bp);
1519 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1523 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1524 * if the MAC that's been programmed now is a different one, then,
1525 * copy that addr to filter->l2_addr
1528 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1529 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1531 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1533 filter->mac_index = index;
1534 if (filter->mac_index == 0)
1535 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1537 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1539 bnxt_free_filter(bp, filter);
1545 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1546 struct rte_ether_addr *mac_addr,
1547 uint32_t index, uint32_t pool)
1549 struct bnxt *bp = eth_dev->data->dev_private;
1550 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1553 rc = is_bnxt_in_error(bp);
1557 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1558 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1563 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1567 /* Filter settings will get applied when port is started */
1568 if (!eth_dev->data->dev_started)
1571 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1576 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1579 struct bnxt *bp = eth_dev->data->dev_private;
1580 struct rte_eth_link new;
1581 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1582 BNXT_MIN_LINK_WAIT_CNT;
1584 rc = is_bnxt_in_error(bp);
1588 memset(&new, 0, sizeof(new));
1590 /* Retrieve link info from hardware */
1591 rc = bnxt_get_hwrm_link_config(bp, &new);
1593 new.link_speed = ETH_LINK_SPEED_100M;
1594 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1596 "Failed to retrieve link rc = 0x%x!\n", rc);
1600 if (!wait_to_complete || new.link_status)
1603 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1606 /* Only single function PF can bring phy down.
1607 * When port is stopped, report link down for VF/MH/NPAR functions.
1609 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1610 memset(&new, 0, sizeof(new));
1613 /* Timed out or success */
1614 if (new.link_status != eth_dev->data->dev_link.link_status ||
1615 new.link_speed != eth_dev->data->dev_link.link_speed) {
1616 rte_eth_linkstatus_set(eth_dev, &new);
1618 rte_eth_dev_callback_process(eth_dev,
1619 RTE_ETH_EVENT_INTR_LSC,
1622 bnxt_print_link_info(eth_dev);
1628 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1630 struct bnxt *bp = eth_dev->data->dev_private;
1631 struct bnxt_vnic_info *vnic;
1635 rc = is_bnxt_in_error(bp);
1639 /* Filter settings will get applied when port is started */
1640 if (!eth_dev->data->dev_started)
1643 if (bp->vnic_info == NULL)
1646 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1648 old_flags = vnic->flags;
1649 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1650 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1652 vnic->flags = old_flags;
1657 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1659 struct bnxt *bp = eth_dev->data->dev_private;
1660 struct bnxt_vnic_info *vnic;
1664 rc = is_bnxt_in_error(bp);
1668 /* Filter settings will get applied when port is started */
1669 if (!eth_dev->data->dev_started)
1672 if (bp->vnic_info == NULL)
1675 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1677 old_flags = vnic->flags;
1678 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1679 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1681 vnic->flags = old_flags;
1686 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1688 struct bnxt *bp = eth_dev->data->dev_private;
1689 struct bnxt_vnic_info *vnic;
1693 rc = is_bnxt_in_error(bp);
1697 /* Filter settings will get applied when port is started */
1698 if (!eth_dev->data->dev_started)
1701 if (bp->vnic_info == NULL)
1704 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1706 old_flags = vnic->flags;
1707 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1708 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1710 vnic->flags = old_flags;
1715 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1717 struct bnxt *bp = eth_dev->data->dev_private;
1718 struct bnxt_vnic_info *vnic;
1722 rc = is_bnxt_in_error(bp);
1726 /* Filter settings will get applied when port is started */
1727 if (!eth_dev->data->dev_started)
1730 if (bp->vnic_info == NULL)
1733 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1735 old_flags = vnic->flags;
1736 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1737 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1739 vnic->flags = old_flags;
1744 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1745 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1747 if (qid >= bp->rx_nr_rings)
1750 return bp->eth_dev->data->rx_queues[qid];
1753 /* Return rxq corresponding to a given rss table ring/group ID. */
1754 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1756 struct bnxt_rx_queue *rxq;
1759 if (!BNXT_HAS_RING_GRPS(bp)) {
1760 for (i = 0; i < bp->rx_nr_rings; i++) {
1761 rxq = bp->eth_dev->data->rx_queues[i];
1762 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1766 for (i = 0; i < bp->rx_nr_rings; i++) {
1767 if (bp->grp_info[i].fw_grp_id == fwr)
1772 return INVALID_HW_RING_ID;
1775 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1776 struct rte_eth_rss_reta_entry64 *reta_conf,
1779 struct bnxt *bp = eth_dev->data->dev_private;
1780 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1781 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1782 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1786 rc = is_bnxt_in_error(bp);
1790 if (!vnic->rss_table)
1793 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1796 if (reta_size != tbl_size) {
1797 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1798 "(%d) must equal the size supported by the hardware "
1799 "(%d)\n", reta_size, tbl_size);
1803 for (i = 0; i < reta_size; i++) {
1804 struct bnxt_rx_queue *rxq;
1806 idx = i / RTE_RETA_GROUP_SIZE;
1807 sft = i % RTE_RETA_GROUP_SIZE;
1809 if (!(reta_conf[idx].mask & (1ULL << sft)))
1812 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1814 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1818 if (BNXT_CHIP_P5(bp)) {
1819 vnic->rss_table[i * 2] =
1820 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1821 vnic->rss_table[i * 2 + 1] =
1822 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1824 vnic->rss_table[i] =
1825 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1829 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1833 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1834 struct rte_eth_rss_reta_entry64 *reta_conf,
1837 struct bnxt *bp = eth_dev->data->dev_private;
1838 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1839 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1840 uint16_t idx, sft, i;
1843 rc = is_bnxt_in_error(bp);
1847 /* Retrieve from the default VNIC */
1850 if (!vnic->rss_table)
1853 if (reta_size != tbl_size) {
1854 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1855 "(%d) must equal the size supported by the hardware "
1856 "(%d)\n", reta_size, tbl_size);
1860 for (idx = 0, i = 0; i < reta_size; i++) {
1861 idx = i / RTE_RETA_GROUP_SIZE;
1862 sft = i % RTE_RETA_GROUP_SIZE;
1864 if (reta_conf[idx].mask & (1ULL << sft)) {
1867 if (BNXT_CHIP_P5(bp))
1868 qid = bnxt_rss_to_qid(bp,
1869 vnic->rss_table[i * 2]);
1871 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1873 if (qid == INVALID_HW_RING_ID) {
1874 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1877 reta_conf[idx].reta[sft] = qid;
1884 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1885 struct rte_eth_rss_conf *rss_conf)
1887 struct bnxt *bp = eth_dev->data->dev_private;
1888 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1889 struct bnxt_vnic_info *vnic;
1892 rc = is_bnxt_in_error(bp);
1897 * If RSS enablement were different than dev_configure,
1898 * then return -EINVAL
1900 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1901 if (!rss_conf->rss_hf)
1902 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1904 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1908 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1909 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
1913 /* Update the default RSS VNIC(s) */
1914 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1915 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1917 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
1918 ETH_RSS_LEVEL(rss_conf->rss_hf));
1921 * If hashkey is not specified, use the previously configured
1924 if (!rss_conf->rss_key)
1927 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1929 "Invalid hashkey length, should be 16 bytes\n");
1932 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1935 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1939 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1940 struct rte_eth_rss_conf *rss_conf)
1942 struct bnxt *bp = eth_dev->data->dev_private;
1943 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1945 uint32_t hash_types;
1947 rc = is_bnxt_in_error(bp);
1951 /* RSS configuration is the same for all VNICs */
1952 if (vnic && vnic->rss_hash_key) {
1953 if (rss_conf->rss_key) {
1954 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1955 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1956 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1959 hash_types = vnic->hash_type;
1960 rss_conf->rss_hf = 0;
1961 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1962 rss_conf->rss_hf |= ETH_RSS_IPV4;
1963 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1965 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1966 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1968 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1970 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1971 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1973 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1975 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1976 rss_conf->rss_hf |= ETH_RSS_IPV6;
1977 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1979 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1980 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1982 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1984 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1985 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1987 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1991 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
1995 "Unknown RSS config from firmware (%08x), RSS disabled",
2000 rss_conf->rss_hf = 0;
2005 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2006 struct rte_eth_fc_conf *fc_conf)
2008 struct bnxt *bp = dev->data->dev_private;
2009 struct rte_eth_link link_info;
2012 rc = is_bnxt_in_error(bp);
2016 rc = bnxt_get_hwrm_link_config(bp, &link_info);
2020 memset(fc_conf, 0, sizeof(*fc_conf));
2021 if (bp->link_info->auto_pause)
2022 fc_conf->autoneg = 1;
2023 switch (bp->link_info->pause) {
2025 fc_conf->mode = RTE_FC_NONE;
2027 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2028 fc_conf->mode = RTE_FC_TX_PAUSE;
2030 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2031 fc_conf->mode = RTE_FC_RX_PAUSE;
2033 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2034 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2035 fc_conf->mode = RTE_FC_FULL;
2041 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2042 struct rte_eth_fc_conf *fc_conf)
2044 struct bnxt *bp = dev->data->dev_private;
2047 rc = is_bnxt_in_error(bp);
2051 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2052 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2056 switch (fc_conf->mode) {
2058 bp->link_info->auto_pause = 0;
2059 bp->link_info->force_pause = 0;
2061 case RTE_FC_RX_PAUSE:
2062 if (fc_conf->autoneg) {
2063 bp->link_info->auto_pause =
2064 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2065 bp->link_info->force_pause = 0;
2067 bp->link_info->auto_pause = 0;
2068 bp->link_info->force_pause =
2069 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2072 case RTE_FC_TX_PAUSE:
2073 if (fc_conf->autoneg) {
2074 bp->link_info->auto_pause =
2075 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2076 bp->link_info->force_pause = 0;
2078 bp->link_info->auto_pause = 0;
2079 bp->link_info->force_pause =
2080 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2084 if (fc_conf->autoneg) {
2085 bp->link_info->auto_pause =
2086 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2087 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2088 bp->link_info->force_pause = 0;
2090 bp->link_info->auto_pause = 0;
2091 bp->link_info->force_pause =
2092 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2093 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2097 return bnxt_set_hwrm_link_config(bp, true);
2100 /* Add UDP tunneling port */
2102 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2103 struct rte_eth_udp_tunnel *udp_tunnel)
2105 struct bnxt *bp = eth_dev->data->dev_private;
2106 uint16_t tunnel_type = 0;
2109 rc = is_bnxt_in_error(bp);
2113 switch (udp_tunnel->prot_type) {
2114 case RTE_TUNNEL_TYPE_VXLAN:
2115 if (bp->vxlan_port_cnt) {
2116 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2117 udp_tunnel->udp_port);
2118 if (bp->vxlan_port != udp_tunnel->udp_port) {
2119 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2122 bp->vxlan_port_cnt++;
2126 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2127 bp->vxlan_port_cnt++;
2129 case RTE_TUNNEL_TYPE_GENEVE:
2130 if (bp->geneve_port_cnt) {
2131 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2132 udp_tunnel->udp_port);
2133 if (bp->geneve_port != udp_tunnel->udp_port) {
2134 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2137 bp->geneve_port_cnt++;
2141 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2142 bp->geneve_port_cnt++;
2145 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2148 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2154 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2155 struct rte_eth_udp_tunnel *udp_tunnel)
2157 struct bnxt *bp = eth_dev->data->dev_private;
2158 uint16_t tunnel_type = 0;
2162 rc = is_bnxt_in_error(bp);
2166 switch (udp_tunnel->prot_type) {
2167 case RTE_TUNNEL_TYPE_VXLAN:
2168 if (!bp->vxlan_port_cnt) {
2169 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2172 if (bp->vxlan_port != udp_tunnel->udp_port) {
2173 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2174 udp_tunnel->udp_port, bp->vxlan_port);
2177 if (--bp->vxlan_port_cnt)
2181 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2182 port = bp->vxlan_fw_dst_port_id;
2184 case RTE_TUNNEL_TYPE_GENEVE:
2185 if (!bp->geneve_port_cnt) {
2186 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2189 if (bp->geneve_port != udp_tunnel->udp_port) {
2190 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2191 udp_tunnel->udp_port, bp->geneve_port);
2194 if (--bp->geneve_port_cnt)
2198 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2199 port = bp->geneve_fw_dst_port_id;
2202 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2206 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2210 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2212 struct bnxt_filter_info *filter;
2213 struct bnxt_vnic_info *vnic;
2215 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2217 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2218 filter = STAILQ_FIRST(&vnic->filter);
2220 /* Search for this matching MAC+VLAN filter */
2221 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2222 /* Delete the filter */
2223 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2226 STAILQ_REMOVE(&vnic->filter, filter,
2227 bnxt_filter_info, next);
2228 bnxt_free_filter(bp, filter);
2230 "Deleted vlan filter for %d\n",
2234 filter = STAILQ_NEXT(filter, next);
2239 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2241 struct bnxt_filter_info *filter;
2242 struct bnxt_vnic_info *vnic;
2244 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2245 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2246 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2248 /* Implementation notes on the use of VNIC in this command:
2250 * By default, these filters belong to default vnic for the function.
2251 * Once these filters are set up, only destination VNIC can be modified.
2252 * If the destination VNIC is not specified in this command,
2253 * then the HWRM shall only create an l2 context id.
2256 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2257 filter = STAILQ_FIRST(&vnic->filter);
2258 /* Check if the VLAN has already been added */
2260 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2263 filter = STAILQ_NEXT(filter, next);
2266 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2267 * command to create MAC+VLAN filter with the right flags, enables set.
2269 filter = bnxt_alloc_filter(bp);
2272 "MAC/VLAN filter alloc failed\n");
2275 /* MAC + VLAN ID filter */
2276 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2277 * untagged packets are received
2279 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2280 * packets and only the programmed vlan's packets are received
2282 filter->l2_ivlan = vlan_id;
2283 filter->l2_ivlan_mask = 0x0FFF;
2284 filter->enables |= en;
2285 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2287 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2289 /* Free the newly allocated filter as we were
2290 * not able to create the filter in hardware.
2292 bnxt_free_filter(bp, filter);
2296 filter->mac_index = 0;
2297 /* Add this new filter to the list */
2299 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2301 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2304 "Added Vlan filter for %d\n", vlan_id);
2308 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2309 uint16_t vlan_id, int on)
2311 struct bnxt *bp = eth_dev->data->dev_private;
2314 rc = is_bnxt_in_error(bp);
2318 if (!eth_dev->data->dev_started) {
2319 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2323 /* These operations apply to ALL existing MAC/VLAN filters */
2325 return bnxt_add_vlan_filter(bp, vlan_id);
2327 return bnxt_del_vlan_filter(bp, vlan_id);
2330 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2331 struct bnxt_vnic_info *vnic)
2333 struct bnxt_filter_info *filter;
2336 filter = STAILQ_FIRST(&vnic->filter);
2338 if (filter->mac_index == 0 &&
2339 !memcmp(filter->l2_addr, bp->mac_addr,
2340 RTE_ETHER_ADDR_LEN)) {
2341 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2343 STAILQ_REMOVE(&vnic->filter, filter,
2344 bnxt_filter_info, next);
2345 bnxt_free_filter(bp, filter);
2349 filter = STAILQ_NEXT(filter, next);
2355 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2357 struct bnxt_vnic_info *vnic;
2361 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2362 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2363 /* Remove any VLAN filters programmed */
2364 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2365 bnxt_del_vlan_filter(bp, i);
2367 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2371 /* Default filter will allow packets that match the
2372 * dest mac. So, it has to be deleted, otherwise, we
2373 * will endup receiving vlan packets for which the
2374 * filter is not programmed, when hw-vlan-filter
2375 * configuration is ON
2377 bnxt_del_dflt_mac_filter(bp, vnic);
2378 /* This filter will allow only untagged packets */
2379 bnxt_add_vlan_filter(bp, 0);
2381 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2382 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2387 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2389 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2393 /* Destroy vnic filters and vnic */
2394 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2395 DEV_RX_OFFLOAD_VLAN_FILTER) {
2396 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2397 bnxt_del_vlan_filter(bp, i);
2399 bnxt_del_dflt_mac_filter(bp, vnic);
2401 rc = bnxt_hwrm_vnic_free(bp, vnic);
2405 rte_free(vnic->fw_grp_ids);
2406 vnic->fw_grp_ids = NULL;
2408 vnic->rx_queue_cnt = 0;
2414 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2416 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2419 /* Destroy, recreate and reconfigure the default vnic */
2420 rc = bnxt_free_one_vnic(bp, 0);
2424 /* default vnic 0 */
2425 rc = bnxt_setup_one_vnic(bp, 0);
2429 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2430 DEV_RX_OFFLOAD_VLAN_FILTER) {
2431 rc = bnxt_add_vlan_filter(bp, 0);
2434 rc = bnxt_restore_vlan_filters(bp);
2438 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2443 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2447 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2448 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2454 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2456 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2457 struct bnxt *bp = dev->data->dev_private;
2460 rc = is_bnxt_in_error(bp);
2464 /* Filter settings will get applied when port is started */
2465 if (!dev->data->dev_started)
2468 if (mask & ETH_VLAN_FILTER_MASK) {
2469 /* Enable or disable VLAN filtering */
2470 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2475 if (mask & ETH_VLAN_STRIP_MASK) {
2476 /* Enable or disable VLAN stripping */
2477 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2482 if (mask & ETH_VLAN_EXTEND_MASK) {
2483 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2484 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2486 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2493 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2496 struct bnxt *bp = dev->data->dev_private;
2497 int qinq = dev->data->dev_conf.rxmode.offloads &
2498 DEV_RX_OFFLOAD_VLAN_EXTEND;
2500 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2501 vlan_type != ETH_VLAN_TYPE_OUTER) {
2503 "Unsupported vlan type.");
2508 "QinQ not enabled. Needs to be ON as we can "
2509 "accelerate only outer vlan\n");
2513 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2515 case RTE_ETHER_TYPE_QINQ:
2517 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2519 case RTE_ETHER_TYPE_VLAN:
2521 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2523 case RTE_ETHER_TYPE_QINQ1:
2525 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2527 case RTE_ETHER_TYPE_QINQ2:
2529 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2531 case RTE_ETHER_TYPE_QINQ3:
2533 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2536 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2539 bp->outer_tpid_bd |= tpid;
2540 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2541 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2543 "Can accelerate only outer vlan in QinQ\n");
2551 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2552 struct rte_ether_addr *addr)
2554 struct bnxt *bp = dev->data->dev_private;
2555 /* Default Filter is tied to VNIC 0 */
2556 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2559 rc = is_bnxt_in_error(bp);
2563 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2566 if (rte_is_zero_ether_addr(addr))
2569 /* Filter settings will get applied when port is started */
2570 if (!dev->data->dev_started)
2573 /* Check if the requested MAC is already added */
2574 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2577 /* Destroy filter and re-create it */
2578 bnxt_del_dflt_mac_filter(bp, vnic);
2580 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2581 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2582 /* This filter will allow only untagged packets */
2583 rc = bnxt_add_vlan_filter(bp, 0);
2585 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2588 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2593 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2594 struct rte_ether_addr *mc_addr_set,
2595 uint32_t nb_mc_addr)
2597 struct bnxt *bp = eth_dev->data->dev_private;
2598 char *mc_addr_list = (char *)mc_addr_set;
2599 struct bnxt_vnic_info *vnic;
2600 uint32_t off = 0, i = 0;
2603 rc = is_bnxt_in_error(bp);
2607 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2609 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2610 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2614 /* TODO Check for Duplicate mcast addresses */
2615 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2616 for (i = 0; i < nb_mc_addr; i++) {
2617 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2618 RTE_ETHER_ADDR_LEN);
2619 off += RTE_ETHER_ADDR_LEN;
2622 vnic->mc_addr_cnt = i;
2623 if (vnic->mc_addr_cnt)
2624 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2626 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2629 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2633 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2635 struct bnxt *bp = dev->data->dev_private;
2636 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2637 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2638 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2639 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2642 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2643 fw_major, fw_minor, fw_updt, fw_rsvd);
2645 ret += 1; /* add the size of '\0' */
2646 if (fw_size < (uint32_t)ret)
2653 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2654 struct rte_eth_rxq_info *qinfo)
2656 struct bnxt *bp = dev->data->dev_private;
2657 struct bnxt_rx_queue *rxq;
2659 if (is_bnxt_in_error(bp))
2662 rxq = dev->data->rx_queues[queue_id];
2664 qinfo->mp = rxq->mb_pool;
2665 qinfo->scattered_rx = dev->data->scattered_rx;
2666 qinfo->nb_desc = rxq->nb_rx_desc;
2668 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2669 qinfo->conf.rx_drop_en = rxq->drop_en;
2670 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2671 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2675 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2676 struct rte_eth_txq_info *qinfo)
2678 struct bnxt *bp = dev->data->dev_private;
2679 struct bnxt_tx_queue *txq;
2681 if (is_bnxt_in_error(bp))
2684 txq = dev->data->tx_queues[queue_id];
2686 qinfo->nb_desc = txq->nb_tx_desc;
2688 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2689 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2690 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2692 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2693 qinfo->conf.tx_rs_thresh = 0;
2694 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2695 qinfo->conf.offloads = txq->offloads;
2698 static const struct {
2699 eth_rx_burst_t pkt_burst;
2701 } bnxt_rx_burst_info[] = {
2702 {bnxt_recv_pkts, "Scalar"},
2703 #if defined(RTE_ARCH_X86)
2704 {bnxt_recv_pkts_vec, "Vector SSE"},
2705 #elif defined(RTE_ARCH_ARM64)
2706 {bnxt_recv_pkts_vec, "Vector Neon"},
2711 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2712 struct rte_eth_burst_mode *mode)
2714 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2717 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2718 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2719 snprintf(mode->info, sizeof(mode->info), "%s",
2720 bnxt_rx_burst_info[i].info);
2728 static const struct {
2729 eth_tx_burst_t pkt_burst;
2731 } bnxt_tx_burst_info[] = {
2732 {bnxt_xmit_pkts, "Scalar"},
2733 #if defined(RTE_ARCH_X86)
2734 {bnxt_xmit_pkts_vec, "Vector SSE"},
2735 #elif defined(RTE_ARCH_ARM64)
2736 {bnxt_xmit_pkts_vec, "Vector Neon"},
2741 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2742 struct rte_eth_burst_mode *mode)
2744 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2747 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2748 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2749 snprintf(mode->info, sizeof(mode->info), "%s",
2750 bnxt_tx_burst_info[i].info);
2758 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2760 struct bnxt *bp = eth_dev->data->dev_private;
2761 uint32_t new_pkt_size;
2765 rc = is_bnxt_in_error(bp);
2769 /* Exit if receive queues are not configured yet */
2770 if (!eth_dev->data->nb_rx_queues)
2773 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2774 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2777 * Disallow any MTU change that would require scattered receive support
2778 * if it is not already enabled.
2780 if (eth_dev->data->dev_started &&
2781 !eth_dev->data->scattered_rx &&
2783 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2785 "MTU change would require scattered rx support. ");
2786 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2790 if (new_mtu > RTE_ETHER_MTU) {
2791 bp->flags |= BNXT_FLAG_JUMBO;
2792 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2793 DEV_RX_OFFLOAD_JUMBO_FRAME;
2795 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2796 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2797 bp->flags &= ~BNXT_FLAG_JUMBO;
2800 /* Is there a change in mtu setting? */
2801 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2804 for (i = 0; i < bp->nr_vnics; i++) {
2805 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2808 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2809 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2813 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2814 size -= RTE_PKTMBUF_HEADROOM;
2816 if (size < new_mtu) {
2817 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2824 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2826 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2832 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2834 struct bnxt *bp = dev->data->dev_private;
2835 uint16_t vlan = bp->vlan;
2838 rc = is_bnxt_in_error(bp);
2842 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2844 "PVID cannot be modified for this function\n");
2847 bp->vlan = on ? pvid : 0;
2849 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2856 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2858 struct bnxt *bp = dev->data->dev_private;
2861 rc = is_bnxt_in_error(bp);
2865 return bnxt_hwrm_port_led_cfg(bp, true);
2869 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2871 struct bnxt *bp = dev->data->dev_private;
2874 rc = is_bnxt_in_error(bp);
2878 return bnxt_hwrm_port_led_cfg(bp, false);
2882 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2884 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2885 uint32_t desc = 0, raw_cons = 0, cons;
2886 struct bnxt_cp_ring_info *cpr;
2887 struct bnxt_rx_queue *rxq;
2888 struct rx_pkt_cmpl *rxcmp;
2891 rc = is_bnxt_in_error(bp);
2895 rxq = dev->data->rx_queues[rx_queue_id];
2897 raw_cons = cpr->cp_raw_cons;
2900 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2901 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2902 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2904 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2916 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2918 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2919 struct bnxt_rx_ring_info *rxr;
2920 struct bnxt_cp_ring_info *cpr;
2921 struct rte_mbuf *rx_buf;
2922 struct rx_pkt_cmpl *rxcmp;
2923 uint32_t cons, cp_cons;
2929 rc = is_bnxt_in_error(rxq->bp);
2936 if (offset >= rxq->nb_rx_desc)
2939 cons = RING_CMP(cpr->cp_ring_struct, offset);
2940 cp_cons = cpr->cp_raw_cons;
2941 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2943 if (cons > cp_cons) {
2944 if (CMPL_VALID(rxcmp, cpr->valid))
2945 return RTE_ETH_RX_DESC_DONE;
2947 if (CMPL_VALID(rxcmp, !cpr->valid))
2948 return RTE_ETH_RX_DESC_DONE;
2950 rx_buf = rxr->rx_buf_ring[cons];
2951 if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2952 return RTE_ETH_RX_DESC_UNAVAIL;
2955 return RTE_ETH_RX_DESC_AVAIL;
2959 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2961 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2962 struct bnxt_tx_ring_info *txr;
2963 struct bnxt_cp_ring_info *cpr;
2964 struct bnxt_sw_tx_bd *tx_buf;
2965 struct tx_pkt_cmpl *txcmp;
2966 uint32_t cons, cp_cons;
2972 rc = is_bnxt_in_error(txq->bp);
2979 if (offset >= txq->nb_tx_desc)
2982 cons = RING_CMP(cpr->cp_ring_struct, offset);
2983 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2984 cp_cons = cpr->cp_raw_cons;
2986 if (cons > cp_cons) {
2987 if (CMPL_VALID(txcmp, cpr->valid))
2988 return RTE_ETH_TX_DESC_UNAVAIL;
2990 if (CMPL_VALID(txcmp, !cpr->valid))
2991 return RTE_ETH_TX_DESC_UNAVAIL;
2993 tx_buf = &txr->tx_buf_ring[cons];
2994 if (tx_buf->mbuf == NULL)
2995 return RTE_ETH_TX_DESC_DONE;
2997 return RTE_ETH_TX_DESC_FULL;
3001 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3002 enum rte_filter_type filter_type,
3003 enum rte_filter_op filter_op, void *arg)
3005 struct bnxt *bp = dev->data->dev_private;
3011 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3012 struct bnxt_representor *vfr = dev->data->dev_private;
3013 bp = vfr->parent_dev->data->dev_private;
3014 /* parent is deleted while children are still valid */
3016 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3024 ret = is_bnxt_in_error(bp);
3028 switch (filter_type) {
3029 case RTE_ETH_FILTER_GENERIC:
3030 if (filter_op != RTE_ETH_FILTER_GET)
3033 /* PMD supports thread-safe flow operations. rte_flow API
3034 * functions can avoid mutex for multi-thread safety.
3036 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3038 if (BNXT_TRUFLOW_EN(bp))
3039 *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3041 *(const void **)arg = &bnxt_flow_ops;
3045 "Filter type (%d) not supported", filter_type);
3052 static const uint32_t *
3053 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3055 static const uint32_t ptypes[] = {
3056 RTE_PTYPE_L2_ETHER_VLAN,
3057 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3058 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3062 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3063 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3064 RTE_PTYPE_INNER_L4_ICMP,
3065 RTE_PTYPE_INNER_L4_TCP,
3066 RTE_PTYPE_INNER_L4_UDP,
3070 if (!dev->rx_pkt_burst)
3076 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3079 uint32_t reg_base = *reg_arr & 0xfffff000;
3083 for (i = 0; i < count; i++) {
3084 if ((reg_arr[i] & 0xfffff000) != reg_base)
3087 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3088 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3092 static int bnxt_map_ptp_regs(struct bnxt *bp)
3094 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3098 reg_arr = ptp->rx_regs;
3099 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3103 reg_arr = ptp->tx_regs;
3104 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3108 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3109 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3111 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3112 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3117 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3119 rte_write32(0, (uint8_t *)bp->bar0 +
3120 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3121 rte_write32(0, (uint8_t *)bp->bar0 +
3122 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3125 static uint64_t bnxt_cc_read(struct bnxt *bp)
3129 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3130 BNXT_GRCPF_REG_SYNC_TIME));
3131 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3132 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3136 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3138 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3141 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3142 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3143 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3146 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3147 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3148 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3149 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3150 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3151 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3156 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3158 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3159 struct bnxt_pf_info *pf = bp->pf;
3166 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3167 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3168 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3171 port_id = pf->port_id;
3172 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3173 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3175 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3176 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3177 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3178 /* bnxt_clr_rx_ts(bp); TBD */
3182 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3183 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3184 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3185 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3191 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3194 struct bnxt *bp = dev->data->dev_private;
3195 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3200 ns = rte_timespec_to_ns(ts);
3201 /* Set the timecounters to a new value. */
3208 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3210 struct bnxt *bp = dev->data->dev_private;
3211 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3212 uint64_t ns, systime_cycles = 0;
3218 if (BNXT_CHIP_P5(bp))
3219 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3222 systime_cycles = bnxt_cc_read(bp);
3224 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3225 *ts = rte_ns_to_timespec(ns);
3230 bnxt_timesync_enable(struct rte_eth_dev *dev)
3232 struct bnxt *bp = dev->data->dev_private;
3233 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3241 ptp->tx_tstamp_en = 1;
3242 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3244 rc = bnxt_hwrm_ptp_cfg(bp);
3248 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3249 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3250 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3252 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3253 ptp->tc.cc_shift = shift;
3254 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3256 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3257 ptp->rx_tstamp_tc.cc_shift = shift;
3258 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3260 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3261 ptp->tx_tstamp_tc.cc_shift = shift;
3262 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3264 if (!BNXT_CHIP_P5(bp))
3265 bnxt_map_ptp_regs(bp);
3271 bnxt_timesync_disable(struct rte_eth_dev *dev)
3273 struct bnxt *bp = dev->data->dev_private;
3274 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3280 ptp->tx_tstamp_en = 0;
3283 bnxt_hwrm_ptp_cfg(bp);
3285 if (!BNXT_CHIP_P5(bp))
3286 bnxt_unmap_ptp_regs(bp);
3292 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3293 struct timespec *timestamp,
3294 uint32_t flags __rte_unused)
3296 struct bnxt *bp = dev->data->dev_private;
3297 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3298 uint64_t rx_tstamp_cycles = 0;
3304 if (BNXT_CHIP_P5(bp))
3305 rx_tstamp_cycles = ptp->rx_timestamp;
3307 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3309 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3310 *timestamp = rte_ns_to_timespec(ns);
3315 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3316 struct timespec *timestamp)
3318 struct bnxt *bp = dev->data->dev_private;
3319 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3320 uint64_t tx_tstamp_cycles = 0;
3327 if (BNXT_CHIP_P5(bp))
3328 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3331 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3333 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3334 *timestamp = rte_ns_to_timespec(ns);
3340 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3342 struct bnxt *bp = dev->data->dev_private;
3343 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3348 ptp->tc.nsec += delta;
3354 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3356 struct bnxt *bp = dev->data->dev_private;
3358 uint32_t dir_entries;
3359 uint32_t entry_length;
3361 rc = is_bnxt_in_error(bp);
3365 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3366 bp->pdev->addr.domain, bp->pdev->addr.bus,
3367 bp->pdev->addr.devid, bp->pdev->addr.function);
3369 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3373 return dir_entries * entry_length;
3377 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3378 struct rte_dev_eeprom_info *in_eeprom)
3380 struct bnxt *bp = dev->data->dev_private;
3385 rc = is_bnxt_in_error(bp);
3389 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3390 bp->pdev->addr.domain, bp->pdev->addr.bus,
3391 bp->pdev->addr.devid, bp->pdev->addr.function,
3392 in_eeprom->offset, in_eeprom->length);
3394 if (in_eeprom->offset == 0) /* special offset value to get directory */
3395 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3398 index = in_eeprom->offset >> 24;
3399 offset = in_eeprom->offset & 0xffffff;
3402 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3403 in_eeprom->length, in_eeprom->data);
3408 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3411 case BNX_DIR_TYPE_CHIMP_PATCH:
3412 case BNX_DIR_TYPE_BOOTCODE:
3413 case BNX_DIR_TYPE_BOOTCODE_2:
3414 case BNX_DIR_TYPE_APE_FW:
3415 case BNX_DIR_TYPE_APE_PATCH:
3416 case BNX_DIR_TYPE_KONG_FW:
3417 case BNX_DIR_TYPE_KONG_PATCH:
3418 case BNX_DIR_TYPE_BONO_FW:
3419 case BNX_DIR_TYPE_BONO_PATCH:
3427 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3430 case BNX_DIR_TYPE_AVS:
3431 case BNX_DIR_TYPE_EXP_ROM_MBA:
3432 case BNX_DIR_TYPE_PCIE:
3433 case BNX_DIR_TYPE_TSCF_UCODE:
3434 case BNX_DIR_TYPE_EXT_PHY:
3435 case BNX_DIR_TYPE_CCM:
3436 case BNX_DIR_TYPE_ISCSI_BOOT:
3437 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3438 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3446 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3448 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3449 bnxt_dir_type_is_other_exec_format(dir_type);
3453 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3454 struct rte_dev_eeprom_info *in_eeprom)
3456 struct bnxt *bp = dev->data->dev_private;
3457 uint8_t index, dir_op;
3458 uint16_t type, ext, ordinal, attr;
3461 rc = is_bnxt_in_error(bp);
3465 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3466 bp->pdev->addr.domain, bp->pdev->addr.bus,
3467 bp->pdev->addr.devid, bp->pdev->addr.function,
3468 in_eeprom->offset, in_eeprom->length);
3471 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3475 type = in_eeprom->magic >> 16;
3477 if (type == 0xffff) { /* special value for directory operations */
3478 index = in_eeprom->magic & 0xff;
3479 dir_op = in_eeprom->magic >> 8;
3483 case 0x0e: /* erase */
3484 if (in_eeprom->offset != ~in_eeprom->magic)
3486 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3492 /* Create or re-write an NVM item: */
3493 if (bnxt_dir_type_is_executable(type) == true)
3495 ext = in_eeprom->magic & 0xffff;
3496 ordinal = in_eeprom->offset >> 16;
3497 attr = in_eeprom->offset & 0xffff;
3499 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3500 in_eeprom->data, in_eeprom->length);
3507 static const struct eth_dev_ops bnxt_dev_ops = {
3508 .dev_infos_get = bnxt_dev_info_get_op,
3509 .dev_close = bnxt_dev_close_op,
3510 .dev_configure = bnxt_dev_configure_op,
3511 .dev_start = bnxt_dev_start_op,
3512 .dev_stop = bnxt_dev_stop_op,
3513 .dev_set_link_up = bnxt_dev_set_link_up_op,
3514 .dev_set_link_down = bnxt_dev_set_link_down_op,
3515 .stats_get = bnxt_stats_get_op,
3516 .stats_reset = bnxt_stats_reset_op,
3517 .rx_queue_setup = bnxt_rx_queue_setup_op,
3518 .rx_queue_release = bnxt_rx_queue_release_op,
3519 .tx_queue_setup = bnxt_tx_queue_setup_op,
3520 .tx_queue_release = bnxt_tx_queue_release_op,
3521 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3522 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3523 .reta_update = bnxt_reta_update_op,
3524 .reta_query = bnxt_reta_query_op,
3525 .rss_hash_update = bnxt_rss_hash_update_op,
3526 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3527 .link_update = bnxt_link_update_op,
3528 .promiscuous_enable = bnxt_promiscuous_enable_op,
3529 .promiscuous_disable = bnxt_promiscuous_disable_op,
3530 .allmulticast_enable = bnxt_allmulticast_enable_op,
3531 .allmulticast_disable = bnxt_allmulticast_disable_op,
3532 .mac_addr_add = bnxt_mac_addr_add_op,
3533 .mac_addr_remove = bnxt_mac_addr_remove_op,
3534 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3535 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3536 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3537 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3538 .vlan_filter_set = bnxt_vlan_filter_set_op,
3539 .vlan_offload_set = bnxt_vlan_offload_set_op,
3540 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3541 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3542 .mtu_set = bnxt_mtu_set_op,
3543 .mac_addr_set = bnxt_set_default_mac_addr_op,
3544 .xstats_get = bnxt_dev_xstats_get_op,
3545 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3546 .xstats_reset = bnxt_dev_xstats_reset_op,
3547 .fw_version_get = bnxt_fw_version_get,
3548 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3549 .rxq_info_get = bnxt_rxq_info_get_op,
3550 .txq_info_get = bnxt_txq_info_get_op,
3551 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3552 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3553 .dev_led_on = bnxt_dev_led_on_op,
3554 .dev_led_off = bnxt_dev_led_off_op,
3555 .rx_queue_start = bnxt_rx_queue_start,
3556 .rx_queue_stop = bnxt_rx_queue_stop,
3557 .tx_queue_start = bnxt_tx_queue_start,
3558 .tx_queue_stop = bnxt_tx_queue_stop,
3559 .filter_ctrl = bnxt_filter_ctrl_op,
3560 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3561 .get_eeprom_length = bnxt_get_eeprom_length_op,
3562 .get_eeprom = bnxt_get_eeprom_op,
3563 .set_eeprom = bnxt_set_eeprom_op,
3564 .timesync_enable = bnxt_timesync_enable,
3565 .timesync_disable = bnxt_timesync_disable,
3566 .timesync_read_time = bnxt_timesync_read_time,
3567 .timesync_write_time = bnxt_timesync_write_time,
3568 .timesync_adjust_time = bnxt_timesync_adjust_time,
3569 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3570 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3573 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3577 /* Only pre-map the reset GRC registers using window 3 */
3578 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3579 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3581 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3586 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3588 struct bnxt_error_recovery_info *info = bp->recovery_info;
3589 uint32_t reg_base = 0xffffffff;
3592 /* Only pre-map the monitoring GRC registers using window 2 */
3593 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3594 uint32_t reg = info->status_regs[i];
3596 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3599 if (reg_base == 0xffffffff)
3600 reg_base = reg & 0xfffff000;
3601 if ((reg & 0xfffff000) != reg_base)
3604 /* Use mask 0xffc as the Lower 2 bits indicates
3605 * address space location
3607 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3611 if (reg_base == 0xffffffff)
3614 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3615 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3620 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3622 struct bnxt_error_recovery_info *info = bp->recovery_info;
3623 uint32_t delay = info->delay_after_reset[index];
3624 uint32_t val = info->reset_reg_val[index];
3625 uint32_t reg = info->reset_reg[index];
3626 uint32_t type, offset;
3628 type = BNXT_FW_STATUS_REG_TYPE(reg);
3629 offset = BNXT_FW_STATUS_REG_OFF(reg);
3632 case BNXT_FW_STATUS_REG_TYPE_CFG:
3633 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3635 case BNXT_FW_STATUS_REG_TYPE_GRC:
3636 offset = bnxt_map_reset_regs(bp, offset);
3637 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3639 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3640 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3643 /* wait on a specific interval of time until core reset is complete */
3645 rte_delay_ms(delay);
3648 static void bnxt_dev_cleanup(struct bnxt *bp)
3650 bp->eth_dev->data->dev_link.link_status = 0;
3651 bp->link_info->link_up = 0;
3652 if (bp->eth_dev->data->dev_started)
3653 bnxt_dev_stop_op(bp->eth_dev);
3655 bnxt_uninit_resources(bp, true);
3658 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3660 struct rte_eth_dev *dev = bp->eth_dev;
3661 struct rte_vlan_filter_conf *vfc;
3665 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3666 vfc = &dev->data->vlan_filter_conf;
3667 vidx = vlan_id / 64;
3668 vbit = vlan_id % 64;
3670 /* Each bit corresponds to a VLAN id */
3671 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3672 rc = bnxt_add_vlan_filter(bp, vlan_id);
3681 static int bnxt_restore_mac_filters(struct bnxt *bp)
3683 struct rte_eth_dev *dev = bp->eth_dev;
3684 struct rte_eth_dev_info dev_info;
3685 struct rte_ether_addr *addr;
3691 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3694 rc = bnxt_dev_info_get_op(dev, &dev_info);
3698 /* replay MAC address configuration */
3699 for (i = 1; i < dev_info.max_mac_addrs; i++) {
3700 addr = &dev->data->mac_addrs[i];
3702 /* skip zero address */
3703 if (rte_is_zero_ether_addr(addr))
3707 pool_mask = dev->data->mac_pool_sel[i];
3710 if (pool_mask & 1ULL) {
3711 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3717 } while (pool_mask);
3723 static int bnxt_restore_filters(struct bnxt *bp)
3725 struct rte_eth_dev *dev = bp->eth_dev;
3728 if (dev->data->all_multicast) {
3729 ret = bnxt_allmulticast_enable_op(dev);
3733 if (dev->data->promiscuous) {
3734 ret = bnxt_promiscuous_enable_op(dev);
3739 ret = bnxt_restore_mac_filters(bp);
3743 ret = bnxt_restore_vlan_filters(bp);
3744 /* TODO restore other filters as well */
3748 static void bnxt_dev_recover(void *arg)
3750 struct bnxt *bp = arg;
3751 int timeout = bp->fw_reset_max_msecs;
3754 /* Clear Error flag so that device re-init should happen */
3755 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3758 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
3761 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3762 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3763 } while (rc && timeout);
3766 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3770 rc = bnxt_init_resources(bp, true);
3773 "Failed to initialize resources after reset\n");
3776 /* clear reset flag as the device is initialized now */
3777 bp->flags &= ~BNXT_FLAG_FW_RESET;
3779 rc = bnxt_dev_start_op(bp->eth_dev);
3781 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3785 rc = bnxt_restore_filters(bp);
3789 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3792 bnxt_dev_stop_op(bp->eth_dev);
3794 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3795 bnxt_uninit_resources(bp, false);
3796 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3799 void bnxt_dev_reset_and_resume(void *arg)
3801 struct bnxt *bp = arg;
3804 bnxt_dev_cleanup(bp);
3806 bnxt_wait_for_device_shutdown(bp);
3808 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3809 bnxt_dev_recover, (void *)bp);
3811 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3814 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3816 struct bnxt_error_recovery_info *info = bp->recovery_info;
3817 uint32_t reg = info->status_regs[index];
3818 uint32_t type, offset, val = 0;
3820 type = BNXT_FW_STATUS_REG_TYPE(reg);
3821 offset = BNXT_FW_STATUS_REG_OFF(reg);
3824 case BNXT_FW_STATUS_REG_TYPE_CFG:
3825 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3827 case BNXT_FW_STATUS_REG_TYPE_GRC:
3828 offset = info->mapped_status_regs[index];
3830 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3831 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3839 static int bnxt_fw_reset_all(struct bnxt *bp)
3841 struct bnxt_error_recovery_info *info = bp->recovery_info;
3845 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3846 /* Reset through master function driver */
3847 for (i = 0; i < info->reg_array_cnt; i++)
3848 bnxt_write_fw_reset_reg(bp, i);
3849 /* Wait for time specified by FW after triggering reset */
3850 rte_delay_ms(info->master_func_wait_period_after_reset);
3851 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3852 /* Reset with the help of Kong processor */
3853 rc = bnxt_hwrm_fw_reset(bp);
3855 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3861 static void bnxt_fw_reset_cb(void *arg)
3863 struct bnxt *bp = arg;
3864 struct bnxt_error_recovery_info *info = bp->recovery_info;
3867 /* Only Master function can do FW reset */
3868 if (bnxt_is_master_func(bp) &&
3869 bnxt_is_recovery_enabled(bp)) {
3870 rc = bnxt_fw_reset_all(bp);
3872 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3877 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3878 * EXCEPTION_FATAL_ASYNC event to all the functions
3879 * (including MASTER FUNC). After receiving this Async, all the active
3880 * drivers should treat this case as FW initiated recovery
3882 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3883 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3884 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3886 /* To recover from error */
3887 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3892 /* Driver should poll FW heartbeat, reset_counter with the frequency
3893 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3894 * When the driver detects heartbeat stop or change in reset_counter,
3895 * it has to trigger a reset to recover from the error condition.
3896 * A “master PF” is the function who will have the privilege to
3897 * initiate the chimp reset. The master PF will be elected by the
3898 * firmware and will be notified through async message.
3900 static void bnxt_check_fw_health(void *arg)
3902 struct bnxt *bp = arg;
3903 struct bnxt_error_recovery_info *info = bp->recovery_info;
3904 uint32_t val = 0, wait_msec;
3906 if (!info || !bnxt_is_recovery_enabled(bp) ||
3907 is_bnxt_in_error(bp))
3910 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3911 if (val == info->last_heart_beat)
3914 info->last_heart_beat = val;
3916 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3917 if (val != info->last_reset_counter)
3920 info->last_reset_counter = val;
3922 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3923 bnxt_check_fw_health, (void *)bp);
3927 /* Stop DMA to/from device */
3928 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3929 bp->flags |= BNXT_FLAG_FW_RESET;
3931 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3933 if (bnxt_is_master_func(bp))
3934 wait_msec = info->master_func_wait_period;
3936 wait_msec = info->normal_func_wait_period;
3938 rte_eal_alarm_set(US_PER_MS * wait_msec,
3939 bnxt_fw_reset_cb, (void *)bp);
3942 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3944 uint32_t polling_freq;
3946 pthread_mutex_lock(&bp->health_check_lock);
3948 if (!bnxt_is_recovery_enabled(bp))
3951 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
3954 polling_freq = bp->recovery_info->driver_polling_freq;
3956 rte_eal_alarm_set(US_PER_MS * polling_freq,
3957 bnxt_check_fw_health, (void *)bp);
3958 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3961 pthread_mutex_unlock(&bp->health_check_lock);
3964 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
3966 if (!bnxt_is_recovery_enabled(bp))
3969 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
3970 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3973 static bool bnxt_vf_pciid(uint16_t device_id)
3975 switch (device_id) {
3976 case BROADCOM_DEV_ID_57304_VF:
3977 case BROADCOM_DEV_ID_57406_VF:
3978 case BROADCOM_DEV_ID_5731X_VF:
3979 case BROADCOM_DEV_ID_5741X_VF:
3980 case BROADCOM_DEV_ID_57414_VF:
3981 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
3982 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
3983 case BROADCOM_DEV_ID_58802_VF:
3984 case BROADCOM_DEV_ID_57500_VF1:
3985 case BROADCOM_DEV_ID_57500_VF2:
3986 case BROADCOM_DEV_ID_58818_VF:
3994 /* Phase 5 device */
3995 static bool bnxt_p5_device(uint16_t device_id)
3997 switch (device_id) {
3998 case BROADCOM_DEV_ID_57508:
3999 case BROADCOM_DEV_ID_57504:
4000 case BROADCOM_DEV_ID_57502:
4001 case BROADCOM_DEV_ID_57508_MF1:
4002 case BROADCOM_DEV_ID_57504_MF1:
4003 case BROADCOM_DEV_ID_57502_MF1:
4004 case BROADCOM_DEV_ID_57508_MF2:
4005 case BROADCOM_DEV_ID_57504_MF2:
4006 case BROADCOM_DEV_ID_57502_MF2:
4007 case BROADCOM_DEV_ID_57500_VF1:
4008 case BROADCOM_DEV_ID_57500_VF2:
4009 case BROADCOM_DEV_ID_58812:
4010 case BROADCOM_DEV_ID_58814:
4011 case BROADCOM_DEV_ID_58818:
4012 case BROADCOM_DEV_ID_58818_VF:
4020 bool bnxt_stratus_device(struct bnxt *bp)
4022 uint16_t device_id = bp->pdev->id.device_id;
4024 switch (device_id) {
4025 case BROADCOM_DEV_ID_STRATUS_NIC:
4026 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4027 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4035 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4037 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4038 struct bnxt *bp = eth_dev->data->dev_private;
4040 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4041 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4042 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4043 if (!bp->bar0 || !bp->doorbell_base) {
4044 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4048 bp->eth_dev = eth_dev;
4054 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4055 struct bnxt_ctx_pg_info *ctx_pg,
4060 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4061 const struct rte_memzone *mz = NULL;
4062 char mz_name[RTE_MEMZONE_NAMESIZE];
4063 rte_iova_t mz_phys_addr;
4064 uint64_t valid_bits = 0;
4071 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4073 rmem->page_size = BNXT_PAGE_SIZE;
4074 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4075 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4076 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4078 valid_bits = PTU_PTE_VALID;
4080 if (rmem->nr_pages > 1) {
4081 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4082 "bnxt_ctx_pg_tbl%s_%x_%d",
4083 suffix, idx, bp->eth_dev->data->port_id);
4084 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4085 mz = rte_memzone_lookup(mz_name);
4087 mz = rte_memzone_reserve_aligned(mz_name,
4091 RTE_MEMZONE_SIZE_HINT_ONLY |
4092 RTE_MEMZONE_IOVA_CONTIG,
4098 memset(mz->addr, 0, mz->len);
4099 mz_phys_addr = mz->iova;
4101 rmem->pg_tbl = mz->addr;
4102 rmem->pg_tbl_map = mz_phys_addr;
4103 rmem->pg_tbl_mz = mz;
4106 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4107 suffix, idx, bp->eth_dev->data->port_id);
4108 mz = rte_memzone_lookup(mz_name);
4110 mz = rte_memzone_reserve_aligned(mz_name,
4114 RTE_MEMZONE_SIZE_HINT_ONLY |
4115 RTE_MEMZONE_IOVA_CONTIG,
4121 memset(mz->addr, 0, mz->len);
4122 mz_phys_addr = mz->iova;
4124 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4125 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4126 rmem->dma_arr[i] = mz_phys_addr + sz;
4128 if (rmem->nr_pages > 1) {
4129 if (i == rmem->nr_pages - 2 &&
4130 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4131 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4132 else if (i == rmem->nr_pages - 1 &&
4133 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4134 valid_bits |= PTU_PTE_LAST;
4136 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4142 if (rmem->vmem_size)
4143 rmem->vmem = (void **)mz->addr;
4144 rmem->dma_arr[0] = mz_phys_addr;
4148 static void bnxt_free_ctx_mem(struct bnxt *bp)
4152 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4155 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4156 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4157 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4158 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4159 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4160 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4161 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4162 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4163 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4164 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4165 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4167 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4168 if (bp->ctx->tqm_mem[i])
4169 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4176 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4178 #define min_t(type, x, y) ({ \
4179 type __min1 = (x); \
4180 type __min2 = (y); \
4181 __min1 < __min2 ? __min1 : __min2; })
4183 #define max_t(type, x, y) ({ \
4184 type __max1 = (x); \
4185 type __max2 = (y); \
4186 __max1 > __max2 ? __max1 : __max2; })
4188 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4190 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4192 struct bnxt_ctx_pg_info *ctx_pg;
4193 struct bnxt_ctx_mem_info *ctx;
4194 uint32_t mem_size, ena, entries;
4195 uint32_t entries_sp, min;
4198 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4200 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4204 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4207 ctx_pg = &ctx->qp_mem;
4208 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4209 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4210 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4214 ctx_pg = &ctx->srq_mem;
4215 ctx_pg->entries = ctx->srq_max_l2_entries;
4216 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4217 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4221 ctx_pg = &ctx->cq_mem;
4222 ctx_pg->entries = ctx->cq_max_l2_entries;
4223 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4224 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4228 ctx_pg = &ctx->vnic_mem;
4229 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4230 ctx->vnic_max_ring_table_entries;
4231 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4232 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4236 ctx_pg = &ctx->stat_mem;
4237 ctx_pg->entries = ctx->stat_max_entries;
4238 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4239 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4243 min = ctx->tqm_min_entries_per_ring;
4245 entries_sp = ctx->qp_max_l2_entries +
4246 ctx->vnic_max_vnic_entries +
4247 2 * ctx->qp_min_qp1_entries + min;
4248 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4250 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4251 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4252 entries = clamp_t(uint32_t, entries, min,
4253 ctx->tqm_max_entries_per_ring);
4254 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4255 ctx_pg = ctx->tqm_mem[i];
4256 ctx_pg->entries = i ? entries : entries_sp;
4257 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4258 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4261 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4264 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4265 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4268 "Failed to configure context mem: rc = %d\n", rc);
4270 ctx->flags |= BNXT_CTX_FLAG_INITED;
4275 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4277 struct rte_pci_device *pci_dev = bp->pdev;
4278 char mz_name[RTE_MEMZONE_NAMESIZE];
4279 const struct rte_memzone *mz = NULL;
4280 uint32_t total_alloc_len;
4281 rte_iova_t mz_phys_addr;
4283 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4286 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4287 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4288 pci_dev->addr.bus, pci_dev->addr.devid,
4289 pci_dev->addr.function, "rx_port_stats");
4290 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4291 mz = rte_memzone_lookup(mz_name);
4293 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4294 sizeof(struct rx_port_stats_ext) + 512);
4296 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4299 RTE_MEMZONE_SIZE_HINT_ONLY |
4300 RTE_MEMZONE_IOVA_CONTIG);
4304 memset(mz->addr, 0, mz->len);
4305 mz_phys_addr = mz->iova;
4307 bp->rx_mem_zone = (const void *)mz;
4308 bp->hw_rx_port_stats = mz->addr;
4309 bp->hw_rx_port_stats_map = mz_phys_addr;
4311 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4312 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4313 pci_dev->addr.bus, pci_dev->addr.devid,
4314 pci_dev->addr.function, "tx_port_stats");
4315 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4316 mz = rte_memzone_lookup(mz_name);
4318 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4319 sizeof(struct tx_port_stats_ext) + 512);
4321 mz = rte_memzone_reserve(mz_name,
4325 RTE_MEMZONE_SIZE_HINT_ONLY |
4326 RTE_MEMZONE_IOVA_CONTIG);
4330 memset(mz->addr, 0, mz->len);
4331 mz_phys_addr = mz->iova;
4333 bp->tx_mem_zone = (const void *)mz;
4334 bp->hw_tx_port_stats = mz->addr;
4335 bp->hw_tx_port_stats_map = mz_phys_addr;
4336 bp->flags |= BNXT_FLAG_PORT_STATS;
4338 /* Display extended statistics if FW supports it */
4339 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4340 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4341 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4344 bp->hw_rx_port_stats_ext = (void *)
4345 ((uint8_t *)bp->hw_rx_port_stats +
4346 sizeof(struct rx_port_stats));
4347 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4348 sizeof(struct rx_port_stats);
4349 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4351 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4352 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4353 bp->hw_tx_port_stats_ext = (void *)
4354 ((uint8_t *)bp->hw_tx_port_stats +
4355 sizeof(struct tx_port_stats));
4356 bp->hw_tx_port_stats_ext_map =
4357 bp->hw_tx_port_stats_map +
4358 sizeof(struct tx_port_stats);
4359 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4365 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4367 struct bnxt *bp = eth_dev->data->dev_private;
4370 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4371 RTE_ETHER_ADDR_LEN *
4374 if (eth_dev->data->mac_addrs == NULL) {
4375 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4379 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4383 /* Generate a random MAC address, if none was assigned by PF */
4384 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4385 bnxt_eth_hw_addr_random(bp->mac_addr);
4387 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4388 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4389 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4391 rc = bnxt_hwrm_set_mac(bp);
4396 /* Copy the permanent MAC from the FUNC_QCAPS response */
4397 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4402 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4406 /* MAC is already configured in FW */
4407 if (BNXT_HAS_DFLT_MAC_SET(bp))
4410 /* Restore the old MAC configured */
4411 rc = bnxt_hwrm_set_mac(bp);
4413 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4418 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4423 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4425 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4426 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4427 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4428 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4429 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4430 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4434 bnxt_get_svif(uint16_t port_id, bool func_svif,
4435 enum bnxt_ulp_intf_type type)
4437 struct rte_eth_dev *eth_dev;
4440 eth_dev = &rte_eth_devices[port_id];
4441 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4442 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4446 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4449 eth_dev = vfr->parent_dev;
4452 bp = eth_dev->data->dev_private;
4454 return func_svif ? bp->func_svif : bp->port_svif;
4458 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4460 struct rte_eth_dev *eth_dev;
4461 struct bnxt_vnic_info *vnic;
4464 eth_dev = &rte_eth_devices[port];
4465 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4466 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4470 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4471 return vfr->dflt_vnic_id;
4473 eth_dev = vfr->parent_dev;
4476 bp = eth_dev->data->dev_private;
4478 vnic = BNXT_GET_DEFAULT_VNIC(bp);
4480 return vnic->fw_vnic_id;
4484 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4486 struct rte_eth_dev *eth_dev;
4489 eth_dev = &rte_eth_devices[port];
4490 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4491 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4495 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4498 eth_dev = vfr->parent_dev;
4501 bp = eth_dev->data->dev_private;
4506 enum bnxt_ulp_intf_type
4507 bnxt_get_interface_type(uint16_t port)
4509 struct rte_eth_dev *eth_dev;
4512 eth_dev = &rte_eth_devices[port];
4513 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4514 return BNXT_ULP_INTF_TYPE_VF_REP;
4516 bp = eth_dev->data->dev_private;
4518 return BNXT_ULP_INTF_TYPE_PF;
4519 else if (BNXT_VF_IS_TRUSTED(bp))
4520 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4521 else if (BNXT_VF(bp))
4522 return BNXT_ULP_INTF_TYPE_VF;
4524 return BNXT_ULP_INTF_TYPE_INVALID;
4528 bnxt_get_phy_port_id(uint16_t port_id)
4530 struct bnxt_representor *vfr;
4531 struct rte_eth_dev *eth_dev;
4534 eth_dev = &rte_eth_devices[port_id];
4535 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4536 vfr = eth_dev->data->dev_private;
4540 eth_dev = vfr->parent_dev;
4543 bp = eth_dev->data->dev_private;
4545 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4549 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4551 struct rte_eth_dev *eth_dev;
4554 eth_dev = &rte_eth_devices[port_id];
4555 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4556 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4560 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4561 return vfr->fw_fid - 1;
4563 eth_dev = vfr->parent_dev;
4566 bp = eth_dev->data->dev_private;
4568 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
4572 bnxt_get_vport(uint16_t port_id)
4574 return (1 << bnxt_get_phy_port_id(port_id));
4577 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4579 struct bnxt_error_recovery_info *info = bp->recovery_info;
4582 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4583 memset(info, 0, sizeof(*info));
4587 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4590 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4593 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4595 bp->recovery_info = info;
4598 static void bnxt_check_fw_status(struct bnxt *bp)
4602 if (!(bp->recovery_info &&
4603 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
4606 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
4607 if (fw_status != BNXT_FW_STATUS_HEALTHY)
4608 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
4612 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
4614 struct bnxt_error_recovery_info *info = bp->recovery_info;
4615 uint32_t status_loc;
4618 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
4619 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4620 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4621 BNXT_GRCP_WINDOW_2_BASE +
4622 offsetof(struct hcomm_status,
4624 /* If the signature is absent, then FW does not support this feature */
4625 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
4626 HCOMM_STATUS_SIGNATURE_VAL)
4630 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4634 bp->recovery_info = info;
4636 memset(info, 0, sizeof(*info));
4639 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4640 BNXT_GRCP_WINDOW_2_BASE +
4641 offsetof(struct hcomm_status,
4644 /* Only pre-map the FW health status GRC register */
4645 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
4648 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
4649 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
4650 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
4652 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
4653 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4655 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
4660 static int bnxt_init_fw(struct bnxt *bp)
4667 rc = bnxt_map_hcomm_fw_status_reg(bp);
4671 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4673 bnxt_check_fw_status(bp);
4677 rc = bnxt_hwrm_func_reset(bp);
4681 rc = bnxt_hwrm_vnic_qcaps(bp);
4685 rc = bnxt_hwrm_queue_qportcfg(bp);
4689 /* Get the MAX capabilities for this function.
4690 * This function also allocates context memory for TQM rings and
4691 * informs the firmware about this allocated backing store memory.
4693 rc = bnxt_hwrm_func_qcaps(bp);
4697 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4701 bnxt_hwrm_port_mac_qcfg(bp);
4703 bnxt_hwrm_parent_pf_qcfg(bp);
4705 bnxt_hwrm_port_phy_qcaps(bp);
4707 bnxt_alloc_error_recovery_info(bp);
4708 /* Get the adapter error recovery support info */
4709 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4711 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4713 bnxt_hwrm_port_led_qcaps(bp);
4719 bnxt_init_locks(struct bnxt *bp)
4723 err = pthread_mutex_init(&bp->flow_lock, NULL);
4725 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4729 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4731 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4735 err = pthread_mutex_init(&bp->health_check_lock, NULL);
4737 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
4741 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4745 rc = bnxt_init_fw(bp);
4749 if (!reconfig_dev) {
4750 rc = bnxt_setup_mac_addr(bp->eth_dev);
4754 rc = bnxt_restore_dflt_mac(bp);
4759 bnxt_config_vf_req_fwd(bp);
4761 rc = bnxt_hwrm_func_driver_register(bp);
4763 PMD_DRV_LOG(ERR, "Failed to register driver");
4768 if (bp->pdev->max_vfs) {
4769 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4771 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4775 rc = bnxt_hwrm_allocate_pf_only(bp);
4778 "Failed to allocate PF resources");
4784 rc = bnxt_alloc_mem(bp, reconfig_dev);
4788 rc = bnxt_setup_int(bp);
4792 rc = bnxt_request_int(bp);
4796 rc = bnxt_init_ctx_mem(bp);
4798 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
4802 rc = bnxt_init_locks(bp);
4810 bnxt_parse_devarg_truflow(__rte_unused const char *key,
4811 const char *value, void *opaque_arg)
4813 struct bnxt *bp = opaque_arg;
4814 unsigned long truflow;
4817 if (!value || !opaque_arg) {
4819 "Invalid parameter passed to truflow devargs.\n");
4823 truflow = strtoul(value, &end, 10);
4824 if (end == NULL || *end != '\0' ||
4825 (truflow == ULONG_MAX && errno == ERANGE)) {
4827 "Invalid parameter passed to truflow devargs.\n");
4831 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
4833 "Invalid value passed to truflow devargs.\n");
4838 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
4839 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
4841 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
4842 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
4849 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
4850 const char *value, void *opaque_arg)
4852 struct bnxt *bp = opaque_arg;
4853 unsigned long flow_xstat;
4856 if (!value || !opaque_arg) {
4858 "Invalid parameter passed to flow_xstat devarg.\n");
4862 flow_xstat = strtoul(value, &end, 10);
4863 if (end == NULL || *end != '\0' ||
4864 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
4866 "Invalid parameter passed to flow_xstat devarg.\n");
4870 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
4872 "Invalid value passed to flow_xstat devarg.\n");
4876 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
4877 if (BNXT_FLOW_XSTATS_EN(bp))
4878 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
4884 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
4885 const char *value, void *opaque_arg)
4887 struct bnxt *bp = opaque_arg;
4888 unsigned long max_num_kflows;
4891 if (!value || !opaque_arg) {
4893 "Invalid parameter passed to max_num_kflows devarg.\n");
4897 max_num_kflows = strtoul(value, &end, 10);
4898 if (end == NULL || *end != '\0' ||
4899 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
4901 "Invalid parameter passed to max_num_kflows devarg.\n");
4905 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
4907 "Invalid value passed to max_num_kflows devarg.\n");
4911 bp->max_num_kflows = max_num_kflows;
4912 if (bp->max_num_kflows)
4913 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
4920 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
4921 const char *value, void *opaque_arg)
4923 struct bnxt_representor *vfr_bp = opaque_arg;
4924 unsigned long rep_is_pf;
4927 if (!value || !opaque_arg) {
4929 "Invalid parameter passed to rep_is_pf devargs.\n");
4933 rep_is_pf = strtoul(value, &end, 10);
4934 if (end == NULL || *end != '\0' ||
4935 (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
4937 "Invalid parameter passed to rep_is_pf devargs.\n");
4941 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
4943 "Invalid value passed to rep_is_pf devargs.\n");
4947 vfr_bp->flags |= rep_is_pf;
4948 if (BNXT_REP_PF(vfr_bp))
4949 PMD_DRV_LOG(INFO, "PF representor\n");
4951 PMD_DRV_LOG(INFO, "VF representor\n");
4957 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
4958 const char *value, void *opaque_arg)
4960 struct bnxt_representor *vfr_bp = opaque_arg;
4961 unsigned long rep_based_pf;
4964 if (!value || !opaque_arg) {
4966 "Invalid parameter passed to rep_based_pf "
4971 rep_based_pf = strtoul(value, &end, 10);
4972 if (end == NULL || *end != '\0' ||
4973 (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
4975 "Invalid parameter passed to rep_based_pf "
4980 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
4982 "Invalid value passed to rep_based_pf devargs.\n");
4986 vfr_bp->rep_based_pf = rep_based_pf;
4987 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
4989 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
4995 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
4996 const char *value, void *opaque_arg)
4998 struct bnxt_representor *vfr_bp = opaque_arg;
4999 unsigned long rep_q_r2f;
5002 if (!value || !opaque_arg) {
5004 "Invalid parameter passed to rep_q_r2f "
5009 rep_q_r2f = strtoul(value, &end, 10);
5010 if (end == NULL || *end != '\0' ||
5011 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5013 "Invalid parameter passed to rep_q_r2f "
5018 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5020 "Invalid value passed to rep_q_r2f devargs.\n");
5024 vfr_bp->rep_q_r2f = rep_q_r2f;
5025 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5026 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5032 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5033 const char *value, void *opaque_arg)
5035 struct bnxt_representor *vfr_bp = opaque_arg;
5036 unsigned long rep_q_f2r;
5039 if (!value || !opaque_arg) {
5041 "Invalid parameter passed to rep_q_f2r "
5046 rep_q_f2r = strtoul(value, &end, 10);
5047 if (end == NULL || *end != '\0' ||
5048 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5050 "Invalid parameter passed to rep_q_f2r "
5055 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5057 "Invalid value passed to rep_q_f2r devargs.\n");
5061 vfr_bp->rep_q_f2r = rep_q_f2r;
5062 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5063 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5069 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5070 const char *value, void *opaque_arg)
5072 struct bnxt_representor *vfr_bp = opaque_arg;
5073 unsigned long rep_fc_r2f;
5076 if (!value || !opaque_arg) {
5078 "Invalid parameter passed to rep_fc_r2f "
5083 rep_fc_r2f = strtoul(value, &end, 10);
5084 if (end == NULL || *end != '\0' ||
5085 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5087 "Invalid parameter passed to rep_fc_r2f "
5092 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5094 "Invalid value passed to rep_fc_r2f devargs.\n");
5098 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5099 vfr_bp->rep_fc_r2f = rep_fc_r2f;
5100 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5106 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5107 const char *value, void *opaque_arg)
5109 struct bnxt_representor *vfr_bp = opaque_arg;
5110 unsigned long rep_fc_f2r;
5113 if (!value || !opaque_arg) {
5115 "Invalid parameter passed to rep_fc_f2r "
5120 rep_fc_f2r = strtoul(value, &end, 10);
5121 if (end == NULL || *end != '\0' ||
5122 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5124 "Invalid parameter passed to rep_fc_f2r "
5129 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5131 "Invalid value passed to rep_fc_f2r devargs.\n");
5135 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5136 vfr_bp->rep_fc_f2r = rep_fc_f2r;
5137 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5143 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5145 struct rte_kvargs *kvlist;
5147 if (devargs == NULL)
5150 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5155 * Handler for "truflow" devarg.
5156 * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1"
5158 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5159 bnxt_parse_devarg_truflow, bp);
5162 * Handler for "flow_xstat" devarg.
5163 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5165 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5166 bnxt_parse_devarg_flow_xstat, bp);
5169 * Handler for "max_num_kflows" devarg.
5170 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5172 rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5173 bnxt_parse_devarg_max_num_kflows, bp);
5175 rte_kvargs_free(kvlist);
5178 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5182 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5183 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5186 "Failed to alloc switch domain: %d\n", rc);
5189 "Switch domain allocated %d\n",
5190 bp->switch_domain_id);
5197 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5199 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5200 static int version_printed;
5204 if (version_printed++ == 0)
5205 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5207 eth_dev->dev_ops = &bnxt_dev_ops;
5208 eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5209 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5210 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5211 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5212 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5215 * For secondary processes, we don't initialise any further
5216 * as primary has already done this work.
5218 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5221 rte_eth_copy_pci_info(eth_dev, pci_dev);
5222 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5224 bp = eth_dev->data->dev_private;
5226 /* Parse dev arguments passed on when starting the DPDK application. */
5227 bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5229 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5231 if (bnxt_vf_pciid(pci_dev->id.device_id))
5232 bp->flags |= BNXT_FLAG_VF;
5234 if (bnxt_p5_device(pci_dev->id.device_id))
5235 bp->flags |= BNXT_FLAG_CHIP_P5;
5237 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5238 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5239 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5240 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5241 bp->flags |= BNXT_FLAG_STINGRAY;
5243 if (BNXT_TRUFLOW_EN(bp)) {
5244 /* extra mbuf field is required to store CFA code from mark */
5245 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5246 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5247 .size = sizeof(bnxt_cfa_code_dynfield_t),
5248 .align = __alignof__(bnxt_cfa_code_dynfield_t),
5250 bnxt_cfa_code_dynfield_offset =
5251 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5252 if (bnxt_cfa_code_dynfield_offset < 0) {
5254 "Failed to register mbuf field for TruFlow mark\n");
5259 rc = bnxt_init_board(eth_dev);
5262 "Failed to initialize board rc: %x\n", rc);
5266 rc = bnxt_alloc_pf_info(bp);
5270 rc = bnxt_alloc_link_info(bp);
5274 rc = bnxt_alloc_parent_info(bp);
5278 rc = bnxt_alloc_hwrm_resources(bp);
5281 "Failed to allocate hwrm resource rc: %x\n", rc);
5284 rc = bnxt_alloc_leds_info(bp);
5288 rc = bnxt_alloc_cos_queues(bp);
5292 rc = bnxt_init_resources(bp, false);
5296 rc = bnxt_alloc_stats_mem(bp);
5300 bnxt_alloc_switch_domain(bp);
5303 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5304 pci_dev->mem_resource[0].phys_addr,
5305 pci_dev->mem_resource[0].addr);
5310 bnxt_dev_uninit(eth_dev);
5315 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5324 ctx->dma = RTE_BAD_IOVA;
5325 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5328 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5330 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5331 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5332 bp->flow_stat->rx_fc_out_tbl.ctx_id,
5333 bp->flow_stat->max_fc,
5336 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5337 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5338 bp->flow_stat->tx_fc_out_tbl.ctx_id,
5339 bp->flow_stat->max_fc,
5342 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5343 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5344 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5346 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5347 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5348 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5350 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5351 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5352 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5354 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5355 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5356 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5359 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5361 bnxt_unregister_fc_ctx_mem(bp);
5363 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5364 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5365 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5366 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5369 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5371 if (BNXT_FLOW_XSTATS_EN(bp))
5372 bnxt_uninit_fc_ctx_mem(bp);
5376 bnxt_free_error_recovery_info(struct bnxt *bp)
5378 rte_free(bp->recovery_info);
5379 bp->recovery_info = NULL;
5380 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5384 bnxt_uninit_locks(struct bnxt *bp)
5386 pthread_mutex_destroy(&bp->flow_lock);
5387 pthread_mutex_destroy(&bp->def_cp_lock);
5388 pthread_mutex_destroy(&bp->health_check_lock);
5390 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5391 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
5396 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5401 bnxt_free_mem(bp, reconfig_dev);
5403 bnxt_hwrm_func_buf_unrgtr(bp);
5404 rte_free(bp->pf->vf_req_buf);
5406 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5407 bp->flags &= ~BNXT_FLAG_REGISTERED;
5408 bnxt_free_ctx_mem(bp);
5409 if (!reconfig_dev) {
5410 bnxt_free_hwrm_resources(bp);
5411 bnxt_free_error_recovery_info(bp);
5414 bnxt_uninit_ctx_mem(bp);
5416 bnxt_uninit_locks(bp);
5417 bnxt_free_flow_stats_info(bp);
5418 bnxt_free_rep_info(bp);
5419 rte_free(bp->ptp_cfg);
5425 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5427 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5430 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5432 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5433 bnxt_dev_close_op(eth_dev);
5438 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5440 struct bnxt *bp = eth_dev->data->dev_private;
5441 struct rte_eth_dev *vf_rep_eth_dev;
5447 for (i = 0; i < bp->num_reps; i++) {
5448 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5449 if (!vf_rep_eth_dev)
5451 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5452 vf_rep_eth_dev->data->port_id);
5453 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5455 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5456 eth_dev->data->port_id);
5457 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5462 static void bnxt_free_rep_info(struct bnxt *bp)
5464 rte_free(bp->rep_info);
5465 bp->rep_info = NULL;
5466 rte_free(bp->cfa_code_map);
5467 bp->cfa_code_map = NULL;
5470 static int bnxt_init_rep_info(struct bnxt *bp)
5477 bp->rep_info = rte_zmalloc("bnxt_rep_info",
5478 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5480 if (!bp->rep_info) {
5481 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5484 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5485 sizeof(*bp->cfa_code_map) *
5486 BNXT_MAX_CFA_CODE, 0);
5487 if (!bp->cfa_code_map) {
5488 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5489 bnxt_free_rep_info(bp);
5493 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5494 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5496 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5498 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5499 bnxt_free_rep_info(bp);
5503 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5505 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5506 bnxt_free_rep_info(bp);
5513 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5514 struct rte_eth_devargs *eth_da,
5515 struct rte_eth_dev *backing_eth_dev,
5516 const char *dev_args)
5518 struct rte_eth_dev *vf_rep_eth_dev;
5519 char name[RTE_ETH_NAME_MAX_LEN];
5520 struct bnxt *backing_bp;
5523 struct rte_kvargs *kvlist = NULL;
5525 num_rep = eth_da->nb_representor_ports;
5526 if (num_rep > BNXT_MAX_VF_REPS) {
5527 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5528 num_rep, BNXT_MAX_VF_REPS);
5532 if (num_rep >= RTE_MAX_ETHPORTS) {
5534 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5535 num_rep, RTE_MAX_ETHPORTS);
5539 backing_bp = backing_eth_dev->data->dev_private;
5541 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5543 "Not a PF or trusted VF. No Representor support\n");
5544 /* Returning an error is not an option.
5545 * Applications are not handling this correctly
5550 if (bnxt_init_rep_info(backing_bp))
5553 for (i = 0; i < num_rep; i++) {
5554 struct bnxt_representor representor = {
5555 .vf_id = eth_da->representor_ports[i],
5556 .switch_domain_id = backing_bp->switch_domain_id,
5557 .parent_dev = backing_eth_dev
5560 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5561 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5562 representor.vf_id, BNXT_MAX_VF_REPS);
5566 /* representor port net_bdf_port */
5567 snprintf(name, sizeof(name), "net_%s_representor_%d",
5568 pci_dev->device.name, eth_da->representor_ports[i]);
5570 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
5573 * Handler for "rep_is_pf" devarg.
5574 * Invoked as for ex: "-a 000:00:0d.0,
5575 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5577 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
5578 bnxt_parse_devarg_rep_is_pf,
5579 (void *)&representor);
5585 * Handler for "rep_based_pf" devarg.
5586 * Invoked as for ex: "-a 000:00:0d.0,
5587 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5589 ret = rte_kvargs_process(kvlist,
5590 BNXT_DEVARG_REP_BASED_PF,
5591 bnxt_parse_devarg_rep_based_pf,
5592 (void *)&representor);
5598 * Handler for "rep_based_pf" devarg.
5599 * Invoked as for ex: "-a 000:00:0d.0,
5600 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5602 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
5603 bnxt_parse_devarg_rep_q_r2f,
5604 (void *)&representor);
5610 * Handler for "rep_based_pf" devarg.
5611 * Invoked as for ex: "-a 000:00:0d.0,
5612 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5614 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
5615 bnxt_parse_devarg_rep_q_f2r,
5616 (void *)&representor);
5622 * Handler for "rep_based_pf" devarg.
5623 * Invoked as for ex: "-a 000:00:0d.0,
5624 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5626 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
5627 bnxt_parse_devarg_rep_fc_r2f,
5628 (void *)&representor);
5634 * Handler for "rep_based_pf" devarg.
5635 * Invoked as for ex: "-a 000:00:0d.0,
5636 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5638 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
5639 bnxt_parse_devarg_rep_fc_f2r,
5640 (void *)&representor);
5647 ret = rte_eth_dev_create(&pci_dev->device, name,
5648 sizeof(struct bnxt_representor),
5650 bnxt_representor_init,
5653 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
5654 "representor %s.", name);
5658 vf_rep_eth_dev = rte_eth_dev_allocated(name);
5659 if (!vf_rep_eth_dev) {
5660 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
5661 " for VF-Rep: %s.", name);
5666 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
5667 backing_eth_dev->data->port_id);
5668 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
5670 backing_bp->num_reps++;
5674 rte_kvargs_free(kvlist);
5678 /* If num_rep > 1, then rollback already created
5679 * ports, since we'll be failing the probe anyway
5682 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
5684 rte_kvargs_free(kvlist);
5689 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5690 struct rte_pci_device *pci_dev)
5692 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
5693 struct rte_eth_dev *backing_eth_dev;
5697 if (pci_dev->device.devargs) {
5698 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
5704 num_rep = eth_da.nb_representor_ports;
5705 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
5708 /* We could come here after first level of probe is already invoked
5709 * as part of an application bringup(OVS-DPDK vswitchd), so first check
5710 * for already allocated eth_dev for the backing device (PF/Trusted VF)
5712 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5713 if (backing_eth_dev == NULL) {
5714 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
5715 sizeof(struct bnxt),
5716 eth_dev_pci_specific_init, pci_dev,
5717 bnxt_dev_init, NULL);
5719 if (ret || !num_rep)
5722 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5724 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
5725 backing_eth_dev->data->port_id);
5730 /* probe representor ports now */
5731 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev,
5732 pci_dev->device.devargs->args);
5737 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5739 struct rte_eth_dev *eth_dev;
5741 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5743 return 0; /* Invoked typically only by OVS-DPDK, by the
5744 * time it comes here the eth_dev is already
5745 * deleted by rte_eth_dev_close(), so returning
5746 * +ve value will at least help in proper cleanup
5749 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
5750 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
5751 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
5752 return rte_eth_dev_destroy(eth_dev,
5753 bnxt_representor_uninit);
5755 return rte_eth_dev_destroy(eth_dev,
5758 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5762 static struct rte_pci_driver bnxt_rte_pmd = {
5763 .id_table = bnxt_pci_id_map,
5764 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
5765 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
5768 .probe = bnxt_pci_probe,
5769 .remove = bnxt_pci_remove,
5773 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5775 if (strcmp(dev->device->driver->name, drv->driver.name))
5781 bool is_bnxt_supported(struct rte_eth_dev *dev)
5783 return is_device_supported(dev, &bnxt_rte_pmd);
5786 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
5787 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5788 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5789 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");