1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
18 #include "bnxt_filter.h"
19 #include "bnxt_hwrm.h"
21 #include "bnxt_reps.h"
22 #include "bnxt_ring.h"
25 #include "bnxt_stats.h"
28 #include "bnxt_vnic.h"
29 #include "hsi_struct_def_dpdk.h"
30 #include "bnxt_nvm_defs.h"
31 #include "bnxt_tf_common.h"
32 #include "ulp_flow_db.h"
34 #define DRV_MODULE_NAME "bnxt"
35 static const char bnxt_version[] =
36 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
39 * The set of PCI devices this driver supports
41 static const struct rte_pci_id bnxt_pci_id_map[] = {
42 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
43 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
95 { .vendor_id = 0, /* sentinel */ },
98 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
99 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
100 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
101 #define BNXT_DEVARG_REPRESENTOR "representor"
103 static const char *const bnxt_dev_args[] = {
104 BNXT_DEVARG_REPRESENTOR,
106 BNXT_DEVARG_FLOW_XSTAT,
107 BNXT_DEVARG_MAX_NUM_KFLOWS,
112 * truflow == false to disable the feature
113 * truflow == true to enable the feature
115 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
118 * flow_xstat == false to disable the feature
119 * flow_xstat == true to enable the feature
121 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
124 * max_num_kflows must be >= 32
125 * and must be a power-of-2 supported value
126 * return: 1 -> invalid
129 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
131 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
136 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
137 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
138 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
139 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
140 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
141 static int bnxt_restore_vlan_filters(struct bnxt *bp);
142 static void bnxt_dev_recover(void *arg);
143 static void bnxt_free_error_recovery_info(struct bnxt *bp);
144 static void bnxt_free_rep_info(struct bnxt *bp);
146 int is_bnxt_in_error(struct bnxt *bp)
148 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
150 if (bp->flags & BNXT_FLAG_FW_RESET)
156 /***********************/
159 * High level utility functions
162 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
164 if (!BNXT_CHIP_THOR(bp))
167 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
168 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
169 BNXT_RSS_ENTRIES_PER_CTX_THOR;
172 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
174 if (!BNXT_CHIP_THOR(bp))
175 return HW_HASH_INDEX_SIZE;
177 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
180 static void bnxt_free_parent_info(struct bnxt *bp)
182 rte_free(bp->parent);
185 static void bnxt_free_pf_info(struct bnxt *bp)
190 static void bnxt_free_link_info(struct bnxt *bp)
192 rte_free(bp->link_info);
195 static void bnxt_free_leds_info(struct bnxt *bp)
204 static void bnxt_free_flow_stats_info(struct bnxt *bp)
206 rte_free(bp->flow_stat);
207 bp->flow_stat = NULL;
210 static void bnxt_free_cos_queues(struct bnxt *bp)
212 rte_free(bp->rx_cos_queue);
213 rte_free(bp->tx_cos_queue);
216 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
218 bnxt_free_filter_mem(bp);
219 bnxt_free_vnic_attributes(bp);
220 bnxt_free_vnic_mem(bp);
222 /* tx/rx rings are configured as part of *_queue_setup callbacks.
223 * If the number of rings change across fw update,
224 * we don't have much choice except to warn the user.
228 bnxt_free_tx_rings(bp);
229 bnxt_free_rx_rings(bp);
231 bnxt_free_async_cp_ring(bp);
232 bnxt_free_rxtx_nq_ring(bp);
234 rte_free(bp->grp_info);
238 static int bnxt_alloc_parent_info(struct bnxt *bp)
240 bp->parent = rte_zmalloc("bnxt_parent_info",
241 sizeof(struct bnxt_parent_info), 0);
242 if (bp->parent == NULL)
248 static int bnxt_alloc_pf_info(struct bnxt *bp)
250 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
257 static int bnxt_alloc_link_info(struct bnxt *bp)
260 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
261 if (bp->link_info == NULL)
267 static int bnxt_alloc_leds_info(struct bnxt *bp)
272 bp->leds = rte_zmalloc("bnxt_leds",
273 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
275 if (bp->leds == NULL)
281 static int bnxt_alloc_cos_queues(struct bnxt *bp)
284 rte_zmalloc("bnxt_rx_cosq",
285 BNXT_COS_QUEUE_COUNT *
286 sizeof(struct bnxt_cos_queue_info),
288 if (bp->rx_cos_queue == NULL)
292 rte_zmalloc("bnxt_tx_cosq",
293 BNXT_COS_QUEUE_COUNT *
294 sizeof(struct bnxt_cos_queue_info),
296 if (bp->tx_cos_queue == NULL)
302 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
304 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
305 sizeof(struct bnxt_flow_stat_info), 0);
306 if (bp->flow_stat == NULL)
312 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
316 rc = bnxt_alloc_ring_grps(bp);
320 rc = bnxt_alloc_async_ring_struct(bp);
324 rc = bnxt_alloc_vnic_mem(bp);
328 rc = bnxt_alloc_vnic_attributes(bp);
332 rc = bnxt_alloc_filter_mem(bp);
336 rc = bnxt_alloc_async_cp_ring(bp);
340 rc = bnxt_alloc_rxtx_nq_ring(bp);
344 if (BNXT_FLOW_XSTATS_EN(bp)) {
345 rc = bnxt_alloc_flow_stats_info(bp);
353 bnxt_free_mem(bp, reconfig);
357 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
359 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
360 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
361 uint64_t rx_offloads = dev_conf->rxmode.offloads;
362 struct bnxt_rx_queue *rxq;
366 rc = bnxt_vnic_grp_alloc(bp, vnic);
370 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
371 vnic_id, vnic, vnic->fw_grp_ids);
373 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
377 /* Alloc RSS context only if RSS mode is enabled */
378 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
379 int j, nr_ctxs = bnxt_rss_ctxts(bp);
382 for (j = 0; j < nr_ctxs; j++) {
383 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
389 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
393 vnic->num_lb_ctxts = nr_ctxs;
397 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
398 * setting is not available at this time, it will not be
399 * configured correctly in the CFA.
401 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
402 vnic->vlan_strip = true;
404 vnic->vlan_strip = false;
406 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
410 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
414 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
415 rxq = bp->eth_dev->data->rx_queues[j];
418 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
419 j, rxq->vnic, rxq->vnic->fw_grp_ids);
421 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
422 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
424 vnic->rx_queue_cnt++;
427 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
429 rc = bnxt_vnic_rss_configure(bp, vnic);
433 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
435 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
436 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
438 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
442 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
447 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
451 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
452 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
457 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
458 " rx_fc_in_tbl.ctx_id = %d\n",
459 bp->flow_stat->rx_fc_in_tbl.va,
460 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
461 bp->flow_stat->rx_fc_in_tbl.ctx_id);
463 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
464 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
469 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
470 " rx_fc_out_tbl.ctx_id = %d\n",
471 bp->flow_stat->rx_fc_out_tbl.va,
472 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
473 bp->flow_stat->rx_fc_out_tbl.ctx_id);
475 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
476 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
481 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
482 " tx_fc_in_tbl.ctx_id = %d\n",
483 bp->flow_stat->tx_fc_in_tbl.va,
484 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
485 bp->flow_stat->tx_fc_in_tbl.ctx_id);
487 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
488 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
493 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
494 " tx_fc_out_tbl.ctx_id = %d\n",
495 bp->flow_stat->tx_fc_out_tbl.va,
496 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
497 bp->flow_stat->tx_fc_out_tbl.ctx_id);
499 memset(bp->flow_stat->rx_fc_out_tbl.va,
501 bp->flow_stat->rx_fc_out_tbl.size);
502 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
503 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
504 bp->flow_stat->rx_fc_out_tbl.ctx_id,
505 bp->flow_stat->max_fc,
510 memset(bp->flow_stat->tx_fc_out_tbl.va,
512 bp->flow_stat->tx_fc_out_tbl.size);
513 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
514 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
515 bp->flow_stat->tx_fc_out_tbl.ctx_id,
516 bp->flow_stat->max_fc,
522 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
523 struct bnxt_ctx_mem_buf_info *ctx)
528 ctx->va = rte_zmalloc(type, size, 0);
531 rte_mem_lock_page(ctx->va);
533 ctx->dma = rte_mem_virt2iova(ctx->va);
534 if (ctx->dma == RTE_BAD_IOVA)
540 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
542 struct rte_pci_device *pdev = bp->pdev;
543 char type[RTE_MEMZONE_NAMESIZE];
547 max_fc = bp->flow_stat->max_fc;
549 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
550 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
551 /* 4 bytes for each counter-id */
552 rc = bnxt_alloc_ctx_mem_buf(type,
554 &bp->flow_stat->rx_fc_in_tbl);
558 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
559 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
560 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
561 rc = bnxt_alloc_ctx_mem_buf(type,
563 &bp->flow_stat->rx_fc_out_tbl);
567 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
568 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
569 /* 4 bytes for each counter-id */
570 rc = bnxt_alloc_ctx_mem_buf(type,
572 &bp->flow_stat->tx_fc_in_tbl);
576 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
577 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
578 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
579 rc = bnxt_alloc_ctx_mem_buf(type,
581 &bp->flow_stat->tx_fc_out_tbl);
585 rc = bnxt_register_fc_ctx_mem(bp);
590 static int bnxt_init_ctx_mem(struct bnxt *bp)
594 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
595 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
596 !BNXT_FLOW_XSTATS_EN(bp))
599 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
603 rc = bnxt_init_fc_ctx_mem(bp);
608 static int bnxt_update_phy_setting(struct bnxt *bp)
610 struct rte_eth_link new;
613 rc = bnxt_get_hwrm_link_config(bp, &new);
615 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
620 * On BCM957508-N2100 adapters, FW will not allow any user other
621 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
622 * always returns link up. Force phy update always in that case.
624 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
625 rc = bnxt_set_hwrm_link_config(bp, true);
627 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
635 static int bnxt_init_chip(struct bnxt *bp)
637 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
638 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
639 uint32_t intr_vector = 0;
640 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
641 uint32_t vec = BNXT_MISC_VEC_ID;
645 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
646 bp->eth_dev->data->dev_conf.rxmode.offloads |=
647 DEV_RX_OFFLOAD_JUMBO_FRAME;
648 bp->flags |= BNXT_FLAG_JUMBO;
650 bp->eth_dev->data->dev_conf.rxmode.offloads &=
651 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
652 bp->flags &= ~BNXT_FLAG_JUMBO;
655 /* THOR does not support ring groups.
656 * But we will use the array to save RSS context IDs.
658 if (BNXT_CHIP_THOR(bp))
659 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
661 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
663 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
667 rc = bnxt_alloc_hwrm_rings(bp);
669 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
673 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
675 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
679 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
682 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
683 if (bp->rx_cos_queue[i].id != 0xff) {
684 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
688 "Num pools more than FW profile\n");
692 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
698 rc = bnxt_mq_rx_configure(bp);
700 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
704 /* VNIC configuration */
705 for (i = 0; i < bp->nr_vnics; i++) {
706 rc = bnxt_setup_one_vnic(bp, i);
711 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
714 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
718 /* check and configure queue intr-vector mapping */
719 if ((rte_intr_cap_multiple(intr_handle) ||
720 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
721 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
722 intr_vector = bp->eth_dev->data->nb_rx_queues;
723 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
724 if (intr_vector > bp->rx_cp_nr_rings) {
725 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
729 rc = rte_intr_efd_enable(intr_handle, intr_vector);
734 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
735 intr_handle->intr_vec =
736 rte_zmalloc("intr_vec",
737 bp->eth_dev->data->nb_rx_queues *
739 if (intr_handle->intr_vec == NULL) {
740 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
741 " intr_vec", bp->eth_dev->data->nb_rx_queues);
745 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
746 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
747 intr_handle->intr_vec, intr_handle->nb_efd,
748 intr_handle->max_intr);
749 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
751 intr_handle->intr_vec[queue_id] =
752 vec + BNXT_RX_VEC_START;
753 if (vec < base + intr_handle->nb_efd - 1)
758 /* enable uio/vfio intr/eventfd mapping */
759 rc = rte_intr_enable(intr_handle);
760 #ifndef RTE_EXEC_ENV_FREEBSD
761 /* In FreeBSD OS, nic_uio driver does not support interrupts */
766 rc = bnxt_update_phy_setting(bp);
770 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
772 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
777 rte_free(intr_handle->intr_vec);
779 rte_intr_efd_disable(intr_handle);
781 /* Some of the error status returned by FW may not be from errno.h */
788 static int bnxt_shutdown_nic(struct bnxt *bp)
790 bnxt_free_all_hwrm_resources(bp);
791 bnxt_free_all_filters(bp);
792 bnxt_free_all_vnics(bp);
797 * Device configuration and status function
800 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
802 uint32_t link_speed = bp->link_info->support_speeds;
803 uint32_t speed_capa = 0;
805 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
806 speed_capa |= ETH_LINK_SPEED_100M;
807 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
808 speed_capa |= ETH_LINK_SPEED_100M_HD;
809 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
810 speed_capa |= ETH_LINK_SPEED_1G;
811 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
812 speed_capa |= ETH_LINK_SPEED_2_5G;
813 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
814 speed_capa |= ETH_LINK_SPEED_10G;
815 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
816 speed_capa |= ETH_LINK_SPEED_20G;
817 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
818 speed_capa |= ETH_LINK_SPEED_25G;
819 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
820 speed_capa |= ETH_LINK_SPEED_40G;
821 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
822 speed_capa |= ETH_LINK_SPEED_50G;
823 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
824 speed_capa |= ETH_LINK_SPEED_100G;
825 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
826 speed_capa |= ETH_LINK_SPEED_200G;
828 if (bp->link_info->auto_mode ==
829 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
830 speed_capa |= ETH_LINK_SPEED_FIXED;
832 speed_capa |= ETH_LINK_SPEED_AUTONEG;
837 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
838 struct rte_eth_dev_info *dev_info)
840 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
841 struct bnxt *bp = eth_dev->data->dev_private;
842 uint16_t max_vnics, i, j, vpool, vrxq;
843 unsigned int max_rx_rings;
846 rc = is_bnxt_in_error(bp);
851 dev_info->max_mac_addrs = bp->max_l2_ctx;
852 dev_info->max_hash_mac_addrs = 0;
854 /* PF/VF specifics */
856 dev_info->max_vfs = pdev->max_vfs;
858 max_rx_rings = BNXT_MAX_RINGS(bp);
859 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
860 dev_info->max_rx_queues = max_rx_rings;
861 dev_info->max_tx_queues = max_rx_rings;
862 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
863 dev_info->hash_key_size = 40;
864 max_vnics = bp->max_vnics;
867 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
868 dev_info->max_mtu = BNXT_MAX_MTU;
870 /* Fast path specifics */
871 dev_info->min_rx_bufsize = 1;
872 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
874 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
875 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
876 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
877 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
878 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
880 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
883 dev_info->default_rxconf = (struct rte_eth_rxconf) {
889 .rx_free_thresh = 32,
890 /* If no descriptors available, pkts are dropped by default */
894 dev_info->default_txconf = (struct rte_eth_txconf) {
900 .tx_free_thresh = 32,
903 eth_dev->data->dev_conf.intr_conf.lsc = 1;
905 eth_dev->data->dev_conf.intr_conf.rxq = 1;
906 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
907 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
908 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
909 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
914 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
915 * need further investigation.
919 vpool = 64; /* ETH_64_POOLS */
920 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
921 for (i = 0; i < 4; vpool >>= 1, i++) {
922 if (max_vnics > vpool) {
923 for (j = 0; j < 5; vrxq >>= 1, j++) {
924 if (dev_info->max_rx_queues > vrxq) {
930 /* Not enough resources to support VMDq */
934 /* Not enough resources to support VMDq */
938 dev_info->max_vmdq_pools = vpool;
939 dev_info->vmdq_queue_num = vrxq;
941 dev_info->vmdq_pool_base = 0;
942 dev_info->vmdq_queue_base = 0;
947 /* Configure the device based on the configuration provided */
948 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
950 struct bnxt *bp = eth_dev->data->dev_private;
951 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
954 bp->rx_queues = (void *)eth_dev->data->rx_queues;
955 bp->tx_queues = (void *)eth_dev->data->tx_queues;
956 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
957 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
959 rc = is_bnxt_in_error(bp);
963 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
964 rc = bnxt_hwrm_check_vf_rings(bp);
966 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
970 /* If a resource has already been allocated - in this case
971 * it is the async completion ring, free it. Reallocate it after
972 * resource reservation. This will ensure the resource counts
973 * are calculated correctly.
976 pthread_mutex_lock(&bp->def_cp_lock);
978 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
979 bnxt_disable_int(bp);
980 bnxt_free_cp_ring(bp, bp->async_cp_ring);
983 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
985 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
986 pthread_mutex_unlock(&bp->def_cp_lock);
990 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
991 rc = bnxt_alloc_async_cp_ring(bp);
993 pthread_mutex_unlock(&bp->def_cp_lock);
999 pthread_mutex_unlock(&bp->def_cp_lock);
1001 /* legacy driver needs to get updated values */
1002 rc = bnxt_hwrm_func_qcaps(bp);
1004 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
1009 /* Inherit new configurations */
1010 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1011 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1012 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1013 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1014 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1016 goto resource_error;
1018 if (BNXT_HAS_RING_GRPS(bp) &&
1019 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1020 goto resource_error;
1022 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1023 bp->max_vnics < eth_dev->data->nb_rx_queues)
1024 goto resource_error;
1026 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1027 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1029 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1030 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1031 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1033 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1034 eth_dev->data->mtu =
1035 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1036 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1038 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1044 "Insufficient resources to support requested config\n");
1046 "Num Queues Requested: Tx %d, Rx %d\n",
1047 eth_dev->data->nb_tx_queues,
1048 eth_dev->data->nb_rx_queues);
1050 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1051 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1052 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1056 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1058 struct rte_eth_link *link = ð_dev->data->dev_link;
1060 if (link->link_status)
1061 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1062 eth_dev->data->port_id,
1063 (uint32_t)link->link_speed,
1064 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1065 ("full-duplex") : ("half-duplex\n"));
1067 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1068 eth_dev->data->port_id);
1072 * Determine whether the current configuration requires support for scattered
1073 * receive; return 1 if scattered receive is required and 0 if not.
1075 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1080 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1083 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1084 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1086 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1087 RTE_PKTMBUF_HEADROOM);
1088 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1094 static eth_rx_burst_t
1095 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1097 struct bnxt *bp = eth_dev->data->dev_private;
1099 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1100 #ifndef RTE_LIBRTE_IEEE1588
1102 * Vector mode receive can be enabled only if scatter rx is not
1103 * in use and rx offloads are limited to VLAN stripping and
1106 if (!eth_dev->data->scattered_rx &&
1107 !(eth_dev->data->dev_conf.rxmode.offloads &
1108 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1109 DEV_RX_OFFLOAD_KEEP_CRC |
1110 DEV_RX_OFFLOAD_JUMBO_FRAME |
1111 DEV_RX_OFFLOAD_IPV4_CKSUM |
1112 DEV_RX_OFFLOAD_UDP_CKSUM |
1113 DEV_RX_OFFLOAD_TCP_CKSUM |
1114 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1115 DEV_RX_OFFLOAD_RSS_HASH |
1116 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1117 !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp)) {
1118 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1119 eth_dev->data->port_id);
1120 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1121 return bnxt_recv_pkts_vec;
1123 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1124 eth_dev->data->port_id);
1126 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1127 eth_dev->data->port_id,
1128 eth_dev->data->scattered_rx,
1129 eth_dev->data->dev_conf.rxmode.offloads);
1132 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1133 return bnxt_recv_pkts;
1136 static eth_tx_burst_t
1137 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1139 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1140 #ifndef RTE_LIBRTE_IEEE1588
1141 struct bnxt *bp = eth_dev->data->dev_private;
1144 * Vector mode transmit can be enabled only if not using scatter rx
1147 if (!eth_dev->data->scattered_rx &&
1148 !eth_dev->data->dev_conf.txmode.offloads &&
1149 !BNXT_TRUFLOW_EN(bp)) {
1150 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1151 eth_dev->data->port_id);
1152 return bnxt_xmit_pkts_vec;
1154 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1155 eth_dev->data->port_id);
1157 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1158 eth_dev->data->port_id,
1159 eth_dev->data->scattered_rx,
1160 eth_dev->data->dev_conf.txmode.offloads);
1163 return bnxt_xmit_pkts;
1166 static int bnxt_handle_if_change_status(struct bnxt *bp)
1170 /* Since fw has undergone a reset and lost all contexts,
1171 * set fatal flag to not issue hwrm during cleanup
1173 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1174 bnxt_uninit_resources(bp, true);
1176 /* clear fatal flag so that re-init happens */
1177 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1178 rc = bnxt_init_resources(bp, true);
1180 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1185 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1187 struct bnxt *bp = eth_dev->data->dev_private;
1188 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1190 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1192 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1193 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1197 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1199 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1200 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1204 rc = bnxt_hwrm_if_change(bp, true);
1205 if (rc == 0 || rc != -EAGAIN)
1208 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1209 } while (retry_cnt--);
1214 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1215 rc = bnxt_handle_if_change_status(bp);
1220 bnxt_enable_int(bp);
1222 rc = bnxt_init_chip(bp);
1226 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1227 eth_dev->data->dev_started = 1;
1229 bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1231 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1232 vlan_mask |= ETH_VLAN_FILTER_MASK;
1233 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1234 vlan_mask |= ETH_VLAN_STRIP_MASK;
1235 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1239 /* Initialize bnxt ULP port details */
1240 rc = bnxt_ulp_port_init(bp);
1244 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1245 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1247 pthread_mutex_lock(&bp->def_cp_lock);
1248 bnxt_schedule_fw_health_check(bp);
1249 pthread_mutex_unlock(&bp->def_cp_lock);
1254 bnxt_shutdown_nic(bp);
1255 bnxt_free_tx_mbufs(bp);
1256 bnxt_free_rx_mbufs(bp);
1257 bnxt_hwrm_if_change(bp, false);
1258 eth_dev->data->dev_started = 0;
1262 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1264 struct bnxt *bp = eth_dev->data->dev_private;
1267 if (!bp->link_info->link_up)
1268 rc = bnxt_set_hwrm_link_config(bp, true);
1270 eth_dev->data->dev_link.link_status = 1;
1272 bnxt_print_link_info(eth_dev);
1276 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1278 struct bnxt *bp = eth_dev->data->dev_private;
1280 eth_dev->data->dev_link.link_status = 0;
1281 bnxt_set_hwrm_link_config(bp, false);
1282 bp->link_info->link_up = 0;
1287 static void bnxt_free_switch_domain(struct bnxt *bp)
1289 if (bp->switch_domain_id)
1290 rte_eth_switch_domain_free(bp->switch_domain_id);
1293 /* Unload the driver, release resources */
1294 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1296 struct bnxt *bp = eth_dev->data->dev_private;
1297 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1298 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1300 eth_dev->data->dev_started = 0;
1301 eth_dev->data->scattered_rx = 0;
1303 /* Prevent crashes when queues are still in use */
1304 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1305 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1307 bnxt_disable_int(bp);
1309 /* disable uio/vfio intr/eventfd mapping */
1310 rte_intr_disable(intr_handle);
1312 /* delete the bnxt ULP port details */
1313 bnxt_ulp_port_deinit(bp);
1315 bnxt_cancel_fw_health_check(bp);
1317 bnxt_dev_set_link_down_op(eth_dev);
1319 /* Wait for link to be reset and the async notification to process.
1320 * During reset recovery, there is no need to wait and
1321 * VF/NPAR functions do not have privilege to change PHY config.
1323 if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1324 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1326 /* Clean queue intr-vector mapping */
1327 rte_intr_efd_disable(intr_handle);
1328 if (intr_handle->intr_vec != NULL) {
1329 rte_free(intr_handle->intr_vec);
1330 intr_handle->intr_vec = NULL;
1333 bnxt_hwrm_port_clr_stats(bp);
1334 bnxt_free_tx_mbufs(bp);
1335 bnxt_free_rx_mbufs(bp);
1336 /* Process any remaining notifications in default completion queue */
1337 bnxt_int_handler(eth_dev);
1338 bnxt_shutdown_nic(bp);
1339 bnxt_hwrm_if_change(bp, false);
1341 rte_free(bp->mark_table);
1342 bp->mark_table = NULL;
1344 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1345 bp->rx_cosq_cnt = 0;
1346 /* All filters are deleted on a port stop. */
1347 if (BNXT_FLOW_XSTATS_EN(bp))
1348 bp->flow_stat->flow_count = 0;
1351 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1353 struct bnxt *bp = eth_dev->data->dev_private;
1355 /* cancel the recovery handler before remove dev */
1356 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1357 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1358 bnxt_cancel_fc_thread(bp);
1360 if (eth_dev->data->dev_started)
1361 bnxt_dev_stop_op(eth_dev);
1363 bnxt_free_switch_domain(bp);
1365 bnxt_uninit_resources(bp, false);
1367 bnxt_free_leds_info(bp);
1368 bnxt_free_cos_queues(bp);
1369 bnxt_free_link_info(bp);
1370 bnxt_free_pf_info(bp);
1371 bnxt_free_parent_info(bp);
1373 eth_dev->dev_ops = NULL;
1374 eth_dev->rx_pkt_burst = NULL;
1375 eth_dev->tx_pkt_burst = NULL;
1377 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1378 bp->tx_mem_zone = NULL;
1379 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1380 bp->rx_mem_zone = NULL;
1382 bnxt_hwrm_free_vf_info(bp);
1384 rte_free(bp->grp_info);
1385 bp->grp_info = NULL;
1388 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1391 struct bnxt *bp = eth_dev->data->dev_private;
1392 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1393 struct bnxt_vnic_info *vnic;
1394 struct bnxt_filter_info *filter, *temp_filter;
1397 if (is_bnxt_in_error(bp))
1401 * Loop through all VNICs from the specified filter flow pools to
1402 * remove the corresponding MAC addr filter
1404 for (i = 0; i < bp->nr_vnics; i++) {
1405 if (!(pool_mask & (1ULL << i)))
1408 vnic = &bp->vnic_info[i];
1409 filter = STAILQ_FIRST(&vnic->filter);
1411 temp_filter = STAILQ_NEXT(filter, next);
1412 if (filter->mac_index == index) {
1413 STAILQ_REMOVE(&vnic->filter, filter,
1414 bnxt_filter_info, next);
1415 bnxt_hwrm_clear_l2_filter(bp, filter);
1416 bnxt_free_filter(bp, filter);
1418 filter = temp_filter;
1423 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1424 struct rte_ether_addr *mac_addr, uint32_t index,
1427 struct bnxt_filter_info *filter;
1430 /* Attach requested MAC address to the new l2_filter */
1431 STAILQ_FOREACH(filter, &vnic->filter, next) {
1432 if (filter->mac_index == index) {
1434 "MAC addr already existed for pool %d\n",
1440 filter = bnxt_alloc_filter(bp);
1442 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1446 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1447 * if the MAC that's been programmed now is a different one, then,
1448 * copy that addr to filter->l2_addr
1451 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1452 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1454 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1456 filter->mac_index = index;
1457 if (filter->mac_index == 0)
1458 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1460 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1462 bnxt_free_filter(bp, filter);
1468 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1469 struct rte_ether_addr *mac_addr,
1470 uint32_t index, uint32_t pool)
1472 struct bnxt *bp = eth_dev->data->dev_private;
1473 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1476 rc = is_bnxt_in_error(bp);
1480 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1481 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1486 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1490 /* Filter settings will get applied when port is started */
1491 if (!eth_dev->data->dev_started)
1494 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1499 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1500 bool exp_link_status)
1503 struct bnxt *bp = eth_dev->data->dev_private;
1504 struct rte_eth_link new;
1505 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1506 BNXT_LINK_DOWN_WAIT_CNT;
1508 rc = is_bnxt_in_error(bp);
1512 memset(&new, 0, sizeof(new));
1514 /* Retrieve link info from hardware */
1515 rc = bnxt_get_hwrm_link_config(bp, &new);
1517 new.link_speed = ETH_LINK_SPEED_100M;
1518 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1520 "Failed to retrieve link rc = 0x%x!\n", rc);
1524 if (!wait_to_complete || new.link_status == exp_link_status)
1527 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1531 /* Timed out or success */
1532 if (new.link_status != eth_dev->data->dev_link.link_status ||
1533 new.link_speed != eth_dev->data->dev_link.link_speed) {
1534 rte_eth_linkstatus_set(eth_dev, &new);
1536 rte_eth_dev_callback_process(eth_dev,
1537 RTE_ETH_EVENT_INTR_LSC,
1540 bnxt_print_link_info(eth_dev);
1546 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1547 int wait_to_complete)
1549 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1552 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1554 struct bnxt *bp = eth_dev->data->dev_private;
1555 struct bnxt_vnic_info *vnic;
1559 rc = is_bnxt_in_error(bp);
1563 /* Filter settings will get applied when port is started */
1564 if (!eth_dev->data->dev_started)
1567 if (bp->vnic_info == NULL)
1570 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1572 old_flags = vnic->flags;
1573 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1574 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1576 vnic->flags = old_flags;
1581 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1583 struct bnxt *bp = eth_dev->data->dev_private;
1584 struct bnxt_vnic_info *vnic;
1588 rc = is_bnxt_in_error(bp);
1592 /* Filter settings will get applied when port is started */
1593 if (!eth_dev->data->dev_started)
1596 if (bp->vnic_info == NULL)
1599 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1601 old_flags = vnic->flags;
1602 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1603 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1605 vnic->flags = old_flags;
1610 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1612 struct bnxt *bp = eth_dev->data->dev_private;
1613 struct bnxt_vnic_info *vnic;
1617 rc = is_bnxt_in_error(bp);
1621 /* Filter settings will get applied when port is started */
1622 if (!eth_dev->data->dev_started)
1625 if (bp->vnic_info == NULL)
1628 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1630 old_flags = vnic->flags;
1631 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1632 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1634 vnic->flags = old_flags;
1639 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1641 struct bnxt *bp = eth_dev->data->dev_private;
1642 struct bnxt_vnic_info *vnic;
1646 rc = is_bnxt_in_error(bp);
1650 /* Filter settings will get applied when port is started */
1651 if (!eth_dev->data->dev_started)
1654 if (bp->vnic_info == NULL)
1657 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1659 old_flags = vnic->flags;
1660 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1661 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1663 vnic->flags = old_flags;
1668 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1669 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1671 if (qid >= bp->rx_nr_rings)
1674 return bp->eth_dev->data->rx_queues[qid];
1677 /* Return rxq corresponding to a given rss table ring/group ID. */
1678 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1680 struct bnxt_rx_queue *rxq;
1683 if (!BNXT_HAS_RING_GRPS(bp)) {
1684 for (i = 0; i < bp->rx_nr_rings; i++) {
1685 rxq = bp->eth_dev->data->rx_queues[i];
1686 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1690 for (i = 0; i < bp->rx_nr_rings; i++) {
1691 if (bp->grp_info[i].fw_grp_id == fwr)
1696 return INVALID_HW_RING_ID;
1699 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1700 struct rte_eth_rss_reta_entry64 *reta_conf,
1703 struct bnxt *bp = eth_dev->data->dev_private;
1704 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1705 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1706 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1710 rc = is_bnxt_in_error(bp);
1714 if (!vnic->rss_table)
1717 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1720 if (reta_size != tbl_size) {
1721 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1722 "(%d) must equal the size supported by the hardware "
1723 "(%d)\n", reta_size, tbl_size);
1727 for (i = 0; i < reta_size; i++) {
1728 struct bnxt_rx_queue *rxq;
1730 idx = i / RTE_RETA_GROUP_SIZE;
1731 sft = i % RTE_RETA_GROUP_SIZE;
1733 if (!(reta_conf[idx].mask & (1ULL << sft)))
1736 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1738 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1742 if (BNXT_CHIP_THOR(bp)) {
1743 vnic->rss_table[i * 2] =
1744 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1745 vnic->rss_table[i * 2 + 1] =
1746 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1748 vnic->rss_table[i] =
1749 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1753 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1757 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1758 struct rte_eth_rss_reta_entry64 *reta_conf,
1761 struct bnxt *bp = eth_dev->data->dev_private;
1762 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1763 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1764 uint16_t idx, sft, i;
1767 rc = is_bnxt_in_error(bp);
1771 /* Retrieve from the default VNIC */
1774 if (!vnic->rss_table)
1777 if (reta_size != tbl_size) {
1778 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1779 "(%d) must equal the size supported by the hardware "
1780 "(%d)\n", reta_size, tbl_size);
1784 for (idx = 0, i = 0; i < reta_size; i++) {
1785 idx = i / RTE_RETA_GROUP_SIZE;
1786 sft = i % RTE_RETA_GROUP_SIZE;
1788 if (reta_conf[idx].mask & (1ULL << sft)) {
1791 if (BNXT_CHIP_THOR(bp))
1792 qid = bnxt_rss_to_qid(bp,
1793 vnic->rss_table[i * 2]);
1795 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1797 if (qid == INVALID_HW_RING_ID) {
1798 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1801 reta_conf[idx].reta[sft] = qid;
1808 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1809 struct rte_eth_rss_conf *rss_conf)
1811 struct bnxt *bp = eth_dev->data->dev_private;
1812 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1813 struct bnxt_vnic_info *vnic;
1816 rc = is_bnxt_in_error(bp);
1821 * If RSS enablement were different than dev_configure,
1822 * then return -EINVAL
1824 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1825 if (!rss_conf->rss_hf)
1826 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1828 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1832 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1833 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
1837 /* Update the default RSS VNIC(s) */
1838 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1839 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1842 * If hashkey is not specified, use the previously configured
1845 if (!rss_conf->rss_key)
1848 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1850 "Invalid hashkey length, should be 16 bytes\n");
1853 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1856 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1860 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1861 struct rte_eth_rss_conf *rss_conf)
1863 struct bnxt *bp = eth_dev->data->dev_private;
1864 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1866 uint32_t hash_types;
1868 rc = is_bnxt_in_error(bp);
1872 /* RSS configuration is the same for all VNICs */
1873 if (vnic && vnic->rss_hash_key) {
1874 if (rss_conf->rss_key) {
1875 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1876 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1877 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1880 hash_types = vnic->hash_type;
1881 rss_conf->rss_hf = 0;
1882 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1883 rss_conf->rss_hf |= ETH_RSS_IPV4;
1884 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1886 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1887 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1889 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1891 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1892 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1894 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1896 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1897 rss_conf->rss_hf |= ETH_RSS_IPV6;
1898 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1900 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1901 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1903 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1905 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1906 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1908 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1912 "Unknown RSS config from firmware (%08x), RSS disabled",
1917 rss_conf->rss_hf = 0;
1922 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1923 struct rte_eth_fc_conf *fc_conf)
1925 struct bnxt *bp = dev->data->dev_private;
1926 struct rte_eth_link link_info;
1929 rc = is_bnxt_in_error(bp);
1933 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1937 memset(fc_conf, 0, sizeof(*fc_conf));
1938 if (bp->link_info->auto_pause)
1939 fc_conf->autoneg = 1;
1940 switch (bp->link_info->pause) {
1942 fc_conf->mode = RTE_FC_NONE;
1944 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1945 fc_conf->mode = RTE_FC_TX_PAUSE;
1947 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1948 fc_conf->mode = RTE_FC_RX_PAUSE;
1950 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1951 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1952 fc_conf->mode = RTE_FC_FULL;
1958 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1959 struct rte_eth_fc_conf *fc_conf)
1961 struct bnxt *bp = dev->data->dev_private;
1964 rc = is_bnxt_in_error(bp);
1968 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1969 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1973 switch (fc_conf->mode) {
1975 bp->link_info->auto_pause = 0;
1976 bp->link_info->force_pause = 0;
1978 case RTE_FC_RX_PAUSE:
1979 if (fc_conf->autoneg) {
1980 bp->link_info->auto_pause =
1981 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1982 bp->link_info->force_pause = 0;
1984 bp->link_info->auto_pause = 0;
1985 bp->link_info->force_pause =
1986 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1989 case RTE_FC_TX_PAUSE:
1990 if (fc_conf->autoneg) {
1991 bp->link_info->auto_pause =
1992 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1993 bp->link_info->force_pause = 0;
1995 bp->link_info->auto_pause = 0;
1996 bp->link_info->force_pause =
1997 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2001 if (fc_conf->autoneg) {
2002 bp->link_info->auto_pause =
2003 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2004 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2005 bp->link_info->force_pause = 0;
2007 bp->link_info->auto_pause = 0;
2008 bp->link_info->force_pause =
2009 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2010 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2014 return bnxt_set_hwrm_link_config(bp, true);
2017 /* Add UDP tunneling port */
2019 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2020 struct rte_eth_udp_tunnel *udp_tunnel)
2022 struct bnxt *bp = eth_dev->data->dev_private;
2023 uint16_t tunnel_type = 0;
2026 rc = is_bnxt_in_error(bp);
2030 switch (udp_tunnel->prot_type) {
2031 case RTE_TUNNEL_TYPE_VXLAN:
2032 if (bp->vxlan_port_cnt) {
2033 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2034 udp_tunnel->udp_port);
2035 if (bp->vxlan_port != udp_tunnel->udp_port) {
2036 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2039 bp->vxlan_port_cnt++;
2043 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2044 bp->vxlan_port_cnt++;
2046 case RTE_TUNNEL_TYPE_GENEVE:
2047 if (bp->geneve_port_cnt) {
2048 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2049 udp_tunnel->udp_port);
2050 if (bp->geneve_port != udp_tunnel->udp_port) {
2051 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2054 bp->geneve_port_cnt++;
2058 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2059 bp->geneve_port_cnt++;
2062 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2065 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2071 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2072 struct rte_eth_udp_tunnel *udp_tunnel)
2074 struct bnxt *bp = eth_dev->data->dev_private;
2075 uint16_t tunnel_type = 0;
2079 rc = is_bnxt_in_error(bp);
2083 switch (udp_tunnel->prot_type) {
2084 case RTE_TUNNEL_TYPE_VXLAN:
2085 if (!bp->vxlan_port_cnt) {
2086 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2089 if (bp->vxlan_port != udp_tunnel->udp_port) {
2090 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2091 udp_tunnel->udp_port, bp->vxlan_port);
2094 if (--bp->vxlan_port_cnt)
2098 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2099 port = bp->vxlan_fw_dst_port_id;
2101 case RTE_TUNNEL_TYPE_GENEVE:
2102 if (!bp->geneve_port_cnt) {
2103 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2106 if (bp->geneve_port != udp_tunnel->udp_port) {
2107 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2108 udp_tunnel->udp_port, bp->geneve_port);
2111 if (--bp->geneve_port_cnt)
2115 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2116 port = bp->geneve_fw_dst_port_id;
2119 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2123 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2126 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2129 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2130 bp->geneve_port = 0;
2135 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2137 struct bnxt_filter_info *filter;
2138 struct bnxt_vnic_info *vnic;
2140 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2142 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2143 filter = STAILQ_FIRST(&vnic->filter);
2145 /* Search for this matching MAC+VLAN filter */
2146 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2147 /* Delete the filter */
2148 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2151 STAILQ_REMOVE(&vnic->filter, filter,
2152 bnxt_filter_info, next);
2153 bnxt_free_filter(bp, filter);
2155 "Deleted vlan filter for %d\n",
2159 filter = STAILQ_NEXT(filter, next);
2164 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2166 struct bnxt_filter_info *filter;
2167 struct bnxt_vnic_info *vnic;
2169 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2170 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2171 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2173 /* Implementation notes on the use of VNIC in this command:
2175 * By default, these filters belong to default vnic for the function.
2176 * Once these filters are set up, only destination VNIC can be modified.
2177 * If the destination VNIC is not specified in this command,
2178 * then the HWRM shall only create an l2 context id.
2181 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2182 filter = STAILQ_FIRST(&vnic->filter);
2183 /* Check if the VLAN has already been added */
2185 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2188 filter = STAILQ_NEXT(filter, next);
2191 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2192 * command to create MAC+VLAN filter with the right flags, enables set.
2194 filter = bnxt_alloc_filter(bp);
2197 "MAC/VLAN filter alloc failed\n");
2200 /* MAC + VLAN ID filter */
2201 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2202 * untagged packets are received
2204 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2205 * packets and only the programmed vlan's packets are received
2207 filter->l2_ivlan = vlan_id;
2208 filter->l2_ivlan_mask = 0x0FFF;
2209 filter->enables |= en;
2210 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2212 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2214 /* Free the newly allocated filter as we were
2215 * not able to create the filter in hardware.
2217 bnxt_free_filter(bp, filter);
2221 filter->mac_index = 0;
2222 /* Add this new filter to the list */
2224 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2226 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2229 "Added Vlan filter for %d\n", vlan_id);
2233 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2234 uint16_t vlan_id, int on)
2236 struct bnxt *bp = eth_dev->data->dev_private;
2239 rc = is_bnxt_in_error(bp);
2243 if (!eth_dev->data->dev_started) {
2244 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2248 /* These operations apply to ALL existing MAC/VLAN filters */
2250 return bnxt_add_vlan_filter(bp, vlan_id);
2252 return bnxt_del_vlan_filter(bp, vlan_id);
2255 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2256 struct bnxt_vnic_info *vnic)
2258 struct bnxt_filter_info *filter;
2261 filter = STAILQ_FIRST(&vnic->filter);
2263 if (filter->mac_index == 0 &&
2264 !memcmp(filter->l2_addr, bp->mac_addr,
2265 RTE_ETHER_ADDR_LEN)) {
2266 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2268 STAILQ_REMOVE(&vnic->filter, filter,
2269 bnxt_filter_info, next);
2270 bnxt_free_filter(bp, filter);
2274 filter = STAILQ_NEXT(filter, next);
2280 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2282 struct bnxt_vnic_info *vnic;
2286 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2287 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2288 /* Remove any VLAN filters programmed */
2289 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2290 bnxt_del_vlan_filter(bp, i);
2292 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2296 /* Default filter will allow packets that match the
2297 * dest mac. So, it has to be deleted, otherwise, we
2298 * will endup receiving vlan packets for which the
2299 * filter is not programmed, when hw-vlan-filter
2300 * configuration is ON
2302 bnxt_del_dflt_mac_filter(bp, vnic);
2303 /* This filter will allow only untagged packets */
2304 bnxt_add_vlan_filter(bp, 0);
2306 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2307 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2312 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2314 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2318 /* Destroy vnic filters and vnic */
2319 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2320 DEV_RX_OFFLOAD_VLAN_FILTER) {
2321 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2322 bnxt_del_vlan_filter(bp, i);
2324 bnxt_del_dflt_mac_filter(bp, vnic);
2326 rc = bnxt_hwrm_vnic_free(bp, vnic);
2330 rte_free(vnic->fw_grp_ids);
2331 vnic->fw_grp_ids = NULL;
2333 vnic->rx_queue_cnt = 0;
2339 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2341 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2344 /* Destroy, recreate and reconfigure the default vnic */
2345 rc = bnxt_free_one_vnic(bp, 0);
2349 /* default vnic 0 */
2350 rc = bnxt_setup_one_vnic(bp, 0);
2354 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2355 DEV_RX_OFFLOAD_VLAN_FILTER) {
2356 rc = bnxt_add_vlan_filter(bp, 0);
2359 rc = bnxt_restore_vlan_filters(bp);
2363 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2368 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2372 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2373 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2379 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2381 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2382 struct bnxt *bp = dev->data->dev_private;
2385 rc = is_bnxt_in_error(bp);
2389 /* Filter settings will get applied when port is started */
2390 if (!dev->data->dev_started)
2393 if (mask & ETH_VLAN_FILTER_MASK) {
2394 /* Enable or disable VLAN filtering */
2395 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2400 if (mask & ETH_VLAN_STRIP_MASK) {
2401 /* Enable or disable VLAN stripping */
2402 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2407 if (mask & ETH_VLAN_EXTEND_MASK) {
2408 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2409 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2411 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2418 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2421 struct bnxt *bp = dev->data->dev_private;
2422 int qinq = dev->data->dev_conf.rxmode.offloads &
2423 DEV_RX_OFFLOAD_VLAN_EXTEND;
2425 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2426 vlan_type != ETH_VLAN_TYPE_OUTER) {
2428 "Unsupported vlan type.");
2433 "QinQ not enabled. Needs to be ON as we can "
2434 "accelerate only outer vlan\n");
2438 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2440 case RTE_ETHER_TYPE_QINQ:
2442 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2444 case RTE_ETHER_TYPE_VLAN:
2446 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2448 case RTE_ETHER_TYPE_QINQ1:
2450 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2452 case RTE_ETHER_TYPE_QINQ2:
2454 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2456 case RTE_ETHER_TYPE_QINQ3:
2458 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2461 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2464 bp->outer_tpid_bd |= tpid;
2465 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2466 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2468 "Can accelerate only outer vlan in QinQ\n");
2476 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2477 struct rte_ether_addr *addr)
2479 struct bnxt *bp = dev->data->dev_private;
2480 /* Default Filter is tied to VNIC 0 */
2481 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2484 rc = is_bnxt_in_error(bp);
2488 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2491 if (rte_is_zero_ether_addr(addr))
2494 /* Filter settings will get applied when port is started */
2495 if (!dev->data->dev_started)
2498 /* Check if the requested MAC is already added */
2499 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2502 /* Destroy filter and re-create it */
2503 bnxt_del_dflt_mac_filter(bp, vnic);
2505 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2506 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2507 /* This filter will allow only untagged packets */
2508 rc = bnxt_add_vlan_filter(bp, 0);
2510 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2513 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2518 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2519 struct rte_ether_addr *mc_addr_set,
2520 uint32_t nb_mc_addr)
2522 struct bnxt *bp = eth_dev->data->dev_private;
2523 char *mc_addr_list = (char *)mc_addr_set;
2524 struct bnxt_vnic_info *vnic;
2525 uint32_t off = 0, i = 0;
2528 rc = is_bnxt_in_error(bp);
2532 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2534 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2535 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2539 /* TODO Check for Duplicate mcast addresses */
2540 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2541 for (i = 0; i < nb_mc_addr; i++) {
2542 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2543 RTE_ETHER_ADDR_LEN);
2544 off += RTE_ETHER_ADDR_LEN;
2547 vnic->mc_addr_cnt = i;
2548 if (vnic->mc_addr_cnt)
2549 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2551 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2554 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2558 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2560 struct bnxt *bp = dev->data->dev_private;
2561 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2562 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2563 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2564 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2567 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2568 fw_major, fw_minor, fw_updt, fw_rsvd);
2570 ret += 1; /* add the size of '\0' */
2571 if (fw_size < (uint32_t)ret)
2578 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2579 struct rte_eth_rxq_info *qinfo)
2581 struct bnxt *bp = dev->data->dev_private;
2582 struct bnxt_rx_queue *rxq;
2584 if (is_bnxt_in_error(bp))
2587 rxq = dev->data->rx_queues[queue_id];
2589 qinfo->mp = rxq->mb_pool;
2590 qinfo->scattered_rx = dev->data->scattered_rx;
2591 qinfo->nb_desc = rxq->nb_rx_desc;
2593 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2594 qinfo->conf.rx_drop_en = 0;
2595 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2599 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2600 struct rte_eth_txq_info *qinfo)
2602 struct bnxt *bp = dev->data->dev_private;
2603 struct bnxt_tx_queue *txq;
2605 if (is_bnxt_in_error(bp))
2608 txq = dev->data->tx_queues[queue_id];
2610 qinfo->nb_desc = txq->nb_tx_desc;
2612 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2613 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2614 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2616 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2617 qinfo->conf.tx_rs_thresh = 0;
2618 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2621 static const struct {
2622 eth_rx_burst_t pkt_burst;
2624 } bnxt_rx_burst_info[] = {
2625 {bnxt_recv_pkts, "Scalar"},
2626 #if defined(RTE_ARCH_X86)
2627 {bnxt_recv_pkts_vec, "Vector SSE"},
2628 #elif defined(RTE_ARCH_ARM64)
2629 {bnxt_recv_pkts_vec, "Vector Neon"},
2634 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2635 struct rte_eth_burst_mode *mode)
2637 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2640 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2641 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2642 snprintf(mode->info, sizeof(mode->info), "%s",
2643 bnxt_rx_burst_info[i].info);
2651 static const struct {
2652 eth_tx_burst_t pkt_burst;
2654 } bnxt_tx_burst_info[] = {
2655 {bnxt_xmit_pkts, "Scalar"},
2656 #if defined(RTE_ARCH_X86)
2657 {bnxt_xmit_pkts_vec, "Vector SSE"},
2658 #elif defined(RTE_ARCH_ARM64)
2659 {bnxt_xmit_pkts_vec, "Vector Neon"},
2664 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2665 struct rte_eth_burst_mode *mode)
2667 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2670 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2671 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2672 snprintf(mode->info, sizeof(mode->info), "%s",
2673 bnxt_tx_burst_info[i].info);
2681 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2683 struct bnxt *bp = eth_dev->data->dev_private;
2684 uint32_t new_pkt_size;
2688 rc = is_bnxt_in_error(bp);
2692 /* Exit if receive queues are not configured yet */
2693 if (!eth_dev->data->nb_rx_queues)
2696 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2697 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2700 * Disallow any MTU change that would require scattered receive support
2701 * if it is not already enabled.
2703 if (eth_dev->data->dev_started &&
2704 !eth_dev->data->scattered_rx &&
2706 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2708 "MTU change would require scattered rx support. ");
2709 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2713 if (new_mtu > RTE_ETHER_MTU) {
2714 bp->flags |= BNXT_FLAG_JUMBO;
2715 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2716 DEV_RX_OFFLOAD_JUMBO_FRAME;
2718 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2719 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2720 bp->flags &= ~BNXT_FLAG_JUMBO;
2723 /* Is there a change in mtu setting? */
2724 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2727 for (i = 0; i < bp->nr_vnics; i++) {
2728 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2731 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2732 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2736 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2737 size -= RTE_PKTMBUF_HEADROOM;
2739 if (size < new_mtu) {
2740 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2747 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2749 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2755 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2757 struct bnxt *bp = dev->data->dev_private;
2758 uint16_t vlan = bp->vlan;
2761 rc = is_bnxt_in_error(bp);
2765 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2767 "PVID cannot be modified for this function\n");
2770 bp->vlan = on ? pvid : 0;
2772 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2779 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2781 struct bnxt *bp = dev->data->dev_private;
2784 rc = is_bnxt_in_error(bp);
2788 return bnxt_hwrm_port_led_cfg(bp, true);
2792 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2794 struct bnxt *bp = dev->data->dev_private;
2797 rc = is_bnxt_in_error(bp);
2801 return bnxt_hwrm_port_led_cfg(bp, false);
2805 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2807 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2808 uint32_t desc = 0, raw_cons = 0, cons;
2809 struct bnxt_cp_ring_info *cpr;
2810 struct bnxt_rx_queue *rxq;
2811 struct rx_pkt_cmpl *rxcmp;
2814 rc = is_bnxt_in_error(bp);
2818 rxq = dev->data->rx_queues[rx_queue_id];
2820 raw_cons = cpr->cp_raw_cons;
2823 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2824 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2825 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2827 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2839 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2841 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2842 struct bnxt_rx_ring_info *rxr;
2843 struct bnxt_cp_ring_info *cpr;
2844 struct rte_mbuf *rx_buf;
2845 struct rx_pkt_cmpl *rxcmp;
2846 uint32_t cons, cp_cons;
2852 rc = is_bnxt_in_error(rxq->bp);
2859 if (offset >= rxq->nb_rx_desc)
2862 cons = RING_CMP(cpr->cp_ring_struct, offset);
2863 cp_cons = cpr->cp_raw_cons;
2864 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2866 if (cons > cp_cons) {
2867 if (CMPL_VALID(rxcmp, cpr->valid))
2868 return RTE_ETH_RX_DESC_DONE;
2870 if (CMPL_VALID(rxcmp, !cpr->valid))
2871 return RTE_ETH_RX_DESC_DONE;
2873 rx_buf = rxr->rx_buf_ring[cons];
2874 if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2875 return RTE_ETH_RX_DESC_UNAVAIL;
2878 return RTE_ETH_RX_DESC_AVAIL;
2882 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2884 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2885 struct bnxt_tx_ring_info *txr;
2886 struct bnxt_cp_ring_info *cpr;
2887 struct bnxt_sw_tx_bd *tx_buf;
2888 struct tx_pkt_cmpl *txcmp;
2889 uint32_t cons, cp_cons;
2895 rc = is_bnxt_in_error(txq->bp);
2902 if (offset >= txq->nb_tx_desc)
2905 cons = RING_CMP(cpr->cp_ring_struct, offset);
2906 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2907 cp_cons = cpr->cp_raw_cons;
2909 if (cons > cp_cons) {
2910 if (CMPL_VALID(txcmp, cpr->valid))
2911 return RTE_ETH_TX_DESC_UNAVAIL;
2913 if (CMPL_VALID(txcmp, !cpr->valid))
2914 return RTE_ETH_TX_DESC_UNAVAIL;
2916 tx_buf = &txr->tx_buf_ring[cons];
2917 if (tx_buf->mbuf == NULL)
2918 return RTE_ETH_TX_DESC_DONE;
2920 return RTE_ETH_TX_DESC_FULL;
2923 static struct bnxt_filter_info *
2924 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2925 struct rte_eth_ethertype_filter *efilter,
2926 struct bnxt_vnic_info *vnic0,
2927 struct bnxt_vnic_info *vnic,
2930 struct bnxt_filter_info *mfilter = NULL;
2934 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2935 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2936 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2937 " ethertype filter.", efilter->ether_type);
2941 if (efilter->queue >= bp->rx_nr_rings) {
2942 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2947 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2948 vnic = &bp->vnic_info[efilter->queue];
2950 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2955 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2956 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2957 if ((!memcmp(efilter->mac_addr.addr_bytes,
2958 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2960 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2961 mfilter->ethertype == efilter->ether_type)) {
2967 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2968 if ((!memcmp(efilter->mac_addr.addr_bytes,
2969 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2970 mfilter->ethertype == efilter->ether_type &&
2972 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2986 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2987 enum rte_filter_op filter_op,
2990 struct bnxt *bp = dev->data->dev_private;
2991 struct rte_eth_ethertype_filter *efilter =
2992 (struct rte_eth_ethertype_filter *)arg;
2993 struct bnxt_filter_info *bfilter, *filter1;
2994 struct bnxt_vnic_info *vnic, *vnic0;
2997 if (filter_op == RTE_ETH_FILTER_NOP)
3001 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3006 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3007 vnic = &bp->vnic_info[efilter->queue];
3009 switch (filter_op) {
3010 case RTE_ETH_FILTER_ADD:
3011 bnxt_match_and_validate_ether_filter(bp, efilter,
3016 bfilter = bnxt_get_unused_filter(bp);
3017 if (bfilter == NULL) {
3019 "Not enough resources for a new filter.\n");
3022 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3023 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
3024 RTE_ETHER_ADDR_LEN);
3025 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
3026 RTE_ETHER_ADDR_LEN);
3027 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3028 bfilter->ethertype = efilter->ether_type;
3029 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3031 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3032 if (filter1 == NULL) {
3037 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3038 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3040 bfilter->dst_id = vnic->fw_vnic_id;
3042 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3044 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3047 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3050 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3052 case RTE_ETH_FILTER_DELETE:
3053 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3055 if (ret == -EEXIST) {
3056 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3058 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3060 bnxt_free_filter(bp, filter1);
3061 } else if (ret == 0) {
3062 PMD_DRV_LOG(ERR, "No matching filter found\n");
3066 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3072 bnxt_free_filter(bp, bfilter);
3078 parse_ntuple_filter(struct bnxt *bp,
3079 struct rte_eth_ntuple_filter *nfilter,
3080 struct bnxt_filter_info *bfilter)
3084 if (nfilter->queue >= bp->rx_nr_rings) {
3085 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3089 switch (nfilter->dst_port_mask) {
3091 bfilter->dst_port_mask = -1;
3092 bfilter->dst_port = nfilter->dst_port;
3093 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3094 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3097 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3101 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3102 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3104 switch (nfilter->proto_mask) {
3106 if (nfilter->proto == 17) /* IPPROTO_UDP */
3107 bfilter->ip_protocol = 17;
3108 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3109 bfilter->ip_protocol = 6;
3112 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3115 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3119 switch (nfilter->dst_ip_mask) {
3121 bfilter->dst_ipaddr_mask[0] = -1;
3122 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3123 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3124 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3127 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3131 switch (nfilter->src_ip_mask) {
3133 bfilter->src_ipaddr_mask[0] = -1;
3134 bfilter->src_ipaddr[0] = nfilter->src_ip;
3135 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3136 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3139 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3143 switch (nfilter->src_port_mask) {
3145 bfilter->src_port_mask = -1;
3146 bfilter->src_port = nfilter->src_port;
3147 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3148 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3151 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3155 bfilter->enables = en;
3159 static struct bnxt_filter_info*
3160 bnxt_match_ntuple_filter(struct bnxt *bp,
3161 struct bnxt_filter_info *bfilter,
3162 struct bnxt_vnic_info **mvnic)
3164 struct bnxt_filter_info *mfilter = NULL;
3167 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3168 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3169 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3170 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3171 bfilter->src_ipaddr_mask[0] ==
3172 mfilter->src_ipaddr_mask[0] &&
3173 bfilter->src_port == mfilter->src_port &&
3174 bfilter->src_port_mask == mfilter->src_port_mask &&
3175 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3176 bfilter->dst_ipaddr_mask[0] ==
3177 mfilter->dst_ipaddr_mask[0] &&
3178 bfilter->dst_port == mfilter->dst_port &&
3179 bfilter->dst_port_mask == mfilter->dst_port_mask &&
3180 bfilter->flags == mfilter->flags &&
3181 bfilter->enables == mfilter->enables) {
3192 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3193 struct rte_eth_ntuple_filter *nfilter,
3194 enum rte_filter_op filter_op)
3196 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3197 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3200 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3201 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3205 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3206 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3210 bfilter = bnxt_get_unused_filter(bp);
3211 if (bfilter == NULL) {
3213 "Not enough resources for a new filter.\n");
3216 ret = parse_ntuple_filter(bp, nfilter, bfilter);
3220 vnic = &bp->vnic_info[nfilter->queue];
3221 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3222 filter1 = STAILQ_FIRST(&vnic0->filter);
3223 if (filter1 == NULL) {
3228 bfilter->dst_id = vnic->fw_vnic_id;
3229 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3231 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3232 bfilter->ethertype = 0x800;
3233 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3235 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3237 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3238 bfilter->dst_id == mfilter->dst_id) {
3239 PMD_DRV_LOG(ERR, "filter exists.\n");
3242 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3243 bfilter->dst_id != mfilter->dst_id) {
3244 mfilter->dst_id = vnic->fw_vnic_id;
3245 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3246 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3247 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3248 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3249 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3252 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3253 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3258 if (filter_op == RTE_ETH_FILTER_ADD) {
3259 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3260 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3263 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3265 if (mfilter == NULL) {
3266 /* This should not happen. But for Coverity! */
3270 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3272 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3273 bnxt_free_filter(bp, mfilter);
3274 bnxt_free_filter(bp, bfilter);
3279 bnxt_free_filter(bp, bfilter);
3284 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3285 enum rte_filter_op filter_op,
3288 struct bnxt *bp = dev->data->dev_private;
3291 if (filter_op == RTE_ETH_FILTER_NOP)
3295 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3300 switch (filter_op) {
3301 case RTE_ETH_FILTER_ADD:
3302 ret = bnxt_cfg_ntuple_filter(bp,
3303 (struct rte_eth_ntuple_filter *)arg,
3306 case RTE_ETH_FILTER_DELETE:
3307 ret = bnxt_cfg_ntuple_filter(bp,
3308 (struct rte_eth_ntuple_filter *)arg,
3312 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3320 bnxt_parse_fdir_filter(struct bnxt *bp,
3321 struct rte_eth_fdir_filter *fdir,
3322 struct bnxt_filter_info *filter)
3324 enum rte_fdir_mode fdir_mode =
3325 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3326 struct bnxt_vnic_info *vnic0, *vnic;
3327 struct bnxt_filter_info *filter1;
3331 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3334 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3335 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3337 switch (fdir->input.flow_type) {
3338 case RTE_ETH_FLOW_IPV4:
3339 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3341 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3342 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3343 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3344 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3345 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3346 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3347 filter->ip_addr_type =
3348 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3349 filter->src_ipaddr_mask[0] = 0xffffffff;
3350 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3351 filter->dst_ipaddr_mask[0] = 0xffffffff;
3352 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3353 filter->ethertype = 0x800;
3354 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3356 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3357 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3358 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3359 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3360 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3361 filter->dst_port_mask = 0xffff;
3362 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3363 filter->src_port_mask = 0xffff;
3364 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3365 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3366 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3367 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3368 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3369 filter->ip_protocol = 6;
3370 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3371 filter->ip_addr_type =
3372 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3373 filter->src_ipaddr_mask[0] = 0xffffffff;
3374 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3375 filter->dst_ipaddr_mask[0] = 0xffffffff;
3376 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3377 filter->ethertype = 0x800;
3378 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3380 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3381 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3382 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3383 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3384 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3385 filter->dst_port_mask = 0xffff;
3386 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3387 filter->src_port_mask = 0xffff;
3388 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3389 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3390 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3391 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3392 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3393 filter->ip_protocol = 17;
3394 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3395 filter->ip_addr_type =
3396 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3397 filter->src_ipaddr_mask[0] = 0xffffffff;
3398 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3399 filter->dst_ipaddr_mask[0] = 0xffffffff;
3400 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3401 filter->ethertype = 0x800;
3402 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3404 case RTE_ETH_FLOW_IPV6:
3405 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3407 filter->ip_addr_type =
3408 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3409 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3410 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3411 rte_memcpy(filter->src_ipaddr,
3412 fdir->input.flow.ipv6_flow.src_ip, 16);
3413 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3414 rte_memcpy(filter->dst_ipaddr,
3415 fdir->input.flow.ipv6_flow.dst_ip, 16);
3416 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3417 memset(filter->dst_ipaddr_mask, 0xff, 16);
3418 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3419 memset(filter->src_ipaddr_mask, 0xff, 16);
3420 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3421 filter->ethertype = 0x86dd;
3422 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3424 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3425 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3426 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3427 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3428 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3429 filter->dst_port_mask = 0xffff;
3430 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3431 filter->src_port_mask = 0xffff;
3432 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3433 filter->ip_addr_type =
3434 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3435 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3436 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3437 rte_memcpy(filter->src_ipaddr,
3438 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3439 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3440 rte_memcpy(filter->dst_ipaddr,
3441 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3442 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3443 memset(filter->dst_ipaddr_mask, 0xff, 16);
3444 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3445 memset(filter->src_ipaddr_mask, 0xff, 16);
3446 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3447 filter->ethertype = 0x86dd;
3448 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3450 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3451 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3452 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3453 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3454 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3455 filter->dst_port_mask = 0xffff;
3456 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3457 filter->src_port_mask = 0xffff;
3458 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3459 filter->ip_addr_type =
3460 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3461 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3462 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3463 rte_memcpy(filter->src_ipaddr,
3464 fdir->input.flow.udp6_flow.ip.src_ip, 16);
3465 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3466 rte_memcpy(filter->dst_ipaddr,
3467 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3468 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3469 memset(filter->dst_ipaddr_mask, 0xff, 16);
3470 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3471 memset(filter->src_ipaddr_mask, 0xff, 16);
3472 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3473 filter->ethertype = 0x86dd;
3474 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3476 case RTE_ETH_FLOW_L2_PAYLOAD:
3477 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3478 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3480 case RTE_ETH_FLOW_VXLAN:
3481 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3483 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3484 filter->tunnel_type =
3485 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3486 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3488 case RTE_ETH_FLOW_NVGRE:
3489 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3491 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3492 filter->tunnel_type =
3493 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3494 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3496 case RTE_ETH_FLOW_UNKNOWN:
3497 case RTE_ETH_FLOW_RAW:
3498 case RTE_ETH_FLOW_FRAG_IPV4:
3499 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3500 case RTE_ETH_FLOW_FRAG_IPV6:
3501 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3502 case RTE_ETH_FLOW_IPV6_EX:
3503 case RTE_ETH_FLOW_IPV6_TCP_EX:
3504 case RTE_ETH_FLOW_IPV6_UDP_EX:
3505 case RTE_ETH_FLOW_GENEVE:
3511 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3512 vnic = &bp->vnic_info[fdir->action.rx_queue];
3514 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3518 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3519 rte_memcpy(filter->dst_macaddr,
3520 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3521 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3524 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3525 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3526 filter1 = STAILQ_FIRST(&vnic0->filter);
3527 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3529 filter->dst_id = vnic->fw_vnic_id;
3530 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3531 if (filter->dst_macaddr[i] == 0x00)
3532 filter1 = STAILQ_FIRST(&vnic0->filter);
3534 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3537 if (filter1 == NULL)
3540 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3541 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3543 filter->enables = en;
3548 static struct bnxt_filter_info *
3549 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3550 struct bnxt_vnic_info **mvnic)
3552 struct bnxt_filter_info *mf = NULL;
3555 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3556 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3558 STAILQ_FOREACH(mf, &vnic->filter, next) {
3559 if (mf->filter_type == nf->filter_type &&
3560 mf->flags == nf->flags &&
3561 mf->src_port == nf->src_port &&
3562 mf->src_port_mask == nf->src_port_mask &&
3563 mf->dst_port == nf->dst_port &&
3564 mf->dst_port_mask == nf->dst_port_mask &&
3565 mf->ip_protocol == nf->ip_protocol &&
3566 mf->ip_addr_type == nf->ip_addr_type &&
3567 mf->ethertype == nf->ethertype &&
3568 mf->vni == nf->vni &&
3569 mf->tunnel_type == nf->tunnel_type &&
3570 mf->l2_ovlan == nf->l2_ovlan &&
3571 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3572 mf->l2_ivlan == nf->l2_ivlan &&
3573 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3574 !memcmp(mf->l2_addr, nf->l2_addr,
3575 RTE_ETHER_ADDR_LEN) &&
3576 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3577 RTE_ETHER_ADDR_LEN) &&
3578 !memcmp(mf->src_macaddr, nf->src_macaddr,
3579 RTE_ETHER_ADDR_LEN) &&
3580 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3581 RTE_ETHER_ADDR_LEN) &&
3582 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3583 sizeof(nf->src_ipaddr)) &&
3584 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3585 sizeof(nf->src_ipaddr_mask)) &&
3586 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3587 sizeof(nf->dst_ipaddr)) &&
3588 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3589 sizeof(nf->dst_ipaddr_mask))) {
3600 bnxt_fdir_filter(struct rte_eth_dev *dev,
3601 enum rte_filter_op filter_op,
3604 struct bnxt *bp = dev->data->dev_private;
3605 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3606 struct bnxt_filter_info *filter, *match;
3607 struct bnxt_vnic_info *vnic, *mvnic;
3610 if (filter_op == RTE_ETH_FILTER_NOP)
3613 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3616 switch (filter_op) {
3617 case RTE_ETH_FILTER_ADD:
3618 case RTE_ETH_FILTER_DELETE:
3620 filter = bnxt_get_unused_filter(bp);
3621 if (filter == NULL) {
3623 "Not enough resources for a new flow.\n");
3627 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3630 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3632 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3633 vnic = &bp->vnic_info[0];
3635 vnic = &bp->vnic_info[fdir->action.rx_queue];
3637 match = bnxt_match_fdir(bp, filter, &mvnic);
3638 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3639 if (match->dst_id == vnic->fw_vnic_id) {
3640 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3644 match->dst_id = vnic->fw_vnic_id;
3645 ret = bnxt_hwrm_set_ntuple_filter(bp,
3648 STAILQ_REMOVE(&mvnic->filter, match,
3649 bnxt_filter_info, next);
3650 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3652 "Filter with matching pattern exist\n");
3654 "Updated it to new destination q\n");
3658 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3659 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3664 if (filter_op == RTE_ETH_FILTER_ADD) {
3665 ret = bnxt_hwrm_set_ntuple_filter(bp,
3670 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3672 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3673 STAILQ_REMOVE(&vnic->filter, match,
3674 bnxt_filter_info, next);
3675 bnxt_free_filter(bp, match);
3676 bnxt_free_filter(bp, filter);
3679 case RTE_ETH_FILTER_FLUSH:
3680 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3681 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3683 STAILQ_FOREACH(filter, &vnic->filter, next) {
3684 if (filter->filter_type ==
3685 HWRM_CFA_NTUPLE_FILTER) {
3687 bnxt_hwrm_clear_ntuple_filter(bp,
3689 STAILQ_REMOVE(&vnic->filter, filter,
3690 bnxt_filter_info, next);
3695 case RTE_ETH_FILTER_UPDATE:
3696 case RTE_ETH_FILTER_STATS:
3697 case RTE_ETH_FILTER_INFO:
3698 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3701 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3708 bnxt_free_filter(bp, filter);
3713 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3714 enum rte_filter_type filter_type,
3715 enum rte_filter_op filter_op, void *arg)
3717 struct bnxt *bp = dev->data->dev_private;
3723 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3724 struct bnxt_vf_representor *vfr = dev->data->dev_private;
3725 bp = vfr->parent_dev->data->dev_private;
3730 ret = is_bnxt_in_error(bp);
3734 switch (filter_type) {
3735 case RTE_ETH_FILTER_TUNNEL:
3737 "filter type: %d: To be implemented\n", filter_type);
3739 case RTE_ETH_FILTER_FDIR:
3740 ret = bnxt_fdir_filter(dev, filter_op, arg);
3742 case RTE_ETH_FILTER_NTUPLE:
3743 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3745 case RTE_ETH_FILTER_ETHERTYPE:
3746 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3748 case RTE_ETH_FILTER_GENERIC:
3749 if (filter_op != RTE_ETH_FILTER_GET)
3751 if (BNXT_TRUFLOW_EN(bp))
3752 *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3754 *(const void **)arg = &bnxt_flow_ops;
3758 "Filter type (%d) not supported", filter_type);
3765 static const uint32_t *
3766 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3768 static const uint32_t ptypes[] = {
3769 RTE_PTYPE_L2_ETHER_VLAN,
3770 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3771 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3775 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3776 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3777 RTE_PTYPE_INNER_L4_ICMP,
3778 RTE_PTYPE_INNER_L4_TCP,
3779 RTE_PTYPE_INNER_L4_UDP,
3783 if (!dev->rx_pkt_burst)
3789 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3792 uint32_t reg_base = *reg_arr & 0xfffff000;
3796 for (i = 0; i < count; i++) {
3797 if ((reg_arr[i] & 0xfffff000) != reg_base)
3800 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3801 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3805 static int bnxt_map_ptp_regs(struct bnxt *bp)
3807 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3811 reg_arr = ptp->rx_regs;
3812 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3816 reg_arr = ptp->tx_regs;
3817 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3821 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3822 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3824 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3825 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3830 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3832 rte_write32(0, (uint8_t *)bp->bar0 +
3833 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3834 rte_write32(0, (uint8_t *)bp->bar0 +
3835 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3838 static uint64_t bnxt_cc_read(struct bnxt *bp)
3842 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3843 BNXT_GRCPF_REG_SYNC_TIME));
3844 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3845 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3849 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3851 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3854 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3855 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3856 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3859 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3860 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3861 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3862 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3863 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3864 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3869 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3871 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3872 struct bnxt_pf_info *pf = bp->pf;
3879 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3880 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3881 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3884 port_id = pf->port_id;
3885 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3886 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3888 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3889 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3890 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3891 /* bnxt_clr_rx_ts(bp); TBD */
3895 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3896 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3897 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3898 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3904 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3907 struct bnxt *bp = dev->data->dev_private;
3908 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3913 ns = rte_timespec_to_ns(ts);
3914 /* Set the timecounters to a new value. */
3921 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3923 struct bnxt *bp = dev->data->dev_private;
3924 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3925 uint64_t ns, systime_cycles = 0;
3931 if (BNXT_CHIP_THOR(bp))
3932 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3935 systime_cycles = bnxt_cc_read(bp);
3937 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3938 *ts = rte_ns_to_timespec(ns);
3943 bnxt_timesync_enable(struct rte_eth_dev *dev)
3945 struct bnxt *bp = dev->data->dev_private;
3946 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3954 ptp->tx_tstamp_en = 1;
3955 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3957 rc = bnxt_hwrm_ptp_cfg(bp);
3961 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3962 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3963 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3965 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3966 ptp->tc.cc_shift = shift;
3967 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3969 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3970 ptp->rx_tstamp_tc.cc_shift = shift;
3971 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3973 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3974 ptp->tx_tstamp_tc.cc_shift = shift;
3975 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3977 if (!BNXT_CHIP_THOR(bp))
3978 bnxt_map_ptp_regs(bp);
3984 bnxt_timesync_disable(struct rte_eth_dev *dev)
3986 struct bnxt *bp = dev->data->dev_private;
3987 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3993 ptp->tx_tstamp_en = 0;
3996 bnxt_hwrm_ptp_cfg(bp);
3998 if (!BNXT_CHIP_THOR(bp))
3999 bnxt_unmap_ptp_regs(bp);
4005 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4006 struct timespec *timestamp,
4007 uint32_t flags __rte_unused)
4009 struct bnxt *bp = dev->data->dev_private;
4010 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4011 uint64_t rx_tstamp_cycles = 0;
4017 if (BNXT_CHIP_THOR(bp))
4018 rx_tstamp_cycles = ptp->rx_timestamp;
4020 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
4022 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
4023 *timestamp = rte_ns_to_timespec(ns);
4028 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4029 struct timespec *timestamp)
4031 struct bnxt *bp = dev->data->dev_private;
4032 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4033 uint64_t tx_tstamp_cycles = 0;
4040 if (BNXT_CHIP_THOR(bp))
4041 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4044 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4046 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4047 *timestamp = rte_ns_to_timespec(ns);
4053 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4055 struct bnxt *bp = dev->data->dev_private;
4056 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4061 ptp->tc.nsec += delta;
4067 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4069 struct bnxt *bp = dev->data->dev_private;
4071 uint32_t dir_entries;
4072 uint32_t entry_length;
4074 rc = is_bnxt_in_error(bp);
4078 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4079 bp->pdev->addr.domain, bp->pdev->addr.bus,
4080 bp->pdev->addr.devid, bp->pdev->addr.function);
4082 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4086 return dir_entries * entry_length;
4090 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4091 struct rte_dev_eeprom_info *in_eeprom)
4093 struct bnxt *bp = dev->data->dev_private;
4098 rc = is_bnxt_in_error(bp);
4102 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4103 bp->pdev->addr.domain, bp->pdev->addr.bus,
4104 bp->pdev->addr.devid, bp->pdev->addr.function,
4105 in_eeprom->offset, in_eeprom->length);
4107 if (in_eeprom->offset == 0) /* special offset value to get directory */
4108 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4111 index = in_eeprom->offset >> 24;
4112 offset = in_eeprom->offset & 0xffffff;
4115 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4116 in_eeprom->length, in_eeprom->data);
4121 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4124 case BNX_DIR_TYPE_CHIMP_PATCH:
4125 case BNX_DIR_TYPE_BOOTCODE:
4126 case BNX_DIR_TYPE_BOOTCODE_2:
4127 case BNX_DIR_TYPE_APE_FW:
4128 case BNX_DIR_TYPE_APE_PATCH:
4129 case BNX_DIR_TYPE_KONG_FW:
4130 case BNX_DIR_TYPE_KONG_PATCH:
4131 case BNX_DIR_TYPE_BONO_FW:
4132 case BNX_DIR_TYPE_BONO_PATCH:
4140 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4143 case BNX_DIR_TYPE_AVS:
4144 case BNX_DIR_TYPE_EXP_ROM_MBA:
4145 case BNX_DIR_TYPE_PCIE:
4146 case BNX_DIR_TYPE_TSCF_UCODE:
4147 case BNX_DIR_TYPE_EXT_PHY:
4148 case BNX_DIR_TYPE_CCM:
4149 case BNX_DIR_TYPE_ISCSI_BOOT:
4150 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4151 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4159 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4161 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4162 bnxt_dir_type_is_other_exec_format(dir_type);
4166 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4167 struct rte_dev_eeprom_info *in_eeprom)
4169 struct bnxt *bp = dev->data->dev_private;
4170 uint8_t index, dir_op;
4171 uint16_t type, ext, ordinal, attr;
4174 rc = is_bnxt_in_error(bp);
4178 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4179 bp->pdev->addr.domain, bp->pdev->addr.bus,
4180 bp->pdev->addr.devid, bp->pdev->addr.function,
4181 in_eeprom->offset, in_eeprom->length);
4184 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4188 type = in_eeprom->magic >> 16;
4190 if (type == 0xffff) { /* special value for directory operations */
4191 index = in_eeprom->magic & 0xff;
4192 dir_op = in_eeprom->magic >> 8;
4196 case 0x0e: /* erase */
4197 if (in_eeprom->offset != ~in_eeprom->magic)
4199 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4205 /* Create or re-write an NVM item: */
4206 if (bnxt_dir_type_is_executable(type) == true)
4208 ext = in_eeprom->magic & 0xffff;
4209 ordinal = in_eeprom->offset >> 16;
4210 attr = in_eeprom->offset & 0xffff;
4212 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4213 in_eeprom->data, in_eeprom->length);
4220 static const struct eth_dev_ops bnxt_dev_ops = {
4221 .dev_infos_get = bnxt_dev_info_get_op,
4222 .dev_close = bnxt_dev_close_op,
4223 .dev_configure = bnxt_dev_configure_op,
4224 .dev_start = bnxt_dev_start_op,
4225 .dev_stop = bnxt_dev_stop_op,
4226 .dev_set_link_up = bnxt_dev_set_link_up_op,
4227 .dev_set_link_down = bnxt_dev_set_link_down_op,
4228 .stats_get = bnxt_stats_get_op,
4229 .stats_reset = bnxt_stats_reset_op,
4230 .rx_queue_setup = bnxt_rx_queue_setup_op,
4231 .rx_queue_release = bnxt_rx_queue_release_op,
4232 .tx_queue_setup = bnxt_tx_queue_setup_op,
4233 .tx_queue_release = bnxt_tx_queue_release_op,
4234 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4235 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4236 .reta_update = bnxt_reta_update_op,
4237 .reta_query = bnxt_reta_query_op,
4238 .rss_hash_update = bnxt_rss_hash_update_op,
4239 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4240 .link_update = bnxt_link_update_op,
4241 .promiscuous_enable = bnxt_promiscuous_enable_op,
4242 .promiscuous_disable = bnxt_promiscuous_disable_op,
4243 .allmulticast_enable = bnxt_allmulticast_enable_op,
4244 .allmulticast_disable = bnxt_allmulticast_disable_op,
4245 .mac_addr_add = bnxt_mac_addr_add_op,
4246 .mac_addr_remove = bnxt_mac_addr_remove_op,
4247 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4248 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4249 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
4250 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
4251 .vlan_filter_set = bnxt_vlan_filter_set_op,
4252 .vlan_offload_set = bnxt_vlan_offload_set_op,
4253 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4254 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4255 .mtu_set = bnxt_mtu_set_op,
4256 .mac_addr_set = bnxt_set_default_mac_addr_op,
4257 .xstats_get = bnxt_dev_xstats_get_op,
4258 .xstats_get_names = bnxt_dev_xstats_get_names_op,
4259 .xstats_reset = bnxt_dev_xstats_reset_op,
4260 .fw_version_get = bnxt_fw_version_get,
4261 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4262 .rxq_info_get = bnxt_rxq_info_get_op,
4263 .txq_info_get = bnxt_txq_info_get_op,
4264 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4265 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4266 .dev_led_on = bnxt_dev_led_on_op,
4267 .dev_led_off = bnxt_dev_led_off_op,
4268 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4269 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4270 .rx_queue_start = bnxt_rx_queue_start,
4271 .rx_queue_stop = bnxt_rx_queue_stop,
4272 .tx_queue_start = bnxt_tx_queue_start,
4273 .tx_queue_stop = bnxt_tx_queue_stop,
4274 .filter_ctrl = bnxt_filter_ctrl_op,
4275 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4276 .get_eeprom_length = bnxt_get_eeprom_length_op,
4277 .get_eeprom = bnxt_get_eeprom_op,
4278 .set_eeprom = bnxt_set_eeprom_op,
4279 .timesync_enable = bnxt_timesync_enable,
4280 .timesync_disable = bnxt_timesync_disable,
4281 .timesync_read_time = bnxt_timesync_read_time,
4282 .timesync_write_time = bnxt_timesync_write_time,
4283 .timesync_adjust_time = bnxt_timesync_adjust_time,
4284 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4285 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4288 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4292 /* Only pre-map the reset GRC registers using window 3 */
4293 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4294 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4296 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4301 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4303 struct bnxt_error_recovery_info *info = bp->recovery_info;
4304 uint32_t reg_base = 0xffffffff;
4307 /* Only pre-map the monitoring GRC registers using window 2 */
4308 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4309 uint32_t reg = info->status_regs[i];
4311 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4314 if (reg_base == 0xffffffff)
4315 reg_base = reg & 0xfffff000;
4316 if ((reg & 0xfffff000) != reg_base)
4319 /* Use mask 0xffc as the Lower 2 bits indicates
4320 * address space location
4322 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4326 if (reg_base == 0xffffffff)
4329 rte_write32(reg_base, (uint8_t *)bp->bar0 +
4330 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4335 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4337 struct bnxt_error_recovery_info *info = bp->recovery_info;
4338 uint32_t delay = info->delay_after_reset[index];
4339 uint32_t val = info->reset_reg_val[index];
4340 uint32_t reg = info->reset_reg[index];
4341 uint32_t type, offset;
4343 type = BNXT_FW_STATUS_REG_TYPE(reg);
4344 offset = BNXT_FW_STATUS_REG_OFF(reg);
4347 case BNXT_FW_STATUS_REG_TYPE_CFG:
4348 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4350 case BNXT_FW_STATUS_REG_TYPE_GRC:
4351 offset = bnxt_map_reset_regs(bp, offset);
4352 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4354 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4355 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4358 /* wait on a specific interval of time until core reset is complete */
4360 rte_delay_ms(delay);
4363 static void bnxt_dev_cleanup(struct bnxt *bp)
4365 bnxt_set_hwrm_link_config(bp, false);
4366 bp->link_info->link_up = 0;
4367 if (bp->eth_dev->data->dev_started)
4368 bnxt_dev_stop_op(bp->eth_dev);
4370 bnxt_uninit_resources(bp, true);
4373 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4375 struct rte_eth_dev *dev = bp->eth_dev;
4376 struct rte_vlan_filter_conf *vfc;
4380 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4381 vfc = &dev->data->vlan_filter_conf;
4382 vidx = vlan_id / 64;
4383 vbit = vlan_id % 64;
4385 /* Each bit corresponds to a VLAN id */
4386 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4387 rc = bnxt_add_vlan_filter(bp, vlan_id);
4396 static int bnxt_restore_mac_filters(struct bnxt *bp)
4398 struct rte_eth_dev *dev = bp->eth_dev;
4399 struct rte_eth_dev_info dev_info;
4400 struct rte_ether_addr *addr;
4406 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4409 rc = bnxt_dev_info_get_op(dev, &dev_info);
4413 /* replay MAC address configuration */
4414 for (i = 1; i < dev_info.max_mac_addrs; i++) {
4415 addr = &dev->data->mac_addrs[i];
4417 /* skip zero address */
4418 if (rte_is_zero_ether_addr(addr))
4422 pool_mask = dev->data->mac_pool_sel[i];
4425 if (pool_mask & 1ULL) {
4426 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4432 } while (pool_mask);
4438 static int bnxt_restore_filters(struct bnxt *bp)
4440 struct rte_eth_dev *dev = bp->eth_dev;
4443 if (dev->data->all_multicast) {
4444 ret = bnxt_allmulticast_enable_op(dev);
4448 if (dev->data->promiscuous) {
4449 ret = bnxt_promiscuous_enable_op(dev);
4454 ret = bnxt_restore_mac_filters(bp);
4458 ret = bnxt_restore_vlan_filters(bp);
4459 /* TODO restore other filters as well */
4463 static void bnxt_dev_recover(void *arg)
4465 struct bnxt *bp = arg;
4466 int timeout = bp->fw_reset_max_msecs;
4469 /* Clear Error flag so that device re-init should happen */
4470 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4473 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4476 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4477 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4478 } while (rc && timeout);
4481 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4485 rc = bnxt_init_resources(bp, true);
4488 "Failed to initialize resources after reset\n");
4491 /* clear reset flag as the device is initialized now */
4492 bp->flags &= ~BNXT_FLAG_FW_RESET;
4494 rc = bnxt_dev_start_op(bp->eth_dev);
4496 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4500 rc = bnxt_restore_filters(bp);
4504 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4507 bnxt_dev_stop_op(bp->eth_dev);
4509 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4510 bnxt_uninit_resources(bp, false);
4511 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4514 void bnxt_dev_reset_and_resume(void *arg)
4516 struct bnxt *bp = arg;
4519 bnxt_dev_cleanup(bp);
4521 bnxt_wait_for_device_shutdown(bp);
4523 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4524 bnxt_dev_recover, (void *)bp);
4526 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4529 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4531 struct bnxt_error_recovery_info *info = bp->recovery_info;
4532 uint32_t reg = info->status_regs[index];
4533 uint32_t type, offset, val = 0;
4535 type = BNXT_FW_STATUS_REG_TYPE(reg);
4536 offset = BNXT_FW_STATUS_REG_OFF(reg);
4539 case BNXT_FW_STATUS_REG_TYPE_CFG:
4540 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4542 case BNXT_FW_STATUS_REG_TYPE_GRC:
4543 offset = info->mapped_status_regs[index];
4545 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4546 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4554 static int bnxt_fw_reset_all(struct bnxt *bp)
4556 struct bnxt_error_recovery_info *info = bp->recovery_info;
4560 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4561 /* Reset through master function driver */
4562 for (i = 0; i < info->reg_array_cnt; i++)
4563 bnxt_write_fw_reset_reg(bp, i);
4564 /* Wait for time specified by FW after triggering reset */
4565 rte_delay_ms(info->master_func_wait_period_after_reset);
4566 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4567 /* Reset with the help of Kong processor */
4568 rc = bnxt_hwrm_fw_reset(bp);
4570 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4576 static void bnxt_fw_reset_cb(void *arg)
4578 struct bnxt *bp = arg;
4579 struct bnxt_error_recovery_info *info = bp->recovery_info;
4582 /* Only Master function can do FW reset */
4583 if (bnxt_is_master_func(bp) &&
4584 bnxt_is_recovery_enabled(bp)) {
4585 rc = bnxt_fw_reset_all(bp);
4587 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4592 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4593 * EXCEPTION_FATAL_ASYNC event to all the functions
4594 * (including MASTER FUNC). After receiving this Async, all the active
4595 * drivers should treat this case as FW initiated recovery
4597 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4598 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4599 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4601 /* To recover from error */
4602 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4607 /* Driver should poll FW heartbeat, reset_counter with the frequency
4608 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4609 * When the driver detects heartbeat stop or change in reset_counter,
4610 * it has to trigger a reset to recover from the error condition.
4611 * A “master PF” is the function who will have the privilege to
4612 * initiate the chimp reset. The master PF will be elected by the
4613 * firmware and will be notified through async message.
4615 static void bnxt_check_fw_health(void *arg)
4617 struct bnxt *bp = arg;
4618 struct bnxt_error_recovery_info *info = bp->recovery_info;
4619 uint32_t val = 0, wait_msec;
4621 if (!info || !bnxt_is_recovery_enabled(bp) ||
4622 is_bnxt_in_error(bp))
4625 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4626 if (val == info->last_heart_beat)
4629 info->last_heart_beat = val;
4631 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4632 if (val != info->last_reset_counter)
4635 info->last_reset_counter = val;
4637 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4638 bnxt_check_fw_health, (void *)bp);
4642 /* Stop DMA to/from device */
4643 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4644 bp->flags |= BNXT_FLAG_FW_RESET;
4646 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4648 if (bnxt_is_master_func(bp))
4649 wait_msec = info->master_func_wait_period;
4651 wait_msec = info->normal_func_wait_period;
4653 rte_eal_alarm_set(US_PER_MS * wait_msec,
4654 bnxt_fw_reset_cb, (void *)bp);
4657 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4659 uint32_t polling_freq;
4661 if (!bnxt_is_recovery_enabled(bp))
4664 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4667 polling_freq = bp->recovery_info->driver_polling_freq;
4669 rte_eal_alarm_set(US_PER_MS * polling_freq,
4670 bnxt_check_fw_health, (void *)bp);
4671 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4674 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4676 if (!bnxt_is_recovery_enabled(bp))
4679 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4680 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4683 static bool bnxt_vf_pciid(uint16_t device_id)
4685 switch (device_id) {
4686 case BROADCOM_DEV_ID_57304_VF:
4687 case BROADCOM_DEV_ID_57406_VF:
4688 case BROADCOM_DEV_ID_5731X_VF:
4689 case BROADCOM_DEV_ID_5741X_VF:
4690 case BROADCOM_DEV_ID_57414_VF:
4691 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4692 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4693 case BROADCOM_DEV_ID_58802_VF:
4694 case BROADCOM_DEV_ID_57500_VF1:
4695 case BROADCOM_DEV_ID_57500_VF2:
4703 static bool bnxt_thor_device(uint16_t device_id)
4705 switch (device_id) {
4706 case BROADCOM_DEV_ID_57508:
4707 case BROADCOM_DEV_ID_57504:
4708 case BROADCOM_DEV_ID_57502:
4709 case BROADCOM_DEV_ID_57508_MF1:
4710 case BROADCOM_DEV_ID_57504_MF1:
4711 case BROADCOM_DEV_ID_57502_MF1:
4712 case BROADCOM_DEV_ID_57508_MF2:
4713 case BROADCOM_DEV_ID_57504_MF2:
4714 case BROADCOM_DEV_ID_57502_MF2:
4715 case BROADCOM_DEV_ID_57500_VF1:
4716 case BROADCOM_DEV_ID_57500_VF2:
4724 bool bnxt_stratus_device(struct bnxt *bp)
4726 uint16_t device_id = bp->pdev->id.device_id;
4728 switch (device_id) {
4729 case BROADCOM_DEV_ID_STRATUS_NIC:
4730 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4731 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4739 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4741 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4742 struct bnxt *bp = eth_dev->data->dev_private;
4744 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4745 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4746 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4747 if (!bp->bar0 || !bp->doorbell_base) {
4748 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4752 bp->eth_dev = eth_dev;
4758 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4759 struct bnxt_ctx_pg_info *ctx_pg,
4764 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4765 const struct rte_memzone *mz = NULL;
4766 char mz_name[RTE_MEMZONE_NAMESIZE];
4767 rte_iova_t mz_phys_addr;
4768 uint64_t valid_bits = 0;
4775 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4777 rmem->page_size = BNXT_PAGE_SIZE;
4778 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4779 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4780 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4782 valid_bits = PTU_PTE_VALID;
4784 if (rmem->nr_pages > 1) {
4785 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4786 "bnxt_ctx_pg_tbl%s_%x_%d",
4787 suffix, idx, bp->eth_dev->data->port_id);
4788 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4789 mz = rte_memzone_lookup(mz_name);
4791 mz = rte_memzone_reserve_aligned(mz_name,
4795 RTE_MEMZONE_SIZE_HINT_ONLY |
4796 RTE_MEMZONE_IOVA_CONTIG,
4802 memset(mz->addr, 0, mz->len);
4803 mz_phys_addr = mz->iova;
4805 rmem->pg_tbl = mz->addr;
4806 rmem->pg_tbl_map = mz_phys_addr;
4807 rmem->pg_tbl_mz = mz;
4810 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4811 suffix, idx, bp->eth_dev->data->port_id);
4812 mz = rte_memzone_lookup(mz_name);
4814 mz = rte_memzone_reserve_aligned(mz_name,
4818 RTE_MEMZONE_SIZE_HINT_ONLY |
4819 RTE_MEMZONE_IOVA_CONTIG,
4825 memset(mz->addr, 0, mz->len);
4826 mz_phys_addr = mz->iova;
4828 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4829 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4830 rmem->dma_arr[i] = mz_phys_addr + sz;
4832 if (rmem->nr_pages > 1) {
4833 if (i == rmem->nr_pages - 2 &&
4834 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4835 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4836 else if (i == rmem->nr_pages - 1 &&
4837 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4838 valid_bits |= PTU_PTE_LAST;
4840 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4846 if (rmem->vmem_size)
4847 rmem->vmem = (void **)mz->addr;
4848 rmem->dma_arr[0] = mz_phys_addr;
4852 static void bnxt_free_ctx_mem(struct bnxt *bp)
4856 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4859 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4860 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4861 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4862 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4863 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4864 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4865 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4866 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4867 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4868 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4869 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4871 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4872 if (bp->ctx->tqm_mem[i])
4873 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4880 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4882 #define min_t(type, x, y) ({ \
4883 type __min1 = (x); \
4884 type __min2 = (y); \
4885 __min1 < __min2 ? __min1 : __min2; })
4887 #define max_t(type, x, y) ({ \
4888 type __max1 = (x); \
4889 type __max2 = (y); \
4890 __max1 > __max2 ? __max1 : __max2; })
4892 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4894 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4896 struct bnxt_ctx_pg_info *ctx_pg;
4897 struct bnxt_ctx_mem_info *ctx;
4898 uint32_t mem_size, ena, entries;
4899 uint32_t entries_sp, min;
4902 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4904 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4908 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4911 ctx_pg = &ctx->qp_mem;
4912 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4913 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4914 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4918 ctx_pg = &ctx->srq_mem;
4919 ctx_pg->entries = ctx->srq_max_l2_entries;
4920 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4921 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4925 ctx_pg = &ctx->cq_mem;
4926 ctx_pg->entries = ctx->cq_max_l2_entries;
4927 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4928 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4932 ctx_pg = &ctx->vnic_mem;
4933 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4934 ctx->vnic_max_ring_table_entries;
4935 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4936 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4940 ctx_pg = &ctx->stat_mem;
4941 ctx_pg->entries = ctx->stat_max_entries;
4942 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4943 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4947 min = ctx->tqm_min_entries_per_ring;
4949 entries_sp = ctx->qp_max_l2_entries +
4950 ctx->vnic_max_vnic_entries +
4951 2 * ctx->qp_min_qp1_entries + min;
4952 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4954 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4955 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4956 entries = clamp_t(uint32_t, entries, min,
4957 ctx->tqm_max_entries_per_ring);
4958 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4959 ctx_pg = ctx->tqm_mem[i];
4960 ctx_pg->entries = i ? entries : entries_sp;
4961 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4962 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4965 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4968 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4969 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4972 "Failed to configure context mem: rc = %d\n", rc);
4974 ctx->flags |= BNXT_CTX_FLAG_INITED;
4979 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4981 struct rte_pci_device *pci_dev = bp->pdev;
4982 char mz_name[RTE_MEMZONE_NAMESIZE];
4983 const struct rte_memzone *mz = NULL;
4984 uint32_t total_alloc_len;
4985 rte_iova_t mz_phys_addr;
4987 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4990 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4991 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4992 pci_dev->addr.bus, pci_dev->addr.devid,
4993 pci_dev->addr.function, "rx_port_stats");
4994 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4995 mz = rte_memzone_lookup(mz_name);
4997 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4998 sizeof(struct rx_port_stats_ext) + 512);
5000 mz = rte_memzone_reserve(mz_name, total_alloc_len,
5003 RTE_MEMZONE_SIZE_HINT_ONLY |
5004 RTE_MEMZONE_IOVA_CONTIG);
5008 memset(mz->addr, 0, mz->len);
5009 mz_phys_addr = mz->iova;
5011 bp->rx_mem_zone = (const void *)mz;
5012 bp->hw_rx_port_stats = mz->addr;
5013 bp->hw_rx_port_stats_map = mz_phys_addr;
5015 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5016 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5017 pci_dev->addr.bus, pci_dev->addr.devid,
5018 pci_dev->addr.function, "tx_port_stats");
5019 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5020 mz = rte_memzone_lookup(mz_name);
5022 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
5023 sizeof(struct tx_port_stats_ext) + 512);
5025 mz = rte_memzone_reserve(mz_name,
5029 RTE_MEMZONE_SIZE_HINT_ONLY |
5030 RTE_MEMZONE_IOVA_CONTIG);
5034 memset(mz->addr, 0, mz->len);
5035 mz_phys_addr = mz->iova;
5037 bp->tx_mem_zone = (const void *)mz;
5038 bp->hw_tx_port_stats = mz->addr;
5039 bp->hw_tx_port_stats_map = mz_phys_addr;
5040 bp->flags |= BNXT_FLAG_PORT_STATS;
5042 /* Display extended statistics if FW supports it */
5043 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5044 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5045 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5048 bp->hw_rx_port_stats_ext = (void *)
5049 ((uint8_t *)bp->hw_rx_port_stats +
5050 sizeof(struct rx_port_stats));
5051 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5052 sizeof(struct rx_port_stats);
5053 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5055 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5056 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5057 bp->hw_tx_port_stats_ext = (void *)
5058 ((uint8_t *)bp->hw_tx_port_stats +
5059 sizeof(struct tx_port_stats));
5060 bp->hw_tx_port_stats_ext_map =
5061 bp->hw_tx_port_stats_map +
5062 sizeof(struct tx_port_stats);
5063 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5069 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5071 struct bnxt *bp = eth_dev->data->dev_private;
5074 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5075 RTE_ETHER_ADDR_LEN *
5078 if (eth_dev->data->mac_addrs == NULL) {
5079 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5083 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5087 /* Generate a random MAC address, if none was assigned by PF */
5088 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5089 bnxt_eth_hw_addr_random(bp->mac_addr);
5091 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5092 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5093 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5095 rc = bnxt_hwrm_set_mac(bp);
5100 /* Copy the permanent MAC from the FUNC_QCAPS response */
5101 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5106 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5110 /* MAC is already configured in FW */
5111 if (BNXT_HAS_DFLT_MAC_SET(bp))
5114 /* Restore the old MAC configured */
5115 rc = bnxt_hwrm_set_mac(bp);
5117 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5122 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5127 #define ALLOW_FUNC(x) \
5129 uint32_t arg = (x); \
5130 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5131 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5134 /* Forward all requests if firmware is new enough */
5135 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5136 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5137 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5138 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5140 PMD_DRV_LOG(WARNING,
5141 "Firmware too old for VF mailbox functionality\n");
5142 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5146 * The following are used for driver cleanup. If we disallow these,
5147 * VF drivers can't clean up cleanly.
5149 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5150 ALLOW_FUNC(HWRM_VNIC_FREE);
5151 ALLOW_FUNC(HWRM_RING_FREE);
5152 ALLOW_FUNC(HWRM_RING_GRP_FREE);
5153 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5154 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5155 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5156 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5157 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5161 bnxt_get_svif(uint16_t port_id, bool func_svif,
5162 enum bnxt_ulp_intf_type type)
5164 struct rte_eth_dev *eth_dev;
5167 eth_dev = &rte_eth_devices[port_id];
5168 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5169 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5173 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5176 eth_dev = vfr->parent_dev;
5179 bp = eth_dev->data->dev_private;
5181 return func_svif ? bp->func_svif : bp->port_svif;
5185 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5187 struct rte_eth_dev *eth_dev;
5188 struct bnxt_vnic_info *vnic;
5191 eth_dev = &rte_eth_devices[port];
5192 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5193 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5197 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5198 return vfr->dflt_vnic_id;
5200 eth_dev = vfr->parent_dev;
5203 bp = eth_dev->data->dev_private;
5205 vnic = BNXT_GET_DEFAULT_VNIC(bp);
5207 return vnic->fw_vnic_id;
5211 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5213 struct rte_eth_dev *eth_dev;
5216 eth_dev = &rte_eth_devices[port];
5217 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5218 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5222 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5225 eth_dev = vfr->parent_dev;
5228 bp = eth_dev->data->dev_private;
5233 enum bnxt_ulp_intf_type
5234 bnxt_get_interface_type(uint16_t port)
5236 struct rte_eth_dev *eth_dev;
5239 eth_dev = &rte_eth_devices[port];
5240 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5241 return BNXT_ULP_INTF_TYPE_VF_REP;
5243 bp = eth_dev->data->dev_private;
5245 return BNXT_ULP_INTF_TYPE_PF;
5246 else if (BNXT_VF_IS_TRUSTED(bp))
5247 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5248 else if (BNXT_VF(bp))
5249 return BNXT_ULP_INTF_TYPE_VF;
5251 return BNXT_ULP_INTF_TYPE_INVALID;
5255 bnxt_get_phy_port_id(uint16_t port_id)
5257 struct bnxt_vf_representor *vfr;
5258 struct rte_eth_dev *eth_dev;
5261 eth_dev = &rte_eth_devices[port_id];
5262 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5263 vfr = eth_dev->data->dev_private;
5267 eth_dev = vfr->parent_dev;
5270 bp = eth_dev->data->dev_private;
5272 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5276 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5278 struct rte_eth_dev *eth_dev;
5281 eth_dev = &rte_eth_devices[port_id];
5282 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5283 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5287 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5288 return vfr->fw_fid - 1;
5290 eth_dev = vfr->parent_dev;
5293 bp = eth_dev->data->dev_private;
5295 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5299 bnxt_get_vport(uint16_t port_id)
5301 return (1 << bnxt_get_phy_port_id(port_id));
5304 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5306 struct bnxt_error_recovery_info *info = bp->recovery_info;
5309 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5310 memset(info, 0, sizeof(*info));
5314 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5317 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5320 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5322 bp->recovery_info = info;
5325 static void bnxt_check_fw_status(struct bnxt *bp)
5329 if (!(bp->recovery_info &&
5330 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5333 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5334 if (fw_status != BNXT_FW_STATUS_HEALTHY)
5335 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5339 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5341 struct bnxt_error_recovery_info *info = bp->recovery_info;
5342 uint32_t status_loc;
5345 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5346 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5347 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5348 BNXT_GRCP_WINDOW_2_BASE +
5349 offsetof(struct hcomm_status,
5351 /* If the signature is absent, then FW does not support this feature */
5352 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5353 HCOMM_STATUS_SIGNATURE_VAL)
5357 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5361 bp->recovery_info = info;
5363 memset(info, 0, sizeof(*info));
5366 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5367 BNXT_GRCP_WINDOW_2_BASE +
5368 offsetof(struct hcomm_status,
5371 /* Only pre-map the FW health status GRC register */
5372 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5375 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5376 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5377 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5379 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5380 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5382 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5387 static int bnxt_init_fw(struct bnxt *bp)
5394 rc = bnxt_map_hcomm_fw_status_reg(bp);
5398 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5400 bnxt_check_fw_status(bp);
5404 rc = bnxt_hwrm_func_reset(bp);
5408 rc = bnxt_hwrm_vnic_qcaps(bp);
5412 rc = bnxt_hwrm_queue_qportcfg(bp);
5416 /* Get the MAX capabilities for this function.
5417 * This function also allocates context memory for TQM rings and
5418 * informs the firmware about this allocated backing store memory.
5420 rc = bnxt_hwrm_func_qcaps(bp);
5424 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5428 bnxt_hwrm_port_mac_qcfg(bp);
5430 bnxt_hwrm_parent_pf_qcfg(bp);
5432 bnxt_hwrm_port_phy_qcaps(bp);
5434 bnxt_alloc_error_recovery_info(bp);
5435 /* Get the adapter error recovery support info */
5436 rc = bnxt_hwrm_error_recovery_qcfg(bp);
5438 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5440 bnxt_hwrm_port_led_qcaps(bp);
5446 bnxt_init_locks(struct bnxt *bp)
5450 err = pthread_mutex_init(&bp->flow_lock, NULL);
5452 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5456 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5458 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5462 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5466 rc = bnxt_init_fw(bp);
5470 if (!reconfig_dev) {
5471 rc = bnxt_setup_mac_addr(bp->eth_dev);
5475 rc = bnxt_restore_dflt_mac(bp);
5480 bnxt_config_vf_req_fwd(bp);
5482 rc = bnxt_hwrm_func_driver_register(bp);
5484 PMD_DRV_LOG(ERR, "Failed to register driver");
5489 if (bp->pdev->max_vfs) {
5490 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5492 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5496 rc = bnxt_hwrm_allocate_pf_only(bp);
5499 "Failed to allocate PF resources");
5505 rc = bnxt_alloc_mem(bp, reconfig_dev);
5509 rc = bnxt_setup_int(bp);
5513 rc = bnxt_request_int(bp);
5517 rc = bnxt_init_ctx_mem(bp);
5519 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5523 rc = bnxt_init_locks(bp);
5531 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5532 const char *value, void *opaque_arg)
5534 struct bnxt *bp = opaque_arg;
5535 unsigned long truflow;
5538 if (!value || !opaque_arg) {
5540 "Invalid parameter passed to truflow devargs.\n");
5544 truflow = strtoul(value, &end, 10);
5545 if (end == NULL || *end != '\0' ||
5546 (truflow == ULONG_MAX && errno == ERANGE)) {
5548 "Invalid parameter passed to truflow devargs.\n");
5552 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5554 "Invalid value passed to truflow devargs.\n");
5558 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5559 if (BNXT_TRUFLOW_EN(bp))
5560 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5566 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5567 const char *value, void *opaque_arg)
5569 struct bnxt *bp = opaque_arg;
5570 unsigned long flow_xstat;
5573 if (!value || !opaque_arg) {
5575 "Invalid parameter passed to flow_xstat devarg.\n");
5579 flow_xstat = strtoul(value, &end, 10);
5580 if (end == NULL || *end != '\0' ||
5581 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5583 "Invalid parameter passed to flow_xstat devarg.\n");
5587 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5589 "Invalid value passed to flow_xstat devarg.\n");
5593 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5594 if (BNXT_FLOW_XSTATS_EN(bp))
5595 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5601 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5602 const char *value, void *opaque_arg)
5604 struct bnxt *bp = opaque_arg;
5605 unsigned long max_num_kflows;
5608 if (!value || !opaque_arg) {
5610 "Invalid parameter passed to max_num_kflows devarg.\n");
5614 max_num_kflows = strtoul(value, &end, 10);
5615 if (end == NULL || *end != '\0' ||
5616 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5618 "Invalid parameter passed to max_num_kflows devarg.\n");
5622 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5624 "Invalid value passed to max_num_kflows devarg.\n");
5628 bp->max_num_kflows = max_num_kflows;
5629 if (bp->max_num_kflows)
5630 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5637 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5639 struct rte_kvargs *kvlist;
5641 if (devargs == NULL)
5644 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5649 * Handler for "truflow" devarg.
5650 * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5652 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5653 bnxt_parse_devarg_truflow, bp);
5656 * Handler for "flow_xstat" devarg.
5657 * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5659 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5660 bnxt_parse_devarg_flow_xstat, bp);
5663 * Handler for "max_num_kflows" devarg.
5664 * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5666 rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5667 bnxt_parse_devarg_max_num_kflows, bp);
5669 rte_kvargs_free(kvlist);
5672 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5676 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5677 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5680 "Failed to alloc switch domain: %d\n", rc);
5683 "Switch domain allocated %d\n",
5684 bp->switch_domain_id);
5691 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5693 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5694 static int version_printed;
5698 if (version_printed++ == 0)
5699 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5701 eth_dev->dev_ops = &bnxt_dev_ops;
5702 eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5703 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5704 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5705 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5706 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5709 * For secondary processes, we don't initialise any further
5710 * as primary has already done this work.
5712 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5715 rte_eth_copy_pci_info(eth_dev, pci_dev);
5717 bp = eth_dev->data->dev_private;
5719 /* Parse dev arguments passed on when starting the DPDK application. */
5720 bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5722 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5724 if (bnxt_vf_pciid(pci_dev->id.device_id))
5725 bp->flags |= BNXT_FLAG_VF;
5727 if (bnxt_thor_device(pci_dev->id.device_id))
5728 bp->flags |= BNXT_FLAG_THOR_CHIP;
5730 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5731 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5732 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5733 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5734 bp->flags |= BNXT_FLAG_STINGRAY;
5736 rc = bnxt_init_board(eth_dev);
5739 "Failed to initialize board rc: %x\n", rc);
5743 rc = bnxt_alloc_pf_info(bp);
5747 rc = bnxt_alloc_link_info(bp);
5751 rc = bnxt_alloc_parent_info(bp);
5755 rc = bnxt_alloc_hwrm_resources(bp);
5758 "Failed to allocate hwrm resource rc: %x\n", rc);
5761 rc = bnxt_alloc_leds_info(bp);
5765 rc = bnxt_alloc_cos_queues(bp);
5769 rc = bnxt_init_resources(bp, false);
5773 rc = bnxt_alloc_stats_mem(bp);
5777 bnxt_alloc_switch_domain(bp);
5779 /* Pass the information to the rte_eth_dev_close() that it should also
5780 * release the private port resources.
5782 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5785 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5786 pci_dev->mem_resource[0].phys_addr,
5787 pci_dev->mem_resource[0].addr);
5792 bnxt_dev_uninit(eth_dev);
5797 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5806 ctx->dma = RTE_BAD_IOVA;
5807 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5810 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5812 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5813 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5814 bp->flow_stat->rx_fc_out_tbl.ctx_id,
5815 bp->flow_stat->max_fc,
5818 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5819 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5820 bp->flow_stat->tx_fc_out_tbl.ctx_id,
5821 bp->flow_stat->max_fc,
5824 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5825 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5826 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5828 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5829 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5830 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5832 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5833 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5834 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5836 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5837 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5838 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5841 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5843 bnxt_unregister_fc_ctx_mem(bp);
5845 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5846 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5847 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5848 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5851 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5853 if (BNXT_FLOW_XSTATS_EN(bp))
5854 bnxt_uninit_fc_ctx_mem(bp);
5858 bnxt_free_error_recovery_info(struct bnxt *bp)
5860 rte_free(bp->recovery_info);
5861 bp->recovery_info = NULL;
5862 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5866 bnxt_uninit_locks(struct bnxt *bp)
5868 pthread_mutex_destroy(&bp->flow_lock);
5869 pthread_mutex_destroy(&bp->def_cp_lock);
5871 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5872 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
5877 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5882 bnxt_free_mem(bp, reconfig_dev);
5883 bnxt_hwrm_func_buf_unrgtr(bp);
5884 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5885 bp->flags &= ~BNXT_FLAG_REGISTERED;
5886 bnxt_free_ctx_mem(bp);
5887 if (!reconfig_dev) {
5888 bnxt_free_hwrm_resources(bp);
5889 bnxt_free_error_recovery_info(bp);
5892 bnxt_uninit_ctx_mem(bp);
5894 bnxt_uninit_locks(bp);
5895 bnxt_free_flow_stats_info(bp);
5896 bnxt_free_rep_info(bp);
5897 rte_free(bp->ptp_cfg);
5903 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5905 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5908 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5910 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5911 bnxt_dev_close_op(eth_dev);
5916 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5918 struct bnxt *bp = eth_dev->data->dev_private;
5919 struct rte_eth_dev *vf_rep_eth_dev;
5925 for (i = 0; i < bp->num_reps; i++) {
5926 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5927 if (!vf_rep_eth_dev)
5929 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_vf_representor_uninit);
5931 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5936 static void bnxt_free_rep_info(struct bnxt *bp)
5938 rte_free(bp->rep_info);
5939 bp->rep_info = NULL;
5940 rte_free(bp->cfa_code_map);
5941 bp->cfa_code_map = NULL;
5944 static int bnxt_init_rep_info(struct bnxt *bp)
5951 bp->rep_info = rte_zmalloc("bnxt_rep_info",
5952 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5954 if (!bp->rep_info) {
5955 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5958 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5959 sizeof(*bp->cfa_code_map) *
5960 BNXT_MAX_CFA_CODE, 0);
5961 if (!bp->cfa_code_map) {
5962 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5963 bnxt_free_rep_info(bp);
5967 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5968 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5970 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5972 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5973 bnxt_free_rep_info(bp);
5977 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5979 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5980 bnxt_free_rep_info(bp);
5987 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5988 struct rte_eth_devargs eth_da,
5989 struct rte_eth_dev *backing_eth_dev)
5991 struct rte_eth_dev *vf_rep_eth_dev;
5992 char name[RTE_ETH_NAME_MAX_LEN];
5993 struct bnxt *backing_bp;
5997 num_rep = eth_da.nb_representor_ports;
5998 if (num_rep > BNXT_MAX_VF_REPS) {
5999 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6000 num_rep, BNXT_MAX_VF_REPS);
6004 if (num_rep > RTE_MAX_ETHPORTS) {
6006 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6007 num_rep, RTE_MAX_ETHPORTS);
6011 backing_bp = backing_eth_dev->data->dev_private;
6013 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6015 "Not a PF or trusted VF. No Representor support\n");
6016 /* Returning an error is not an option.
6017 * Applications are not handling this correctly
6022 if (bnxt_init_rep_info(backing_bp))
6025 for (i = 0; i < num_rep; i++) {
6026 struct bnxt_vf_representor representor = {
6027 .vf_id = eth_da.representor_ports[i],
6028 .switch_domain_id = backing_bp->switch_domain_id,
6029 .parent_dev = backing_eth_dev
6032 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6033 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6034 representor.vf_id, BNXT_MAX_VF_REPS);
6038 /* representor port net_bdf_port */
6039 snprintf(name, sizeof(name), "net_%s_representor_%d",
6040 pci_dev->device.name, eth_da.representor_ports[i]);
6042 ret = rte_eth_dev_create(&pci_dev->device, name,
6043 sizeof(struct bnxt_vf_representor),
6045 bnxt_vf_representor_init,
6049 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6050 if (!vf_rep_eth_dev) {
6051 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6052 " for VF-Rep: %s.", name);
6053 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6057 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6059 backing_bp->num_reps++;
6061 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6062 "representor %s.", name);
6063 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6070 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6071 struct rte_pci_device *pci_dev)
6073 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6074 struct rte_eth_dev *backing_eth_dev;
6078 if (pci_dev->device.devargs) {
6079 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6085 num_rep = eth_da.nb_representor_ports;
6086 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6089 /* We could come here after first level of probe is already invoked
6090 * as part of an application bringup(OVS-DPDK vswitchd), so first check
6091 * for already allocated eth_dev for the backing device (PF/Trusted VF)
6093 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6094 if (backing_eth_dev == NULL) {
6095 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6096 sizeof(struct bnxt),
6097 eth_dev_pci_specific_init, pci_dev,
6098 bnxt_dev_init, NULL);
6100 if (ret || !num_rep)
6103 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6106 /* probe representor ports now */
6107 ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev);
6112 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6114 struct rte_eth_dev *eth_dev;
6116 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6118 return 0; /* Invoked typically only by OVS-DPDK, by the
6119 * time it comes here the eth_dev is already
6120 * deleted by rte_eth_dev_close(), so returning
6121 * +ve value will at least help in proper cleanup
6124 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6125 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6126 return rte_eth_dev_destroy(eth_dev,
6127 bnxt_vf_representor_uninit);
6129 return rte_eth_dev_destroy(eth_dev,
6132 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6136 static struct rte_pci_driver bnxt_rte_pmd = {
6137 .id_table = bnxt_pci_id_map,
6138 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6139 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6142 .probe = bnxt_pci_probe,
6143 .remove = bnxt_pci_remove,
6147 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6149 if (strcmp(dev->device->driver->name, drv->driver.name))
6155 bool is_bnxt_supported(struct rte_eth_dev *dev)
6157 return is_device_supported(dev, &bnxt_rte_pmd);
6160 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6161 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6162 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6163 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");