1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
29 #include "bnxt_util.h"
31 #define DRV_MODULE_NAME "bnxt"
32 static const char bnxt_version[] =
33 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
34 int bnxt_logtype_driver;
36 #define PCI_VENDOR_ID_BROADCOM 0x14E4
38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
41 #define BROADCOM_DEV_ID_57414_VF 0x16c1
42 #define BROADCOM_DEV_ID_57301 0x16c8
43 #define BROADCOM_DEV_ID_57302 0x16c9
44 #define BROADCOM_DEV_ID_57304_PF 0x16ca
45 #define BROADCOM_DEV_ID_57304_VF 0x16cb
46 #define BROADCOM_DEV_ID_57417_MF 0x16cc
47 #define BROADCOM_DEV_ID_NS2 0x16cd
48 #define BROADCOM_DEV_ID_57311 0x16ce
49 #define BROADCOM_DEV_ID_57312 0x16cf
50 #define BROADCOM_DEV_ID_57402 0x16d0
51 #define BROADCOM_DEV_ID_57404 0x16d1
52 #define BROADCOM_DEV_ID_57406_PF 0x16d2
53 #define BROADCOM_DEV_ID_57406_VF 0x16d3
54 #define BROADCOM_DEV_ID_57402_MF 0x16d4
55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
56 #define BROADCOM_DEV_ID_57412 0x16d6
57 #define BROADCOM_DEV_ID_57414 0x16d7
58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
61 #define BROADCOM_DEV_ID_57412_MF 0x16de
62 #define BROADCOM_DEV_ID_57314 0x16df
63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
68 #define BROADCOM_DEV_ID_57404_MF 0x16e7
69 #define BROADCOM_DEV_ID_57406_MF 0x16e8
70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
71 #define BROADCOM_DEV_ID_57407_MF 0x16ea
72 #define BROADCOM_DEV_ID_57414_MF 0x16ec
73 #define BROADCOM_DEV_ID_57416_MF 0x16ee
74 #define BROADCOM_DEV_ID_57508 0x1750
75 #define BROADCOM_DEV_ID_57504 0x1751
76 #define BROADCOM_DEV_ID_57502 0x1752
77 #define BROADCOM_DEV_ID_57500_VF 0x1807
78 #define BROADCOM_DEV_ID_58802 0xd802
79 #define BROADCOM_DEV_ID_58804 0xd804
80 #define BROADCOM_DEV_ID_58808 0x16f0
81 #define BROADCOM_DEV_ID_58802_VF 0xd800
83 static const struct rte_pci_id bnxt_pci_id_map[] = {
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
85 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
87 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF) },
130 { .vendor_id = 0, /* sentinel */ },
133 #define BNXT_ETH_RSS_SUPPORT ( \
135 ETH_RSS_NONFRAG_IPV4_TCP | \
136 ETH_RSS_NONFRAG_IPV4_UDP | \
138 ETH_RSS_NONFRAG_IPV6_TCP | \
139 ETH_RSS_NONFRAG_IPV6_UDP)
141 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
142 DEV_TX_OFFLOAD_IPV4_CKSUM | \
143 DEV_TX_OFFLOAD_TCP_CKSUM | \
144 DEV_TX_OFFLOAD_UDP_CKSUM | \
145 DEV_TX_OFFLOAD_TCP_TSO | \
146 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
147 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
148 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
149 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
150 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
151 DEV_TX_OFFLOAD_MULTI_SEGS)
153 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
154 DEV_RX_OFFLOAD_VLAN_STRIP | \
155 DEV_RX_OFFLOAD_IPV4_CKSUM | \
156 DEV_RX_OFFLOAD_UDP_CKSUM | \
157 DEV_RX_OFFLOAD_TCP_CKSUM | \
158 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
159 DEV_RX_OFFLOAD_JUMBO_FRAME | \
160 DEV_RX_OFFLOAD_KEEP_CRC | \
161 DEV_RX_OFFLOAD_TCP_LRO)
163 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
164 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
165 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
166 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
168 /***********************/
171 * High level utility functions
174 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
176 if (!BNXT_CHIP_THOR(bp))
179 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
180 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
181 BNXT_RSS_ENTRIES_PER_CTX_THOR;
184 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
186 if (!BNXT_CHIP_THOR(bp))
187 return HW_HASH_INDEX_SIZE;
189 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
192 static void bnxt_free_mem(struct bnxt *bp)
194 bnxt_free_filter_mem(bp);
195 bnxt_free_vnic_attributes(bp);
196 bnxt_free_vnic_mem(bp);
199 bnxt_free_tx_rings(bp);
200 bnxt_free_rx_rings(bp);
203 static int bnxt_alloc_mem(struct bnxt *bp)
207 rc = bnxt_alloc_vnic_mem(bp);
211 rc = bnxt_alloc_vnic_attributes(bp);
215 rc = bnxt_alloc_filter_mem(bp);
226 static int bnxt_init_chip(struct bnxt *bp)
228 struct bnxt_rx_queue *rxq;
229 struct rte_eth_link new;
230 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
231 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
232 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
233 uint64_t rx_offloads = dev_conf->rxmode.offloads;
234 uint32_t intr_vector = 0;
235 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
236 uint32_t vec = BNXT_MISC_VEC_ID;
240 /* disable uio/vfio intr/eventfd mapping */
241 rte_intr_disable(intr_handle);
243 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
244 bp->eth_dev->data->dev_conf.rxmode.offloads |=
245 DEV_RX_OFFLOAD_JUMBO_FRAME;
246 bp->flags |= BNXT_FLAG_JUMBO;
248 bp->eth_dev->data->dev_conf.rxmode.offloads &=
249 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
250 bp->flags &= ~BNXT_FLAG_JUMBO;
253 /* THOR does not support ring groups.
254 * But we will use the array to save RSS context IDs.
256 if (BNXT_CHIP_THOR(bp))
257 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
259 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
261 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
265 rc = bnxt_alloc_hwrm_rings(bp);
267 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
271 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
273 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
277 rc = bnxt_mq_rx_configure(bp);
279 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
283 /* VNIC configuration */
284 for (i = 0; i < bp->nr_vnics; i++) {
285 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
286 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
287 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
289 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
290 if (!vnic->fw_grp_ids) {
292 "Failed to alloc %d bytes for group ids\n",
297 memset(vnic->fw_grp_ids, -1, size);
299 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
300 i, vnic, vnic->fw_grp_ids);
302 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
304 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
309 /* Alloc RSS context only if RSS mode is enabled */
310 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
311 int j, nr_ctxs = bnxt_rss_ctxts(bp);
314 for (j = 0; j < nr_ctxs; j++) {
315 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
321 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
325 vnic->num_lb_ctxts = nr_ctxs;
329 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
330 * setting is not available at this time, it will not be
331 * configured correctly in the CFA.
333 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
334 vnic->vlan_strip = true;
336 vnic->vlan_strip = false;
338 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
340 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
345 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
348 "HWRM vnic %d filter failure rc: %x\n",
353 for (j = 0; j < bp->rx_nr_rings; j++) {
354 rxq = bp->eth_dev->data->rx_queues[j];
357 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
358 j, rxq->vnic, rxq->vnic->fw_grp_ids);
360 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
361 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
364 rc = bnxt_vnic_rss_configure(bp, vnic);
367 "HWRM vnic set RSS failure rc: %x\n", rc);
371 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
373 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
374 DEV_RX_OFFLOAD_TCP_LRO)
375 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
377 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
379 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
382 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
386 /* check and configure queue intr-vector mapping */
387 if ((rte_intr_cap_multiple(intr_handle) ||
388 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
389 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
390 intr_vector = bp->eth_dev->data->nb_rx_queues;
391 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
392 if (intr_vector > bp->rx_cp_nr_rings) {
393 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
397 rc = rte_intr_efd_enable(intr_handle, intr_vector);
402 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
403 intr_handle->intr_vec =
404 rte_zmalloc("intr_vec",
405 bp->eth_dev->data->nb_rx_queues *
407 if (intr_handle->intr_vec == NULL) {
408 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
409 " intr_vec", bp->eth_dev->data->nb_rx_queues);
413 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
414 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
415 intr_handle->intr_vec, intr_handle->nb_efd,
416 intr_handle->max_intr);
417 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
419 intr_handle->intr_vec[queue_id] = vec;
420 if (vec < base + intr_handle->nb_efd - 1)
425 /* enable uio/vfio intr/eventfd mapping */
426 rc = rte_intr_enable(intr_handle);
430 rc = bnxt_get_hwrm_link_config(bp, &new);
432 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
436 if (!bp->link_info.link_up) {
437 rc = bnxt_set_hwrm_link_config(bp, true);
440 "HWRM link config failure rc: %x\n", rc);
444 bnxt_print_link_info(bp->eth_dev);
449 rte_free(intr_handle->intr_vec);
451 rte_intr_efd_disable(intr_handle);
453 /* Some of the error status returned by FW may not be from errno.h */
460 static int bnxt_shutdown_nic(struct bnxt *bp)
462 bnxt_free_all_hwrm_resources(bp);
463 bnxt_free_all_filters(bp);
464 bnxt_free_all_vnics(bp);
468 static int bnxt_init_nic(struct bnxt *bp)
472 if (BNXT_HAS_RING_GRPS(bp)) {
473 rc = bnxt_init_ring_grps(bp);
479 bnxt_init_filters(bp);
485 * Device configuration and status function
488 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
489 struct rte_eth_dev_info *dev_info)
491 struct bnxt *bp = eth_dev->data->dev_private;
492 uint16_t max_vnics, i, j, vpool, vrxq;
493 unsigned int max_rx_rings;
496 dev_info->max_mac_addrs = bp->max_l2_ctx;
497 dev_info->max_hash_mac_addrs = 0;
499 /* PF/VF specifics */
501 dev_info->max_vfs = bp->pdev->max_vfs;
502 max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
503 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
504 dev_info->max_rx_queues = max_rx_rings;
505 dev_info->max_tx_queues = max_rx_rings;
506 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
507 dev_info->hash_key_size = 40;
508 max_vnics = bp->max_vnics;
510 /* Fast path specifics */
511 dev_info->min_rx_bufsize = 1;
512 dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
513 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
515 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
516 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
517 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
518 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
519 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
522 dev_info->default_rxconf = (struct rte_eth_rxconf) {
528 .rx_free_thresh = 32,
529 /* If no descriptors available, pkts are dropped by default */
533 dev_info->default_txconf = (struct rte_eth_txconf) {
539 .tx_free_thresh = 32,
542 eth_dev->data->dev_conf.intr_conf.lsc = 1;
544 eth_dev->data->dev_conf.intr_conf.rxq = 1;
545 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
546 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
547 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
548 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
553 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
554 * need further investigation.
558 vpool = 64; /* ETH_64_POOLS */
559 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
560 for (i = 0; i < 4; vpool >>= 1, i++) {
561 if (max_vnics > vpool) {
562 for (j = 0; j < 5; vrxq >>= 1, j++) {
563 if (dev_info->max_rx_queues > vrxq) {
569 /* Not enough resources to support VMDq */
573 /* Not enough resources to support VMDq */
577 dev_info->max_vmdq_pools = vpool;
578 dev_info->vmdq_queue_num = vrxq;
580 dev_info->vmdq_pool_base = 0;
581 dev_info->vmdq_queue_base = 0;
584 /* Configure the device based on the configuration provided */
585 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
587 struct bnxt *bp = eth_dev->data->dev_private;
588 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
591 bp->rx_queues = (void *)eth_dev->data->rx_queues;
592 bp->tx_queues = (void *)eth_dev->data->tx_queues;
593 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
594 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
596 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
597 rc = bnxt_hwrm_check_vf_rings(bp);
599 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
603 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
605 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
609 /* legacy driver needs to get updated values */
610 rc = bnxt_hwrm_func_qcaps(bp);
612 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
617 /* Inherit new configurations */
618 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
619 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
620 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
622 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
626 if (BNXT_HAS_RING_GRPS(bp) &&
627 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
630 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
631 bp->max_vnics < eth_dev->data->nb_rx_queues)
634 bp->rx_cp_nr_rings = bp->rx_nr_rings;
635 bp->tx_cp_nr_rings = bp->tx_nr_rings;
637 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
639 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
640 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
642 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
648 "Insufficient resources to support requested config\n");
650 "Num Queues Requested: Tx %d, Rx %d\n",
651 eth_dev->data->nb_tx_queues,
652 eth_dev->data->nb_rx_queues);
654 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
655 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
656 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
660 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
662 struct rte_eth_link *link = ð_dev->data->dev_link;
664 if (link->link_status)
665 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
666 eth_dev->data->port_id,
667 (uint32_t)link->link_speed,
668 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
669 ("full-duplex") : ("half-duplex\n"));
671 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
672 eth_dev->data->port_id);
676 * Determine whether the current configuration requires support for scattered
677 * receive; return 1 if scattered receive is required and 0 if not.
679 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
684 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
685 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
687 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
688 RTE_PKTMBUF_HEADROOM);
689 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
695 static eth_rx_burst_t
696 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
700 * Vector mode receive can be enabled only if scatter rx is not
701 * in use and rx offloads are limited to VLAN stripping and
704 if (!eth_dev->data->scattered_rx &&
705 !(eth_dev->data->dev_conf.rxmode.offloads &
706 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
707 DEV_RX_OFFLOAD_KEEP_CRC |
708 DEV_RX_OFFLOAD_JUMBO_FRAME |
709 DEV_RX_OFFLOAD_IPV4_CKSUM |
710 DEV_RX_OFFLOAD_UDP_CKSUM |
711 DEV_RX_OFFLOAD_TCP_CKSUM |
712 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
713 DEV_RX_OFFLOAD_VLAN_FILTER))) {
714 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
715 eth_dev->data->port_id);
716 return bnxt_recv_pkts_vec;
718 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
719 eth_dev->data->port_id);
721 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
722 eth_dev->data->port_id,
723 eth_dev->data->scattered_rx,
724 eth_dev->data->dev_conf.rxmode.offloads);
726 return bnxt_recv_pkts;
729 static eth_tx_burst_t
730 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
734 * Vector mode receive can be enabled only if scatter tx is not
735 * in use and tx offloads other than VLAN insertion are not
738 if (!eth_dev->data->scattered_rx &&
739 !(eth_dev->data->dev_conf.txmode.offloads &
740 ~DEV_TX_OFFLOAD_VLAN_INSERT)) {
741 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
742 eth_dev->data->port_id);
743 return bnxt_xmit_pkts_vec;
745 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
746 eth_dev->data->port_id);
748 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
749 eth_dev->data->port_id,
750 eth_dev->data->scattered_rx,
751 eth_dev->data->dev_conf.txmode.offloads);
753 return bnxt_xmit_pkts;
756 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
758 struct bnxt *bp = eth_dev->data->dev_private;
759 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
763 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
765 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
766 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
769 rc = bnxt_init_chip(bp);
773 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
775 bnxt_link_update_op(eth_dev, 1);
777 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
778 vlan_mask |= ETH_VLAN_FILTER_MASK;
779 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
780 vlan_mask |= ETH_VLAN_STRIP_MASK;
781 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
785 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
786 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
788 bp->flags |= BNXT_FLAG_INIT_DONE;
793 bnxt_shutdown_nic(bp);
794 bnxt_free_tx_mbufs(bp);
795 bnxt_free_rx_mbufs(bp);
799 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
801 struct bnxt *bp = eth_dev->data->dev_private;
804 if (!bp->link_info.link_up)
805 rc = bnxt_set_hwrm_link_config(bp, true);
807 eth_dev->data->dev_link.link_status = 1;
809 bnxt_print_link_info(eth_dev);
813 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
815 struct bnxt *bp = eth_dev->data->dev_private;
817 eth_dev->data->dev_link.link_status = 0;
818 bnxt_set_hwrm_link_config(bp, false);
819 bp->link_info.link_up = 0;
824 /* Unload the driver, release resources */
825 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
827 struct bnxt *bp = eth_dev->data->dev_private;
828 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
829 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
831 bnxt_disable_int(bp);
833 /* disable uio/vfio intr/eventfd mapping */
834 rte_intr_disable(intr_handle);
836 bp->flags &= ~BNXT_FLAG_INIT_DONE;
837 if (bp->eth_dev->data->dev_started) {
838 /* TBD: STOP HW queues DMA */
839 eth_dev->data->dev_link.link_status = 0;
841 bnxt_set_hwrm_link_config(bp, false);
843 /* Clean queue intr-vector mapping */
844 rte_intr_efd_disable(intr_handle);
845 if (intr_handle->intr_vec != NULL) {
846 rte_free(intr_handle->intr_vec);
847 intr_handle->intr_vec = NULL;
850 bnxt_hwrm_port_clr_stats(bp);
851 bnxt_free_tx_mbufs(bp);
852 bnxt_free_rx_mbufs(bp);
853 bnxt_shutdown_nic(bp);
857 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
859 struct bnxt *bp = eth_dev->data->dev_private;
861 if (bp->dev_stopped == 0)
862 bnxt_dev_stop_op(eth_dev);
864 if (eth_dev->data->mac_addrs != NULL) {
865 rte_free(eth_dev->data->mac_addrs);
866 eth_dev->data->mac_addrs = NULL;
868 if (bp->grp_info != NULL) {
869 rte_free(bp->grp_info);
873 bnxt_dev_uninit(eth_dev);
876 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
879 struct bnxt *bp = eth_dev->data->dev_private;
880 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
881 struct bnxt_vnic_info *vnic;
882 struct bnxt_filter_info *filter, *temp_filter;
886 * Loop through all VNICs from the specified filter flow pools to
887 * remove the corresponding MAC addr filter
889 for (i = 0; i < bp->nr_vnics; i++) {
890 if (!(pool_mask & (1ULL << i)))
893 vnic = &bp->vnic_info[i];
894 filter = STAILQ_FIRST(&vnic->filter);
896 temp_filter = STAILQ_NEXT(filter, next);
897 if (filter->mac_index == index) {
898 STAILQ_REMOVE(&vnic->filter, filter,
899 bnxt_filter_info, next);
900 bnxt_hwrm_clear_l2_filter(bp, filter);
901 filter->mac_index = INVALID_MAC_INDEX;
902 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
903 STAILQ_INSERT_TAIL(&bp->free_filter_list,
906 filter = temp_filter;
911 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
912 struct rte_ether_addr *mac_addr,
913 uint32_t index, uint32_t pool)
915 struct bnxt *bp = eth_dev->data->dev_private;
916 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
917 struct bnxt_filter_info *filter;
920 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
921 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
926 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
929 /* Attach requested MAC address to the new l2_filter */
930 STAILQ_FOREACH(filter, &vnic->filter, next) {
931 if (filter->mac_index == index) {
933 "MAC addr already existed for pool %d\n", pool);
937 filter = bnxt_alloc_filter(bp);
939 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
943 filter->mac_index = index;
944 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
946 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
948 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
950 filter->mac_index = INVALID_MAC_INDEX;
951 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
952 bnxt_free_filter(bp, filter);
958 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
961 struct bnxt *bp = eth_dev->data->dev_private;
962 struct rte_eth_link new;
963 unsigned int cnt = BNXT_LINK_WAIT_CNT;
965 memset(&new, 0, sizeof(new));
967 /* Retrieve link info from hardware */
968 rc = bnxt_get_hwrm_link_config(bp, &new);
970 new.link_speed = ETH_LINK_SPEED_100M;
971 new.link_duplex = ETH_LINK_FULL_DUPLEX;
973 "Failed to retrieve link rc = 0x%x!\n", rc);
976 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
978 if (!wait_to_complete)
980 } while (!new.link_status && cnt--);
983 /* Timed out or success */
984 if (new.link_status != eth_dev->data->dev_link.link_status ||
985 new.link_speed != eth_dev->data->dev_link.link_speed) {
986 memcpy(ð_dev->data->dev_link, &new,
987 sizeof(struct rte_eth_link));
989 _rte_eth_dev_callback_process(eth_dev,
990 RTE_ETH_EVENT_INTR_LSC,
993 bnxt_print_link_info(eth_dev);
999 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1001 struct bnxt *bp = eth_dev->data->dev_private;
1002 struct bnxt_vnic_info *vnic;
1004 if (bp->vnic_info == NULL)
1007 vnic = &bp->vnic_info[0];
1009 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1010 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1013 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1015 struct bnxt *bp = eth_dev->data->dev_private;
1016 struct bnxt_vnic_info *vnic;
1018 if (bp->vnic_info == NULL)
1021 vnic = &bp->vnic_info[0];
1023 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1024 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1027 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1029 struct bnxt *bp = eth_dev->data->dev_private;
1030 struct bnxt_vnic_info *vnic;
1032 if (bp->vnic_info == NULL)
1035 vnic = &bp->vnic_info[0];
1037 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1038 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1041 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1043 struct bnxt *bp = eth_dev->data->dev_private;
1044 struct bnxt_vnic_info *vnic;
1046 if (bp->vnic_info == NULL)
1049 vnic = &bp->vnic_info[0];
1051 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1052 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1055 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1056 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1058 if (qid >= bp->rx_nr_rings)
1061 return bp->eth_dev->data->rx_queues[qid];
1064 /* Return rxq corresponding to a given rss table ring/group ID. */
1065 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1067 struct bnxt_rx_queue *rxq;
1070 if (!BNXT_HAS_RING_GRPS(bp)) {
1071 for (i = 0; i < bp->rx_nr_rings; i++) {
1072 rxq = bp->eth_dev->data->rx_queues[i];
1073 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1077 for (i = 0; i < bp->rx_nr_rings; i++) {
1078 if (bp->grp_info[i].fw_grp_id == fwr)
1083 return INVALID_HW_RING_ID;
1086 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1087 struct rte_eth_rss_reta_entry64 *reta_conf,
1090 struct bnxt *bp = eth_dev->data->dev_private;
1091 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1092 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1093 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1097 if (!vnic->rss_table)
1100 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1103 if (reta_size != tbl_size) {
1104 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1105 "(%d) must equal the size supported by the hardware "
1106 "(%d)\n", reta_size, tbl_size);
1110 for (i = 0; i < reta_size; i++) {
1111 struct bnxt_rx_queue *rxq;
1113 idx = i / RTE_RETA_GROUP_SIZE;
1114 sft = i % RTE_RETA_GROUP_SIZE;
1116 if (!(reta_conf[idx].mask & (1ULL << sft)))
1119 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1121 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1125 if (BNXT_CHIP_THOR(bp)) {
1126 vnic->rss_table[i * 2] =
1127 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1128 vnic->rss_table[i * 2 + 1] =
1129 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1131 vnic->rss_table[i] =
1132 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1135 vnic->rss_table[i] =
1136 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1139 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1143 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1144 struct rte_eth_rss_reta_entry64 *reta_conf,
1147 struct bnxt *bp = eth_dev->data->dev_private;
1148 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1149 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1150 uint16_t idx, sft, i;
1152 /* Retrieve from the default VNIC */
1155 if (!vnic->rss_table)
1158 if (reta_size != tbl_size) {
1159 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1160 "(%d) must equal the size supported by the hardware "
1161 "(%d)\n", reta_size, tbl_size);
1165 for (idx = 0, i = 0; i < reta_size; i++) {
1166 idx = i / RTE_RETA_GROUP_SIZE;
1167 sft = i % RTE_RETA_GROUP_SIZE;
1169 if (reta_conf[idx].mask & (1ULL << sft)) {
1172 if (BNXT_CHIP_THOR(bp))
1173 qid = bnxt_rss_to_qid(bp,
1174 vnic->rss_table[i * 2]);
1176 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1178 if (qid == INVALID_HW_RING_ID) {
1179 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1182 reta_conf[idx].reta[sft] = qid;
1189 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1190 struct rte_eth_rss_conf *rss_conf)
1192 struct bnxt *bp = eth_dev->data->dev_private;
1193 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1194 struct bnxt_vnic_info *vnic;
1195 uint16_t hash_type = 0;
1199 * If RSS enablement were different than dev_configure,
1200 * then return -EINVAL
1202 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1203 if (!rss_conf->rss_hf)
1204 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1206 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1210 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1211 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1213 if (rss_conf->rss_hf & ETH_RSS_IPV4)
1214 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1215 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1216 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1217 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1218 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1219 if (rss_conf->rss_hf & ETH_RSS_IPV6)
1220 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1221 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1222 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1223 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1224 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1226 /* Update the RSS VNIC(s) */
1227 for (i = 0; i < bp->nr_vnics; i++) {
1228 vnic = &bp->vnic_info[i];
1229 vnic->hash_type = hash_type;
1232 * Use the supplied key if the key length is
1233 * acceptable and the rss_key is not NULL
1235 if (rss_conf->rss_key &&
1236 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1237 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1238 rss_conf->rss_key_len);
1240 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1245 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1246 struct rte_eth_rss_conf *rss_conf)
1248 struct bnxt *bp = eth_dev->data->dev_private;
1249 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1251 uint32_t hash_types;
1253 /* RSS configuration is the same for all VNICs */
1254 if (vnic && vnic->rss_hash_key) {
1255 if (rss_conf->rss_key) {
1256 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1257 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1258 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1261 hash_types = vnic->hash_type;
1262 rss_conf->rss_hf = 0;
1263 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1264 rss_conf->rss_hf |= ETH_RSS_IPV4;
1265 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1267 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1268 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1270 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1272 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1273 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1275 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1277 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1278 rss_conf->rss_hf |= ETH_RSS_IPV6;
1279 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1281 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1282 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1284 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1286 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1287 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1289 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1293 "Unknwon RSS config from firmware (%08x), RSS disabled",
1298 rss_conf->rss_hf = 0;
1303 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1304 struct rte_eth_fc_conf *fc_conf)
1306 struct bnxt *bp = dev->data->dev_private;
1307 struct rte_eth_link link_info;
1310 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1314 memset(fc_conf, 0, sizeof(*fc_conf));
1315 if (bp->link_info.auto_pause)
1316 fc_conf->autoneg = 1;
1317 switch (bp->link_info.pause) {
1319 fc_conf->mode = RTE_FC_NONE;
1321 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1322 fc_conf->mode = RTE_FC_TX_PAUSE;
1324 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1325 fc_conf->mode = RTE_FC_RX_PAUSE;
1327 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1328 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1329 fc_conf->mode = RTE_FC_FULL;
1335 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1336 struct rte_eth_fc_conf *fc_conf)
1338 struct bnxt *bp = dev->data->dev_private;
1340 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1341 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1345 switch (fc_conf->mode) {
1347 bp->link_info.auto_pause = 0;
1348 bp->link_info.force_pause = 0;
1350 case RTE_FC_RX_PAUSE:
1351 if (fc_conf->autoneg) {
1352 bp->link_info.auto_pause =
1353 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1354 bp->link_info.force_pause = 0;
1356 bp->link_info.auto_pause = 0;
1357 bp->link_info.force_pause =
1358 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1361 case RTE_FC_TX_PAUSE:
1362 if (fc_conf->autoneg) {
1363 bp->link_info.auto_pause =
1364 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1365 bp->link_info.force_pause = 0;
1367 bp->link_info.auto_pause = 0;
1368 bp->link_info.force_pause =
1369 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1373 if (fc_conf->autoneg) {
1374 bp->link_info.auto_pause =
1375 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1376 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1377 bp->link_info.force_pause = 0;
1379 bp->link_info.auto_pause = 0;
1380 bp->link_info.force_pause =
1381 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1382 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1386 return bnxt_set_hwrm_link_config(bp, true);
1389 /* Add UDP tunneling port */
1391 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1392 struct rte_eth_udp_tunnel *udp_tunnel)
1394 struct bnxt *bp = eth_dev->data->dev_private;
1395 uint16_t tunnel_type = 0;
1398 switch (udp_tunnel->prot_type) {
1399 case RTE_TUNNEL_TYPE_VXLAN:
1400 if (bp->vxlan_port_cnt) {
1401 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1402 udp_tunnel->udp_port);
1403 if (bp->vxlan_port != udp_tunnel->udp_port) {
1404 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1407 bp->vxlan_port_cnt++;
1411 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1412 bp->vxlan_port_cnt++;
1414 case RTE_TUNNEL_TYPE_GENEVE:
1415 if (bp->geneve_port_cnt) {
1416 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1417 udp_tunnel->udp_port);
1418 if (bp->geneve_port != udp_tunnel->udp_port) {
1419 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1422 bp->geneve_port_cnt++;
1426 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1427 bp->geneve_port_cnt++;
1430 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1433 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1439 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1440 struct rte_eth_udp_tunnel *udp_tunnel)
1442 struct bnxt *bp = eth_dev->data->dev_private;
1443 uint16_t tunnel_type = 0;
1447 switch (udp_tunnel->prot_type) {
1448 case RTE_TUNNEL_TYPE_VXLAN:
1449 if (!bp->vxlan_port_cnt) {
1450 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1453 if (bp->vxlan_port != udp_tunnel->udp_port) {
1454 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1455 udp_tunnel->udp_port, bp->vxlan_port);
1458 if (--bp->vxlan_port_cnt)
1462 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1463 port = bp->vxlan_fw_dst_port_id;
1465 case RTE_TUNNEL_TYPE_GENEVE:
1466 if (!bp->geneve_port_cnt) {
1467 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1470 if (bp->geneve_port != udp_tunnel->udp_port) {
1471 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1472 udp_tunnel->udp_port, bp->geneve_port);
1475 if (--bp->geneve_port_cnt)
1479 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1480 port = bp->geneve_fw_dst_port_id;
1483 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1487 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1490 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1493 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1494 bp->geneve_port = 0;
1499 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1501 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1502 struct bnxt_vnic_info *vnic;
1505 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1507 /* Cycle through all VNICs */
1508 for (i = 0; i < bp->nr_vnics; i++) {
1510 * For each VNIC and each associated filter(s)
1511 * if VLAN exists && VLAN matches vlan_id
1512 * remove the MAC+VLAN filter
1513 * add a new MAC only filter
1515 * VLAN filter doesn't exist, just skip and continue
1517 vnic = &bp->vnic_info[i];
1518 filter = STAILQ_FIRST(&vnic->filter);
1520 temp_filter = STAILQ_NEXT(filter, next);
1522 if (filter->enables & chk &&
1523 filter->l2_ovlan == vlan_id) {
1524 /* Must delete the filter */
1525 STAILQ_REMOVE(&vnic->filter, filter,
1526 bnxt_filter_info, next);
1527 bnxt_hwrm_clear_l2_filter(bp, filter);
1528 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1532 * Need to examine to see if the MAC
1533 * filter already existed or not before
1534 * allocating a new one
1537 new_filter = bnxt_alloc_filter(bp);
1540 "MAC/VLAN filter alloc failed\n");
1544 STAILQ_INSERT_TAIL(&vnic->filter,
1546 /* Inherit MAC from previous filter */
1547 new_filter->mac_index =
1549 memcpy(new_filter->l2_addr, filter->l2_addr,
1550 RTE_ETHER_ADDR_LEN);
1551 /* MAC only filter */
1552 rc = bnxt_hwrm_set_l2_filter(bp,
1558 "Del Vlan filter for %d\n",
1561 filter = temp_filter;
1568 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1570 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1571 struct bnxt_vnic_info *vnic;
1574 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1575 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1576 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1578 /* Cycle through all VNICs */
1579 for (i = 0; i < bp->nr_vnics; i++) {
1581 * For each VNIC and each associated filter(s)
1583 * if VLAN matches vlan_id
1584 * VLAN filter already exists, just skip and continue
1586 * add a new MAC+VLAN filter
1588 * Remove the old MAC only filter
1589 * Add a new MAC+VLAN filter
1591 vnic = &bp->vnic_info[i];
1592 filter = STAILQ_FIRST(&vnic->filter);
1594 temp_filter = STAILQ_NEXT(filter, next);
1596 if (filter->enables & chk) {
1597 if (filter->l2_ivlan == vlan_id)
1600 /* Must delete the MAC filter */
1601 STAILQ_REMOVE(&vnic->filter, filter,
1602 bnxt_filter_info, next);
1603 bnxt_hwrm_clear_l2_filter(bp, filter);
1604 filter->l2_ovlan = 0;
1605 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1608 new_filter = bnxt_alloc_filter(bp);
1611 "MAC/VLAN filter alloc failed\n");
1615 STAILQ_INSERT_TAIL(&vnic->filter, new_filter, next);
1616 /* Inherit MAC from the previous filter */
1617 new_filter->mac_index = filter->mac_index;
1618 memcpy(new_filter->l2_addr, filter->l2_addr,
1619 RTE_ETHER_ADDR_LEN);
1620 /* MAC + VLAN ID filter */
1621 new_filter->l2_ivlan = vlan_id;
1622 new_filter->l2_ivlan_mask = 0xF000;
1623 new_filter->enables |= en;
1624 rc = bnxt_hwrm_set_l2_filter(bp,
1630 "Added Vlan filter for %d\n", vlan_id);
1632 filter = temp_filter;
1639 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1640 uint16_t vlan_id, int on)
1642 struct bnxt *bp = eth_dev->data->dev_private;
1644 /* These operations apply to ALL existing MAC/VLAN filters */
1646 return bnxt_add_vlan_filter(bp, vlan_id);
1648 return bnxt_del_vlan_filter(bp, vlan_id);
1652 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1654 struct bnxt *bp = dev->data->dev_private;
1655 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1658 if (mask & ETH_VLAN_FILTER_MASK) {
1659 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1660 /* Remove any VLAN filters programmed */
1661 for (i = 0; i < 4095; i++)
1662 bnxt_del_vlan_filter(bp, i);
1664 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1665 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1668 if (mask & ETH_VLAN_STRIP_MASK) {
1669 /* Enable or disable VLAN stripping */
1670 for (i = 0; i < bp->nr_vnics; i++) {
1671 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1672 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1673 vnic->vlan_strip = true;
1675 vnic->vlan_strip = false;
1676 bnxt_hwrm_vnic_cfg(bp, vnic);
1678 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1679 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1682 if (mask & ETH_VLAN_EXTEND_MASK)
1683 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1689 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1690 struct rte_ether_addr *addr)
1692 struct bnxt *bp = dev->data->dev_private;
1693 /* Default Filter is tied to VNIC 0 */
1694 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1695 struct bnxt_filter_info *filter;
1698 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1701 memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1703 STAILQ_FOREACH(filter, &vnic->filter, next) {
1704 /* Default Filter is at Index 0 */
1705 if (filter->mac_index != 0)
1707 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1710 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1711 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1712 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1714 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1715 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1716 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1719 filter->mac_index = 0;
1720 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1727 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1728 struct rte_ether_addr *mc_addr_set,
1729 uint32_t nb_mc_addr)
1731 struct bnxt *bp = eth_dev->data->dev_private;
1732 char *mc_addr_list = (char *)mc_addr_set;
1733 struct bnxt_vnic_info *vnic;
1734 uint32_t off = 0, i = 0;
1736 vnic = &bp->vnic_info[0];
1738 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1739 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1743 /* TODO Check for Duplicate mcast addresses */
1744 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1745 for (i = 0; i < nb_mc_addr; i++) {
1746 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1747 RTE_ETHER_ADDR_LEN);
1748 off += RTE_ETHER_ADDR_LEN;
1751 vnic->mc_addr_cnt = i;
1754 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1758 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1760 struct bnxt *bp = dev->data->dev_private;
1761 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1762 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1763 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1766 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1767 fw_major, fw_minor, fw_updt);
1769 ret += 1; /* add the size of '\0' */
1770 if (fw_size < (uint32_t)ret)
1777 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1778 struct rte_eth_rxq_info *qinfo)
1780 struct bnxt_rx_queue *rxq;
1782 rxq = dev->data->rx_queues[queue_id];
1784 qinfo->mp = rxq->mb_pool;
1785 qinfo->scattered_rx = dev->data->scattered_rx;
1786 qinfo->nb_desc = rxq->nb_rx_desc;
1788 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1789 qinfo->conf.rx_drop_en = 0;
1790 qinfo->conf.rx_deferred_start = 0;
1794 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1795 struct rte_eth_txq_info *qinfo)
1797 struct bnxt_tx_queue *txq;
1799 txq = dev->data->tx_queues[queue_id];
1801 qinfo->nb_desc = txq->nb_tx_desc;
1803 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1804 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1805 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1807 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1808 qinfo->conf.tx_rs_thresh = 0;
1809 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1812 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1814 struct bnxt *bp = eth_dev->data->dev_private;
1815 struct rte_eth_dev_info dev_info;
1816 uint32_t new_pkt_size;
1820 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1821 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1823 bnxt_dev_info_get_op(eth_dev, &dev_info);
1825 if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1826 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1827 RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1833 * If vector-mode tx/rx is active, disallow any MTU change that would
1834 * require scattered receive support.
1836 if (eth_dev->data->dev_started &&
1837 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1838 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1840 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1842 "MTU change would require scattered rx support. ");
1843 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
1848 if (new_mtu > RTE_ETHER_MTU) {
1849 bp->flags |= BNXT_FLAG_JUMBO;
1850 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1851 DEV_RX_OFFLOAD_JUMBO_FRAME;
1853 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1854 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1855 bp->flags &= ~BNXT_FLAG_JUMBO;
1858 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
1860 eth_dev->data->mtu = new_mtu;
1861 PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1863 for (i = 0; i < bp->nr_vnics; i++) {
1864 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1867 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1868 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1869 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1873 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1874 size -= RTE_PKTMBUF_HEADROOM;
1876 if (size < new_mtu) {
1877 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1887 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1889 struct bnxt *bp = dev->data->dev_private;
1890 uint16_t vlan = bp->vlan;
1893 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1895 "PVID cannot be modified for this function\n");
1898 bp->vlan = on ? pvid : 0;
1900 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1907 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1909 struct bnxt *bp = dev->data->dev_private;
1911 return bnxt_hwrm_port_led_cfg(bp, true);
1915 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1917 struct bnxt *bp = dev->data->dev_private;
1919 return bnxt_hwrm_port_led_cfg(bp, false);
1923 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1925 uint32_t desc = 0, raw_cons = 0, cons;
1926 struct bnxt_cp_ring_info *cpr;
1927 struct bnxt_rx_queue *rxq;
1928 struct rx_pkt_cmpl *rxcmp;
1933 rxq = dev->data->rx_queues[rx_queue_id];
1937 while (raw_cons < rxq->nb_rx_desc) {
1938 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1939 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1941 if (!CMPL_VALID(rxcmp, valid))
1943 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1944 cmp_type = CMP_TYPE(rxcmp);
1945 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1946 cmp = (rte_le_to_cpu_32(
1947 ((struct rx_tpa_end_cmpl *)
1948 (rxcmp))->agg_bufs_v1) &
1949 RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1950 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1952 } else if (cmp_type == 0x11) {
1954 cmp = (rxcmp->agg_bufs_v1 &
1955 RX_PKT_CMPL_AGG_BUFS_MASK) >>
1956 RX_PKT_CMPL_AGG_BUFS_SFT;
1961 raw_cons += cmp ? cmp : 2;
1968 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1970 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1971 struct bnxt_rx_ring_info *rxr;
1972 struct bnxt_cp_ring_info *cpr;
1973 struct bnxt_sw_rx_bd *rx_buf;
1974 struct rx_pkt_cmpl *rxcmp;
1975 uint32_t cons, cp_cons;
1983 if (offset >= rxq->nb_rx_desc)
1986 cons = RING_CMP(cpr->cp_ring_struct, offset);
1987 cp_cons = cpr->cp_raw_cons;
1988 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1990 if (cons > cp_cons) {
1991 if (CMPL_VALID(rxcmp, cpr->valid))
1992 return RTE_ETH_RX_DESC_DONE;
1994 if (CMPL_VALID(rxcmp, !cpr->valid))
1995 return RTE_ETH_RX_DESC_DONE;
1997 rx_buf = &rxr->rx_buf_ring[cons];
1998 if (rx_buf->mbuf == NULL)
1999 return RTE_ETH_RX_DESC_UNAVAIL;
2002 return RTE_ETH_RX_DESC_AVAIL;
2006 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2008 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2009 struct bnxt_tx_ring_info *txr;
2010 struct bnxt_cp_ring_info *cpr;
2011 struct bnxt_sw_tx_bd *tx_buf;
2012 struct tx_pkt_cmpl *txcmp;
2013 uint32_t cons, cp_cons;
2021 if (offset >= txq->nb_tx_desc)
2024 cons = RING_CMP(cpr->cp_ring_struct, offset);
2025 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2026 cp_cons = cpr->cp_raw_cons;
2028 if (cons > cp_cons) {
2029 if (CMPL_VALID(txcmp, cpr->valid))
2030 return RTE_ETH_TX_DESC_UNAVAIL;
2032 if (CMPL_VALID(txcmp, !cpr->valid))
2033 return RTE_ETH_TX_DESC_UNAVAIL;
2035 tx_buf = &txr->tx_buf_ring[cons];
2036 if (tx_buf->mbuf == NULL)
2037 return RTE_ETH_TX_DESC_DONE;
2039 return RTE_ETH_TX_DESC_FULL;
2042 static struct bnxt_filter_info *
2043 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2044 struct rte_eth_ethertype_filter *efilter,
2045 struct bnxt_vnic_info *vnic0,
2046 struct bnxt_vnic_info *vnic,
2049 struct bnxt_filter_info *mfilter = NULL;
2053 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2054 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2055 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2056 " ethertype filter.", efilter->ether_type);
2060 if (efilter->queue >= bp->rx_nr_rings) {
2061 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2066 vnic0 = &bp->vnic_info[0];
2067 vnic = &bp->vnic_info[efilter->queue];
2069 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2074 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2075 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2076 if ((!memcmp(efilter->mac_addr.addr_bytes,
2077 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2079 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2080 mfilter->ethertype == efilter->ether_type)) {
2086 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2087 if ((!memcmp(efilter->mac_addr.addr_bytes,
2088 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2089 mfilter->ethertype == efilter->ether_type &&
2091 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2105 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2106 enum rte_filter_op filter_op,
2109 struct bnxt *bp = dev->data->dev_private;
2110 struct rte_eth_ethertype_filter *efilter =
2111 (struct rte_eth_ethertype_filter *)arg;
2112 struct bnxt_filter_info *bfilter, *filter1;
2113 struct bnxt_vnic_info *vnic, *vnic0;
2116 if (filter_op == RTE_ETH_FILTER_NOP)
2120 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2125 vnic0 = &bp->vnic_info[0];
2126 vnic = &bp->vnic_info[efilter->queue];
2128 switch (filter_op) {
2129 case RTE_ETH_FILTER_ADD:
2130 bnxt_match_and_validate_ether_filter(bp, efilter,
2135 bfilter = bnxt_get_unused_filter(bp);
2136 if (bfilter == NULL) {
2138 "Not enough resources for a new filter.\n");
2141 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2142 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2143 RTE_ETHER_ADDR_LEN);
2144 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2145 RTE_ETHER_ADDR_LEN);
2146 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2147 bfilter->ethertype = efilter->ether_type;
2148 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2150 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2151 if (filter1 == NULL) {
2156 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2157 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2159 bfilter->dst_id = vnic->fw_vnic_id;
2161 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2163 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2166 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2169 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2171 case RTE_ETH_FILTER_DELETE:
2172 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2174 if (ret == -EEXIST) {
2175 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2177 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2179 bnxt_free_filter(bp, filter1);
2180 } else if (ret == 0) {
2181 PMD_DRV_LOG(ERR, "No matching filter found\n");
2185 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2191 bnxt_free_filter(bp, bfilter);
2197 parse_ntuple_filter(struct bnxt *bp,
2198 struct rte_eth_ntuple_filter *nfilter,
2199 struct bnxt_filter_info *bfilter)
2203 if (nfilter->queue >= bp->rx_nr_rings) {
2204 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2208 switch (nfilter->dst_port_mask) {
2210 bfilter->dst_port_mask = -1;
2211 bfilter->dst_port = nfilter->dst_port;
2212 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2213 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2216 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2220 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2221 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2223 switch (nfilter->proto_mask) {
2225 if (nfilter->proto == 17) /* IPPROTO_UDP */
2226 bfilter->ip_protocol = 17;
2227 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2228 bfilter->ip_protocol = 6;
2231 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2234 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2238 switch (nfilter->dst_ip_mask) {
2240 bfilter->dst_ipaddr_mask[0] = -1;
2241 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2242 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2243 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2246 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2250 switch (nfilter->src_ip_mask) {
2252 bfilter->src_ipaddr_mask[0] = -1;
2253 bfilter->src_ipaddr[0] = nfilter->src_ip;
2254 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2255 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2258 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2262 switch (nfilter->src_port_mask) {
2264 bfilter->src_port_mask = -1;
2265 bfilter->src_port = nfilter->src_port;
2266 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2267 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2270 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2275 //nfilter->priority = (uint8_t)filter->priority;
2277 bfilter->enables = en;
2281 static struct bnxt_filter_info*
2282 bnxt_match_ntuple_filter(struct bnxt *bp,
2283 struct bnxt_filter_info *bfilter,
2284 struct bnxt_vnic_info **mvnic)
2286 struct bnxt_filter_info *mfilter = NULL;
2289 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2290 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2291 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2292 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2293 bfilter->src_ipaddr_mask[0] ==
2294 mfilter->src_ipaddr_mask[0] &&
2295 bfilter->src_port == mfilter->src_port &&
2296 bfilter->src_port_mask == mfilter->src_port_mask &&
2297 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2298 bfilter->dst_ipaddr_mask[0] ==
2299 mfilter->dst_ipaddr_mask[0] &&
2300 bfilter->dst_port == mfilter->dst_port &&
2301 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2302 bfilter->flags == mfilter->flags &&
2303 bfilter->enables == mfilter->enables) {
2314 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2315 struct rte_eth_ntuple_filter *nfilter,
2316 enum rte_filter_op filter_op)
2318 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2319 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2322 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2323 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2327 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2328 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2332 bfilter = bnxt_get_unused_filter(bp);
2333 if (bfilter == NULL) {
2335 "Not enough resources for a new filter.\n");
2338 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2342 vnic = &bp->vnic_info[nfilter->queue];
2343 vnic0 = &bp->vnic_info[0];
2344 filter1 = STAILQ_FIRST(&vnic0->filter);
2345 if (filter1 == NULL) {
2350 bfilter->dst_id = vnic->fw_vnic_id;
2351 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2353 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2354 bfilter->ethertype = 0x800;
2355 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2357 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2359 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2360 bfilter->dst_id == mfilter->dst_id) {
2361 PMD_DRV_LOG(ERR, "filter exists.\n");
2364 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2365 bfilter->dst_id != mfilter->dst_id) {
2366 mfilter->dst_id = vnic->fw_vnic_id;
2367 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2368 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2369 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2370 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2371 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2374 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2375 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2380 if (filter_op == RTE_ETH_FILTER_ADD) {
2381 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2382 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2385 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2387 if (mfilter == NULL) {
2388 /* This should not happen. But for Coverity! */
2392 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2394 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2395 bnxt_free_filter(bp, mfilter);
2396 mfilter->fw_l2_filter_id = -1;
2397 bnxt_free_filter(bp, bfilter);
2398 bfilter->fw_l2_filter_id = -1;
2403 bfilter->fw_l2_filter_id = -1;
2404 bnxt_free_filter(bp, bfilter);
2409 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2410 enum rte_filter_op filter_op,
2413 struct bnxt *bp = dev->data->dev_private;
2416 if (filter_op == RTE_ETH_FILTER_NOP)
2420 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2425 switch (filter_op) {
2426 case RTE_ETH_FILTER_ADD:
2427 ret = bnxt_cfg_ntuple_filter(bp,
2428 (struct rte_eth_ntuple_filter *)arg,
2431 case RTE_ETH_FILTER_DELETE:
2432 ret = bnxt_cfg_ntuple_filter(bp,
2433 (struct rte_eth_ntuple_filter *)arg,
2437 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2445 bnxt_parse_fdir_filter(struct bnxt *bp,
2446 struct rte_eth_fdir_filter *fdir,
2447 struct bnxt_filter_info *filter)
2449 enum rte_fdir_mode fdir_mode =
2450 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2451 struct bnxt_vnic_info *vnic0, *vnic;
2452 struct bnxt_filter_info *filter1;
2456 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2459 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2460 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2462 switch (fdir->input.flow_type) {
2463 case RTE_ETH_FLOW_IPV4:
2464 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2466 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2467 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2468 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2469 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2470 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2471 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2472 filter->ip_addr_type =
2473 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2474 filter->src_ipaddr_mask[0] = 0xffffffff;
2475 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2476 filter->dst_ipaddr_mask[0] = 0xffffffff;
2477 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2478 filter->ethertype = 0x800;
2479 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2481 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2482 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2483 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2484 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2485 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2486 filter->dst_port_mask = 0xffff;
2487 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2488 filter->src_port_mask = 0xffff;
2489 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2490 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2491 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2492 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2493 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2494 filter->ip_protocol = 6;
2495 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2496 filter->ip_addr_type =
2497 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2498 filter->src_ipaddr_mask[0] = 0xffffffff;
2499 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2500 filter->dst_ipaddr_mask[0] = 0xffffffff;
2501 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2502 filter->ethertype = 0x800;
2503 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2505 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2506 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2507 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2508 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2509 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2510 filter->dst_port_mask = 0xffff;
2511 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2512 filter->src_port_mask = 0xffff;
2513 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2514 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2515 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2516 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2517 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2518 filter->ip_protocol = 17;
2519 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2520 filter->ip_addr_type =
2521 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2522 filter->src_ipaddr_mask[0] = 0xffffffff;
2523 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2524 filter->dst_ipaddr_mask[0] = 0xffffffff;
2525 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2526 filter->ethertype = 0x800;
2527 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2529 case RTE_ETH_FLOW_IPV6:
2530 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2532 filter->ip_addr_type =
2533 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2534 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2535 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2536 rte_memcpy(filter->src_ipaddr,
2537 fdir->input.flow.ipv6_flow.src_ip, 16);
2538 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2539 rte_memcpy(filter->dst_ipaddr,
2540 fdir->input.flow.ipv6_flow.dst_ip, 16);
2541 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2542 memset(filter->dst_ipaddr_mask, 0xff, 16);
2543 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2544 memset(filter->src_ipaddr_mask, 0xff, 16);
2545 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2546 filter->ethertype = 0x86dd;
2547 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2549 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2550 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2551 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2552 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2553 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2554 filter->dst_port_mask = 0xffff;
2555 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2556 filter->src_port_mask = 0xffff;
2557 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2558 filter->ip_addr_type =
2559 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2560 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2561 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2562 rte_memcpy(filter->src_ipaddr,
2563 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2564 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2565 rte_memcpy(filter->dst_ipaddr,
2566 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2567 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2568 memset(filter->dst_ipaddr_mask, 0xff, 16);
2569 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2570 memset(filter->src_ipaddr_mask, 0xff, 16);
2571 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2572 filter->ethertype = 0x86dd;
2573 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2575 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2576 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2577 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2578 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2579 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2580 filter->dst_port_mask = 0xffff;
2581 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2582 filter->src_port_mask = 0xffff;
2583 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2584 filter->ip_addr_type =
2585 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2586 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2587 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2588 rte_memcpy(filter->src_ipaddr,
2589 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2590 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2591 rte_memcpy(filter->dst_ipaddr,
2592 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2593 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2594 memset(filter->dst_ipaddr_mask, 0xff, 16);
2595 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2596 memset(filter->src_ipaddr_mask, 0xff, 16);
2597 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2598 filter->ethertype = 0x86dd;
2599 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2601 case RTE_ETH_FLOW_L2_PAYLOAD:
2602 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2603 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2605 case RTE_ETH_FLOW_VXLAN:
2606 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2608 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2609 filter->tunnel_type =
2610 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2611 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2613 case RTE_ETH_FLOW_NVGRE:
2614 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2616 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2617 filter->tunnel_type =
2618 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2619 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2621 case RTE_ETH_FLOW_UNKNOWN:
2622 case RTE_ETH_FLOW_RAW:
2623 case RTE_ETH_FLOW_FRAG_IPV4:
2624 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2625 case RTE_ETH_FLOW_FRAG_IPV6:
2626 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2627 case RTE_ETH_FLOW_IPV6_EX:
2628 case RTE_ETH_FLOW_IPV6_TCP_EX:
2629 case RTE_ETH_FLOW_IPV6_UDP_EX:
2630 case RTE_ETH_FLOW_GENEVE:
2636 vnic0 = &bp->vnic_info[0];
2637 vnic = &bp->vnic_info[fdir->action.rx_queue];
2639 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2644 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2645 rte_memcpy(filter->dst_macaddr,
2646 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2647 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2650 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2651 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2652 filter1 = STAILQ_FIRST(&vnic0->filter);
2653 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2655 filter->dst_id = vnic->fw_vnic_id;
2656 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2657 if (filter->dst_macaddr[i] == 0x00)
2658 filter1 = STAILQ_FIRST(&vnic0->filter);
2660 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2663 if (filter1 == NULL)
2666 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2667 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2669 filter->enables = en;
2674 static struct bnxt_filter_info *
2675 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2676 struct bnxt_vnic_info **mvnic)
2678 struct bnxt_filter_info *mf = NULL;
2681 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2682 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2684 STAILQ_FOREACH(mf, &vnic->filter, next) {
2685 if (mf->filter_type == nf->filter_type &&
2686 mf->flags == nf->flags &&
2687 mf->src_port == nf->src_port &&
2688 mf->src_port_mask == nf->src_port_mask &&
2689 mf->dst_port == nf->dst_port &&
2690 mf->dst_port_mask == nf->dst_port_mask &&
2691 mf->ip_protocol == nf->ip_protocol &&
2692 mf->ip_addr_type == nf->ip_addr_type &&
2693 mf->ethertype == nf->ethertype &&
2694 mf->vni == nf->vni &&
2695 mf->tunnel_type == nf->tunnel_type &&
2696 mf->l2_ovlan == nf->l2_ovlan &&
2697 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2698 mf->l2_ivlan == nf->l2_ivlan &&
2699 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2700 !memcmp(mf->l2_addr, nf->l2_addr,
2701 RTE_ETHER_ADDR_LEN) &&
2702 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2703 RTE_ETHER_ADDR_LEN) &&
2704 !memcmp(mf->src_macaddr, nf->src_macaddr,
2705 RTE_ETHER_ADDR_LEN) &&
2706 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2707 RTE_ETHER_ADDR_LEN) &&
2708 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2709 sizeof(nf->src_ipaddr)) &&
2710 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2711 sizeof(nf->src_ipaddr_mask)) &&
2712 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2713 sizeof(nf->dst_ipaddr)) &&
2714 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2715 sizeof(nf->dst_ipaddr_mask))) {
2726 bnxt_fdir_filter(struct rte_eth_dev *dev,
2727 enum rte_filter_op filter_op,
2730 struct bnxt *bp = dev->data->dev_private;
2731 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2732 struct bnxt_filter_info *filter, *match;
2733 struct bnxt_vnic_info *vnic, *mvnic;
2736 if (filter_op == RTE_ETH_FILTER_NOP)
2739 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2742 switch (filter_op) {
2743 case RTE_ETH_FILTER_ADD:
2744 case RTE_ETH_FILTER_DELETE:
2746 filter = bnxt_get_unused_filter(bp);
2747 if (filter == NULL) {
2749 "Not enough resources for a new flow.\n");
2753 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2756 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2758 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2759 vnic = &bp->vnic_info[0];
2761 vnic = &bp->vnic_info[fdir->action.rx_queue];
2763 match = bnxt_match_fdir(bp, filter, &mvnic);
2764 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2765 if (match->dst_id == vnic->fw_vnic_id) {
2766 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2770 match->dst_id = vnic->fw_vnic_id;
2771 ret = bnxt_hwrm_set_ntuple_filter(bp,
2774 STAILQ_REMOVE(&mvnic->filter, match,
2775 bnxt_filter_info, next);
2776 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2778 "Filter with matching pattern exist\n");
2780 "Updated it to new destination q\n");
2784 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2785 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2790 if (filter_op == RTE_ETH_FILTER_ADD) {
2791 ret = bnxt_hwrm_set_ntuple_filter(bp,
2796 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2798 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2799 STAILQ_REMOVE(&vnic->filter, match,
2800 bnxt_filter_info, next);
2801 bnxt_free_filter(bp, match);
2802 filter->fw_l2_filter_id = -1;
2803 bnxt_free_filter(bp, filter);
2806 case RTE_ETH_FILTER_FLUSH:
2807 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2808 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2810 STAILQ_FOREACH(filter, &vnic->filter, next) {
2811 if (filter->filter_type ==
2812 HWRM_CFA_NTUPLE_FILTER) {
2814 bnxt_hwrm_clear_ntuple_filter(bp,
2816 STAILQ_REMOVE(&vnic->filter, filter,
2817 bnxt_filter_info, next);
2822 case RTE_ETH_FILTER_UPDATE:
2823 case RTE_ETH_FILTER_STATS:
2824 case RTE_ETH_FILTER_INFO:
2825 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2828 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2835 filter->fw_l2_filter_id = -1;
2836 bnxt_free_filter(bp, filter);
2841 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2842 enum rte_filter_type filter_type,
2843 enum rte_filter_op filter_op, void *arg)
2847 switch (filter_type) {
2848 case RTE_ETH_FILTER_TUNNEL:
2850 "filter type: %d: To be implemented\n", filter_type);
2852 case RTE_ETH_FILTER_FDIR:
2853 ret = bnxt_fdir_filter(dev, filter_op, arg);
2855 case RTE_ETH_FILTER_NTUPLE:
2856 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2858 case RTE_ETH_FILTER_ETHERTYPE:
2859 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2861 case RTE_ETH_FILTER_GENERIC:
2862 if (filter_op != RTE_ETH_FILTER_GET)
2864 *(const void **)arg = &bnxt_flow_ops;
2868 "Filter type (%d) not supported", filter_type);
2875 static const uint32_t *
2876 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2878 static const uint32_t ptypes[] = {
2879 RTE_PTYPE_L2_ETHER_VLAN,
2880 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2881 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2885 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2886 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2887 RTE_PTYPE_INNER_L4_ICMP,
2888 RTE_PTYPE_INNER_L4_TCP,
2889 RTE_PTYPE_INNER_L4_UDP,
2893 if (!dev->rx_pkt_burst)
2899 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2902 uint32_t reg_base = *reg_arr & 0xfffff000;
2906 for (i = 0; i < count; i++) {
2907 if ((reg_arr[i] & 0xfffff000) != reg_base)
2910 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2911 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
2915 static int bnxt_map_ptp_regs(struct bnxt *bp)
2917 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2921 reg_arr = ptp->rx_regs;
2922 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2926 reg_arr = ptp->tx_regs;
2927 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2931 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2932 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2934 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2935 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2940 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2942 rte_write32(0, (uint8_t *)bp->bar0 +
2943 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
2944 rte_write32(0, (uint8_t *)bp->bar0 +
2945 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
2948 static uint64_t bnxt_cc_read(struct bnxt *bp)
2952 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2953 BNXT_GRCPF_REG_SYNC_TIME));
2954 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2955 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2959 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2961 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2964 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2965 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2966 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2969 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2970 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2971 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2972 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2973 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2974 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2979 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2981 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2982 struct bnxt_pf_info *pf = &bp->pf;
2989 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2990 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2991 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2994 port_id = pf->port_id;
2995 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2996 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
2998 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2999 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3000 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3001 /* bnxt_clr_rx_ts(bp); TBD */
3005 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3006 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3007 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3008 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3014 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3017 struct bnxt *bp = dev->data->dev_private;
3018 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3023 ns = rte_timespec_to_ns(ts);
3024 /* Set the timecounters to a new value. */
3031 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3033 uint64_t ns, systime_cycles;
3034 struct bnxt *bp = dev->data->dev_private;
3035 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3040 systime_cycles = bnxt_cc_read(bp);
3041 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3042 *ts = rte_ns_to_timespec(ns);
3047 bnxt_timesync_enable(struct rte_eth_dev *dev)
3049 struct bnxt *bp = dev->data->dev_private;
3050 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3057 ptp->tx_tstamp_en = 1;
3058 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3060 if (!bnxt_hwrm_ptp_cfg(bp))
3061 bnxt_map_ptp_regs(bp);
3063 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3064 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3065 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3067 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3068 ptp->tc.cc_shift = shift;
3069 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3071 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3072 ptp->rx_tstamp_tc.cc_shift = shift;
3073 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3075 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3076 ptp->tx_tstamp_tc.cc_shift = shift;
3077 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3083 bnxt_timesync_disable(struct rte_eth_dev *dev)
3085 struct bnxt *bp = dev->data->dev_private;
3086 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3092 ptp->tx_tstamp_en = 0;
3095 bnxt_hwrm_ptp_cfg(bp);
3097 bnxt_unmap_ptp_regs(bp);
3103 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3104 struct timespec *timestamp,
3105 uint32_t flags __rte_unused)
3107 struct bnxt *bp = dev->data->dev_private;
3108 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3109 uint64_t rx_tstamp_cycles = 0;
3115 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3116 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3117 *timestamp = rte_ns_to_timespec(ns);
3122 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3123 struct timespec *timestamp)
3125 struct bnxt *bp = dev->data->dev_private;
3126 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3127 uint64_t tx_tstamp_cycles = 0;
3133 bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3134 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3135 *timestamp = rte_ns_to_timespec(ns);
3141 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3143 struct bnxt *bp = dev->data->dev_private;
3144 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3149 ptp->tc.nsec += delta;
3155 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3157 struct bnxt *bp = dev->data->dev_private;
3159 uint32_t dir_entries;
3160 uint32_t entry_length;
3162 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3163 bp->pdev->addr.domain, bp->pdev->addr.bus,
3164 bp->pdev->addr.devid, bp->pdev->addr.function);
3166 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3170 return dir_entries * entry_length;
3174 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3175 struct rte_dev_eeprom_info *in_eeprom)
3177 struct bnxt *bp = dev->data->dev_private;
3181 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3182 "len = %d\n", bp->pdev->addr.domain,
3183 bp->pdev->addr.bus, bp->pdev->addr.devid,
3184 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3186 if (in_eeprom->offset == 0) /* special offset value to get directory */
3187 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3190 index = in_eeprom->offset >> 24;
3191 offset = in_eeprom->offset & 0xffffff;
3194 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3195 in_eeprom->length, in_eeprom->data);
3200 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3203 case BNX_DIR_TYPE_CHIMP_PATCH:
3204 case BNX_DIR_TYPE_BOOTCODE:
3205 case BNX_DIR_TYPE_BOOTCODE_2:
3206 case BNX_DIR_TYPE_APE_FW:
3207 case BNX_DIR_TYPE_APE_PATCH:
3208 case BNX_DIR_TYPE_KONG_FW:
3209 case BNX_DIR_TYPE_KONG_PATCH:
3210 case BNX_DIR_TYPE_BONO_FW:
3211 case BNX_DIR_TYPE_BONO_PATCH:
3219 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3222 case BNX_DIR_TYPE_AVS:
3223 case BNX_DIR_TYPE_EXP_ROM_MBA:
3224 case BNX_DIR_TYPE_PCIE:
3225 case BNX_DIR_TYPE_TSCF_UCODE:
3226 case BNX_DIR_TYPE_EXT_PHY:
3227 case BNX_DIR_TYPE_CCM:
3228 case BNX_DIR_TYPE_ISCSI_BOOT:
3229 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3230 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3238 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3240 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3241 bnxt_dir_type_is_other_exec_format(dir_type);
3245 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3246 struct rte_dev_eeprom_info *in_eeprom)
3248 struct bnxt *bp = dev->data->dev_private;
3249 uint8_t index, dir_op;
3250 uint16_t type, ext, ordinal, attr;
3252 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3253 "len = %d\n", bp->pdev->addr.domain,
3254 bp->pdev->addr.bus, bp->pdev->addr.devid,
3255 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3258 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3262 type = in_eeprom->magic >> 16;
3264 if (type == 0xffff) { /* special value for directory operations */
3265 index = in_eeprom->magic & 0xff;
3266 dir_op = in_eeprom->magic >> 8;
3270 case 0x0e: /* erase */
3271 if (in_eeprom->offset != ~in_eeprom->magic)
3273 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3279 /* Create or re-write an NVM item: */
3280 if (bnxt_dir_type_is_executable(type) == true)
3282 ext = in_eeprom->magic & 0xffff;
3283 ordinal = in_eeprom->offset >> 16;
3284 attr = in_eeprom->offset & 0xffff;
3286 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3287 in_eeprom->data, in_eeprom->length);
3295 static const struct eth_dev_ops bnxt_dev_ops = {
3296 .dev_infos_get = bnxt_dev_info_get_op,
3297 .dev_close = bnxt_dev_close_op,
3298 .dev_configure = bnxt_dev_configure_op,
3299 .dev_start = bnxt_dev_start_op,
3300 .dev_stop = bnxt_dev_stop_op,
3301 .dev_set_link_up = bnxt_dev_set_link_up_op,
3302 .dev_set_link_down = bnxt_dev_set_link_down_op,
3303 .stats_get = bnxt_stats_get_op,
3304 .stats_reset = bnxt_stats_reset_op,
3305 .rx_queue_setup = bnxt_rx_queue_setup_op,
3306 .rx_queue_release = bnxt_rx_queue_release_op,
3307 .tx_queue_setup = bnxt_tx_queue_setup_op,
3308 .tx_queue_release = bnxt_tx_queue_release_op,
3309 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3310 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3311 .reta_update = bnxt_reta_update_op,
3312 .reta_query = bnxt_reta_query_op,
3313 .rss_hash_update = bnxt_rss_hash_update_op,
3314 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3315 .link_update = bnxt_link_update_op,
3316 .promiscuous_enable = bnxt_promiscuous_enable_op,
3317 .promiscuous_disable = bnxt_promiscuous_disable_op,
3318 .allmulticast_enable = bnxt_allmulticast_enable_op,
3319 .allmulticast_disable = bnxt_allmulticast_disable_op,
3320 .mac_addr_add = bnxt_mac_addr_add_op,
3321 .mac_addr_remove = bnxt_mac_addr_remove_op,
3322 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3323 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3324 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3325 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3326 .vlan_filter_set = bnxt_vlan_filter_set_op,
3327 .vlan_offload_set = bnxt_vlan_offload_set_op,
3328 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3329 .mtu_set = bnxt_mtu_set_op,
3330 .mac_addr_set = bnxt_set_default_mac_addr_op,
3331 .xstats_get = bnxt_dev_xstats_get_op,
3332 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3333 .xstats_reset = bnxt_dev_xstats_reset_op,
3334 .fw_version_get = bnxt_fw_version_get,
3335 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3336 .rxq_info_get = bnxt_rxq_info_get_op,
3337 .txq_info_get = bnxt_txq_info_get_op,
3338 .dev_led_on = bnxt_dev_led_on_op,
3339 .dev_led_off = bnxt_dev_led_off_op,
3340 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3341 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3342 .rx_queue_count = bnxt_rx_queue_count_op,
3343 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3344 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3345 .rx_queue_start = bnxt_rx_queue_start,
3346 .rx_queue_stop = bnxt_rx_queue_stop,
3347 .tx_queue_start = bnxt_tx_queue_start,
3348 .tx_queue_stop = bnxt_tx_queue_stop,
3349 .filter_ctrl = bnxt_filter_ctrl_op,
3350 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3351 .get_eeprom_length = bnxt_get_eeprom_length_op,
3352 .get_eeprom = bnxt_get_eeprom_op,
3353 .set_eeprom = bnxt_set_eeprom_op,
3354 .timesync_enable = bnxt_timesync_enable,
3355 .timesync_disable = bnxt_timesync_disable,
3356 .timesync_read_time = bnxt_timesync_read_time,
3357 .timesync_write_time = bnxt_timesync_write_time,
3358 .timesync_adjust_time = bnxt_timesync_adjust_time,
3359 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3360 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3363 static bool bnxt_vf_pciid(uint16_t id)
3365 if (id == BROADCOM_DEV_ID_57304_VF ||
3366 id == BROADCOM_DEV_ID_57406_VF ||
3367 id == BROADCOM_DEV_ID_5731X_VF ||
3368 id == BROADCOM_DEV_ID_5741X_VF ||
3369 id == BROADCOM_DEV_ID_57414_VF ||
3370 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3371 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3372 id == BROADCOM_DEV_ID_58802_VF ||
3373 id == BROADCOM_DEV_ID_57500_VF)
3378 bool bnxt_stratus_device(struct bnxt *bp)
3380 uint16_t id = bp->pdev->id.device_id;
3382 if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3383 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3384 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3389 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3391 struct bnxt *bp = eth_dev->data->dev_private;
3392 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3395 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3396 if (!pci_dev->mem_resource[0].addr) {
3398 "Cannot find PCI device base address, aborting\n");
3400 goto init_err_disable;
3403 bp->eth_dev = eth_dev;
3406 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3408 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3410 goto init_err_release;
3413 if (!pci_dev->mem_resource[2].addr) {
3415 "Cannot find PCI device BAR 2 address, aborting\n");
3417 goto init_err_release;
3419 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3427 if (bp->doorbell_base)
3428 bp->doorbell_base = NULL;
3435 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3436 struct bnxt_ctx_pg_info *ctx_pg,
3441 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3442 const struct rte_memzone *mz = NULL;
3443 char mz_name[RTE_MEMZONE_NAMESIZE];
3444 rte_iova_t mz_phys_addr;
3445 uint64_t valid_bits = 0;
3452 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3454 rmem->page_size = BNXT_PAGE_SIZE;
3455 rmem->pg_arr = ctx_pg->ctx_pg_arr;
3456 rmem->dma_arr = ctx_pg->ctx_dma_arr;
3457 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3459 valid_bits = PTU_PTE_VALID;
3461 if (rmem->nr_pages > 1) {
3462 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_pg_tbl%s_%x",
3464 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3465 mz = rte_memzone_lookup(mz_name);
3467 mz = rte_memzone_reserve_aligned(mz_name,
3471 RTE_MEMZONE_SIZE_HINT_ONLY |
3472 RTE_MEMZONE_IOVA_CONTIG,
3478 memset(mz->addr, 0, mz->len);
3479 mz_phys_addr = mz->iova;
3480 if ((unsigned long)mz->addr == mz_phys_addr) {
3481 PMD_DRV_LOG(WARNING,
3482 "Memzone physical address same as virtual.\n");
3483 PMD_DRV_LOG(WARNING,
3484 "Using rte_mem_virt2iova()\n");
3485 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3486 if (mz_phys_addr == RTE_BAD_IOVA) {
3488 "unable to map addr to phys memory\n");
3492 rte_mem_lock_page(((char *)mz->addr));
3494 rmem->pg_tbl = mz->addr;
3495 rmem->pg_tbl_map = mz_phys_addr;
3496 rmem->pg_tbl_mz = mz;
3499 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x", suffix, idx);
3500 mz = rte_memzone_lookup(mz_name);
3502 mz = rte_memzone_reserve_aligned(mz_name,
3506 RTE_MEMZONE_SIZE_HINT_ONLY |
3507 RTE_MEMZONE_IOVA_CONTIG,
3513 memset(mz->addr, 0, mz->len);
3514 mz_phys_addr = mz->iova;
3515 if ((unsigned long)mz->addr == mz_phys_addr) {
3516 PMD_DRV_LOG(WARNING,
3517 "Memzone physical address same as virtual.\n");
3518 PMD_DRV_LOG(WARNING,
3519 "Using rte_mem_virt2iova()\n");
3520 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
3521 rte_mem_lock_page(((char *)mz->addr) + sz);
3522 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3523 if (mz_phys_addr == RTE_BAD_IOVA) {
3525 "unable to map addr to phys memory\n");
3530 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
3531 rte_mem_lock_page(((char *)mz->addr) + sz);
3532 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
3533 rmem->dma_arr[i] = mz_phys_addr + sz;
3535 if (rmem->nr_pages > 1) {
3536 if (i == rmem->nr_pages - 2 &&
3537 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3538 valid_bits |= PTU_PTE_NEXT_TO_LAST;
3539 else if (i == rmem->nr_pages - 1 &&
3540 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3541 valid_bits |= PTU_PTE_LAST;
3543 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
3549 if (rmem->vmem_size)
3550 rmem->vmem = (void **)mz->addr;
3551 rmem->dma_arr[0] = mz_phys_addr;
3555 static void bnxt_free_ctx_mem(struct bnxt *bp)
3559 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
3562 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
3563 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
3564 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
3565 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
3566 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
3567 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
3568 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
3569 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
3570 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
3571 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
3572 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
3574 for (i = 0; i < BNXT_MAX_Q; i++) {
3575 if (bp->ctx->tqm_mem[i])
3576 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
3583 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
3585 #define min_t(type, x, y) ({ \
3586 type __min1 = (x); \
3587 type __min2 = (y); \
3588 __min1 < __min2 ? __min1 : __min2; })
3590 #define max_t(type, x, y) ({ \
3591 type __max1 = (x); \
3592 type __max2 = (y); \
3593 __max1 > __max2 ? __max1 : __max2; })
3595 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
3597 int bnxt_alloc_ctx_mem(struct bnxt *bp)
3599 struct bnxt_ctx_pg_info *ctx_pg;
3600 struct bnxt_ctx_mem_info *ctx;
3601 uint32_t mem_size, ena, entries;
3604 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
3606 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
3610 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
3613 ctx_pg = &ctx->qp_mem;
3614 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
3615 mem_size = ctx->qp_entry_size * ctx_pg->entries;
3616 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
3620 ctx_pg = &ctx->srq_mem;
3621 ctx_pg->entries = ctx->srq_max_l2_entries;
3622 mem_size = ctx->srq_entry_size * ctx_pg->entries;
3623 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
3627 ctx_pg = &ctx->cq_mem;
3628 ctx_pg->entries = ctx->cq_max_l2_entries;
3629 mem_size = ctx->cq_entry_size * ctx_pg->entries;
3630 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
3634 ctx_pg = &ctx->vnic_mem;
3635 ctx_pg->entries = ctx->vnic_max_vnic_entries +
3636 ctx->vnic_max_ring_table_entries;
3637 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
3638 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
3642 ctx_pg = &ctx->stat_mem;
3643 ctx_pg->entries = ctx->stat_max_entries;
3644 mem_size = ctx->stat_entry_size * ctx_pg->entries;
3645 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
3649 entries = ctx->qp_max_l2_entries;
3650 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
3651 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
3652 ctx->tqm_max_entries_per_ring);
3653 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
3654 ctx_pg = ctx->tqm_mem[i];
3655 /* use min tqm entries for now. */
3656 ctx_pg->entries = entries;
3657 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
3658 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
3661 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
3664 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
3665 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
3668 "Failed to configure context mem: rc = %d\n", rc);
3670 ctx->flags |= BNXT_CTX_FLAG_INITED;
3675 static int bnxt_alloc_stats_mem(struct bnxt *bp)
3677 struct rte_pci_device *pci_dev = bp->pdev;
3678 char mz_name[RTE_MEMZONE_NAMESIZE];
3679 const struct rte_memzone *mz = NULL;
3680 uint32_t total_alloc_len;
3681 rte_iova_t mz_phys_addr;
3683 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
3686 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3687 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3688 pci_dev->addr.bus, pci_dev->addr.devid,
3689 pci_dev->addr.function, "rx_port_stats");
3690 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3691 mz = rte_memzone_lookup(mz_name);
3693 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
3694 sizeof(struct rx_port_stats_ext) + 512);
3696 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3699 RTE_MEMZONE_SIZE_HINT_ONLY |
3700 RTE_MEMZONE_IOVA_CONTIG);
3704 memset(mz->addr, 0, mz->len);
3705 mz_phys_addr = mz->iova;
3706 if ((unsigned long)mz->addr == mz_phys_addr) {
3707 PMD_DRV_LOG(WARNING,
3708 "Memzone physical address same as virtual.\n");
3709 PMD_DRV_LOG(WARNING,
3710 "Using rte_mem_virt2iova()\n");
3711 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3712 if (mz_phys_addr == RTE_BAD_IOVA) {
3714 "Can't map address to physical memory\n");
3719 bp->rx_mem_zone = (const void *)mz;
3720 bp->hw_rx_port_stats = mz->addr;
3721 bp->hw_rx_port_stats_map = mz_phys_addr;
3723 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3724 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3725 pci_dev->addr.bus, pci_dev->addr.devid,
3726 pci_dev->addr.function, "tx_port_stats");
3727 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3728 mz = rte_memzone_lookup(mz_name);
3730 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
3731 sizeof(struct tx_port_stats_ext) + 512);
3733 mz = rte_memzone_reserve(mz_name,
3737 RTE_MEMZONE_SIZE_HINT_ONLY |
3738 RTE_MEMZONE_IOVA_CONTIG);
3742 memset(mz->addr, 0, mz->len);
3743 mz_phys_addr = mz->iova;
3744 if ((unsigned long)mz->addr == mz_phys_addr) {
3745 PMD_DRV_LOG(WARNING,
3746 "Memzone physical address same as virtual\n");
3747 PMD_DRV_LOG(WARNING,
3748 "Using rte_mem_virt2iova()\n");
3749 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3750 if (mz_phys_addr == RTE_BAD_IOVA) {
3752 "Can't map address to physical memory\n");
3757 bp->tx_mem_zone = (const void *)mz;
3758 bp->hw_tx_port_stats = mz->addr;
3759 bp->hw_tx_port_stats_map = mz_phys_addr;
3760 bp->flags |= BNXT_FLAG_PORT_STATS;
3762 /* Display extended statistics if FW supports it */
3763 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
3764 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
3765 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
3768 bp->hw_rx_port_stats_ext = (void *)
3769 ((uint8_t *)bp->hw_rx_port_stats +
3770 sizeof(struct rx_port_stats));
3771 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
3772 sizeof(struct rx_port_stats);
3773 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
3775 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
3776 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
3777 bp->hw_tx_port_stats_ext = (void *)
3778 ((uint8_t *)bp->hw_tx_port_stats +
3779 sizeof(struct tx_port_stats));
3780 bp->hw_tx_port_stats_ext_map =
3781 bp->hw_tx_port_stats_map +
3782 sizeof(struct tx_port_stats);
3783 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
3789 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
3791 struct bnxt *bp = eth_dev->data->dev_private;
3794 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3795 RTE_ETHER_ADDR_LEN *
3798 if (eth_dev->data->mac_addrs == NULL) {
3799 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
3803 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
3807 /* Generate a random MAC address, if none was assigned by PF */
3808 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
3809 bnxt_eth_hw_addr_random(bp->mac_addr);
3811 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
3812 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
3813 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
3815 rc = bnxt_hwrm_set_mac(bp);
3817 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
3818 RTE_ETHER_ADDR_LEN);
3822 /* Copy the permanent MAC from the FUNC_QCAPS response */
3823 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
3824 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
3829 #define ALLOW_FUNC(x) \
3831 uint32_t arg = (x); \
3832 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3833 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3836 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3838 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3839 static int version_printed;
3844 if (version_printed++ == 0)
3845 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3847 rte_eth_copy_pci_info(eth_dev, pci_dev);
3849 bp = eth_dev->data->dev_private;
3851 bp->dev_stopped = 1;
3853 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3856 if (bnxt_vf_pciid(pci_dev->id.device_id))
3857 bp->flags |= BNXT_FLAG_VF;
3859 if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
3860 pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
3861 pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
3862 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF)
3863 bp->flags |= BNXT_FLAG_THOR_CHIP;
3865 rc = bnxt_init_board(eth_dev);
3868 "Board initialization failed rc: %x\n", rc);
3872 eth_dev->dev_ops = &bnxt_dev_ops;
3873 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3874 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3875 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3878 rc = bnxt_alloc_hwrm_resources(bp);
3881 "hwrm resource allocation failure rc: %x\n", rc);
3884 rc = bnxt_hwrm_ver_get(bp);
3888 rc = bnxt_hwrm_func_reset(bp);
3890 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3895 rc = bnxt_hwrm_queue_qportcfg(bp);
3897 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3900 /* Get the MAX capabilities for this function */
3901 rc = bnxt_hwrm_func_qcaps(bp);
3903 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3907 rc = bnxt_alloc_stats_mem(bp);
3911 if (bp->max_tx_rings == 0) {
3912 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3917 rc = bnxt_setup_mac_addr(eth_dev);
3921 /* THOR does not support ring groups.
3922 * But we will use the array to save RSS context IDs.
3924 if (BNXT_CHIP_THOR(bp)) {
3925 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
3926 } else if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3927 /* 1 ring is for default completion ring */
3928 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3933 if (BNXT_HAS_RING_GRPS(bp)) {
3934 bp->grp_info = rte_zmalloc("bnxt_grp_info",
3935 sizeof(*bp->grp_info) *
3936 bp->max_ring_grps, 0);
3937 if (!bp->grp_info) {
3939 "Failed to alloc %zu bytes for grp info tbl.\n",
3940 sizeof(*bp->grp_info) * bp->max_ring_grps);
3946 /* Forward all requests if firmware is new enough */
3947 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3948 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3949 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3950 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3952 PMD_DRV_LOG(WARNING,
3953 "Firmware too old for VF mailbox functionality\n");
3954 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3958 * The following are used for driver cleanup. If we disallow these,
3959 * VF drivers can't clean up cleanly.
3961 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3962 ALLOW_FUNC(HWRM_VNIC_FREE);
3963 ALLOW_FUNC(HWRM_RING_FREE);
3964 ALLOW_FUNC(HWRM_RING_GRP_FREE);
3965 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3966 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3967 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3968 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3969 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3970 rc = bnxt_hwrm_func_driver_register(bp);
3973 "Failed to register driver");
3979 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3980 pci_dev->mem_resource[0].phys_addr,
3981 pci_dev->mem_resource[0].addr);
3983 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
3985 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3989 if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
3990 mtu != eth_dev->data->mtu)
3991 eth_dev->data->mtu = mtu;
3994 //if (bp->pf.active_vfs) {
3995 // TODO: Deallocate VF resources?
3997 if (bp->pdev->max_vfs) {
3998 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4000 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4004 rc = bnxt_hwrm_allocate_pf_only(bp);
4007 "Failed to allocate PF resources\n");
4013 bnxt_hwrm_port_led_qcaps(bp);
4015 rc = bnxt_setup_int(bp);
4019 rc = bnxt_alloc_mem(bp);
4021 goto error_free_int;
4023 rc = bnxt_request_int(bp);
4025 goto error_free_int;
4032 bnxt_disable_int(bp);
4033 bnxt_hwrm_func_buf_unrgtr(bp);
4037 bnxt_dev_uninit(eth_dev);
4043 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4045 struct bnxt *bp = eth_dev->data->dev_private;
4048 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4051 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4052 bnxt_disable_int(bp);
4055 if (bp->grp_info != NULL) {
4056 rte_free(bp->grp_info);
4057 bp->grp_info = NULL;
4059 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4060 bnxt_free_hwrm_resources(bp);
4062 if (bp->tx_mem_zone) {
4063 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4064 bp->tx_mem_zone = NULL;
4067 if (bp->rx_mem_zone) {
4068 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4069 bp->rx_mem_zone = NULL;
4072 if (bp->dev_stopped == 0)
4073 bnxt_dev_close_op(eth_dev);
4075 rte_free(bp->pf.vf_info);
4076 bnxt_free_ctx_mem(bp);
4077 eth_dev->dev_ops = NULL;
4078 eth_dev->rx_pkt_burst = NULL;
4079 eth_dev->tx_pkt_burst = NULL;
4084 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4085 struct rte_pci_device *pci_dev)
4087 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4091 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4093 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4094 return rte_eth_dev_pci_generic_remove(pci_dev,
4097 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4100 static struct rte_pci_driver bnxt_rte_pmd = {
4101 .id_table = bnxt_pci_id_map,
4102 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4103 .probe = bnxt_pci_probe,
4104 .remove = bnxt_pci_remove,
4108 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4110 if (strcmp(dev->device->driver->name, drv->driver.name))
4116 bool is_bnxt_supported(struct rte_eth_dev *dev)
4118 return is_device_supported(dev, &bnxt_rte_pmd);
4121 RTE_INIT(bnxt_init_log)
4123 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4124 if (bnxt_logtype_driver >= 0)
4125 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4128 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4129 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4130 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");