4 * Copyright(c) Broadcom Limited.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include <rte_ethdev.h>
39 #include <rte_ethdev_pci.h>
40 #include <rte_malloc.h>
41 #include <rte_cycles.h>
45 #include "bnxt_filter.h"
46 #include "bnxt_hwrm.h"
48 #include "bnxt_ring.h"
51 #include "bnxt_stats.h"
54 #include "bnxt_vnic.h"
55 #include "hsi_struct_def_dpdk.h"
57 #define DRV_MODULE_NAME "bnxt"
58 static const char bnxt_version[] =
59 "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
61 #define PCI_VENDOR_ID_BROADCOM 0x14E4
63 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
64 #define BROADCOM_DEV_ID_57414_VF 0x16c1
65 #define BROADCOM_DEV_ID_57301 0x16c8
66 #define BROADCOM_DEV_ID_57302 0x16c9
67 #define BROADCOM_DEV_ID_57304_PF 0x16ca
68 #define BROADCOM_DEV_ID_57304_VF 0x16cb
69 #define BROADCOM_DEV_ID_57417_MF 0x16cc
70 #define BROADCOM_DEV_ID_NS2 0x16cd
71 #define BROADCOM_DEV_ID_57311 0x16ce
72 #define BROADCOM_DEV_ID_57312 0x16cf
73 #define BROADCOM_DEV_ID_57402 0x16d0
74 #define BROADCOM_DEV_ID_57404 0x16d1
75 #define BROADCOM_DEV_ID_57406_PF 0x16d2
76 #define BROADCOM_DEV_ID_57406_VF 0x16d3
77 #define BROADCOM_DEV_ID_57402_MF 0x16d4
78 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
79 #define BROADCOM_DEV_ID_57412 0x16d6
80 #define BROADCOM_DEV_ID_57414 0x16d7
81 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
82 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
83 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
84 #define BROADCOM_DEV_ID_57412_MF 0x16de
85 #define BROADCOM_DEV_ID_57314 0x16df
86 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
87 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
88 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
89 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
90 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
91 #define BROADCOM_DEV_ID_57404_MF 0x16e7
92 #define BROADCOM_DEV_ID_57406_MF 0x16e8
93 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
94 #define BROADCOM_DEV_ID_57407_MF 0x16ea
95 #define BROADCOM_DEV_ID_57414_MF 0x16ec
96 #define BROADCOM_DEV_ID_57416_MF 0x16ee
98 static const struct rte_pci_id bnxt_pci_id_map[] = {
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
130 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
131 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
132 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
133 { .vendor_id = 0, /* sentinel */ },
136 #define BNXT_ETH_RSS_SUPPORT ( \
138 ETH_RSS_NONFRAG_IPV4_TCP | \
139 ETH_RSS_NONFRAG_IPV4_UDP | \
141 ETH_RSS_NONFRAG_IPV6_TCP | \
142 ETH_RSS_NONFRAG_IPV6_UDP)
144 static void bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
145 /***********************/
148 * High level utility functions
151 static void bnxt_free_mem(struct bnxt *bp)
153 bnxt_free_filter_mem(bp);
154 bnxt_free_vnic_attributes(bp);
155 bnxt_free_vnic_mem(bp);
158 bnxt_free_tx_rings(bp);
159 bnxt_free_rx_rings(bp);
160 bnxt_free_def_cp_ring(bp);
163 static int bnxt_alloc_mem(struct bnxt *bp)
167 /* Default completion ring */
168 rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
172 rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
173 bp->def_cp_ring, "def_cp");
177 rc = bnxt_alloc_vnic_mem(bp);
181 rc = bnxt_alloc_vnic_attributes(bp);
185 rc = bnxt_alloc_filter_mem(bp);
196 static int bnxt_init_chip(struct bnxt *bp)
198 unsigned int i, rss_idx, fw_idx;
199 struct rte_eth_link new;
202 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
204 RTE_LOG(ERR, PMD, "HWRM stat ctx alloc failure rc: %x\n", rc);
208 rc = bnxt_alloc_hwrm_rings(bp);
210 RTE_LOG(ERR, PMD, "HWRM ring alloc failure rc: %x\n", rc);
214 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
216 RTE_LOG(ERR, PMD, "HWRM ring grp alloc failure: %x\n", rc);
220 rc = bnxt_mq_rx_configure(bp);
222 RTE_LOG(ERR, PMD, "MQ mode configure failure rc: %x\n", rc);
226 /* VNIC configuration */
227 for (i = 0; i < bp->nr_vnics; i++) {
228 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
230 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
232 RTE_LOG(ERR, PMD, "HWRM vnic %d alloc failure rc: %x\n",
237 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
240 "HWRM vnic %d ctx alloc failure rc: %x\n",
245 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
247 RTE_LOG(ERR, PMD, "HWRM vnic %d cfg failure rc: %x\n",
252 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
255 "HWRM vnic %d filter failure rc: %x\n",
259 if (vnic->rss_table && vnic->hash_type) {
261 * Fill the RSS hash & redirection table with
262 * ring group ids for all VNICs
264 for (rss_idx = 0, fw_idx = 0;
265 rss_idx < HW_HASH_INDEX_SIZE;
266 rss_idx++, fw_idx++) {
267 if (vnic->fw_grp_ids[fw_idx] ==
270 vnic->rss_table[rss_idx] =
271 vnic->fw_grp_ids[fw_idx];
273 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
276 "HWRM vnic %d set RSS failure rc: %x\n",
282 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0]);
285 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
289 rc = bnxt_get_hwrm_link_config(bp, &new);
291 RTE_LOG(ERR, PMD, "HWRM Get link config failure rc: %x\n", rc);
295 if (!bp->link_info.link_up) {
296 rc = bnxt_set_hwrm_link_config(bp, true);
299 "HWRM link config failure rc: %x\n", rc);
307 bnxt_free_all_hwrm_resources(bp);
312 static int bnxt_shutdown_nic(struct bnxt *bp)
314 bnxt_free_all_hwrm_resources(bp);
315 bnxt_free_all_filters(bp);
316 bnxt_free_all_vnics(bp);
320 static int bnxt_init_nic(struct bnxt *bp)
324 bnxt_init_ring_grps(bp);
326 bnxt_init_filters(bp);
328 rc = bnxt_init_chip(bp);
336 * Device configuration and status function
339 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
340 struct rte_eth_dev_info *dev_info)
342 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
343 uint16_t max_vnics, i, j, vpool, vrxq;
345 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
348 dev_info->max_mac_addrs = MAX_NUM_MAC_ADDR;
349 dev_info->max_hash_mac_addrs = 0;
351 /* PF/VF specifics */
353 dev_info->max_vfs = bp->pdev->max_vfs;
354 dev_info->max_rx_queues = bp->max_rx_rings;
355 dev_info->max_tx_queues = bp->max_tx_rings;
356 dev_info->reta_size = bp->max_rsscos_ctx;
357 max_vnics = bp->max_vnics;
359 /* Fast path specifics */
360 dev_info->min_rx_bufsize = 1;
361 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
363 dev_info->rx_offload_capa = 0;
364 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
365 DEV_TX_OFFLOAD_TCP_CKSUM |
366 DEV_TX_OFFLOAD_UDP_CKSUM |
367 DEV_TX_OFFLOAD_TCP_TSO |
368 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
369 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
370 DEV_TX_OFFLOAD_GRE_TNL_TSO |
371 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
372 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
375 dev_info->default_rxconf = (struct rte_eth_rxconf) {
381 .rx_free_thresh = 32,
385 dev_info->default_txconf = (struct rte_eth_txconf) {
391 .tx_free_thresh = 32,
393 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
394 ETH_TXQ_FLAGS_NOOFFLOADS,
396 eth_dev->data->dev_conf.intr_conf.lsc = 1;
401 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
402 * need further investigation.
406 vpool = 64; /* ETH_64_POOLS */
407 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
408 for (i = 0; i < 4; vpool >>= 1, i++) {
409 if (max_vnics > vpool) {
410 for (j = 0; j < 5; vrxq >>= 1, j++) {
411 if (dev_info->max_rx_queues > vrxq) {
417 /* Not enough resources to support VMDq */
421 /* Not enough resources to support VMDq */
425 dev_info->max_vmdq_pools = vpool;
426 dev_info->vmdq_queue_num = vrxq;
428 dev_info->vmdq_pool_base = 0;
429 dev_info->vmdq_queue_base = 0;
432 /* Configure the device based on the configuration provided */
433 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
435 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
437 bp->rx_queues = (void *)eth_dev->data->rx_queues;
438 bp->tx_queues = (void *)eth_dev->data->tx_queues;
440 /* Inherit new configurations */
441 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
442 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
443 bp->rx_cp_nr_rings = bp->rx_nr_rings;
444 bp->tx_cp_nr_rings = bp->tx_nr_rings;
446 if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
448 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
449 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
454 rte_bnxt_atomic_write_link_status(struct rte_eth_dev *eth_dev,
455 struct rte_eth_link *link)
457 struct rte_eth_link *dst = ð_dev->data->dev_link;
458 struct rte_eth_link *src = link;
460 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
461 *(uint64_t *)src) == 0)
467 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
469 struct rte_eth_link *link = ð_dev->data->dev_link;
471 if (link->link_status)
472 RTE_LOG(INFO, PMD, "Port %d Link Up - speed %u Mbps - %s\n",
473 (uint8_t)(eth_dev->data->port_id),
474 (uint32_t)link->link_speed,
475 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
476 ("full-duplex") : ("half-duplex\n"));
478 RTE_LOG(INFO, PMD, "Port %d Link Down\n",
479 (uint8_t)(eth_dev->data->port_id));
482 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
484 bnxt_print_link_info(eth_dev);
488 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
490 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
496 rc = bnxt_init_nic(bp);
500 bnxt_link_update_op(eth_dev, 0);
502 if (eth_dev->data->dev_conf.rxmode.hw_vlan_filter)
503 vlan_mask |= ETH_VLAN_FILTER_MASK;
504 if (eth_dev->data->dev_conf.rxmode.hw_vlan_strip)
505 vlan_mask |= ETH_VLAN_STRIP_MASK;
506 bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
511 bnxt_shutdown_nic(bp);
512 bnxt_free_tx_mbufs(bp);
513 bnxt_free_rx_mbufs(bp);
517 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
519 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
521 eth_dev->data->dev_link.link_status = 1;
522 bnxt_set_hwrm_link_config(bp, true);
526 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
528 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
530 eth_dev->data->dev_link.link_status = 0;
531 bnxt_set_hwrm_link_config(bp, false);
535 /* Unload the driver, release resources */
536 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
538 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
540 if (bp->eth_dev->data->dev_started) {
541 /* TBD: STOP HW queues DMA */
542 eth_dev->data->dev_link.link_status = 0;
544 bnxt_set_hwrm_link_config(bp, false);
545 bnxt_hwrm_port_clr_stats(bp);
546 bnxt_shutdown_nic(bp);
550 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
552 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
554 if (bp->dev_stopped == 0)
555 bnxt_dev_stop_op(eth_dev);
557 bnxt_free_tx_mbufs(bp);
558 bnxt_free_rx_mbufs(bp);
560 if (eth_dev->data->mac_addrs != NULL) {
561 rte_free(eth_dev->data->mac_addrs);
562 eth_dev->data->mac_addrs = NULL;
564 if (bp->grp_info != NULL) {
565 rte_free(bp->grp_info);
570 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
573 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
574 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
575 struct bnxt_vnic_info *vnic;
576 struct bnxt_filter_info *filter, *temp_filter;
580 * Loop through all VNICs from the specified filter flow pools to
581 * remove the corresponding MAC addr filter
583 for (i = 0; i < MAX_FF_POOLS; i++) {
584 if (!(pool_mask & (1ULL << i)))
587 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
588 filter = STAILQ_FIRST(&vnic->filter);
590 temp_filter = STAILQ_NEXT(filter, next);
591 if (filter->mac_index == index) {
592 STAILQ_REMOVE(&vnic->filter, filter,
593 bnxt_filter_info, next);
594 bnxt_hwrm_clear_filter(bp, filter);
595 filter->mac_index = INVALID_MAC_INDEX;
596 memset(&filter->l2_addr, 0,
599 &bp->free_filter_list,
602 filter = temp_filter;
608 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
609 struct ether_addr *mac_addr,
610 uint32_t index, uint32_t pool)
612 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
613 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
614 struct bnxt_filter_info *filter;
617 RTE_LOG(ERR, PMD, "Cannot add MAC address to a VF interface\n");
622 RTE_LOG(ERR, PMD, "VNIC not found for pool %d!\n", pool);
625 /* Attach requested MAC address to the new l2_filter */
626 STAILQ_FOREACH(filter, &vnic->filter, next) {
627 if (filter->mac_index == index) {
629 "MAC addr already existed for pool %d\n", pool);
633 filter = bnxt_alloc_filter(bp);
635 RTE_LOG(ERR, PMD, "L2 filter alloc failed\n");
638 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
639 filter->mac_index = index;
640 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
641 return bnxt_hwrm_set_filter(bp, vnic, filter);
644 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
647 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
648 struct rte_eth_link new;
649 unsigned int cnt = BNXT_LINK_WAIT_CNT;
651 memset(&new, 0, sizeof(new));
653 /* Retrieve link info from hardware */
654 rc = bnxt_get_hwrm_link_config(bp, &new);
656 new.link_speed = ETH_LINK_SPEED_100M;
657 new.link_duplex = ETH_LINK_FULL_DUPLEX;
659 "Failed to retrieve link rc = 0x%x!\n", rc);
662 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
664 if (!wait_to_complete)
666 } while (!new.link_status && cnt--);
669 /* Timed out or success */
670 if (new.link_status != eth_dev->data->dev_link.link_status ||
671 new.link_speed != eth_dev->data->dev_link.link_speed) {
672 rte_bnxt_atomic_write_link_status(eth_dev, &new);
673 bnxt_print_link_info(eth_dev);
679 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
681 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
682 struct bnxt_vnic_info *vnic;
684 if (bp->vnic_info == NULL)
687 vnic = &bp->vnic_info[0];
689 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
690 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
693 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
695 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
696 struct bnxt_vnic_info *vnic;
698 if (bp->vnic_info == NULL)
701 vnic = &bp->vnic_info[0];
703 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
704 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
707 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
709 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
710 struct bnxt_vnic_info *vnic;
712 if (bp->vnic_info == NULL)
715 vnic = &bp->vnic_info[0];
717 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
718 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
721 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
723 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
724 struct bnxt_vnic_info *vnic;
726 if (bp->vnic_info == NULL)
729 vnic = &bp->vnic_info[0];
731 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
732 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
735 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
736 struct rte_eth_rss_reta_entry64 *reta_conf,
739 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
740 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
741 struct bnxt_vnic_info *vnic;
744 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
747 if (reta_size != HW_HASH_INDEX_SIZE) {
748 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
749 "(%d) must equal the size supported by the hardware "
750 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
753 /* Update the RSS VNIC(s) */
754 for (i = 0; i < MAX_FF_POOLS; i++) {
755 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
756 memcpy(vnic->rss_table, reta_conf, reta_size);
758 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
764 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
765 struct rte_eth_rss_reta_entry64 *reta_conf,
768 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
769 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
770 struct rte_intr_handle *intr_handle
771 = &bp->pdev->intr_handle;
773 /* Retrieve from the default VNIC */
776 if (!vnic->rss_table)
779 if (reta_size != HW_HASH_INDEX_SIZE) {
780 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
781 "(%d) must equal the size supported by the hardware "
782 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
785 /* EW - need to revisit here copying from u64 to u16 */
786 memcpy(reta_conf, vnic->rss_table, reta_size);
788 if (rte_intr_allow_others(intr_handle)) {
789 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
790 bnxt_dev_lsc_intr_setup(eth_dev);
796 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
797 struct rte_eth_rss_conf *rss_conf)
799 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
800 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
801 struct bnxt_vnic_info *vnic;
802 uint16_t hash_type = 0;
806 * If RSS enablement were different than dev_configure,
807 * then return -EINVAL
809 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
810 if (!rss_conf->rss_hf)
813 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
816 if (rss_conf->rss_hf & ETH_RSS_IPV4)
817 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
818 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
819 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
820 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
821 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
822 if (rss_conf->rss_hf & ETH_RSS_IPV6)
823 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
824 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
825 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
826 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
827 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
829 /* Update the RSS VNIC(s) */
830 for (i = 0; i < MAX_FF_POOLS; i++) {
831 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
832 vnic->hash_type = hash_type;
835 * Use the supplied key if the key length is
836 * acceptable and the rss_key is not NULL
838 if (rss_conf->rss_key &&
839 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
840 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
841 rss_conf->rss_key_len);
843 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
849 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
850 struct rte_eth_rss_conf *rss_conf)
852 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
853 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
857 /* RSS configuration is the same for all VNICs */
858 if (vnic && vnic->rss_hash_key) {
859 if (rss_conf->rss_key) {
860 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
861 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
862 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
865 hash_types = vnic->hash_type;
866 rss_conf->rss_hf = 0;
867 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
868 rss_conf->rss_hf |= ETH_RSS_IPV4;
869 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
871 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
872 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
874 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
876 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
877 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
879 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
881 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
882 rss_conf->rss_hf |= ETH_RSS_IPV6;
883 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
885 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
886 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
888 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
890 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
891 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
893 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
897 "Unknwon RSS config from firmware (%08x), RSS disabled",
902 rss_conf->rss_hf = 0;
907 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
908 struct rte_eth_fc_conf *fc_conf)
910 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
911 struct rte_eth_link link_info;
914 rc = bnxt_get_hwrm_link_config(bp, &link_info);
918 memset(fc_conf, 0, sizeof(*fc_conf));
919 if (bp->link_info.auto_pause)
920 fc_conf->autoneg = 1;
921 switch (bp->link_info.pause) {
923 fc_conf->mode = RTE_FC_NONE;
925 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
926 fc_conf->mode = RTE_FC_TX_PAUSE;
928 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
929 fc_conf->mode = RTE_FC_RX_PAUSE;
931 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
932 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
933 fc_conf->mode = RTE_FC_FULL;
939 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
940 struct rte_eth_fc_conf *fc_conf)
942 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
944 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp)) {
945 RTE_LOG(ERR, PMD, "Flow Control Settings cannot be modified\n");
949 switch (fc_conf->mode) {
951 bp->link_info.auto_pause = 0;
952 bp->link_info.force_pause = 0;
954 case RTE_FC_RX_PAUSE:
955 if (fc_conf->autoneg) {
956 bp->link_info.auto_pause =
957 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
958 bp->link_info.force_pause = 0;
960 bp->link_info.auto_pause = 0;
961 bp->link_info.force_pause =
962 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
965 case RTE_FC_TX_PAUSE:
966 if (fc_conf->autoneg) {
967 bp->link_info.auto_pause =
968 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
969 bp->link_info.force_pause = 0;
971 bp->link_info.auto_pause = 0;
972 bp->link_info.force_pause =
973 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
977 if (fc_conf->autoneg) {
978 bp->link_info.auto_pause =
979 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
980 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
981 bp->link_info.force_pause = 0;
983 bp->link_info.auto_pause = 0;
984 bp->link_info.force_pause =
985 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
986 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
990 return bnxt_set_hwrm_link_config(bp, true);
993 /* Add UDP tunneling port */
995 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
996 struct rte_eth_udp_tunnel *udp_tunnel)
998 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
999 uint16_t tunnel_type = 0;
1002 switch (udp_tunnel->prot_type) {
1003 case RTE_TUNNEL_TYPE_VXLAN:
1004 if (bp->vxlan_port_cnt) {
1005 RTE_LOG(ERR, PMD, "Tunnel Port %d already programmed\n",
1006 udp_tunnel->udp_port);
1007 if (bp->vxlan_port != udp_tunnel->udp_port) {
1008 RTE_LOG(ERR, PMD, "Only one port allowed\n");
1011 bp->vxlan_port_cnt++;
1015 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1016 bp->vxlan_port_cnt++;
1018 case RTE_TUNNEL_TYPE_GENEVE:
1019 if (bp->geneve_port_cnt) {
1020 RTE_LOG(ERR, PMD, "Tunnel Port %d already programmed\n",
1021 udp_tunnel->udp_port);
1022 if (bp->geneve_port != udp_tunnel->udp_port) {
1023 RTE_LOG(ERR, PMD, "Only one port allowed\n");
1026 bp->geneve_port_cnt++;
1030 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1031 bp->geneve_port_cnt++;
1034 RTE_LOG(ERR, PMD, "Tunnel type is not supported\n");
1037 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1043 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1044 struct rte_eth_udp_tunnel *udp_tunnel)
1046 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1047 uint16_t tunnel_type = 0;
1051 switch (udp_tunnel->prot_type) {
1052 case RTE_TUNNEL_TYPE_VXLAN:
1053 if (!bp->vxlan_port_cnt) {
1054 RTE_LOG(ERR, PMD, "No Tunnel port configured yet\n");
1057 if (bp->vxlan_port != udp_tunnel->udp_port) {
1058 RTE_LOG(ERR, PMD, "Req Port: %d. Configured port: %d\n",
1059 udp_tunnel->udp_port, bp->vxlan_port);
1062 if (--bp->vxlan_port_cnt)
1066 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1067 port = bp->vxlan_fw_dst_port_id;
1069 case RTE_TUNNEL_TYPE_GENEVE:
1070 if (!bp->geneve_port_cnt) {
1071 RTE_LOG(ERR, PMD, "No Tunnel port configured yet\n");
1074 if (bp->geneve_port != udp_tunnel->udp_port) {
1075 RTE_LOG(ERR, PMD, "Req Port: %d. Configured port: %d\n",
1076 udp_tunnel->udp_port, bp->geneve_port);
1079 if (--bp->geneve_port_cnt)
1083 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1084 port = bp->geneve_fw_dst_port_id;
1087 RTE_LOG(ERR, PMD, "Tunnel type is not supported\n");
1091 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1094 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1097 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1098 bp->geneve_port = 0;
1103 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1105 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1106 struct bnxt_vnic_info *vnic;
1109 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1111 /* Cycle through all VNICs */
1112 for (i = 0; i < bp->nr_vnics; i++) {
1114 * For each VNIC and each associated filter(s)
1115 * if VLAN exists && VLAN matches vlan_id
1116 * remove the MAC+VLAN filter
1117 * add a new MAC only filter
1119 * VLAN filter doesn't exist, just skip and continue
1121 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1122 filter = STAILQ_FIRST(&vnic->filter);
1124 temp_filter = STAILQ_NEXT(filter, next);
1126 if (filter->enables & chk &&
1127 filter->l2_ovlan == vlan_id) {
1128 /* Must delete the filter */
1129 STAILQ_REMOVE(&vnic->filter, filter,
1130 bnxt_filter_info, next);
1131 bnxt_hwrm_clear_filter(bp, filter);
1133 &bp->free_filter_list,
1137 * Need to examine to see if the MAC
1138 * filter already existed or not before
1139 * allocating a new one
1142 new_filter = bnxt_alloc_filter(bp);
1145 "MAC/VLAN filter alloc failed\n");
1149 STAILQ_INSERT_TAIL(&vnic->filter,
1151 /* Inherit MAC from previous filter */
1152 new_filter->mac_index =
1154 memcpy(new_filter->l2_addr,
1155 filter->l2_addr, ETHER_ADDR_LEN);
1156 /* MAC only filter */
1157 rc = bnxt_hwrm_set_filter(bp,
1163 "Del Vlan filter for %d\n",
1166 filter = temp_filter;
1174 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1176 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1177 struct bnxt_vnic_info *vnic;
1180 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN |
1181 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK;
1182 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1184 /* Cycle through all VNICs */
1185 for (i = 0; i < bp->nr_vnics; i++) {
1187 * For each VNIC and each associated filter(s)
1189 * if VLAN matches vlan_id
1190 * VLAN filter already exists, just skip and continue
1192 * add a new MAC+VLAN filter
1194 * Remove the old MAC only filter
1195 * Add a new MAC+VLAN filter
1197 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1198 filter = STAILQ_FIRST(&vnic->filter);
1200 temp_filter = STAILQ_NEXT(filter, next);
1202 if (filter->enables & chk) {
1203 if (filter->l2_ovlan == vlan_id)
1206 /* Must delete the MAC filter */
1207 STAILQ_REMOVE(&vnic->filter, filter,
1208 bnxt_filter_info, next);
1209 bnxt_hwrm_clear_filter(bp, filter);
1210 filter->l2_ovlan = 0;
1212 &bp->free_filter_list,
1215 new_filter = bnxt_alloc_filter(bp);
1218 "MAC/VLAN filter alloc failed\n");
1222 STAILQ_INSERT_TAIL(&vnic->filter, new_filter,
1224 /* Inherit MAC from the previous filter */
1225 new_filter->mac_index = filter->mac_index;
1226 memcpy(new_filter->l2_addr, filter->l2_addr,
1228 /* MAC + VLAN ID filter */
1229 new_filter->l2_ovlan = vlan_id;
1230 new_filter->l2_ovlan_mask = 0xF000;
1231 new_filter->enables |= en;
1232 rc = bnxt_hwrm_set_filter(bp, vnic,
1237 "Added Vlan filter for %d\n", vlan_id);
1239 filter = temp_filter;
1247 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1248 uint16_t vlan_id, int on)
1250 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1252 /* These operations apply to ALL existing MAC/VLAN filters */
1254 return bnxt_add_vlan_filter(bp, vlan_id);
1256 return bnxt_del_vlan_filter(bp, vlan_id);
1260 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1262 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1265 if (mask & ETH_VLAN_FILTER_MASK) {
1266 if (!dev->data->dev_conf.rxmode.hw_vlan_filter) {
1267 /* Remove any VLAN filters programmed */
1268 for (i = 0; i < 4095; i++)
1269 bnxt_del_vlan_filter(bp, i);
1271 RTE_LOG(INFO, PMD, "VLAN Filtering: %d\n",
1272 dev->data->dev_conf.rxmode.hw_vlan_filter);
1275 if (mask & ETH_VLAN_STRIP_MASK) {
1276 /* Enable or disable VLAN stripping */
1277 for (i = 0; i < bp->nr_vnics; i++) {
1278 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1279 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1280 vnic->vlan_strip = true;
1282 vnic->vlan_strip = false;
1283 bnxt_hwrm_vnic_cfg(bp, vnic);
1285 RTE_LOG(INFO, PMD, "VLAN Strip Offload: %d\n",
1286 dev->data->dev_conf.rxmode.hw_vlan_strip);
1289 if (mask & ETH_VLAN_EXTEND_MASK)
1290 RTE_LOG(ERR, PMD, "Extend VLAN Not supported\n");
1297 static const struct eth_dev_ops bnxt_dev_ops = {
1298 .dev_infos_get = bnxt_dev_info_get_op,
1299 .dev_close = bnxt_dev_close_op,
1300 .dev_configure = bnxt_dev_configure_op,
1301 .dev_start = bnxt_dev_start_op,
1302 .dev_stop = bnxt_dev_stop_op,
1303 .dev_set_link_up = bnxt_dev_set_link_up_op,
1304 .dev_set_link_down = bnxt_dev_set_link_down_op,
1305 .stats_get = bnxt_stats_get_op,
1306 .stats_reset = bnxt_stats_reset_op,
1307 .rx_queue_setup = bnxt_rx_queue_setup_op,
1308 .rx_queue_release = bnxt_rx_queue_release_op,
1309 .tx_queue_setup = bnxt_tx_queue_setup_op,
1310 .tx_queue_release = bnxt_tx_queue_release_op,
1311 .reta_update = bnxt_reta_update_op,
1312 .reta_query = bnxt_reta_query_op,
1313 .rss_hash_update = bnxt_rss_hash_update_op,
1314 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
1315 .link_update = bnxt_link_update_op,
1316 .promiscuous_enable = bnxt_promiscuous_enable_op,
1317 .promiscuous_disable = bnxt_promiscuous_disable_op,
1318 .allmulticast_enable = bnxt_allmulticast_enable_op,
1319 .allmulticast_disable = bnxt_allmulticast_disable_op,
1320 .mac_addr_add = bnxt_mac_addr_add_op,
1321 .mac_addr_remove = bnxt_mac_addr_remove_op,
1322 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
1323 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
1324 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
1325 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
1326 .vlan_filter_set = bnxt_vlan_filter_set_op,
1327 .vlan_offload_set = bnxt_vlan_offload_set_op,
1328 .xstats_get = bnxt_dev_xstats_get_op,
1329 .xstats_get_names = bnxt_dev_xstats_get_names_op,
1330 .xstats_reset = bnxt_dev_xstats_reset_op,
1333 static bool bnxt_vf_pciid(uint16_t id)
1335 if (id == BROADCOM_DEV_ID_57304_VF ||
1336 id == BROADCOM_DEV_ID_57406_VF ||
1337 id == BROADCOM_DEV_ID_5731X_VF ||
1338 id == BROADCOM_DEV_ID_5741X_VF ||
1339 id == BROADCOM_DEV_ID_57414_VF)
1344 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
1346 struct bnxt *bp = eth_dev->data->dev_private;
1347 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1350 /* enable device (incl. PCI PM wakeup), and bus-mastering */
1351 if (!pci_dev->mem_resource[0].addr) {
1353 "Cannot find PCI device base address, aborting\n");
1355 goto init_err_disable;
1358 bp->eth_dev = eth_dev;
1361 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
1363 RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n");
1365 goto init_err_release;
1378 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
1380 #define ALLOW_FUNC(x) \
1382 typeof(x) arg = (x); \
1383 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
1384 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
1387 bnxt_dev_init(struct rte_eth_dev *eth_dev)
1389 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1390 char mz_name[RTE_MEMZONE_NAMESIZE];
1391 const struct rte_memzone *mz = NULL;
1392 static int version_printed;
1393 uint32_t total_alloc_len;
1394 phys_addr_t mz_phys_addr;
1398 if (version_printed++ == 0)
1399 RTE_LOG(INFO, PMD, "%s\n", bnxt_version);
1401 rte_eth_copy_pci_info(eth_dev, pci_dev);
1402 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1404 bp = eth_dev->data->dev_private;
1405 bp->dev_stopped = 1;
1407 if (bnxt_vf_pciid(pci_dev->id.device_id))
1408 bp->flags |= BNXT_FLAG_VF;
1410 rc = bnxt_init_board(eth_dev);
1413 "Board initialization failed rc: %x\n", rc);
1416 eth_dev->dev_ops = &bnxt_dev_ops;
1417 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
1418 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
1420 if (BNXT_PF(bp) && pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
1421 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
1422 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
1423 pci_dev->addr.bus, pci_dev->addr.devid,
1424 pci_dev->addr.function, "rx_port_stats");
1425 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
1426 mz = rte_memzone_lookup(mz_name);
1427 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
1428 sizeof(struct rx_port_stats) + 512);
1430 mz = rte_memzone_reserve(mz_name, total_alloc_len,
1433 RTE_MEMZONE_SIZE_HINT_ONLY);
1437 memset(mz->addr, 0, mz->len);
1438 mz_phys_addr = mz->phys_addr;
1439 if ((unsigned long)mz->addr == mz_phys_addr) {
1440 RTE_LOG(WARNING, PMD,
1441 "Memzone physical address same as virtual.\n");
1442 RTE_LOG(WARNING, PMD,
1443 "Using rte_mem_virt2phy()\n");
1444 mz_phys_addr = rte_mem_virt2phy(mz->addr);
1445 if (mz_phys_addr == 0) {
1447 "unable to map address to physical memory\n");
1452 bp->rx_mem_zone = (const void *)mz;
1453 bp->hw_rx_port_stats = mz->addr;
1454 bp->hw_rx_port_stats_map = mz_phys_addr;
1456 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
1457 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
1458 pci_dev->addr.bus, pci_dev->addr.devid,
1459 pci_dev->addr.function, "tx_port_stats");
1460 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
1461 mz = rte_memzone_lookup(mz_name);
1462 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
1463 sizeof(struct tx_port_stats) + 512);
1465 mz = rte_memzone_reserve(mz_name, total_alloc_len,
1468 RTE_MEMZONE_SIZE_HINT_ONLY);
1472 memset(mz->addr, 0, mz->len);
1473 mz_phys_addr = mz->phys_addr;
1474 if ((unsigned long)mz->addr == mz_phys_addr) {
1475 RTE_LOG(WARNING, PMD,
1476 "Memzone physical address same as virtual.\n");
1477 RTE_LOG(WARNING, PMD,
1478 "Using rte_mem_virt2phy()\n");
1479 mz_phys_addr = rte_mem_virt2phy(mz->addr);
1480 if (mz_phys_addr == 0) {
1482 "unable to map address to physical memory\n");
1487 bp->tx_mem_zone = (const void *)mz;
1488 bp->hw_tx_port_stats = mz->addr;
1489 bp->hw_tx_port_stats_map = mz_phys_addr;
1491 bp->flags |= BNXT_FLAG_PORT_STATS;
1494 rc = bnxt_alloc_hwrm_resources(bp);
1497 "hwrm resource allocation failure rc: %x\n", rc);
1500 rc = bnxt_hwrm_ver_get(bp);
1503 bnxt_hwrm_queue_qportcfg(bp);
1505 bnxt_hwrm_func_qcfg(bp);
1507 /* Get the MAX capabilities for this function */
1508 rc = bnxt_hwrm_func_qcaps(bp);
1510 RTE_LOG(ERR, PMD, "hwrm query capability failure rc: %x\n", rc);
1513 if (bp->max_tx_rings == 0) {
1514 RTE_LOG(ERR, PMD, "No TX rings available!\n");
1518 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
1519 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR, 0);
1520 if (eth_dev->data->mac_addrs == NULL) {
1522 "Failed to alloc %u bytes needed to store MAC addr tbl",
1523 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR);
1527 /* Copy the permanent MAC from the qcap response address now. */
1528 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
1529 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
1530 bp->grp_info = rte_zmalloc("bnxt_grp_info",
1531 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
1532 if (!bp->grp_info) {
1534 "Failed to alloc %zu bytes needed to store group info table\n",
1535 sizeof(*bp->grp_info) * bp->max_ring_grps);
1540 /* Forward all requests if firmware is new enough */
1541 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
1542 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
1543 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
1544 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
1546 RTE_LOG(WARNING, PMD,
1547 "Firmware too old for VF mailbox functionality\n");
1548 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
1552 * The following are used for driver cleanup. If we disallow these,
1553 * VF drivers can't clean up cleanly.
1555 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
1556 ALLOW_FUNC(HWRM_VNIC_FREE);
1557 ALLOW_FUNC(HWRM_RING_FREE);
1558 ALLOW_FUNC(HWRM_RING_GRP_FREE);
1559 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
1560 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
1561 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
1562 rc = bnxt_hwrm_func_driver_register(bp);
1565 "Failed to register driver");
1571 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
1572 pci_dev->mem_resource[0].phys_addr,
1573 pci_dev->mem_resource[0].addr);
1575 rc = bnxt_hwrm_func_reset(bp);
1577 RTE_LOG(ERR, PMD, "hwrm chip reset failure rc: %x\n", rc);
1583 //if (bp->pf.active_vfs) {
1584 // TODO: Deallocate VF resources?
1586 if (bp->pdev->max_vfs) {
1587 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
1589 RTE_LOG(ERR, PMD, "Failed to allocate VFs\n");
1593 rc = bnxt_hwrm_allocate_pf_only(bp);
1596 "Failed to allocate PF resources\n");
1602 rc = bnxt_setup_int(bp);
1606 rc = bnxt_alloc_mem(bp);
1608 goto error_free_int;
1610 rc = bnxt_request_int(bp);
1612 goto error_free_int;
1614 rc = bnxt_alloc_def_cp_ring(bp);
1616 goto error_free_int;
1618 bnxt_enable_int(bp);
1623 bnxt_disable_int(bp);
1624 bnxt_free_def_cp_ring(bp);
1625 bnxt_hwrm_func_buf_unrgtr(bp);
1629 bnxt_dev_uninit(eth_dev);
1635 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
1636 struct bnxt *bp = eth_dev->data->dev_private;
1639 bnxt_disable_int(bp);
1642 if (eth_dev->data->mac_addrs != NULL) {
1643 rte_free(eth_dev->data->mac_addrs);
1644 eth_dev->data->mac_addrs = NULL;
1646 if (bp->grp_info != NULL) {
1647 rte_free(bp->grp_info);
1648 bp->grp_info = NULL;
1650 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
1651 bnxt_free_hwrm_resources(bp);
1652 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1653 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1654 if (bp->dev_stopped == 0)
1655 bnxt_dev_close_op(eth_dev);
1657 rte_free(bp->pf.vf_info);
1658 eth_dev->dev_ops = NULL;
1659 eth_dev->rx_pkt_burst = NULL;
1660 eth_dev->tx_pkt_burst = NULL;
1665 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg)
1667 struct rte_pmd_bnxt_mb_event_param cb_param;
1669 cb_param.retval = RTE_PMD_BNXT_MB_EVENT_PROCEED;
1670 cb_param.vf_id = vf_id;
1673 _rte_eth_dev_callback_process(bp->eth_dev, RTE_ETH_EVENT_VF_MBOX,
1676 /* Default to approve */
1677 if (cb_param.retval == RTE_PMD_BNXT_MB_EVENT_PROCEED)
1678 cb_param.retval = RTE_PMD_BNXT_MB_EVENT_NOOP_ACK;
1680 return cb_param.retval == RTE_PMD_BNXT_MB_EVENT_NOOP_ACK ? true : false;
1683 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1684 struct rte_pci_device *pci_dev)
1686 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
1690 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
1692 return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
1695 static struct rte_pci_driver bnxt_rte_pmd = {
1696 .id_table = bnxt_pci_id_map,
1697 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
1698 RTE_PCI_DRV_INTR_LSC,
1699 .probe = bnxt_pci_probe,
1700 .remove = bnxt_pci_remove,
1703 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
1704 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
1705 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");