drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16 #include <rte_vect.h>
  17
  18 #include "bnxt.h"
  19 #include "bnxt_filter.h"
  20 #include "bnxt_hwrm.h"
  21 #include "bnxt_irq.h"
  22 #include "bnxt_reps.h"
  23 #include "bnxt_ring.h"
  24 #include "bnxt_rxq.h"
  25 #include "bnxt_rxr.h"
  26 #include "bnxt_stats.h"
  27 #include "bnxt_txq.h"
  28 #include "bnxt_txr.h"
  29 #include "bnxt_vnic.h"
  30 #include "hsi_struct_def_dpdk.h"
  31 #include "bnxt_nvm_defs.h"
  32 #include "bnxt_tf_common.h"
  33 #include "ulp_flow_db.h"
  34 #include "rte_pmd_bnxt.h"
  35
  36 #define DRV_MODULE_NAME         "bnxt"
  37 static const char bnxt_version[] =
  38         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  39
  40 /*
  41  * The set of PCI devices this driver supports
  42  */
  43 static const struct rte_pci_id bnxt_pci_id_map[] = {
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  47                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
  87         { .vendor_id = 0, /* sentinel */ },
  88 };
  89
  90 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
  91 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
  92 #define BNXT_DEVARG_REPRESENTOR "representor"
  93 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
  94 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
  95 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
  96 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
  97 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
  98 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
  99 #define BNXT_DEVARG_APP_ID      "app-id"
 100
 101 static const char *const bnxt_dev_args[] = {
 102         BNXT_DEVARG_REPRESENTOR,
 103         BNXT_DEVARG_FLOW_XSTAT,
 104         BNXT_DEVARG_MAX_NUM_KFLOWS,
 105         BNXT_DEVARG_REP_BASED_PF,
 106         BNXT_DEVARG_REP_IS_PF,
 107         BNXT_DEVARG_REP_Q_R2F,
 108         BNXT_DEVARG_REP_Q_F2R,
 109         BNXT_DEVARG_REP_FC_R2F,
 110         BNXT_DEVARG_REP_FC_F2R,
 111         BNXT_DEVARG_APP_ID,
 112         NULL
 113 };
 114
 115 /*
 116  * app-id = an non-negative 8-bit number
 117  */
 118 #define BNXT_DEVARG_APP_ID_INVALID(val)                 ((val) > 255)
 119
 120 /*
 121  * flow_xstat == false to disable the feature
 122  * flow_xstat == true to enable the feature
 123  */
 124 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 125
 126 /*
 127  * rep_is_pf == false to indicate VF representor
 128  * rep_is_pf == true to indicate PF representor
 129  */
 130 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 131
 132 /*
 133  * rep_based_pf == Physical index of the PF
 134  */
 135 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 136 /*
 137  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 138  */
 139 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 140
 141 /*
 142  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 143  */
 144 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 145
 146 /*
 147  * rep_fc_r2f == Flow control for the representor to endpoint direction
 148  */
 149 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 150
 151 /*
 152  * rep_fc_f2r == Flow control for the endpoint to representor direction
 153  */
 154 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 155
 156 int bnxt_cfa_code_dynfield_offset = -1;
 157
 158 /*
 159  * max_num_kflows must be >= 32
 160  * and must be a power-of-2 supported value
 161  * return: 1 -> invalid
 162  *         0 -> valid
 163  */
 164 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 165 {
 166         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 167                 return 1;
 168         return 0;
 169 }
 170
 171 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 172 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 173 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 174 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 175 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 176 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 177 static void bnxt_dev_recover(void *arg);
 178 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 179 static void bnxt_free_rep_info(struct bnxt *bp);
 180
 181 int is_bnxt_in_error(struct bnxt *bp)
 182 {
 183         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 184                 return -EIO;
 185         if (bp->flags & BNXT_FLAG_FW_RESET)
 186                 return -EBUSY;
 187
 188         return 0;
 189 }
 190
 191 /***********************/
 192
 193 /*
 194  * High level utility functions
 195  */
 196
 197 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 198 {
 199         unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
 200                                              BNXT_RSS_TBL_SIZE_P5);
 201
 202         if (!BNXT_CHIP_P5(bp))
 203                 return 1;
 204
 205         return RTE_ALIGN_MUL_CEIL(num_rss_rings,
 206                                   BNXT_RSS_ENTRIES_PER_CTX_P5) /
 207                                   BNXT_RSS_ENTRIES_PER_CTX_P5;
 208 }
 209
 210 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 211 {
 212         if (!BNXT_CHIP_P5(bp))
 213                 return HW_HASH_INDEX_SIZE;
 214
 215         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
 216 }
 217
 218 static void bnxt_free_parent_info(struct bnxt *bp)
 219 {
 220         rte_free(bp->parent);
 221         bp->parent = NULL;
 222 }
 223
 224 static void bnxt_free_pf_info(struct bnxt *bp)
 225 {
 226         rte_free(bp->pf);
 227         bp->pf = NULL;
 228 }
 229
 230 static void bnxt_free_link_info(struct bnxt *bp)
 231 {
 232         rte_free(bp->link_info);
 233         bp->link_info = NULL;
 234 }
 235
 236 static void bnxt_free_leds_info(struct bnxt *bp)
 237 {
 238         if (BNXT_VF(bp))
 239                 return;
 240
 241         rte_free(bp->leds);
 242         bp->leds = NULL;
 243 }
 244
 245 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 246 {
 247         rte_free(bp->flow_stat);
 248         bp->flow_stat = NULL;
 249 }
 250
 251 static void bnxt_free_cos_queues(struct bnxt *bp)
 252 {
 253         rte_free(bp->rx_cos_queue);
 254         bp->rx_cos_queue = NULL;
 255         rte_free(bp->tx_cos_queue);
 256         bp->tx_cos_queue = NULL;
 257 }
 258
 259 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 260 {
 261         bnxt_free_filter_mem(bp);
 262         bnxt_free_vnic_attributes(bp);
 263         bnxt_free_vnic_mem(bp);
 264
 265         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 266          * If the number of rings change across fw update,
 267          * we don't have much choice except to warn the user.
 268          */
 269         if (!reconfig) {
 270                 bnxt_free_stats(bp);
 271                 bnxt_free_tx_rings(bp);
 272                 bnxt_free_rx_rings(bp);
 273         }
 274         bnxt_free_async_cp_ring(bp);
 275         bnxt_free_rxtx_nq_ring(bp);
 276
 277         rte_free(bp->grp_info);
 278         bp->grp_info = NULL;
 279 }
 280
 281 static int bnxt_alloc_parent_info(struct bnxt *bp)
 282 {
 283         bp->parent = rte_zmalloc("bnxt_parent_info",
 284                                  sizeof(struct bnxt_parent_info), 0);
 285         if (bp->parent == NULL)
 286                 return -ENOMEM;
 287
 288         return 0;
 289 }
 290
 291 static int bnxt_alloc_pf_info(struct bnxt *bp)
 292 {
 293         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 294         if (bp->pf == NULL)
 295                 return -ENOMEM;
 296
 297         return 0;
 298 }
 299
 300 static int bnxt_alloc_link_info(struct bnxt *bp)
 301 {
 302         bp->link_info =
 303                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 304         if (bp->link_info == NULL)
 305                 return -ENOMEM;
 306
 307         return 0;
 308 }
 309
 310 static int bnxt_alloc_leds_info(struct bnxt *bp)
 311 {
 312         if (BNXT_VF(bp))
 313                 return 0;
 314
 315         bp->leds = rte_zmalloc("bnxt_leds",
 316                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 317                                0);
 318         if (bp->leds == NULL)
 319                 return -ENOMEM;
 320
 321         return 0;
 322 }
 323
 324 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 325 {
 326         bp->rx_cos_queue =
 327                 rte_zmalloc("bnxt_rx_cosq",
 328                             BNXT_COS_QUEUE_COUNT *
 329                             sizeof(struct bnxt_cos_queue_info),
 330                             0);
 331         if (bp->rx_cos_queue == NULL)
 332                 return -ENOMEM;
 333
 334         bp->tx_cos_queue =
 335                 rte_zmalloc("bnxt_tx_cosq",
 336                             BNXT_COS_QUEUE_COUNT *
 337                             sizeof(struct bnxt_cos_queue_info),
 338                             0);
 339         if (bp->tx_cos_queue == NULL)
 340                 return -ENOMEM;
 341
 342         return 0;
 343 }
 344
 345 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 346 {
 347         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 348                                     sizeof(struct bnxt_flow_stat_info), 0);
 349         if (bp->flow_stat == NULL)
 350                 return -ENOMEM;
 351
 352         return 0;
 353 }
 354
 355 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 356 {
 357         int rc;
 358
 359         rc = bnxt_alloc_ring_grps(bp);
 360         if (rc)
 361                 goto alloc_mem_err;
 362
 363         rc = bnxt_alloc_async_ring_struct(bp);
 364         if (rc)
 365                 goto alloc_mem_err;
 366
 367         rc = bnxt_alloc_vnic_mem(bp);
 368         if (rc)
 369                 goto alloc_mem_err;
 370
 371         rc = bnxt_alloc_vnic_attributes(bp, reconfig);
 372         if (rc)
 373                 goto alloc_mem_err;
 374
 375         rc = bnxt_alloc_filter_mem(bp);
 376         if (rc)
 377                 goto alloc_mem_err;
 378
 379         rc = bnxt_alloc_async_cp_ring(bp);
 380         if (rc)
 381                 goto alloc_mem_err;
 382
 383         rc = bnxt_alloc_rxtx_nq_ring(bp);
 384         if (rc)
 385                 goto alloc_mem_err;
 386
 387         if (BNXT_FLOW_XSTATS_EN(bp)) {
 388                 rc = bnxt_alloc_flow_stats_info(bp);
 389                 if (rc)
 390                         goto alloc_mem_err;
 391         }
 392
 393         return 0;
 394
 395 alloc_mem_err:
 396         bnxt_free_mem(bp, reconfig);
 397         return rc;
 398 }
 399
 400 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 401 {
 402         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 403         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 404         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 405         struct bnxt_rx_queue *rxq;
 406         unsigned int j;
 407         int rc;
 408
 409         rc = bnxt_vnic_grp_alloc(bp, vnic);
 410         if (rc)
 411                 goto err_out;
 412
 413         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 414                     vnic_id, vnic, vnic->fw_grp_ids);
 415
 416         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 417         if (rc)
 418                 goto err_out;
 419
 420         /* Alloc RSS context only if RSS mode is enabled */
 421         if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS) {
 422                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 423
 424                 /* RSS table size in Thor is 512.
 425                  * Cap max Rx rings to same value
 426                  */
 427                 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
 428                         PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
 429                                     bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
 430                         goto err_out;
 431                 }
 432
 433                 rc = 0;
 434                 for (j = 0; j < nr_ctxs; j++) {
 435                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 436                         if (rc)
 437                                 break;
 438                 }
 439                 if (rc) {
 440                         PMD_DRV_LOG(ERR,
 441                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 442                                     vnic_id, j, rc);
 443                         goto err_out;
 444                 }
 445                 vnic->num_lb_ctxts = nr_ctxs;
 446         }
 447
 448         /*
 449          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 450          * setting is not available at this time, it will not be
 451          * configured correctly in the CFA.
 452          */
 453         if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
 454                 vnic->vlan_strip = true;
 455         else
 456                 vnic->vlan_strip = false;
 457
 458         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 459         if (rc)
 460                 goto err_out;
 461
 462         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 463         if (rc)
 464                 goto err_out;
 465
 466         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 467                 rxq = bp->eth_dev->data->rx_queues[j];
 468
 469                 PMD_DRV_LOG(DEBUG,
 470                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 471                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 472
 473                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 474                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 475                 else
 476                         vnic->rx_queue_cnt++;
 477         }
 478
 479         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 480
 481         rc = bnxt_vnic_rss_configure(bp, vnic);
 482         if (rc)
 483                 goto err_out;
 484
 485         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 486
 487         rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic,
 488                                     (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) ?
 489                                     true : false);
 490         if (rc)
 491                 goto err_out;
 492
 493         return 0;
 494 err_out:
 495         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 496                     vnic_id, rc);
 497         return rc;
 498 }
 499
 500 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 501 {
 502         int rc = 0;
 503
 504         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 505                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 506         if (rc)
 507                 return rc;
 508
 509         PMD_DRV_LOG(DEBUG,
 510                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 511                     " rx_fc_in_tbl.ctx_id = %d\n",
 512                     bp->flow_stat->rx_fc_in_tbl.va,
 513                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 514                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 515
 516         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 517                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 518         if (rc)
 519                 return rc;
 520
 521         PMD_DRV_LOG(DEBUG,
 522                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 523                     " rx_fc_out_tbl.ctx_id = %d\n",
 524                     bp->flow_stat->rx_fc_out_tbl.va,
 525                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 526                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 527
 528         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 529                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 530         if (rc)
 531                 return rc;
 532
 533         PMD_DRV_LOG(DEBUG,
 534                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 535                     " tx_fc_in_tbl.ctx_id = %d\n",
 536                     bp->flow_stat->tx_fc_in_tbl.va,
 537                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 538                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 539
 540         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 541                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 542         if (rc)
 543                 return rc;
 544
 545         PMD_DRV_LOG(DEBUG,
 546                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 547                     " tx_fc_out_tbl.ctx_id = %d\n",
 548                     bp->flow_stat->tx_fc_out_tbl.va,
 549                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 550                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 551
 552         memset(bp->flow_stat->rx_fc_out_tbl.va,
 553                0,
 554                bp->flow_stat->rx_fc_out_tbl.size);
 555         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 556                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 557                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 558                                        bp->flow_stat->max_fc,
 559                                        true);
 560         if (rc)
 561                 return rc;
 562
 563         memset(bp->flow_stat->tx_fc_out_tbl.va,
 564                0,
 565                bp->flow_stat->tx_fc_out_tbl.size);
 566         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 567                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 568                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 569                                        bp->flow_stat->max_fc,
 570                                        true);
 571
 572         return rc;
 573 }
 574
 575 static int bnxt_alloc_ctx_mem_buf(struct bnxt *bp, char *type, size_t size,
 576                                   struct bnxt_ctx_mem_buf_info *ctx)
 577 {
 578         if (!ctx)
 579                 return -EINVAL;
 580
 581         ctx->va = rte_zmalloc_socket(type, size, 0,
 582                                      bp->eth_dev->device->numa_node);
 583         if (ctx->va == NULL)
 584                 return -ENOMEM;
 585         rte_mem_lock_page(ctx->va);
 586         ctx->size = size;
 587         ctx->dma = rte_mem_virt2iova(ctx->va);
 588         if (ctx->dma == RTE_BAD_IOVA)
 589                 return -ENOMEM;
 590
 591         return 0;
 592 }
 593
 594 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 595 {
 596         struct rte_pci_device *pdev = bp->pdev;
 597         char type[RTE_MEMZONE_NAMESIZE];
 598         uint16_t max_fc;
 599         int rc = 0;
 600
 601         max_fc = bp->flow_stat->max_fc;
 602
 603         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 604                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 605         /* 4 bytes for each counter-id */
 606         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 607                                     max_fc * 4,
 608                                     &bp->flow_stat->rx_fc_in_tbl);
 609         if (rc)
 610                 return rc;
 611
 612         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 613                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 614         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 615         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 616                                     max_fc * 16,
 617                                     &bp->flow_stat->rx_fc_out_tbl);
 618         if (rc)
 619                 return rc;
 620
 621         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 622                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 623         /* 4 bytes for each counter-id */
 624         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 625                                     max_fc * 4,
 626                                     &bp->flow_stat->tx_fc_in_tbl);
 627         if (rc)
 628                 return rc;
 629
 630         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 631                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 632         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 633         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 634                                     max_fc * 16,
 635                                     &bp->flow_stat->tx_fc_out_tbl);
 636         if (rc)
 637                 return rc;
 638
 639         rc = bnxt_register_fc_ctx_mem(bp);
 640
 641         return rc;
 642 }
 643
 644 static int bnxt_init_ctx_mem(struct bnxt *bp)
 645 {
 646         int rc = 0;
 647
 648         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 649             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 650             !BNXT_FLOW_XSTATS_EN(bp))
 651                 return 0;
 652
 653         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 654         if (rc)
 655                 return rc;
 656
 657         rc = bnxt_init_fc_ctx_mem(bp);
 658
 659         return rc;
 660 }
 661
 662 static int bnxt_update_phy_setting(struct bnxt *bp)
 663 {
 664         struct rte_eth_link new;
 665         int rc;
 666
 667         rc = bnxt_get_hwrm_link_config(bp, &new);
 668         if (rc) {
 669                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 670                 return rc;
 671         }
 672
 673         /*
 674          * On BCM957508-N2100 adapters, FW will not allow any user other
 675          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 676          * always returns link up. Force phy update always in that case.
 677          */
 678         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 679                 rc = bnxt_set_hwrm_link_config(bp, true);
 680                 if (rc) {
 681                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 682                         return rc;
 683                 }
 684         }
 685
 686         return rc;
 687 }
 688
 689 static void bnxt_free_prev_ring_stats(struct bnxt *bp)
 690 {
 691         rte_free(bp->prev_rx_ring_stats);
 692         rte_free(bp->prev_tx_ring_stats);
 693
 694         bp->prev_rx_ring_stats = NULL;
 695         bp->prev_tx_ring_stats = NULL;
 696 }
 697
 698 static int bnxt_alloc_prev_ring_stats(struct bnxt *bp)
 699 {
 700         bp->prev_rx_ring_stats =  rte_zmalloc("bnxt_prev_rx_ring_stats",
 701                                               sizeof(struct bnxt_ring_stats) *
 702                                               bp->rx_cp_nr_rings,
 703                                               0);
 704         if (bp->prev_rx_ring_stats == NULL)
 705                 return -ENOMEM;
 706
 707         bp->prev_tx_ring_stats = rte_zmalloc("bnxt_prev_tx_ring_stats",
 708                                              sizeof(struct bnxt_ring_stats) *
 709                                              bp->tx_cp_nr_rings,
 710                                              0);
 711         if (bp->prev_tx_ring_stats == NULL)
 712                 goto error;
 713
 714         return 0;
 715
 716 error:
 717         bnxt_free_prev_ring_stats(bp);
 718         return -ENOMEM;
 719 }
 720
 721 static int bnxt_start_nic(struct bnxt *bp)
 722 {
 723         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 724         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
 725         uint32_t intr_vector = 0;
 726         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 727         uint32_t vec = BNXT_MISC_VEC_ID;
 728         unsigned int i, j;
 729         int rc;
 730
 731         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU)
 732                 bp->flags |= BNXT_FLAG_JUMBO;
 733         else
 734                 bp->flags &= ~BNXT_FLAG_JUMBO;
 735
 736         /* THOR does not support ring groups.
 737          * But we will use the array to save RSS context IDs.
 738          */
 739         if (BNXT_CHIP_P5(bp))
 740                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
 741
 742         rc = bnxt_alloc_hwrm_rings(bp);
 743         if (rc) {
 744                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 745                 goto err_out;
 746         }
 747
 748         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 749         if (rc) {
 750                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 751                 goto err_out;
 752         }
 753
 754         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 755                 goto skip_cosq_cfg;
 756
 757         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 758                 if (bp->rx_cos_queue[i].id != 0xff) {
 759                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 760
 761                         if (!vnic) {
 762                                 PMD_DRV_LOG(ERR,
 763                                             "Num pools more than FW profile\n");
 764                                 rc = -EINVAL;
 765                                 goto err_out;
 766                         }
 767                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 768                         bp->rx_cosq_cnt++;
 769                 }
 770         }
 771
 772 skip_cosq_cfg:
 773         rc = bnxt_mq_rx_configure(bp);
 774         if (rc) {
 775                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 776                 goto err_out;
 777         }
 778
 779         for (j = 0; j < bp->rx_nr_rings; j++) {
 780                 struct bnxt_rx_queue *rxq = bp->rx_queues[j];
 781
 782                 if (!rxq->rx_deferred_start) {
 783                         bp->eth_dev->data->rx_queue_state[j] =
 784                                 RTE_ETH_QUEUE_STATE_STARTED;
 785                         rxq->rx_started = true;
 786                 }
 787         }
 788
 789         /* VNIC configuration */
 790         for (i = 0; i < bp->nr_vnics; i++) {
 791                 rc = bnxt_setup_one_vnic(bp, i);
 792                 if (rc)
 793                         goto err_out;
 794         }
 795
 796         for (j = 0; j < bp->tx_nr_rings; j++) {
 797                 struct bnxt_tx_queue *txq = bp->tx_queues[j];
 798
 799                 if (!txq->tx_deferred_start) {
 800                         bp->eth_dev->data->tx_queue_state[j] =
 801                                 RTE_ETH_QUEUE_STATE_STARTED;
 802                         txq->tx_started = true;
 803                 }
 804         }
 805
 806         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 807         if (rc) {
 808                 PMD_DRV_LOG(ERR,
 809                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 810                 goto err_out;
 811         }
 812
 813         /* check and configure queue intr-vector mapping */
 814         if ((rte_intr_cap_multiple(intr_handle) ||
 815              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 816             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 817                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 818                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 819                 if (intr_vector > bp->rx_cp_nr_rings) {
 820                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 821                                         bp->rx_cp_nr_rings);
 822                         return -ENOTSUP;
 823                 }
 824                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 825                 if (rc)
 826                         return rc;
 827         }
 828
 829         if (rte_intr_dp_is_en(intr_handle)) {
 830                 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
 831                                         bp->eth_dev->data->nb_rx_queues)) {
 832                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 833                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 834                         rc = -ENOMEM;
 835                         goto err_out;
 836                 }
 837                 PMD_DRV_LOG(DEBUG, "intr_handle->nb_efd = %d "
 838                             "intr_handle->max_intr = %d\n",
 839                             rte_intr_nb_efd_get(intr_handle),
 840                             rte_intr_max_intr_get(intr_handle));
 841                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 842                      queue_id++) {
 843                         rte_intr_vec_list_index_set(intr_handle,
 844                                         queue_id, vec + BNXT_RX_VEC_START);
 845                         if (vec < base + rte_intr_nb_efd_get(intr_handle)
 846                             - 1)
 847                                 vec++;
 848                 }
 849         }
 850
 851         /* enable uio/vfio intr/eventfd mapping */
 852         rc = rte_intr_enable(intr_handle);
 853 #ifndef RTE_EXEC_ENV_FREEBSD
 854         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 855         if (rc)
 856                 goto err_out;
 857 #endif
 858
 859         rc = bnxt_update_phy_setting(bp);
 860         if (rc)
 861                 goto err_out;
 862
 863         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 864         if (!bp->mark_table)
 865                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 866
 867         return 0;
 868
 869 err_out:
 870         /* Some of the error status returned by FW may not be from errno.h */
 871         if (rc > 0)
 872                 rc = -EIO;
 873
 874         return rc;
 875 }
 876
 877 static int bnxt_shutdown_nic(struct bnxt *bp)
 878 {
 879         bnxt_free_all_hwrm_resources(bp);
 880         bnxt_free_all_filters(bp);
 881         bnxt_free_all_vnics(bp);
 882         return 0;
 883 }
 884
 885 /*
 886  * Device configuration and status function
 887  */
 888
 889 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 890 {
 891         uint32_t link_speed = 0;
 892         uint32_t speed_capa = 0;
 893
 894         if (bp->link_info == NULL)
 895                 return 0;
 896
 897         link_speed = bp->link_info->support_speeds;
 898
 899         /* If PAM4 is configured, use PAM4 supported speed */
 900         if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
 901                 link_speed = bp->link_info->support_pam4_speeds;
 902
 903         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 904                 speed_capa |= RTE_ETH_LINK_SPEED_100M;
 905         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 906                 speed_capa |= RTE_ETH_LINK_SPEED_100M_HD;
 907         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 908                 speed_capa |= RTE_ETH_LINK_SPEED_1G;
 909         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 910                 speed_capa |= RTE_ETH_LINK_SPEED_2_5G;
 911         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 912                 speed_capa |= RTE_ETH_LINK_SPEED_10G;
 913         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 914                 speed_capa |= RTE_ETH_LINK_SPEED_20G;
 915         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 916                 speed_capa |= RTE_ETH_LINK_SPEED_25G;
 917         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 918                 speed_capa |= RTE_ETH_LINK_SPEED_40G;
 919         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 920                 speed_capa |= RTE_ETH_LINK_SPEED_50G;
 921         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 922                 speed_capa |= RTE_ETH_LINK_SPEED_100G;
 923         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 924                 speed_capa |= RTE_ETH_LINK_SPEED_50G;
 925         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 926                 speed_capa |= RTE_ETH_LINK_SPEED_100G;
 927         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 928                 speed_capa |= RTE_ETH_LINK_SPEED_200G;
 929
 930         if (bp->link_info->auto_mode ==
 931             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 932                 speed_capa |= RTE_ETH_LINK_SPEED_FIXED;
 933
 934         return speed_capa;
 935 }
 936
 937 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 938                                 struct rte_eth_dev_info *dev_info)
 939 {
 940         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 941         struct bnxt *bp = eth_dev->data->dev_private;
 942         uint16_t max_vnics, i, j, vpool, vrxq;
 943         unsigned int max_rx_rings;
 944         int rc;
 945
 946         rc = is_bnxt_in_error(bp);
 947         if (rc)
 948                 return rc;
 949
 950         /* MAC Specifics */
 951         dev_info->max_mac_addrs = RTE_MIN(bp->max_l2_ctx, RTE_ETH_NUM_RECEIVE_MAC_ADDR);
 952         dev_info->max_hash_mac_addrs = 0;
 953
 954         /* PF/VF specifics */
 955         if (BNXT_PF(bp))
 956                 dev_info->max_vfs = pdev->max_vfs;
 957
 958         max_rx_rings = bnxt_max_rings(bp);
 959         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 960         dev_info->max_rx_queues = max_rx_rings;
 961         dev_info->max_tx_queues = max_rx_rings;
 962         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 963         dev_info->hash_key_size = HW_HASH_KEY_SIZE;
 964         max_vnics = bp->max_vnics;
 965
 966         /* MTU specifics */
 967         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 968         dev_info->max_mtu = BNXT_MAX_MTU;
 969
 970         /* Fast path specifics */
 971         dev_info->min_rx_bufsize = 1;
 972         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 973
 974         dev_info->rx_offload_capa = bnxt_get_rx_port_offloads(bp);
 975         dev_info->tx_queue_offload_capa = RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;
 976         dev_info->tx_offload_capa = bnxt_get_tx_port_offloads(bp) |
 977                                     dev_info->tx_queue_offload_capa;
 978         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 979
 980         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 981         dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
 982                              RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
 983         dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
 984
 985         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 986                 .rx_thresh = {
 987                         .pthresh = 8,
 988                         .hthresh = 8,
 989                         .wthresh = 0,
 990                 },
 991                 .rx_free_thresh = 32,
 992                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
 993         };
 994
 995         dev_info->default_txconf = (struct rte_eth_txconf) {
 996                 .tx_thresh = {
 997                         .pthresh = 32,
 998                         .hthresh = 0,
 999                         .wthresh = 0,
1000                 },
1001                 .tx_free_thresh = 32,
1002                 .tx_rs_thresh = 32,
1003         };
1004         eth_dev->data->dev_conf.intr_conf.lsc = 1;
1005
1006         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1007         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
1008         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1009         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
1010
1011         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
1012                 dev_info->switch_info.name = eth_dev->device->name;
1013                 dev_info->switch_info.domain_id = bp->switch_domain_id;
1014                 dev_info->switch_info.port_id =
1015                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
1016                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
1017         }
1018
1019         /*
1020          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
1021          *       need further investigation.
1022          */
1023
1024         /* VMDq resources */
1025         vpool = 64; /* RTE_ETH_64_POOLS */
1026         vrxq = 128; /* RTE_ETH_VMDQ_DCB_NUM_QUEUES */
1027         for (i = 0; i < 4; vpool >>= 1, i++) {
1028                 if (max_vnics > vpool) {
1029                         for (j = 0; j < 5; vrxq >>= 1, j++) {
1030                                 if (dev_info->max_rx_queues > vrxq) {
1031                                         if (vpool > vrxq)
1032                                                 vpool = vrxq;
1033                                         goto found;
1034                                 }
1035                         }
1036                         /* Not enough resources to support VMDq */
1037                         break;
1038                 }
1039         }
1040         /* Not enough resources to support VMDq */
1041         vpool = 0;
1042         vrxq = 0;
1043 found:
1044         dev_info->max_vmdq_pools = vpool;
1045         dev_info->vmdq_queue_num = vrxq;
1046
1047         dev_info->vmdq_pool_base = 0;
1048         dev_info->vmdq_queue_base = 0;
1049
1050         return 0;
1051 }
1052
1053 /* Configure the device based on the configuration provided */
1054 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1055 {
1056         struct bnxt *bp = eth_dev->data->dev_private;
1057         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1058         struct rte_eth_rss_conf *rss_conf = &eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1059         int rc;
1060
1061         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1062         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1063         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1064         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1065
1066         rc = is_bnxt_in_error(bp);
1067         if (rc)
1068                 return rc;
1069
1070         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1071                 rc = bnxt_hwrm_check_vf_rings(bp);
1072                 if (rc) {
1073                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1074                         return -ENOSPC;
1075                 }
1076
1077                 /* If a resource has already been allocated - in this case
1078                  * it is the async completion ring, free it. Reallocate it after
1079                  * resource reservation. This will ensure the resource counts
1080                  * are calculated correctly.
1081                  */
1082
1083                 pthread_mutex_lock(&bp->def_cp_lock);
1084
1085                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1086                         bnxt_disable_int(bp);
1087                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1088                 }
1089
1090                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1091                 if (rc) {
1092                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1093                         pthread_mutex_unlock(&bp->def_cp_lock);
1094                         return -ENOSPC;
1095                 }
1096
1097                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1098                         rc = bnxt_alloc_async_cp_ring(bp);
1099                         if (rc) {
1100                                 pthread_mutex_unlock(&bp->def_cp_lock);
1101                                 return rc;
1102                         }
1103                         bnxt_enable_int(bp);
1104                 }
1105
1106                 pthread_mutex_unlock(&bp->def_cp_lock);
1107         }
1108
1109         /* Inherit new configurations */
1110         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1111             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1112             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1113                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1114             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1115             bp->max_stat_ctx)
1116                 goto resource_error;
1117
1118         if (BNXT_HAS_RING_GRPS(bp) &&
1119             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1120                 goto resource_error;
1121
1122         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS) &&
1123             bp->max_vnics < eth_dev->data->nb_rx_queues)
1124                 goto resource_error;
1125
1126         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1127         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1128
1129         if (eth_dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
1130                 rx_offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
1131         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1132
1133         /* application provides the hash key to program */
1134         if (rss_conf->rss_key != NULL) {
1135                 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE)
1136                         PMD_DRV_LOG(WARNING, "port %u RSS key len must be %d bytes long",
1137                                     eth_dev->data->port_id, HW_HASH_KEY_SIZE);
1138                 else
1139                         memcpy(bp->rss_conf.rss_key, rss_conf->rss_key, HW_HASH_KEY_SIZE);
1140         }
1141         bp->rss_conf.rss_key_len = HW_HASH_KEY_SIZE;
1142         bp->rss_conf.rss_hf = rss_conf->rss_hf;
1143
1144         bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1145
1146         return 0;
1147
1148 resource_error:
1149         PMD_DRV_LOG(ERR,
1150                     "Insufficient resources to support requested config\n");
1151         PMD_DRV_LOG(ERR,
1152                     "Num Queues Requested: Tx %d, Rx %d\n",
1153                     eth_dev->data->nb_tx_queues,
1154                     eth_dev->data->nb_rx_queues);
1155         PMD_DRV_LOG(ERR,
1156                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1157                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1158                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1159         return -ENOSPC;
1160 }
1161
1162 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1163 {
1164         struct rte_eth_link *link = &eth_dev->data->dev_link;
1165
1166         if (link->link_status)
1167                 PMD_DRV_LOG(DEBUG, "Port %d Link Up - speed %u Mbps - %s\n",
1168                         eth_dev->data->port_id,
1169                         (uint32_t)link->link_speed,
1170                         (link->link_duplex == RTE_ETH_LINK_FULL_DUPLEX) ?
1171                         ("full-duplex") : ("half-duplex\n"));
1172         else
1173                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1174                         eth_dev->data->port_id);
1175 }
1176
1177 /*
1178  * Determine whether the current configuration requires support for scattered
1179  * receive; return 1 if scattered receive is required and 0 if not.
1180  */
1181 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1182 {
1183         uint32_t overhead = BNXT_MAX_PKT_LEN - BNXT_MAX_MTU;
1184         uint16_t buf_size;
1185         int i;
1186
1187         if (eth_dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER)
1188                 return 1;
1189
1190         if (eth_dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO)
1191                 return 1;
1192
1193         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1194                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1195
1196                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1197                                       RTE_PKTMBUF_HEADROOM);
1198                 if (eth_dev->data->mtu + overhead > buf_size)
1199                         return 1;
1200         }
1201         return 0;
1202 }
1203
1204 static eth_rx_burst_t
1205 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1206 {
1207         struct bnxt *bp = eth_dev->data->dev_private;
1208
1209         /* Disable vector mode RX for Stingray2 for now */
1210         if (BNXT_CHIP_SR2(bp)) {
1211                 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1212                 return bnxt_recv_pkts;
1213         }
1214
1215 #if (defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)) && \
1216         !defined(RTE_LIBRTE_IEEE1588)
1217
1218         /* Vector mode receive cannot be enabled if scattered rx is in use. */
1219         if (eth_dev->data->scattered_rx)
1220                 goto use_scalar_rx;
1221
1222         /*
1223          * Vector mode receive cannot be enabled if Truflow is enabled or if
1224          * asynchronous completions and receive completions can be placed in
1225          * the same completion ring.
1226          */
1227         if (BNXT_TRUFLOW_EN(bp) || !BNXT_NUM_ASYNC_CPR(bp))
1228                 goto use_scalar_rx;
1229
1230         /*
1231          * Vector mode receive cannot be enabled if any receive offloads outside
1232          * a limited subset have been enabled.
1233          */
1234         if (eth_dev->data->dev_conf.rxmode.offloads &
1235                 ~(RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
1236                   RTE_ETH_RX_OFFLOAD_KEEP_CRC |
1237                   RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
1238                   RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
1239                   RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
1240                   RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1241                   RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
1242                   RTE_ETH_RX_OFFLOAD_RSS_HASH |
1243                   RTE_ETH_RX_OFFLOAD_VLAN_FILTER))
1244                 goto use_scalar_rx;
1245
1246 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1247         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1248             rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1249                 PMD_DRV_LOG(INFO,
1250                             "Using AVX2 vector mode receive for port %d\n",
1251                             eth_dev->data->port_id);
1252                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1253                 return bnxt_recv_pkts_vec_avx2;
1254         }
1255  #endif
1256         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1257                 PMD_DRV_LOG(INFO,
1258                             "Using SSE vector mode receive for port %d\n",
1259                             eth_dev->data->port_id);
1260                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1261                 return bnxt_recv_pkts_vec;
1262         }
1263
1264 use_scalar_rx:
1265         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1266                     eth_dev->data->port_id);
1267         PMD_DRV_LOG(INFO,
1268                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1269                     eth_dev->data->port_id,
1270                     eth_dev->data->scattered_rx,
1271                     eth_dev->data->dev_conf.rxmode.offloads);
1272 #endif
1273         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1274         return bnxt_recv_pkts;
1275 }
1276
1277 static eth_tx_burst_t
1278 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1279 {
1280         struct bnxt *bp = eth_dev->data->dev_private;
1281
1282         /* Disable vector mode TX for Stingray2 for now */
1283         if (BNXT_CHIP_SR2(bp))
1284                 return bnxt_xmit_pkts;
1285
1286 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) && \
1287         !defined(RTE_LIBRTE_IEEE1588)
1288         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1289
1290         /*
1291          * Vector mode transmit can be enabled only if not using scatter rx
1292          * or tx offloads.
1293          */
1294         if (eth_dev->data->scattered_rx ||
1295             (offloads & ~RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) ||
1296             BNXT_TRUFLOW_EN(bp))
1297                 goto use_scalar_tx;
1298
1299 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1300         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1301             rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1302                 PMD_DRV_LOG(INFO,
1303                             "Using AVX2 vector mode transmit for port %d\n",
1304                             eth_dev->data->port_id);
1305                 return bnxt_xmit_pkts_vec_avx2;
1306         }
1307 #endif
1308         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1309                 PMD_DRV_LOG(INFO,
1310                             "Using SSE vector mode transmit for port %d\n",
1311                             eth_dev->data->port_id);
1312                 return bnxt_xmit_pkts_vec;
1313         }
1314
1315 use_scalar_tx:
1316         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1317                     eth_dev->data->port_id);
1318         PMD_DRV_LOG(INFO,
1319                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1320                     eth_dev->data->port_id,
1321                     eth_dev->data->scattered_rx,
1322                     offloads);
1323 #endif
1324         return bnxt_xmit_pkts;
1325 }
1326
1327 static int bnxt_handle_if_change_status(struct bnxt *bp)
1328 {
1329         int rc;
1330
1331         /* Since fw has undergone a reset and lost all contexts,
1332          * set fatal flag to not issue hwrm during cleanup
1333          */
1334         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1335         bnxt_uninit_resources(bp, true);
1336
1337         /* clear fatal flag so that re-init happens */
1338         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1339         rc = bnxt_init_resources(bp, true);
1340
1341         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1342
1343         return rc;
1344 }
1345
1346 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1347 {
1348         struct bnxt *bp = eth_dev->data->dev_private;
1349         int rc = 0;
1350
1351         if (!BNXT_SINGLE_PF(bp))
1352                 return -ENOTSUP;
1353
1354         if (!bp->link_info->link_up)
1355                 rc = bnxt_set_hwrm_link_config(bp, true);
1356         if (!rc)
1357                 eth_dev->data->dev_link.link_status = 1;
1358
1359         bnxt_print_link_info(eth_dev);
1360         return rc;
1361 }
1362
1363 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1364 {
1365         struct bnxt *bp = eth_dev->data->dev_private;
1366
1367         if (!BNXT_SINGLE_PF(bp))
1368                 return -ENOTSUP;
1369
1370         eth_dev->data->dev_link.link_status = 0;
1371         bnxt_set_hwrm_link_config(bp, false);
1372         bp->link_info->link_up = 0;
1373
1374         return 0;
1375 }
1376
1377 static void bnxt_free_switch_domain(struct bnxt *bp)
1378 {
1379         int rc = 0;
1380
1381         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
1382                 return;
1383
1384         rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1385         if (rc)
1386                 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1387                             bp->switch_domain_id, rc);
1388 }
1389
1390 static void bnxt_ptp_get_current_time(void *arg)
1391 {
1392         struct bnxt *bp = arg;
1393         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1394         int rc;
1395
1396         rc = is_bnxt_in_error(bp);
1397         if (rc)
1398                 return;
1399
1400         if (!ptp)
1401                 return;
1402
1403         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1404                                 &ptp->current_time);
1405
1406         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1407         if (rc != 0) {
1408                 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1409                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1410         }
1411 }
1412
1413 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1414 {
1415         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1416         int rc;
1417
1418         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1419                 return 0;
1420
1421         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1422                                 &ptp->current_time);
1423
1424         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1425         return rc;
1426 }
1427
1428 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1429 {
1430         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1431                 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1432                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1433         }
1434 }
1435
1436 static void bnxt_ptp_stop(struct bnxt *bp)
1437 {
1438         bnxt_cancel_ptp_alarm(bp);
1439         bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1440 }
1441
1442 static int bnxt_ptp_start(struct bnxt *bp)
1443 {
1444         int rc;
1445
1446         rc = bnxt_schedule_ptp_alarm(bp);
1447         if (rc != 0) {
1448                 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1449         } else {
1450                 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1451                 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1452         }
1453
1454         return rc;
1455 }
1456
1457 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1458 {
1459         struct bnxt *bp = eth_dev->data->dev_private;
1460         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1461         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1462         struct rte_eth_link link;
1463         int ret;
1464
1465         eth_dev->data->dev_started = 0;
1466
1467         /* Prevent crashes when queues are still in use */
1468         bnxt_stop_rxtx(eth_dev);
1469
1470         bnxt_disable_int(bp);
1471
1472         /* disable uio/vfio intr/eventfd mapping */
1473         rte_intr_disable(intr_handle);
1474
1475         /* Stop the child representors for this device */
1476         ret = bnxt_rep_stop_all(bp);
1477         if (ret != 0)
1478                 return ret;
1479
1480         /* delete the bnxt ULP port details */
1481         bnxt_ulp_port_deinit(bp);
1482
1483         bnxt_cancel_fw_health_check(bp);
1484
1485         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1486                 bnxt_cancel_ptp_alarm(bp);
1487
1488         /* Do not bring link down during reset recovery */
1489         if (!is_bnxt_in_error(bp)) {
1490                 bnxt_dev_set_link_down_op(eth_dev);
1491                 /* Wait for link to be reset */
1492                 if (BNXT_SINGLE_PF(bp))
1493                         rte_delay_ms(500);
1494                 /* clear the recorded link status */
1495                 memset(&link, 0, sizeof(link));
1496                 rte_eth_linkstatus_set(eth_dev, &link);
1497         }
1498
1499         /* Clean queue intr-vector mapping */
1500         rte_intr_efd_disable(intr_handle);
1501         rte_intr_vec_list_free(intr_handle);
1502
1503         bnxt_hwrm_port_clr_stats(bp);
1504         bnxt_free_tx_mbufs(bp);
1505         bnxt_free_rx_mbufs(bp);
1506         /* Process any remaining notifications in default completion queue */
1507         bnxt_int_handler(eth_dev);
1508         bnxt_shutdown_nic(bp);
1509         bnxt_hwrm_if_change(bp, false);
1510
1511         bnxt_free_prev_ring_stats(bp);
1512         rte_free(bp->mark_table);
1513         bp->mark_table = NULL;
1514
1515         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1516         bp->rx_cosq_cnt = 0;
1517         /* All filters are deleted on a port stop. */
1518         if (BNXT_FLOW_XSTATS_EN(bp))
1519                 bp->flow_stat->flow_count = 0;
1520
1521         eth_dev->data->scattered_rx = 0;
1522
1523         return 0;
1524 }
1525
1526 /* Unload the driver, release resources */
1527 int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1528 {
1529         struct bnxt *bp = eth_dev->data->dev_private;
1530
1531         pthread_mutex_lock(&bp->err_recovery_lock);
1532         if (bp->flags & BNXT_FLAG_FW_RESET) {
1533                 PMD_DRV_LOG(ERR,
1534                             "Adapter recovering from error..Please retry\n");
1535                 pthread_mutex_unlock(&bp->err_recovery_lock);
1536                 return -EAGAIN;
1537         }
1538         pthread_mutex_unlock(&bp->err_recovery_lock);
1539
1540         return bnxt_dev_stop(eth_dev);
1541 }
1542
1543 int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1544 {
1545         struct bnxt *bp = eth_dev->data->dev_private;
1546         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1547         int vlan_mask = 0;
1548         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1549
1550         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1551                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1552                 return -EINVAL;
1553         }
1554
1555         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1556                 PMD_DRV_LOG(ERR,
1557                             "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1558                             bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1559
1560         do {
1561                 rc = bnxt_hwrm_if_change(bp, true);
1562                 if (rc == 0 || rc != -EAGAIN)
1563                         break;
1564
1565                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1566         } while (retry_cnt--);
1567
1568         if (rc)
1569                 return rc;
1570
1571         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1572                 rc = bnxt_handle_if_change_status(bp);
1573                 if (rc)
1574                         return rc;
1575         }
1576
1577         bnxt_enable_int(bp);
1578
1579         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1580
1581         rc = bnxt_start_nic(bp);
1582         if (rc)
1583                 goto error;
1584
1585         rc = bnxt_alloc_prev_ring_stats(bp);
1586         if (rc)
1587                 goto error;
1588
1589         eth_dev->data->dev_started = 1;
1590
1591         bnxt_link_update_op(eth_dev, 1);
1592
1593         if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
1594                 vlan_mask |= RTE_ETH_VLAN_FILTER_MASK;
1595         if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
1596                 vlan_mask |= RTE_ETH_VLAN_STRIP_MASK;
1597         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1598         if (rc)
1599                 goto error;
1600
1601         /* Initialize bnxt ULP port details */
1602         rc = bnxt_ulp_port_init(bp);
1603         if (rc)
1604                 goto error;
1605
1606         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1607         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1608
1609         bnxt_schedule_fw_health_check(bp);
1610
1611         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1612                 bnxt_schedule_ptp_alarm(bp);
1613
1614         return 0;
1615
1616 error:
1617         bnxt_dev_stop(eth_dev);
1618         return rc;
1619 }
1620
1621 static void
1622 bnxt_uninit_locks(struct bnxt *bp)
1623 {
1624         pthread_mutex_destroy(&bp->flow_lock);
1625         pthread_mutex_destroy(&bp->def_cp_lock);
1626         pthread_mutex_destroy(&bp->health_check_lock);
1627         pthread_mutex_destroy(&bp->err_recovery_lock);
1628         if (bp->rep_info) {
1629                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1630                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1631         }
1632 }
1633
1634 static void bnxt_drv_uninit(struct bnxt *bp)
1635 {
1636         bnxt_free_leds_info(bp);
1637         bnxt_free_cos_queues(bp);
1638         bnxt_free_link_info(bp);
1639         bnxt_free_parent_info(bp);
1640         bnxt_uninit_locks(bp);
1641
1642         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1643         bp->tx_mem_zone = NULL;
1644         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1645         bp->rx_mem_zone = NULL;
1646
1647         bnxt_free_vf_info(bp);
1648         bnxt_free_pf_info(bp);
1649
1650         rte_free(bp->grp_info);
1651         bp->grp_info = NULL;
1652 }
1653
1654 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1655 {
1656         struct bnxt *bp = eth_dev->data->dev_private;
1657         int ret = 0;
1658
1659         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1660                 return 0;
1661
1662         pthread_mutex_lock(&bp->err_recovery_lock);
1663         if (bp->flags & BNXT_FLAG_FW_RESET) {
1664                 PMD_DRV_LOG(ERR,
1665                             "Adapter recovering from error...Please retry\n");
1666                 pthread_mutex_unlock(&bp->err_recovery_lock);
1667                 return -EAGAIN;
1668         }
1669         pthread_mutex_unlock(&bp->err_recovery_lock);
1670
1671         /* cancel the recovery handler before remove dev */
1672         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1673         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1674         bnxt_cancel_fc_thread(bp);
1675         rte_eal_alarm_cancel(bnxt_handle_vf_cfg_change, (void *)bp);
1676
1677         if (eth_dev->data->dev_started)
1678                 ret = bnxt_dev_stop(eth_dev);
1679
1680         bnxt_uninit_resources(bp, false);
1681
1682         bnxt_drv_uninit(bp);
1683
1684         return ret;
1685 }
1686
1687 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1688                                     uint32_t index)
1689 {
1690         struct bnxt *bp = eth_dev->data->dev_private;
1691         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1692         struct bnxt_vnic_info *vnic;
1693         struct bnxt_filter_info *filter, *temp_filter;
1694         uint32_t i;
1695
1696         if (is_bnxt_in_error(bp))
1697                 return;
1698
1699         /*
1700          * Loop through all VNICs from the specified filter flow pools to
1701          * remove the corresponding MAC addr filter
1702          */
1703         for (i = 0; i < bp->nr_vnics; i++) {
1704                 if (!(pool_mask & (1ULL << i)))
1705                         continue;
1706
1707                 vnic = &bp->vnic_info[i];
1708                 filter = STAILQ_FIRST(&vnic->filter);
1709                 while (filter) {
1710                         temp_filter = STAILQ_NEXT(filter, next);
1711                         if (filter->mac_index == index) {
1712                                 STAILQ_REMOVE(&vnic->filter, filter,
1713                                                 bnxt_filter_info, next);
1714                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1715                                 bnxt_free_filter(bp, filter);
1716                         }
1717                         filter = temp_filter;
1718                 }
1719         }
1720 }
1721
1722 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1723                                struct rte_ether_addr *mac_addr, uint32_t index,
1724                                uint32_t pool)
1725 {
1726         struct bnxt_filter_info *filter;
1727         int rc = 0;
1728
1729         /* Attach requested MAC address to the new l2_filter */
1730         STAILQ_FOREACH(filter, &vnic->filter, next) {
1731                 if (filter->mac_index == index) {
1732                         PMD_DRV_LOG(DEBUG,
1733                                     "MAC addr already existed for pool %d\n",
1734                                     pool);
1735                         return 0;
1736                 }
1737         }
1738
1739         filter = bnxt_alloc_filter(bp);
1740         if (!filter) {
1741                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1742                 return -ENODEV;
1743         }
1744
1745         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1746          * if the MAC that's been programmed now is a different one, then,
1747          * copy that addr to filter->l2_addr
1748          */
1749         if (mac_addr)
1750                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1751         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1752
1753         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1754         if (!rc) {
1755                 filter->mac_index = index;
1756                 if (filter->mac_index == 0)
1757                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1758                 else
1759                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1760         } else {
1761                 bnxt_free_filter(bp, filter);
1762         }
1763
1764         return rc;
1765 }
1766
1767 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1768                                 struct rte_ether_addr *mac_addr,
1769                                 uint32_t index, uint32_t pool)
1770 {
1771         struct bnxt *bp = eth_dev->data->dev_private;
1772         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1773         int rc = 0;
1774
1775         rc = is_bnxt_in_error(bp);
1776         if (rc)
1777                 return rc;
1778
1779         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1780                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1781                 return -ENOTSUP;
1782         }
1783
1784         if (!vnic) {
1785                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1786                 return -EINVAL;
1787         }
1788
1789         /* Filter settings will get applied when port is started */
1790         if (!eth_dev->data->dev_started)
1791                 return 0;
1792
1793         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1794
1795         return rc;
1796 }
1797
1798 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1799 {
1800         int rc = 0;
1801         struct bnxt *bp = eth_dev->data->dev_private;
1802         struct rte_eth_link new;
1803         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1804                         BNXT_MIN_LINK_WAIT_CNT;
1805
1806         rc = is_bnxt_in_error(bp);
1807         if (rc)
1808                 return rc;
1809
1810         memset(&new, 0, sizeof(new));
1811
1812         if (bp->link_info == NULL)
1813                 goto out;
1814
1815         do {
1816                 /* Retrieve link info from hardware */
1817                 rc = bnxt_get_hwrm_link_config(bp, &new);
1818                 if (rc) {
1819                         new.link_speed = RTE_ETH_LINK_SPEED_100M;
1820                         new.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
1821                         PMD_DRV_LOG(ERR,
1822                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1823                         goto out;
1824                 }
1825
1826                 if (!wait_to_complete || new.link_status)
1827                         break;
1828
1829                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1830         } while (cnt--);
1831
1832         /* Only single function PF can bring phy down.
1833          * When port is stopped, report link down for VF/MH/NPAR functions.
1834          */
1835         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1836                 memset(&new, 0, sizeof(new));
1837
1838 out:
1839         /* Timed out or success */
1840         if (new.link_status != eth_dev->data->dev_link.link_status ||
1841             new.link_speed != eth_dev->data->dev_link.link_speed) {
1842                 rte_eth_linkstatus_set(eth_dev, &new);
1843                 bnxt_print_link_info(eth_dev);
1844         }
1845
1846         return rc;
1847 }
1848
1849 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1850 {
1851         struct bnxt *bp = eth_dev->data->dev_private;
1852         struct bnxt_vnic_info *vnic;
1853         uint32_t old_flags;
1854         int rc;
1855
1856         rc = is_bnxt_in_error(bp);
1857         if (rc)
1858                 return rc;
1859
1860         /* Filter settings will get applied when port is started */
1861         if (!eth_dev->data->dev_started)
1862                 return 0;
1863
1864         if (bp->vnic_info == NULL)
1865                 return 0;
1866
1867         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1868
1869         old_flags = vnic->flags;
1870         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1871         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1872         if (rc != 0)
1873                 vnic->flags = old_flags;
1874
1875         return rc;
1876 }
1877
1878 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1879 {
1880         struct bnxt *bp = eth_dev->data->dev_private;
1881         struct bnxt_vnic_info *vnic;
1882         uint32_t old_flags;
1883         int rc;
1884
1885         rc = is_bnxt_in_error(bp);
1886         if (rc)
1887                 return rc;
1888
1889         /* Filter settings will get applied when port is started */
1890         if (!eth_dev->data->dev_started)
1891                 return 0;
1892
1893         if (bp->vnic_info == NULL)
1894                 return 0;
1895
1896         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1897
1898         old_flags = vnic->flags;
1899         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1900         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1901         if (rc != 0)
1902                 vnic->flags = old_flags;
1903
1904         return rc;
1905 }
1906
1907 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1908 {
1909         struct bnxt *bp = eth_dev->data->dev_private;
1910         struct bnxt_vnic_info *vnic;
1911         uint32_t old_flags;
1912         int rc;
1913
1914         rc = is_bnxt_in_error(bp);
1915         if (rc)
1916                 return rc;
1917
1918         /* Filter settings will get applied when port is started */
1919         if (!eth_dev->data->dev_started)
1920                 return 0;
1921
1922         if (bp->vnic_info == NULL)
1923                 return 0;
1924
1925         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1926
1927         old_flags = vnic->flags;
1928         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1929         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1930         if (rc != 0)
1931                 vnic->flags = old_flags;
1932
1933         return rc;
1934 }
1935
1936 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1937 {
1938         struct bnxt *bp = eth_dev->data->dev_private;
1939         struct bnxt_vnic_info *vnic;
1940         uint32_t old_flags;
1941         int rc;
1942
1943         rc = is_bnxt_in_error(bp);
1944         if (rc)
1945                 return rc;
1946
1947         /* Filter settings will get applied when port is started */
1948         if (!eth_dev->data->dev_started)
1949                 return 0;
1950
1951         if (bp->vnic_info == NULL)
1952                 return 0;
1953
1954         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1955
1956         old_flags = vnic->flags;
1957         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1958         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1959         if (rc != 0)
1960                 vnic->flags = old_flags;
1961
1962         return rc;
1963 }
1964
1965 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1966 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1967 {
1968         if (qid >= bp->rx_nr_rings)
1969                 return NULL;
1970
1971         return bp->eth_dev->data->rx_queues[qid];
1972 }
1973
1974 /* Return rxq corresponding to a given rss table ring/group ID. */
1975 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1976 {
1977         struct bnxt_rx_queue *rxq;
1978         unsigned int i;
1979
1980         if (!BNXT_HAS_RING_GRPS(bp)) {
1981                 for (i = 0; i < bp->rx_nr_rings; i++) {
1982                         rxq = bp->eth_dev->data->rx_queues[i];
1983                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1984                                 return rxq->index;
1985                 }
1986         } else {
1987                 for (i = 0; i < bp->rx_nr_rings; i++) {
1988                         if (bp->grp_info[i].fw_grp_id == fwr)
1989                                 return i;
1990                 }
1991         }
1992
1993         return INVALID_HW_RING_ID;
1994 }
1995
1996 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1997                             struct rte_eth_rss_reta_entry64 *reta_conf,
1998                             uint16_t reta_size)
1999 {
2000         struct bnxt *bp = eth_dev->data->dev_private;
2001         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2002         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2003         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2004         uint16_t idx, sft;
2005         int i, rc;
2006
2007         rc = is_bnxt_in_error(bp);
2008         if (rc)
2009                 return rc;
2010
2011         if (!vnic->rss_table)
2012                 return -EINVAL;
2013
2014         if (!(dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG))
2015                 return -EINVAL;
2016
2017         if (reta_size != tbl_size) {
2018                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2019                         "(%d) must equal the size supported by the hardware "
2020                         "(%d)\n", reta_size, tbl_size);
2021                 return -EINVAL;
2022         }
2023
2024         for (i = 0; i < reta_size; i++) {
2025                 struct bnxt_rx_queue *rxq;
2026
2027                 idx = i / RTE_ETH_RETA_GROUP_SIZE;
2028                 sft = i % RTE_ETH_RETA_GROUP_SIZE;
2029
2030                 if (!(reta_conf[idx].mask & (1ULL << sft)))
2031                         continue;
2032
2033                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
2034                 if (!rxq) {
2035                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
2036                         return -EINVAL;
2037                 }
2038
2039                 if (BNXT_CHIP_P5(bp)) {
2040                         vnic->rss_table[i * 2] =
2041                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
2042                         vnic->rss_table[i * 2 + 1] =
2043                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
2044                 } else {
2045                         vnic->rss_table[i] =
2046                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
2047                 }
2048         }
2049
2050         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2051         return rc;
2052 }
2053
2054 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
2055                               struct rte_eth_rss_reta_entry64 *reta_conf,
2056                               uint16_t reta_size)
2057 {
2058         struct bnxt *bp = eth_dev->data->dev_private;
2059         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2060         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2061         uint16_t idx, sft, i;
2062         int rc;
2063
2064         rc = is_bnxt_in_error(bp);
2065         if (rc)
2066                 return rc;
2067
2068         if (!vnic)
2069                 return -EINVAL;
2070         if (!vnic->rss_table)
2071                 return -EINVAL;
2072
2073         if (reta_size != tbl_size) {
2074                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2075                         "(%d) must equal the size supported by the hardware "
2076                         "(%d)\n", reta_size, tbl_size);
2077                 return -EINVAL;
2078         }
2079
2080         for (idx = 0, i = 0; i < reta_size; i++) {
2081                 idx = i / RTE_ETH_RETA_GROUP_SIZE;
2082                 sft = i % RTE_ETH_RETA_GROUP_SIZE;
2083
2084                 if (reta_conf[idx].mask & (1ULL << sft)) {
2085                         uint16_t qid;
2086
2087                         if (BNXT_CHIP_P5(bp))
2088                                 qid = bnxt_rss_to_qid(bp,
2089                                                       vnic->rss_table[i * 2]);
2090                         else
2091                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2092
2093                         if (qid == INVALID_HW_RING_ID) {
2094                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2095                                 return -EINVAL;
2096                         }
2097                         reta_conf[idx].reta[sft] = qid;
2098                 }
2099         }
2100
2101         return 0;
2102 }
2103
2104 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2105                                    struct rte_eth_rss_conf *rss_conf)
2106 {
2107         struct bnxt *bp = eth_dev->data->dev_private;
2108         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2109         struct bnxt_vnic_info *vnic;
2110         int rc;
2111
2112         rc = is_bnxt_in_error(bp);
2113         if (rc)
2114                 return rc;
2115
2116         /*
2117          * If RSS enablement were different than dev_configure,
2118          * then return -EINVAL
2119          */
2120         if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
2121                 if (!rss_conf->rss_hf)
2122                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
2123         } else {
2124                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2125                         return -EINVAL;
2126         }
2127
2128         /* Update the default RSS VNIC(s) */
2129         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2130         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2131         vnic->hash_mode =
2132                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2133                                             RTE_ETH_RSS_LEVEL(rss_conf->rss_hf));
2134
2135         /* Cache the hash function */
2136         bp->rss_conf.rss_hf = rss_conf->rss_hf;
2137
2138         /*
2139          * If hashkey is not specified, use the previously configured
2140          * hashkey
2141          */
2142         if (!rss_conf->rss_key)
2143                 goto rss_config;
2144
2145         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2146                 PMD_DRV_LOG(ERR,
2147                             "Invalid hashkey length, should be %d bytes\n",
2148                             HW_HASH_KEY_SIZE);
2149                 return -EINVAL;
2150         }
2151         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2152
2153         /* Cache the hash key */
2154         memcpy(bp->rss_conf.rss_key, rss_conf->rss_key, HW_HASH_KEY_SIZE);
2155
2156 rss_config:
2157         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2158         return rc;
2159 }
2160
2161 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2162                                      struct rte_eth_rss_conf *rss_conf)
2163 {
2164         struct bnxt *bp = eth_dev->data->dev_private;
2165         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2166         int len, rc;
2167         uint32_t hash_types;
2168
2169         rc = is_bnxt_in_error(bp);
2170         if (rc)
2171                 return rc;
2172
2173         /* RSS configuration is the same for all VNICs */
2174         if (vnic && vnic->rss_hash_key) {
2175                 if (rss_conf->rss_key) {
2176                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2177                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2178                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2179                 }
2180
2181                 hash_types = vnic->hash_type;
2182                 rss_conf->rss_hf = 0;
2183                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2184                         rss_conf->rss_hf |= RTE_ETH_RSS_IPV4;
2185                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2186                 }
2187                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2188                         rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_TCP;
2189                         hash_types &=
2190                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2191                 }
2192                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2193                         rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_UDP;
2194                         hash_types &=
2195                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2196                 }
2197                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2198                         rss_conf->rss_hf |= RTE_ETH_RSS_IPV6;
2199                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2200                 }
2201                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2202                         rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_TCP;
2203                         hash_types &=
2204                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2205                 }
2206                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2207                         rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_UDP;
2208                         hash_types &=
2209                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2210                 }
2211
2212                 rss_conf->rss_hf |=
2213                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2214
2215                 if (hash_types) {
2216                         PMD_DRV_LOG(ERR,
2217                                 "Unknown RSS config from firmware (%08x), RSS disabled",
2218                                 vnic->hash_type);
2219                         return -ENOTSUP;
2220                 }
2221         } else {
2222                 rss_conf->rss_hf = 0;
2223         }
2224         return 0;
2225 }
2226
2227 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2228                                struct rte_eth_fc_conf *fc_conf)
2229 {
2230         struct bnxt *bp = dev->data->dev_private;
2231         struct rte_eth_link link_info;
2232         int rc;
2233
2234         rc = is_bnxt_in_error(bp);
2235         if (rc)
2236                 return rc;
2237
2238         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2239         if (rc)
2240                 return rc;
2241
2242         memset(fc_conf, 0, sizeof(*fc_conf));
2243         if (bp->link_info->auto_pause)
2244                 fc_conf->autoneg = 1;
2245         switch (bp->link_info->pause) {
2246         case 0:
2247                 fc_conf->mode = RTE_ETH_FC_NONE;
2248                 break;
2249         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2250                 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
2251                 break;
2252         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2253                 fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
2254                 break;
2255         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2256                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2257                 fc_conf->mode = RTE_ETH_FC_FULL;
2258                 break;
2259         }
2260         return 0;
2261 }
2262
2263 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2264                                struct rte_eth_fc_conf *fc_conf)
2265 {
2266         struct bnxt *bp = dev->data->dev_private;
2267         int rc;
2268
2269         rc = is_bnxt_in_error(bp);
2270         if (rc)
2271                 return rc;
2272
2273         if (!BNXT_SINGLE_PF(bp)) {
2274                 PMD_DRV_LOG(ERR,
2275                             "Flow Control Settings cannot be modified on VF or on shared PF\n");
2276                 return -ENOTSUP;
2277         }
2278
2279         switch (fc_conf->mode) {
2280         case RTE_ETH_FC_NONE:
2281                 bp->link_info->auto_pause = 0;
2282                 bp->link_info->force_pause = 0;
2283                 break;
2284         case RTE_ETH_FC_RX_PAUSE:
2285                 if (fc_conf->autoneg) {
2286                         bp->link_info->auto_pause =
2287                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2288                         bp->link_info->force_pause = 0;
2289                 } else {
2290                         bp->link_info->auto_pause = 0;
2291                         bp->link_info->force_pause =
2292                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2293                 }
2294                 break;
2295         case RTE_ETH_FC_TX_PAUSE:
2296                 if (fc_conf->autoneg) {
2297                         bp->link_info->auto_pause =
2298                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2299                         bp->link_info->force_pause = 0;
2300                 } else {
2301                         bp->link_info->auto_pause = 0;
2302                         bp->link_info->force_pause =
2303                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2304                 }
2305                 break;
2306         case RTE_ETH_FC_FULL:
2307                 if (fc_conf->autoneg) {
2308                         bp->link_info->auto_pause =
2309                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2310                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2311                         bp->link_info->force_pause = 0;
2312                 } else {
2313                         bp->link_info->auto_pause = 0;
2314                         bp->link_info->force_pause =
2315                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2316                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2317                 }
2318                 break;
2319         }
2320         return bnxt_set_hwrm_link_config(bp, true);
2321 }
2322
2323 /* Add UDP tunneling port */
2324 static int
2325 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2326                          struct rte_eth_udp_tunnel *udp_tunnel)
2327 {
2328         struct bnxt *bp = eth_dev->data->dev_private;
2329         uint16_t tunnel_type = 0;
2330         int rc = 0;
2331
2332         rc = is_bnxt_in_error(bp);
2333         if (rc)
2334                 return rc;
2335
2336         switch (udp_tunnel->prot_type) {
2337         case RTE_ETH_TUNNEL_TYPE_VXLAN:
2338                 if (bp->vxlan_port_cnt) {
2339                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2340                                 udp_tunnel->udp_port);
2341                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2342                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2343                                 return -ENOSPC;
2344                         }
2345                         bp->vxlan_port_cnt++;
2346                         return 0;
2347                 }
2348                 tunnel_type =
2349                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2350                 break;
2351         case RTE_ETH_TUNNEL_TYPE_GENEVE:
2352                 if (bp->geneve_port_cnt) {
2353                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2354                                 udp_tunnel->udp_port);
2355                         if (bp->geneve_port != udp_tunnel->udp_port) {
2356                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2357                                 return -ENOSPC;
2358                         }
2359                         bp->geneve_port_cnt++;
2360                         return 0;
2361                 }
2362                 tunnel_type =
2363                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2364                 break;
2365         default:
2366                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2367                 return -ENOTSUP;
2368         }
2369         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2370                                              tunnel_type);
2371
2372         if (rc != 0)
2373                 return rc;
2374
2375         if (tunnel_type ==
2376             HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN)
2377                 bp->vxlan_port_cnt++;
2378
2379         if (tunnel_type ==
2380             HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE)
2381                 bp->geneve_port_cnt++;
2382
2383         return rc;
2384 }
2385
2386 static int
2387 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2388                          struct rte_eth_udp_tunnel *udp_tunnel)
2389 {
2390         struct bnxt *bp = eth_dev->data->dev_private;
2391         uint16_t tunnel_type = 0;
2392         uint16_t port = 0;
2393         int rc = 0;
2394
2395         rc = is_bnxt_in_error(bp);
2396         if (rc)
2397                 return rc;
2398
2399         switch (udp_tunnel->prot_type) {
2400         case RTE_ETH_TUNNEL_TYPE_VXLAN:
2401                 if (!bp->vxlan_port_cnt) {
2402                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2403                         return -EINVAL;
2404                 }
2405                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2406                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2407                                 udp_tunnel->udp_port, bp->vxlan_port);
2408                         return -EINVAL;
2409                 }
2410                 if (--bp->vxlan_port_cnt)
2411                         return 0;
2412
2413                 tunnel_type =
2414                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2415                 port = bp->vxlan_fw_dst_port_id;
2416                 break;
2417         case RTE_ETH_TUNNEL_TYPE_GENEVE:
2418                 if (!bp->geneve_port_cnt) {
2419                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2420                         return -EINVAL;
2421                 }
2422                 if (bp->geneve_port != udp_tunnel->udp_port) {
2423                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2424                                 udp_tunnel->udp_port, bp->geneve_port);
2425                         return -EINVAL;
2426                 }
2427                 if (--bp->geneve_port_cnt)
2428                         return 0;
2429
2430                 tunnel_type =
2431                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2432                 port = bp->geneve_fw_dst_port_id;
2433                 break;
2434         default:
2435                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2436                 return -ENOTSUP;
2437         }
2438
2439         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2440         return rc;
2441 }
2442
2443 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2444 {
2445         struct bnxt_filter_info *filter;
2446         struct bnxt_vnic_info *vnic;
2447         int rc = 0;
2448         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2449
2450         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2451         filter = STAILQ_FIRST(&vnic->filter);
2452         while (filter) {
2453                 /* Search for this matching MAC+VLAN filter */
2454                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2455                         /* Delete the filter */
2456                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2457                         if (rc)
2458                                 return rc;
2459                         STAILQ_REMOVE(&vnic->filter, filter,
2460                                       bnxt_filter_info, next);
2461                         bnxt_free_filter(bp, filter);
2462                         PMD_DRV_LOG(INFO,
2463                                     "Deleted vlan filter for %d\n",
2464                                     vlan_id);
2465                         return 0;
2466                 }
2467                 filter = STAILQ_NEXT(filter, next);
2468         }
2469         return -ENOENT;
2470 }
2471
2472 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2473 {
2474         struct bnxt_filter_info *filter;
2475         struct bnxt_vnic_info *vnic;
2476         int rc = 0;
2477         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2478                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2479         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2480
2481         /* Implementation notes on the use of VNIC in this command:
2482          *
2483          * By default, these filters belong to default vnic for the function.
2484          * Once these filters are set up, only destination VNIC can be modified.
2485          * If the destination VNIC is not specified in this command,
2486          * then the HWRM shall only create an l2 context id.
2487          */
2488
2489         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2490         filter = STAILQ_FIRST(&vnic->filter);
2491         /* Check if the VLAN has already been added */
2492         while (filter) {
2493                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2494                         return -EEXIST;
2495
2496                 filter = STAILQ_NEXT(filter, next);
2497         }
2498
2499         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2500          * command to create MAC+VLAN filter with the right flags, enables set.
2501          */
2502         filter = bnxt_alloc_filter(bp);
2503         if (!filter) {
2504                 PMD_DRV_LOG(ERR,
2505                             "MAC/VLAN filter alloc failed\n");
2506                 return -ENOMEM;
2507         }
2508         /* MAC + VLAN ID filter */
2509         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2510          * untagged packets are received
2511          *
2512          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2513          * packets and only the programmed vlan's packets are received
2514          */
2515         filter->l2_ivlan = vlan_id;
2516         filter->l2_ivlan_mask = 0x0FFF;
2517         filter->enables |= en;
2518         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2519
2520         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2521         if (rc) {
2522                 /* Free the newly allocated filter as we were
2523                  * not able to create the filter in hardware.
2524                  */
2525                 bnxt_free_filter(bp, filter);
2526                 return rc;
2527         }
2528
2529         filter->mac_index = 0;
2530         /* Add this new filter to the list */
2531         if (vlan_id == 0)
2532                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2533         else
2534                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2535
2536         PMD_DRV_LOG(INFO,
2537                     "Added Vlan filter for %d\n", vlan_id);
2538         return rc;
2539 }
2540
2541 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2542                 uint16_t vlan_id, int on)
2543 {
2544         struct bnxt *bp = eth_dev->data->dev_private;
2545         int rc;
2546
2547         rc = is_bnxt_in_error(bp);
2548         if (rc)
2549                 return rc;
2550
2551         if (!eth_dev->data->dev_started) {
2552                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2553                 return -EINVAL;
2554         }
2555
2556         /* These operations apply to ALL existing MAC/VLAN filters */
2557         if (on)
2558                 return bnxt_add_vlan_filter(bp, vlan_id);
2559         else
2560                 return bnxt_del_vlan_filter(bp, vlan_id);
2561 }
2562
2563 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2564                                     struct bnxt_vnic_info *vnic)
2565 {
2566         struct bnxt_filter_info *filter;
2567         int rc;
2568
2569         filter = STAILQ_FIRST(&vnic->filter);
2570         while (filter) {
2571                 if (filter->mac_index == 0 &&
2572                     !memcmp(filter->l2_addr, bp->mac_addr,
2573                             RTE_ETHER_ADDR_LEN)) {
2574                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2575                         if (!rc) {
2576                                 STAILQ_REMOVE(&vnic->filter, filter,
2577                                               bnxt_filter_info, next);
2578                                 bnxt_free_filter(bp, filter);
2579                         }
2580                         return rc;
2581                 }
2582                 filter = STAILQ_NEXT(filter, next);
2583         }
2584         return 0;
2585 }
2586
2587 static int
2588 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2589 {
2590         struct bnxt_vnic_info *vnic;
2591         unsigned int i;
2592         int rc;
2593
2594         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2595         if (!(rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)) {
2596                 /* Remove any VLAN filters programmed */
2597                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2598                         bnxt_del_vlan_filter(bp, i);
2599
2600                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2601                 if (rc)
2602                         return rc;
2603         } else {
2604                 /* Default filter will allow packets that match the
2605                  * dest mac. So, it has to be deleted, otherwise, we
2606                  * will endup receiving vlan packets for which the
2607                  * filter is not programmed, when hw-vlan-filter
2608                  * configuration is ON
2609                  */
2610                 bnxt_del_dflt_mac_filter(bp, vnic);
2611                 /* This filter will allow only untagged packets */
2612                 bnxt_add_vlan_filter(bp, 0);
2613         }
2614         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2615                     !!(rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER));
2616
2617         return 0;
2618 }
2619
2620 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2621 {
2622         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2623         unsigned int i;
2624         int rc;
2625
2626         /* Destroy vnic filters and vnic */
2627         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2628             RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
2629                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2630                         bnxt_del_vlan_filter(bp, i);
2631         }
2632         bnxt_del_dflt_mac_filter(bp, vnic);
2633
2634         rc = bnxt_hwrm_vnic_ctx_free(bp, vnic);
2635         if (rc)
2636                 return rc;
2637
2638         rc = bnxt_hwrm_vnic_free(bp, vnic);
2639         if (rc)
2640                 return rc;
2641
2642         rte_free(vnic->fw_grp_ids);
2643         vnic->fw_grp_ids = NULL;
2644
2645         vnic->rx_queue_cnt = 0;
2646
2647         return 0;
2648 }
2649
2650 static int
2651 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2652 {
2653         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2654         int rc;
2655
2656         /* Destroy, recreate and reconfigure the default vnic */
2657         rc = bnxt_free_one_vnic(bp, 0);
2658         if (rc)
2659                 return rc;
2660
2661         /* default vnic 0 */
2662         rc = bnxt_setup_one_vnic(bp, 0);
2663         if (rc)
2664                 return rc;
2665
2666         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2667             RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
2668                 rc = bnxt_add_vlan_filter(bp, 0);
2669                 if (rc)
2670                         return rc;
2671                 rc = bnxt_restore_vlan_filters(bp);
2672                 if (rc)
2673                         return rc;
2674         } else {
2675                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2676                 if (rc)
2677                         return rc;
2678         }
2679
2680         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2681         if (rc)
2682                 return rc;
2683
2684         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2685                     !!(rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP));
2686
2687         return rc;
2688 }
2689
2690 static int
2691 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2692 {
2693         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2694         struct bnxt *bp = dev->data->dev_private;
2695         int rc;
2696
2697         rc = is_bnxt_in_error(bp);
2698         if (rc)
2699                 return rc;
2700
2701         /* Filter settings will get applied when port is started */
2702         if (!dev->data->dev_started)
2703                 return 0;
2704
2705         if (mask & RTE_ETH_VLAN_FILTER_MASK) {
2706                 /* Enable or disable VLAN filtering */
2707                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2708                 if (rc)
2709                         return rc;
2710         }
2711
2712         if (mask & RTE_ETH_VLAN_STRIP_MASK) {
2713                 /* Enable or disable VLAN stripping */
2714                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2715                 if (rc)
2716                         return rc;
2717         }
2718
2719         if (mask & RTE_ETH_VLAN_EXTEND_MASK) {
2720                 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND)
2721                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2722                 else
2723                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2724         }
2725
2726         return 0;
2727 }
2728
2729 static int
2730 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2731                       uint16_t tpid)
2732 {
2733         struct bnxt *bp = dev->data->dev_private;
2734         int qinq = dev->data->dev_conf.rxmode.offloads &
2735                    RTE_ETH_RX_OFFLOAD_VLAN_EXTEND;
2736
2737         if (vlan_type != RTE_ETH_VLAN_TYPE_INNER &&
2738             vlan_type != RTE_ETH_VLAN_TYPE_OUTER) {
2739                 PMD_DRV_LOG(ERR,
2740                             "Unsupported vlan type.");
2741                 return -EINVAL;
2742         }
2743         if (!qinq) {
2744                 PMD_DRV_LOG(ERR,
2745                             "QinQ not enabled. Needs to be ON as we can "
2746                             "accelerate only outer vlan\n");
2747                 return -EINVAL;
2748         }
2749
2750         if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER) {
2751                 switch (tpid) {
2752                 case RTE_ETHER_TYPE_QINQ:
2753                         bp->outer_tpid_bd =
2754                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2755                                 break;
2756                 case RTE_ETHER_TYPE_VLAN:
2757                         bp->outer_tpid_bd =
2758                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2759                                 break;
2760                 case RTE_ETHER_TYPE_QINQ1:
2761                         bp->outer_tpid_bd =
2762                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2763                                 break;
2764                 case RTE_ETHER_TYPE_QINQ2:
2765                         bp->outer_tpid_bd =
2766                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2767                                 break;
2768                 case RTE_ETHER_TYPE_QINQ3:
2769                         bp->outer_tpid_bd =
2770                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2771                                 break;
2772                 default:
2773                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2774                         return -EINVAL;
2775                 }
2776                 bp->outer_tpid_bd |= tpid;
2777                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2778         } else if (vlan_type == RTE_ETH_VLAN_TYPE_INNER) {
2779                 PMD_DRV_LOG(ERR,
2780                             "Can accelerate only outer vlan in QinQ\n");
2781                 return -EINVAL;
2782         }
2783
2784         return 0;
2785 }
2786
2787 static int
2788 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2789                              struct rte_ether_addr *addr)
2790 {
2791         struct bnxt *bp = dev->data->dev_private;
2792         /* Default Filter is tied to VNIC 0 */
2793         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2794         int rc;
2795
2796         rc = is_bnxt_in_error(bp);
2797         if (rc)
2798                 return rc;
2799
2800         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2801                 return -EPERM;
2802
2803         if (rte_is_zero_ether_addr(addr))
2804                 return -EINVAL;
2805
2806         /* Filter settings will get applied when port is started */
2807         if (!dev->data->dev_started)
2808                 return 0;
2809
2810         /* Check if the requested MAC is already added */
2811         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2812                 return 0;
2813
2814         /* Destroy filter and re-create it */
2815         bnxt_del_dflt_mac_filter(bp, vnic);
2816
2817         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2818         if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
2819                 /* This filter will allow only untagged packets */
2820                 rc = bnxt_add_vlan_filter(bp, 0);
2821         } else {
2822                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2823         }
2824
2825         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2826         return rc;
2827 }
2828
2829 static int
2830 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2831                           struct rte_ether_addr *mc_addr_set,
2832                           uint32_t nb_mc_addr)
2833 {
2834         struct bnxt *bp = eth_dev->data->dev_private;
2835         struct bnxt_vnic_info *vnic;
2836         uint32_t i = 0;
2837         int rc;
2838
2839         rc = is_bnxt_in_error(bp);
2840         if (rc)
2841                 return rc;
2842
2843         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2844
2845         bp->nb_mc_addr = nb_mc_addr;
2846
2847         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2848                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2849                 goto allmulti;
2850         }
2851
2852         /* TODO Check for Duplicate mcast addresses */
2853         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2854         for (i = 0; i < nb_mc_addr; i++)
2855                 rte_ether_addr_copy(&mc_addr_set[i], &bp->mcast_addr_list[i]);
2856
2857         if (bp->nb_mc_addr)
2858                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2859         else
2860                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2861
2862 allmulti:
2863         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2864 }
2865
2866 static int
2867 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2868 {
2869         struct bnxt *bp = dev->data->dev_private;
2870         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2871         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2872         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2873         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2874         int ret;
2875
2876         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2877                         fw_major, fw_minor, fw_updt, fw_rsvd);
2878         if (ret < 0)
2879                 return -EINVAL;
2880
2881         ret += 1; /* add the size of '\0' */
2882         if (fw_size < (size_t)ret)
2883                 return ret;
2884         else
2885                 return 0;
2886 }
2887
2888 static void
2889 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2890         struct rte_eth_rxq_info *qinfo)
2891 {
2892         struct bnxt *bp = dev->data->dev_private;
2893         struct bnxt_rx_queue *rxq;
2894
2895         if (is_bnxt_in_error(bp))
2896                 return;
2897
2898         rxq = dev->data->rx_queues[queue_id];
2899
2900         qinfo->mp = rxq->mb_pool;
2901         qinfo->scattered_rx = dev->data->scattered_rx;
2902         qinfo->nb_desc = rxq->nb_rx_desc;
2903
2904         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2905         qinfo->conf.rx_drop_en = rxq->drop_en;
2906         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2907         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2908 }
2909
2910 static void
2911 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2912         struct rte_eth_txq_info *qinfo)
2913 {
2914         struct bnxt *bp = dev->data->dev_private;
2915         struct bnxt_tx_queue *txq;
2916
2917         if (is_bnxt_in_error(bp))
2918                 return;
2919
2920         txq = dev->data->tx_queues[queue_id];
2921
2922         qinfo->nb_desc = txq->nb_tx_desc;
2923
2924         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2925         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2926         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2927
2928         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2929         qinfo->conf.tx_rs_thresh = 0;
2930         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2931         qinfo->conf.offloads = txq->offloads;
2932 }
2933
2934 static const struct {
2935         eth_rx_burst_t pkt_burst;
2936         const char *info;
2937 } bnxt_rx_burst_info[] = {
2938         {bnxt_recv_pkts,                "Scalar"},
2939 #if defined(RTE_ARCH_X86)
2940         {bnxt_recv_pkts_vec,            "Vector SSE"},
2941 #endif
2942 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2943         {bnxt_recv_pkts_vec_avx2,       "Vector AVX2"},
2944 #endif
2945 #if defined(RTE_ARCH_ARM64)
2946         {bnxt_recv_pkts_vec,            "Vector Neon"},
2947 #endif
2948 };
2949
2950 static int
2951 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2952                        struct rte_eth_burst_mode *mode)
2953 {
2954         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2955         size_t i;
2956
2957         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2958                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2959                         snprintf(mode->info, sizeof(mode->info), "%s",
2960                                  bnxt_rx_burst_info[i].info);
2961                         return 0;
2962                 }
2963         }
2964
2965         return -EINVAL;
2966 }
2967
2968 static const struct {
2969         eth_tx_burst_t pkt_burst;
2970         const char *info;
2971 } bnxt_tx_burst_info[] = {
2972         {bnxt_xmit_pkts,                "Scalar"},
2973 #if defined(RTE_ARCH_X86)
2974         {bnxt_xmit_pkts_vec,            "Vector SSE"},
2975 #endif
2976 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2977         {bnxt_xmit_pkts_vec_avx2,       "Vector AVX2"},
2978 #endif
2979 #if defined(RTE_ARCH_ARM64)
2980         {bnxt_xmit_pkts_vec,            "Vector Neon"},
2981 #endif
2982 };
2983
2984 static int
2985 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2986                        struct rte_eth_burst_mode *mode)
2987 {
2988         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2989         size_t i;
2990
2991         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2992                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2993                         snprintf(mode->info, sizeof(mode->info), "%s",
2994                                  bnxt_tx_burst_info[i].info);
2995                         return 0;
2996                 }
2997         }
2998
2999         return -EINVAL;
3000 }
3001
3002 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
3003 {
3004         uint32_t overhead = BNXT_MAX_PKT_LEN - BNXT_MAX_MTU;
3005         struct bnxt *bp = eth_dev->data->dev_private;
3006         uint32_t new_pkt_size;
3007         uint32_t rc;
3008         uint32_t i;
3009
3010         rc = is_bnxt_in_error(bp);
3011         if (rc)
3012                 return rc;
3013
3014         /* Exit if receive queues are not configured yet */
3015         if (!eth_dev->data->nb_rx_queues)
3016                 return rc;
3017
3018         new_pkt_size = new_mtu + overhead;
3019
3020         /*
3021          * Disallow any MTU change that would require scattered receive support
3022          * if it is not already enabled.
3023          */
3024         if (eth_dev->data->dev_started &&
3025             !eth_dev->data->scattered_rx &&
3026             (new_pkt_size >
3027              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3028                 PMD_DRV_LOG(ERR,
3029                             "MTU change would require scattered rx support. ");
3030                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
3031                 return -EINVAL;
3032         }
3033
3034         if (new_mtu > RTE_ETHER_MTU)
3035                 bp->flags |= BNXT_FLAG_JUMBO;
3036         else
3037                 bp->flags &= ~BNXT_FLAG_JUMBO;
3038
3039         /* Is there a change in mtu setting? */
3040         if (eth_dev->data->mtu == new_mtu)
3041                 return rc;
3042
3043         for (i = 0; i < bp->nr_vnics; i++) {
3044                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3045                 uint16_t size = 0;
3046
3047                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
3048                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
3049                 if (rc)
3050                         break;
3051
3052                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
3053                 size -= RTE_PKTMBUF_HEADROOM;
3054
3055                 if (size < new_mtu) {
3056                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
3057                         if (rc)
3058                                 return rc;
3059                 }
3060         }
3061
3062         if (bnxt_hwrm_config_host_mtu(bp))
3063                 PMD_DRV_LOG(WARNING, "Failed to configure host MTU\n");
3064
3065         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
3066
3067         return rc;
3068 }
3069
3070 static int
3071 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
3072 {
3073         struct bnxt *bp = dev->data->dev_private;
3074         uint16_t vlan = bp->vlan;
3075         int rc;
3076
3077         rc = is_bnxt_in_error(bp);
3078         if (rc)
3079                 return rc;
3080
3081         if (!BNXT_SINGLE_PF(bp)) {
3082                 PMD_DRV_LOG(ERR, "PVID cannot be modified on VF or on shared PF\n");
3083                 return -ENOTSUP;
3084         }
3085         bp->vlan = on ? pvid : 0;
3086
3087         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
3088         if (rc)
3089                 bp->vlan = vlan;
3090         return rc;
3091 }
3092
3093 static int
3094 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
3095 {
3096         struct bnxt *bp = dev->data->dev_private;
3097         int rc;
3098
3099         rc = is_bnxt_in_error(bp);
3100         if (rc)
3101                 return rc;
3102
3103         return bnxt_hwrm_port_led_cfg(bp, true);
3104 }
3105
3106 static int
3107 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3108 {
3109         struct bnxt *bp = dev->data->dev_private;
3110         int rc;
3111
3112         rc = is_bnxt_in_error(bp);
3113         if (rc)
3114                 return rc;
3115
3116         return bnxt_hwrm_port_led_cfg(bp, false);
3117 }
3118
3119 static uint32_t
3120 bnxt_rx_queue_count_op(void *rx_queue)
3121 {
3122         struct bnxt *bp;
3123         struct bnxt_cp_ring_info *cpr;
3124         uint32_t desc = 0, raw_cons, cp_ring_size;
3125         struct bnxt_rx_queue *rxq;
3126         struct rx_pkt_cmpl *rxcmp;
3127         int rc;
3128
3129         rxq = rx_queue;
3130         bp = rxq->bp;
3131
3132         rc = is_bnxt_in_error(bp);
3133         if (rc)
3134                 return rc;
3135
3136         cpr = rxq->cp_ring;
3137         raw_cons = cpr->cp_raw_cons;
3138         cp_ring_size = cpr->cp_ring_struct->ring_size;
3139
3140         while (1) {
3141                 uint32_t agg_cnt, cons, cmpl_type;
3142
3143                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3144                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3145
3146                 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3147                         break;
3148
3149                 cmpl_type = CMP_TYPE(rxcmp);
3150
3151                 switch (cmpl_type) {
3152                 case CMPL_BASE_TYPE_RX_L2:
3153                 case CMPL_BASE_TYPE_RX_L2_V2:
3154                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3155                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3156                         desc++;
3157                         break;
3158
3159                 case CMPL_BASE_TYPE_RX_TPA_END:
3160                         if (BNXT_CHIP_P5(rxq->bp)) {
3161                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3162
3163                                 p5_tpa_end = (void *)rxcmp;
3164                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3165                         } else {
3166                                 struct rx_tpa_end_cmpl *tpa_end;
3167
3168                                 tpa_end = (void *)rxcmp;
3169                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3170                         }
3171
3172                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3173                         desc++;
3174                         break;
3175
3176                 default:
3177                         raw_cons += CMP_LEN(cmpl_type);
3178                 }
3179         }
3180
3181         return desc;
3182 }
3183
3184 static int
3185 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3186 {
3187         struct bnxt_rx_queue *rxq = rx_queue;
3188         struct bnxt_cp_ring_info *cpr;
3189         struct bnxt_rx_ring_info *rxr;
3190         uint32_t desc, raw_cons, cp_ring_size;
3191         struct bnxt *bp = rxq->bp;
3192         struct rx_pkt_cmpl *rxcmp;
3193         int rc;
3194
3195         rc = is_bnxt_in_error(bp);
3196         if (rc)
3197                 return rc;
3198
3199         if (offset >= rxq->nb_rx_desc)
3200                 return -EINVAL;
3201
3202         rxr = rxq->rx_ring;
3203         cpr = rxq->cp_ring;
3204         cp_ring_size = cpr->cp_ring_struct->ring_size;
3205
3206         /*
3207          * For the vector receive case, the completion at the requested
3208          * offset can be indexed directly.
3209          */
3210 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3211         if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3212                 struct rx_pkt_cmpl *rxcmp;
3213                 uint32_t cons;
3214
3215                 /* Check status of completion descriptor. */
3216                 raw_cons = cpr->cp_raw_cons +
3217                            offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3218                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3219                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3220
3221                 if (bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3222                         return RTE_ETH_RX_DESC_DONE;
3223
3224                 /* Check whether rx desc has an mbuf attached. */
3225                 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3226                 if (cons >= rxq->rxrearm_start &&
3227                     cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3228                         return RTE_ETH_RX_DESC_UNAVAIL;
3229                 }
3230
3231                 return RTE_ETH_RX_DESC_AVAIL;
3232         }
3233 #endif
3234
3235         /*
3236          * For the non-vector receive case, scan the completion ring to
3237          * locate the completion descriptor for the requested offset.
3238          */
3239         raw_cons = cpr->cp_raw_cons;
3240         desc = 0;
3241         while (1) {
3242                 uint32_t agg_cnt, cons, cmpl_type;
3243
3244                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3245                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3246
3247                 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3248                         break;
3249
3250                 cmpl_type = CMP_TYPE(rxcmp);
3251
3252                 switch (cmpl_type) {
3253                 case CMPL_BASE_TYPE_RX_L2:
3254                 case CMPL_BASE_TYPE_RX_L2_V2:
3255                         if (desc == offset) {
3256                                 cons = rxcmp->opaque;
3257                                 if (rxr->rx_buf_ring[cons])
3258                                         return RTE_ETH_RX_DESC_DONE;
3259                                 else
3260                                         return RTE_ETH_RX_DESC_UNAVAIL;
3261                         }
3262                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3263                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3264                         desc++;
3265                         break;
3266
3267                 case CMPL_BASE_TYPE_RX_TPA_END:
3268                         if (desc == offset)
3269                                 return RTE_ETH_RX_DESC_DONE;
3270
3271                         if (BNXT_CHIP_P5(rxq->bp)) {
3272                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3273
3274                                 p5_tpa_end = (void *)rxcmp;
3275                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3276                         } else {
3277                                 struct rx_tpa_end_cmpl *tpa_end;
3278
3279                                 tpa_end = (void *)rxcmp;
3280                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3281                         }
3282
3283                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3284                         desc++;
3285                         break;
3286
3287                 default:
3288                         raw_cons += CMP_LEN(cmpl_type);
3289                 }
3290         }
3291
3292         return RTE_ETH_RX_DESC_AVAIL;
3293 }
3294
3295 static int
3296 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3297 {
3298         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3299         struct bnxt_cp_ring_info *cpr = txq->cp_ring;
3300         uint32_t ring_mask, raw_cons, nb_tx_pkts = 0;
3301         struct cmpl_base *cp_desc_ring;
3302         int rc;
3303
3304         rc = is_bnxt_in_error(txq->bp);
3305         if (rc)
3306                 return rc;
3307
3308         if (offset >= txq->nb_tx_desc)
3309                 return -EINVAL;
3310
3311         /* Return "desc done" if descriptor is available for use. */
3312         if (bnxt_tx_bds_in_hw(txq) <= offset)
3313                 return RTE_ETH_TX_DESC_DONE;
3314
3315         raw_cons = cpr->cp_raw_cons;
3316         cp_desc_ring = cpr->cp_desc_ring;
3317         ring_mask = cpr->cp_ring_struct->ring_mask;
3318
3319         /* Check to see if hw has posted a completion for the descriptor. */
3320         while (1) {
3321                 struct tx_cmpl *txcmp;
3322                 uint32_t cons;
3323
3324                 cons = RING_CMPL(ring_mask, raw_cons);
3325                 txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
3326
3327                 if (!bnxt_cpr_cmp_valid(txcmp, raw_cons, ring_mask + 1))
3328                         break;
3329
3330                 if (CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2)
3331                         nb_tx_pkts += rte_le_to_cpu_32(txcmp->opaque);
3332
3333                 if (nb_tx_pkts > offset)
3334                         return RTE_ETH_TX_DESC_DONE;
3335
3336                 raw_cons = NEXT_RAW_CMP(raw_cons);
3337         }
3338
3339         /* Descriptor is pending transmit, not yet completed by hardware. */
3340         return RTE_ETH_TX_DESC_FULL;
3341 }
3342
3343 int
3344 bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
3345                      const struct rte_flow_ops **ops)
3346 {
3347         struct bnxt *bp = dev->data->dev_private;
3348         int ret = 0;
3349
3350         if (!bp)
3351                 return -EIO;
3352
3353         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3354                 struct bnxt_representor *vfr = dev->data->dev_private;
3355                 bp = vfr->parent_dev->data->dev_private;
3356                 /* parent is deleted while children are still valid */
3357                 if (!bp) {
3358                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n",
3359                                     dev->data->port_id);
3360                         return -EIO;
3361                 }
3362         }
3363
3364         ret = is_bnxt_in_error(bp);
3365         if (ret)
3366                 return ret;
3367
3368         /* PMD supports thread-safe flow operations.  rte_flow API
3369          * functions can avoid mutex for multi-thread safety.
3370          */
3371         dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3372
3373         if (BNXT_TRUFLOW_EN(bp))
3374                 *ops = &bnxt_ulp_rte_flow_ops;
3375         else
3376                 *ops = &bnxt_flow_ops;
3377
3378         return ret;
3379 }
3380
3381 static const uint32_t *
3382 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3383 {
3384         static const uint32_t ptypes[] = {
3385                 RTE_PTYPE_L2_ETHER_VLAN,
3386                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3387                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3388                 RTE_PTYPE_L4_ICMP,
3389                 RTE_PTYPE_L4_TCP,
3390                 RTE_PTYPE_L4_UDP,
3391                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3392                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3393                 RTE_PTYPE_INNER_L4_ICMP,
3394                 RTE_PTYPE_INNER_L4_TCP,
3395                 RTE_PTYPE_INNER_L4_UDP,
3396                 RTE_PTYPE_UNKNOWN
3397         };
3398
3399         if (!dev->rx_pkt_burst)
3400                 return NULL;
3401
3402         return ptypes;
3403 }
3404
3405 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3406                          int reg_win)
3407 {
3408         uint32_t reg_base = *reg_arr & 0xfffff000;
3409         uint32_t win_off;
3410         int i;
3411
3412         for (i = 0; i < count; i++) {
3413                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3414                         return -ERANGE;
3415         }
3416         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3417         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3418         return 0;
3419 }
3420
3421 static int bnxt_map_ptp_regs(struct bnxt *bp)
3422 {
3423         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3424         uint32_t *reg_arr;
3425         int rc, i;
3426
3427         reg_arr = ptp->rx_regs;
3428         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3429         if (rc)
3430                 return rc;
3431
3432         reg_arr = ptp->tx_regs;
3433         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3434         if (rc)
3435                 return rc;
3436
3437         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3438                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3439
3440         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3441                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3442
3443         return 0;
3444 }
3445
3446 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3447 {
3448         rte_write32(0, (uint8_t *)bp->bar0 +
3449                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3450         rte_write32(0, (uint8_t *)bp->bar0 +
3451                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3452 }
3453
3454 static uint64_t bnxt_cc_read(struct bnxt *bp)
3455 {
3456         uint64_t ns;
3457
3458         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3459                               BNXT_GRCPF_REG_SYNC_TIME));
3460         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3461                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3462         return ns;
3463 }
3464
3465 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3466 {
3467         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3468         uint32_t fifo;
3469
3470         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3471                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3472         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3473                 return -EAGAIN;
3474
3475         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3476                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3477         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3478                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3479         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3480                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3481         rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]);
3482
3483         return 0;
3484 }
3485
3486 static int bnxt_clr_rx_ts(struct bnxt *bp, uint64_t *last_ts)
3487 {
3488         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3489         struct bnxt_pf_info *pf = bp->pf;
3490         uint16_t port_id;
3491         int i = 0;
3492         uint32_t fifo;
3493
3494         if (!ptp || (bp->flags & BNXT_FLAG_CHIP_P5))
3495                 return -EINVAL;
3496
3497         port_id = pf->port_id;
3498         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3499                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3500         while ((fifo & BNXT_PTP_RX_FIFO_PENDING) && (i < BNXT_PTP_RX_PND_CNT)) {
3501                 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3502                             ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3503                 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3504                                         ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3505                 *last_ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3506                                         ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3507                 *last_ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3508                                         ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3509                 i++;
3510         }
3511
3512         if (i >= BNXT_PTP_RX_PND_CNT)
3513                 return -EBUSY;
3514
3515         return 0;
3516 }
3517
3518 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3519 {
3520         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3521         struct bnxt_pf_info *pf = bp->pf;
3522         uint16_t port_id;
3523         uint32_t fifo;
3524
3525         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3526                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3527         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3528                 return -EAGAIN;
3529
3530         port_id = pf->port_id;
3531         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3532                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3533
3534         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3535                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3536         if (fifo & BNXT_PTP_RX_FIFO_PENDING)
3537                 return bnxt_clr_rx_ts(bp, ts);
3538
3539         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3540                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3541         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3542                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3543
3544         return 0;
3545 }
3546
3547 static int
3548 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3549 {
3550         uint64_t ns;
3551         struct bnxt *bp = dev->data->dev_private;
3552         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3553
3554         if (!ptp)
3555                 return -ENOTSUP;
3556
3557         ns = rte_timespec_to_ns(ts);
3558         /* Set the timecounters to a new value. */
3559         ptp->tc.nsec = ns;
3560         ptp->tx_tstamp_tc.nsec = ns;
3561         ptp->rx_tstamp_tc.nsec = ns;
3562
3563         return 0;
3564 }
3565
3566 static int
3567 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3568 {
3569         struct bnxt *bp = dev->data->dev_private;
3570         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3571         uint64_t ns, systime_cycles = 0;
3572         int rc = 0;
3573
3574         if (!ptp)
3575                 return -ENOTSUP;
3576
3577         if (BNXT_CHIP_P5(bp))
3578                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3579                                              &systime_cycles);
3580         else
3581                 systime_cycles = bnxt_cc_read(bp);
3582
3583         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3584         *ts = rte_ns_to_timespec(ns);
3585
3586         return rc;
3587 }
3588 static int
3589 bnxt_timesync_enable(struct rte_eth_dev *dev)
3590 {
3591         struct bnxt *bp = dev->data->dev_private;
3592         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3593         uint32_t shift = 0;
3594         int rc;
3595
3596         if (!ptp)
3597                 return -ENOTSUP;
3598
3599         ptp->rx_filter = 1;
3600         ptp->tx_tstamp_en = 1;
3601         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3602
3603         rc = bnxt_hwrm_ptp_cfg(bp);
3604         if (rc)
3605                 return rc;
3606
3607         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3608         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3609         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3610
3611         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3612         ptp->tc.cc_shift = shift;
3613         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3614
3615         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3616         ptp->rx_tstamp_tc.cc_shift = shift;
3617         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3618
3619         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3620         ptp->tx_tstamp_tc.cc_shift = shift;
3621         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3622
3623         if (!BNXT_CHIP_P5(bp))
3624                 bnxt_map_ptp_regs(bp);
3625         else
3626                 rc = bnxt_ptp_start(bp);
3627
3628         return rc;
3629 }
3630
3631 static int
3632 bnxt_timesync_disable(struct rte_eth_dev *dev)
3633 {
3634         struct bnxt *bp = dev->data->dev_private;
3635         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3636
3637         if (!ptp)
3638                 return -ENOTSUP;
3639
3640         ptp->rx_filter = 0;
3641         ptp->tx_tstamp_en = 0;
3642         ptp->rxctl = 0;
3643
3644         bnxt_hwrm_ptp_cfg(bp);
3645
3646         if (!BNXT_CHIP_P5(bp))
3647                 bnxt_unmap_ptp_regs(bp);
3648         else
3649                 bnxt_ptp_stop(bp);
3650
3651         return 0;
3652 }
3653
3654 static int
3655 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3656                                  struct timespec *timestamp,
3657                                  uint32_t flags __rte_unused)
3658 {
3659         struct bnxt *bp = dev->data->dev_private;
3660         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3661         uint64_t rx_tstamp_cycles = 0;
3662         uint64_t ns;
3663
3664         if (!ptp)
3665                 return -ENOTSUP;
3666
3667         if (BNXT_CHIP_P5(bp))
3668                 rx_tstamp_cycles = ptp->rx_timestamp;
3669         else
3670                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3671
3672         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3673         *timestamp = rte_ns_to_timespec(ns);
3674         return  0;
3675 }
3676
3677 static int
3678 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3679                                  struct timespec *timestamp)
3680 {
3681         struct bnxt *bp = dev->data->dev_private;
3682         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3683         uint64_t tx_tstamp_cycles = 0;
3684         uint64_t ns;
3685         int rc = 0;
3686
3687         if (!ptp)
3688                 return -ENOTSUP;
3689
3690         if (BNXT_CHIP_P5(bp))
3691                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3692                                              &tx_tstamp_cycles);
3693         else
3694                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3695
3696         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3697         *timestamp = rte_ns_to_timespec(ns);
3698
3699         return rc;
3700 }
3701
3702 static int
3703 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3704 {
3705         struct bnxt *bp = dev->data->dev_private;
3706         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3707
3708         if (!ptp)
3709                 return -ENOTSUP;
3710
3711         ptp->tc.nsec += delta;
3712         ptp->tx_tstamp_tc.nsec += delta;
3713         ptp->rx_tstamp_tc.nsec += delta;
3714
3715         return 0;
3716 }
3717
3718 static int
3719 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3720 {
3721         struct bnxt *bp = dev->data->dev_private;
3722         int rc;
3723         uint32_t dir_entries;
3724         uint32_t entry_length;
3725
3726         rc = is_bnxt_in_error(bp);
3727         if (rc)
3728                 return rc;
3729
3730         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3731                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3732                     bp->pdev->addr.devid, bp->pdev->addr.function);
3733
3734         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3735         if (rc != 0)
3736                 return rc;
3737
3738         return dir_entries * entry_length;
3739 }
3740
3741 static int
3742 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3743                 struct rte_dev_eeprom_info *in_eeprom)
3744 {
3745         struct bnxt *bp = dev->data->dev_private;
3746         uint32_t index;
3747         uint32_t offset;
3748         int rc;
3749
3750         rc = is_bnxt_in_error(bp);
3751         if (rc)
3752                 return rc;
3753
3754         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3755                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3756                     bp->pdev->addr.devid, bp->pdev->addr.function,
3757                     in_eeprom->offset, in_eeprom->length);
3758
3759         if (in_eeprom->offset == 0) /* special offset value to get directory */
3760                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3761                                                 in_eeprom->data);
3762
3763         index = in_eeprom->offset >> 24;
3764         offset = in_eeprom->offset & 0xffffff;
3765
3766         if (index != 0)
3767                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3768                                            in_eeprom->length, in_eeprom->data);
3769
3770         return 0;
3771 }
3772
3773 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3774 {
3775         switch (dir_type) {
3776         case BNX_DIR_TYPE_CHIMP_PATCH:
3777         case BNX_DIR_TYPE_BOOTCODE:
3778         case BNX_DIR_TYPE_BOOTCODE_2:
3779         case BNX_DIR_TYPE_APE_FW:
3780         case BNX_DIR_TYPE_APE_PATCH:
3781         case BNX_DIR_TYPE_KONG_FW:
3782         case BNX_DIR_TYPE_KONG_PATCH:
3783         case BNX_DIR_TYPE_BONO_FW:
3784         case BNX_DIR_TYPE_BONO_PATCH:
3785                 /* FALLTHROUGH */
3786                 return true;
3787         }
3788
3789         return false;
3790 }
3791
3792 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3793 {
3794         switch (dir_type) {
3795         case BNX_DIR_TYPE_AVS:
3796         case BNX_DIR_TYPE_EXP_ROM_MBA:
3797         case BNX_DIR_TYPE_PCIE:
3798         case BNX_DIR_TYPE_TSCF_UCODE:
3799         case BNX_DIR_TYPE_EXT_PHY:
3800         case BNX_DIR_TYPE_CCM:
3801         case BNX_DIR_TYPE_ISCSI_BOOT:
3802         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3803         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3804                 /* FALLTHROUGH */
3805                 return true;
3806         }
3807
3808         return false;
3809 }
3810
3811 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3812 {
3813         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3814                 bnxt_dir_type_is_other_exec_format(dir_type);
3815 }
3816
3817 static int
3818 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3819                 struct rte_dev_eeprom_info *in_eeprom)
3820 {
3821         struct bnxt *bp = dev->data->dev_private;
3822         uint8_t index, dir_op;
3823         uint16_t type, ext, ordinal, attr;
3824         int rc;
3825
3826         rc = is_bnxt_in_error(bp);
3827         if (rc)
3828                 return rc;
3829
3830         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3831                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3832                     bp->pdev->addr.devid, bp->pdev->addr.function,
3833                     in_eeprom->offset, in_eeprom->length);
3834
3835         if (!BNXT_PF(bp)) {
3836                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3837                 return -EINVAL;
3838         }
3839
3840         type = in_eeprom->magic >> 16;
3841
3842         if (type == 0xffff) { /* special value for directory operations */
3843                 index = in_eeprom->magic & 0xff;
3844                 dir_op = in_eeprom->magic >> 8;
3845                 if (index == 0)
3846                         return -EINVAL;
3847                 switch (dir_op) {
3848                 case 0x0e: /* erase */
3849                         if (in_eeprom->offset != ~in_eeprom->magic)
3850                                 return -EINVAL;
3851                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3852                 default:
3853                         return -EINVAL;
3854                 }
3855         }
3856
3857         /* Create or re-write an NVM item: */
3858         if (bnxt_dir_type_is_executable(type) == true)
3859                 return -EOPNOTSUPP;
3860         ext = in_eeprom->magic & 0xffff;
3861         ordinal = in_eeprom->offset >> 16;
3862         attr = in_eeprom->offset & 0xffff;
3863
3864         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3865                                      in_eeprom->data, in_eeprom->length);
3866 }
3867
3868 static int bnxt_get_module_info(struct rte_eth_dev *dev,
3869                                 struct rte_eth_dev_module_info *modinfo)
3870 {
3871         uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3872         struct bnxt *bp = dev->data->dev_private;
3873         int rc;
3874
3875         /* No point in going further if phy status indicates
3876          * module is not inserted or if it is powered down or
3877          * if it is of type 10GBase-T
3878          */
3879         if (bp->link_info->module_status >
3880             HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG) {
3881                 PMD_DRV_LOG(NOTICE, "Port %u : Module is not inserted or is powered down\n",
3882                             dev->data->port_id);
3883                 return -ENOTSUP;
3884         }
3885
3886         /* This feature is not supported in older firmware versions */
3887         if (bp->hwrm_spec_code < 0x10202) {
3888                 PMD_DRV_LOG(NOTICE, "Port %u : Feature is not supported in older firmware\n",
3889                             dev->data->port_id);
3890                 return -ENOTSUP;
3891         }
3892
3893         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3894                                                    SFF_DIAG_SUPPORT_OFFSET + 1,
3895                                                    module_info);
3896
3897         if (rc)
3898                 return rc;
3899
3900         switch (module_info[0]) {
3901         case SFF_MODULE_ID_SFP:
3902                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
3903                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
3904                 if (module_info[SFF_DIAG_SUPPORT_OFFSET] == 0)
3905                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3906                 break;
3907         case SFF_MODULE_ID_QSFP:
3908         case SFF_MODULE_ID_QSFP_PLUS:
3909                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
3910                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3911                 break;
3912         case SFF_MODULE_ID_QSFP28:
3913                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
3914                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
3915                 if (module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK)
3916                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_LEN;
3917                 break;
3918         default:
3919                 PMD_DRV_LOG(NOTICE, "Port %u : Unsupported module\n", dev->data->port_id);
3920                 return -ENOTSUP;
3921         }
3922
3923         PMD_DRV_LOG(INFO, "Port %u : modinfo->type = %d modinfo->eeprom_len = %d\n",
3924                     dev->data->port_id, modinfo->type, modinfo->eeprom_len);
3925
3926         return 0;
3927 }
3928
3929 static int bnxt_get_module_eeprom(struct rte_eth_dev *dev,
3930                                   struct rte_dev_eeprom_info *info)
3931 {
3932         uint8_t pg_addr[5] = { I2C_DEV_ADDR_A0, I2C_DEV_ADDR_A0 };
3933         uint32_t offset = info->offset, length = info->length;
3934         uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3935         struct bnxt *bp = dev->data->dev_private;
3936         uint8_t *data = info->data;
3937         uint8_t page = offset >> 7;
3938         uint8_t max_pages = 2;
3939         uint8_t opt_pages;
3940         int rc;
3941
3942         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3943                                                    SFF_DIAG_SUPPORT_OFFSET + 1,
3944                                                    module_info);
3945         if (rc)
3946                 return rc;
3947
3948         switch (module_info[0]) {
3949         case SFF_MODULE_ID_SFP:
3950                 module_info[SFF_DIAG_SUPPORT_OFFSET] = 0;
3951                 if (module_info[SFF_DIAG_SUPPORT_OFFSET]) {
3952                         pg_addr[2] = I2C_DEV_ADDR_A2;
3953                         pg_addr[3] = I2C_DEV_ADDR_A2;
3954                         max_pages = 4;
3955                 }
3956                 break;
3957         case SFF_MODULE_ID_QSFP28:
3958                 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0,
3959                                                            SFF8636_OPT_PAGES_OFFSET,
3960                                                            1, &opt_pages);
3961                 if (rc)
3962                         return rc;
3963
3964                 if (opt_pages & SFF8636_PAGE1_MASK) {
3965                         pg_addr[2] = I2C_DEV_ADDR_A0;
3966                         max_pages = 3;
3967                 }
3968                 if (opt_pages & SFF8636_PAGE2_MASK) {
3969                         pg_addr[3] = I2C_DEV_ADDR_A0;
3970                         max_pages = 4;
3971                 }
3972                 if (~module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK) {
3973                         pg_addr[4] = I2C_DEV_ADDR_A0;
3974                         max_pages = 5;
3975                 }
3976                 break;
3977         default:
3978                 break;
3979         }
3980
3981         memset(data, 0, length);
3982
3983         offset &= 0xff;
3984         while (length && page < max_pages) {
3985                 uint8_t raw_page = page ? page - 1 : 0;
3986                 uint16_t chunk;
3987
3988                 if (pg_addr[page] == I2C_DEV_ADDR_A2)
3989                         raw_page = 0;
3990                 else if (page)
3991                         offset |= 0x80;
3992                 chunk = RTE_MIN(length, 256 - offset);
3993
3994                 if (pg_addr[page]) {
3995                         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, pg_addr[page],
3996                                                                    raw_page, offset,
3997                                                                    chunk, data);
3998                         if (rc)
3999                                 return rc;
4000                 }
4001
4002                 data += chunk;
4003                 length -= chunk;
4004                 offset = 0;
4005                 page += 1 + (chunk > 128);
4006         }
4007
4008         return length ? -EINVAL : 0;
4009 }
4010
4011 /*
4012  * Initialization
4013  */
4014
4015 static const struct eth_dev_ops bnxt_dev_ops = {
4016         .dev_infos_get = bnxt_dev_info_get_op,
4017         .dev_close = bnxt_dev_close_op,
4018         .dev_configure = bnxt_dev_configure_op,
4019         .dev_start = bnxt_dev_start_op,
4020         .dev_stop = bnxt_dev_stop_op,
4021         .dev_set_link_up = bnxt_dev_set_link_up_op,
4022         .dev_set_link_down = bnxt_dev_set_link_down_op,
4023         .stats_get = bnxt_stats_get_op,
4024         .stats_reset = bnxt_stats_reset_op,
4025         .rx_queue_setup = bnxt_rx_queue_setup_op,
4026         .rx_queue_release = bnxt_rx_queue_release_op,
4027         .tx_queue_setup = bnxt_tx_queue_setup_op,
4028         .tx_queue_release = bnxt_tx_queue_release_op,
4029         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4030         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4031         .reta_update = bnxt_reta_update_op,
4032         .reta_query = bnxt_reta_query_op,
4033         .rss_hash_update = bnxt_rss_hash_update_op,
4034         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4035         .link_update = bnxt_link_update_op,
4036         .promiscuous_enable = bnxt_promiscuous_enable_op,
4037         .promiscuous_disable = bnxt_promiscuous_disable_op,
4038         .allmulticast_enable = bnxt_allmulticast_enable_op,
4039         .allmulticast_disable = bnxt_allmulticast_disable_op,
4040         .mac_addr_add = bnxt_mac_addr_add_op,
4041         .mac_addr_remove = bnxt_mac_addr_remove_op,
4042         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4043         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4044         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4045         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4046         .vlan_filter_set = bnxt_vlan_filter_set_op,
4047         .vlan_offload_set = bnxt_vlan_offload_set_op,
4048         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4049         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4050         .mtu_set = bnxt_mtu_set_op,
4051         .mac_addr_set = bnxt_set_default_mac_addr_op,
4052         .xstats_get = bnxt_dev_xstats_get_op,
4053         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4054         .xstats_reset = bnxt_dev_xstats_reset_op,
4055         .fw_version_get = bnxt_fw_version_get,
4056         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4057         .rxq_info_get = bnxt_rxq_info_get_op,
4058         .txq_info_get = bnxt_txq_info_get_op,
4059         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4060         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4061         .dev_led_on = bnxt_dev_led_on_op,
4062         .dev_led_off = bnxt_dev_led_off_op,
4063         .rx_queue_start = bnxt_rx_queue_start,
4064         .rx_queue_stop = bnxt_rx_queue_stop,
4065         .tx_queue_start = bnxt_tx_queue_start,
4066         .tx_queue_stop = bnxt_tx_queue_stop,
4067         .flow_ops_get = bnxt_flow_ops_get_op,
4068         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4069         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4070         .get_eeprom           = bnxt_get_eeprom_op,
4071         .set_eeprom           = bnxt_set_eeprom_op,
4072         .get_module_info = bnxt_get_module_info,
4073         .get_module_eeprom = bnxt_get_module_eeprom,
4074         .timesync_enable      = bnxt_timesync_enable,
4075         .timesync_disable     = bnxt_timesync_disable,
4076         .timesync_read_time   = bnxt_timesync_read_time,
4077         .timesync_write_time   = bnxt_timesync_write_time,
4078         .timesync_adjust_time = bnxt_timesync_adjust_time,
4079         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4080         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4081 };
4082
4083 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4084 {
4085         uint32_t offset;
4086
4087         /* Only pre-map the reset GRC registers using window 3 */
4088         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4089                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4090
4091         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4092
4093         return offset;
4094 }
4095
4096 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4097 {
4098         struct bnxt_error_recovery_info *info = bp->recovery_info;
4099         uint32_t reg_base = 0xffffffff;
4100         int i;
4101
4102         /* Only pre-map the monitoring GRC registers using window 2 */
4103         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4104                 uint32_t reg = info->status_regs[i];
4105
4106                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4107                         continue;
4108
4109                 if (reg_base == 0xffffffff)
4110                         reg_base = reg & 0xfffff000;
4111                 if ((reg & 0xfffff000) != reg_base)
4112                         return -ERANGE;
4113
4114                 /* Use mask 0xffc as the Lower 2 bits indicates
4115                  * address space location
4116                  */
4117                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4118                                                 (reg & 0xffc);
4119         }
4120
4121         if (reg_base == 0xffffffff)
4122                 return 0;
4123
4124         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4125                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4126
4127         return 0;
4128 }
4129
4130 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4131 {
4132         struct bnxt_error_recovery_info *info = bp->recovery_info;
4133         uint32_t delay = info->delay_after_reset[index];
4134         uint32_t val = info->reset_reg_val[index];
4135         uint32_t reg = info->reset_reg[index];
4136         uint32_t type, offset;
4137         int ret;
4138
4139         type = BNXT_FW_STATUS_REG_TYPE(reg);
4140         offset = BNXT_FW_STATUS_REG_OFF(reg);
4141
4142         switch (type) {
4143         case BNXT_FW_STATUS_REG_TYPE_CFG:
4144                 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4145                 if (ret < 0) {
4146                         PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x",
4147                                     val, offset);
4148                         return;
4149                 }
4150                 break;
4151         case BNXT_FW_STATUS_REG_TYPE_GRC:
4152                 offset = bnxt_map_reset_regs(bp, offset);
4153                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4154                 break;
4155         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4156                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4157                 break;
4158         }
4159         /* wait on a specific interval of time until core reset is complete */
4160         if (delay)
4161                 rte_delay_ms(delay);
4162 }
4163
4164 static void bnxt_dev_cleanup(struct bnxt *bp)
4165 {
4166         bp->eth_dev->data->dev_link.link_status = 0;
4167         bp->link_info->link_up = 0;
4168         if (bp->eth_dev->data->dev_started)
4169                 bnxt_dev_stop(bp->eth_dev);
4170
4171         bnxt_uninit_resources(bp, true);
4172 }
4173
4174 static int
4175 bnxt_check_fw_reset_done(struct bnxt *bp)
4176 {
4177         int timeout = bp->fw_reset_max_msecs;
4178         uint16_t val = 0;
4179         int rc;
4180
4181         do {
4182                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4183                 if (rc < 0) {
4184                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4185                         return rc;
4186                 }
4187                 if (val != 0xffff)
4188                         break;
4189                 rte_delay_ms(1);
4190         } while (timeout--);
4191
4192         if (val == 0xffff) {
4193                 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
4194                 return -1;
4195         }
4196
4197         return 0;
4198 }
4199
4200 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4201 {
4202         struct rte_eth_dev *dev = bp->eth_dev;
4203         struct rte_vlan_filter_conf *vfc;
4204         int vidx, vbit, rc;
4205         uint16_t vlan_id;
4206
4207         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4208                 vfc = &dev->data->vlan_filter_conf;
4209                 vidx = vlan_id / 64;
4210                 vbit = vlan_id % 64;
4211
4212                 /* Each bit corresponds to a VLAN id */
4213                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4214                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4215                         if (rc)
4216                                 return rc;
4217                 }
4218         }
4219
4220         return 0;
4221 }
4222
4223 static int bnxt_restore_mac_filters(struct bnxt *bp)
4224 {
4225         struct rte_eth_dev *dev = bp->eth_dev;
4226         struct rte_eth_dev_info dev_info;
4227         struct rte_ether_addr *addr;
4228         uint64_t pool_mask;
4229         uint32_t pool = 0;
4230         uint32_t i;
4231         int rc;
4232
4233         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4234                 return 0;
4235
4236         rc = bnxt_dev_info_get_op(dev, &dev_info);
4237         if (rc)
4238                 return rc;
4239
4240         /* replay MAC address configuration */
4241         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4242                 addr = &dev->data->mac_addrs[i];
4243
4244                 /* skip zero address */
4245                 if (rte_is_zero_ether_addr(addr))
4246                         continue;
4247
4248                 pool = 0;
4249                 pool_mask = dev->data->mac_pool_sel[i];
4250
4251                 do {
4252                         if (pool_mask & 1ULL) {
4253                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4254                                 if (rc)
4255                                         return rc;
4256                         }
4257                         pool_mask >>= 1;
4258                         pool++;
4259                 } while (pool_mask);
4260         }
4261
4262         return 0;
4263 }
4264
4265 static int bnxt_restore_mcast_mac_filters(struct bnxt *bp)
4266 {
4267         int ret = 0;
4268
4269         ret = bnxt_dev_set_mc_addr_list_op(bp->eth_dev, bp->mcast_addr_list,
4270                                            bp->nb_mc_addr);
4271         if (ret)
4272                 PMD_DRV_LOG(ERR, "Failed to restore multicast MAC addreeses\n");
4273
4274         return ret;
4275 }
4276
4277 static int bnxt_restore_filters(struct bnxt *bp)
4278 {
4279         struct rte_eth_dev *dev = bp->eth_dev;
4280         int ret = 0;
4281
4282         if (dev->data->all_multicast) {
4283                 ret = bnxt_allmulticast_enable_op(dev);
4284                 if (ret)
4285                         return ret;
4286         }
4287         if (dev->data->promiscuous) {
4288                 ret = bnxt_promiscuous_enable_op(dev);
4289                 if (ret)
4290                         return ret;
4291         }
4292
4293         ret = bnxt_restore_mac_filters(bp);
4294         if (ret)
4295                 return ret;
4296
4297         /* if vlans are already programmed, this can fail with -EEXIST */
4298         ret = bnxt_restore_vlan_filters(bp);
4299         if (ret && ret != -EEXIST)
4300                 return ret;
4301
4302         ret = bnxt_restore_mcast_mac_filters(bp);
4303         if (ret)
4304                 return ret;
4305
4306         return ret;
4307 }
4308
4309 static int bnxt_check_fw_ready(struct bnxt *bp)
4310 {
4311         int timeout = bp->fw_reset_max_msecs;
4312         int rc = 0;
4313
4314         do {
4315                 rc = bnxt_hwrm_poll_ver_get(bp);
4316                 if (rc == 0)
4317                         break;
4318                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4319                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4320         } while (rc && timeout > 0);
4321
4322         if (rc)
4323                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4324
4325         return rc;
4326 }
4327
4328 static void bnxt_dev_recover(void *arg)
4329 {
4330         struct bnxt *bp = arg;
4331         int rc = 0;
4332
4333         pthread_mutex_lock(&bp->err_recovery_lock);
4334
4335         if (!bp->fw_reset_min_msecs) {
4336                 rc = bnxt_check_fw_reset_done(bp);
4337                 if (rc)
4338                         goto err;
4339         }
4340
4341         /* Clear Error flag so that device re-init should happen */
4342         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4343         PMD_DRV_LOG(INFO, "Port: %u Starting recovery...\n",
4344                     bp->eth_dev->data->port_id);
4345
4346         rc = bnxt_check_fw_ready(bp);
4347         if (rc)
4348                 goto err;
4349
4350         rc = bnxt_init_resources(bp, true);
4351         if (rc) {
4352                 PMD_DRV_LOG(ERR,
4353                             "Failed to initialize resources after reset\n");
4354                 goto err;
4355         }
4356         /* clear reset flag as the device is initialized now */
4357         bp->flags &= ~BNXT_FLAG_FW_RESET;
4358
4359         rc = bnxt_dev_start_op(bp->eth_dev);
4360         if (rc) {
4361                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4362                 goto err_start;
4363         }
4364
4365         rc = bnxt_restore_filters(bp);
4366         if (rc)
4367                 goto err_start;
4368
4369         rte_eth_fp_ops[bp->eth_dev->data->port_id].rx_pkt_burst =
4370                 bp->eth_dev->rx_pkt_burst;
4371         rte_eth_fp_ops[bp->eth_dev->data->port_id].tx_pkt_burst =
4372                 bp->eth_dev->tx_pkt_burst;
4373         rte_mb();
4374
4375         PMD_DRV_LOG(INFO, "Port: %u Recovered from FW reset\n",
4376                     bp->eth_dev->data->port_id);
4377         pthread_mutex_unlock(&bp->err_recovery_lock);
4378
4379         return;
4380 err_start:
4381         bnxt_dev_stop(bp->eth_dev);
4382 err:
4383         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4384         bnxt_uninit_resources(bp, false);
4385         if (bp->eth_dev->data->dev_conf.intr_conf.rmv)
4386                 rte_eth_dev_callback_process(bp->eth_dev,
4387                                              RTE_ETH_EVENT_INTR_RMV,
4388                                              NULL);
4389         pthread_mutex_unlock(&bp->err_recovery_lock);
4390         PMD_DRV_LOG(ERR, "Port %u: Failed to recover from FW reset\n",
4391                     bp->eth_dev->data->port_id);
4392 }
4393
4394 void bnxt_dev_reset_and_resume(void *arg)
4395 {
4396         struct bnxt *bp = arg;
4397         uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4398         uint16_t val = 0;
4399         int rc;
4400
4401         bnxt_dev_cleanup(bp);
4402         PMD_DRV_LOG(INFO, "Port: %u Finished bnxt_dev_cleanup\n",
4403                     bp->eth_dev->data->port_id);
4404
4405         bnxt_wait_for_device_shutdown(bp);
4406
4407         /* During some fatal firmware error conditions, the PCI config space
4408          * register 0x2e which normally contains the subsystem ID will become
4409          * 0xffff. This register will revert back to the normal value after
4410          * the chip has completed core reset. If we detect this condition,
4411          * we can poll this config register immediately for the value to revert.
4412          */
4413         if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4414                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4415                 if (rc < 0) {
4416                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4417                         return;
4418                 }
4419                 if (val == 0xffff) {
4420                         bp->fw_reset_min_msecs = 0;
4421                         us = 1;
4422                 }
4423         }
4424
4425         rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4426         if (rc)
4427                 PMD_DRV_LOG(ERR, "Port %u: Error setting recovery alarm",
4428                             bp->eth_dev->data->port_id);
4429 }
4430
4431 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4432 {
4433         struct bnxt_error_recovery_info *info = bp->recovery_info;
4434         uint32_t reg = info->status_regs[index];
4435         uint32_t type, offset, val = 0;
4436         int ret = 0;
4437
4438         type = BNXT_FW_STATUS_REG_TYPE(reg);
4439         offset = BNXT_FW_STATUS_REG_OFF(reg);
4440
4441         switch (type) {
4442         case BNXT_FW_STATUS_REG_TYPE_CFG:
4443                 ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4444                 if (ret < 0)
4445                         PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x",
4446                                     offset);
4447                 break;
4448         case BNXT_FW_STATUS_REG_TYPE_GRC:
4449                 offset = info->mapped_status_regs[index];
4450                 /* FALLTHROUGH */
4451         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4452                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4453                                        offset));
4454                 break;
4455         }
4456
4457         return val;
4458 }
4459
4460 static int bnxt_fw_reset_all(struct bnxt *bp)
4461 {
4462         struct bnxt_error_recovery_info *info = bp->recovery_info;
4463         uint32_t i;
4464         int rc = 0;
4465
4466         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4467                 /* Reset through primary function driver */
4468                 for (i = 0; i < info->reg_array_cnt; i++)
4469                         bnxt_write_fw_reset_reg(bp, i);
4470                 /* Wait for time specified by FW after triggering reset */
4471                 rte_delay_ms(info->primary_func_wait_period_after_reset);
4472         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4473                 /* Reset with the help of Kong processor */
4474                 rc = bnxt_hwrm_fw_reset(bp);
4475                 if (rc)
4476                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4477         }
4478
4479         return rc;
4480 }
4481
4482 static void bnxt_fw_reset_cb(void *arg)
4483 {
4484         struct bnxt *bp = arg;
4485         struct bnxt_error_recovery_info *info = bp->recovery_info;
4486         int rc = 0;
4487
4488         /* Only Primary function can do FW reset */
4489         if (bnxt_is_primary_func(bp) &&
4490             bnxt_is_recovery_enabled(bp)) {
4491                 rc = bnxt_fw_reset_all(bp);
4492                 if (rc) {
4493                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4494                         return;
4495                 }
4496         }
4497
4498         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4499          * EXCEPTION_FATAL_ASYNC event to all the functions
4500          * (including MASTER FUNC). After receiving this Async, all the active
4501          * drivers should treat this case as FW initiated recovery
4502          */
4503         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4504                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4505                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4506
4507                 /* To recover from error */
4508                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4509                                   (void *)bp);
4510         }
4511 }
4512
4513 /* Driver should poll FW heartbeat, reset_counter with the frequency
4514  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4515  * When the driver detects heartbeat stop or change in reset_counter,
4516  * it has to trigger a reset to recover from the error condition.
4517  * A “primary function” is the function who will have the privilege to
4518  * initiate the chimp reset. The primary function will be elected by the
4519  * firmware and will be notified through async message.
4520  */
4521 static void bnxt_check_fw_health(void *arg)
4522 {
4523         struct bnxt *bp = arg;
4524         struct bnxt_error_recovery_info *info = bp->recovery_info;
4525         uint32_t val = 0, wait_msec;
4526
4527         if (!info || !bnxt_is_recovery_enabled(bp) ||
4528             is_bnxt_in_error(bp))
4529                 return;
4530
4531         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4532         if (val == info->last_heart_beat)
4533                 goto reset;
4534
4535         info->last_heart_beat = val;
4536
4537         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4538         if (val != info->last_reset_counter)
4539                 goto reset;
4540
4541         info->last_reset_counter = val;
4542
4543         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4544                           bnxt_check_fw_health, (void *)bp);
4545
4546         return;
4547 reset:
4548         /* Stop DMA to/from device */
4549         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4550         bp->flags |= BNXT_FLAG_FW_RESET;
4551
4552         bnxt_stop_rxtx(bp->eth_dev);
4553
4554         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4555
4556         if (bnxt_is_primary_func(bp))
4557                 wait_msec = info->primary_func_wait_period;
4558         else
4559                 wait_msec = info->normal_func_wait_period;
4560
4561         rte_eal_alarm_set(US_PER_MS * wait_msec,
4562                           bnxt_fw_reset_cb, (void *)bp);
4563 }
4564
4565 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4566 {
4567         uint32_t polling_freq;
4568
4569         pthread_mutex_lock(&bp->health_check_lock);
4570
4571         if (!bnxt_is_recovery_enabled(bp))
4572                 goto done;
4573
4574         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4575                 goto done;
4576
4577         polling_freq = bp->recovery_info->driver_polling_freq;
4578
4579         rte_eal_alarm_set(US_PER_MS * polling_freq,
4580                           bnxt_check_fw_health, (void *)bp);
4581         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4582
4583 done:
4584         pthread_mutex_unlock(&bp->health_check_lock);
4585 }
4586
4587 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4588 {
4589         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4590         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4591 }
4592
4593 static bool bnxt_vf_pciid(uint16_t device_id)
4594 {
4595         switch (device_id) {
4596         case BROADCOM_DEV_ID_57304_VF:
4597         case BROADCOM_DEV_ID_57406_VF:
4598         case BROADCOM_DEV_ID_5731X_VF:
4599         case BROADCOM_DEV_ID_5741X_VF:
4600         case BROADCOM_DEV_ID_57414_VF:
4601         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4602         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4603         case BROADCOM_DEV_ID_58802_VF:
4604         case BROADCOM_DEV_ID_57500_VF1:
4605         case BROADCOM_DEV_ID_57500_VF2:
4606         case BROADCOM_DEV_ID_58818_VF:
4607                 /* FALLTHROUGH */
4608                 return true;
4609         default:
4610                 return false;
4611         }
4612 }
4613
4614 /* Phase 5 device */
4615 static bool bnxt_p5_device(uint16_t device_id)
4616 {
4617         switch (device_id) {
4618         case BROADCOM_DEV_ID_57508:
4619         case BROADCOM_DEV_ID_57504:
4620         case BROADCOM_DEV_ID_57502:
4621         case BROADCOM_DEV_ID_57508_MF1:
4622         case BROADCOM_DEV_ID_57504_MF1:
4623         case BROADCOM_DEV_ID_57502_MF1:
4624         case BROADCOM_DEV_ID_57508_MF2:
4625         case BROADCOM_DEV_ID_57504_MF2:
4626         case BROADCOM_DEV_ID_57502_MF2:
4627         case BROADCOM_DEV_ID_57500_VF1:
4628         case BROADCOM_DEV_ID_57500_VF2:
4629         case BROADCOM_DEV_ID_58812:
4630         case BROADCOM_DEV_ID_58814:
4631         case BROADCOM_DEV_ID_58818:
4632         case BROADCOM_DEV_ID_58818_VF:
4633                 /* FALLTHROUGH */
4634                 return true;
4635         default:
4636                 return false;
4637         }
4638 }
4639
4640 bool bnxt_stratus_device(struct bnxt *bp)
4641 {
4642         uint16_t device_id = bp->pdev->id.device_id;
4643
4644         switch (device_id) {
4645         case BROADCOM_DEV_ID_STRATUS_NIC:
4646         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4647         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4648                 /* FALLTHROUGH */
4649                 return true;
4650         default:
4651                 return false;
4652         }
4653 }
4654
4655 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4656 {
4657         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4658         struct bnxt *bp = eth_dev->data->dev_private;
4659
4660         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4661         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4662         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4663         if (!bp->bar0 || !bp->doorbell_base) {
4664                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4665                 return -ENODEV;
4666         }
4667
4668         bp->eth_dev = eth_dev;
4669         bp->pdev = pci_dev;
4670
4671         return 0;
4672 }
4673
4674 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4675                                   struct bnxt_ctx_pg_info *ctx_pg,
4676                                   uint32_t mem_size,
4677                                   const char *suffix,
4678                                   uint16_t idx)
4679 {
4680         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4681         const struct rte_memzone *mz = NULL;
4682         char mz_name[RTE_MEMZONE_NAMESIZE];
4683         rte_iova_t mz_phys_addr;
4684         uint64_t valid_bits = 0;
4685         uint32_t sz;
4686         int i;
4687
4688         if (!mem_size)
4689                 return 0;
4690
4691         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4692                          BNXT_PAGE_SIZE;
4693         rmem->page_size = BNXT_PAGE_SIZE;
4694         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4695         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4696         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4697
4698         valid_bits = PTU_PTE_VALID;
4699
4700         if (rmem->nr_pages > 1) {
4701                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4702                          "bnxt_ctx_pg_tbl%s_%x_%d",
4703                          suffix, idx, bp->eth_dev->data->port_id);
4704                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4705                 mz = rte_memzone_lookup(mz_name);
4706                 if (!mz) {
4707                         mz = rte_memzone_reserve_aligned(mz_name,
4708                                                 rmem->nr_pages * 8,
4709                                                 bp->eth_dev->device->numa_node,
4710                                                 RTE_MEMZONE_2MB |
4711                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4712                                                 RTE_MEMZONE_IOVA_CONTIG,
4713                                                 BNXT_PAGE_SIZE);
4714                         if (mz == NULL)
4715                                 return -ENOMEM;
4716                 }
4717
4718                 memset(mz->addr, 0, mz->len);
4719                 mz_phys_addr = mz->iova;
4720
4721                 rmem->pg_tbl = mz->addr;
4722                 rmem->pg_tbl_map = mz_phys_addr;
4723                 rmem->pg_tbl_mz = mz;
4724         }
4725
4726         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4727                  suffix, idx, bp->eth_dev->data->port_id);
4728         mz = rte_memzone_lookup(mz_name);
4729         if (!mz) {
4730                 mz = rte_memzone_reserve_aligned(mz_name,
4731                                                  mem_size,
4732                                                  bp->eth_dev->device->numa_node,
4733                                                  RTE_MEMZONE_1GB |
4734                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4735                                                  RTE_MEMZONE_IOVA_CONTIG,
4736                                                  BNXT_PAGE_SIZE);
4737                 if (mz == NULL)
4738                         return -ENOMEM;
4739         }
4740
4741         memset(mz->addr, 0, mz->len);
4742         mz_phys_addr = mz->iova;
4743
4744         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4745                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4746                 rmem->dma_arr[i] = mz_phys_addr + sz;
4747
4748                 if (rmem->nr_pages > 1) {
4749                         if (i == rmem->nr_pages - 2 &&
4750                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4751                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4752                         else if (i == rmem->nr_pages - 1 &&
4753                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4754                                 valid_bits |= PTU_PTE_LAST;
4755
4756                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4757                                                            valid_bits);
4758                 }
4759         }
4760
4761         rmem->mz = mz;
4762         if (rmem->vmem_size)
4763                 rmem->vmem = (void **)mz->addr;
4764         rmem->dma_arr[0] = mz_phys_addr;
4765         return 0;
4766 }
4767
4768 static void bnxt_free_ctx_mem(struct bnxt *bp)
4769 {
4770         int i;
4771
4772         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4773                 return;
4774
4775         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4776         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4777         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4778         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4779         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4780         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4781         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4782         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4783         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4784         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4785         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4786
4787         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4788                 if (bp->ctx->tqm_mem[i])
4789                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4790         }
4791
4792         rte_free(bp->ctx);
4793         bp->ctx = NULL;
4794 }
4795
4796 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4797
4798 #define min_t(type, x, y) ({                    \
4799         type __min1 = (x);                      \
4800         type __min2 = (y);                      \
4801         __min1 < __min2 ? __min1 : __min2; })
4802
4803 #define max_t(type, x, y) ({                    \
4804         type __max1 = (x);                      \
4805         type __max2 = (y);                      \
4806         __max1 > __max2 ? __max1 : __max2; })
4807
4808 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4809
4810 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4811 {
4812         struct bnxt_ctx_pg_info *ctx_pg;
4813         struct bnxt_ctx_mem_info *ctx;
4814         uint32_t mem_size, ena, entries;
4815         uint32_t entries_sp, min;
4816         int i, rc;
4817
4818         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4819         if (rc) {
4820                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4821                 return rc;
4822         }
4823         ctx = bp->ctx;
4824         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4825                 return 0;
4826
4827         ctx_pg = &ctx->qp_mem;
4828         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4829         if (ctx->qp_entry_size) {
4830                 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4831                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4832                 if (rc)
4833                         return rc;
4834         }
4835
4836         ctx_pg = &ctx->srq_mem;
4837         ctx_pg->entries = ctx->srq_max_l2_entries;
4838         if (ctx->srq_entry_size) {
4839                 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4840                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4841                 if (rc)
4842                         return rc;
4843         }
4844
4845         ctx_pg = &ctx->cq_mem;
4846         ctx_pg->entries = ctx->cq_max_l2_entries;
4847         if (ctx->cq_entry_size) {
4848                 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4849                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4850                 if (rc)
4851                         return rc;
4852         }
4853
4854         ctx_pg = &ctx->vnic_mem;
4855         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4856                 ctx->vnic_max_ring_table_entries;
4857         if (ctx->vnic_entry_size) {
4858                 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4859                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4860                 if (rc)
4861                         return rc;
4862         }
4863
4864         ctx_pg = &ctx->stat_mem;
4865         ctx_pg->entries = ctx->stat_max_entries;
4866         if (ctx->stat_entry_size) {
4867                 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4868                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4869                 if (rc)
4870                         return rc;
4871         }
4872
4873         min = ctx->tqm_min_entries_per_ring;
4874
4875         entries_sp = ctx->qp_max_l2_entries +
4876                      ctx->vnic_max_vnic_entries +
4877                      2 * ctx->qp_min_qp1_entries + min;
4878         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4879
4880         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4881         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4882         entries = clamp_t(uint32_t, entries, min,
4883                           ctx->tqm_max_entries_per_ring);
4884         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4885                 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4886                  * i > 8 is other ext rings.
4887                  */
4888                 ctx_pg = ctx->tqm_mem[i];
4889                 ctx_pg->entries = i ? entries : entries_sp;
4890                 if (ctx->tqm_entry_size) {
4891                         mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4892                         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4893                                                     "tqm_mem", i);
4894                         if (rc)
4895                                 return rc;
4896                 }
4897                 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4898                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4899                 else
4900                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4901         }
4902
4903         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4904         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4905         if (rc)
4906                 PMD_DRV_LOG(ERR,
4907                             "Failed to configure context mem: rc = %d\n", rc);
4908         else
4909                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4910
4911         return rc;
4912 }
4913
4914 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4915 {
4916         struct rte_pci_device *pci_dev = bp->pdev;
4917         char mz_name[RTE_MEMZONE_NAMESIZE];
4918         const struct rte_memzone *mz = NULL;
4919         uint32_t total_alloc_len;
4920         rte_iova_t mz_phys_addr;
4921
4922         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4923                 return 0;
4924
4925         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4926                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4927                  pci_dev->addr.bus, pci_dev->addr.devid,
4928                  pci_dev->addr.function, "rx_port_stats");
4929         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4930         mz = rte_memzone_lookup(mz_name);
4931         total_alloc_len =
4932                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4933                                        sizeof(struct rx_port_stats_ext) + 512);
4934         if (!mz) {
4935                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4936                                          SOCKET_ID_ANY,
4937                                          RTE_MEMZONE_2MB |
4938                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4939                                          RTE_MEMZONE_IOVA_CONTIG);
4940                 if (mz == NULL)
4941                         return -ENOMEM;
4942         }
4943         memset(mz->addr, 0, mz->len);
4944         mz_phys_addr = mz->iova;
4945
4946         bp->rx_mem_zone = (const void *)mz;
4947         bp->hw_rx_port_stats = mz->addr;
4948         bp->hw_rx_port_stats_map = mz_phys_addr;
4949
4950         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4951                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4952                  pci_dev->addr.bus, pci_dev->addr.devid,
4953                  pci_dev->addr.function, "tx_port_stats");
4954         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4955         mz = rte_memzone_lookup(mz_name);
4956         total_alloc_len =
4957                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4958                                        sizeof(struct tx_port_stats_ext) + 512);
4959         if (!mz) {
4960                 mz = rte_memzone_reserve(mz_name,
4961                                          total_alloc_len,
4962                                          SOCKET_ID_ANY,
4963                                          RTE_MEMZONE_2MB |
4964                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4965                                          RTE_MEMZONE_IOVA_CONTIG);
4966                 if (mz == NULL)
4967                         return -ENOMEM;
4968         }
4969         memset(mz->addr, 0, mz->len);
4970         mz_phys_addr = mz->iova;
4971
4972         bp->tx_mem_zone = (const void *)mz;
4973         bp->hw_tx_port_stats = mz->addr;
4974         bp->hw_tx_port_stats_map = mz_phys_addr;
4975         bp->flags |= BNXT_FLAG_PORT_STATS;
4976
4977         /* Display extended statistics if FW supports it */
4978         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4979             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4980             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4981                 return 0;
4982
4983         bp->hw_rx_port_stats_ext = (void *)
4984                 ((uint8_t *)bp->hw_rx_port_stats +
4985                  sizeof(struct rx_port_stats));
4986         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4987                 sizeof(struct rx_port_stats);
4988         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4989
4990         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4991             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4992                 bp->hw_tx_port_stats_ext = (void *)
4993                         ((uint8_t *)bp->hw_tx_port_stats +
4994                          sizeof(struct tx_port_stats));
4995                 bp->hw_tx_port_stats_ext_map =
4996                         bp->hw_tx_port_stats_map +
4997                         sizeof(struct tx_port_stats);
4998                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4999         }
5000
5001         return 0;
5002 }
5003
5004 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5005 {
5006         struct bnxt *bp = eth_dev->data->dev_private;
5007         size_t max_mac_addr = RTE_MIN(bp->max_l2_ctx, RTE_ETH_NUM_RECEIVE_MAC_ADDR);
5008         int rc = 0;
5009
5010         if (bp->max_l2_ctx > RTE_ETH_NUM_RECEIVE_MAC_ADDR)
5011                 PMD_DRV_LOG(INFO, "Max number of MAC addrs supported is %d, but will be limited to %d\n",
5012                             bp->max_l2_ctx, RTE_ETH_NUM_RECEIVE_MAC_ADDR);
5013
5014         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5015                                                RTE_ETHER_ADDR_LEN * max_mac_addr,
5016                                                0);
5017         if (eth_dev->data->mac_addrs == NULL) {
5018                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5019                 return -ENOMEM;
5020         }
5021
5022         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5023                 if (BNXT_PF(bp))
5024                         return -EINVAL;
5025
5026                 /* Generate a random MAC address, if none was assigned by PF */
5027                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5028                 bnxt_eth_hw_addr_random(bp->mac_addr);
5029                 PMD_DRV_LOG(INFO,
5030                             "Assign random MAC:" RTE_ETHER_ADDR_PRT_FMT "\n",
5031                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5032                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5033
5034                 rc = bnxt_hwrm_set_mac(bp);
5035                 if (rc)
5036                         return rc;
5037         }
5038
5039         /* Copy the permanent MAC from the FUNC_QCAPS response */
5040         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5041
5042         /*
5043          *  Allocate memory to hold multicast mac addresses added.
5044          *  Used to restore them during reset recovery
5045          */
5046         bp->mcast_addr_list = rte_zmalloc("bnxt_mcast_addr_tbl",
5047                                           sizeof(struct rte_ether_addr) *
5048                                           BNXT_MAX_MC_ADDRS, 0);
5049         if (bp->mcast_addr_list == NULL) {
5050                 PMD_DRV_LOG(ERR, "Failed to allocate multicast addr table\n");
5051                 return -ENOMEM;
5052         }
5053         bp->mc_list_dma_addr = rte_malloc_virt2iova(bp->mcast_addr_list);
5054         if (bp->mc_list_dma_addr == RTE_BAD_IOVA) {
5055                 PMD_DRV_LOG(ERR, "Fail to map mcast_addr_list to physical memory\n");
5056                 return -ENOMEM;
5057         }
5058
5059         return rc;
5060 }
5061
5062 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5063 {
5064         int rc = 0;
5065
5066         /* MAC is already configured in FW */
5067         if (BNXT_HAS_DFLT_MAC_SET(bp))
5068                 return 0;
5069
5070         /* Restore the old MAC configured */
5071         rc = bnxt_hwrm_set_mac(bp);
5072         if (rc)
5073                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5074
5075         return rc;
5076 }
5077
5078 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5079 {
5080         if (!BNXT_PF(bp))
5081                 return;
5082
5083         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5084
5085         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
5086                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
5087         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
5088         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
5089         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
5090         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
5091 }
5092
5093 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5094 {
5095         struct bnxt_error_recovery_info *info = bp->recovery_info;
5096
5097         if (info) {
5098                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5099                         memset(info, 0, sizeof(*info));
5100                 return;
5101         }
5102
5103         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5104                 return;
5105
5106         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5107                            sizeof(*info), 0);
5108         if (!info)
5109                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5110
5111         bp->recovery_info = info;
5112 }
5113
5114 static void bnxt_check_fw_status(struct bnxt *bp)
5115 {
5116         uint32_t fw_status;
5117
5118         if (!(bp->recovery_info &&
5119               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5120                 return;
5121
5122         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5123         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5124                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5125                             fw_status);
5126 }
5127
5128 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5129 {
5130         struct bnxt_error_recovery_info *info = bp->recovery_info;
5131         uint32_t status_loc;
5132         uint32_t sig_ver;
5133
5134         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5135                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5136         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5137                                    BNXT_GRCP_WINDOW_2_BASE +
5138                                    offsetof(struct hcomm_status,
5139                                             sig_ver)));
5140         /* If the signature is absent, then FW does not support this feature */
5141         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5142             HCOMM_STATUS_SIGNATURE_VAL)
5143                 return 0;
5144
5145         if (!info) {
5146                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5147                                    sizeof(*info), 0);
5148                 if (!info)
5149                         return -ENOMEM;
5150                 bp->recovery_info = info;
5151         } else {
5152                 memset(info, 0, sizeof(*info));
5153         }
5154
5155         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5156                                       BNXT_GRCP_WINDOW_2_BASE +
5157                                       offsetof(struct hcomm_status,
5158                                                fw_status_loc)));
5159
5160         /* Only pre-map the FW health status GRC register */
5161         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5162                 return 0;
5163
5164         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5165         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5166                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5167
5168         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5169                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5170
5171         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5172
5173         return 0;
5174 }
5175
5176 /* This function gets the FW version along with the
5177  * capabilities(MAX and current) of the function, vnic,
5178  * error recovery, phy and other chip related info
5179  */
5180 static int bnxt_get_config(struct bnxt *bp)
5181 {
5182         uint16_t mtu;
5183         int rc = 0;
5184
5185         bp->fw_cap = 0;
5186
5187         rc = bnxt_map_hcomm_fw_status_reg(bp);
5188         if (rc)
5189                 return rc;
5190
5191         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5192         if (rc) {
5193                 bnxt_check_fw_status(bp);
5194                 return rc;
5195         }
5196
5197         rc = bnxt_hwrm_func_reset(bp);
5198         if (rc)
5199                 return -EIO;
5200
5201         rc = bnxt_hwrm_vnic_qcaps(bp);
5202         if (rc)
5203                 return rc;
5204
5205         rc = bnxt_hwrm_queue_qportcfg(bp);
5206         if (rc)
5207                 return rc;
5208
5209         /* Get the MAX capabilities for this function.
5210          * This function also allocates context memory for TQM rings and
5211          * informs the firmware about this allocated backing store memory.
5212          */
5213         rc = bnxt_hwrm_func_qcaps(bp);
5214         if (rc)
5215                 return rc;
5216
5217         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5218         if (rc)
5219                 return rc;
5220
5221         bnxt_hwrm_port_mac_qcfg(bp);
5222
5223         bnxt_hwrm_parent_pf_qcfg(bp);
5224
5225         bnxt_hwrm_port_phy_qcaps(bp);
5226
5227         bnxt_alloc_error_recovery_info(bp);
5228         /* Get the adapter error recovery support info */
5229         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5230         if (rc)
5231                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5232
5233         bnxt_hwrm_port_led_qcaps(bp);
5234
5235         return 0;
5236 }
5237
5238 static int
5239 bnxt_init_locks(struct bnxt *bp)
5240 {
5241         int err;
5242
5243         err = pthread_mutex_init(&bp->flow_lock, NULL);
5244         if (err) {
5245                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5246                 return err;
5247         }
5248
5249         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5250         if (err) {
5251                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5252                 return err;
5253         }
5254
5255         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5256         if (err) {
5257                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5258                 return err;
5259         }
5260
5261         err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5262         if (err)
5263                 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5264
5265         return err;
5266 }
5267
5268 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5269 {
5270         int rc = 0;
5271
5272         rc = bnxt_get_config(bp);
5273         if (rc)
5274                 return rc;
5275
5276         if (!reconfig_dev) {
5277                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5278                 if (rc)
5279                         return rc;
5280         } else {
5281                 rc = bnxt_restore_dflt_mac(bp);
5282                 if (rc)
5283                         return rc;
5284         }
5285
5286         bnxt_config_vf_req_fwd(bp);
5287
5288         rc = bnxt_hwrm_func_driver_register(bp);
5289         if (rc) {
5290                 PMD_DRV_LOG(ERR, "Failed to register driver");
5291                 return -EBUSY;
5292         }
5293
5294         if (BNXT_PF(bp)) {
5295                 if (bp->pdev->max_vfs) {
5296                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5297                         if (rc) {
5298                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5299                                 return rc;
5300                         }
5301                 } else {
5302                         rc = bnxt_hwrm_allocate_pf_only(bp);
5303                         if (rc) {
5304                                 PMD_DRV_LOG(ERR,
5305                                             "Failed to allocate PF resources");
5306                                 return rc;
5307                         }
5308                 }
5309         }
5310
5311         if (!reconfig_dev) {
5312                 bp->rss_conf.rss_key = rte_zmalloc("bnxt_rss_key",
5313                                                    HW_HASH_KEY_SIZE, 0);
5314                 if (bp->rss_conf.rss_key == NULL) {
5315                         PMD_DRV_LOG(ERR, "port %u cannot allocate RSS hash key memory",
5316                                     bp->eth_dev->data->port_id);
5317                         return -ENOMEM;
5318                 }
5319         }
5320
5321         rc = bnxt_alloc_mem(bp, reconfig_dev);
5322         if (rc)
5323                 return rc;
5324
5325         rc = bnxt_setup_int(bp);
5326         if (rc)
5327                 return rc;
5328
5329         rc = bnxt_request_int(bp);
5330         if (rc)
5331                 return rc;
5332
5333         rc = bnxt_init_ctx_mem(bp);
5334         if (rc) {
5335                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5336                 return rc;
5337         }
5338
5339         return 0;
5340 }
5341
5342 static int
5343 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5344                              const char *value, void *opaque_arg)
5345 {
5346         struct bnxt *bp = opaque_arg;
5347         unsigned long flow_xstat;
5348         char *end = NULL;
5349
5350         if (!value || !opaque_arg) {
5351                 PMD_DRV_LOG(ERR,
5352                             "Invalid parameter passed to flow_xstat devarg.\n");
5353                 return -EINVAL;
5354         }
5355
5356         flow_xstat = strtoul(value, &end, 10);
5357         if (end == NULL || *end != '\0' ||
5358             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5359                 PMD_DRV_LOG(ERR,
5360                             "Invalid parameter passed to flow_xstat devarg.\n");
5361                 return -EINVAL;
5362         }
5363
5364         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5365                 PMD_DRV_LOG(ERR,
5366                             "Invalid value passed to flow_xstat devarg.\n");
5367                 return -EINVAL;
5368         }
5369
5370         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5371         if (BNXT_FLOW_XSTATS_EN(bp))
5372                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5373
5374         return 0;
5375 }
5376
5377 static int
5378 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5379                                         const char *value, void *opaque_arg)
5380 {
5381         struct bnxt *bp = opaque_arg;
5382         unsigned long max_num_kflows;
5383         char *end = NULL;
5384
5385         if (!value || !opaque_arg) {
5386                 PMD_DRV_LOG(ERR,
5387                         "Invalid parameter passed to max_num_kflows devarg.\n");
5388                 return -EINVAL;
5389         }
5390
5391         max_num_kflows = strtoul(value, &end, 10);
5392         if (end == NULL || *end != '\0' ||
5393                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5394                 PMD_DRV_LOG(ERR,
5395                         "Invalid parameter passed to max_num_kflows devarg.\n");
5396                 return -EINVAL;
5397         }
5398
5399         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5400                 PMD_DRV_LOG(ERR,
5401                         "Invalid value passed to max_num_kflows devarg.\n");
5402                 return -EINVAL;
5403         }
5404
5405         bp->max_num_kflows = max_num_kflows;
5406         if (bp->max_num_kflows)
5407                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5408                                 max_num_kflows);
5409
5410         return 0;
5411 }
5412
5413 static int
5414 bnxt_parse_devarg_app_id(__rte_unused const char *key,
5415                                  const char *value, void *opaque_arg)
5416 {
5417         struct bnxt *bp = opaque_arg;
5418         unsigned long app_id;
5419         char *end = NULL;
5420
5421         if (!value || !opaque_arg) {
5422                 PMD_DRV_LOG(ERR,
5423                             "Invalid parameter passed to app-id "
5424                             "devargs.\n");
5425                 return -EINVAL;
5426         }
5427
5428         app_id = strtoul(value, &end, 10);
5429         if (end == NULL || *end != '\0' ||
5430             (app_id == ULONG_MAX && errno == ERANGE)) {
5431                 PMD_DRV_LOG(ERR,
5432                             "Invalid parameter passed to app_id "
5433                             "devargs.\n");
5434                 return -EINVAL;
5435         }
5436
5437         if (BNXT_DEVARG_APP_ID_INVALID(app_id)) {
5438                 PMD_DRV_LOG(ERR, "Invalid app-id(%d) devargs.\n",
5439                             (uint16_t)app_id);
5440                 return -EINVAL;
5441         }
5442
5443         bp->app_id = app_id;
5444         PMD_DRV_LOG(INFO, "app-id=%d feature enabled.\n", (uint16_t)app_id);
5445
5446         return 0;
5447 }
5448
5449 static int
5450 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5451                             const char *value, void *opaque_arg)
5452 {
5453         struct bnxt_representor *vfr_bp = opaque_arg;
5454         unsigned long rep_is_pf;
5455         char *end = NULL;
5456
5457         if (!value || !opaque_arg) {
5458                 PMD_DRV_LOG(ERR,
5459                             "Invalid parameter passed to rep_is_pf devargs.\n");
5460                 return -EINVAL;
5461         }
5462
5463         rep_is_pf = strtoul(value, &end, 10);
5464         if (end == NULL || *end != '\0' ||
5465             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5466                 PMD_DRV_LOG(ERR,
5467                             "Invalid parameter passed to rep_is_pf devargs.\n");
5468                 return -EINVAL;
5469         }
5470
5471         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5472                 PMD_DRV_LOG(ERR,
5473                             "Invalid value passed to rep_is_pf devargs.\n");
5474                 return -EINVAL;
5475         }
5476
5477         vfr_bp->flags |= rep_is_pf;
5478         if (BNXT_REP_PF(vfr_bp))
5479                 PMD_DRV_LOG(INFO, "PF representor\n");
5480         else
5481                 PMD_DRV_LOG(INFO, "VF representor\n");
5482
5483         return 0;
5484 }
5485
5486 static int
5487 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5488                                const char *value, void *opaque_arg)
5489 {
5490         struct bnxt_representor *vfr_bp = opaque_arg;
5491         unsigned long rep_based_pf;
5492         char *end = NULL;
5493
5494         if (!value || !opaque_arg) {
5495                 PMD_DRV_LOG(ERR,
5496                             "Invalid parameter passed to rep_based_pf "
5497                             "devargs.\n");
5498                 return -EINVAL;
5499         }
5500
5501         rep_based_pf = strtoul(value, &end, 10);
5502         if (end == NULL || *end != '\0' ||
5503             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5504                 PMD_DRV_LOG(ERR,
5505                             "Invalid parameter passed to rep_based_pf "
5506                             "devargs.\n");
5507                 return -EINVAL;
5508         }
5509
5510         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5511                 PMD_DRV_LOG(ERR,
5512                             "Invalid value passed to rep_based_pf devargs.\n");
5513                 return -EINVAL;
5514         }
5515
5516         vfr_bp->rep_based_pf = rep_based_pf;
5517         vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5518
5519         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5520
5521         return 0;
5522 }
5523
5524 static int
5525 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5526                             const char *value, void *opaque_arg)
5527 {
5528         struct bnxt_representor *vfr_bp = opaque_arg;
5529         unsigned long rep_q_r2f;
5530         char *end = NULL;
5531
5532         if (!value || !opaque_arg) {
5533                 PMD_DRV_LOG(ERR,
5534                             "Invalid parameter passed to rep_q_r2f "
5535                             "devargs.\n");
5536                 return -EINVAL;
5537         }
5538
5539         rep_q_r2f = strtoul(value, &end, 10);
5540         if (end == NULL || *end != '\0' ||
5541             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5542                 PMD_DRV_LOG(ERR,
5543                             "Invalid parameter passed to rep_q_r2f "
5544                             "devargs.\n");
5545                 return -EINVAL;
5546         }
5547
5548         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5549                 PMD_DRV_LOG(ERR,
5550                             "Invalid value passed to rep_q_r2f devargs.\n");
5551                 return -EINVAL;
5552         }
5553
5554         vfr_bp->rep_q_r2f = rep_q_r2f;
5555         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5556         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5557
5558         return 0;
5559 }
5560
5561 static int
5562 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5563                             const char *value, void *opaque_arg)
5564 {
5565         struct bnxt_representor *vfr_bp = opaque_arg;
5566         unsigned long rep_q_f2r;
5567         char *end = NULL;
5568
5569         if (!value || !opaque_arg) {
5570                 PMD_DRV_LOG(ERR,
5571                             "Invalid parameter passed to rep_q_f2r "
5572                             "devargs.\n");
5573                 return -EINVAL;
5574         }
5575
5576         rep_q_f2r = strtoul(value, &end, 10);
5577         if (end == NULL || *end != '\0' ||
5578             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5579                 PMD_DRV_LOG(ERR,
5580                             "Invalid parameter passed to rep_q_f2r "
5581                             "devargs.\n");
5582                 return -EINVAL;
5583         }
5584
5585         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5586                 PMD_DRV_LOG(ERR,
5587                             "Invalid value passed to rep_q_f2r devargs.\n");
5588                 return -EINVAL;
5589         }
5590
5591         vfr_bp->rep_q_f2r = rep_q_f2r;
5592         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5593         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5594
5595         return 0;
5596 }
5597
5598 static int
5599 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5600                              const char *value, void *opaque_arg)
5601 {
5602         struct bnxt_representor *vfr_bp = opaque_arg;
5603         unsigned long rep_fc_r2f;
5604         char *end = NULL;
5605
5606         if (!value || !opaque_arg) {
5607                 PMD_DRV_LOG(ERR,
5608                             "Invalid parameter passed to rep_fc_r2f "
5609                             "devargs.\n");
5610                 return -EINVAL;
5611         }
5612
5613         rep_fc_r2f = strtoul(value, &end, 10);
5614         if (end == NULL || *end != '\0' ||
5615             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5616                 PMD_DRV_LOG(ERR,
5617                             "Invalid parameter passed to rep_fc_r2f "
5618                             "devargs.\n");
5619                 return -EINVAL;
5620         }
5621
5622         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5623                 PMD_DRV_LOG(ERR,
5624                             "Invalid value passed to rep_fc_r2f devargs.\n");
5625                 return -EINVAL;
5626         }
5627
5628         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5629         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5630         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5631
5632         return 0;
5633 }
5634
5635 static int
5636 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5637                              const char *value, void *opaque_arg)
5638 {
5639         struct bnxt_representor *vfr_bp = opaque_arg;
5640         unsigned long rep_fc_f2r;
5641         char *end = NULL;
5642
5643         if (!value || !opaque_arg) {
5644                 PMD_DRV_LOG(ERR,
5645                             "Invalid parameter passed to rep_fc_f2r "
5646                             "devargs.\n");
5647                 return -EINVAL;
5648         }
5649
5650         rep_fc_f2r = strtoul(value, &end, 10);
5651         if (end == NULL || *end != '\0' ||
5652             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5653                 PMD_DRV_LOG(ERR,
5654                             "Invalid parameter passed to rep_fc_f2r "
5655                             "devargs.\n");
5656                 return -EINVAL;
5657         }
5658
5659         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5660                 PMD_DRV_LOG(ERR,
5661                             "Invalid value passed to rep_fc_f2r devargs.\n");
5662                 return -EINVAL;
5663         }
5664
5665         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5666         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5667         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5668
5669         return 0;
5670 }
5671
5672 static int
5673 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5674 {
5675         struct rte_kvargs *kvlist;
5676         int ret;
5677
5678         if (devargs == NULL)
5679                 return 0;
5680
5681         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5682         if (kvlist == NULL)
5683                 return -EINVAL;
5684
5685         /*
5686          * Handler for "flow_xstat" devarg.
5687          * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5688          */
5689         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5690                                  bnxt_parse_devarg_flow_xstat, bp);
5691         if (ret)
5692                 goto err;
5693
5694         /*
5695          * Handler for "max_num_kflows" devarg.
5696          * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5697          */
5698         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5699                                  bnxt_parse_devarg_max_num_kflows, bp);
5700         if (ret)
5701                 goto err;
5702
5703 err:
5704         /*
5705          * Handler for "app-id" devarg.
5706          * Invoked as for ex: "-a 000:00:0d.0,app-id=1"
5707          */
5708         rte_kvargs_process(kvlist, BNXT_DEVARG_APP_ID,
5709                            bnxt_parse_devarg_app_id, bp);
5710
5711         rte_kvargs_free(kvlist);
5712         return ret;
5713 }
5714
5715 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5716 {
5717         int rc = 0;
5718
5719         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5720                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5721                 if (rc)
5722                         PMD_DRV_LOG(ERR,
5723                                     "Failed to alloc switch domain: %d\n", rc);
5724                 else
5725                         PMD_DRV_LOG(INFO,
5726                                     "Switch domain allocated %d\n",
5727                                     bp->switch_domain_id);
5728         }
5729
5730         return rc;
5731 }
5732
5733 /* Allocate and initialize various fields in bnxt struct that
5734  * need to be allocated/destroyed only once in the lifetime of the driver
5735  */
5736 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5737 {
5738         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5739         struct bnxt *bp = eth_dev->data->dev_private;
5740         int rc = 0;
5741
5742         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5743
5744         if (bnxt_vf_pciid(pci_dev->id.device_id))
5745                 bp->flags |= BNXT_FLAG_VF;
5746
5747         if (bnxt_p5_device(pci_dev->id.device_id))
5748                 bp->flags |= BNXT_FLAG_CHIP_P5;
5749
5750         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5751             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5752             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5753             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5754                 bp->flags |= BNXT_FLAG_STINGRAY;
5755
5756         if (BNXT_TRUFLOW_EN(bp)) {
5757                 /* extra mbuf field is required to store CFA code from mark */
5758                 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5759                         .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5760                         .size = sizeof(bnxt_cfa_code_dynfield_t),
5761                         .align = __alignof__(bnxt_cfa_code_dynfield_t),
5762                 };
5763                 bnxt_cfa_code_dynfield_offset =
5764                         rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5765                 if (bnxt_cfa_code_dynfield_offset < 0) {
5766                         PMD_DRV_LOG(ERR,
5767                             "Failed to register mbuf field for TruFlow mark\n");
5768                         return -rte_errno;
5769                 }
5770         }
5771
5772         rc = bnxt_map_pci_bars(eth_dev);
5773         if (rc) {
5774                 PMD_DRV_LOG(ERR,
5775                             "Failed to initialize board rc: %x\n", rc);
5776                 return rc;
5777         }
5778
5779         rc = bnxt_alloc_pf_info(bp);
5780         if (rc)
5781                 return rc;
5782
5783         rc = bnxt_alloc_link_info(bp);
5784         if (rc)
5785                 return rc;
5786
5787         rc = bnxt_alloc_parent_info(bp);
5788         if (rc)
5789                 return rc;
5790
5791         rc = bnxt_alloc_hwrm_resources(bp);
5792         if (rc) {
5793                 PMD_DRV_LOG(ERR,
5794                             "Failed to allocate response buffer rc: %x\n", rc);
5795                 return rc;
5796         }
5797         rc = bnxt_alloc_leds_info(bp);
5798         if (rc)
5799                 return rc;
5800
5801         rc = bnxt_alloc_cos_queues(bp);
5802         if (rc)
5803                 return rc;
5804
5805         rc = bnxt_init_locks(bp);
5806         if (rc)
5807                 return rc;
5808
5809         rc = bnxt_alloc_switch_domain(bp);
5810         if (rc)
5811                 return rc;
5812
5813         return rc;
5814 }
5815
5816 static int
5817 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5818 {
5819         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5820         static int version_printed;
5821         struct bnxt *bp;
5822         int rc;
5823
5824         if (version_printed++ == 0)
5825                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5826
5827         eth_dev->dev_ops = &bnxt_dev_ops;
5828         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5829         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5830         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5831         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5832         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5833
5834         /*
5835          * For secondary processes, we don't initialise any further
5836          * as primary has already done this work.
5837          */
5838         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5839                 return 0;
5840
5841         rte_eth_copy_pci_info(eth_dev, pci_dev);
5842         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5843
5844         bp = eth_dev->data->dev_private;
5845
5846         /* Parse dev arguments passed on when starting the DPDK application. */
5847         rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5848         if (rc)
5849                 goto error_free;
5850
5851         rc = bnxt_drv_init(eth_dev);
5852         if (rc)
5853                 goto error_free;
5854
5855         rc = bnxt_init_resources(bp, false);
5856         if (rc)
5857                 goto error_free;
5858
5859         rc = bnxt_alloc_stats_mem(bp);
5860         if (rc)
5861                 goto error_free;
5862
5863         PMD_DRV_LOG(INFO,
5864                     "Found %s device at mem %" PRIX64 ", node addr %pM\n",
5865                     DRV_MODULE_NAME,
5866                     pci_dev->mem_resource[0].phys_addr,
5867                     pci_dev->mem_resource[0].addr);
5868
5869         return 0;
5870
5871 error_free:
5872         bnxt_dev_uninit(eth_dev);
5873         return rc;
5874 }
5875
5876
5877 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5878 {
5879         if (!ctx)
5880                 return;
5881
5882         rte_free(ctx->va);
5883
5884         ctx->va = NULL;
5885         ctx->dma = RTE_BAD_IOVA;
5886         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5887 }
5888
5889 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5890 {
5891         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5892                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5893                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5894                                   bp->flow_stat->max_fc,
5895                                   false);
5896
5897         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5898                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5899                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5900                                   bp->flow_stat->max_fc,
5901                                   false);
5902
5903         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5904                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5905         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5906
5907         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5908                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5909         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5910
5911         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5912                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5913         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5914
5915         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5916                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5917         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5918 }
5919
5920 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5921 {
5922         bnxt_unregister_fc_ctx_mem(bp);
5923
5924         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5925         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5926         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5927         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5928 }
5929
5930 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5931 {
5932         if (BNXT_FLOW_XSTATS_EN(bp))
5933                 bnxt_uninit_fc_ctx_mem(bp);
5934 }
5935
5936 static void
5937 bnxt_free_error_recovery_info(struct bnxt *bp)
5938 {
5939         rte_free(bp->recovery_info);
5940         bp->recovery_info = NULL;
5941         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5942 }
5943
5944 static int
5945 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5946 {
5947         int rc;
5948
5949         bnxt_free_int(bp);
5950         bnxt_free_mem(bp, reconfig_dev);
5951
5952         bnxt_hwrm_func_buf_unrgtr(bp);
5953         if (bp->pf != NULL) {
5954                 rte_free(bp->pf->vf_req_buf);
5955                 bp->pf->vf_req_buf = NULL;
5956         }
5957
5958         rc = bnxt_hwrm_func_driver_unregister(bp);
5959         bp->flags &= ~BNXT_FLAG_REGISTERED;
5960         bnxt_free_ctx_mem(bp);
5961         if (!reconfig_dev) {
5962                 bnxt_free_hwrm_resources(bp);
5963                 bnxt_free_error_recovery_info(bp);
5964                 rte_free(bp->mcast_addr_list);
5965                 bp->mcast_addr_list = NULL;
5966                 rte_free(bp->rss_conf.rss_key);
5967                 bp->rss_conf.rss_key = NULL;
5968         }
5969
5970         bnxt_uninit_ctx_mem(bp);
5971
5972         bnxt_free_flow_stats_info(bp);
5973         if (bp->rep_info != NULL)
5974                 bnxt_free_switch_domain(bp);
5975         bnxt_free_rep_info(bp);
5976         rte_free(bp->ptp_cfg);
5977         bp->ptp_cfg = NULL;
5978         return rc;
5979 }
5980
5981 static int
5982 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5983 {
5984         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5985                 return -EPERM;
5986
5987         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5988
5989         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5990                 bnxt_dev_close_op(eth_dev);
5991
5992         return 0;
5993 }
5994
5995 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5996 {
5997         struct bnxt *bp = eth_dev->data->dev_private;
5998         struct rte_eth_dev *vf_rep_eth_dev;
5999         int ret = 0, i;
6000
6001         if (!bp)
6002                 return -EINVAL;
6003
6004         for (i = 0; i < bp->num_reps; i++) {
6005                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6006                 if (!vf_rep_eth_dev)
6007                         continue;
6008                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6009                             vf_rep_eth_dev->data->port_id);
6010                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6011         }
6012         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6013                     eth_dev->data->port_id);
6014         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6015
6016         return ret;
6017 }
6018
6019 static void bnxt_free_rep_info(struct bnxt *bp)
6020 {
6021         rte_free(bp->rep_info);
6022         bp->rep_info = NULL;
6023         rte_free(bp->cfa_code_map);
6024         bp->cfa_code_map = NULL;
6025 }
6026
6027 static int bnxt_init_rep_info(struct bnxt *bp)
6028 {
6029         int i = 0, rc;
6030
6031         if (bp->rep_info)
6032                 return 0;
6033
6034         bp->rep_info = rte_zmalloc("bnxt_rep_info",
6035                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS(bp),
6036                                    0);
6037         if (!bp->rep_info) {
6038                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6039                 return -ENOMEM;
6040         }
6041         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6042                                        sizeof(*bp->cfa_code_map) *
6043                                        BNXT_MAX_CFA_CODE, 0);
6044         if (!bp->cfa_code_map) {
6045                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6046                 bnxt_free_rep_info(bp);
6047                 return -ENOMEM;
6048         }
6049
6050         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6051                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6052
6053         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6054         if (rc) {
6055                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6056                 bnxt_free_rep_info(bp);
6057                 return rc;
6058         }
6059
6060         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6061         if (rc) {
6062                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6063                 bnxt_free_rep_info(bp);
6064                 return rc;
6065         }
6066
6067         return rc;
6068 }
6069
6070 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6071                                struct rte_eth_devargs *eth_da,
6072                                struct rte_eth_dev *backing_eth_dev,
6073                                const char *dev_args)
6074 {
6075         struct rte_eth_dev *vf_rep_eth_dev;
6076         char name[RTE_ETH_NAME_MAX_LEN];
6077         struct bnxt *backing_bp = backing_eth_dev->data->dev_private;
6078         uint16_t max_vf_reps = BNXT_MAX_VF_REPS(backing_bp);
6079
6080         uint16_t num_rep;
6081         int i, ret = 0;
6082         struct rte_kvargs *kvlist = NULL;
6083
6084         if (eth_da->type == RTE_ETH_REPRESENTOR_NONE)
6085                 return 0;
6086         if (eth_da->type != RTE_ETH_REPRESENTOR_VF) {
6087                 PMD_DRV_LOG(ERR, "unsupported representor type %d\n",
6088                             eth_da->type);
6089                 return -ENOTSUP;
6090         }
6091         num_rep = eth_da->nb_representor_ports;
6092         if (num_rep > max_vf_reps) {
6093                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6094                             num_rep, max_vf_reps);
6095                 return -EINVAL;
6096         }
6097
6098         if (num_rep >= RTE_MAX_ETHPORTS) {
6099                 PMD_DRV_LOG(ERR,
6100                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6101                             num_rep, RTE_MAX_ETHPORTS);
6102                 return -EINVAL;
6103         }
6104
6105         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6106                 PMD_DRV_LOG(ERR,
6107                             "Not a PF or trusted VF. No Representor support\n");
6108                 /* Returning an error is not an option.
6109                  * Applications are not handling this correctly
6110                  */
6111                 return 0;
6112         }
6113
6114         if (bnxt_init_rep_info(backing_bp))
6115                 return 0;
6116
6117         for (i = 0; i < num_rep; i++) {
6118                 struct bnxt_representor representor = {
6119                         .vf_id = eth_da->representor_ports[i],
6120                         .switch_domain_id = backing_bp->switch_domain_id,
6121                         .parent_dev = backing_eth_dev
6122                 };
6123
6124                 if (representor.vf_id >= max_vf_reps) {
6125                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6126                                     representor.vf_id, max_vf_reps);
6127                         continue;
6128                 }
6129
6130                 /* representor port net_bdf_port */
6131                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6132                          pci_dev->device.name, eth_da->representor_ports[i]);
6133
6134                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6135                 if (kvlist) {
6136                         /*
6137                          * Handler for "rep_is_pf" devarg.
6138                          * Invoked as for ex: "-a 000:00:0d.0,
6139                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6140                          */
6141                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6142                                                  bnxt_parse_devarg_rep_is_pf,
6143                                                  (void *)&representor);
6144                         if (ret) {
6145                                 ret = -EINVAL;
6146                                 goto err;
6147                         }
6148                         /*
6149                          * Handler for "rep_based_pf" devarg.
6150                          * Invoked as for ex: "-a 000:00:0d.0,
6151                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6152                          */
6153                         ret = rte_kvargs_process(kvlist,
6154                                                  BNXT_DEVARG_REP_BASED_PF,
6155                                                  bnxt_parse_devarg_rep_based_pf,
6156                                                  (void *)&representor);
6157                         if (ret) {
6158                                 ret = -EINVAL;
6159                                 goto err;
6160                         }
6161                         /*
6162                          * Handler for "rep_based_pf" devarg.
6163                          * Invoked as for ex: "-a 000:00:0d.0,
6164                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6165                          */
6166                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6167                                                  bnxt_parse_devarg_rep_q_r2f,
6168                                                  (void *)&representor);
6169                         if (ret) {
6170                                 ret = -EINVAL;
6171                                 goto err;
6172                         }
6173                         /*
6174                          * Handler for "rep_based_pf" devarg.
6175                          * Invoked as for ex: "-a 000:00:0d.0,
6176                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6177                          */
6178                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6179                                                  bnxt_parse_devarg_rep_q_f2r,
6180                                                  (void *)&representor);
6181                         if (ret) {
6182                                 ret = -EINVAL;
6183                                 goto err;
6184                         }
6185                         /*
6186                          * Handler for "rep_based_pf" devarg.
6187                          * Invoked as for ex: "-a 000:00:0d.0,
6188                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6189                          */
6190                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6191                                                  bnxt_parse_devarg_rep_fc_r2f,
6192                                                  (void *)&representor);
6193                         if (ret) {
6194                                 ret = -EINVAL;
6195                                 goto err;
6196                         }
6197                         /*
6198                          * Handler for "rep_based_pf" devarg.
6199                          * Invoked as for ex: "-a 000:00:0d.0,
6200                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6201                          */
6202                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6203                                                  bnxt_parse_devarg_rep_fc_f2r,
6204                                                  (void *)&representor);
6205                         if (ret) {
6206                                 ret = -EINVAL;
6207                                 goto err;
6208                         }
6209                 }
6210
6211                 ret = rte_eth_dev_create(&pci_dev->device, name,
6212                                          sizeof(struct bnxt_representor),
6213                                          NULL, NULL,
6214                                          bnxt_representor_init,
6215                                          &representor);
6216                 if (ret) {
6217                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6218                                     "representor %s.", name);
6219                         goto err;
6220                 }
6221
6222                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6223                 if (!vf_rep_eth_dev) {
6224                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6225                                     " for VF-Rep: %s.", name);
6226                         ret = -ENODEV;
6227                         goto err;
6228                 }
6229
6230                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6231                             backing_eth_dev->data->port_id);
6232                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6233                                                          vf_rep_eth_dev;
6234                 backing_bp->num_reps++;
6235
6236         }
6237
6238         rte_kvargs_free(kvlist);
6239         return 0;
6240
6241 err:
6242         /* If num_rep > 1, then rollback already created
6243          * ports, since we'll be failing the probe anyway
6244          */
6245         if (num_rep > 1)
6246                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6247         rte_errno = -ret;
6248         rte_kvargs_free(kvlist);
6249
6250         return ret;
6251 }
6252
6253 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6254                           struct rte_pci_device *pci_dev)
6255 {
6256         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6257         struct rte_eth_dev *backing_eth_dev;
6258         uint16_t num_rep;
6259         int ret = 0;
6260
6261         if (pci_dev->device.devargs) {
6262                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6263                                             &eth_da);
6264                 if (ret)
6265                         return ret;
6266         }
6267
6268         num_rep = eth_da.nb_representor_ports;
6269         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6270                     num_rep);
6271
6272         /* We could come here after first level of probe is already invoked
6273          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6274          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6275          */
6276         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6277         if (backing_eth_dev == NULL) {
6278                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6279                                          sizeof(struct bnxt),
6280                                          eth_dev_pci_specific_init, pci_dev,
6281                                          bnxt_dev_init, NULL);
6282
6283                 if (ret || !num_rep)
6284                         return ret;
6285
6286                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6287         }
6288         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6289                     backing_eth_dev->data->port_id);
6290
6291         if (!num_rep)
6292                 return ret;
6293
6294         /* probe representor ports now */
6295         ret = bnxt_rep_port_probe(pci_dev, &eth_da, backing_eth_dev,
6296                                   pci_dev->device.devargs->args);
6297
6298         return ret;
6299 }
6300
6301 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6302 {
6303         struct rte_eth_dev *eth_dev;
6304
6305         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6306         if (!eth_dev)
6307                 return 0; /* Invoked typically only by OVS-DPDK, by the
6308                            * time it comes here the eth_dev is already
6309                            * deleted by rte_eth_dev_close(), so returning
6310                            * +ve value will at least help in proper cleanup
6311                            */
6312
6313         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6314         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6315                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6316                         return rte_eth_dev_destroy(eth_dev,
6317                                                    bnxt_representor_uninit);
6318                 else
6319                         return rte_eth_dev_destroy(eth_dev,
6320                                                    bnxt_dev_uninit);
6321         } else {
6322                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6323         }
6324 }
6325
6326 static struct rte_pci_driver bnxt_rte_pmd = {
6327         .id_table = bnxt_pci_id_map,
6328         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6329                         RTE_PCI_DRV_INTR_RMV |
6330                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6331                                                   * and OVS-DPDK
6332                                                   */
6333         .probe = bnxt_pci_probe,
6334         .remove = bnxt_pci_remove,
6335 };
6336
6337 static bool
6338 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6339 {
6340         if (strcmp(dev->device->driver->name, drv->driver.name))
6341                 return false;
6342
6343         return true;
6344 }
6345
6346 bool is_bnxt_supported(struct rte_eth_dev *dev)
6347 {
6348         return is_device_supported(dev, &bnxt_rte_pmd);
6349 }
6350
6351 RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE);
6352 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6353 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6354 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");