1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
30 #define DRV_MODULE_NAME "bnxt"
31 static const char bnxt_version[] =
32 "Broadcom NetXtreme driver " DRV_MODULE_NAME "\n";
33 int bnxt_logtype_driver;
35 #define PCI_VENDOR_ID_BROADCOM 0x14E4
37 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
39 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
40 #define BROADCOM_DEV_ID_57414_VF 0x16c1
41 #define BROADCOM_DEV_ID_57301 0x16c8
42 #define BROADCOM_DEV_ID_57302 0x16c9
43 #define BROADCOM_DEV_ID_57304_PF 0x16ca
44 #define BROADCOM_DEV_ID_57304_VF 0x16cb
45 #define BROADCOM_DEV_ID_57417_MF 0x16cc
46 #define BROADCOM_DEV_ID_NS2 0x16cd
47 #define BROADCOM_DEV_ID_57311 0x16ce
48 #define BROADCOM_DEV_ID_57312 0x16cf
49 #define BROADCOM_DEV_ID_57402 0x16d0
50 #define BROADCOM_DEV_ID_57404 0x16d1
51 #define BROADCOM_DEV_ID_57406_PF 0x16d2
52 #define BROADCOM_DEV_ID_57406_VF 0x16d3
53 #define BROADCOM_DEV_ID_57402_MF 0x16d4
54 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
55 #define BROADCOM_DEV_ID_57412 0x16d6
56 #define BROADCOM_DEV_ID_57414 0x16d7
57 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
58 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
59 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
60 #define BROADCOM_DEV_ID_57412_MF 0x16de
61 #define BROADCOM_DEV_ID_57314 0x16df
62 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
63 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
64 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
65 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
66 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
67 #define BROADCOM_DEV_ID_57404_MF 0x16e7
68 #define BROADCOM_DEV_ID_57406_MF 0x16e8
69 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
70 #define BROADCOM_DEV_ID_57407_MF 0x16ea
71 #define BROADCOM_DEV_ID_57414_MF 0x16ec
72 #define BROADCOM_DEV_ID_57416_MF 0x16ee
73 #define BROADCOM_DEV_ID_58802 0xd802
74 #define BROADCOM_DEV_ID_58804 0xd804
75 #define BROADCOM_DEV_ID_58808 0x16f0
76 #define BROADCOM_DEV_ID_58802_VF 0xd800
78 static const struct rte_pci_id bnxt_pci_id_map[] = {
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
80 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
82 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
121 { .vendor_id = 0, /* sentinel */ },
124 #define BNXT_ETH_RSS_SUPPORT ( \
126 ETH_RSS_NONFRAG_IPV4_TCP | \
127 ETH_RSS_NONFRAG_IPV4_UDP | \
129 ETH_RSS_NONFRAG_IPV6_TCP | \
130 ETH_RSS_NONFRAG_IPV6_UDP)
132 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
133 DEV_TX_OFFLOAD_IPV4_CKSUM | \
134 DEV_TX_OFFLOAD_TCP_CKSUM | \
135 DEV_TX_OFFLOAD_UDP_CKSUM | \
136 DEV_TX_OFFLOAD_TCP_TSO | \
137 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
138 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
139 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
140 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
141 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
142 DEV_TX_OFFLOAD_MULTI_SEGS)
144 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
145 DEV_RX_OFFLOAD_VLAN_STRIP | \
146 DEV_RX_OFFLOAD_IPV4_CKSUM | \
147 DEV_RX_OFFLOAD_UDP_CKSUM | \
148 DEV_RX_OFFLOAD_TCP_CKSUM | \
149 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
150 DEV_RX_OFFLOAD_JUMBO_FRAME | \
151 DEV_RX_OFFLOAD_CRC_STRIP | \
152 DEV_RX_OFFLOAD_KEEP_CRC | \
153 DEV_RX_OFFLOAD_TCP_LRO)
155 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
156 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
157 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
158 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
160 /***********************/
163 * High level utility functions
166 static void bnxt_free_mem(struct bnxt *bp)
168 bnxt_free_filter_mem(bp);
169 bnxt_free_vnic_attributes(bp);
170 bnxt_free_vnic_mem(bp);
173 bnxt_free_tx_rings(bp);
174 bnxt_free_rx_rings(bp);
177 static int bnxt_alloc_mem(struct bnxt *bp)
181 rc = bnxt_alloc_vnic_mem(bp);
185 rc = bnxt_alloc_vnic_attributes(bp);
189 rc = bnxt_alloc_filter_mem(bp);
200 static int bnxt_init_chip(struct bnxt *bp)
202 struct bnxt_rx_queue *rxq;
203 struct rte_eth_link new;
204 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
205 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
206 uint32_t intr_vector = 0;
207 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
208 uint32_t vec = BNXT_MISC_VEC_ID;
212 /* disable uio/vfio intr/eventfd mapping */
213 rte_intr_disable(intr_handle);
215 if (bp->eth_dev->data->mtu > ETHER_MTU) {
216 bp->eth_dev->data->dev_conf.rxmode.offloads |=
217 DEV_RX_OFFLOAD_JUMBO_FRAME;
218 bp->flags |= BNXT_FLAG_JUMBO;
220 bp->eth_dev->data->dev_conf.rxmode.offloads &=
221 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
222 bp->flags &= ~BNXT_FLAG_JUMBO;
225 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
227 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
231 rc = bnxt_alloc_hwrm_rings(bp);
233 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
237 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
239 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
243 rc = bnxt_mq_rx_configure(bp);
245 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
249 /* VNIC configuration */
250 for (i = 0; i < bp->nr_vnics; i++) {
251 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
253 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
255 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
260 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
263 "HWRM vnic %d ctx alloc failure rc: %x\n",
268 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
270 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
275 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
278 "HWRM vnic %d filter failure rc: %x\n",
283 for (j = 0; j < bp->rx_nr_rings; j++) {
284 rxq = bp->eth_dev->data->rx_queues[j];
286 if (rxq->rx_deferred_start)
287 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
290 rc = bnxt_vnic_rss_configure(bp, vnic);
293 "HWRM vnic set RSS failure rc: %x\n", rc);
297 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
299 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
300 DEV_RX_OFFLOAD_TCP_LRO)
301 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
303 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
305 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
308 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
312 /* check and configure queue intr-vector mapping */
313 if ((rte_intr_cap_multiple(intr_handle) ||
314 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
315 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
316 intr_vector = bp->eth_dev->data->nb_rx_queues;
317 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
318 if (intr_vector > bp->rx_cp_nr_rings) {
319 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
323 if (rte_intr_efd_enable(intr_handle, intr_vector))
327 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
328 intr_handle->intr_vec =
329 rte_zmalloc("intr_vec",
330 bp->eth_dev->data->nb_rx_queues *
332 if (intr_handle->intr_vec == NULL) {
333 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
334 " intr_vec", bp->eth_dev->data->nb_rx_queues);
337 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
338 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
339 intr_handle->intr_vec, intr_handle->nb_efd,
340 intr_handle->max_intr);
343 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
345 intr_handle->intr_vec[queue_id] = vec;
346 if (vec < base + intr_handle->nb_efd - 1)
350 /* enable uio/vfio intr/eventfd mapping */
351 rte_intr_enable(intr_handle);
353 rc = bnxt_get_hwrm_link_config(bp, &new);
355 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
359 if (!bp->link_info.link_up) {
360 rc = bnxt_set_hwrm_link_config(bp, true);
363 "HWRM link config failure rc: %x\n", rc);
367 bnxt_print_link_info(bp->eth_dev);
372 bnxt_free_all_hwrm_resources(bp);
374 /* Some of the error status returned by FW may not be from errno.h */
381 static int bnxt_shutdown_nic(struct bnxt *bp)
383 bnxt_free_all_hwrm_resources(bp);
384 bnxt_free_all_filters(bp);
385 bnxt_free_all_vnics(bp);
389 static int bnxt_init_nic(struct bnxt *bp)
393 rc = bnxt_init_ring_grps(bp);
398 bnxt_init_filters(bp);
404 * Device configuration and status function
407 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
408 struct rte_eth_dev_info *dev_info)
410 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
411 uint16_t max_vnics, i, j, vpool, vrxq;
412 unsigned int max_rx_rings;
415 dev_info->max_mac_addrs = bp->max_l2_ctx;
416 dev_info->max_hash_mac_addrs = 0;
418 /* PF/VF specifics */
420 dev_info->max_vfs = bp->pdev->max_vfs;
421 max_rx_rings = RTE_MIN(bp->max_vnics, bp->max_stat_ctx);
422 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
423 dev_info->max_rx_queues = max_rx_rings;
424 dev_info->max_tx_queues = max_rx_rings;
425 dev_info->reta_size = bp->max_rsscos_ctx;
426 dev_info->hash_key_size = 40;
427 max_vnics = bp->max_vnics;
429 /* Fast path specifics */
430 dev_info->min_rx_bufsize = 1;
431 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
434 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
435 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
436 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
437 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
438 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
441 dev_info->default_rxconf = (struct rte_eth_rxconf) {
447 .rx_free_thresh = 32,
448 /* If no descriptors available, pkts are dropped by default */
452 dev_info->default_txconf = (struct rte_eth_txconf) {
458 .tx_free_thresh = 32,
461 eth_dev->data->dev_conf.intr_conf.lsc = 1;
463 eth_dev->data->dev_conf.intr_conf.rxq = 1;
464 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
465 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
466 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
467 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
472 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
473 * need further investigation.
477 vpool = 64; /* ETH_64_POOLS */
478 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
479 for (i = 0; i < 4; vpool >>= 1, i++) {
480 if (max_vnics > vpool) {
481 for (j = 0; j < 5; vrxq >>= 1, j++) {
482 if (dev_info->max_rx_queues > vrxq) {
488 /* Not enough resources to support VMDq */
492 /* Not enough resources to support VMDq */
496 dev_info->max_vmdq_pools = vpool;
497 dev_info->vmdq_queue_num = vrxq;
499 dev_info->vmdq_pool_base = 0;
500 dev_info->vmdq_queue_base = 0;
503 /* Configure the device based on the configuration provided */
504 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
506 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
507 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
509 bp->rx_queues = (void *)eth_dev->data->rx_queues;
510 bp->tx_queues = (void *)eth_dev->data->tx_queues;
511 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
512 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
514 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
517 rc = bnxt_hwrm_func_reserve_vf_resc(bp);
519 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
523 /* legacy driver needs to get updated values */
524 rc = bnxt_hwrm_func_qcaps(bp);
526 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
531 /* Inherit new configurations */
532 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
533 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
534 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
536 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
538 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) {
540 "Insufficient resources to support requested config\n");
542 "Num Queues Requested: Tx %d, Rx %d\n",
543 eth_dev->data->nb_tx_queues,
544 eth_dev->data->nb_rx_queues);
546 "Res available: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d\n",
547 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
548 bp->max_stat_ctx, bp->max_ring_grps);
552 bp->rx_cp_nr_rings = bp->rx_nr_rings;
553 bp->tx_cp_nr_rings = bp->tx_nr_rings;
555 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
557 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
558 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE *
560 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
565 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
567 struct rte_eth_link *link = ð_dev->data->dev_link;
569 if (link->link_status)
570 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
571 eth_dev->data->port_id,
572 (uint32_t)link->link_speed,
573 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
574 ("full-duplex") : ("half-duplex\n"));
576 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
577 eth_dev->data->port_id);
580 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
582 bnxt_print_link_info(eth_dev);
586 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
588 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
589 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
593 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
595 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
596 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
600 rc = bnxt_init_chip(bp);
604 bnxt_link_update_op(eth_dev, 1);
606 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
607 vlan_mask |= ETH_VLAN_FILTER_MASK;
608 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
609 vlan_mask |= ETH_VLAN_STRIP_MASK;
610 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
614 bp->flags |= BNXT_FLAG_INIT_DONE;
618 bnxt_shutdown_nic(bp);
619 bnxt_free_tx_mbufs(bp);
620 bnxt_free_rx_mbufs(bp);
624 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
626 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
629 if (!bp->link_info.link_up)
630 rc = bnxt_set_hwrm_link_config(bp, true);
632 eth_dev->data->dev_link.link_status = 1;
634 bnxt_print_link_info(eth_dev);
638 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
640 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
642 eth_dev->data->dev_link.link_status = 0;
643 bnxt_set_hwrm_link_config(bp, false);
644 bp->link_info.link_up = 0;
649 /* Unload the driver, release resources */
650 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
652 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
654 bp->flags &= ~BNXT_FLAG_INIT_DONE;
655 if (bp->eth_dev->data->dev_started) {
656 /* TBD: STOP HW queues DMA */
657 eth_dev->data->dev_link.link_status = 0;
659 bnxt_set_hwrm_link_config(bp, false);
660 bnxt_hwrm_port_clr_stats(bp);
661 bnxt_free_tx_mbufs(bp);
662 bnxt_free_rx_mbufs(bp);
663 bnxt_shutdown_nic(bp);
667 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
669 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
671 if (bp->dev_stopped == 0)
672 bnxt_dev_stop_op(eth_dev);
675 if (eth_dev->data->mac_addrs != NULL) {
676 rte_free(eth_dev->data->mac_addrs);
677 eth_dev->data->mac_addrs = NULL;
679 if (bp->grp_info != NULL) {
680 rte_free(bp->grp_info);
684 bnxt_dev_uninit(eth_dev);
687 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
690 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
691 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
692 struct bnxt_vnic_info *vnic;
693 struct bnxt_filter_info *filter, *temp_filter;
694 uint32_t pool = RTE_MIN(MAX_FF_POOLS, ETH_64_POOLS);
698 * Loop through all VNICs from the specified filter flow pools to
699 * remove the corresponding MAC addr filter
701 for (i = 0; i < pool; i++) {
702 if (!(pool_mask & (1ULL << i)))
705 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
706 filter = STAILQ_FIRST(&vnic->filter);
708 temp_filter = STAILQ_NEXT(filter, next);
709 if (filter->mac_index == index) {
710 STAILQ_REMOVE(&vnic->filter, filter,
711 bnxt_filter_info, next);
712 bnxt_hwrm_clear_l2_filter(bp, filter);
713 filter->mac_index = INVALID_MAC_INDEX;
714 memset(&filter->l2_addr, 0,
717 &bp->free_filter_list,
720 filter = temp_filter;
726 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
727 struct ether_addr *mac_addr,
728 uint32_t index, uint32_t pool)
730 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
731 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
732 struct bnxt_filter_info *filter;
735 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
740 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
743 /* Attach requested MAC address to the new l2_filter */
744 STAILQ_FOREACH(filter, &vnic->filter, next) {
745 if (filter->mac_index == index) {
747 "MAC addr already existed for pool %d\n", pool);
751 filter = bnxt_alloc_filter(bp);
753 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
756 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
757 filter->mac_index = index;
758 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
759 return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
762 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
765 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
766 struct rte_eth_link new;
767 unsigned int cnt = BNXT_LINK_WAIT_CNT;
769 memset(&new, 0, sizeof(new));
771 /* Retrieve link info from hardware */
772 rc = bnxt_get_hwrm_link_config(bp, &new);
774 new.link_speed = ETH_LINK_SPEED_100M;
775 new.link_duplex = ETH_LINK_FULL_DUPLEX;
777 "Failed to retrieve link rc = 0x%x!\n", rc);
780 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
782 if (!wait_to_complete)
784 } while (!new.link_status && cnt--);
787 /* Timed out or success */
788 if (new.link_status != eth_dev->data->dev_link.link_status ||
789 new.link_speed != eth_dev->data->dev_link.link_speed) {
790 memcpy(ð_dev->data->dev_link, &new,
791 sizeof(struct rte_eth_link));
793 _rte_eth_dev_callback_process(eth_dev,
794 RTE_ETH_EVENT_INTR_LSC,
797 bnxt_print_link_info(eth_dev);
803 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
805 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
806 struct bnxt_vnic_info *vnic;
808 if (bp->vnic_info == NULL)
811 vnic = &bp->vnic_info[0];
813 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
814 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
817 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
819 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
820 struct bnxt_vnic_info *vnic;
822 if (bp->vnic_info == NULL)
825 vnic = &bp->vnic_info[0];
827 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
828 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
831 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
833 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
834 struct bnxt_vnic_info *vnic;
836 if (bp->vnic_info == NULL)
839 vnic = &bp->vnic_info[0];
841 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
842 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
845 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
847 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
848 struct bnxt_vnic_info *vnic;
850 if (bp->vnic_info == NULL)
853 vnic = &bp->vnic_info[0];
855 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
856 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
859 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
860 struct rte_eth_rss_reta_entry64 *reta_conf,
863 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
864 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
865 struct bnxt_vnic_info *vnic;
868 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
871 if (reta_size != HW_HASH_INDEX_SIZE) {
872 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
873 "(%d) must equal the size supported by the hardware "
874 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
877 /* Update the RSS VNIC(s) */
878 for (i = 0; i < MAX_FF_POOLS; i++) {
879 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
880 memcpy(vnic->rss_table, reta_conf, reta_size);
882 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
888 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
889 struct rte_eth_rss_reta_entry64 *reta_conf,
892 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
893 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
894 struct rte_intr_handle *intr_handle
895 = &bp->pdev->intr_handle;
897 /* Retrieve from the default VNIC */
900 if (!vnic->rss_table)
903 if (reta_size != HW_HASH_INDEX_SIZE) {
904 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
905 "(%d) must equal the size supported by the hardware "
906 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
909 /* EW - need to revisit here copying from uint64_t to uint16_t */
910 memcpy(reta_conf, vnic->rss_table, reta_size);
912 if (rte_intr_allow_others(intr_handle)) {
913 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
914 bnxt_dev_lsc_intr_setup(eth_dev);
920 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
921 struct rte_eth_rss_conf *rss_conf)
923 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
924 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
925 struct bnxt_vnic_info *vnic;
926 uint16_t hash_type = 0;
930 * If RSS enablement were different than dev_configure,
931 * then return -EINVAL
933 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
934 if (!rss_conf->rss_hf)
935 PMD_DRV_LOG(ERR, "Hash type NONE\n");
937 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
941 bp->flags |= BNXT_FLAG_UPDATE_HASH;
942 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
944 if (rss_conf->rss_hf & ETH_RSS_IPV4)
945 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
946 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
947 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
948 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
949 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
950 if (rss_conf->rss_hf & ETH_RSS_IPV6)
951 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
952 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
953 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
954 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
955 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
957 /* Update the RSS VNIC(s) */
958 for (i = 0; i < MAX_FF_POOLS; i++) {
959 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
960 vnic->hash_type = hash_type;
963 * Use the supplied key if the key length is
964 * acceptable and the rss_key is not NULL
966 if (rss_conf->rss_key &&
967 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
968 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
969 rss_conf->rss_key_len);
971 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
977 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
978 struct rte_eth_rss_conf *rss_conf)
980 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
981 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
985 /* RSS configuration is the same for all VNICs */
986 if (vnic && vnic->rss_hash_key) {
987 if (rss_conf->rss_key) {
988 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
989 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
990 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
993 hash_types = vnic->hash_type;
994 rss_conf->rss_hf = 0;
995 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
996 rss_conf->rss_hf |= ETH_RSS_IPV4;
997 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
999 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1000 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1002 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1004 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1005 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1007 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1009 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1010 rss_conf->rss_hf |= ETH_RSS_IPV6;
1011 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1013 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1014 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1016 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1018 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1019 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1021 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1025 "Unknwon RSS config from firmware (%08x), RSS disabled",
1030 rss_conf->rss_hf = 0;
1035 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1036 struct rte_eth_fc_conf *fc_conf)
1038 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1039 struct rte_eth_link link_info;
1042 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1046 memset(fc_conf, 0, sizeof(*fc_conf));
1047 if (bp->link_info.auto_pause)
1048 fc_conf->autoneg = 1;
1049 switch (bp->link_info.pause) {
1051 fc_conf->mode = RTE_FC_NONE;
1053 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1054 fc_conf->mode = RTE_FC_TX_PAUSE;
1056 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1057 fc_conf->mode = RTE_FC_RX_PAUSE;
1059 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1060 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1061 fc_conf->mode = RTE_FC_FULL;
1067 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1068 struct rte_eth_fc_conf *fc_conf)
1070 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1072 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1073 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1077 switch (fc_conf->mode) {
1079 bp->link_info.auto_pause = 0;
1080 bp->link_info.force_pause = 0;
1082 case RTE_FC_RX_PAUSE:
1083 if (fc_conf->autoneg) {
1084 bp->link_info.auto_pause =
1085 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1086 bp->link_info.force_pause = 0;
1088 bp->link_info.auto_pause = 0;
1089 bp->link_info.force_pause =
1090 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1093 case RTE_FC_TX_PAUSE:
1094 if (fc_conf->autoneg) {
1095 bp->link_info.auto_pause =
1096 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1097 bp->link_info.force_pause = 0;
1099 bp->link_info.auto_pause = 0;
1100 bp->link_info.force_pause =
1101 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1105 if (fc_conf->autoneg) {
1106 bp->link_info.auto_pause =
1107 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1108 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1109 bp->link_info.force_pause = 0;
1111 bp->link_info.auto_pause = 0;
1112 bp->link_info.force_pause =
1113 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1114 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1118 return bnxt_set_hwrm_link_config(bp, true);
1121 /* Add UDP tunneling port */
1123 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1124 struct rte_eth_udp_tunnel *udp_tunnel)
1126 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1127 uint16_t tunnel_type = 0;
1130 switch (udp_tunnel->prot_type) {
1131 case RTE_TUNNEL_TYPE_VXLAN:
1132 if (bp->vxlan_port_cnt) {
1133 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1134 udp_tunnel->udp_port);
1135 if (bp->vxlan_port != udp_tunnel->udp_port) {
1136 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1139 bp->vxlan_port_cnt++;
1143 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1144 bp->vxlan_port_cnt++;
1146 case RTE_TUNNEL_TYPE_GENEVE:
1147 if (bp->geneve_port_cnt) {
1148 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1149 udp_tunnel->udp_port);
1150 if (bp->geneve_port != udp_tunnel->udp_port) {
1151 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1154 bp->geneve_port_cnt++;
1158 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1159 bp->geneve_port_cnt++;
1162 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1165 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1171 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1172 struct rte_eth_udp_tunnel *udp_tunnel)
1174 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1175 uint16_t tunnel_type = 0;
1179 switch (udp_tunnel->prot_type) {
1180 case RTE_TUNNEL_TYPE_VXLAN:
1181 if (!bp->vxlan_port_cnt) {
1182 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1185 if (bp->vxlan_port != udp_tunnel->udp_port) {
1186 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1187 udp_tunnel->udp_port, bp->vxlan_port);
1190 if (--bp->vxlan_port_cnt)
1194 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1195 port = bp->vxlan_fw_dst_port_id;
1197 case RTE_TUNNEL_TYPE_GENEVE:
1198 if (!bp->geneve_port_cnt) {
1199 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1202 if (bp->geneve_port != udp_tunnel->udp_port) {
1203 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1204 udp_tunnel->udp_port, bp->geneve_port);
1207 if (--bp->geneve_port_cnt)
1211 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1212 port = bp->geneve_fw_dst_port_id;
1215 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1219 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1222 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1225 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1226 bp->geneve_port = 0;
1231 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1233 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1234 struct bnxt_vnic_info *vnic;
1237 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1239 /* Cycle through all VNICs */
1240 for (i = 0; i < bp->nr_vnics; i++) {
1242 * For each VNIC and each associated filter(s)
1243 * if VLAN exists && VLAN matches vlan_id
1244 * remove the MAC+VLAN filter
1245 * add a new MAC only filter
1247 * VLAN filter doesn't exist, just skip and continue
1249 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1250 filter = STAILQ_FIRST(&vnic->filter);
1252 temp_filter = STAILQ_NEXT(filter, next);
1254 if (filter->enables & chk &&
1255 filter->l2_ovlan == vlan_id) {
1256 /* Must delete the filter */
1257 STAILQ_REMOVE(&vnic->filter, filter,
1258 bnxt_filter_info, next);
1259 bnxt_hwrm_clear_l2_filter(bp, filter);
1261 &bp->free_filter_list,
1265 * Need to examine to see if the MAC
1266 * filter already existed or not before
1267 * allocating a new one
1270 new_filter = bnxt_alloc_filter(bp);
1273 "MAC/VLAN filter alloc failed\n");
1277 STAILQ_INSERT_TAIL(&vnic->filter,
1279 /* Inherit MAC from previous filter */
1280 new_filter->mac_index =
1282 memcpy(new_filter->l2_addr,
1283 filter->l2_addr, ETHER_ADDR_LEN);
1284 /* MAC only filter */
1285 rc = bnxt_hwrm_set_l2_filter(bp,
1291 "Del Vlan filter for %d\n",
1294 filter = temp_filter;
1302 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1304 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1305 struct bnxt_vnic_info *vnic;
1308 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN |
1309 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK;
1310 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1312 /* Cycle through all VNICs */
1313 for (i = 0; i < bp->nr_vnics; i++) {
1315 * For each VNIC and each associated filter(s)
1317 * if VLAN matches vlan_id
1318 * VLAN filter already exists, just skip and continue
1320 * add a new MAC+VLAN filter
1322 * Remove the old MAC only filter
1323 * Add a new MAC+VLAN filter
1325 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1326 filter = STAILQ_FIRST(&vnic->filter);
1328 temp_filter = STAILQ_NEXT(filter, next);
1330 if (filter->enables & chk) {
1331 if (filter->l2_ovlan == vlan_id)
1334 /* Must delete the MAC filter */
1335 STAILQ_REMOVE(&vnic->filter, filter,
1336 bnxt_filter_info, next);
1337 bnxt_hwrm_clear_l2_filter(bp, filter);
1338 filter->l2_ovlan = 0;
1340 &bp->free_filter_list,
1343 new_filter = bnxt_alloc_filter(bp);
1346 "MAC/VLAN filter alloc failed\n");
1350 STAILQ_INSERT_TAIL(&vnic->filter, new_filter,
1352 /* Inherit MAC from the previous filter */
1353 new_filter->mac_index = filter->mac_index;
1354 memcpy(new_filter->l2_addr, filter->l2_addr,
1356 /* MAC + VLAN ID filter */
1357 new_filter->l2_ovlan = vlan_id;
1358 new_filter->l2_ovlan_mask = 0xF000;
1359 new_filter->enables |= en;
1360 rc = bnxt_hwrm_set_l2_filter(bp,
1366 "Added Vlan filter for %d\n", vlan_id);
1368 filter = temp_filter;
1376 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1377 uint16_t vlan_id, int on)
1379 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1381 /* These operations apply to ALL existing MAC/VLAN filters */
1383 return bnxt_add_vlan_filter(bp, vlan_id);
1385 return bnxt_del_vlan_filter(bp, vlan_id);
1389 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1391 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1392 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1395 if (mask & ETH_VLAN_FILTER_MASK) {
1396 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1397 /* Remove any VLAN filters programmed */
1398 for (i = 0; i < 4095; i++)
1399 bnxt_del_vlan_filter(bp, i);
1401 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1402 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1405 if (mask & ETH_VLAN_STRIP_MASK) {
1406 /* Enable or disable VLAN stripping */
1407 for (i = 0; i < bp->nr_vnics; i++) {
1408 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1409 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1410 vnic->vlan_strip = true;
1412 vnic->vlan_strip = false;
1413 bnxt_hwrm_vnic_cfg(bp, vnic);
1415 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1416 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1419 if (mask & ETH_VLAN_EXTEND_MASK)
1420 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1426 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr)
1428 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1429 /* Default Filter is tied to VNIC 0 */
1430 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1431 struct bnxt_filter_info *filter;
1437 memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1439 STAILQ_FOREACH(filter, &vnic->filter, next) {
1440 /* Default Filter is at Index 0 */
1441 if (filter->mac_index != 0)
1443 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1446 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN);
1447 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN);
1448 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1450 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1451 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1452 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1455 filter->mac_index = 0;
1456 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1463 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1464 struct ether_addr *mc_addr_set,
1465 uint32_t nb_mc_addr)
1467 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1468 char *mc_addr_list = (char *)mc_addr_set;
1469 struct bnxt_vnic_info *vnic;
1470 uint32_t off = 0, i = 0;
1472 vnic = &bp->vnic_info[0];
1474 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1475 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1479 /* TODO Check for Duplicate mcast addresses */
1480 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1481 for (i = 0; i < nb_mc_addr; i++) {
1482 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN);
1483 off += ETHER_ADDR_LEN;
1486 vnic->mc_addr_cnt = i;
1489 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1493 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1495 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1496 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1497 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1498 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1501 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1502 fw_major, fw_minor, fw_updt);
1504 ret += 1; /* add the size of '\0' */
1505 if (fw_size < (uint32_t)ret)
1512 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1513 struct rte_eth_rxq_info *qinfo)
1515 struct bnxt_rx_queue *rxq;
1517 rxq = dev->data->rx_queues[queue_id];
1519 qinfo->mp = rxq->mb_pool;
1520 qinfo->scattered_rx = dev->data->scattered_rx;
1521 qinfo->nb_desc = rxq->nb_rx_desc;
1523 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1524 qinfo->conf.rx_drop_en = 0;
1525 qinfo->conf.rx_deferred_start = 0;
1529 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1530 struct rte_eth_txq_info *qinfo)
1532 struct bnxt_tx_queue *txq;
1534 txq = dev->data->tx_queues[queue_id];
1536 qinfo->nb_desc = txq->nb_tx_desc;
1538 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1539 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1540 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1542 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1543 qinfo->conf.tx_rs_thresh = 0;
1544 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1547 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1549 struct bnxt *bp = eth_dev->data->dev_private;
1550 struct rte_eth_dev_info dev_info;
1551 uint32_t max_dev_mtu;
1555 bnxt_dev_info_get_op(eth_dev, &dev_info);
1556 max_dev_mtu = dev_info.max_rx_pktlen -
1557 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2;
1559 if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) {
1560 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1561 ETHER_MIN_MTU, max_dev_mtu);
1566 if (new_mtu > ETHER_MTU) {
1567 bp->flags |= BNXT_FLAG_JUMBO;
1568 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1569 DEV_RX_OFFLOAD_JUMBO_FRAME;
1571 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1572 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1573 bp->flags &= ~BNXT_FLAG_JUMBO;
1576 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
1577 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1579 eth_dev->data->mtu = new_mtu;
1580 PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1582 for (i = 0; i < bp->nr_vnics; i++) {
1583 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1585 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1586 ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1587 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1591 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1600 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1602 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1603 uint16_t vlan = bp->vlan;
1606 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1608 "PVID cannot be modified for this function\n");
1611 bp->vlan = on ? pvid : 0;
1613 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1620 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1622 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1624 return bnxt_hwrm_port_led_cfg(bp, true);
1628 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1630 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1632 return bnxt_hwrm_port_led_cfg(bp, false);
1636 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1638 uint32_t desc = 0, raw_cons = 0, cons;
1639 struct bnxt_cp_ring_info *cpr;
1640 struct bnxt_rx_queue *rxq;
1641 struct rx_pkt_cmpl *rxcmp;
1646 rxq = dev->data->rx_queues[rx_queue_id];
1650 while (raw_cons < rxq->nb_rx_desc) {
1651 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1652 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1654 if (!CMPL_VALID(rxcmp, valid))
1656 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1657 cmp_type = CMP_TYPE(rxcmp);
1658 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1659 cmp = (rte_le_to_cpu_32(
1660 ((struct rx_tpa_end_cmpl *)
1661 (rxcmp))->agg_bufs_v1) &
1662 RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1663 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1665 } else if (cmp_type == 0x11) {
1667 cmp = (rxcmp->agg_bufs_v1 &
1668 RX_PKT_CMPL_AGG_BUFS_MASK) >>
1669 RX_PKT_CMPL_AGG_BUFS_SFT;
1674 raw_cons += cmp ? cmp : 2;
1681 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1683 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1684 struct bnxt_rx_ring_info *rxr;
1685 struct bnxt_cp_ring_info *cpr;
1686 struct bnxt_sw_rx_bd *rx_buf;
1687 struct rx_pkt_cmpl *rxcmp;
1688 uint32_t cons, cp_cons;
1696 if (offset >= rxq->nb_rx_desc)
1699 cons = RING_CMP(cpr->cp_ring_struct, offset);
1700 cp_cons = cpr->cp_raw_cons;
1701 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1703 if (cons > cp_cons) {
1704 if (CMPL_VALID(rxcmp, cpr->valid))
1705 return RTE_ETH_RX_DESC_DONE;
1707 if (CMPL_VALID(rxcmp, !cpr->valid))
1708 return RTE_ETH_RX_DESC_DONE;
1710 rx_buf = &rxr->rx_buf_ring[cons];
1711 if (rx_buf->mbuf == NULL)
1712 return RTE_ETH_RX_DESC_UNAVAIL;
1715 return RTE_ETH_RX_DESC_AVAIL;
1719 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1721 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1722 struct bnxt_tx_ring_info *txr;
1723 struct bnxt_cp_ring_info *cpr;
1724 struct bnxt_sw_tx_bd *tx_buf;
1725 struct tx_pkt_cmpl *txcmp;
1726 uint32_t cons, cp_cons;
1734 if (offset >= txq->nb_tx_desc)
1737 cons = RING_CMP(cpr->cp_ring_struct, offset);
1738 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1739 cp_cons = cpr->cp_raw_cons;
1741 if (cons > cp_cons) {
1742 if (CMPL_VALID(txcmp, cpr->valid))
1743 return RTE_ETH_TX_DESC_UNAVAIL;
1745 if (CMPL_VALID(txcmp, !cpr->valid))
1746 return RTE_ETH_TX_DESC_UNAVAIL;
1748 tx_buf = &txr->tx_buf_ring[cons];
1749 if (tx_buf->mbuf == NULL)
1750 return RTE_ETH_TX_DESC_DONE;
1752 return RTE_ETH_TX_DESC_FULL;
1755 static struct bnxt_filter_info *
1756 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1757 struct rte_eth_ethertype_filter *efilter,
1758 struct bnxt_vnic_info *vnic0,
1759 struct bnxt_vnic_info *vnic,
1762 struct bnxt_filter_info *mfilter = NULL;
1766 if (efilter->ether_type == ETHER_TYPE_IPv4 ||
1767 efilter->ether_type == ETHER_TYPE_IPv6) {
1768 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
1769 " ethertype filter.", efilter->ether_type);
1773 if (efilter->queue >= bp->rx_nr_rings) {
1774 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1779 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1780 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1782 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1787 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1788 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1789 if ((!memcmp(efilter->mac_addr.addr_bytes,
1790 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1792 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1793 mfilter->ethertype == efilter->ether_type)) {
1799 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1800 if ((!memcmp(efilter->mac_addr.addr_bytes,
1801 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1802 mfilter->ethertype == efilter->ether_type &&
1804 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
1818 bnxt_ethertype_filter(struct rte_eth_dev *dev,
1819 enum rte_filter_op filter_op,
1822 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1823 struct rte_eth_ethertype_filter *efilter =
1824 (struct rte_eth_ethertype_filter *)arg;
1825 struct bnxt_filter_info *bfilter, *filter1;
1826 struct bnxt_vnic_info *vnic, *vnic0;
1829 if (filter_op == RTE_ETH_FILTER_NOP)
1833 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
1838 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1839 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1841 switch (filter_op) {
1842 case RTE_ETH_FILTER_ADD:
1843 bnxt_match_and_validate_ether_filter(bp, efilter,
1848 bfilter = bnxt_get_unused_filter(bp);
1849 if (bfilter == NULL) {
1851 "Not enough resources for a new filter.\n");
1854 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
1855 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
1857 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
1859 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
1860 bfilter->ethertype = efilter->ether_type;
1861 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
1863 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
1864 if (filter1 == NULL) {
1869 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
1870 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
1872 bfilter->dst_id = vnic->fw_vnic_id;
1874 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1876 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
1879 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
1882 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
1884 case RTE_ETH_FILTER_DELETE:
1885 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
1887 if (ret == -EEXIST) {
1888 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
1890 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
1892 bnxt_free_filter(bp, filter1);
1893 } else if (ret == 0) {
1894 PMD_DRV_LOG(ERR, "No matching filter found\n");
1898 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
1904 bnxt_free_filter(bp, bfilter);
1910 parse_ntuple_filter(struct bnxt *bp,
1911 struct rte_eth_ntuple_filter *nfilter,
1912 struct bnxt_filter_info *bfilter)
1916 if (nfilter->queue >= bp->rx_nr_rings) {
1917 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
1921 switch (nfilter->dst_port_mask) {
1923 bfilter->dst_port_mask = -1;
1924 bfilter->dst_port = nfilter->dst_port;
1925 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
1926 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
1929 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
1933 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
1934 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1936 switch (nfilter->proto_mask) {
1938 if (nfilter->proto == 17) /* IPPROTO_UDP */
1939 bfilter->ip_protocol = 17;
1940 else if (nfilter->proto == 6) /* IPPROTO_TCP */
1941 bfilter->ip_protocol = 6;
1944 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1947 PMD_DRV_LOG(ERR, "invalid protocol mask.");
1951 switch (nfilter->dst_ip_mask) {
1953 bfilter->dst_ipaddr_mask[0] = -1;
1954 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
1955 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
1956 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
1959 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
1963 switch (nfilter->src_ip_mask) {
1965 bfilter->src_ipaddr_mask[0] = -1;
1966 bfilter->src_ipaddr[0] = nfilter->src_ip;
1967 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
1968 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
1971 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
1975 switch (nfilter->src_port_mask) {
1977 bfilter->src_port_mask = -1;
1978 bfilter->src_port = nfilter->src_port;
1979 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
1980 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
1983 PMD_DRV_LOG(ERR, "invalid src_port mask.");
1988 //nfilter->priority = (uint8_t)filter->priority;
1990 bfilter->enables = en;
1994 static struct bnxt_filter_info*
1995 bnxt_match_ntuple_filter(struct bnxt *bp,
1996 struct bnxt_filter_info *bfilter,
1997 struct bnxt_vnic_info **mvnic)
1999 struct bnxt_filter_info *mfilter = NULL;
2002 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2003 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2004 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2005 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2006 bfilter->src_ipaddr_mask[0] ==
2007 mfilter->src_ipaddr_mask[0] &&
2008 bfilter->src_port == mfilter->src_port &&
2009 bfilter->src_port_mask == mfilter->src_port_mask &&
2010 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2011 bfilter->dst_ipaddr_mask[0] ==
2012 mfilter->dst_ipaddr_mask[0] &&
2013 bfilter->dst_port == mfilter->dst_port &&
2014 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2015 bfilter->flags == mfilter->flags &&
2016 bfilter->enables == mfilter->enables) {
2027 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2028 struct rte_eth_ntuple_filter *nfilter,
2029 enum rte_filter_op filter_op)
2031 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2032 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2035 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2036 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2040 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2041 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2045 bfilter = bnxt_get_unused_filter(bp);
2046 if (bfilter == NULL) {
2048 "Not enough resources for a new filter.\n");
2051 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2055 vnic = STAILQ_FIRST(&bp->ff_pool[nfilter->queue]);
2056 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2057 filter1 = STAILQ_FIRST(&vnic0->filter);
2058 if (filter1 == NULL) {
2063 bfilter->dst_id = vnic->fw_vnic_id;
2064 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2066 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2067 bfilter->ethertype = 0x800;
2068 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2070 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2072 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2073 bfilter->dst_id == mfilter->dst_id) {
2074 PMD_DRV_LOG(ERR, "filter exists.\n");
2077 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2078 bfilter->dst_id != mfilter->dst_id) {
2079 mfilter->dst_id = vnic->fw_vnic_id;
2080 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2081 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2082 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2083 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2084 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2087 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2088 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2093 if (filter_op == RTE_ETH_FILTER_ADD) {
2094 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2095 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2098 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2100 if (mfilter == NULL) {
2101 /* This should not happen. But for Coverity! */
2105 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2107 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2108 bnxt_free_filter(bp, mfilter);
2109 mfilter->fw_l2_filter_id = -1;
2110 bnxt_free_filter(bp, bfilter);
2111 bfilter->fw_l2_filter_id = -1;
2116 bfilter->fw_l2_filter_id = -1;
2117 bnxt_free_filter(bp, bfilter);
2122 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2123 enum rte_filter_op filter_op,
2126 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2129 if (filter_op == RTE_ETH_FILTER_NOP)
2133 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2138 switch (filter_op) {
2139 case RTE_ETH_FILTER_ADD:
2140 ret = bnxt_cfg_ntuple_filter(bp,
2141 (struct rte_eth_ntuple_filter *)arg,
2144 case RTE_ETH_FILTER_DELETE:
2145 ret = bnxt_cfg_ntuple_filter(bp,
2146 (struct rte_eth_ntuple_filter *)arg,
2150 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2158 bnxt_parse_fdir_filter(struct bnxt *bp,
2159 struct rte_eth_fdir_filter *fdir,
2160 struct bnxt_filter_info *filter)
2162 enum rte_fdir_mode fdir_mode =
2163 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2164 struct bnxt_vnic_info *vnic0, *vnic;
2165 struct bnxt_filter_info *filter1;
2169 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2172 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2173 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2175 switch (fdir->input.flow_type) {
2176 case RTE_ETH_FLOW_IPV4:
2177 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2179 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2180 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2181 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2182 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2183 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2184 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2185 filter->ip_addr_type =
2186 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2187 filter->src_ipaddr_mask[0] = 0xffffffff;
2188 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2189 filter->dst_ipaddr_mask[0] = 0xffffffff;
2190 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2191 filter->ethertype = 0x800;
2192 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2194 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2195 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2196 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2197 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2198 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2199 filter->dst_port_mask = 0xffff;
2200 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2201 filter->src_port_mask = 0xffff;
2202 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2203 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2204 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2205 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2206 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2207 filter->ip_protocol = 6;
2208 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2209 filter->ip_addr_type =
2210 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2211 filter->src_ipaddr_mask[0] = 0xffffffff;
2212 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2213 filter->dst_ipaddr_mask[0] = 0xffffffff;
2214 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2215 filter->ethertype = 0x800;
2216 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2218 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2219 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2220 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2221 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2222 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2223 filter->dst_port_mask = 0xffff;
2224 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2225 filter->src_port_mask = 0xffff;
2226 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2227 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2228 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2229 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2230 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2231 filter->ip_protocol = 17;
2232 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2233 filter->ip_addr_type =
2234 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2235 filter->src_ipaddr_mask[0] = 0xffffffff;
2236 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2237 filter->dst_ipaddr_mask[0] = 0xffffffff;
2238 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2239 filter->ethertype = 0x800;
2240 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2242 case RTE_ETH_FLOW_IPV6:
2243 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2245 filter->ip_addr_type =
2246 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2247 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2248 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2249 rte_memcpy(filter->src_ipaddr,
2250 fdir->input.flow.ipv6_flow.src_ip, 16);
2251 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2252 rte_memcpy(filter->dst_ipaddr,
2253 fdir->input.flow.ipv6_flow.dst_ip, 16);
2254 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2255 memset(filter->dst_ipaddr_mask, 0xff, 16);
2256 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2257 memset(filter->src_ipaddr_mask, 0xff, 16);
2258 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2259 filter->ethertype = 0x86dd;
2260 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2262 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2263 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2264 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2265 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2266 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2267 filter->dst_port_mask = 0xffff;
2268 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2269 filter->src_port_mask = 0xffff;
2270 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2271 filter->ip_addr_type =
2272 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2273 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2274 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2275 rte_memcpy(filter->src_ipaddr,
2276 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2277 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2278 rte_memcpy(filter->dst_ipaddr,
2279 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2280 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2281 memset(filter->dst_ipaddr_mask, 0xff, 16);
2282 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2283 memset(filter->src_ipaddr_mask, 0xff, 16);
2284 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2285 filter->ethertype = 0x86dd;
2286 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2288 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2289 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2290 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2291 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2292 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2293 filter->dst_port_mask = 0xffff;
2294 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2295 filter->src_port_mask = 0xffff;
2296 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2297 filter->ip_addr_type =
2298 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2299 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2300 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2301 rte_memcpy(filter->src_ipaddr,
2302 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2303 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2304 rte_memcpy(filter->dst_ipaddr,
2305 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2306 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2307 memset(filter->dst_ipaddr_mask, 0xff, 16);
2308 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2309 memset(filter->src_ipaddr_mask, 0xff, 16);
2310 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2311 filter->ethertype = 0x86dd;
2312 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2314 case RTE_ETH_FLOW_L2_PAYLOAD:
2315 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2316 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2318 case RTE_ETH_FLOW_VXLAN:
2319 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2321 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2322 filter->tunnel_type =
2323 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2324 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2326 case RTE_ETH_FLOW_NVGRE:
2327 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2329 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2330 filter->tunnel_type =
2331 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2332 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2334 case RTE_ETH_FLOW_UNKNOWN:
2335 case RTE_ETH_FLOW_RAW:
2336 case RTE_ETH_FLOW_FRAG_IPV4:
2337 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2338 case RTE_ETH_FLOW_FRAG_IPV6:
2339 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2340 case RTE_ETH_FLOW_IPV6_EX:
2341 case RTE_ETH_FLOW_IPV6_TCP_EX:
2342 case RTE_ETH_FLOW_IPV6_UDP_EX:
2343 case RTE_ETH_FLOW_GENEVE:
2349 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2350 vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2352 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2357 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2358 rte_memcpy(filter->dst_macaddr,
2359 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2360 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2363 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2364 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2365 filter1 = STAILQ_FIRST(&vnic0->filter);
2366 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2368 filter->dst_id = vnic->fw_vnic_id;
2369 for (i = 0; i < ETHER_ADDR_LEN; i++)
2370 if (filter->dst_macaddr[i] == 0x00)
2371 filter1 = STAILQ_FIRST(&vnic0->filter);
2373 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2376 if (filter1 == NULL)
2379 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2380 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2382 filter->enables = en;
2387 static struct bnxt_filter_info *
2388 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2389 struct bnxt_vnic_info **mvnic)
2391 struct bnxt_filter_info *mf = NULL;
2394 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2395 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2397 STAILQ_FOREACH(mf, &vnic->filter, next) {
2398 if (mf->filter_type == nf->filter_type &&
2399 mf->flags == nf->flags &&
2400 mf->src_port == nf->src_port &&
2401 mf->src_port_mask == nf->src_port_mask &&
2402 mf->dst_port == nf->dst_port &&
2403 mf->dst_port_mask == nf->dst_port_mask &&
2404 mf->ip_protocol == nf->ip_protocol &&
2405 mf->ip_addr_type == nf->ip_addr_type &&
2406 mf->ethertype == nf->ethertype &&
2407 mf->vni == nf->vni &&
2408 mf->tunnel_type == nf->tunnel_type &&
2409 mf->l2_ovlan == nf->l2_ovlan &&
2410 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2411 mf->l2_ivlan == nf->l2_ivlan &&
2412 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2413 !memcmp(mf->l2_addr, nf->l2_addr, ETHER_ADDR_LEN) &&
2414 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2416 !memcmp(mf->src_macaddr, nf->src_macaddr,
2418 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2420 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2421 sizeof(nf->src_ipaddr)) &&
2422 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2423 sizeof(nf->src_ipaddr_mask)) &&
2424 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2425 sizeof(nf->dst_ipaddr)) &&
2426 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2427 sizeof(nf->dst_ipaddr_mask))) {
2438 bnxt_fdir_filter(struct rte_eth_dev *dev,
2439 enum rte_filter_op filter_op,
2442 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2443 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2444 struct bnxt_filter_info *filter, *match;
2445 struct bnxt_vnic_info *vnic, *mvnic;
2448 if (filter_op == RTE_ETH_FILTER_NOP)
2451 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2454 switch (filter_op) {
2455 case RTE_ETH_FILTER_ADD:
2456 case RTE_ETH_FILTER_DELETE:
2458 filter = bnxt_get_unused_filter(bp);
2459 if (filter == NULL) {
2461 "Not enough resources for a new flow.\n");
2465 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2468 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2470 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2471 vnic = STAILQ_FIRST(&bp->ff_pool[0]);
2473 vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2475 match = bnxt_match_fdir(bp, filter, &mvnic);
2476 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2477 if (match->dst_id == vnic->fw_vnic_id) {
2478 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2482 match->dst_id = vnic->fw_vnic_id;
2483 ret = bnxt_hwrm_set_ntuple_filter(bp,
2486 STAILQ_REMOVE(&mvnic->filter, match,
2487 bnxt_filter_info, next);
2488 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2490 "Filter with matching pattern exist\n");
2492 "Updated it to new destination q\n");
2496 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2497 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2502 if (filter_op == RTE_ETH_FILTER_ADD) {
2503 ret = bnxt_hwrm_set_ntuple_filter(bp,
2508 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2510 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2511 STAILQ_REMOVE(&vnic->filter, match,
2512 bnxt_filter_info, next);
2513 bnxt_free_filter(bp, match);
2514 filter->fw_l2_filter_id = -1;
2515 bnxt_free_filter(bp, filter);
2518 case RTE_ETH_FILTER_FLUSH:
2519 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2520 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2522 STAILQ_FOREACH(filter, &vnic->filter, next) {
2523 if (filter->filter_type ==
2524 HWRM_CFA_NTUPLE_FILTER) {
2526 bnxt_hwrm_clear_ntuple_filter(bp,
2528 STAILQ_REMOVE(&vnic->filter, filter,
2529 bnxt_filter_info, next);
2534 case RTE_ETH_FILTER_UPDATE:
2535 case RTE_ETH_FILTER_STATS:
2536 case RTE_ETH_FILTER_INFO:
2537 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2540 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2547 filter->fw_l2_filter_id = -1;
2548 bnxt_free_filter(bp, filter);
2553 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2554 enum rte_filter_type filter_type,
2555 enum rte_filter_op filter_op, void *arg)
2559 switch (filter_type) {
2560 case RTE_ETH_FILTER_TUNNEL:
2562 "filter type: %d: To be implemented\n", filter_type);
2564 case RTE_ETH_FILTER_FDIR:
2565 ret = bnxt_fdir_filter(dev, filter_op, arg);
2567 case RTE_ETH_FILTER_NTUPLE:
2568 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2570 case RTE_ETH_FILTER_ETHERTYPE:
2571 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2573 case RTE_ETH_FILTER_GENERIC:
2574 if (filter_op != RTE_ETH_FILTER_GET)
2576 *(const void **)arg = &bnxt_flow_ops;
2580 "Filter type (%d) not supported", filter_type);
2587 static const uint32_t *
2588 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2590 static const uint32_t ptypes[] = {
2591 RTE_PTYPE_L2_ETHER_VLAN,
2592 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2593 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2597 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2598 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2599 RTE_PTYPE_INNER_L4_ICMP,
2600 RTE_PTYPE_INNER_L4_TCP,
2601 RTE_PTYPE_INNER_L4_UDP,
2605 if (dev->rx_pkt_burst == bnxt_recv_pkts)
2610 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2613 uint32_t reg_base = *reg_arr & 0xfffff000;
2617 for (i = 0; i < count; i++) {
2618 if ((reg_arr[i] & 0xfffff000) != reg_base)
2621 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2622 rte_cpu_to_le_32(rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off));
2626 static int bnxt_map_ptp_regs(struct bnxt *bp)
2628 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2632 reg_arr = ptp->rx_regs;
2633 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2637 reg_arr = ptp->tx_regs;
2638 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2642 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2643 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2645 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2646 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2651 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2653 rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2654 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16));
2655 rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2656 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20));
2659 static uint64_t bnxt_cc_read(struct bnxt *bp)
2663 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2664 BNXT_GRCPF_REG_SYNC_TIME));
2665 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2666 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2670 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2672 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2675 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2676 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2677 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2680 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2681 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2682 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2683 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2684 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2685 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2690 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2692 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2693 struct bnxt_pf_info *pf = &bp->pf;
2700 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2701 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2702 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2705 port_id = pf->port_id;
2706 rte_cpu_to_le_32(rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2707 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]));
2709 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2710 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2711 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2712 /* bnxt_clr_rx_ts(bp); TBD */
2716 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2717 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2718 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2719 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2725 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2728 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2729 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2734 ns = rte_timespec_to_ns(ts);
2735 /* Set the timecounters to a new value. */
2742 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2744 uint64_t ns, systime_cycles;
2745 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2746 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2751 systime_cycles = bnxt_cc_read(bp);
2752 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
2753 *ts = rte_ns_to_timespec(ns);
2758 bnxt_timesync_enable(struct rte_eth_dev *dev)
2760 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2761 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2768 ptp->tx_tstamp_en = 1;
2769 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
2771 if (!bnxt_hwrm_ptp_cfg(bp))
2772 bnxt_map_ptp_regs(bp);
2774 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
2775 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2776 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2778 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2779 ptp->tc.cc_shift = shift;
2780 ptp->tc.nsec_mask = (1ULL << shift) - 1;
2782 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2783 ptp->rx_tstamp_tc.cc_shift = shift;
2784 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2786 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2787 ptp->tx_tstamp_tc.cc_shift = shift;
2788 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2794 bnxt_timesync_disable(struct rte_eth_dev *dev)
2796 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2797 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2803 ptp->tx_tstamp_en = 0;
2806 bnxt_hwrm_ptp_cfg(bp);
2808 bnxt_unmap_ptp_regs(bp);
2814 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
2815 struct timespec *timestamp,
2816 uint32_t flags __rte_unused)
2818 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2819 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2820 uint64_t rx_tstamp_cycles = 0;
2826 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
2827 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
2828 *timestamp = rte_ns_to_timespec(ns);
2833 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
2834 struct timespec *timestamp)
2836 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2837 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2838 uint64_t tx_tstamp_cycles = 0;
2844 bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
2845 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
2846 *timestamp = rte_ns_to_timespec(ns);
2852 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
2854 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2855 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2860 ptp->tc.nsec += delta;
2866 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
2868 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2870 uint32_t dir_entries;
2871 uint32_t entry_length;
2873 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
2874 bp->pdev->addr.domain, bp->pdev->addr.bus,
2875 bp->pdev->addr.devid, bp->pdev->addr.function);
2877 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
2881 return dir_entries * entry_length;
2885 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
2886 struct rte_dev_eeprom_info *in_eeprom)
2888 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2892 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2893 "len = %d\n", bp->pdev->addr.domain,
2894 bp->pdev->addr.bus, bp->pdev->addr.devid,
2895 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2897 if (in_eeprom->offset == 0) /* special offset value to get directory */
2898 return bnxt_get_nvram_directory(bp, in_eeprom->length,
2901 index = in_eeprom->offset >> 24;
2902 offset = in_eeprom->offset & 0xffffff;
2905 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
2906 in_eeprom->length, in_eeprom->data);
2911 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
2914 case BNX_DIR_TYPE_CHIMP_PATCH:
2915 case BNX_DIR_TYPE_BOOTCODE:
2916 case BNX_DIR_TYPE_BOOTCODE_2:
2917 case BNX_DIR_TYPE_APE_FW:
2918 case BNX_DIR_TYPE_APE_PATCH:
2919 case BNX_DIR_TYPE_KONG_FW:
2920 case BNX_DIR_TYPE_KONG_PATCH:
2921 case BNX_DIR_TYPE_BONO_FW:
2922 case BNX_DIR_TYPE_BONO_PATCH:
2930 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
2933 case BNX_DIR_TYPE_AVS:
2934 case BNX_DIR_TYPE_EXP_ROM_MBA:
2935 case BNX_DIR_TYPE_PCIE:
2936 case BNX_DIR_TYPE_TSCF_UCODE:
2937 case BNX_DIR_TYPE_EXT_PHY:
2938 case BNX_DIR_TYPE_CCM:
2939 case BNX_DIR_TYPE_ISCSI_BOOT:
2940 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2941 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2949 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
2951 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2952 bnxt_dir_type_is_other_exec_format(dir_type);
2956 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
2957 struct rte_dev_eeprom_info *in_eeprom)
2959 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2960 uint8_t index, dir_op;
2961 uint16_t type, ext, ordinal, attr;
2963 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2964 "len = %d\n", bp->pdev->addr.domain,
2965 bp->pdev->addr.bus, bp->pdev->addr.devid,
2966 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2969 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
2973 type = in_eeprom->magic >> 16;
2975 if (type == 0xffff) { /* special value for directory operations */
2976 index = in_eeprom->magic & 0xff;
2977 dir_op = in_eeprom->magic >> 8;
2981 case 0x0e: /* erase */
2982 if (in_eeprom->offset != ~in_eeprom->magic)
2984 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
2990 /* Create or re-write an NVM item: */
2991 if (bnxt_dir_type_is_executable(type) == true)
2993 ext = in_eeprom->magic & 0xffff;
2994 ordinal = in_eeprom->offset >> 16;
2995 attr = in_eeprom->offset & 0xffff;
2997 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
2998 in_eeprom->data, in_eeprom->length);
3006 static const struct eth_dev_ops bnxt_dev_ops = {
3007 .dev_infos_get = bnxt_dev_info_get_op,
3008 .dev_close = bnxt_dev_close_op,
3009 .dev_configure = bnxt_dev_configure_op,
3010 .dev_start = bnxt_dev_start_op,
3011 .dev_stop = bnxt_dev_stop_op,
3012 .dev_set_link_up = bnxt_dev_set_link_up_op,
3013 .dev_set_link_down = bnxt_dev_set_link_down_op,
3014 .stats_get = bnxt_stats_get_op,
3015 .stats_reset = bnxt_stats_reset_op,
3016 .rx_queue_setup = bnxt_rx_queue_setup_op,
3017 .rx_queue_release = bnxt_rx_queue_release_op,
3018 .tx_queue_setup = bnxt_tx_queue_setup_op,
3019 .tx_queue_release = bnxt_tx_queue_release_op,
3020 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3021 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3022 .reta_update = bnxt_reta_update_op,
3023 .reta_query = bnxt_reta_query_op,
3024 .rss_hash_update = bnxt_rss_hash_update_op,
3025 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3026 .link_update = bnxt_link_update_op,
3027 .promiscuous_enable = bnxt_promiscuous_enable_op,
3028 .promiscuous_disable = bnxt_promiscuous_disable_op,
3029 .allmulticast_enable = bnxt_allmulticast_enable_op,
3030 .allmulticast_disable = bnxt_allmulticast_disable_op,
3031 .mac_addr_add = bnxt_mac_addr_add_op,
3032 .mac_addr_remove = bnxt_mac_addr_remove_op,
3033 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3034 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3035 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3036 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3037 .vlan_filter_set = bnxt_vlan_filter_set_op,
3038 .vlan_offload_set = bnxt_vlan_offload_set_op,
3039 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3040 .mtu_set = bnxt_mtu_set_op,
3041 .mac_addr_set = bnxt_set_default_mac_addr_op,
3042 .xstats_get = bnxt_dev_xstats_get_op,
3043 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3044 .xstats_reset = bnxt_dev_xstats_reset_op,
3045 .fw_version_get = bnxt_fw_version_get,
3046 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3047 .rxq_info_get = bnxt_rxq_info_get_op,
3048 .txq_info_get = bnxt_txq_info_get_op,
3049 .dev_led_on = bnxt_dev_led_on_op,
3050 .dev_led_off = bnxt_dev_led_off_op,
3051 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3052 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3053 .rx_queue_count = bnxt_rx_queue_count_op,
3054 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3055 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3056 .rx_queue_start = bnxt_rx_queue_start,
3057 .rx_queue_stop = bnxt_rx_queue_stop,
3058 .tx_queue_start = bnxt_tx_queue_start,
3059 .tx_queue_stop = bnxt_tx_queue_stop,
3060 .filter_ctrl = bnxt_filter_ctrl_op,
3061 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3062 .get_eeprom_length = bnxt_get_eeprom_length_op,
3063 .get_eeprom = bnxt_get_eeprom_op,
3064 .set_eeprom = bnxt_set_eeprom_op,
3065 .timesync_enable = bnxt_timesync_enable,
3066 .timesync_disable = bnxt_timesync_disable,
3067 .timesync_read_time = bnxt_timesync_read_time,
3068 .timesync_write_time = bnxt_timesync_write_time,
3069 .timesync_adjust_time = bnxt_timesync_adjust_time,
3070 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3071 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3074 static bool bnxt_vf_pciid(uint16_t id)
3076 if (id == BROADCOM_DEV_ID_57304_VF ||
3077 id == BROADCOM_DEV_ID_57406_VF ||
3078 id == BROADCOM_DEV_ID_5731X_VF ||
3079 id == BROADCOM_DEV_ID_5741X_VF ||
3080 id == BROADCOM_DEV_ID_57414_VF ||
3081 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3082 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3083 id == BROADCOM_DEV_ID_58802_VF)
3088 bool bnxt_stratus_device(struct bnxt *bp)
3090 uint16_t id = bp->pdev->id.device_id;
3092 if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3093 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3094 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3099 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3101 struct bnxt *bp = eth_dev->data->dev_private;
3102 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3105 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3106 if (!pci_dev->mem_resource[0].addr) {
3108 "Cannot find PCI device base address, aborting\n");
3110 goto init_err_disable;
3113 bp->eth_dev = eth_dev;
3116 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3118 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3120 goto init_err_release;
3123 if (!pci_dev->mem_resource[2].addr) {
3125 "Cannot find PCI device BAR 2 address, aborting\n");
3127 goto init_err_release;
3129 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3137 if (bp->doorbell_base)
3138 bp->doorbell_base = NULL;
3146 #define ALLOW_FUNC(x) \
3148 typeof(x) arg = (x); \
3149 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3150 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3153 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3155 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3156 char mz_name[RTE_MEMZONE_NAMESIZE];
3157 const struct rte_memzone *mz = NULL;
3158 static int version_printed;
3159 uint32_t total_alloc_len;
3160 rte_iova_t mz_phys_addr;
3164 if (version_printed++ == 0)
3165 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3167 rte_eth_copy_pci_info(eth_dev, pci_dev);
3169 bp = eth_dev->data->dev_private;
3171 bp->dev_stopped = 1;
3173 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3176 if (bnxt_vf_pciid(pci_dev->id.device_id))
3177 bp->flags |= BNXT_FLAG_VF;
3179 rc = bnxt_init_board(eth_dev);
3182 "Board initialization failed rc: %x\n", rc);
3186 eth_dev->dev_ops = &bnxt_dev_ops;
3187 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3188 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3189 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3192 if (pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3193 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3194 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3195 pci_dev->addr.bus, pci_dev->addr.devid,
3196 pci_dev->addr.function, "rx_port_stats");
3197 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3198 mz = rte_memzone_lookup(mz_name);
3199 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3200 sizeof(struct rx_port_stats) + 512);
3202 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3205 RTE_MEMZONE_SIZE_HINT_ONLY |
3206 RTE_MEMZONE_IOVA_CONTIG);
3210 memset(mz->addr, 0, mz->len);
3211 mz_phys_addr = mz->iova;
3212 if ((unsigned long)mz->addr == mz_phys_addr) {
3213 PMD_DRV_LOG(WARNING,
3214 "Memzone physical address same as virtual.\n");
3215 PMD_DRV_LOG(WARNING,
3216 "Using rte_mem_virt2iova()\n");
3217 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3218 if (mz_phys_addr == 0) {
3220 "unable to map address to physical memory\n");
3225 bp->rx_mem_zone = (const void *)mz;
3226 bp->hw_rx_port_stats = mz->addr;
3227 bp->hw_rx_port_stats_map = mz_phys_addr;
3229 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3230 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3231 pci_dev->addr.bus, pci_dev->addr.devid,
3232 pci_dev->addr.function, "tx_port_stats");
3233 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3234 mz = rte_memzone_lookup(mz_name);
3235 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3236 sizeof(struct tx_port_stats) + 512);
3238 mz = rte_memzone_reserve(mz_name,
3242 RTE_MEMZONE_SIZE_HINT_ONLY |
3243 RTE_MEMZONE_IOVA_CONTIG);
3247 memset(mz->addr, 0, mz->len);
3248 mz_phys_addr = mz->iova;
3249 if ((unsigned long)mz->addr == mz_phys_addr) {
3250 PMD_DRV_LOG(WARNING,
3251 "Memzone physical address same as virtual.\n");
3252 PMD_DRV_LOG(WARNING,
3253 "Using rte_mem_virt2iova()\n");
3254 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3255 if (mz_phys_addr == 0) {
3257 "unable to map address to physical memory\n");
3262 bp->tx_mem_zone = (const void *)mz;
3263 bp->hw_tx_port_stats = mz->addr;
3264 bp->hw_tx_port_stats_map = mz_phys_addr;
3266 bp->flags |= BNXT_FLAG_PORT_STATS;
3269 rc = bnxt_alloc_hwrm_resources(bp);
3272 "hwrm resource allocation failure rc: %x\n", rc);
3275 rc = bnxt_hwrm_ver_get(bp);
3278 rc = bnxt_hwrm_queue_qportcfg(bp);
3280 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3284 rc = bnxt_hwrm_func_qcfg(bp);
3286 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3290 /* Get the MAX capabilities for this function */
3291 rc = bnxt_hwrm_func_qcaps(bp);
3293 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3296 if (bp->max_tx_rings == 0) {
3297 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3301 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3302 ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3303 if (eth_dev->data->mac_addrs == NULL) {
3305 "Failed to alloc %u bytes needed to store MAC addr tbl",
3306 ETHER_ADDR_LEN * bp->max_l2_ctx);
3311 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, ETHER_ADDR_LEN)) {
3313 "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
3314 bp->dflt_mac_addr[0], bp->dflt_mac_addr[1],
3315 bp->dflt_mac_addr[2], bp->dflt_mac_addr[3],
3316 bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]);
3320 /* Copy the permanent MAC from the qcap response address now. */
3321 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3322 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
3324 if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3325 /* 1 ring is for default completion ring */
3326 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3331 bp->grp_info = rte_zmalloc("bnxt_grp_info",
3332 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3333 if (!bp->grp_info) {
3335 "Failed to alloc %zu bytes to store group info table\n",
3336 sizeof(*bp->grp_info) * bp->max_ring_grps);
3341 /* Forward all requests if firmware is new enough */
3342 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3343 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3344 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3345 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3347 PMD_DRV_LOG(WARNING,
3348 "Firmware too old for VF mailbox functionality\n");
3349 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3353 * The following are used for driver cleanup. If we disallow these,
3354 * VF drivers can't clean up cleanly.
3356 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3357 ALLOW_FUNC(HWRM_VNIC_FREE);
3358 ALLOW_FUNC(HWRM_RING_FREE);
3359 ALLOW_FUNC(HWRM_RING_GRP_FREE);
3360 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3361 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3362 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3363 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3364 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3365 rc = bnxt_hwrm_func_driver_register(bp);
3368 "Failed to register driver");
3374 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3375 pci_dev->mem_resource[0].phys_addr,
3376 pci_dev->mem_resource[0].addr);
3378 rc = bnxt_hwrm_func_reset(bp);
3380 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3386 //if (bp->pf.active_vfs) {
3387 // TODO: Deallocate VF resources?
3389 if (bp->pdev->max_vfs) {
3390 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3392 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3396 rc = bnxt_hwrm_allocate_pf_only(bp);
3399 "Failed to allocate PF resources\n");
3405 bnxt_hwrm_port_led_qcaps(bp);
3407 rc = bnxt_setup_int(bp);
3411 rc = bnxt_alloc_mem(bp);
3413 goto error_free_int;
3415 rc = bnxt_request_int(bp);
3417 goto error_free_int;
3419 bnxt_enable_int(bp);
3425 bnxt_disable_int(bp);
3426 bnxt_hwrm_func_buf_unrgtr(bp);
3430 bnxt_dev_uninit(eth_dev);
3436 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
3438 struct bnxt *bp = eth_dev->data->dev_private;
3441 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3444 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
3445 bnxt_disable_int(bp);
3448 if (eth_dev->data->mac_addrs != NULL) {
3449 rte_free(eth_dev->data->mac_addrs);
3450 eth_dev->data->mac_addrs = NULL;
3452 if (bp->grp_info != NULL) {
3453 rte_free(bp->grp_info);
3454 bp->grp_info = NULL;
3456 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3457 bnxt_free_hwrm_resources(bp);
3459 if (bp->tx_mem_zone) {
3460 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3461 bp->tx_mem_zone = NULL;
3464 if (bp->rx_mem_zone) {
3465 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3466 bp->rx_mem_zone = NULL;
3469 if (bp->dev_stopped == 0)
3470 bnxt_dev_close_op(eth_dev);
3472 rte_free(bp->pf.vf_info);
3473 eth_dev->dev_ops = NULL;
3474 eth_dev->rx_pkt_burst = NULL;
3475 eth_dev->tx_pkt_burst = NULL;
3480 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3481 struct rte_pci_device *pci_dev)
3483 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
3487 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
3489 return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
3492 static struct rte_pci_driver bnxt_rte_pmd = {
3493 .id_table = bnxt_pci_id_map,
3494 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
3495 RTE_PCI_DRV_INTR_LSC,
3496 .probe = bnxt_pci_probe,
3497 .remove = bnxt_pci_remove,
3501 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
3503 if (strcmp(dev->device->driver->name, drv->driver.name))
3509 bool is_bnxt_supported(struct rte_eth_dev *dev)
3511 return is_device_supported(dev, &bnxt_rte_pmd);
3514 RTE_INIT(bnxt_init_log);
3518 bnxt_logtype_driver = rte_log_register("pmd.bnxt.driver");
3519 if (bnxt_logtype_driver >= 0)
3520 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_INFO);
3523 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
3524 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
3525 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");