1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
29 #include "bnxt_util.h"
31 #define DRV_MODULE_NAME "bnxt"
32 static const char bnxt_version[] =
33 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
34 int bnxt_logtype_driver;
36 #define PCI_VENDOR_ID_BROADCOM 0x14E4
38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
41 #define BROADCOM_DEV_ID_57414_VF 0x16c1
42 #define BROADCOM_DEV_ID_57301 0x16c8
43 #define BROADCOM_DEV_ID_57302 0x16c9
44 #define BROADCOM_DEV_ID_57304_PF 0x16ca
45 #define BROADCOM_DEV_ID_57304_VF 0x16cb
46 #define BROADCOM_DEV_ID_57417_MF 0x16cc
47 #define BROADCOM_DEV_ID_NS2 0x16cd
48 #define BROADCOM_DEV_ID_57311 0x16ce
49 #define BROADCOM_DEV_ID_57312 0x16cf
50 #define BROADCOM_DEV_ID_57402 0x16d0
51 #define BROADCOM_DEV_ID_57404 0x16d1
52 #define BROADCOM_DEV_ID_57406_PF 0x16d2
53 #define BROADCOM_DEV_ID_57406_VF 0x16d3
54 #define BROADCOM_DEV_ID_57402_MF 0x16d4
55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
56 #define BROADCOM_DEV_ID_57412 0x16d6
57 #define BROADCOM_DEV_ID_57414 0x16d7
58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
61 #define BROADCOM_DEV_ID_57412_MF 0x16de
62 #define BROADCOM_DEV_ID_57314 0x16df
63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
68 #define BROADCOM_DEV_ID_57404_MF 0x16e7
69 #define BROADCOM_DEV_ID_57406_MF 0x16e8
70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
71 #define BROADCOM_DEV_ID_57407_MF 0x16ea
72 #define BROADCOM_DEV_ID_57414_MF 0x16ec
73 #define BROADCOM_DEV_ID_57416_MF 0x16ee
74 #define BROADCOM_DEV_ID_57508 0x1750
75 #define BROADCOM_DEV_ID_57504 0x1751
76 #define BROADCOM_DEV_ID_57502 0x1752
77 #define BROADCOM_DEV_ID_57500_VF 0x1807
78 #define BROADCOM_DEV_ID_58802 0xd802
79 #define BROADCOM_DEV_ID_58804 0xd804
80 #define BROADCOM_DEV_ID_58808 0x16f0
81 #define BROADCOM_DEV_ID_58802_VF 0xd800
83 static const struct rte_pci_id bnxt_pci_id_map[] = {
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
85 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
87 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF) },
130 { .vendor_id = 0, /* sentinel */ },
133 #define BNXT_ETH_RSS_SUPPORT ( \
135 ETH_RSS_NONFRAG_IPV4_TCP | \
136 ETH_RSS_NONFRAG_IPV4_UDP | \
138 ETH_RSS_NONFRAG_IPV6_TCP | \
139 ETH_RSS_NONFRAG_IPV6_UDP)
141 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
142 DEV_TX_OFFLOAD_IPV4_CKSUM | \
143 DEV_TX_OFFLOAD_TCP_CKSUM | \
144 DEV_TX_OFFLOAD_UDP_CKSUM | \
145 DEV_TX_OFFLOAD_TCP_TSO | \
146 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
147 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
148 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
149 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
150 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
151 DEV_TX_OFFLOAD_MULTI_SEGS)
153 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
154 DEV_RX_OFFLOAD_VLAN_STRIP | \
155 DEV_RX_OFFLOAD_IPV4_CKSUM | \
156 DEV_RX_OFFLOAD_UDP_CKSUM | \
157 DEV_RX_OFFLOAD_TCP_CKSUM | \
158 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
159 DEV_RX_OFFLOAD_JUMBO_FRAME | \
160 DEV_RX_OFFLOAD_KEEP_CRC | \
161 DEV_RX_OFFLOAD_TCP_LRO)
163 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
164 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
165 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
166 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
168 /***********************/
171 * High level utility functions
174 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
176 if (!BNXT_CHIP_THOR(bp))
179 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
180 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
181 BNXT_RSS_ENTRIES_PER_CTX_THOR;
184 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
186 if (!BNXT_CHIP_THOR(bp))
187 return HW_HASH_INDEX_SIZE;
189 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
192 static void bnxt_free_mem(struct bnxt *bp)
194 bnxt_free_filter_mem(bp);
195 bnxt_free_vnic_attributes(bp);
196 bnxt_free_vnic_mem(bp);
199 bnxt_free_tx_rings(bp);
200 bnxt_free_rx_rings(bp);
203 static int bnxt_alloc_mem(struct bnxt *bp)
207 rc = bnxt_alloc_vnic_mem(bp);
211 rc = bnxt_alloc_vnic_attributes(bp);
215 rc = bnxt_alloc_filter_mem(bp);
226 static int bnxt_init_chip(struct bnxt *bp)
228 struct bnxt_rx_queue *rxq;
229 struct rte_eth_link new;
230 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
231 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
232 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
233 uint64_t rx_offloads = dev_conf->rxmode.offloads;
234 uint32_t intr_vector = 0;
235 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
236 uint32_t vec = BNXT_MISC_VEC_ID;
240 /* disable uio/vfio intr/eventfd mapping */
241 rte_intr_disable(intr_handle);
243 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
244 bp->eth_dev->data->dev_conf.rxmode.offloads |=
245 DEV_RX_OFFLOAD_JUMBO_FRAME;
246 bp->flags |= BNXT_FLAG_JUMBO;
248 bp->eth_dev->data->dev_conf.rxmode.offloads &=
249 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
250 bp->flags &= ~BNXT_FLAG_JUMBO;
253 /* THOR does not support ring groups.
254 * But we will use the array to save RSS context IDs.
256 if (BNXT_CHIP_THOR(bp))
257 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
259 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
261 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
265 rc = bnxt_alloc_hwrm_rings(bp);
267 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
271 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
273 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
277 rc = bnxt_mq_rx_configure(bp);
279 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
283 /* VNIC configuration */
284 for (i = 0; i < bp->nr_vnics; i++) {
285 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
286 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
287 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
289 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
290 if (!vnic->fw_grp_ids) {
292 "Failed to alloc %d bytes for group ids\n",
297 memset(vnic->fw_grp_ids, -1, size);
299 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
300 i, vnic, vnic->fw_grp_ids);
302 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
304 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
309 /* Alloc RSS context only if RSS mode is enabled */
310 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
311 int j, nr_ctxs = bnxt_rss_ctxts(bp);
314 for (j = 0; j < nr_ctxs; j++) {
315 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
321 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
325 vnic->num_lb_ctxts = nr_ctxs;
329 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
330 * setting is not available at this time, it will not be
331 * configured correctly in the CFA.
333 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
334 vnic->vlan_strip = true;
336 vnic->vlan_strip = false;
338 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
340 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
345 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
348 "HWRM vnic %d filter failure rc: %x\n",
353 for (j = 0; j < bp->rx_nr_rings; j++) {
354 rxq = bp->eth_dev->data->rx_queues[j];
357 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
358 j, rxq->vnic, rxq->vnic->fw_grp_ids);
360 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
361 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
364 rc = bnxt_vnic_rss_configure(bp, vnic);
367 "HWRM vnic set RSS failure rc: %x\n", rc);
371 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
373 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
374 DEV_RX_OFFLOAD_TCP_LRO)
375 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
377 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
379 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
382 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
386 /* check and configure queue intr-vector mapping */
387 if ((rte_intr_cap_multiple(intr_handle) ||
388 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
389 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
390 intr_vector = bp->eth_dev->data->nb_rx_queues;
391 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
392 if (intr_vector > bp->rx_cp_nr_rings) {
393 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
397 if (rte_intr_efd_enable(intr_handle, intr_vector))
401 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
402 intr_handle->intr_vec =
403 rte_zmalloc("intr_vec",
404 bp->eth_dev->data->nb_rx_queues *
406 if (intr_handle->intr_vec == NULL) {
407 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
408 " intr_vec", bp->eth_dev->data->nb_rx_queues);
411 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
412 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
413 intr_handle->intr_vec, intr_handle->nb_efd,
414 intr_handle->max_intr);
417 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
419 intr_handle->intr_vec[queue_id] = vec;
420 if (vec < base + intr_handle->nb_efd - 1)
424 /* enable uio/vfio intr/eventfd mapping */
425 rte_intr_enable(intr_handle);
427 rc = bnxt_get_hwrm_link_config(bp, &new);
429 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
433 if (!bp->link_info.link_up) {
434 rc = bnxt_set_hwrm_link_config(bp, true);
437 "HWRM link config failure rc: %x\n", rc);
441 bnxt_print_link_info(bp->eth_dev);
446 bnxt_free_all_hwrm_resources(bp);
448 /* Some of the error status returned by FW may not be from errno.h */
455 static int bnxt_shutdown_nic(struct bnxt *bp)
457 bnxt_free_all_hwrm_resources(bp);
458 bnxt_free_all_filters(bp);
459 bnxt_free_all_vnics(bp);
463 static int bnxt_init_nic(struct bnxt *bp)
467 rc = bnxt_init_ring_grps(bp);
472 bnxt_init_filters(bp);
478 * Device configuration and status function
481 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
482 struct rte_eth_dev_info *dev_info)
484 struct bnxt *bp = eth_dev->data->dev_private;
485 uint16_t max_vnics, i, j, vpool, vrxq;
486 unsigned int max_rx_rings;
489 dev_info->max_mac_addrs = bp->max_l2_ctx;
490 dev_info->max_hash_mac_addrs = 0;
492 /* PF/VF specifics */
494 dev_info->max_vfs = bp->pdev->max_vfs;
495 max_rx_rings = RTE_MIN(bp->max_vnics, bp->max_stat_ctx);
496 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
497 dev_info->max_rx_queues = max_rx_rings;
498 dev_info->max_tx_queues = max_rx_rings;
499 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
500 dev_info->hash_key_size = 40;
501 max_vnics = bp->max_vnics;
503 /* Fast path specifics */
504 dev_info->min_rx_bufsize = 1;
505 dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
506 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
508 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
509 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
510 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
511 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
512 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
515 dev_info->default_rxconf = (struct rte_eth_rxconf) {
521 .rx_free_thresh = 32,
522 /* If no descriptors available, pkts are dropped by default */
526 dev_info->default_txconf = (struct rte_eth_txconf) {
532 .tx_free_thresh = 32,
535 eth_dev->data->dev_conf.intr_conf.lsc = 1;
537 eth_dev->data->dev_conf.intr_conf.rxq = 1;
538 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
539 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
540 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
541 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
546 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
547 * need further investigation.
551 vpool = 64; /* ETH_64_POOLS */
552 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
553 for (i = 0; i < 4; vpool >>= 1, i++) {
554 if (max_vnics > vpool) {
555 for (j = 0; j < 5; vrxq >>= 1, j++) {
556 if (dev_info->max_rx_queues > vrxq) {
562 /* Not enough resources to support VMDq */
566 /* Not enough resources to support VMDq */
570 dev_info->max_vmdq_pools = vpool;
571 dev_info->vmdq_queue_num = vrxq;
573 dev_info->vmdq_pool_base = 0;
574 dev_info->vmdq_queue_base = 0;
577 /* Configure the device based on the configuration provided */
578 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
580 struct bnxt *bp = eth_dev->data->dev_private;
581 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
584 bp->rx_queues = (void *)eth_dev->data->rx_queues;
585 bp->tx_queues = (void *)eth_dev->data->tx_queues;
586 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
587 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
589 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
590 rc = bnxt_hwrm_check_vf_rings(bp);
592 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
596 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
598 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
602 /* legacy driver needs to get updated values */
603 rc = bnxt_hwrm_func_qcaps(bp);
605 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
610 /* Inherit new configurations */
611 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
612 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
613 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
615 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
619 if (BNXT_HAS_RING_GRPS(bp) &&
620 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
623 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
624 bp->max_vnics < eth_dev->data->nb_rx_queues)
627 bp->rx_cp_nr_rings = bp->rx_nr_rings;
628 bp->tx_cp_nr_rings = bp->tx_nr_rings;
630 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
632 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
633 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
635 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
641 "Insufficient resources to support requested config\n");
643 "Num Queues Requested: Tx %d, Rx %d\n",
644 eth_dev->data->nb_tx_queues,
645 eth_dev->data->nb_rx_queues);
647 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
648 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
649 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
653 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
655 struct rte_eth_link *link = ð_dev->data->dev_link;
657 if (link->link_status)
658 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
659 eth_dev->data->port_id,
660 (uint32_t)link->link_speed,
661 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
662 ("full-duplex") : ("half-duplex\n"));
664 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
665 eth_dev->data->port_id);
669 * Determine whether the current configuration requires support for scattered
670 * receive; return 1 if scattered receive is required and 0 if not.
672 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
677 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
678 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
680 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
681 RTE_PKTMBUF_HEADROOM);
682 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
688 static eth_rx_burst_t
689 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
693 * Vector mode receive can be enabled only if scatter rx is not
694 * in use and rx offloads are limited to VLAN stripping and
697 if (!eth_dev->data->scattered_rx &&
698 !(eth_dev->data->dev_conf.rxmode.offloads &
699 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
700 DEV_RX_OFFLOAD_KEEP_CRC |
701 DEV_RX_OFFLOAD_JUMBO_FRAME |
702 DEV_RX_OFFLOAD_IPV4_CKSUM |
703 DEV_RX_OFFLOAD_UDP_CKSUM |
704 DEV_RX_OFFLOAD_TCP_CKSUM |
705 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
706 DEV_RX_OFFLOAD_VLAN_FILTER))) {
707 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
708 eth_dev->data->port_id);
709 return bnxt_recv_pkts_vec;
711 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
712 eth_dev->data->port_id);
714 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
715 eth_dev->data->port_id,
716 eth_dev->data->scattered_rx,
717 eth_dev->data->dev_conf.rxmode.offloads);
719 return bnxt_recv_pkts;
722 static eth_tx_burst_t
723 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
727 * Vector mode receive can be enabled only if scatter tx is not
728 * in use and tx offloads other than VLAN insertion are not
731 if (!eth_dev->data->scattered_rx &&
732 !(eth_dev->data->dev_conf.txmode.offloads &
733 ~DEV_TX_OFFLOAD_VLAN_INSERT)) {
734 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
735 eth_dev->data->port_id);
736 return bnxt_xmit_pkts_vec;
738 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
739 eth_dev->data->port_id);
741 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
742 eth_dev->data->port_id,
743 eth_dev->data->scattered_rx,
744 eth_dev->data->dev_conf.txmode.offloads);
746 return bnxt_xmit_pkts;
749 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
751 struct bnxt *bp = eth_dev->data->dev_private;
752 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
756 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
758 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
759 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
763 rc = bnxt_init_chip(bp);
767 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
769 bnxt_link_update_op(eth_dev, 1);
771 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
772 vlan_mask |= ETH_VLAN_FILTER_MASK;
773 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
774 vlan_mask |= ETH_VLAN_STRIP_MASK;
775 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
779 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
780 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
781 bp->flags |= BNXT_FLAG_INIT_DONE;
785 bnxt_shutdown_nic(bp);
786 bnxt_free_tx_mbufs(bp);
787 bnxt_free_rx_mbufs(bp);
791 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
793 struct bnxt *bp = eth_dev->data->dev_private;
796 if (!bp->link_info.link_up)
797 rc = bnxt_set_hwrm_link_config(bp, true);
799 eth_dev->data->dev_link.link_status = 1;
801 bnxt_print_link_info(eth_dev);
805 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
807 struct bnxt *bp = eth_dev->data->dev_private;
809 eth_dev->data->dev_link.link_status = 0;
810 bnxt_set_hwrm_link_config(bp, false);
811 bp->link_info.link_up = 0;
816 /* Unload the driver, release resources */
817 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
819 struct bnxt *bp = eth_dev->data->dev_private;
821 bp->flags &= ~BNXT_FLAG_INIT_DONE;
822 if (bp->eth_dev->data->dev_started) {
823 /* TBD: STOP HW queues DMA */
824 eth_dev->data->dev_link.link_status = 0;
826 bnxt_set_hwrm_link_config(bp, false);
827 bnxt_hwrm_port_clr_stats(bp);
828 bnxt_free_tx_mbufs(bp);
829 bnxt_free_rx_mbufs(bp);
830 bnxt_shutdown_nic(bp);
834 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
836 struct bnxt *bp = eth_dev->data->dev_private;
838 if (bp->dev_stopped == 0)
839 bnxt_dev_stop_op(eth_dev);
841 if (eth_dev->data->mac_addrs != NULL) {
842 rte_free(eth_dev->data->mac_addrs);
843 eth_dev->data->mac_addrs = NULL;
845 if (bp->grp_info != NULL) {
846 rte_free(bp->grp_info);
850 bnxt_dev_uninit(eth_dev);
853 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
856 struct bnxt *bp = eth_dev->data->dev_private;
857 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
858 struct bnxt_vnic_info *vnic;
859 struct bnxt_filter_info *filter, *temp_filter;
863 * Loop through all VNICs from the specified filter flow pools to
864 * remove the corresponding MAC addr filter
866 for (i = 0; i < bp->nr_vnics; i++) {
867 if (!(pool_mask & (1ULL << i)))
870 vnic = &bp->vnic_info[i];
871 filter = STAILQ_FIRST(&vnic->filter);
873 temp_filter = STAILQ_NEXT(filter, next);
874 if (filter->mac_index == index) {
875 STAILQ_REMOVE(&vnic->filter, filter,
876 bnxt_filter_info, next);
877 bnxt_hwrm_clear_l2_filter(bp, filter);
878 filter->mac_index = INVALID_MAC_INDEX;
879 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
880 STAILQ_INSERT_TAIL(&bp->free_filter_list,
883 filter = temp_filter;
888 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
889 struct rte_ether_addr *mac_addr,
890 uint32_t index, uint32_t pool)
892 struct bnxt *bp = eth_dev->data->dev_private;
893 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
894 struct bnxt_filter_info *filter;
896 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
897 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
902 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
905 /* Attach requested MAC address to the new l2_filter */
906 STAILQ_FOREACH(filter, &vnic->filter, next) {
907 if (filter->mac_index == index) {
909 "MAC addr already existed for pool %d\n", pool);
913 filter = bnxt_alloc_filter(bp);
915 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
918 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
919 filter->mac_index = index;
920 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
921 return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
924 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
927 struct bnxt *bp = eth_dev->data->dev_private;
928 struct rte_eth_link new;
929 unsigned int cnt = BNXT_LINK_WAIT_CNT;
931 memset(&new, 0, sizeof(new));
933 /* Retrieve link info from hardware */
934 rc = bnxt_get_hwrm_link_config(bp, &new);
936 new.link_speed = ETH_LINK_SPEED_100M;
937 new.link_duplex = ETH_LINK_FULL_DUPLEX;
939 "Failed to retrieve link rc = 0x%x!\n", rc);
942 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
944 if (!wait_to_complete)
946 } while (!new.link_status && cnt--);
949 /* Timed out or success */
950 if (new.link_status != eth_dev->data->dev_link.link_status ||
951 new.link_speed != eth_dev->data->dev_link.link_speed) {
952 memcpy(ð_dev->data->dev_link, &new,
953 sizeof(struct rte_eth_link));
955 _rte_eth_dev_callback_process(eth_dev,
956 RTE_ETH_EVENT_INTR_LSC,
959 bnxt_print_link_info(eth_dev);
965 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
967 struct bnxt *bp = eth_dev->data->dev_private;
968 struct bnxt_vnic_info *vnic;
970 if (bp->vnic_info == NULL)
973 vnic = &bp->vnic_info[0];
975 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
976 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
979 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
981 struct bnxt *bp = eth_dev->data->dev_private;
982 struct bnxt_vnic_info *vnic;
984 if (bp->vnic_info == NULL)
987 vnic = &bp->vnic_info[0];
989 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
990 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
993 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
995 struct bnxt *bp = eth_dev->data->dev_private;
996 struct bnxt_vnic_info *vnic;
998 if (bp->vnic_info == NULL)
1001 vnic = &bp->vnic_info[0];
1003 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1004 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1007 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1009 struct bnxt *bp = eth_dev->data->dev_private;
1010 struct bnxt_vnic_info *vnic;
1012 if (bp->vnic_info == NULL)
1015 vnic = &bp->vnic_info[0];
1017 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1018 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1021 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1022 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1024 if (qid >= bp->rx_nr_rings)
1027 return bp->eth_dev->data->rx_queues[qid];
1030 /* Return rxq corresponding to a given rss table ring/group ID. */
1031 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1033 struct bnxt_rx_queue *rxq;
1036 if (!BNXT_HAS_RING_GRPS(bp)) {
1037 for (i = 0; i < bp->rx_nr_rings; i++) {
1038 rxq = bp->eth_dev->data->rx_queues[i];
1039 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1043 for (i = 0; i < bp->rx_nr_rings; i++) {
1044 if (bp->grp_info[i].fw_grp_id == fwr)
1049 return INVALID_HW_RING_ID;
1052 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1053 struct rte_eth_rss_reta_entry64 *reta_conf,
1056 struct bnxt *bp = eth_dev->data->dev_private;
1057 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1058 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1059 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1063 if (!vnic->rss_table)
1066 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1069 if (reta_size != tbl_size) {
1070 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1071 "(%d) must equal the size supported by the hardware "
1072 "(%d)\n", reta_size, tbl_size);
1076 for (i = 0; i < reta_size; i++) {
1077 struct bnxt_rx_queue *rxq;
1079 idx = i / RTE_RETA_GROUP_SIZE;
1080 sft = i % RTE_RETA_GROUP_SIZE;
1082 if (!(reta_conf[idx].mask & (1ULL << sft)))
1085 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1087 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1091 if (BNXT_CHIP_THOR(bp)) {
1092 vnic->rss_table[i * 2] =
1093 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1094 vnic->rss_table[i * 2 + 1] =
1095 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1097 vnic->rss_table[i] =
1098 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1101 vnic->rss_table[i] =
1102 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1105 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1109 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1110 struct rte_eth_rss_reta_entry64 *reta_conf,
1113 struct bnxt *bp = eth_dev->data->dev_private;
1114 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1115 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1116 uint16_t idx, sft, i;
1118 /* Retrieve from the default VNIC */
1121 if (!vnic->rss_table)
1124 if (reta_size != tbl_size) {
1125 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1126 "(%d) must equal the size supported by the hardware "
1127 "(%d)\n", reta_size, tbl_size);
1131 for (idx = 0, i = 0; i < reta_size; i++) {
1132 idx = i / RTE_RETA_GROUP_SIZE;
1133 sft = i % RTE_RETA_GROUP_SIZE;
1135 if (reta_conf[idx].mask & (1ULL << sft)) {
1138 if (BNXT_CHIP_THOR(bp))
1139 qid = bnxt_rss_to_qid(bp,
1140 vnic->rss_table[i * 2]);
1142 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1144 if (qid == INVALID_HW_RING_ID) {
1145 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1148 reta_conf[idx].reta[sft] = qid;
1155 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1156 struct rte_eth_rss_conf *rss_conf)
1158 struct bnxt *bp = eth_dev->data->dev_private;
1159 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1160 struct bnxt_vnic_info *vnic;
1161 uint16_t hash_type = 0;
1165 * If RSS enablement were different than dev_configure,
1166 * then return -EINVAL
1168 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1169 if (!rss_conf->rss_hf)
1170 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1172 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1176 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1177 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1179 if (rss_conf->rss_hf & ETH_RSS_IPV4)
1180 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1181 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1182 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1183 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1184 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1185 if (rss_conf->rss_hf & ETH_RSS_IPV6)
1186 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1187 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1188 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1189 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1190 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1192 /* Update the RSS VNIC(s) */
1193 for (i = 0; i < bp->nr_vnics; i++) {
1194 vnic = &bp->vnic_info[i];
1195 vnic->hash_type = hash_type;
1198 * Use the supplied key if the key length is
1199 * acceptable and the rss_key is not NULL
1201 if (rss_conf->rss_key &&
1202 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1203 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1204 rss_conf->rss_key_len);
1206 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1211 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1212 struct rte_eth_rss_conf *rss_conf)
1214 struct bnxt *bp = eth_dev->data->dev_private;
1215 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1217 uint32_t hash_types;
1219 /* RSS configuration is the same for all VNICs */
1220 if (vnic && vnic->rss_hash_key) {
1221 if (rss_conf->rss_key) {
1222 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1223 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1224 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1227 hash_types = vnic->hash_type;
1228 rss_conf->rss_hf = 0;
1229 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1230 rss_conf->rss_hf |= ETH_RSS_IPV4;
1231 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1233 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1234 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1236 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1238 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1239 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1241 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1243 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1244 rss_conf->rss_hf |= ETH_RSS_IPV6;
1245 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1247 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1248 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1250 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1252 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1253 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1255 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1259 "Unknwon RSS config from firmware (%08x), RSS disabled",
1264 rss_conf->rss_hf = 0;
1269 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1270 struct rte_eth_fc_conf *fc_conf)
1272 struct bnxt *bp = dev->data->dev_private;
1273 struct rte_eth_link link_info;
1276 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1280 memset(fc_conf, 0, sizeof(*fc_conf));
1281 if (bp->link_info.auto_pause)
1282 fc_conf->autoneg = 1;
1283 switch (bp->link_info.pause) {
1285 fc_conf->mode = RTE_FC_NONE;
1287 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1288 fc_conf->mode = RTE_FC_TX_PAUSE;
1290 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1291 fc_conf->mode = RTE_FC_RX_PAUSE;
1293 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1294 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1295 fc_conf->mode = RTE_FC_FULL;
1301 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1302 struct rte_eth_fc_conf *fc_conf)
1304 struct bnxt *bp = dev->data->dev_private;
1306 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1307 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1311 switch (fc_conf->mode) {
1313 bp->link_info.auto_pause = 0;
1314 bp->link_info.force_pause = 0;
1316 case RTE_FC_RX_PAUSE:
1317 if (fc_conf->autoneg) {
1318 bp->link_info.auto_pause =
1319 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1320 bp->link_info.force_pause = 0;
1322 bp->link_info.auto_pause = 0;
1323 bp->link_info.force_pause =
1324 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1327 case RTE_FC_TX_PAUSE:
1328 if (fc_conf->autoneg) {
1329 bp->link_info.auto_pause =
1330 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1331 bp->link_info.force_pause = 0;
1333 bp->link_info.auto_pause = 0;
1334 bp->link_info.force_pause =
1335 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1339 if (fc_conf->autoneg) {
1340 bp->link_info.auto_pause =
1341 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1342 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1343 bp->link_info.force_pause = 0;
1345 bp->link_info.auto_pause = 0;
1346 bp->link_info.force_pause =
1347 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1348 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1352 return bnxt_set_hwrm_link_config(bp, true);
1355 /* Add UDP tunneling port */
1357 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1358 struct rte_eth_udp_tunnel *udp_tunnel)
1360 struct bnxt *bp = eth_dev->data->dev_private;
1361 uint16_t tunnel_type = 0;
1364 switch (udp_tunnel->prot_type) {
1365 case RTE_TUNNEL_TYPE_VXLAN:
1366 if (bp->vxlan_port_cnt) {
1367 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1368 udp_tunnel->udp_port);
1369 if (bp->vxlan_port != udp_tunnel->udp_port) {
1370 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1373 bp->vxlan_port_cnt++;
1377 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1378 bp->vxlan_port_cnt++;
1380 case RTE_TUNNEL_TYPE_GENEVE:
1381 if (bp->geneve_port_cnt) {
1382 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1383 udp_tunnel->udp_port);
1384 if (bp->geneve_port != udp_tunnel->udp_port) {
1385 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1388 bp->geneve_port_cnt++;
1392 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1393 bp->geneve_port_cnt++;
1396 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1399 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1405 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1406 struct rte_eth_udp_tunnel *udp_tunnel)
1408 struct bnxt *bp = eth_dev->data->dev_private;
1409 uint16_t tunnel_type = 0;
1413 switch (udp_tunnel->prot_type) {
1414 case RTE_TUNNEL_TYPE_VXLAN:
1415 if (!bp->vxlan_port_cnt) {
1416 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1419 if (bp->vxlan_port != udp_tunnel->udp_port) {
1420 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1421 udp_tunnel->udp_port, bp->vxlan_port);
1424 if (--bp->vxlan_port_cnt)
1428 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1429 port = bp->vxlan_fw_dst_port_id;
1431 case RTE_TUNNEL_TYPE_GENEVE:
1432 if (!bp->geneve_port_cnt) {
1433 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1436 if (bp->geneve_port != udp_tunnel->udp_port) {
1437 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1438 udp_tunnel->udp_port, bp->geneve_port);
1441 if (--bp->geneve_port_cnt)
1445 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1446 port = bp->geneve_fw_dst_port_id;
1449 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1453 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1456 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1459 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1460 bp->geneve_port = 0;
1465 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1467 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1468 struct bnxt_vnic_info *vnic;
1471 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1473 /* Cycle through all VNICs */
1474 for (i = 0; i < bp->nr_vnics; i++) {
1476 * For each VNIC and each associated filter(s)
1477 * if VLAN exists && VLAN matches vlan_id
1478 * remove the MAC+VLAN filter
1479 * add a new MAC only filter
1481 * VLAN filter doesn't exist, just skip and continue
1483 vnic = &bp->vnic_info[i];
1484 filter = STAILQ_FIRST(&vnic->filter);
1486 temp_filter = STAILQ_NEXT(filter, next);
1488 if (filter->enables & chk &&
1489 filter->l2_ovlan == vlan_id) {
1490 /* Must delete the filter */
1491 STAILQ_REMOVE(&vnic->filter, filter,
1492 bnxt_filter_info, next);
1493 bnxt_hwrm_clear_l2_filter(bp, filter);
1494 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1498 * Need to examine to see if the MAC
1499 * filter already existed or not before
1500 * allocating a new one
1503 new_filter = bnxt_alloc_filter(bp);
1506 "MAC/VLAN filter alloc failed\n");
1510 STAILQ_INSERT_TAIL(&vnic->filter,
1512 /* Inherit MAC from previous filter */
1513 new_filter->mac_index =
1515 memcpy(new_filter->l2_addr, filter->l2_addr,
1516 RTE_ETHER_ADDR_LEN);
1517 /* MAC only filter */
1518 rc = bnxt_hwrm_set_l2_filter(bp,
1524 "Del Vlan filter for %d\n",
1527 filter = temp_filter;
1534 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1536 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1537 struct bnxt_vnic_info *vnic;
1540 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1541 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1542 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1544 /* Cycle through all VNICs */
1545 for (i = 0; i < bp->nr_vnics; i++) {
1547 * For each VNIC and each associated filter(s)
1549 * if VLAN matches vlan_id
1550 * VLAN filter already exists, just skip and continue
1552 * add a new MAC+VLAN filter
1554 * Remove the old MAC only filter
1555 * Add a new MAC+VLAN filter
1557 vnic = &bp->vnic_info[i];
1558 filter = STAILQ_FIRST(&vnic->filter);
1560 temp_filter = STAILQ_NEXT(filter, next);
1562 if (filter->enables & chk) {
1563 if (filter->l2_ivlan == vlan_id)
1566 /* Must delete the MAC filter */
1567 STAILQ_REMOVE(&vnic->filter, filter,
1568 bnxt_filter_info, next);
1569 bnxt_hwrm_clear_l2_filter(bp, filter);
1570 filter->l2_ovlan = 0;
1571 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1574 new_filter = bnxt_alloc_filter(bp);
1577 "MAC/VLAN filter alloc failed\n");
1581 STAILQ_INSERT_TAIL(&vnic->filter, new_filter, next);
1582 /* Inherit MAC from the previous filter */
1583 new_filter->mac_index = filter->mac_index;
1584 memcpy(new_filter->l2_addr, filter->l2_addr,
1585 RTE_ETHER_ADDR_LEN);
1586 /* MAC + VLAN ID filter */
1587 new_filter->l2_ivlan = vlan_id;
1588 new_filter->l2_ivlan_mask = 0xF000;
1589 new_filter->enables |= en;
1590 rc = bnxt_hwrm_set_l2_filter(bp,
1596 "Added Vlan filter for %d\n", vlan_id);
1598 filter = temp_filter;
1605 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1606 uint16_t vlan_id, int on)
1608 struct bnxt *bp = eth_dev->data->dev_private;
1610 /* These operations apply to ALL existing MAC/VLAN filters */
1612 return bnxt_add_vlan_filter(bp, vlan_id);
1614 return bnxt_del_vlan_filter(bp, vlan_id);
1618 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1620 struct bnxt *bp = dev->data->dev_private;
1621 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1624 if (mask & ETH_VLAN_FILTER_MASK) {
1625 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1626 /* Remove any VLAN filters programmed */
1627 for (i = 0; i < 4095; i++)
1628 bnxt_del_vlan_filter(bp, i);
1630 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1631 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1634 if (mask & ETH_VLAN_STRIP_MASK) {
1635 /* Enable or disable VLAN stripping */
1636 for (i = 0; i < bp->nr_vnics; i++) {
1637 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1638 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1639 vnic->vlan_strip = true;
1641 vnic->vlan_strip = false;
1642 bnxt_hwrm_vnic_cfg(bp, vnic);
1644 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1645 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1648 if (mask & ETH_VLAN_EXTEND_MASK)
1649 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1655 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1656 struct rte_ether_addr *addr)
1658 struct bnxt *bp = dev->data->dev_private;
1659 /* Default Filter is tied to VNIC 0 */
1660 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1661 struct bnxt_filter_info *filter;
1664 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1667 memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1669 STAILQ_FOREACH(filter, &vnic->filter, next) {
1670 /* Default Filter is at Index 0 */
1671 if (filter->mac_index != 0)
1673 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1676 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1677 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1678 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1680 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1681 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1682 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1685 filter->mac_index = 0;
1686 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1693 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1694 struct rte_ether_addr *mc_addr_set,
1695 uint32_t nb_mc_addr)
1697 struct bnxt *bp = eth_dev->data->dev_private;
1698 char *mc_addr_list = (char *)mc_addr_set;
1699 struct bnxt_vnic_info *vnic;
1700 uint32_t off = 0, i = 0;
1702 vnic = &bp->vnic_info[0];
1704 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1705 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1709 /* TODO Check for Duplicate mcast addresses */
1710 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1711 for (i = 0; i < nb_mc_addr; i++) {
1712 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1713 RTE_ETHER_ADDR_LEN);
1714 off += RTE_ETHER_ADDR_LEN;
1717 vnic->mc_addr_cnt = i;
1720 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1724 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1726 struct bnxt *bp = dev->data->dev_private;
1727 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1728 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1729 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1732 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1733 fw_major, fw_minor, fw_updt);
1735 ret += 1; /* add the size of '\0' */
1736 if (fw_size < (uint32_t)ret)
1743 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1744 struct rte_eth_rxq_info *qinfo)
1746 struct bnxt_rx_queue *rxq;
1748 rxq = dev->data->rx_queues[queue_id];
1750 qinfo->mp = rxq->mb_pool;
1751 qinfo->scattered_rx = dev->data->scattered_rx;
1752 qinfo->nb_desc = rxq->nb_rx_desc;
1754 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1755 qinfo->conf.rx_drop_en = 0;
1756 qinfo->conf.rx_deferred_start = 0;
1760 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1761 struct rte_eth_txq_info *qinfo)
1763 struct bnxt_tx_queue *txq;
1765 txq = dev->data->tx_queues[queue_id];
1767 qinfo->nb_desc = txq->nb_tx_desc;
1769 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1770 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1771 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1773 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1774 qinfo->conf.tx_rs_thresh = 0;
1775 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1778 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1780 struct bnxt *bp = eth_dev->data->dev_private;
1781 struct rte_eth_dev_info dev_info;
1782 uint32_t new_pkt_size;
1786 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1787 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1789 bnxt_dev_info_get_op(eth_dev, &dev_info);
1791 if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1792 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1793 RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1799 * If vector-mode tx/rx is active, disallow any MTU change that would
1800 * require scattered receive support.
1802 if (eth_dev->data->dev_started &&
1803 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1804 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1806 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1808 "MTU change would require scattered rx support. ");
1809 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
1814 if (new_mtu > RTE_ETHER_MTU) {
1815 bp->flags |= BNXT_FLAG_JUMBO;
1816 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1817 DEV_RX_OFFLOAD_JUMBO_FRAME;
1819 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1820 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1821 bp->flags &= ~BNXT_FLAG_JUMBO;
1824 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
1826 eth_dev->data->mtu = new_mtu;
1827 PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1829 for (i = 0; i < bp->nr_vnics; i++) {
1830 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1833 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1834 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1835 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1839 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1840 size -= RTE_PKTMBUF_HEADROOM;
1842 if (size < new_mtu) {
1843 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1853 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1855 struct bnxt *bp = dev->data->dev_private;
1856 uint16_t vlan = bp->vlan;
1859 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1861 "PVID cannot be modified for this function\n");
1864 bp->vlan = on ? pvid : 0;
1866 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1873 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1875 struct bnxt *bp = dev->data->dev_private;
1877 return bnxt_hwrm_port_led_cfg(bp, true);
1881 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1883 struct bnxt *bp = dev->data->dev_private;
1885 return bnxt_hwrm_port_led_cfg(bp, false);
1889 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1891 uint32_t desc = 0, raw_cons = 0, cons;
1892 struct bnxt_cp_ring_info *cpr;
1893 struct bnxt_rx_queue *rxq;
1894 struct rx_pkt_cmpl *rxcmp;
1899 rxq = dev->data->rx_queues[rx_queue_id];
1903 while (raw_cons < rxq->nb_rx_desc) {
1904 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1905 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1907 if (!CMPL_VALID(rxcmp, valid))
1909 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1910 cmp_type = CMP_TYPE(rxcmp);
1911 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1912 cmp = (rte_le_to_cpu_32(
1913 ((struct rx_tpa_end_cmpl *)
1914 (rxcmp))->agg_bufs_v1) &
1915 RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1916 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1918 } else if (cmp_type == 0x11) {
1920 cmp = (rxcmp->agg_bufs_v1 &
1921 RX_PKT_CMPL_AGG_BUFS_MASK) >>
1922 RX_PKT_CMPL_AGG_BUFS_SFT;
1927 raw_cons += cmp ? cmp : 2;
1934 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1936 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1937 struct bnxt_rx_ring_info *rxr;
1938 struct bnxt_cp_ring_info *cpr;
1939 struct bnxt_sw_rx_bd *rx_buf;
1940 struct rx_pkt_cmpl *rxcmp;
1941 uint32_t cons, cp_cons;
1949 if (offset >= rxq->nb_rx_desc)
1952 cons = RING_CMP(cpr->cp_ring_struct, offset);
1953 cp_cons = cpr->cp_raw_cons;
1954 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1956 if (cons > cp_cons) {
1957 if (CMPL_VALID(rxcmp, cpr->valid))
1958 return RTE_ETH_RX_DESC_DONE;
1960 if (CMPL_VALID(rxcmp, !cpr->valid))
1961 return RTE_ETH_RX_DESC_DONE;
1963 rx_buf = &rxr->rx_buf_ring[cons];
1964 if (rx_buf->mbuf == NULL)
1965 return RTE_ETH_RX_DESC_UNAVAIL;
1968 return RTE_ETH_RX_DESC_AVAIL;
1972 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1974 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1975 struct bnxt_tx_ring_info *txr;
1976 struct bnxt_cp_ring_info *cpr;
1977 struct bnxt_sw_tx_bd *tx_buf;
1978 struct tx_pkt_cmpl *txcmp;
1979 uint32_t cons, cp_cons;
1987 if (offset >= txq->nb_tx_desc)
1990 cons = RING_CMP(cpr->cp_ring_struct, offset);
1991 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1992 cp_cons = cpr->cp_raw_cons;
1994 if (cons > cp_cons) {
1995 if (CMPL_VALID(txcmp, cpr->valid))
1996 return RTE_ETH_TX_DESC_UNAVAIL;
1998 if (CMPL_VALID(txcmp, !cpr->valid))
1999 return RTE_ETH_TX_DESC_UNAVAIL;
2001 tx_buf = &txr->tx_buf_ring[cons];
2002 if (tx_buf->mbuf == NULL)
2003 return RTE_ETH_TX_DESC_DONE;
2005 return RTE_ETH_TX_DESC_FULL;
2008 static struct bnxt_filter_info *
2009 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2010 struct rte_eth_ethertype_filter *efilter,
2011 struct bnxt_vnic_info *vnic0,
2012 struct bnxt_vnic_info *vnic,
2015 struct bnxt_filter_info *mfilter = NULL;
2019 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2020 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2021 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2022 " ethertype filter.", efilter->ether_type);
2026 if (efilter->queue >= bp->rx_nr_rings) {
2027 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2032 vnic0 = &bp->vnic_info[0];
2033 vnic = &bp->vnic_info[efilter->queue];
2035 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2040 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2041 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2042 if ((!memcmp(efilter->mac_addr.addr_bytes,
2043 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2045 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2046 mfilter->ethertype == efilter->ether_type)) {
2052 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2053 if ((!memcmp(efilter->mac_addr.addr_bytes,
2054 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2055 mfilter->ethertype == efilter->ether_type &&
2057 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2071 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2072 enum rte_filter_op filter_op,
2075 struct bnxt *bp = dev->data->dev_private;
2076 struct rte_eth_ethertype_filter *efilter =
2077 (struct rte_eth_ethertype_filter *)arg;
2078 struct bnxt_filter_info *bfilter, *filter1;
2079 struct bnxt_vnic_info *vnic, *vnic0;
2082 if (filter_op == RTE_ETH_FILTER_NOP)
2086 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2091 vnic0 = &bp->vnic_info[0];
2092 vnic = &bp->vnic_info[efilter->queue];
2094 switch (filter_op) {
2095 case RTE_ETH_FILTER_ADD:
2096 bnxt_match_and_validate_ether_filter(bp, efilter,
2101 bfilter = bnxt_get_unused_filter(bp);
2102 if (bfilter == NULL) {
2104 "Not enough resources for a new filter.\n");
2107 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2108 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2109 RTE_ETHER_ADDR_LEN);
2110 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2111 RTE_ETHER_ADDR_LEN);
2112 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2113 bfilter->ethertype = efilter->ether_type;
2114 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2116 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2117 if (filter1 == NULL) {
2122 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2123 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2125 bfilter->dst_id = vnic->fw_vnic_id;
2127 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2129 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2132 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2135 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2137 case RTE_ETH_FILTER_DELETE:
2138 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2140 if (ret == -EEXIST) {
2141 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2143 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2145 bnxt_free_filter(bp, filter1);
2146 } else if (ret == 0) {
2147 PMD_DRV_LOG(ERR, "No matching filter found\n");
2151 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2157 bnxt_free_filter(bp, bfilter);
2163 parse_ntuple_filter(struct bnxt *bp,
2164 struct rte_eth_ntuple_filter *nfilter,
2165 struct bnxt_filter_info *bfilter)
2169 if (nfilter->queue >= bp->rx_nr_rings) {
2170 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2174 switch (nfilter->dst_port_mask) {
2176 bfilter->dst_port_mask = -1;
2177 bfilter->dst_port = nfilter->dst_port;
2178 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2179 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2182 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2186 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2187 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2189 switch (nfilter->proto_mask) {
2191 if (nfilter->proto == 17) /* IPPROTO_UDP */
2192 bfilter->ip_protocol = 17;
2193 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2194 bfilter->ip_protocol = 6;
2197 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2200 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2204 switch (nfilter->dst_ip_mask) {
2206 bfilter->dst_ipaddr_mask[0] = -1;
2207 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2208 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2209 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2212 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2216 switch (nfilter->src_ip_mask) {
2218 bfilter->src_ipaddr_mask[0] = -1;
2219 bfilter->src_ipaddr[0] = nfilter->src_ip;
2220 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2221 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2224 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2228 switch (nfilter->src_port_mask) {
2230 bfilter->src_port_mask = -1;
2231 bfilter->src_port = nfilter->src_port;
2232 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2233 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2236 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2241 //nfilter->priority = (uint8_t)filter->priority;
2243 bfilter->enables = en;
2247 static struct bnxt_filter_info*
2248 bnxt_match_ntuple_filter(struct bnxt *bp,
2249 struct bnxt_filter_info *bfilter,
2250 struct bnxt_vnic_info **mvnic)
2252 struct bnxt_filter_info *mfilter = NULL;
2255 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2256 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2257 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2258 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2259 bfilter->src_ipaddr_mask[0] ==
2260 mfilter->src_ipaddr_mask[0] &&
2261 bfilter->src_port == mfilter->src_port &&
2262 bfilter->src_port_mask == mfilter->src_port_mask &&
2263 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2264 bfilter->dst_ipaddr_mask[0] ==
2265 mfilter->dst_ipaddr_mask[0] &&
2266 bfilter->dst_port == mfilter->dst_port &&
2267 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2268 bfilter->flags == mfilter->flags &&
2269 bfilter->enables == mfilter->enables) {
2280 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2281 struct rte_eth_ntuple_filter *nfilter,
2282 enum rte_filter_op filter_op)
2284 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2285 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2288 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2289 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2293 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2294 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2298 bfilter = bnxt_get_unused_filter(bp);
2299 if (bfilter == NULL) {
2301 "Not enough resources for a new filter.\n");
2304 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2308 vnic = &bp->vnic_info[nfilter->queue];
2309 vnic0 = &bp->vnic_info[0];
2310 filter1 = STAILQ_FIRST(&vnic0->filter);
2311 if (filter1 == NULL) {
2316 bfilter->dst_id = vnic->fw_vnic_id;
2317 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2319 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2320 bfilter->ethertype = 0x800;
2321 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2323 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2325 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2326 bfilter->dst_id == mfilter->dst_id) {
2327 PMD_DRV_LOG(ERR, "filter exists.\n");
2330 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2331 bfilter->dst_id != mfilter->dst_id) {
2332 mfilter->dst_id = vnic->fw_vnic_id;
2333 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2334 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2335 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2336 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2337 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2340 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2341 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2346 if (filter_op == RTE_ETH_FILTER_ADD) {
2347 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2348 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2351 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2353 if (mfilter == NULL) {
2354 /* This should not happen. But for Coverity! */
2358 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2360 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2361 bnxt_free_filter(bp, mfilter);
2362 mfilter->fw_l2_filter_id = -1;
2363 bnxt_free_filter(bp, bfilter);
2364 bfilter->fw_l2_filter_id = -1;
2369 bfilter->fw_l2_filter_id = -1;
2370 bnxt_free_filter(bp, bfilter);
2375 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2376 enum rte_filter_op filter_op,
2379 struct bnxt *bp = dev->data->dev_private;
2382 if (filter_op == RTE_ETH_FILTER_NOP)
2386 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2391 switch (filter_op) {
2392 case RTE_ETH_FILTER_ADD:
2393 ret = bnxt_cfg_ntuple_filter(bp,
2394 (struct rte_eth_ntuple_filter *)arg,
2397 case RTE_ETH_FILTER_DELETE:
2398 ret = bnxt_cfg_ntuple_filter(bp,
2399 (struct rte_eth_ntuple_filter *)arg,
2403 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2411 bnxt_parse_fdir_filter(struct bnxt *bp,
2412 struct rte_eth_fdir_filter *fdir,
2413 struct bnxt_filter_info *filter)
2415 enum rte_fdir_mode fdir_mode =
2416 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2417 struct bnxt_vnic_info *vnic0, *vnic;
2418 struct bnxt_filter_info *filter1;
2422 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2425 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2426 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2428 switch (fdir->input.flow_type) {
2429 case RTE_ETH_FLOW_IPV4:
2430 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2432 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2433 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2434 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2435 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2436 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2437 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2438 filter->ip_addr_type =
2439 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2440 filter->src_ipaddr_mask[0] = 0xffffffff;
2441 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2442 filter->dst_ipaddr_mask[0] = 0xffffffff;
2443 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2444 filter->ethertype = 0x800;
2445 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2447 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2448 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2449 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2450 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2451 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2452 filter->dst_port_mask = 0xffff;
2453 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2454 filter->src_port_mask = 0xffff;
2455 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2456 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2457 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2458 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2459 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2460 filter->ip_protocol = 6;
2461 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2462 filter->ip_addr_type =
2463 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2464 filter->src_ipaddr_mask[0] = 0xffffffff;
2465 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2466 filter->dst_ipaddr_mask[0] = 0xffffffff;
2467 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2468 filter->ethertype = 0x800;
2469 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2471 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2472 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2473 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2474 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2475 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2476 filter->dst_port_mask = 0xffff;
2477 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2478 filter->src_port_mask = 0xffff;
2479 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2480 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2481 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2482 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2483 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2484 filter->ip_protocol = 17;
2485 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2486 filter->ip_addr_type =
2487 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2488 filter->src_ipaddr_mask[0] = 0xffffffff;
2489 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2490 filter->dst_ipaddr_mask[0] = 0xffffffff;
2491 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2492 filter->ethertype = 0x800;
2493 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2495 case RTE_ETH_FLOW_IPV6:
2496 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2498 filter->ip_addr_type =
2499 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2500 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2501 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2502 rte_memcpy(filter->src_ipaddr,
2503 fdir->input.flow.ipv6_flow.src_ip, 16);
2504 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2505 rte_memcpy(filter->dst_ipaddr,
2506 fdir->input.flow.ipv6_flow.dst_ip, 16);
2507 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2508 memset(filter->dst_ipaddr_mask, 0xff, 16);
2509 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2510 memset(filter->src_ipaddr_mask, 0xff, 16);
2511 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2512 filter->ethertype = 0x86dd;
2513 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2515 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2516 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2517 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2518 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2519 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2520 filter->dst_port_mask = 0xffff;
2521 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2522 filter->src_port_mask = 0xffff;
2523 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2524 filter->ip_addr_type =
2525 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2526 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2527 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2528 rte_memcpy(filter->src_ipaddr,
2529 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2530 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2531 rte_memcpy(filter->dst_ipaddr,
2532 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2533 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2534 memset(filter->dst_ipaddr_mask, 0xff, 16);
2535 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2536 memset(filter->src_ipaddr_mask, 0xff, 16);
2537 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2538 filter->ethertype = 0x86dd;
2539 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2541 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2542 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2543 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2544 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2545 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2546 filter->dst_port_mask = 0xffff;
2547 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2548 filter->src_port_mask = 0xffff;
2549 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2550 filter->ip_addr_type =
2551 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2552 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2553 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2554 rte_memcpy(filter->src_ipaddr,
2555 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2556 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2557 rte_memcpy(filter->dst_ipaddr,
2558 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2559 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2560 memset(filter->dst_ipaddr_mask, 0xff, 16);
2561 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2562 memset(filter->src_ipaddr_mask, 0xff, 16);
2563 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2564 filter->ethertype = 0x86dd;
2565 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2567 case RTE_ETH_FLOW_L2_PAYLOAD:
2568 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2569 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2571 case RTE_ETH_FLOW_VXLAN:
2572 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2574 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2575 filter->tunnel_type =
2576 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2577 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2579 case RTE_ETH_FLOW_NVGRE:
2580 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2582 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2583 filter->tunnel_type =
2584 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2585 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2587 case RTE_ETH_FLOW_UNKNOWN:
2588 case RTE_ETH_FLOW_RAW:
2589 case RTE_ETH_FLOW_FRAG_IPV4:
2590 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2591 case RTE_ETH_FLOW_FRAG_IPV6:
2592 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2593 case RTE_ETH_FLOW_IPV6_EX:
2594 case RTE_ETH_FLOW_IPV6_TCP_EX:
2595 case RTE_ETH_FLOW_IPV6_UDP_EX:
2596 case RTE_ETH_FLOW_GENEVE:
2602 vnic0 = &bp->vnic_info[0];
2603 vnic = &bp->vnic_info[fdir->action.rx_queue];
2605 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2610 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2611 rte_memcpy(filter->dst_macaddr,
2612 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2613 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2616 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2617 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2618 filter1 = STAILQ_FIRST(&vnic0->filter);
2619 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2621 filter->dst_id = vnic->fw_vnic_id;
2622 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2623 if (filter->dst_macaddr[i] == 0x00)
2624 filter1 = STAILQ_FIRST(&vnic0->filter);
2626 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2629 if (filter1 == NULL)
2632 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2633 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2635 filter->enables = en;
2640 static struct bnxt_filter_info *
2641 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2642 struct bnxt_vnic_info **mvnic)
2644 struct bnxt_filter_info *mf = NULL;
2647 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2648 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2650 STAILQ_FOREACH(mf, &vnic->filter, next) {
2651 if (mf->filter_type == nf->filter_type &&
2652 mf->flags == nf->flags &&
2653 mf->src_port == nf->src_port &&
2654 mf->src_port_mask == nf->src_port_mask &&
2655 mf->dst_port == nf->dst_port &&
2656 mf->dst_port_mask == nf->dst_port_mask &&
2657 mf->ip_protocol == nf->ip_protocol &&
2658 mf->ip_addr_type == nf->ip_addr_type &&
2659 mf->ethertype == nf->ethertype &&
2660 mf->vni == nf->vni &&
2661 mf->tunnel_type == nf->tunnel_type &&
2662 mf->l2_ovlan == nf->l2_ovlan &&
2663 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2664 mf->l2_ivlan == nf->l2_ivlan &&
2665 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2666 !memcmp(mf->l2_addr, nf->l2_addr,
2667 RTE_ETHER_ADDR_LEN) &&
2668 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2669 RTE_ETHER_ADDR_LEN) &&
2670 !memcmp(mf->src_macaddr, nf->src_macaddr,
2671 RTE_ETHER_ADDR_LEN) &&
2672 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2673 RTE_ETHER_ADDR_LEN) &&
2674 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2675 sizeof(nf->src_ipaddr)) &&
2676 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2677 sizeof(nf->src_ipaddr_mask)) &&
2678 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2679 sizeof(nf->dst_ipaddr)) &&
2680 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2681 sizeof(nf->dst_ipaddr_mask))) {
2692 bnxt_fdir_filter(struct rte_eth_dev *dev,
2693 enum rte_filter_op filter_op,
2696 struct bnxt *bp = dev->data->dev_private;
2697 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2698 struct bnxt_filter_info *filter, *match;
2699 struct bnxt_vnic_info *vnic, *mvnic;
2702 if (filter_op == RTE_ETH_FILTER_NOP)
2705 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2708 switch (filter_op) {
2709 case RTE_ETH_FILTER_ADD:
2710 case RTE_ETH_FILTER_DELETE:
2712 filter = bnxt_get_unused_filter(bp);
2713 if (filter == NULL) {
2715 "Not enough resources for a new flow.\n");
2719 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2722 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2724 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2725 vnic = &bp->vnic_info[0];
2727 vnic = &bp->vnic_info[fdir->action.rx_queue];
2729 match = bnxt_match_fdir(bp, filter, &mvnic);
2730 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2731 if (match->dst_id == vnic->fw_vnic_id) {
2732 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2736 match->dst_id = vnic->fw_vnic_id;
2737 ret = bnxt_hwrm_set_ntuple_filter(bp,
2740 STAILQ_REMOVE(&mvnic->filter, match,
2741 bnxt_filter_info, next);
2742 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2744 "Filter with matching pattern exist\n");
2746 "Updated it to new destination q\n");
2750 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2751 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2756 if (filter_op == RTE_ETH_FILTER_ADD) {
2757 ret = bnxt_hwrm_set_ntuple_filter(bp,
2762 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2764 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2765 STAILQ_REMOVE(&vnic->filter, match,
2766 bnxt_filter_info, next);
2767 bnxt_free_filter(bp, match);
2768 filter->fw_l2_filter_id = -1;
2769 bnxt_free_filter(bp, filter);
2772 case RTE_ETH_FILTER_FLUSH:
2773 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2774 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2776 STAILQ_FOREACH(filter, &vnic->filter, next) {
2777 if (filter->filter_type ==
2778 HWRM_CFA_NTUPLE_FILTER) {
2780 bnxt_hwrm_clear_ntuple_filter(bp,
2782 STAILQ_REMOVE(&vnic->filter, filter,
2783 bnxt_filter_info, next);
2788 case RTE_ETH_FILTER_UPDATE:
2789 case RTE_ETH_FILTER_STATS:
2790 case RTE_ETH_FILTER_INFO:
2791 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2794 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2801 filter->fw_l2_filter_id = -1;
2802 bnxt_free_filter(bp, filter);
2807 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2808 enum rte_filter_type filter_type,
2809 enum rte_filter_op filter_op, void *arg)
2813 switch (filter_type) {
2814 case RTE_ETH_FILTER_TUNNEL:
2816 "filter type: %d: To be implemented\n", filter_type);
2818 case RTE_ETH_FILTER_FDIR:
2819 ret = bnxt_fdir_filter(dev, filter_op, arg);
2821 case RTE_ETH_FILTER_NTUPLE:
2822 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2824 case RTE_ETH_FILTER_ETHERTYPE:
2825 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2827 case RTE_ETH_FILTER_GENERIC:
2828 if (filter_op != RTE_ETH_FILTER_GET)
2830 *(const void **)arg = &bnxt_flow_ops;
2834 "Filter type (%d) not supported", filter_type);
2841 static const uint32_t *
2842 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2844 static const uint32_t ptypes[] = {
2845 RTE_PTYPE_L2_ETHER_VLAN,
2846 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2847 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2851 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2852 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2853 RTE_PTYPE_INNER_L4_ICMP,
2854 RTE_PTYPE_INNER_L4_TCP,
2855 RTE_PTYPE_INNER_L4_UDP,
2859 if (!dev->rx_pkt_burst)
2865 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2868 uint32_t reg_base = *reg_arr & 0xfffff000;
2872 for (i = 0; i < count; i++) {
2873 if ((reg_arr[i] & 0xfffff000) != reg_base)
2876 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2877 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
2881 static int bnxt_map_ptp_regs(struct bnxt *bp)
2883 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2887 reg_arr = ptp->rx_regs;
2888 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2892 reg_arr = ptp->tx_regs;
2893 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2897 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2898 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2900 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2901 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2906 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2908 rte_write32(0, (uint8_t *)bp->bar0 +
2909 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
2910 rte_write32(0, (uint8_t *)bp->bar0 +
2911 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
2914 static uint64_t bnxt_cc_read(struct bnxt *bp)
2918 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2919 BNXT_GRCPF_REG_SYNC_TIME));
2920 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2921 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2925 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2927 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2930 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2931 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2932 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2935 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2936 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2937 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2938 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2939 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2940 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2945 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2947 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2948 struct bnxt_pf_info *pf = &bp->pf;
2955 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2956 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2957 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2960 port_id = pf->port_id;
2961 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2962 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
2964 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2965 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2966 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2967 /* bnxt_clr_rx_ts(bp); TBD */
2971 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2972 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2973 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2974 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2980 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2983 struct bnxt *bp = dev->data->dev_private;
2984 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2989 ns = rte_timespec_to_ns(ts);
2990 /* Set the timecounters to a new value. */
2997 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2999 uint64_t ns, systime_cycles;
3000 struct bnxt *bp = dev->data->dev_private;
3001 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3006 systime_cycles = bnxt_cc_read(bp);
3007 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3008 *ts = rte_ns_to_timespec(ns);
3013 bnxt_timesync_enable(struct rte_eth_dev *dev)
3015 struct bnxt *bp = dev->data->dev_private;
3016 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3023 ptp->tx_tstamp_en = 1;
3024 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3026 if (!bnxt_hwrm_ptp_cfg(bp))
3027 bnxt_map_ptp_regs(bp);
3029 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3030 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3031 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3033 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3034 ptp->tc.cc_shift = shift;
3035 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3037 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3038 ptp->rx_tstamp_tc.cc_shift = shift;
3039 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3041 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3042 ptp->tx_tstamp_tc.cc_shift = shift;
3043 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3049 bnxt_timesync_disable(struct rte_eth_dev *dev)
3051 struct bnxt *bp = dev->data->dev_private;
3052 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3058 ptp->tx_tstamp_en = 0;
3061 bnxt_hwrm_ptp_cfg(bp);
3063 bnxt_unmap_ptp_regs(bp);
3069 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3070 struct timespec *timestamp,
3071 uint32_t flags __rte_unused)
3073 struct bnxt *bp = dev->data->dev_private;
3074 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3075 uint64_t rx_tstamp_cycles = 0;
3081 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3082 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3083 *timestamp = rte_ns_to_timespec(ns);
3088 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3089 struct timespec *timestamp)
3091 struct bnxt *bp = dev->data->dev_private;
3092 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3093 uint64_t tx_tstamp_cycles = 0;
3099 bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3100 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3101 *timestamp = rte_ns_to_timespec(ns);
3107 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3109 struct bnxt *bp = dev->data->dev_private;
3110 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3115 ptp->tc.nsec += delta;
3121 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3123 struct bnxt *bp = dev->data->dev_private;
3125 uint32_t dir_entries;
3126 uint32_t entry_length;
3128 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3129 bp->pdev->addr.domain, bp->pdev->addr.bus,
3130 bp->pdev->addr.devid, bp->pdev->addr.function);
3132 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3136 return dir_entries * entry_length;
3140 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3141 struct rte_dev_eeprom_info *in_eeprom)
3143 struct bnxt *bp = dev->data->dev_private;
3147 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3148 "len = %d\n", bp->pdev->addr.domain,
3149 bp->pdev->addr.bus, bp->pdev->addr.devid,
3150 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3152 if (in_eeprom->offset == 0) /* special offset value to get directory */
3153 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3156 index = in_eeprom->offset >> 24;
3157 offset = in_eeprom->offset & 0xffffff;
3160 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3161 in_eeprom->length, in_eeprom->data);
3166 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3169 case BNX_DIR_TYPE_CHIMP_PATCH:
3170 case BNX_DIR_TYPE_BOOTCODE:
3171 case BNX_DIR_TYPE_BOOTCODE_2:
3172 case BNX_DIR_TYPE_APE_FW:
3173 case BNX_DIR_TYPE_APE_PATCH:
3174 case BNX_DIR_TYPE_KONG_FW:
3175 case BNX_DIR_TYPE_KONG_PATCH:
3176 case BNX_DIR_TYPE_BONO_FW:
3177 case BNX_DIR_TYPE_BONO_PATCH:
3185 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3188 case BNX_DIR_TYPE_AVS:
3189 case BNX_DIR_TYPE_EXP_ROM_MBA:
3190 case BNX_DIR_TYPE_PCIE:
3191 case BNX_DIR_TYPE_TSCF_UCODE:
3192 case BNX_DIR_TYPE_EXT_PHY:
3193 case BNX_DIR_TYPE_CCM:
3194 case BNX_DIR_TYPE_ISCSI_BOOT:
3195 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3196 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3204 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3206 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3207 bnxt_dir_type_is_other_exec_format(dir_type);
3211 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3212 struct rte_dev_eeprom_info *in_eeprom)
3214 struct bnxt *bp = dev->data->dev_private;
3215 uint8_t index, dir_op;
3216 uint16_t type, ext, ordinal, attr;
3218 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3219 "len = %d\n", bp->pdev->addr.domain,
3220 bp->pdev->addr.bus, bp->pdev->addr.devid,
3221 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3224 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3228 type = in_eeprom->magic >> 16;
3230 if (type == 0xffff) { /* special value for directory operations */
3231 index = in_eeprom->magic & 0xff;
3232 dir_op = in_eeprom->magic >> 8;
3236 case 0x0e: /* erase */
3237 if (in_eeprom->offset != ~in_eeprom->magic)
3239 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3245 /* Create or re-write an NVM item: */
3246 if (bnxt_dir_type_is_executable(type) == true)
3248 ext = in_eeprom->magic & 0xffff;
3249 ordinal = in_eeprom->offset >> 16;
3250 attr = in_eeprom->offset & 0xffff;
3252 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3253 in_eeprom->data, in_eeprom->length);
3261 static const struct eth_dev_ops bnxt_dev_ops = {
3262 .dev_infos_get = bnxt_dev_info_get_op,
3263 .dev_close = bnxt_dev_close_op,
3264 .dev_configure = bnxt_dev_configure_op,
3265 .dev_start = bnxt_dev_start_op,
3266 .dev_stop = bnxt_dev_stop_op,
3267 .dev_set_link_up = bnxt_dev_set_link_up_op,
3268 .dev_set_link_down = bnxt_dev_set_link_down_op,
3269 .stats_get = bnxt_stats_get_op,
3270 .stats_reset = bnxt_stats_reset_op,
3271 .rx_queue_setup = bnxt_rx_queue_setup_op,
3272 .rx_queue_release = bnxt_rx_queue_release_op,
3273 .tx_queue_setup = bnxt_tx_queue_setup_op,
3274 .tx_queue_release = bnxt_tx_queue_release_op,
3275 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3276 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3277 .reta_update = bnxt_reta_update_op,
3278 .reta_query = bnxt_reta_query_op,
3279 .rss_hash_update = bnxt_rss_hash_update_op,
3280 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3281 .link_update = bnxt_link_update_op,
3282 .promiscuous_enable = bnxt_promiscuous_enable_op,
3283 .promiscuous_disable = bnxt_promiscuous_disable_op,
3284 .allmulticast_enable = bnxt_allmulticast_enable_op,
3285 .allmulticast_disable = bnxt_allmulticast_disable_op,
3286 .mac_addr_add = bnxt_mac_addr_add_op,
3287 .mac_addr_remove = bnxt_mac_addr_remove_op,
3288 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3289 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3290 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3291 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3292 .vlan_filter_set = bnxt_vlan_filter_set_op,
3293 .vlan_offload_set = bnxt_vlan_offload_set_op,
3294 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3295 .mtu_set = bnxt_mtu_set_op,
3296 .mac_addr_set = bnxt_set_default_mac_addr_op,
3297 .xstats_get = bnxt_dev_xstats_get_op,
3298 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3299 .xstats_reset = bnxt_dev_xstats_reset_op,
3300 .fw_version_get = bnxt_fw_version_get,
3301 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3302 .rxq_info_get = bnxt_rxq_info_get_op,
3303 .txq_info_get = bnxt_txq_info_get_op,
3304 .dev_led_on = bnxt_dev_led_on_op,
3305 .dev_led_off = bnxt_dev_led_off_op,
3306 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3307 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3308 .rx_queue_count = bnxt_rx_queue_count_op,
3309 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3310 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3311 .rx_queue_start = bnxt_rx_queue_start,
3312 .rx_queue_stop = bnxt_rx_queue_stop,
3313 .tx_queue_start = bnxt_tx_queue_start,
3314 .tx_queue_stop = bnxt_tx_queue_stop,
3315 .filter_ctrl = bnxt_filter_ctrl_op,
3316 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3317 .get_eeprom_length = bnxt_get_eeprom_length_op,
3318 .get_eeprom = bnxt_get_eeprom_op,
3319 .set_eeprom = bnxt_set_eeprom_op,
3320 .timesync_enable = bnxt_timesync_enable,
3321 .timesync_disable = bnxt_timesync_disable,
3322 .timesync_read_time = bnxt_timesync_read_time,
3323 .timesync_write_time = bnxt_timesync_write_time,
3324 .timesync_adjust_time = bnxt_timesync_adjust_time,
3325 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3326 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3329 static bool bnxt_vf_pciid(uint16_t id)
3331 if (id == BROADCOM_DEV_ID_57304_VF ||
3332 id == BROADCOM_DEV_ID_57406_VF ||
3333 id == BROADCOM_DEV_ID_5731X_VF ||
3334 id == BROADCOM_DEV_ID_5741X_VF ||
3335 id == BROADCOM_DEV_ID_57414_VF ||
3336 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3337 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3338 id == BROADCOM_DEV_ID_58802_VF ||
3339 id == BROADCOM_DEV_ID_57500_VF)
3344 bool bnxt_stratus_device(struct bnxt *bp)
3346 uint16_t id = bp->pdev->id.device_id;
3348 if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3349 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3350 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3355 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3357 struct bnxt *bp = eth_dev->data->dev_private;
3358 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3361 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3362 if (!pci_dev->mem_resource[0].addr) {
3364 "Cannot find PCI device base address, aborting\n");
3366 goto init_err_disable;
3369 bp->eth_dev = eth_dev;
3372 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3374 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3376 goto init_err_release;
3379 if (!pci_dev->mem_resource[2].addr) {
3381 "Cannot find PCI device BAR 2 address, aborting\n");
3383 goto init_err_release;
3385 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3393 if (bp->doorbell_base)
3394 bp->doorbell_base = NULL;
3401 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3402 struct bnxt_ctx_pg_info *ctx_pg,
3407 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3408 const struct rte_memzone *mz = NULL;
3409 char mz_name[RTE_MEMZONE_NAMESIZE];
3410 rte_iova_t mz_phys_addr;
3411 uint64_t valid_bits = 0;
3418 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3420 rmem->page_size = BNXT_PAGE_SIZE;
3421 rmem->pg_arr = ctx_pg->ctx_pg_arr;
3422 rmem->dma_arr = ctx_pg->ctx_dma_arr;
3423 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3425 valid_bits = PTU_PTE_VALID;
3427 if (rmem->nr_pages > 1) {
3428 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_pg_tbl%s_%x",
3430 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3431 mz = rte_memzone_lookup(mz_name);
3433 mz = rte_memzone_reserve_aligned(mz_name,
3437 RTE_MEMZONE_SIZE_HINT_ONLY |
3438 RTE_MEMZONE_IOVA_CONTIG,
3444 memset(mz->addr, 0, mz->len);
3445 mz_phys_addr = mz->iova;
3446 if ((unsigned long)mz->addr == mz_phys_addr) {
3447 PMD_DRV_LOG(WARNING,
3448 "Memzone physical address same as virtual.\n");
3449 PMD_DRV_LOG(WARNING,
3450 "Using rte_mem_virt2iova()\n");
3451 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3452 if (mz_phys_addr == 0) {
3454 "unable to map addr to phys memory\n");
3458 rte_mem_lock_page(((char *)mz->addr));
3460 rmem->pg_tbl = mz->addr;
3461 rmem->pg_tbl_map = mz_phys_addr;
3462 rmem->pg_tbl_mz = mz;
3465 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x", suffix, idx);
3466 mz = rte_memzone_lookup(mz_name);
3468 mz = rte_memzone_reserve_aligned(mz_name,
3472 RTE_MEMZONE_SIZE_HINT_ONLY |
3473 RTE_MEMZONE_IOVA_CONTIG,
3479 memset(mz->addr, 0, mz->len);
3480 mz_phys_addr = mz->iova;
3481 if ((unsigned long)mz->addr == mz_phys_addr) {
3482 PMD_DRV_LOG(WARNING,
3483 "Memzone physical address same as virtual.\n");
3484 PMD_DRV_LOG(WARNING,
3485 "Using rte_mem_virt2iova()\n");
3486 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
3487 rte_mem_lock_page(((char *)mz->addr) + sz);
3488 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3489 if (mz_phys_addr == RTE_BAD_IOVA) {
3491 "unable to map addr to phys memory\n");
3496 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
3497 rte_mem_lock_page(((char *)mz->addr) + sz);
3498 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
3499 rmem->dma_arr[i] = mz_phys_addr + sz;
3501 if (rmem->nr_pages > 1) {
3502 if (i == rmem->nr_pages - 2 &&
3503 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3504 valid_bits |= PTU_PTE_NEXT_TO_LAST;
3505 else if (i == rmem->nr_pages - 1 &&
3506 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3507 valid_bits |= PTU_PTE_LAST;
3509 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
3515 if (rmem->vmem_size)
3516 rmem->vmem = (void **)mz->addr;
3517 rmem->dma_arr[0] = mz_phys_addr;
3521 static void bnxt_free_ctx_mem(struct bnxt *bp)
3525 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
3528 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
3529 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
3530 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
3531 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
3532 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
3533 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
3534 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
3535 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
3536 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
3537 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
3538 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
3540 for (i = 0; i < BNXT_MAX_Q; i++) {
3541 if (bp->ctx->tqm_mem[i])
3542 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
3549 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
3551 #define min_t(type, x, y) ({ \
3552 type __min1 = (x); \
3553 type __min2 = (y); \
3554 __min1 < __min2 ? __min1 : __min2; })
3556 #define max_t(type, x, y) ({ \
3557 type __max1 = (x); \
3558 type __max2 = (y); \
3559 __max1 > __max2 ? __max1 : __max2; })
3561 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
3563 int bnxt_alloc_ctx_mem(struct bnxt *bp)
3565 struct bnxt_ctx_pg_info *ctx_pg;
3566 struct bnxt_ctx_mem_info *ctx;
3567 uint32_t mem_size, ena, entries;
3570 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
3572 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
3576 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
3579 ctx_pg = &ctx->qp_mem;
3580 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
3581 mem_size = ctx->qp_entry_size * ctx_pg->entries;
3582 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
3586 ctx_pg = &ctx->srq_mem;
3587 ctx_pg->entries = ctx->srq_max_l2_entries;
3588 mem_size = ctx->srq_entry_size * ctx_pg->entries;
3589 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
3593 ctx_pg = &ctx->cq_mem;
3594 ctx_pg->entries = ctx->cq_max_l2_entries;
3595 mem_size = ctx->cq_entry_size * ctx_pg->entries;
3596 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
3600 ctx_pg = &ctx->vnic_mem;
3601 ctx_pg->entries = ctx->vnic_max_vnic_entries +
3602 ctx->vnic_max_ring_table_entries;
3603 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
3604 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
3608 ctx_pg = &ctx->stat_mem;
3609 ctx_pg->entries = ctx->stat_max_entries;
3610 mem_size = ctx->stat_entry_size * ctx_pg->entries;
3611 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
3615 entries = ctx->qp_max_l2_entries;
3616 entries = roundup(entries, ctx->tqm_entries_multiple);
3617 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
3618 ctx->tqm_max_entries_per_ring);
3619 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
3620 ctx_pg = ctx->tqm_mem[i];
3621 /* use min tqm entries for now. */
3622 ctx_pg->entries = entries;
3623 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
3624 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
3627 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
3630 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
3631 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
3634 "Failed to configure context mem: rc = %d\n", rc);
3636 ctx->flags |= BNXT_CTX_FLAG_INITED;
3641 #define ALLOW_FUNC(x) \
3643 typeof(x) arg = (x); \
3644 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3645 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3648 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3650 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3651 char mz_name[RTE_MEMZONE_NAMESIZE];
3652 const struct rte_memzone *mz = NULL;
3653 static int version_printed;
3654 uint32_t total_alloc_len;
3655 rte_iova_t mz_phys_addr;
3660 if (version_printed++ == 0)
3661 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3663 rte_eth_copy_pci_info(eth_dev, pci_dev);
3665 bp = eth_dev->data->dev_private;
3667 bp->dev_stopped = 1;
3669 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3672 if (bnxt_vf_pciid(pci_dev->id.device_id))
3673 bp->flags |= BNXT_FLAG_VF;
3675 if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
3676 pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
3677 pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
3678 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF)
3679 bp->flags |= BNXT_FLAG_THOR_CHIP;
3681 rc = bnxt_init_board(eth_dev);
3684 "Board initialization failed rc: %x\n", rc);
3688 eth_dev->dev_ops = &bnxt_dev_ops;
3689 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3690 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3691 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3694 if (pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3695 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3696 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3697 pci_dev->addr.bus, pci_dev->addr.devid,
3698 pci_dev->addr.function, "rx_port_stats");
3699 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3700 mz = rte_memzone_lookup(mz_name);
3701 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3702 sizeof(struct rx_port_stats) +
3703 sizeof(struct rx_port_stats_ext) +
3706 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3709 RTE_MEMZONE_SIZE_HINT_ONLY |
3710 RTE_MEMZONE_IOVA_CONTIG);
3714 memset(mz->addr, 0, mz->len);
3715 mz_phys_addr = mz->iova;
3716 if ((unsigned long)mz->addr == mz_phys_addr) {
3718 "Memzone physical address same as virtual using rte_mem_virt2iova()\n");
3719 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3720 if (mz_phys_addr == 0) {
3722 "unable to map address to physical memory\n");
3727 bp->rx_mem_zone = (const void *)mz;
3728 bp->hw_rx_port_stats = mz->addr;
3729 bp->hw_rx_port_stats_map = mz_phys_addr;
3731 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3732 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3733 pci_dev->addr.bus, pci_dev->addr.devid,
3734 pci_dev->addr.function, "tx_port_stats");
3735 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3736 mz = rte_memzone_lookup(mz_name);
3737 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3738 sizeof(struct tx_port_stats) +
3739 sizeof(struct tx_port_stats_ext) +
3742 mz = rte_memzone_reserve(mz_name,
3746 RTE_MEMZONE_SIZE_HINT_ONLY |
3747 RTE_MEMZONE_IOVA_CONTIG);
3751 memset(mz->addr, 0, mz->len);
3752 mz_phys_addr = mz->iova;
3753 if ((unsigned long)mz->addr == mz_phys_addr) {
3754 PMD_DRV_LOG(WARNING,
3755 "Memzone physical address same as virtual.\n");
3756 PMD_DRV_LOG(WARNING,
3757 "Using rte_mem_virt2iova()\n");
3758 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3759 if (mz_phys_addr == 0) {
3761 "unable to map address to physical memory\n");
3766 bp->tx_mem_zone = (const void *)mz;
3767 bp->hw_tx_port_stats = mz->addr;
3768 bp->hw_tx_port_stats_map = mz_phys_addr;
3770 bp->flags |= BNXT_FLAG_PORT_STATS;
3772 /* Display extended statistics if FW supports it */
3773 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
3774 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0)
3775 goto skip_ext_stats;
3777 bp->hw_rx_port_stats_ext = (void *)
3778 (bp->hw_rx_port_stats + sizeof(struct rx_port_stats));
3779 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
3780 sizeof(struct rx_port_stats);
3781 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
3784 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2) {
3785 bp->hw_tx_port_stats_ext = (void *)
3786 (bp->hw_tx_port_stats + sizeof(struct tx_port_stats));
3787 bp->hw_tx_port_stats_ext_map =
3788 bp->hw_tx_port_stats_map +
3789 sizeof(struct tx_port_stats);
3790 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
3795 rc = bnxt_alloc_hwrm_resources(bp);
3798 "hwrm resource allocation failure rc: %x\n", rc);
3801 rc = bnxt_hwrm_ver_get(bp);
3805 rc = bnxt_hwrm_func_reset(bp);
3807 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3812 rc = bnxt_hwrm_queue_qportcfg(bp);
3814 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3817 /* Get the MAX capabilities for this function */
3818 rc = bnxt_hwrm_func_qcaps(bp);
3820 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3823 if (bp->max_tx_rings == 0) {
3824 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3828 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3829 RTE_ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3830 if (eth_dev->data->mac_addrs == NULL) {
3832 "Failed to alloc %u bytes needed to store MAC addr tbl",
3833 RTE_ETHER_ADDR_LEN * bp->max_l2_ctx);
3838 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
3840 "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
3841 bp->dflt_mac_addr[0], bp->dflt_mac_addr[1],
3842 bp->dflt_mac_addr[2], bp->dflt_mac_addr[3],
3843 bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]);
3847 /* Copy the permanent MAC from the qcap response address now. */
3848 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3849 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
3851 /* THOR does not support ring groups.
3852 * But we will use the array to save RSS context IDs.
3854 if (BNXT_CHIP_THOR(bp)) {
3855 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
3856 } else if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3857 /* 1 ring is for default completion ring */
3858 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3863 bp->grp_info = rte_zmalloc("bnxt_grp_info",
3864 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3865 if (!bp->grp_info) {
3867 "Failed to alloc %zu bytes to store group info table\n",
3868 sizeof(*bp->grp_info) * bp->max_ring_grps);
3873 /* Forward all requests if firmware is new enough */
3874 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3875 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3876 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3877 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3879 PMD_DRV_LOG(WARNING,
3880 "Firmware too old for VF mailbox functionality\n");
3881 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3885 * The following are used for driver cleanup. If we disallow these,
3886 * VF drivers can't clean up cleanly.
3888 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3889 ALLOW_FUNC(HWRM_VNIC_FREE);
3890 ALLOW_FUNC(HWRM_RING_FREE);
3891 ALLOW_FUNC(HWRM_RING_GRP_FREE);
3892 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3893 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3894 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3895 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3896 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3897 rc = bnxt_hwrm_func_driver_register(bp);
3900 "Failed to register driver");
3906 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3907 pci_dev->mem_resource[0].phys_addr,
3908 pci_dev->mem_resource[0].addr);
3910 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
3912 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3916 if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
3917 mtu != eth_dev->data->mtu)
3918 eth_dev->data->mtu = mtu;
3921 //if (bp->pf.active_vfs) {
3922 // TODO: Deallocate VF resources?
3924 if (bp->pdev->max_vfs) {
3925 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3927 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3931 rc = bnxt_hwrm_allocate_pf_only(bp);
3934 "Failed to allocate PF resources\n");
3940 bnxt_hwrm_port_led_qcaps(bp);
3942 rc = bnxt_setup_int(bp);
3946 rc = bnxt_alloc_mem(bp);
3948 goto error_free_int;
3950 rc = bnxt_request_int(bp);
3952 goto error_free_int;
3954 bnxt_enable_int(bp);
3960 bnxt_disable_int(bp);
3961 bnxt_hwrm_func_buf_unrgtr(bp);
3965 bnxt_dev_uninit(eth_dev);
3971 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
3973 struct bnxt *bp = eth_dev->data->dev_private;
3976 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3979 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
3980 bnxt_disable_int(bp);
3983 if (bp->grp_info != NULL) {
3984 rte_free(bp->grp_info);
3985 bp->grp_info = NULL;
3987 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3988 bnxt_free_hwrm_resources(bp);
3990 if (bp->tx_mem_zone) {
3991 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3992 bp->tx_mem_zone = NULL;
3995 if (bp->rx_mem_zone) {
3996 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3997 bp->rx_mem_zone = NULL;
4000 if (bp->dev_stopped == 0)
4001 bnxt_dev_close_op(eth_dev);
4003 rte_free(bp->pf.vf_info);
4004 bnxt_free_ctx_mem(bp);
4005 eth_dev->dev_ops = NULL;
4006 eth_dev->rx_pkt_burst = NULL;
4007 eth_dev->tx_pkt_burst = NULL;
4012 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4013 struct rte_pci_device *pci_dev)
4015 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4019 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4021 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4022 return rte_eth_dev_pci_generic_remove(pci_dev,
4025 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4028 static struct rte_pci_driver bnxt_rte_pmd = {
4029 .id_table = bnxt_pci_id_map,
4030 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
4031 RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_IOVA_AS_VA,
4032 .probe = bnxt_pci_probe,
4033 .remove = bnxt_pci_remove,
4037 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4039 if (strcmp(dev->device->driver->name, drv->driver.name))
4045 bool is_bnxt_supported(struct rte_eth_dev *dev)
4047 return is_device_supported(dev, &bnxt_rte_pmd);
4050 RTE_INIT(bnxt_init_log)
4052 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4053 if (bnxt_logtype_driver >= 0)
4054 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4057 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4058 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4059 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");