1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2021 Broadcom
10 #include <ethdev_driver.h>
11 #include <ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
19 #include "bnxt_filter.h"
20 #include "bnxt_hwrm.h"
22 #include "bnxt_reps.h"
23 #include "bnxt_ring.h"
26 #include "bnxt_stats.h"
29 #include "bnxt_vnic.h"
30 #include "hsi_struct_def_dpdk.h"
31 #include "bnxt_nvm_defs.h"
32 #include "bnxt_tf_common.h"
33 #include "ulp_flow_db.h"
34 #include "rte_pmd_bnxt.h"
36 #define DRV_MODULE_NAME "bnxt"
37 static const char bnxt_version[] =
38 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
41 * The set of PCI devices this driver supports
43 static const struct rte_pci_id bnxt_pci_id_map[] = {
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
87 { .vendor_id = 0, /* sentinel */ },
90 #define BNXT_DEVARG_ACCUM_STATS "accum-stats"
91 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
92 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
93 #define BNXT_DEVARG_REPRESENTOR "representor"
94 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf"
95 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf"
96 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f"
97 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r"
98 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f"
99 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r"
100 #define BNXT_DEVARG_APP_ID "app-id"
102 static const char *const bnxt_dev_args[] = {
103 BNXT_DEVARG_REPRESENTOR,
104 BNXT_DEVARG_ACCUM_STATS,
105 BNXT_DEVARG_FLOW_XSTAT,
106 BNXT_DEVARG_MAX_NUM_KFLOWS,
107 BNXT_DEVARG_REP_BASED_PF,
108 BNXT_DEVARG_REP_IS_PF,
109 BNXT_DEVARG_REP_Q_R2F,
110 BNXT_DEVARG_REP_Q_F2R,
111 BNXT_DEVARG_REP_FC_R2F,
112 BNXT_DEVARG_REP_FC_F2R,
118 * accum-stats == false to disable flow counter accumulation
119 * accum-stats == true to enable flow counter accumulation
121 #define BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats) ((accum_stats) > 1)
124 * app-id = an non-negative 8-bit number
126 #define BNXT_DEVARG_APP_ID_INVALID(val) ((val) > 255)
129 * flow_xstat == false to disable the feature
130 * flow_xstat == true to enable the feature
132 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
135 * rep_is_pf == false to indicate VF representor
136 * rep_is_pf == true to indicate PF representor
138 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1)
141 * rep_based_pf == Physical index of the PF
143 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15)
145 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
147 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3)
150 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
152 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3)
155 * rep_fc_r2f == Flow control for the representor to endpoint direction
157 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1)
160 * rep_fc_f2r == Flow control for the endpoint to representor direction
162 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1)
164 int bnxt_cfa_code_dynfield_offset = -1;
167 * max_num_kflows must be >= 32
168 * and must be a power-of-2 supported value
169 * return: 1 -> invalid
172 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
174 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
179 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
180 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
181 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
182 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
183 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
184 static int bnxt_restore_vlan_filters(struct bnxt *bp);
185 static void bnxt_dev_recover(void *arg);
186 static void bnxt_free_error_recovery_info(struct bnxt *bp);
187 static void bnxt_free_rep_info(struct bnxt *bp);
189 int is_bnxt_in_error(struct bnxt *bp)
191 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
193 if (bp->flags & BNXT_FLAG_FW_RESET)
199 /***********************/
202 * High level utility functions
205 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
207 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
208 BNXT_RSS_TBL_SIZE_P5);
210 if (!BNXT_CHIP_P5(bp))
213 return RTE_ALIGN_MUL_CEIL(num_rss_rings,
214 BNXT_RSS_ENTRIES_PER_CTX_P5) /
215 BNXT_RSS_ENTRIES_PER_CTX_P5;
218 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
220 if (!BNXT_CHIP_P5(bp))
221 return HW_HASH_INDEX_SIZE;
223 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
226 static void bnxt_free_parent_info(struct bnxt *bp)
228 rte_free(bp->parent);
232 static void bnxt_free_pf_info(struct bnxt *bp)
238 static void bnxt_free_link_info(struct bnxt *bp)
240 rte_free(bp->link_info);
241 bp->link_info = NULL;
244 static void bnxt_free_leds_info(struct bnxt *bp)
253 static void bnxt_free_flow_stats_info(struct bnxt *bp)
255 rte_free(bp->flow_stat);
256 bp->flow_stat = NULL;
259 static void bnxt_free_cos_queues(struct bnxt *bp)
261 rte_free(bp->rx_cos_queue);
262 bp->rx_cos_queue = NULL;
263 rte_free(bp->tx_cos_queue);
264 bp->tx_cos_queue = NULL;
267 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
269 bnxt_free_filter_mem(bp);
270 bnxt_free_vnic_attributes(bp);
271 bnxt_free_vnic_mem(bp);
273 /* tx/rx rings are configured as part of *_queue_setup callbacks.
274 * If the number of rings change across fw update,
275 * we don't have much choice except to warn the user.
279 bnxt_free_tx_rings(bp);
280 bnxt_free_rx_rings(bp);
282 bnxt_free_async_cp_ring(bp);
283 bnxt_free_rxtx_nq_ring(bp);
285 rte_free(bp->grp_info);
289 static int bnxt_alloc_parent_info(struct bnxt *bp)
291 bp->parent = rte_zmalloc("bnxt_parent_info",
292 sizeof(struct bnxt_parent_info), 0);
293 if (bp->parent == NULL)
299 static int bnxt_alloc_pf_info(struct bnxt *bp)
301 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
308 static int bnxt_alloc_link_info(struct bnxt *bp)
311 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
312 if (bp->link_info == NULL)
318 static int bnxt_alloc_leds_info(struct bnxt *bp)
323 bp->leds = rte_zmalloc("bnxt_leds",
324 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
326 if (bp->leds == NULL)
332 static int bnxt_alloc_cos_queues(struct bnxt *bp)
335 rte_zmalloc("bnxt_rx_cosq",
336 BNXT_COS_QUEUE_COUNT *
337 sizeof(struct bnxt_cos_queue_info),
339 if (bp->rx_cos_queue == NULL)
343 rte_zmalloc("bnxt_tx_cosq",
344 BNXT_COS_QUEUE_COUNT *
345 sizeof(struct bnxt_cos_queue_info),
347 if (bp->tx_cos_queue == NULL)
353 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
355 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
356 sizeof(struct bnxt_flow_stat_info), 0);
357 if (bp->flow_stat == NULL)
363 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
367 rc = bnxt_alloc_ring_grps(bp);
371 rc = bnxt_alloc_async_ring_struct(bp);
375 rc = bnxt_alloc_vnic_mem(bp);
379 rc = bnxt_alloc_vnic_attributes(bp);
383 rc = bnxt_alloc_filter_mem(bp);
387 rc = bnxt_alloc_async_cp_ring(bp);
391 rc = bnxt_alloc_rxtx_nq_ring(bp);
395 if (BNXT_FLOW_XSTATS_EN(bp)) {
396 rc = bnxt_alloc_flow_stats_info(bp);
404 bnxt_free_mem(bp, reconfig);
408 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
410 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
411 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
412 uint64_t rx_offloads = dev_conf->rxmode.offloads;
413 struct bnxt_rx_queue *rxq;
417 rc = bnxt_vnic_grp_alloc(bp, vnic);
421 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
422 vnic_id, vnic, vnic->fw_grp_ids);
424 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
428 /* Alloc RSS context only if RSS mode is enabled */
429 if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS) {
430 int j, nr_ctxs = bnxt_rss_ctxts(bp);
432 /* RSS table size in Thor is 512.
433 * Cap max Rx rings to same value
435 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
436 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
437 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
442 for (j = 0; j < nr_ctxs; j++) {
443 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
449 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
453 vnic->num_lb_ctxts = nr_ctxs;
457 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
458 * setting is not available at this time, it will not be
459 * configured correctly in the CFA.
461 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
462 vnic->vlan_strip = true;
464 vnic->vlan_strip = false;
466 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
470 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
474 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
475 rxq = bp->eth_dev->data->rx_queues[j];
478 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
479 j, rxq->vnic, rxq->vnic->fw_grp_ids);
481 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
482 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
484 vnic->rx_queue_cnt++;
487 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
489 rc = bnxt_vnic_rss_configure(bp, vnic);
493 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
495 rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic,
496 (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) ?
503 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
508 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
512 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
513 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
518 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
519 " rx_fc_in_tbl.ctx_id = %d\n",
520 bp->flow_stat->rx_fc_in_tbl.va,
521 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
522 bp->flow_stat->rx_fc_in_tbl.ctx_id);
524 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
525 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
530 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
531 " rx_fc_out_tbl.ctx_id = %d\n",
532 bp->flow_stat->rx_fc_out_tbl.va,
533 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
534 bp->flow_stat->rx_fc_out_tbl.ctx_id);
536 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
537 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
542 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
543 " tx_fc_in_tbl.ctx_id = %d\n",
544 bp->flow_stat->tx_fc_in_tbl.va,
545 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
546 bp->flow_stat->tx_fc_in_tbl.ctx_id);
548 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
549 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
554 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
555 " tx_fc_out_tbl.ctx_id = %d\n",
556 bp->flow_stat->tx_fc_out_tbl.va,
557 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
558 bp->flow_stat->tx_fc_out_tbl.ctx_id);
560 memset(bp->flow_stat->rx_fc_out_tbl.va,
562 bp->flow_stat->rx_fc_out_tbl.size);
563 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
564 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
565 bp->flow_stat->rx_fc_out_tbl.ctx_id,
566 bp->flow_stat->max_fc,
571 memset(bp->flow_stat->tx_fc_out_tbl.va,
573 bp->flow_stat->tx_fc_out_tbl.size);
574 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
575 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
576 bp->flow_stat->tx_fc_out_tbl.ctx_id,
577 bp->flow_stat->max_fc,
583 static int bnxt_alloc_ctx_mem_buf(struct bnxt *bp, char *type, size_t size,
584 struct bnxt_ctx_mem_buf_info *ctx)
589 ctx->va = rte_zmalloc_socket(type, size, 0,
590 bp->eth_dev->device->numa_node);
593 rte_mem_lock_page(ctx->va);
595 ctx->dma = rte_mem_virt2iova(ctx->va);
596 if (ctx->dma == RTE_BAD_IOVA)
602 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
604 struct rte_pci_device *pdev = bp->pdev;
605 char type[RTE_MEMZONE_NAMESIZE];
609 max_fc = bp->flow_stat->max_fc;
611 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
612 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
613 /* 4 bytes for each counter-id */
614 rc = bnxt_alloc_ctx_mem_buf(bp, type,
616 &bp->flow_stat->rx_fc_in_tbl);
620 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
621 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
622 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
623 rc = bnxt_alloc_ctx_mem_buf(bp, type,
625 &bp->flow_stat->rx_fc_out_tbl);
629 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
630 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
631 /* 4 bytes for each counter-id */
632 rc = bnxt_alloc_ctx_mem_buf(bp, type,
634 &bp->flow_stat->tx_fc_in_tbl);
638 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
639 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
640 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
641 rc = bnxt_alloc_ctx_mem_buf(bp, type,
643 &bp->flow_stat->tx_fc_out_tbl);
647 rc = bnxt_register_fc_ctx_mem(bp);
652 static int bnxt_init_ctx_mem(struct bnxt *bp)
656 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
657 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
658 !BNXT_FLOW_XSTATS_EN(bp))
661 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
665 rc = bnxt_init_fc_ctx_mem(bp);
670 static int bnxt_update_phy_setting(struct bnxt *bp)
672 struct rte_eth_link new;
675 rc = bnxt_get_hwrm_link_config(bp, &new);
677 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
682 * On BCM957508-N2100 adapters, FW will not allow any user other
683 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
684 * always returns link up. Force phy update always in that case.
686 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
687 rc = bnxt_set_hwrm_link_config(bp, true);
689 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
697 static void bnxt_free_prev_ring_stats(struct bnxt *bp)
699 rte_free(bp->prev_rx_ring_stats);
700 rte_free(bp->prev_tx_ring_stats);
702 bp->prev_rx_ring_stats = NULL;
703 bp->prev_tx_ring_stats = NULL;
706 static int bnxt_alloc_prev_ring_stats(struct bnxt *bp)
708 bp->prev_rx_ring_stats = rte_zmalloc("bnxt_prev_rx_ring_stats",
709 sizeof(struct bnxt_ring_stats) *
712 if (bp->prev_rx_ring_stats == NULL)
715 bp->prev_tx_ring_stats = rte_zmalloc("bnxt_prev_tx_ring_stats",
716 sizeof(struct bnxt_ring_stats) *
719 if (bp->prev_tx_ring_stats == NULL)
725 bnxt_free_prev_ring_stats(bp);
729 static int bnxt_start_nic(struct bnxt *bp)
731 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
732 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
733 uint32_t intr_vector = 0;
734 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
735 uint32_t vec = BNXT_MISC_VEC_ID;
739 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU)
740 bp->flags |= BNXT_FLAG_JUMBO;
742 bp->flags &= ~BNXT_FLAG_JUMBO;
744 /* THOR does not support ring groups.
745 * But we will use the array to save RSS context IDs.
747 if (BNXT_CHIP_P5(bp))
748 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
750 rc = bnxt_alloc_hwrm_rings(bp);
752 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
756 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
758 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
762 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
765 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
766 if (bp->rx_cos_queue[i].id != 0xff) {
767 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
771 "Num pools more than FW profile\n");
775 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
781 rc = bnxt_mq_rx_configure(bp);
783 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
787 for (j = 0; j < bp->rx_nr_rings; j++) {
788 struct bnxt_rx_queue *rxq = bp->rx_queues[j];
790 if (!rxq->rx_deferred_start) {
791 bp->eth_dev->data->rx_queue_state[j] =
792 RTE_ETH_QUEUE_STATE_STARTED;
793 rxq->rx_started = true;
798 rc = bnxt_setup_one_vnic(bp, 0);
801 /* VNIC configuration */
802 if (BNXT_RFS_NEEDS_VNIC(bp)) {
803 for (i = 1; i < bp->nr_vnics; i++) {
804 rc = bnxt_setup_one_vnic(bp, i);
810 for (j = 0; j < bp->tx_nr_rings; j++) {
811 struct bnxt_tx_queue *txq = bp->tx_queues[j];
813 if (!txq->tx_deferred_start) {
814 bp->eth_dev->data->tx_queue_state[j] =
815 RTE_ETH_QUEUE_STATE_STARTED;
816 txq->tx_started = true;
820 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
823 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
827 /* check and configure queue intr-vector mapping */
828 if ((rte_intr_cap_multiple(intr_handle) ||
829 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
830 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
831 intr_vector = bp->eth_dev->data->nb_rx_queues;
832 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
833 if (intr_vector > bp->rx_cp_nr_rings) {
834 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
838 rc = rte_intr_efd_enable(intr_handle, intr_vector);
843 if (rte_intr_dp_is_en(intr_handle)) {
844 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
845 bp->eth_dev->data->nb_rx_queues)) {
846 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
847 " intr_vec", bp->eth_dev->data->nb_rx_queues);
851 PMD_DRV_LOG(DEBUG, "intr_handle->nb_efd = %d "
852 "intr_handle->max_intr = %d\n",
853 rte_intr_nb_efd_get(intr_handle),
854 rte_intr_max_intr_get(intr_handle));
855 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
857 rte_intr_vec_list_index_set(intr_handle,
858 queue_id, vec + BNXT_RX_VEC_START);
859 if (vec < base + rte_intr_nb_efd_get(intr_handle)
865 /* enable uio/vfio intr/eventfd mapping */
866 rc = rte_intr_enable(intr_handle);
867 #ifndef RTE_EXEC_ENV_FREEBSD
868 /* In FreeBSD OS, nic_uio driver does not support interrupts */
873 rc = bnxt_update_phy_setting(bp);
877 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
879 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
884 /* Some of the error status returned by FW may not be from errno.h */
891 static int bnxt_shutdown_nic(struct bnxt *bp)
893 bnxt_free_all_hwrm_resources(bp);
894 bnxt_free_all_filters(bp);
895 bnxt_free_all_vnics(bp);
900 * Device configuration and status function
903 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
905 uint32_t link_speed = 0;
906 uint32_t speed_capa = 0;
908 if (bp->link_info == NULL)
911 link_speed = bp->link_info->support_speeds;
913 /* If PAM4 is configured, use PAM4 supported speed */
914 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
915 link_speed = bp->link_info->support_pam4_speeds;
917 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
918 speed_capa |= RTE_ETH_LINK_SPEED_100M;
919 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
920 speed_capa |= RTE_ETH_LINK_SPEED_100M_HD;
921 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
922 speed_capa |= RTE_ETH_LINK_SPEED_1G;
923 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
924 speed_capa |= RTE_ETH_LINK_SPEED_2_5G;
925 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
926 speed_capa |= RTE_ETH_LINK_SPEED_10G;
927 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
928 speed_capa |= RTE_ETH_LINK_SPEED_20G;
929 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
930 speed_capa |= RTE_ETH_LINK_SPEED_25G;
931 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
932 speed_capa |= RTE_ETH_LINK_SPEED_40G;
933 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
934 speed_capa |= RTE_ETH_LINK_SPEED_50G;
935 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
936 speed_capa |= RTE_ETH_LINK_SPEED_100G;
937 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
938 speed_capa |= RTE_ETH_LINK_SPEED_50G;
939 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
940 speed_capa |= RTE_ETH_LINK_SPEED_100G;
941 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
942 speed_capa |= RTE_ETH_LINK_SPEED_200G;
944 if (bp->link_info->auto_mode ==
945 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
946 speed_capa |= RTE_ETH_LINK_SPEED_FIXED;
951 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
952 struct rte_eth_dev_info *dev_info)
954 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
955 struct bnxt *bp = eth_dev->data->dev_private;
956 uint16_t max_vnics, i, j, vpool, vrxq;
957 unsigned int max_rx_rings;
960 rc = is_bnxt_in_error(bp);
965 dev_info->max_mac_addrs = bp->max_l2_ctx;
966 dev_info->max_hash_mac_addrs = 0;
968 /* PF/VF specifics */
970 dev_info->max_vfs = pdev->max_vfs;
972 max_rx_rings = bnxt_max_rings(bp);
973 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
974 dev_info->max_rx_queues = max_rx_rings;
975 dev_info->max_tx_queues = max_rx_rings;
976 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
977 dev_info->hash_key_size = HW_HASH_KEY_SIZE;
978 max_vnics = bp->max_vnics;
981 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
982 dev_info->max_mtu = BNXT_MAX_MTU;
984 /* Fast path specifics */
985 dev_info->min_rx_bufsize = 1;
986 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
988 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
989 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
990 dev_info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_TIMESTAMP;
991 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_VLAN_RX_STRIP)
992 dev_info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
993 dev_info->tx_queue_offload_capa = RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;
994 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
995 dev_info->tx_queue_offload_capa;
996 if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT)
997 dev_info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_VLAN_INSERT;
998 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
1000 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
1001 dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
1002 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
1003 dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
1005 dev_info->default_rxconf = (struct rte_eth_rxconf) {
1011 .rx_free_thresh = 32,
1012 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
1015 dev_info->default_txconf = (struct rte_eth_txconf) {
1021 .tx_free_thresh = 32,
1024 eth_dev->data->dev_conf.intr_conf.lsc = 1;
1026 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1027 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
1028 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1029 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
1031 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
1032 dev_info->switch_info.name = eth_dev->device->name;
1033 dev_info->switch_info.domain_id = bp->switch_domain_id;
1034 dev_info->switch_info.port_id =
1035 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
1036 BNXT_SWITCH_PORT_ID_TRUSTED_VF;
1040 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
1041 * need further investigation.
1044 /* VMDq resources */
1045 vpool = 64; /* RTE_ETH_64_POOLS */
1046 vrxq = 128; /* RTE_ETH_VMDQ_DCB_NUM_QUEUES */
1047 for (i = 0; i < 4; vpool >>= 1, i++) {
1048 if (max_vnics > vpool) {
1049 for (j = 0; j < 5; vrxq >>= 1, j++) {
1050 if (dev_info->max_rx_queues > vrxq) {
1056 /* Not enough resources to support VMDq */
1060 /* Not enough resources to support VMDq */
1064 dev_info->max_vmdq_pools = vpool;
1065 dev_info->vmdq_queue_num = vrxq;
1067 dev_info->vmdq_pool_base = 0;
1068 dev_info->vmdq_queue_base = 0;
1073 /* Configure the device based on the configuration provided */
1074 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1076 struct bnxt *bp = eth_dev->data->dev_private;
1077 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1080 bp->rx_queues = (void *)eth_dev->data->rx_queues;
1081 bp->tx_queues = (void *)eth_dev->data->tx_queues;
1082 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1083 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1085 rc = is_bnxt_in_error(bp);
1089 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1090 rc = bnxt_hwrm_check_vf_rings(bp);
1092 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1096 /* If a resource has already been allocated - in this case
1097 * it is the async completion ring, free it. Reallocate it after
1098 * resource reservation. This will ensure the resource counts
1099 * are calculated correctly.
1102 pthread_mutex_lock(&bp->def_cp_lock);
1104 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1105 bnxt_disable_int(bp);
1106 bnxt_free_cp_ring(bp, bp->async_cp_ring);
1109 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1111 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1112 pthread_mutex_unlock(&bp->def_cp_lock);
1116 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1117 rc = bnxt_alloc_async_cp_ring(bp);
1119 pthread_mutex_unlock(&bp->def_cp_lock);
1122 bnxt_enable_int(bp);
1125 pthread_mutex_unlock(&bp->def_cp_lock);
1128 /* Inherit new configurations */
1129 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1130 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1131 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1132 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1133 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1135 goto resource_error;
1137 if (BNXT_HAS_RING_GRPS(bp) &&
1138 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1139 goto resource_error;
1141 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS) &&
1142 bp->max_vnics < eth_dev->data->nb_rx_queues)
1143 goto resource_error;
1145 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1146 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1148 if (eth_dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
1149 rx_offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
1150 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1152 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1158 "Insufficient resources to support requested config\n");
1160 "Num Queues Requested: Tx %d, Rx %d\n",
1161 eth_dev->data->nb_tx_queues,
1162 eth_dev->data->nb_rx_queues);
1164 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1165 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1166 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1170 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1172 struct rte_eth_link *link = ð_dev->data->dev_link;
1174 if (link->link_status)
1175 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1176 eth_dev->data->port_id,
1177 (uint32_t)link->link_speed,
1178 (link->link_duplex == RTE_ETH_LINK_FULL_DUPLEX) ?
1179 ("full-duplex") : ("half-duplex\n"));
1181 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1182 eth_dev->data->port_id);
1186 * Determine whether the current configuration requires support for scattered
1187 * receive; return 1 if scattered receive is required and 0 if not.
1189 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1191 uint32_t overhead = BNXT_MAX_PKT_LEN - BNXT_MAX_MTU;
1195 if (eth_dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER)
1198 if (eth_dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO)
1201 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1202 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1204 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1205 RTE_PKTMBUF_HEADROOM);
1206 if (eth_dev->data->mtu + overhead > buf_size)
1212 static eth_rx_burst_t
1213 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1215 struct bnxt *bp = eth_dev->data->dev_private;
1217 /* Disable vector mode RX for Stingray2 for now */
1218 if (BNXT_CHIP_SR2(bp)) {
1219 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1220 return bnxt_recv_pkts;
1223 #if (defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)) && \
1224 !defined(RTE_LIBRTE_IEEE1588)
1226 /* Vector mode receive cannot be enabled if scattered rx is in use. */
1227 if (eth_dev->data->scattered_rx)
1231 * Vector mode receive cannot be enabled if Truflow is enabled or if
1232 * asynchronous completions and receive completions can be placed in
1233 * the same completion ring.
1235 if (BNXT_TRUFLOW_EN(bp) || !BNXT_NUM_ASYNC_CPR(bp))
1239 * Vector mode receive cannot be enabled if any receive offloads outside
1240 * a limited subset have been enabled.
1242 if (eth_dev->data->dev_conf.rxmode.offloads &
1243 ~(RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
1244 RTE_ETH_RX_OFFLOAD_KEEP_CRC |
1245 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
1246 RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
1247 RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
1248 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1249 RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
1250 RTE_ETH_RX_OFFLOAD_RSS_HASH |
1251 RTE_ETH_RX_OFFLOAD_VLAN_FILTER))
1254 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1255 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1256 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1258 "Using AVX2 vector mode receive for port %d\n",
1259 eth_dev->data->port_id);
1260 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1261 return bnxt_recv_pkts_vec_avx2;
1264 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1266 "Using SSE vector mode receive for port %d\n",
1267 eth_dev->data->port_id);
1268 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1269 return bnxt_recv_pkts_vec;
1273 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1274 eth_dev->data->port_id);
1276 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1277 eth_dev->data->port_id,
1278 eth_dev->data->scattered_rx,
1279 eth_dev->data->dev_conf.rxmode.offloads);
1281 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1282 return bnxt_recv_pkts;
1285 static eth_tx_burst_t
1286 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1288 struct bnxt *bp = eth_dev->data->dev_private;
1290 /* Disable vector mode TX for Stingray2 for now */
1291 if (BNXT_CHIP_SR2(bp))
1292 return bnxt_xmit_pkts;
1294 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) && \
1295 !defined(RTE_LIBRTE_IEEE1588)
1296 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1299 * Vector mode transmit can be enabled only if not using scatter rx
1302 if (eth_dev->data->scattered_rx ||
1303 (offloads & ~RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) ||
1304 BNXT_TRUFLOW_EN(bp))
1307 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1308 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1309 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1311 "Using AVX2 vector mode transmit for port %d\n",
1312 eth_dev->data->port_id);
1313 return bnxt_xmit_pkts_vec_avx2;
1316 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1318 "Using SSE vector mode transmit for port %d\n",
1319 eth_dev->data->port_id);
1320 return bnxt_xmit_pkts_vec;
1324 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1325 eth_dev->data->port_id);
1327 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1328 eth_dev->data->port_id,
1329 eth_dev->data->scattered_rx,
1332 return bnxt_xmit_pkts;
1335 static int bnxt_handle_if_change_status(struct bnxt *bp)
1339 /* Since fw has undergone a reset and lost all contexts,
1340 * set fatal flag to not issue hwrm during cleanup
1342 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1343 bnxt_uninit_resources(bp, true);
1345 /* clear fatal flag so that re-init happens */
1346 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1347 rc = bnxt_init_resources(bp, true);
1349 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1354 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1356 struct bnxt *bp = eth_dev->data->dev_private;
1359 if (!BNXT_SINGLE_PF(bp))
1362 if (!bp->link_info->link_up)
1363 rc = bnxt_set_hwrm_link_config(bp, true);
1365 eth_dev->data->dev_link.link_status = 1;
1367 bnxt_print_link_info(eth_dev);
1371 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1373 struct bnxt *bp = eth_dev->data->dev_private;
1375 if (!BNXT_SINGLE_PF(bp))
1378 eth_dev->data->dev_link.link_status = 0;
1379 bnxt_set_hwrm_link_config(bp, false);
1380 bp->link_info->link_up = 0;
1385 static void bnxt_free_switch_domain(struct bnxt *bp)
1389 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
1392 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1394 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1395 bp->switch_domain_id, rc);
1398 static void bnxt_ptp_get_current_time(void *arg)
1400 struct bnxt *bp = arg;
1401 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1404 rc = is_bnxt_in_error(bp);
1411 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1412 &ptp->current_time);
1414 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1416 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1417 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1421 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1423 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1426 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1429 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1430 &ptp->current_time);
1432 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1436 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1438 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1439 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1440 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1444 static void bnxt_ptp_stop(struct bnxt *bp)
1446 bnxt_cancel_ptp_alarm(bp);
1447 bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1450 static int bnxt_ptp_start(struct bnxt *bp)
1454 rc = bnxt_schedule_ptp_alarm(bp);
1456 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1458 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1459 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1465 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1467 struct bnxt *bp = eth_dev->data->dev_private;
1468 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1469 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1470 struct rte_eth_link link;
1473 eth_dev->data->dev_started = 0;
1475 /* Prevent crashes when queues are still in use */
1476 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1477 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1479 bnxt_disable_int(bp);
1481 /* disable uio/vfio intr/eventfd mapping */
1482 rte_intr_disable(intr_handle);
1484 /* Stop the child representors for this device */
1485 ret = bnxt_rep_stop_all(bp);
1489 /* delete the bnxt ULP port details */
1490 bnxt_ulp_port_deinit(bp);
1492 bnxt_cancel_fw_health_check(bp);
1494 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1495 bnxt_cancel_ptp_alarm(bp);
1497 /* Do not bring link down during reset recovery */
1498 if (!is_bnxt_in_error(bp)) {
1499 bnxt_dev_set_link_down_op(eth_dev);
1500 /* Wait for link to be reset */
1501 if (BNXT_SINGLE_PF(bp))
1503 /* clear the recorded link status */
1504 memset(&link, 0, sizeof(link));
1505 rte_eth_linkstatus_set(eth_dev, &link);
1508 /* Clean queue intr-vector mapping */
1509 rte_intr_efd_disable(intr_handle);
1510 rte_intr_vec_list_free(intr_handle);
1512 bnxt_hwrm_port_clr_stats(bp);
1513 bnxt_free_tx_mbufs(bp);
1514 bnxt_free_rx_mbufs(bp);
1515 /* Process any remaining notifications in default completion queue */
1516 bnxt_int_handler(eth_dev);
1517 bnxt_shutdown_nic(bp);
1518 bnxt_hwrm_if_change(bp, false);
1520 bnxt_free_prev_ring_stats(bp);
1521 rte_free(bp->mark_table);
1522 bp->mark_table = NULL;
1524 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1525 bp->rx_cosq_cnt = 0;
1526 /* All filters are deleted on a port stop. */
1527 if (BNXT_FLOW_XSTATS_EN(bp))
1528 bp->flow_stat->flow_count = 0;
1530 eth_dev->data->scattered_rx = 0;
1535 /* Unload the driver, release resources */
1536 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1538 struct bnxt *bp = eth_dev->data->dev_private;
1540 pthread_mutex_lock(&bp->err_recovery_lock);
1541 if (bp->flags & BNXT_FLAG_FW_RESET) {
1543 "Adapter recovering from error..Please retry\n");
1544 pthread_mutex_unlock(&bp->err_recovery_lock);
1547 pthread_mutex_unlock(&bp->err_recovery_lock);
1549 return bnxt_dev_stop(eth_dev);
1552 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1554 struct bnxt *bp = eth_dev->data->dev_private;
1555 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1557 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1559 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1560 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1564 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1566 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1567 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1570 rc = bnxt_hwrm_if_change(bp, true);
1571 if (rc == 0 || rc != -EAGAIN)
1574 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1575 } while (retry_cnt--);
1580 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1581 rc = bnxt_handle_if_change_status(bp);
1586 bnxt_enable_int(bp);
1588 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1590 rc = bnxt_start_nic(bp);
1594 rc = bnxt_alloc_prev_ring_stats(bp);
1598 eth_dev->data->dev_started = 1;
1600 bnxt_link_update_op(eth_dev, 1);
1602 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
1603 vlan_mask |= RTE_ETH_VLAN_FILTER_MASK;
1604 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
1605 vlan_mask |= RTE_ETH_VLAN_STRIP_MASK;
1606 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1610 /* Initialize bnxt ULP port details */
1611 rc = bnxt_ulp_port_init(bp);
1615 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1616 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1618 bnxt_schedule_fw_health_check(bp);
1620 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1621 bnxt_schedule_ptp_alarm(bp);
1626 bnxt_dev_stop(eth_dev);
1631 bnxt_uninit_locks(struct bnxt *bp)
1633 pthread_mutex_destroy(&bp->flow_lock);
1634 pthread_mutex_destroy(&bp->def_cp_lock);
1635 pthread_mutex_destroy(&bp->health_check_lock);
1636 pthread_mutex_destroy(&bp->err_recovery_lock);
1638 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1639 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1643 static void bnxt_drv_uninit(struct bnxt *bp)
1645 bnxt_free_leds_info(bp);
1646 bnxt_free_cos_queues(bp);
1647 bnxt_free_link_info(bp);
1648 bnxt_free_parent_info(bp);
1649 bnxt_uninit_locks(bp);
1651 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1652 bp->tx_mem_zone = NULL;
1653 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1654 bp->rx_mem_zone = NULL;
1656 bnxt_free_vf_info(bp);
1657 bnxt_free_pf_info(bp);
1659 rte_free(bp->grp_info);
1660 bp->grp_info = NULL;
1663 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1665 struct bnxt *bp = eth_dev->data->dev_private;
1668 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1671 pthread_mutex_lock(&bp->err_recovery_lock);
1672 if (bp->flags & BNXT_FLAG_FW_RESET) {
1674 "Adapter recovering from error...Please retry\n");
1675 pthread_mutex_unlock(&bp->err_recovery_lock);
1678 pthread_mutex_unlock(&bp->err_recovery_lock);
1680 /* cancel the recovery handler before remove dev */
1681 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1682 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1683 bnxt_cancel_fc_thread(bp);
1685 if (eth_dev->data->dev_started)
1686 ret = bnxt_dev_stop(eth_dev);
1688 bnxt_uninit_resources(bp, false);
1690 bnxt_drv_uninit(bp);
1695 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1698 struct bnxt *bp = eth_dev->data->dev_private;
1699 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1700 struct bnxt_vnic_info *vnic;
1701 struct bnxt_filter_info *filter, *temp_filter;
1704 if (is_bnxt_in_error(bp))
1708 * Loop through all VNICs from the specified filter flow pools to
1709 * remove the corresponding MAC addr filter
1711 for (i = 0; i < bp->nr_vnics; i++) {
1712 if (!(pool_mask & (1ULL << i)))
1715 vnic = &bp->vnic_info[i];
1716 filter = STAILQ_FIRST(&vnic->filter);
1718 temp_filter = STAILQ_NEXT(filter, next);
1719 if (filter->mac_index == index) {
1720 STAILQ_REMOVE(&vnic->filter, filter,
1721 bnxt_filter_info, next);
1722 bnxt_hwrm_clear_l2_filter(bp, filter);
1723 bnxt_free_filter(bp, filter);
1725 filter = temp_filter;
1730 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1731 struct rte_ether_addr *mac_addr, uint32_t index,
1734 struct bnxt_filter_info *filter;
1737 /* Attach requested MAC address to the new l2_filter */
1738 STAILQ_FOREACH(filter, &vnic->filter, next) {
1739 if (filter->mac_index == index) {
1741 "MAC addr already existed for pool %d\n",
1747 filter = bnxt_alloc_filter(bp);
1749 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1753 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1754 * if the MAC that's been programmed now is a different one, then,
1755 * copy that addr to filter->l2_addr
1758 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1759 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1761 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1763 filter->mac_index = index;
1764 if (filter->mac_index == 0)
1765 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1767 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1769 bnxt_free_filter(bp, filter);
1775 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1776 struct rte_ether_addr *mac_addr,
1777 uint32_t index, uint32_t pool)
1779 struct bnxt *bp = eth_dev->data->dev_private;
1780 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1783 rc = is_bnxt_in_error(bp);
1787 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1788 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1793 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1797 /* Filter settings will get applied when port is started */
1798 if (!eth_dev->data->dev_started)
1801 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1806 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1809 struct bnxt *bp = eth_dev->data->dev_private;
1810 struct rte_eth_link new;
1811 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1812 BNXT_MIN_LINK_WAIT_CNT;
1814 rc = is_bnxt_in_error(bp);
1818 memset(&new, 0, sizeof(new));
1820 if (bp->link_info == NULL)
1824 /* Retrieve link info from hardware */
1825 rc = bnxt_get_hwrm_link_config(bp, &new);
1827 new.link_speed = RTE_ETH_LINK_SPEED_100M;
1828 new.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
1830 "Failed to retrieve link rc = 0x%x!\n", rc);
1834 if (!wait_to_complete || new.link_status)
1837 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1840 /* Only single function PF can bring phy down.
1841 * When port is stopped, report link down for VF/MH/NPAR functions.
1843 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1844 memset(&new, 0, sizeof(new));
1847 /* Timed out or success */
1848 if (new.link_status != eth_dev->data->dev_link.link_status ||
1849 new.link_speed != eth_dev->data->dev_link.link_speed) {
1850 rte_eth_linkstatus_set(eth_dev, &new);
1851 bnxt_print_link_info(eth_dev);
1857 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1859 struct bnxt *bp = eth_dev->data->dev_private;
1860 struct bnxt_vnic_info *vnic;
1864 rc = is_bnxt_in_error(bp);
1868 /* Filter settings will get applied when port is started */
1869 if (!eth_dev->data->dev_started)
1872 if (bp->vnic_info == NULL)
1875 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1877 old_flags = vnic->flags;
1878 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1879 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1881 vnic->flags = old_flags;
1886 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1888 struct bnxt *bp = eth_dev->data->dev_private;
1889 struct bnxt_vnic_info *vnic;
1893 rc = is_bnxt_in_error(bp);
1897 /* Filter settings will get applied when port is started */
1898 if (!eth_dev->data->dev_started)
1901 if (bp->vnic_info == NULL)
1904 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1906 old_flags = vnic->flags;
1907 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1908 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1910 vnic->flags = old_flags;
1915 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1917 struct bnxt *bp = eth_dev->data->dev_private;
1918 struct bnxt_vnic_info *vnic;
1922 rc = is_bnxt_in_error(bp);
1926 /* Filter settings will get applied when port is started */
1927 if (!eth_dev->data->dev_started)
1930 if (bp->vnic_info == NULL)
1933 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1935 old_flags = vnic->flags;
1936 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1937 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1939 vnic->flags = old_flags;
1944 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1946 struct bnxt *bp = eth_dev->data->dev_private;
1947 struct bnxt_vnic_info *vnic;
1951 rc = is_bnxt_in_error(bp);
1955 /* Filter settings will get applied when port is started */
1956 if (!eth_dev->data->dev_started)
1959 if (bp->vnic_info == NULL)
1962 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1964 old_flags = vnic->flags;
1965 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1966 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1968 vnic->flags = old_flags;
1973 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1974 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1976 if (qid >= bp->rx_nr_rings)
1979 return bp->eth_dev->data->rx_queues[qid];
1982 /* Return rxq corresponding to a given rss table ring/group ID. */
1983 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1985 struct bnxt_rx_queue *rxq;
1988 if (!BNXT_HAS_RING_GRPS(bp)) {
1989 for (i = 0; i < bp->rx_nr_rings; i++) {
1990 rxq = bp->eth_dev->data->rx_queues[i];
1991 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1995 for (i = 0; i < bp->rx_nr_rings; i++) {
1996 if (bp->grp_info[i].fw_grp_id == fwr)
2001 return INVALID_HW_RING_ID;
2004 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
2005 struct rte_eth_rss_reta_entry64 *reta_conf,
2008 struct bnxt *bp = eth_dev->data->dev_private;
2009 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2010 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2011 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2015 rc = is_bnxt_in_error(bp);
2019 if (!vnic->rss_table)
2022 if (!(dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG))
2025 if (reta_size != tbl_size) {
2026 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2027 "(%d) must equal the size supported by the hardware "
2028 "(%d)\n", reta_size, tbl_size);
2032 for (i = 0; i < reta_size; i++) {
2033 struct bnxt_rx_queue *rxq;
2035 idx = i / RTE_ETH_RETA_GROUP_SIZE;
2036 sft = i % RTE_ETH_RETA_GROUP_SIZE;
2038 if (!(reta_conf[idx].mask & (1ULL << sft)))
2041 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
2043 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
2047 if (BNXT_CHIP_P5(bp)) {
2048 vnic->rss_table[i * 2] =
2049 rxq->rx_ring->rx_ring_struct->fw_ring_id;
2050 vnic->rss_table[i * 2 + 1] =
2051 rxq->cp_ring->cp_ring_struct->fw_ring_id;
2053 vnic->rss_table[i] =
2054 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
2058 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2062 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
2063 struct rte_eth_rss_reta_entry64 *reta_conf,
2066 struct bnxt *bp = eth_dev->data->dev_private;
2067 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2068 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2069 uint16_t idx, sft, i;
2072 rc = is_bnxt_in_error(bp);
2078 if (!vnic->rss_table)
2081 if (reta_size != tbl_size) {
2082 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2083 "(%d) must equal the size supported by the hardware "
2084 "(%d)\n", reta_size, tbl_size);
2088 for (idx = 0, i = 0; i < reta_size; i++) {
2089 idx = i / RTE_ETH_RETA_GROUP_SIZE;
2090 sft = i % RTE_ETH_RETA_GROUP_SIZE;
2092 if (reta_conf[idx].mask & (1ULL << sft)) {
2095 if (BNXT_CHIP_P5(bp))
2096 qid = bnxt_rss_to_qid(bp,
2097 vnic->rss_table[i * 2]);
2099 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2101 if (qid == INVALID_HW_RING_ID) {
2102 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2105 reta_conf[idx].reta[sft] = qid;
2112 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2113 struct rte_eth_rss_conf *rss_conf)
2115 struct bnxt *bp = eth_dev->data->dev_private;
2116 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2117 struct bnxt_vnic_info *vnic;
2120 rc = is_bnxt_in_error(bp);
2125 * If RSS enablement were different than dev_configure,
2126 * then return -EINVAL
2128 if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) {
2129 if (!rss_conf->rss_hf)
2130 PMD_DRV_LOG(ERR, "Hash type NONE\n");
2132 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2136 bp->flags |= BNXT_FLAG_UPDATE_HASH;
2137 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
2141 /* Update the default RSS VNIC(s) */
2142 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2143 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2145 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2146 RTE_ETH_RSS_LEVEL(rss_conf->rss_hf));
2149 * If hashkey is not specified, use the previously configured
2152 if (!rss_conf->rss_key)
2155 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2157 "Invalid hashkey length, should be %d bytes\n",
2161 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2164 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2168 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2169 struct rte_eth_rss_conf *rss_conf)
2171 struct bnxt *bp = eth_dev->data->dev_private;
2172 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2174 uint32_t hash_types;
2176 rc = is_bnxt_in_error(bp);
2180 /* RSS configuration is the same for all VNICs */
2181 if (vnic && vnic->rss_hash_key) {
2182 if (rss_conf->rss_key) {
2183 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2184 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2185 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2188 hash_types = vnic->hash_type;
2189 rss_conf->rss_hf = 0;
2190 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2191 rss_conf->rss_hf |= RTE_ETH_RSS_IPV4;
2192 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2194 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2195 rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_TCP;
2197 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2199 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2200 rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_UDP;
2202 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2204 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2205 rss_conf->rss_hf |= RTE_ETH_RSS_IPV6;
2206 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2208 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2209 rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_TCP;
2211 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2213 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2214 rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_UDP;
2216 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2220 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2224 "Unknown RSS config from firmware (%08x), RSS disabled",
2229 rss_conf->rss_hf = 0;
2234 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2235 struct rte_eth_fc_conf *fc_conf)
2237 struct bnxt *bp = dev->data->dev_private;
2238 struct rte_eth_link link_info;
2241 rc = is_bnxt_in_error(bp);
2245 rc = bnxt_get_hwrm_link_config(bp, &link_info);
2249 memset(fc_conf, 0, sizeof(*fc_conf));
2250 if (bp->link_info->auto_pause)
2251 fc_conf->autoneg = 1;
2252 switch (bp->link_info->pause) {
2254 fc_conf->mode = RTE_ETH_FC_NONE;
2256 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2257 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
2259 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2260 fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
2262 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2263 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2264 fc_conf->mode = RTE_ETH_FC_FULL;
2270 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2271 struct rte_eth_fc_conf *fc_conf)
2273 struct bnxt *bp = dev->data->dev_private;
2276 rc = is_bnxt_in_error(bp);
2280 if (!BNXT_SINGLE_PF(bp)) {
2282 "Flow Control Settings cannot be modified on VF or on shared PF\n");
2286 switch (fc_conf->mode) {
2287 case RTE_ETH_FC_NONE:
2288 bp->link_info->auto_pause = 0;
2289 bp->link_info->force_pause = 0;
2291 case RTE_ETH_FC_RX_PAUSE:
2292 if (fc_conf->autoneg) {
2293 bp->link_info->auto_pause =
2294 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2295 bp->link_info->force_pause = 0;
2297 bp->link_info->auto_pause = 0;
2298 bp->link_info->force_pause =
2299 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2302 case RTE_ETH_FC_TX_PAUSE:
2303 if (fc_conf->autoneg) {
2304 bp->link_info->auto_pause =
2305 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2306 bp->link_info->force_pause = 0;
2308 bp->link_info->auto_pause = 0;
2309 bp->link_info->force_pause =
2310 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2313 case RTE_ETH_FC_FULL:
2314 if (fc_conf->autoneg) {
2315 bp->link_info->auto_pause =
2316 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2317 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2318 bp->link_info->force_pause = 0;
2320 bp->link_info->auto_pause = 0;
2321 bp->link_info->force_pause =
2322 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2323 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2327 return bnxt_set_hwrm_link_config(bp, true);
2330 /* Add UDP tunneling port */
2332 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2333 struct rte_eth_udp_tunnel *udp_tunnel)
2335 struct bnxt *bp = eth_dev->data->dev_private;
2336 uint16_t tunnel_type = 0;
2339 rc = is_bnxt_in_error(bp);
2343 switch (udp_tunnel->prot_type) {
2344 case RTE_ETH_TUNNEL_TYPE_VXLAN:
2345 if (bp->vxlan_port_cnt) {
2346 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2347 udp_tunnel->udp_port);
2348 if (bp->vxlan_port != udp_tunnel->udp_port) {
2349 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2352 bp->vxlan_port_cnt++;
2356 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2358 case RTE_ETH_TUNNEL_TYPE_GENEVE:
2359 if (bp->geneve_port_cnt) {
2360 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2361 udp_tunnel->udp_port);
2362 if (bp->geneve_port != udp_tunnel->udp_port) {
2363 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2366 bp->geneve_port_cnt++;
2370 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2373 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2376 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2383 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN)
2384 bp->vxlan_port_cnt++;
2387 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE)
2388 bp->geneve_port_cnt++;
2394 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2395 struct rte_eth_udp_tunnel *udp_tunnel)
2397 struct bnxt *bp = eth_dev->data->dev_private;
2398 uint16_t tunnel_type = 0;
2402 rc = is_bnxt_in_error(bp);
2406 switch (udp_tunnel->prot_type) {
2407 case RTE_ETH_TUNNEL_TYPE_VXLAN:
2408 if (!bp->vxlan_port_cnt) {
2409 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2412 if (bp->vxlan_port != udp_tunnel->udp_port) {
2413 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2414 udp_tunnel->udp_port, bp->vxlan_port);
2417 if (--bp->vxlan_port_cnt)
2421 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2422 port = bp->vxlan_fw_dst_port_id;
2424 case RTE_ETH_TUNNEL_TYPE_GENEVE:
2425 if (!bp->geneve_port_cnt) {
2426 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2429 if (bp->geneve_port != udp_tunnel->udp_port) {
2430 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2431 udp_tunnel->udp_port, bp->geneve_port);
2434 if (--bp->geneve_port_cnt)
2438 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2439 port = bp->geneve_fw_dst_port_id;
2442 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2446 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2450 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2452 struct bnxt_filter_info *filter;
2453 struct bnxt_vnic_info *vnic;
2455 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2457 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2458 filter = STAILQ_FIRST(&vnic->filter);
2460 /* Search for this matching MAC+VLAN filter */
2461 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2462 /* Delete the filter */
2463 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2466 STAILQ_REMOVE(&vnic->filter, filter,
2467 bnxt_filter_info, next);
2468 bnxt_free_filter(bp, filter);
2470 "Deleted vlan filter for %d\n",
2474 filter = STAILQ_NEXT(filter, next);
2479 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2481 struct bnxt_filter_info *filter;
2482 struct bnxt_vnic_info *vnic;
2484 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2485 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2486 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2488 /* Implementation notes on the use of VNIC in this command:
2490 * By default, these filters belong to default vnic for the function.
2491 * Once these filters are set up, only destination VNIC can be modified.
2492 * If the destination VNIC is not specified in this command,
2493 * then the HWRM shall only create an l2 context id.
2496 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2497 filter = STAILQ_FIRST(&vnic->filter);
2498 /* Check if the VLAN has already been added */
2500 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2503 filter = STAILQ_NEXT(filter, next);
2506 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2507 * command to create MAC+VLAN filter with the right flags, enables set.
2509 filter = bnxt_alloc_filter(bp);
2512 "MAC/VLAN filter alloc failed\n");
2515 /* MAC + VLAN ID filter */
2516 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2517 * untagged packets are received
2519 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2520 * packets and only the programmed vlan's packets are received
2522 filter->l2_ivlan = vlan_id;
2523 filter->l2_ivlan_mask = 0x0FFF;
2524 filter->enables |= en;
2525 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2527 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2529 /* Free the newly allocated filter as we were
2530 * not able to create the filter in hardware.
2532 bnxt_free_filter(bp, filter);
2536 filter->mac_index = 0;
2537 /* Add this new filter to the list */
2539 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2541 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2544 "Added Vlan filter for %d\n", vlan_id);
2548 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2549 uint16_t vlan_id, int on)
2551 struct bnxt *bp = eth_dev->data->dev_private;
2554 rc = is_bnxt_in_error(bp);
2558 if (!eth_dev->data->dev_started) {
2559 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2563 /* These operations apply to ALL existing MAC/VLAN filters */
2565 return bnxt_add_vlan_filter(bp, vlan_id);
2567 return bnxt_del_vlan_filter(bp, vlan_id);
2570 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2571 struct bnxt_vnic_info *vnic)
2573 struct bnxt_filter_info *filter;
2576 filter = STAILQ_FIRST(&vnic->filter);
2578 if (filter->mac_index == 0 &&
2579 !memcmp(filter->l2_addr, bp->mac_addr,
2580 RTE_ETHER_ADDR_LEN)) {
2581 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2583 STAILQ_REMOVE(&vnic->filter, filter,
2584 bnxt_filter_info, next);
2585 bnxt_free_filter(bp, filter);
2589 filter = STAILQ_NEXT(filter, next);
2595 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2597 struct bnxt_vnic_info *vnic;
2601 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2602 if (!(rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)) {
2603 /* Remove any VLAN filters programmed */
2604 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2605 bnxt_del_vlan_filter(bp, i);
2607 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2611 /* Default filter will allow packets that match the
2612 * dest mac. So, it has to be deleted, otherwise, we
2613 * will endup receiving vlan packets for which the
2614 * filter is not programmed, when hw-vlan-filter
2615 * configuration is ON
2617 bnxt_del_dflt_mac_filter(bp, vnic);
2618 /* This filter will allow only untagged packets */
2619 bnxt_add_vlan_filter(bp, 0);
2621 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2622 !!(rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER));
2627 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2629 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2633 /* Destroy vnic filters and vnic */
2634 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2635 RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
2636 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2637 bnxt_del_vlan_filter(bp, i);
2639 bnxt_del_dflt_mac_filter(bp, vnic);
2641 rc = bnxt_hwrm_vnic_ctx_free(bp, vnic);
2645 rc = bnxt_hwrm_vnic_free(bp, vnic);
2649 rte_free(vnic->fw_grp_ids);
2650 vnic->fw_grp_ids = NULL;
2652 vnic->rx_queue_cnt = 0;
2658 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2660 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2663 /* Destroy, recreate and reconfigure the default vnic */
2664 rc = bnxt_free_one_vnic(bp, 0);
2668 /* default vnic 0 */
2669 rc = bnxt_setup_one_vnic(bp, 0);
2673 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2674 RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
2675 rc = bnxt_add_vlan_filter(bp, 0);
2678 rc = bnxt_restore_vlan_filters(bp);
2682 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2687 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2691 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2692 !!(rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP));
2698 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2700 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2701 struct bnxt *bp = dev->data->dev_private;
2704 rc = is_bnxt_in_error(bp);
2708 /* Filter settings will get applied when port is started */
2709 if (!dev->data->dev_started)
2712 if (mask & RTE_ETH_VLAN_FILTER_MASK) {
2713 /* Enable or disable VLAN filtering */
2714 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2719 if (mask & RTE_ETH_VLAN_STRIP_MASK) {
2720 /* Enable or disable VLAN stripping */
2721 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2726 if (mask & RTE_ETH_VLAN_EXTEND_MASK) {
2727 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND)
2728 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2730 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2737 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2740 struct bnxt *bp = dev->data->dev_private;
2741 int qinq = dev->data->dev_conf.rxmode.offloads &
2742 RTE_ETH_RX_OFFLOAD_VLAN_EXTEND;
2744 if (vlan_type != RTE_ETH_VLAN_TYPE_INNER &&
2745 vlan_type != RTE_ETH_VLAN_TYPE_OUTER) {
2747 "Unsupported vlan type.");
2752 "QinQ not enabled. Needs to be ON as we can "
2753 "accelerate only outer vlan\n");
2757 if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER) {
2759 case RTE_ETHER_TYPE_QINQ:
2761 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2763 case RTE_ETHER_TYPE_VLAN:
2765 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2767 case RTE_ETHER_TYPE_QINQ1:
2769 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2771 case RTE_ETHER_TYPE_QINQ2:
2773 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2775 case RTE_ETHER_TYPE_QINQ3:
2777 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2780 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2783 bp->outer_tpid_bd |= tpid;
2784 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2785 } else if (vlan_type == RTE_ETH_VLAN_TYPE_INNER) {
2787 "Can accelerate only outer vlan in QinQ\n");
2795 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2796 struct rte_ether_addr *addr)
2798 struct bnxt *bp = dev->data->dev_private;
2799 /* Default Filter is tied to VNIC 0 */
2800 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2803 rc = is_bnxt_in_error(bp);
2807 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2810 if (rte_is_zero_ether_addr(addr))
2813 /* Filter settings will get applied when port is started */
2814 if (!dev->data->dev_started)
2817 /* Check if the requested MAC is already added */
2818 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2821 /* Destroy filter and re-create it */
2822 bnxt_del_dflt_mac_filter(bp, vnic);
2824 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2825 if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {
2826 /* This filter will allow only untagged packets */
2827 rc = bnxt_add_vlan_filter(bp, 0);
2829 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2832 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2837 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2838 struct rte_ether_addr *mc_addr_set,
2839 uint32_t nb_mc_addr)
2841 struct bnxt *bp = eth_dev->data->dev_private;
2842 char *mc_addr_list = (char *)mc_addr_set;
2843 struct bnxt_vnic_info *vnic;
2844 uint32_t off = 0, i = 0;
2847 rc = is_bnxt_in_error(bp);
2851 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2853 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2854 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2858 /* TODO Check for Duplicate mcast addresses */
2859 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2860 for (i = 0; i < nb_mc_addr; i++) {
2861 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2862 RTE_ETHER_ADDR_LEN);
2863 off += RTE_ETHER_ADDR_LEN;
2866 vnic->mc_addr_cnt = i;
2867 if (vnic->mc_addr_cnt)
2868 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2870 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2873 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2877 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2879 struct bnxt *bp = dev->data->dev_private;
2880 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2881 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2882 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2883 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2886 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2887 fw_major, fw_minor, fw_updt, fw_rsvd);
2891 ret += 1; /* add the size of '\0' */
2892 if (fw_size < (size_t)ret)
2899 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2900 struct rte_eth_rxq_info *qinfo)
2902 struct bnxt *bp = dev->data->dev_private;
2903 struct bnxt_rx_queue *rxq;
2905 if (is_bnxt_in_error(bp))
2908 rxq = dev->data->rx_queues[queue_id];
2910 qinfo->mp = rxq->mb_pool;
2911 qinfo->scattered_rx = dev->data->scattered_rx;
2912 qinfo->nb_desc = rxq->nb_rx_desc;
2914 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2915 qinfo->conf.rx_drop_en = rxq->drop_en;
2916 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2917 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2921 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2922 struct rte_eth_txq_info *qinfo)
2924 struct bnxt *bp = dev->data->dev_private;
2925 struct bnxt_tx_queue *txq;
2927 if (is_bnxt_in_error(bp))
2930 txq = dev->data->tx_queues[queue_id];
2932 qinfo->nb_desc = txq->nb_tx_desc;
2934 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2935 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2936 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2938 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2939 qinfo->conf.tx_rs_thresh = 0;
2940 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2941 qinfo->conf.offloads = txq->offloads;
2944 static const struct {
2945 eth_rx_burst_t pkt_burst;
2947 } bnxt_rx_burst_info[] = {
2948 {bnxt_recv_pkts, "Scalar"},
2949 #if defined(RTE_ARCH_X86)
2950 {bnxt_recv_pkts_vec, "Vector SSE"},
2952 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2953 {bnxt_recv_pkts_vec_avx2, "Vector AVX2"},
2955 #if defined(RTE_ARCH_ARM64)
2956 {bnxt_recv_pkts_vec, "Vector Neon"},
2961 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2962 struct rte_eth_burst_mode *mode)
2964 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2967 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2968 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2969 snprintf(mode->info, sizeof(mode->info), "%s",
2970 bnxt_rx_burst_info[i].info);
2978 static const struct {
2979 eth_tx_burst_t pkt_burst;
2981 } bnxt_tx_burst_info[] = {
2982 {bnxt_xmit_pkts, "Scalar"},
2983 #if defined(RTE_ARCH_X86)
2984 {bnxt_xmit_pkts_vec, "Vector SSE"},
2986 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2987 {bnxt_xmit_pkts_vec_avx2, "Vector AVX2"},
2989 #if defined(RTE_ARCH_ARM64)
2990 {bnxt_xmit_pkts_vec, "Vector Neon"},
2995 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2996 struct rte_eth_burst_mode *mode)
2998 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3001 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
3002 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
3003 snprintf(mode->info, sizeof(mode->info), "%s",
3004 bnxt_tx_burst_info[i].info);
3012 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
3014 uint32_t overhead = BNXT_MAX_PKT_LEN - BNXT_MAX_MTU;
3015 struct bnxt *bp = eth_dev->data->dev_private;
3016 uint32_t new_pkt_size;
3020 rc = is_bnxt_in_error(bp);
3024 /* Exit if receive queues are not configured yet */
3025 if (!eth_dev->data->nb_rx_queues)
3028 new_pkt_size = new_mtu + overhead;
3031 * Disallow any MTU change that would require scattered receive support
3032 * if it is not already enabled.
3034 if (eth_dev->data->dev_started &&
3035 !eth_dev->data->scattered_rx &&
3037 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3039 "MTU change would require scattered rx support. ");
3040 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
3044 if (new_mtu > RTE_ETHER_MTU)
3045 bp->flags |= BNXT_FLAG_JUMBO;
3047 bp->flags &= ~BNXT_FLAG_JUMBO;
3049 /* Is there a change in mtu setting? */
3050 if (eth_dev->data->mtu == new_mtu)
3053 for (i = 0; i < bp->nr_vnics; i++) {
3054 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3057 vnic->mru = BNXT_VNIC_MRU(new_mtu);
3058 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
3062 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
3063 size -= RTE_PKTMBUF_HEADROOM;
3065 if (size < new_mtu) {
3066 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
3072 if (bnxt_hwrm_config_host_mtu(bp))
3073 PMD_DRV_LOG(WARNING, "Failed to configure host MTU\n");
3075 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
3081 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
3083 struct bnxt *bp = dev->data->dev_private;
3084 uint16_t vlan = bp->vlan;
3087 rc = is_bnxt_in_error(bp);
3091 if (!BNXT_SINGLE_PF(bp)) {
3092 PMD_DRV_LOG(ERR, "PVID cannot be modified on VF or on shared PF\n");
3095 bp->vlan = on ? pvid : 0;
3097 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
3104 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
3106 struct bnxt *bp = dev->data->dev_private;
3109 rc = is_bnxt_in_error(bp);
3113 return bnxt_hwrm_port_led_cfg(bp, true);
3117 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3119 struct bnxt *bp = dev->data->dev_private;
3122 rc = is_bnxt_in_error(bp);
3126 return bnxt_hwrm_port_led_cfg(bp, false);
3130 bnxt_rx_queue_count_op(void *rx_queue)
3133 struct bnxt_cp_ring_info *cpr;
3134 uint32_t desc = 0, raw_cons, cp_ring_size;
3135 struct bnxt_rx_queue *rxq;
3136 struct rx_pkt_cmpl *rxcmp;
3142 rc = is_bnxt_in_error(bp);
3147 raw_cons = cpr->cp_raw_cons;
3148 cp_ring_size = cpr->cp_ring_struct->ring_size;
3151 uint32_t agg_cnt, cons, cmpl_type;
3153 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3154 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3156 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3159 cmpl_type = CMP_TYPE(rxcmp);
3161 switch (cmpl_type) {
3162 case CMPL_BASE_TYPE_RX_L2:
3163 case CMPL_BASE_TYPE_RX_L2_V2:
3164 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3165 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3169 case CMPL_BASE_TYPE_RX_TPA_END:
3170 if (BNXT_CHIP_P5(rxq->bp)) {
3171 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3173 p5_tpa_end = (void *)rxcmp;
3174 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3176 struct rx_tpa_end_cmpl *tpa_end;
3178 tpa_end = (void *)rxcmp;
3179 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3182 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3187 raw_cons += CMP_LEN(cmpl_type);
3195 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3197 struct bnxt_rx_queue *rxq = rx_queue;
3198 struct bnxt_cp_ring_info *cpr;
3199 struct bnxt_rx_ring_info *rxr;
3200 uint32_t desc, raw_cons, cp_ring_size;
3201 struct bnxt *bp = rxq->bp;
3202 struct rx_pkt_cmpl *rxcmp;
3205 rc = is_bnxt_in_error(bp);
3209 if (offset >= rxq->nb_rx_desc)
3214 cp_ring_size = cpr->cp_ring_struct->ring_size;
3217 * For the vector receive case, the completion at the requested
3218 * offset can be indexed directly.
3220 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3221 if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3222 struct rx_pkt_cmpl *rxcmp;
3225 /* Check status of completion descriptor. */
3226 raw_cons = cpr->cp_raw_cons +
3227 offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3228 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3229 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3231 if (bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3232 return RTE_ETH_RX_DESC_DONE;
3234 /* Check whether rx desc has an mbuf attached. */
3235 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3236 if (cons >= rxq->rxrearm_start &&
3237 cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3238 return RTE_ETH_RX_DESC_UNAVAIL;
3241 return RTE_ETH_RX_DESC_AVAIL;
3246 * For the non-vector receive case, scan the completion ring to
3247 * locate the completion descriptor for the requested offset.
3249 raw_cons = cpr->cp_raw_cons;
3252 uint32_t agg_cnt, cons, cmpl_type;
3254 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3255 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3257 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3260 cmpl_type = CMP_TYPE(rxcmp);
3262 switch (cmpl_type) {
3263 case CMPL_BASE_TYPE_RX_L2:
3264 case CMPL_BASE_TYPE_RX_L2_V2:
3265 if (desc == offset) {
3266 cons = rxcmp->opaque;
3267 if (rxr->rx_buf_ring[cons])
3268 return RTE_ETH_RX_DESC_DONE;
3270 return RTE_ETH_RX_DESC_UNAVAIL;
3272 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3273 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3277 case CMPL_BASE_TYPE_RX_TPA_END:
3279 return RTE_ETH_RX_DESC_DONE;
3281 if (BNXT_CHIP_P5(rxq->bp)) {
3282 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3284 p5_tpa_end = (void *)rxcmp;
3285 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3287 struct rx_tpa_end_cmpl *tpa_end;
3289 tpa_end = (void *)rxcmp;
3290 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3293 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3298 raw_cons += CMP_LEN(cmpl_type);
3302 return RTE_ETH_RX_DESC_AVAIL;
3306 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3308 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3309 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
3310 uint32_t ring_mask, raw_cons, nb_tx_pkts = 0;
3311 struct cmpl_base *cp_desc_ring;
3314 rc = is_bnxt_in_error(txq->bp);
3318 if (offset >= txq->nb_tx_desc)
3321 /* Return "desc done" if descriptor is available for use. */
3322 if (bnxt_tx_bds_in_hw(txq) <= offset)
3323 return RTE_ETH_TX_DESC_DONE;
3325 raw_cons = cpr->cp_raw_cons;
3326 cp_desc_ring = cpr->cp_desc_ring;
3327 ring_mask = cpr->cp_ring_struct->ring_mask;
3329 /* Check to see if hw has posted a completion for the descriptor. */
3331 struct tx_cmpl *txcmp;
3334 cons = RING_CMPL(ring_mask, raw_cons);
3335 txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
3337 if (!bnxt_cpr_cmp_valid(txcmp, raw_cons, ring_mask + 1))
3340 if (CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2)
3341 nb_tx_pkts += rte_le_to_cpu_32(txcmp->opaque);
3343 if (nb_tx_pkts > offset)
3344 return RTE_ETH_TX_DESC_DONE;
3346 raw_cons = NEXT_RAW_CMP(raw_cons);
3349 /* Descriptor is pending transmit, not yet completed by hardware. */
3350 return RTE_ETH_TX_DESC_FULL;
3354 bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
3355 const struct rte_flow_ops **ops)
3357 struct bnxt *bp = dev->data->dev_private;
3363 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3364 struct bnxt_representor *vfr = dev->data->dev_private;
3365 bp = vfr->parent_dev->data->dev_private;
3366 /* parent is deleted while children are still valid */
3368 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n",
3369 dev->data->port_id);
3374 ret = is_bnxt_in_error(bp);
3378 /* PMD supports thread-safe flow operations. rte_flow API
3379 * functions can avoid mutex for multi-thread safety.
3381 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3383 if (BNXT_TRUFLOW_EN(bp))
3384 *ops = &bnxt_ulp_rte_flow_ops;
3386 *ops = &bnxt_flow_ops;
3391 static const uint32_t *
3392 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3394 static const uint32_t ptypes[] = {
3395 RTE_PTYPE_L2_ETHER_VLAN,
3396 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3397 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3401 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3402 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3403 RTE_PTYPE_INNER_L4_ICMP,
3404 RTE_PTYPE_INNER_L4_TCP,
3405 RTE_PTYPE_INNER_L4_UDP,
3409 if (!dev->rx_pkt_burst)
3415 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3418 uint32_t reg_base = *reg_arr & 0xfffff000;
3422 for (i = 0; i < count; i++) {
3423 if ((reg_arr[i] & 0xfffff000) != reg_base)
3426 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3427 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3431 static int bnxt_map_ptp_regs(struct bnxt *bp)
3433 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3437 reg_arr = ptp->rx_regs;
3438 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3442 reg_arr = ptp->tx_regs;
3443 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3447 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3448 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3450 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3451 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3456 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3458 rte_write32(0, (uint8_t *)bp->bar0 +
3459 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3460 rte_write32(0, (uint8_t *)bp->bar0 +
3461 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3464 static uint64_t bnxt_cc_read(struct bnxt *bp)
3468 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3469 BNXT_GRCPF_REG_SYNC_TIME));
3470 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3471 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3475 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3477 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3480 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3481 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3482 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3485 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3486 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3487 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3488 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3489 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3490 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3491 rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]);
3496 static int bnxt_clr_rx_ts(struct bnxt *bp, uint64_t *last_ts)
3498 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3499 struct bnxt_pf_info *pf = bp->pf;
3504 if (!ptp || (bp->flags & BNXT_FLAG_CHIP_P5))
3507 port_id = pf->port_id;
3508 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3509 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3510 while ((fifo & BNXT_PTP_RX_FIFO_PENDING) && (i < BNXT_PTP_RX_PND_CNT)) {
3511 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3512 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3513 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3514 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3515 *last_ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3516 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3517 *last_ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3518 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3522 if (i >= BNXT_PTP_RX_PND_CNT)
3528 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3530 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3531 struct bnxt_pf_info *pf = bp->pf;
3535 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3536 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3537 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3540 port_id = pf->port_id;
3541 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3542 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3544 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3545 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3546 if (fifo & BNXT_PTP_RX_FIFO_PENDING)
3547 return bnxt_clr_rx_ts(bp, ts);
3549 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3550 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3551 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3552 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3558 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3561 struct bnxt *bp = dev->data->dev_private;
3562 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3567 ns = rte_timespec_to_ns(ts);
3568 /* Set the timecounters to a new value. */
3570 ptp->tx_tstamp_tc.nsec = ns;
3571 ptp->rx_tstamp_tc.nsec = ns;
3577 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3579 struct bnxt *bp = dev->data->dev_private;
3580 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3581 uint64_t ns, systime_cycles = 0;
3587 if (BNXT_CHIP_P5(bp))
3588 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3591 systime_cycles = bnxt_cc_read(bp);
3593 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3594 *ts = rte_ns_to_timespec(ns);
3599 bnxt_timesync_enable(struct rte_eth_dev *dev)
3601 struct bnxt *bp = dev->data->dev_private;
3602 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3610 ptp->tx_tstamp_en = 1;
3611 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3613 rc = bnxt_hwrm_ptp_cfg(bp);
3617 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3618 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3619 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3621 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3622 ptp->tc.cc_shift = shift;
3623 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3625 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3626 ptp->rx_tstamp_tc.cc_shift = shift;
3627 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3629 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3630 ptp->tx_tstamp_tc.cc_shift = shift;
3631 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3633 if (!BNXT_CHIP_P5(bp))
3634 bnxt_map_ptp_regs(bp);
3636 rc = bnxt_ptp_start(bp);
3642 bnxt_timesync_disable(struct rte_eth_dev *dev)
3644 struct bnxt *bp = dev->data->dev_private;
3645 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3651 ptp->tx_tstamp_en = 0;
3654 bnxt_hwrm_ptp_cfg(bp);
3656 if (!BNXT_CHIP_P5(bp))
3657 bnxt_unmap_ptp_regs(bp);
3665 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3666 struct timespec *timestamp,
3667 uint32_t flags __rte_unused)
3669 struct bnxt *bp = dev->data->dev_private;
3670 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3671 uint64_t rx_tstamp_cycles = 0;
3677 if (BNXT_CHIP_P5(bp))
3678 rx_tstamp_cycles = ptp->rx_timestamp;
3680 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3682 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3683 *timestamp = rte_ns_to_timespec(ns);
3688 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3689 struct timespec *timestamp)
3691 struct bnxt *bp = dev->data->dev_private;
3692 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3693 uint64_t tx_tstamp_cycles = 0;
3700 if (BNXT_CHIP_P5(bp))
3701 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3704 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3706 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3707 *timestamp = rte_ns_to_timespec(ns);
3713 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3715 struct bnxt *bp = dev->data->dev_private;
3716 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3721 ptp->tc.nsec += delta;
3722 ptp->tx_tstamp_tc.nsec += delta;
3723 ptp->rx_tstamp_tc.nsec += delta;
3729 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3731 struct bnxt *bp = dev->data->dev_private;
3733 uint32_t dir_entries;
3734 uint32_t entry_length;
3736 rc = is_bnxt_in_error(bp);
3740 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3741 bp->pdev->addr.domain, bp->pdev->addr.bus,
3742 bp->pdev->addr.devid, bp->pdev->addr.function);
3744 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3748 return dir_entries * entry_length;
3752 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3753 struct rte_dev_eeprom_info *in_eeprom)
3755 struct bnxt *bp = dev->data->dev_private;
3760 rc = is_bnxt_in_error(bp);
3764 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3765 bp->pdev->addr.domain, bp->pdev->addr.bus,
3766 bp->pdev->addr.devid, bp->pdev->addr.function,
3767 in_eeprom->offset, in_eeprom->length);
3769 if (in_eeprom->offset == 0) /* special offset value to get directory */
3770 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3773 index = in_eeprom->offset >> 24;
3774 offset = in_eeprom->offset & 0xffffff;
3777 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3778 in_eeprom->length, in_eeprom->data);
3783 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3786 case BNX_DIR_TYPE_CHIMP_PATCH:
3787 case BNX_DIR_TYPE_BOOTCODE:
3788 case BNX_DIR_TYPE_BOOTCODE_2:
3789 case BNX_DIR_TYPE_APE_FW:
3790 case BNX_DIR_TYPE_APE_PATCH:
3791 case BNX_DIR_TYPE_KONG_FW:
3792 case BNX_DIR_TYPE_KONG_PATCH:
3793 case BNX_DIR_TYPE_BONO_FW:
3794 case BNX_DIR_TYPE_BONO_PATCH:
3802 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3805 case BNX_DIR_TYPE_AVS:
3806 case BNX_DIR_TYPE_EXP_ROM_MBA:
3807 case BNX_DIR_TYPE_PCIE:
3808 case BNX_DIR_TYPE_TSCF_UCODE:
3809 case BNX_DIR_TYPE_EXT_PHY:
3810 case BNX_DIR_TYPE_CCM:
3811 case BNX_DIR_TYPE_ISCSI_BOOT:
3812 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3813 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3821 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3823 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3824 bnxt_dir_type_is_other_exec_format(dir_type);
3828 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3829 struct rte_dev_eeprom_info *in_eeprom)
3831 struct bnxt *bp = dev->data->dev_private;
3832 uint8_t index, dir_op;
3833 uint16_t type, ext, ordinal, attr;
3836 rc = is_bnxt_in_error(bp);
3840 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3841 bp->pdev->addr.domain, bp->pdev->addr.bus,
3842 bp->pdev->addr.devid, bp->pdev->addr.function,
3843 in_eeprom->offset, in_eeprom->length);
3846 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3850 type = in_eeprom->magic >> 16;
3852 if (type == 0xffff) { /* special value for directory operations */
3853 index = in_eeprom->magic & 0xff;
3854 dir_op = in_eeprom->magic >> 8;
3858 case 0x0e: /* erase */
3859 if (in_eeprom->offset != ~in_eeprom->magic)
3861 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3867 /* Create or re-write an NVM item: */
3868 if (bnxt_dir_type_is_executable(type) == true)
3870 ext = in_eeprom->magic & 0xffff;
3871 ordinal = in_eeprom->offset >> 16;
3872 attr = in_eeprom->offset & 0xffff;
3874 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3875 in_eeprom->data, in_eeprom->length);
3878 static int bnxt_get_module_info(struct rte_eth_dev *dev,
3879 struct rte_eth_dev_module_info *modinfo)
3881 uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3882 struct bnxt *bp = dev->data->dev_private;
3885 /* No point in going further if phy status indicates
3886 * module is not inserted or if it is powered down or
3887 * if it is of type 10GBase-T
3889 if (bp->link_info->module_status >
3890 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG) {
3891 PMD_DRV_LOG(NOTICE, "Port %u : Module is not inserted or is powered down\n",
3892 dev->data->port_id);
3896 /* This feature is not supported in older firmware versions */
3897 if (bp->hwrm_spec_code < 0x10202) {
3898 PMD_DRV_LOG(NOTICE, "Port %u : Feature is not supported in older firmware\n",
3899 dev->data->port_id);
3903 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3904 SFF_DIAG_SUPPORT_OFFSET + 1,
3910 switch (module_info[0]) {
3911 case SFF_MODULE_ID_SFP:
3912 modinfo->type = RTE_ETH_MODULE_SFF_8472;
3913 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
3914 if (module_info[SFF_DIAG_SUPPORT_OFFSET] == 0)
3915 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3917 case SFF_MODULE_ID_QSFP:
3918 case SFF_MODULE_ID_QSFP_PLUS:
3919 modinfo->type = RTE_ETH_MODULE_SFF_8436;
3920 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3922 case SFF_MODULE_ID_QSFP28:
3923 modinfo->type = RTE_ETH_MODULE_SFF_8636;
3924 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
3925 if (module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK)
3926 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_LEN;
3929 PMD_DRV_LOG(NOTICE, "Port %u : Unsupported module\n", dev->data->port_id);
3933 PMD_DRV_LOG(INFO, "Port %u : modinfo->type = %d modinfo->eeprom_len = %d\n",
3934 dev->data->port_id, modinfo->type, modinfo->eeprom_len);
3939 static int bnxt_get_module_eeprom(struct rte_eth_dev *dev,
3940 struct rte_dev_eeprom_info *info)
3942 uint8_t pg_addr[5] = { I2C_DEV_ADDR_A0, I2C_DEV_ADDR_A0 };
3943 uint32_t offset = info->offset, length = info->length;
3944 uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3945 struct bnxt *bp = dev->data->dev_private;
3946 uint8_t *data = info->data;
3947 uint8_t page = offset >> 7;
3948 uint8_t max_pages = 2;
3952 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3953 SFF_DIAG_SUPPORT_OFFSET + 1,
3958 switch (module_info[0]) {
3959 case SFF_MODULE_ID_SFP:
3960 module_info[SFF_DIAG_SUPPORT_OFFSET] = 0;
3961 if (module_info[SFF_DIAG_SUPPORT_OFFSET]) {
3962 pg_addr[2] = I2C_DEV_ADDR_A2;
3963 pg_addr[3] = I2C_DEV_ADDR_A2;
3967 case SFF_MODULE_ID_QSFP28:
3968 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0,
3969 SFF8636_OPT_PAGES_OFFSET,
3974 if (opt_pages & SFF8636_PAGE1_MASK) {
3975 pg_addr[2] = I2C_DEV_ADDR_A0;
3978 if (opt_pages & SFF8636_PAGE2_MASK) {
3979 pg_addr[3] = I2C_DEV_ADDR_A0;
3982 if (~module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK) {
3983 pg_addr[4] = I2C_DEV_ADDR_A0;
3991 memset(data, 0, length);
3994 while (length && page < max_pages) {
3995 uint8_t raw_page = page ? page - 1 : 0;
3998 if (pg_addr[page] == I2C_DEV_ADDR_A2)
4002 chunk = RTE_MIN(length, 256 - offset);
4004 if (pg_addr[page]) {
4005 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, pg_addr[page],
4015 page += 1 + (chunk > 128);
4018 return length ? -EINVAL : 0;
4025 static const struct eth_dev_ops bnxt_dev_ops = {
4026 .dev_infos_get = bnxt_dev_info_get_op,
4027 .dev_close = bnxt_dev_close_op,
4028 .dev_configure = bnxt_dev_configure_op,
4029 .dev_start = bnxt_dev_start_op,
4030 .dev_stop = bnxt_dev_stop_op,
4031 .dev_set_link_up = bnxt_dev_set_link_up_op,
4032 .dev_set_link_down = bnxt_dev_set_link_down_op,
4033 .stats_get = bnxt_stats_get_op,
4034 .stats_reset = bnxt_stats_reset_op,
4035 .rx_queue_setup = bnxt_rx_queue_setup_op,
4036 .rx_queue_release = bnxt_rx_queue_release_op,
4037 .tx_queue_setup = bnxt_tx_queue_setup_op,
4038 .tx_queue_release = bnxt_tx_queue_release_op,
4039 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4040 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4041 .reta_update = bnxt_reta_update_op,
4042 .reta_query = bnxt_reta_query_op,
4043 .rss_hash_update = bnxt_rss_hash_update_op,
4044 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4045 .link_update = bnxt_link_update_op,
4046 .promiscuous_enable = bnxt_promiscuous_enable_op,
4047 .promiscuous_disable = bnxt_promiscuous_disable_op,
4048 .allmulticast_enable = bnxt_allmulticast_enable_op,
4049 .allmulticast_disable = bnxt_allmulticast_disable_op,
4050 .mac_addr_add = bnxt_mac_addr_add_op,
4051 .mac_addr_remove = bnxt_mac_addr_remove_op,
4052 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4053 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4054 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
4055 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
4056 .vlan_filter_set = bnxt_vlan_filter_set_op,
4057 .vlan_offload_set = bnxt_vlan_offload_set_op,
4058 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4059 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4060 .mtu_set = bnxt_mtu_set_op,
4061 .mac_addr_set = bnxt_set_default_mac_addr_op,
4062 .xstats_get = bnxt_dev_xstats_get_op,
4063 .xstats_get_names = bnxt_dev_xstats_get_names_op,
4064 .xstats_reset = bnxt_dev_xstats_reset_op,
4065 .fw_version_get = bnxt_fw_version_get,
4066 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4067 .rxq_info_get = bnxt_rxq_info_get_op,
4068 .txq_info_get = bnxt_txq_info_get_op,
4069 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4070 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4071 .dev_led_on = bnxt_dev_led_on_op,
4072 .dev_led_off = bnxt_dev_led_off_op,
4073 .rx_queue_start = bnxt_rx_queue_start,
4074 .rx_queue_stop = bnxt_rx_queue_stop,
4075 .tx_queue_start = bnxt_tx_queue_start,
4076 .tx_queue_stop = bnxt_tx_queue_stop,
4077 .flow_ops_get = bnxt_flow_ops_get_op,
4078 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4079 .get_eeprom_length = bnxt_get_eeprom_length_op,
4080 .get_eeprom = bnxt_get_eeprom_op,
4081 .set_eeprom = bnxt_set_eeprom_op,
4082 .get_module_info = bnxt_get_module_info,
4083 .get_module_eeprom = bnxt_get_module_eeprom,
4084 .timesync_enable = bnxt_timesync_enable,
4085 .timesync_disable = bnxt_timesync_disable,
4086 .timesync_read_time = bnxt_timesync_read_time,
4087 .timesync_write_time = bnxt_timesync_write_time,
4088 .timesync_adjust_time = bnxt_timesync_adjust_time,
4089 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4090 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4093 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4097 /* Only pre-map the reset GRC registers using window 3 */
4098 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4099 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4101 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4106 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4108 struct bnxt_error_recovery_info *info = bp->recovery_info;
4109 uint32_t reg_base = 0xffffffff;
4112 /* Only pre-map the monitoring GRC registers using window 2 */
4113 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4114 uint32_t reg = info->status_regs[i];
4116 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4119 if (reg_base == 0xffffffff)
4120 reg_base = reg & 0xfffff000;
4121 if ((reg & 0xfffff000) != reg_base)
4124 /* Use mask 0xffc as the Lower 2 bits indicates
4125 * address space location
4127 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4131 if (reg_base == 0xffffffff)
4134 rte_write32(reg_base, (uint8_t *)bp->bar0 +
4135 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4140 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4142 struct bnxt_error_recovery_info *info = bp->recovery_info;
4143 uint32_t delay = info->delay_after_reset[index];
4144 uint32_t val = info->reset_reg_val[index];
4145 uint32_t reg = info->reset_reg[index];
4146 uint32_t type, offset;
4149 type = BNXT_FW_STATUS_REG_TYPE(reg);
4150 offset = BNXT_FW_STATUS_REG_OFF(reg);
4153 case BNXT_FW_STATUS_REG_TYPE_CFG:
4154 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4156 PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x",
4161 case BNXT_FW_STATUS_REG_TYPE_GRC:
4162 offset = bnxt_map_reset_regs(bp, offset);
4163 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4165 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4166 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4169 /* wait on a specific interval of time until core reset is complete */
4171 rte_delay_ms(delay);
4174 static void bnxt_dev_cleanup(struct bnxt *bp)
4176 bp->eth_dev->data->dev_link.link_status = 0;
4177 bp->link_info->link_up = 0;
4178 if (bp->eth_dev->data->dev_started)
4179 bnxt_dev_stop(bp->eth_dev);
4181 bnxt_uninit_resources(bp, true);
4185 bnxt_check_fw_reset_done(struct bnxt *bp)
4187 int timeout = bp->fw_reset_max_msecs;
4192 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4194 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4200 } while (timeout--);
4202 if (val == 0xffff) {
4203 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
4210 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4212 struct rte_eth_dev *dev = bp->eth_dev;
4213 struct rte_vlan_filter_conf *vfc;
4217 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4218 vfc = &dev->data->vlan_filter_conf;
4219 vidx = vlan_id / 64;
4220 vbit = vlan_id % 64;
4222 /* Each bit corresponds to a VLAN id */
4223 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4224 rc = bnxt_add_vlan_filter(bp, vlan_id);
4233 static int bnxt_restore_mac_filters(struct bnxt *bp)
4235 struct rte_eth_dev *dev = bp->eth_dev;
4236 struct rte_eth_dev_info dev_info;
4237 struct rte_ether_addr *addr;
4243 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4246 rc = bnxt_dev_info_get_op(dev, &dev_info);
4250 /* replay MAC address configuration */
4251 for (i = 1; i < dev_info.max_mac_addrs; i++) {
4252 addr = &dev->data->mac_addrs[i];
4254 /* skip zero address */
4255 if (rte_is_zero_ether_addr(addr))
4259 pool_mask = dev->data->mac_pool_sel[i];
4262 if (pool_mask & 1ULL) {
4263 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4269 } while (pool_mask);
4275 static int bnxt_restore_filters(struct bnxt *bp)
4277 struct rte_eth_dev *dev = bp->eth_dev;
4280 if (dev->data->all_multicast) {
4281 ret = bnxt_allmulticast_enable_op(dev);
4285 if (dev->data->promiscuous) {
4286 ret = bnxt_promiscuous_enable_op(dev);
4291 ret = bnxt_restore_mac_filters(bp);
4295 ret = bnxt_restore_vlan_filters(bp);
4296 /* TODO restore other filters as well */
4300 static int bnxt_check_fw_ready(struct bnxt *bp)
4302 int timeout = bp->fw_reset_max_msecs;
4306 rc = bnxt_hwrm_poll_ver_get(bp);
4309 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4310 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4311 } while (rc && timeout > 0);
4314 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4319 static void bnxt_dev_recover(void *arg)
4321 struct bnxt *bp = arg;
4324 pthread_mutex_lock(&bp->err_recovery_lock);
4326 if (!bp->fw_reset_min_msecs) {
4327 rc = bnxt_check_fw_reset_done(bp);
4332 /* Clear Error flag so that device re-init should happen */
4333 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4335 rc = bnxt_check_fw_ready(bp);
4339 rc = bnxt_init_resources(bp, true);
4342 "Failed to initialize resources after reset\n");
4345 /* clear reset flag as the device is initialized now */
4346 bp->flags &= ~BNXT_FLAG_FW_RESET;
4348 rc = bnxt_dev_start_op(bp->eth_dev);
4350 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4354 rc = bnxt_restore_filters(bp);
4358 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4359 pthread_mutex_unlock(&bp->err_recovery_lock);
4363 bnxt_dev_stop(bp->eth_dev);
4365 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4366 bnxt_uninit_resources(bp, false);
4367 if (bp->eth_dev->data->dev_conf.intr_conf.rmv)
4368 rte_eth_dev_callback_process(bp->eth_dev,
4369 RTE_ETH_EVENT_INTR_RMV,
4371 pthread_mutex_unlock(&bp->err_recovery_lock);
4372 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4375 void bnxt_dev_reset_and_resume(void *arg)
4377 struct bnxt *bp = arg;
4378 uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4382 bnxt_dev_cleanup(bp);
4384 bnxt_wait_for_device_shutdown(bp);
4386 /* During some fatal firmware error conditions, the PCI config space
4387 * register 0x2e which normally contains the subsystem ID will become
4388 * 0xffff. This register will revert back to the normal value after
4389 * the chip has completed core reset. If we detect this condition,
4390 * we can poll this config register immediately for the value to revert.
4392 if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4393 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4395 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4398 if (val == 0xffff) {
4399 bp->fw_reset_min_msecs = 0;
4404 rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4406 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4409 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4411 struct bnxt_error_recovery_info *info = bp->recovery_info;
4412 uint32_t reg = info->status_regs[index];
4413 uint32_t type, offset, val = 0;
4416 type = BNXT_FW_STATUS_REG_TYPE(reg);
4417 offset = BNXT_FW_STATUS_REG_OFF(reg);
4420 case BNXT_FW_STATUS_REG_TYPE_CFG:
4421 ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4423 PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x",
4426 case BNXT_FW_STATUS_REG_TYPE_GRC:
4427 offset = info->mapped_status_regs[index];
4429 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4430 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4438 static int bnxt_fw_reset_all(struct bnxt *bp)
4440 struct bnxt_error_recovery_info *info = bp->recovery_info;
4444 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4445 /* Reset through primary function driver */
4446 for (i = 0; i < info->reg_array_cnt; i++)
4447 bnxt_write_fw_reset_reg(bp, i);
4448 /* Wait for time specified by FW after triggering reset */
4449 rte_delay_ms(info->primary_func_wait_period_after_reset);
4450 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4451 /* Reset with the help of Kong processor */
4452 rc = bnxt_hwrm_fw_reset(bp);
4454 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4460 static void bnxt_fw_reset_cb(void *arg)
4462 struct bnxt *bp = arg;
4463 struct bnxt_error_recovery_info *info = bp->recovery_info;
4466 /* Only Primary function can do FW reset */
4467 if (bnxt_is_primary_func(bp) &&
4468 bnxt_is_recovery_enabled(bp)) {
4469 rc = bnxt_fw_reset_all(bp);
4471 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4476 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4477 * EXCEPTION_FATAL_ASYNC event to all the functions
4478 * (including MASTER FUNC). After receiving this Async, all the active
4479 * drivers should treat this case as FW initiated recovery
4481 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4482 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4483 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4485 /* To recover from error */
4486 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4491 /* Driver should poll FW heartbeat, reset_counter with the frequency
4492 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4493 * When the driver detects heartbeat stop or change in reset_counter,
4494 * it has to trigger a reset to recover from the error condition.
4495 * A “primary function” is the function who will have the privilege to
4496 * initiate the chimp reset. The primary function will be elected by the
4497 * firmware and will be notified through async message.
4499 static void bnxt_check_fw_health(void *arg)
4501 struct bnxt *bp = arg;
4502 struct bnxt_error_recovery_info *info = bp->recovery_info;
4503 uint32_t val = 0, wait_msec;
4505 if (!info || !bnxt_is_recovery_enabled(bp) ||
4506 is_bnxt_in_error(bp))
4509 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4510 if (val == info->last_heart_beat)
4513 info->last_heart_beat = val;
4515 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4516 if (val != info->last_reset_counter)
4519 info->last_reset_counter = val;
4521 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4522 bnxt_check_fw_health, (void *)bp);
4526 /* Stop DMA to/from device */
4527 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4528 bp->flags |= BNXT_FLAG_FW_RESET;
4532 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4534 if (bnxt_is_primary_func(bp))
4535 wait_msec = info->primary_func_wait_period;
4537 wait_msec = info->normal_func_wait_period;
4539 rte_eal_alarm_set(US_PER_MS * wait_msec,
4540 bnxt_fw_reset_cb, (void *)bp);
4543 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4545 uint32_t polling_freq;
4547 pthread_mutex_lock(&bp->health_check_lock);
4549 if (!bnxt_is_recovery_enabled(bp))
4552 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4555 polling_freq = bp->recovery_info->driver_polling_freq;
4557 rte_eal_alarm_set(US_PER_MS * polling_freq,
4558 bnxt_check_fw_health, (void *)bp);
4559 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4562 pthread_mutex_unlock(&bp->health_check_lock);
4565 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4567 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4568 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4571 static bool bnxt_vf_pciid(uint16_t device_id)
4573 switch (device_id) {
4574 case BROADCOM_DEV_ID_57304_VF:
4575 case BROADCOM_DEV_ID_57406_VF:
4576 case BROADCOM_DEV_ID_5731X_VF:
4577 case BROADCOM_DEV_ID_5741X_VF:
4578 case BROADCOM_DEV_ID_57414_VF:
4579 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4580 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4581 case BROADCOM_DEV_ID_58802_VF:
4582 case BROADCOM_DEV_ID_57500_VF1:
4583 case BROADCOM_DEV_ID_57500_VF2:
4584 case BROADCOM_DEV_ID_58818_VF:
4592 /* Phase 5 device */
4593 static bool bnxt_p5_device(uint16_t device_id)
4595 switch (device_id) {
4596 case BROADCOM_DEV_ID_57508:
4597 case BROADCOM_DEV_ID_57504:
4598 case BROADCOM_DEV_ID_57502:
4599 case BROADCOM_DEV_ID_57508_MF1:
4600 case BROADCOM_DEV_ID_57504_MF1:
4601 case BROADCOM_DEV_ID_57502_MF1:
4602 case BROADCOM_DEV_ID_57508_MF2:
4603 case BROADCOM_DEV_ID_57504_MF2:
4604 case BROADCOM_DEV_ID_57502_MF2:
4605 case BROADCOM_DEV_ID_57500_VF1:
4606 case BROADCOM_DEV_ID_57500_VF2:
4607 case BROADCOM_DEV_ID_58812:
4608 case BROADCOM_DEV_ID_58814:
4609 case BROADCOM_DEV_ID_58818:
4610 case BROADCOM_DEV_ID_58818_VF:
4618 bool bnxt_stratus_device(struct bnxt *bp)
4620 uint16_t device_id = bp->pdev->id.device_id;
4622 switch (device_id) {
4623 case BROADCOM_DEV_ID_STRATUS_NIC:
4624 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4625 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4633 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4635 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4636 struct bnxt *bp = eth_dev->data->dev_private;
4638 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4639 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4640 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4641 if (!bp->bar0 || !bp->doorbell_base) {
4642 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4646 bp->eth_dev = eth_dev;
4652 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4653 struct bnxt_ctx_pg_info *ctx_pg,
4658 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4659 const struct rte_memzone *mz = NULL;
4660 char mz_name[RTE_MEMZONE_NAMESIZE];
4661 rte_iova_t mz_phys_addr;
4662 uint64_t valid_bits = 0;
4669 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4671 rmem->page_size = BNXT_PAGE_SIZE;
4672 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4673 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4674 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4676 valid_bits = PTU_PTE_VALID;
4678 if (rmem->nr_pages > 1) {
4679 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4680 "bnxt_ctx_pg_tbl%s_%x_%d",
4681 suffix, idx, bp->eth_dev->data->port_id);
4682 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4683 mz = rte_memzone_lookup(mz_name);
4685 mz = rte_memzone_reserve_aligned(mz_name,
4687 bp->eth_dev->device->numa_node,
4689 RTE_MEMZONE_SIZE_HINT_ONLY |
4690 RTE_MEMZONE_IOVA_CONTIG,
4696 memset(mz->addr, 0, mz->len);
4697 mz_phys_addr = mz->iova;
4699 rmem->pg_tbl = mz->addr;
4700 rmem->pg_tbl_map = mz_phys_addr;
4701 rmem->pg_tbl_mz = mz;
4704 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4705 suffix, idx, bp->eth_dev->data->port_id);
4706 mz = rte_memzone_lookup(mz_name);
4708 mz = rte_memzone_reserve_aligned(mz_name,
4710 bp->eth_dev->device->numa_node,
4712 RTE_MEMZONE_SIZE_HINT_ONLY |
4713 RTE_MEMZONE_IOVA_CONTIG,
4719 memset(mz->addr, 0, mz->len);
4720 mz_phys_addr = mz->iova;
4722 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4723 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4724 rmem->dma_arr[i] = mz_phys_addr + sz;
4726 if (rmem->nr_pages > 1) {
4727 if (i == rmem->nr_pages - 2 &&
4728 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4729 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4730 else if (i == rmem->nr_pages - 1 &&
4731 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4732 valid_bits |= PTU_PTE_LAST;
4734 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4740 if (rmem->vmem_size)
4741 rmem->vmem = (void **)mz->addr;
4742 rmem->dma_arr[0] = mz_phys_addr;
4746 static void bnxt_free_ctx_mem(struct bnxt *bp)
4750 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4753 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4754 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4755 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4756 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4757 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4758 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4759 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4760 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4761 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4762 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4763 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4765 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4766 if (bp->ctx->tqm_mem[i])
4767 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4774 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4776 #define min_t(type, x, y) ({ \
4777 type __min1 = (x); \
4778 type __min2 = (y); \
4779 __min1 < __min2 ? __min1 : __min2; })
4781 #define max_t(type, x, y) ({ \
4782 type __max1 = (x); \
4783 type __max2 = (y); \
4784 __max1 > __max2 ? __max1 : __max2; })
4786 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4788 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4790 struct bnxt_ctx_pg_info *ctx_pg;
4791 struct bnxt_ctx_mem_info *ctx;
4792 uint32_t mem_size, ena, entries;
4793 uint32_t entries_sp, min;
4796 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4798 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4802 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4805 ctx_pg = &ctx->qp_mem;
4806 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4807 if (ctx->qp_entry_size) {
4808 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4809 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4814 ctx_pg = &ctx->srq_mem;
4815 ctx_pg->entries = ctx->srq_max_l2_entries;
4816 if (ctx->srq_entry_size) {
4817 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4818 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4823 ctx_pg = &ctx->cq_mem;
4824 ctx_pg->entries = ctx->cq_max_l2_entries;
4825 if (ctx->cq_entry_size) {
4826 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4827 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4832 ctx_pg = &ctx->vnic_mem;
4833 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4834 ctx->vnic_max_ring_table_entries;
4835 if (ctx->vnic_entry_size) {
4836 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4837 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4842 ctx_pg = &ctx->stat_mem;
4843 ctx_pg->entries = ctx->stat_max_entries;
4844 if (ctx->stat_entry_size) {
4845 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4846 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4851 min = ctx->tqm_min_entries_per_ring;
4853 entries_sp = ctx->qp_max_l2_entries +
4854 ctx->vnic_max_vnic_entries +
4855 2 * ctx->qp_min_qp1_entries + min;
4856 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4858 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4859 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4860 entries = clamp_t(uint32_t, entries, min,
4861 ctx->tqm_max_entries_per_ring);
4862 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4863 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4864 * i > 8 is other ext rings.
4866 ctx_pg = ctx->tqm_mem[i];
4867 ctx_pg->entries = i ? entries : entries_sp;
4868 if (ctx->tqm_entry_size) {
4869 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4870 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4875 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4876 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4878 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4881 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4882 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4885 "Failed to configure context mem: rc = %d\n", rc);
4887 ctx->flags |= BNXT_CTX_FLAG_INITED;
4892 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4894 struct rte_pci_device *pci_dev = bp->pdev;
4895 char mz_name[RTE_MEMZONE_NAMESIZE];
4896 const struct rte_memzone *mz = NULL;
4897 uint32_t total_alloc_len;
4898 rte_iova_t mz_phys_addr;
4900 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4903 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4904 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4905 pci_dev->addr.bus, pci_dev->addr.devid,
4906 pci_dev->addr.function, "rx_port_stats");
4907 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4908 mz = rte_memzone_lookup(mz_name);
4910 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4911 sizeof(struct rx_port_stats_ext) + 512);
4913 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4916 RTE_MEMZONE_SIZE_HINT_ONLY |
4917 RTE_MEMZONE_IOVA_CONTIG);
4921 memset(mz->addr, 0, mz->len);
4922 mz_phys_addr = mz->iova;
4924 bp->rx_mem_zone = (const void *)mz;
4925 bp->hw_rx_port_stats = mz->addr;
4926 bp->hw_rx_port_stats_map = mz_phys_addr;
4928 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4929 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4930 pci_dev->addr.bus, pci_dev->addr.devid,
4931 pci_dev->addr.function, "tx_port_stats");
4932 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4933 mz = rte_memzone_lookup(mz_name);
4935 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4936 sizeof(struct tx_port_stats_ext) + 512);
4938 mz = rte_memzone_reserve(mz_name,
4942 RTE_MEMZONE_SIZE_HINT_ONLY |
4943 RTE_MEMZONE_IOVA_CONTIG);
4947 memset(mz->addr, 0, mz->len);
4948 mz_phys_addr = mz->iova;
4950 bp->tx_mem_zone = (const void *)mz;
4951 bp->hw_tx_port_stats = mz->addr;
4952 bp->hw_tx_port_stats_map = mz_phys_addr;
4953 bp->flags |= BNXT_FLAG_PORT_STATS;
4955 /* Display extended statistics if FW supports it */
4956 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4957 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4958 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4961 bp->hw_rx_port_stats_ext = (void *)
4962 ((uint8_t *)bp->hw_rx_port_stats +
4963 sizeof(struct rx_port_stats));
4964 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4965 sizeof(struct rx_port_stats);
4966 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4968 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4969 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4970 bp->hw_tx_port_stats_ext = (void *)
4971 ((uint8_t *)bp->hw_tx_port_stats +
4972 sizeof(struct tx_port_stats));
4973 bp->hw_tx_port_stats_ext_map =
4974 bp->hw_tx_port_stats_map +
4975 sizeof(struct tx_port_stats);
4976 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4982 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4984 struct bnxt *bp = eth_dev->data->dev_private;
4987 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4988 RTE_ETHER_ADDR_LEN *
4991 if (eth_dev->data->mac_addrs == NULL) {
4992 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4996 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5000 /* Generate a random MAC address, if none was assigned by PF */
5001 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5002 bnxt_eth_hw_addr_random(bp->mac_addr);
5004 "Assign random MAC:" RTE_ETHER_ADDR_PRT_FMT "\n",
5005 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5006 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5008 rc = bnxt_hwrm_set_mac(bp);
5013 /* Copy the permanent MAC from the FUNC_QCAPS response */
5014 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5019 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5023 /* MAC is already configured in FW */
5024 if (BNXT_HAS_DFLT_MAC_SET(bp))
5027 /* Restore the old MAC configured */
5028 rc = bnxt_hwrm_set_mac(bp);
5030 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5035 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5040 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5042 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
5043 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
5044 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
5045 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
5046 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
5047 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
5051 bnxt_get_bp(uint16_t port)
5054 struct rte_eth_dev *dev;
5056 if (!rte_eth_dev_is_valid_port(port)) {
5057 PMD_DRV_LOG(ERR, "Invalid port %d\n", port);
5061 dev = &rte_eth_devices[port];
5062 if (!is_bnxt_supported(dev)) {
5063 PMD_DRV_LOG(ERR, "Device %d not supported\n", port);
5067 bp = (struct bnxt *)dev->data->dev_private;
5068 if (!BNXT_TRUFLOW_EN(bp)) {
5069 PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n");
5077 bnxt_get_svif(uint16_t port_id, bool func_svif,
5078 enum bnxt_ulp_intf_type type)
5080 struct rte_eth_dev *eth_dev;
5083 eth_dev = &rte_eth_devices[port_id];
5084 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5085 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5089 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5092 eth_dev = vfr->parent_dev;
5095 bp = eth_dev->data->dev_private;
5097 return func_svif ? bp->func_svif : bp->port_svif;
5101 bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type,
5102 uint8_t *mac, uint8_t *parent_mac)
5104 struct rte_eth_dev *eth_dev;
5107 if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF &&
5108 type != BNXT_ULP_INTF_TYPE_PF)
5111 eth_dev = &rte_eth_devices[port];
5112 bp = eth_dev->data->dev_private;
5113 memcpy(mac, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5115 if (type == BNXT_ULP_INTF_TYPE_TRUSTED_VF)
5116 memcpy(parent_mac, bp->parent->mac_addr, RTE_ETHER_ADDR_LEN);
5120 bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5122 struct rte_eth_dev *eth_dev;
5125 if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF)
5128 eth_dev = &rte_eth_devices[port];
5129 bp = eth_dev->data->dev_private;
5131 return bp->parent->vnic;
5134 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5136 struct rte_eth_dev *eth_dev;
5137 struct bnxt_vnic_info *vnic;
5140 eth_dev = &rte_eth_devices[port];
5141 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5142 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5146 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5147 return vfr->dflt_vnic_id;
5149 eth_dev = vfr->parent_dev;
5152 bp = eth_dev->data->dev_private;
5154 vnic = BNXT_GET_DEFAULT_VNIC(bp);
5156 return vnic->fw_vnic_id;
5160 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5162 struct rte_eth_dev *eth_dev;
5165 eth_dev = &rte_eth_devices[port];
5166 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5167 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5171 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5174 eth_dev = vfr->parent_dev;
5177 bp = eth_dev->data->dev_private;
5182 enum bnxt_ulp_intf_type
5183 bnxt_get_interface_type(uint16_t port)
5185 struct rte_eth_dev *eth_dev;
5188 eth_dev = &rte_eth_devices[port];
5189 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5190 return BNXT_ULP_INTF_TYPE_VF_REP;
5192 bp = eth_dev->data->dev_private;
5194 return BNXT_ULP_INTF_TYPE_PF;
5195 else if (BNXT_VF_IS_TRUSTED(bp))
5196 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5197 else if (BNXT_VF(bp))
5198 return BNXT_ULP_INTF_TYPE_VF;
5200 return BNXT_ULP_INTF_TYPE_INVALID;
5204 bnxt_get_phy_port_id(uint16_t port_id)
5206 struct bnxt_representor *vfr;
5207 struct rte_eth_dev *eth_dev;
5210 eth_dev = &rte_eth_devices[port_id];
5211 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5212 vfr = eth_dev->data->dev_private;
5216 eth_dev = vfr->parent_dev;
5219 bp = eth_dev->data->dev_private;
5221 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5225 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5227 struct rte_eth_dev *eth_dev;
5230 eth_dev = &rte_eth_devices[port_id];
5231 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5232 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5236 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5237 return vfr->fw_fid - 1;
5239 eth_dev = vfr->parent_dev;
5242 bp = eth_dev->data->dev_private;
5244 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5248 bnxt_get_vport(uint16_t port_id)
5250 return (1 << bnxt_get_phy_port_id(port_id));
5253 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5255 struct bnxt_error_recovery_info *info = bp->recovery_info;
5258 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5259 memset(info, 0, sizeof(*info));
5263 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5266 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5269 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5271 bp->recovery_info = info;
5274 static void bnxt_check_fw_status(struct bnxt *bp)
5278 if (!(bp->recovery_info &&
5279 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5282 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5283 if (fw_status != BNXT_FW_STATUS_HEALTHY)
5284 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5288 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5290 struct bnxt_error_recovery_info *info = bp->recovery_info;
5291 uint32_t status_loc;
5294 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5295 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5296 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5297 BNXT_GRCP_WINDOW_2_BASE +
5298 offsetof(struct hcomm_status,
5300 /* If the signature is absent, then FW does not support this feature */
5301 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5302 HCOMM_STATUS_SIGNATURE_VAL)
5306 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5310 bp->recovery_info = info;
5312 memset(info, 0, sizeof(*info));
5315 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5316 BNXT_GRCP_WINDOW_2_BASE +
5317 offsetof(struct hcomm_status,
5320 /* Only pre-map the FW health status GRC register */
5321 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5324 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5325 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5326 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5328 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5329 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5331 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5336 /* This function gets the FW version along with the
5337 * capabilities(MAX and current) of the function, vnic,
5338 * error recovery, phy and other chip related info
5340 static int bnxt_get_config(struct bnxt *bp)
5347 rc = bnxt_map_hcomm_fw_status_reg(bp);
5351 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5353 bnxt_check_fw_status(bp);
5357 rc = bnxt_hwrm_func_reset(bp);
5361 rc = bnxt_hwrm_vnic_qcaps(bp);
5365 rc = bnxt_hwrm_queue_qportcfg(bp);
5369 /* Get the MAX capabilities for this function.
5370 * This function also allocates context memory for TQM rings and
5371 * informs the firmware about this allocated backing store memory.
5373 rc = bnxt_hwrm_func_qcaps(bp);
5377 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5381 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5385 bnxt_hwrm_port_mac_qcfg(bp);
5387 bnxt_hwrm_parent_pf_qcfg(bp);
5389 bnxt_hwrm_port_phy_qcaps(bp);
5391 bnxt_alloc_error_recovery_info(bp);
5392 /* Get the adapter error recovery support info */
5393 rc = bnxt_hwrm_error_recovery_qcfg(bp);
5395 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5397 bnxt_hwrm_port_led_qcaps(bp);
5403 bnxt_init_locks(struct bnxt *bp)
5407 err = pthread_mutex_init(&bp->flow_lock, NULL);
5409 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5413 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5415 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5419 err = pthread_mutex_init(&bp->health_check_lock, NULL);
5421 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5425 err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5427 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5432 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5436 rc = bnxt_get_config(bp);
5440 if (!reconfig_dev) {
5441 rc = bnxt_setup_mac_addr(bp->eth_dev);
5445 rc = bnxt_restore_dflt_mac(bp);
5450 bnxt_config_vf_req_fwd(bp);
5452 rc = bnxt_hwrm_func_driver_register(bp);
5454 PMD_DRV_LOG(ERR, "Failed to register driver");
5459 if (bp->pdev->max_vfs) {
5460 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5462 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5466 rc = bnxt_hwrm_allocate_pf_only(bp);
5469 "Failed to allocate PF resources");
5475 rc = bnxt_alloc_mem(bp, reconfig_dev);
5479 rc = bnxt_setup_int(bp);
5483 rc = bnxt_request_int(bp);
5487 rc = bnxt_init_ctx_mem(bp);
5489 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5497 bnxt_parse_devarg_accum_stats(__rte_unused const char *key,
5498 const char *value, void *opaque_arg)
5500 struct bnxt *bp = opaque_arg;
5501 unsigned long accum_stats;
5504 if (!value || !opaque_arg) {
5506 "Invalid parameter passed to accum-stats devargs.\n");
5510 accum_stats = strtoul(value, &end, 10);
5511 if (end == NULL || *end != '\0' ||
5512 (accum_stats == ULONG_MAX && errno == ERANGE)) {
5514 "Invalid parameter passed to accum-stats devargs.\n");
5518 if (BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)) {
5520 "Invalid value passed to accum-stats devargs.\n");
5525 bp->flags2 |= BNXT_FLAGS2_ACCUM_STATS_EN;
5526 PMD_DRV_LOG(INFO, "Host-based accum-stats feature enabled.\n");
5528 bp->flags2 &= ~BNXT_FLAGS2_ACCUM_STATS_EN;
5529 PMD_DRV_LOG(INFO, "Host-based accum-stats feature disabled.\n");
5536 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5537 const char *value, void *opaque_arg)
5539 struct bnxt *bp = opaque_arg;
5540 unsigned long flow_xstat;
5543 if (!value || !opaque_arg) {
5545 "Invalid parameter passed to flow_xstat devarg.\n");
5549 flow_xstat = strtoul(value, &end, 10);
5550 if (end == NULL || *end != '\0' ||
5551 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5553 "Invalid parameter passed to flow_xstat devarg.\n");
5557 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5559 "Invalid value passed to flow_xstat devarg.\n");
5563 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5564 if (BNXT_FLOW_XSTATS_EN(bp))
5565 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5571 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5572 const char *value, void *opaque_arg)
5574 struct bnxt *bp = opaque_arg;
5575 unsigned long max_num_kflows;
5578 if (!value || !opaque_arg) {
5580 "Invalid parameter passed to max_num_kflows devarg.\n");
5584 max_num_kflows = strtoul(value, &end, 10);
5585 if (end == NULL || *end != '\0' ||
5586 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5588 "Invalid parameter passed to max_num_kflows devarg.\n");
5592 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5594 "Invalid value passed to max_num_kflows devarg.\n");
5598 bp->max_num_kflows = max_num_kflows;
5599 if (bp->max_num_kflows)
5600 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5607 bnxt_parse_devarg_app_id(__rte_unused const char *key,
5608 const char *value, void *opaque_arg)
5610 struct bnxt *bp = opaque_arg;
5611 unsigned long app_id;
5614 if (!value || !opaque_arg) {
5616 "Invalid parameter passed to app-id "
5621 app_id = strtoul(value, &end, 10);
5622 if (end == NULL || *end != '\0' ||
5623 (app_id == ULONG_MAX && errno == ERANGE)) {
5625 "Invalid parameter passed to app_id "
5630 if (BNXT_DEVARG_APP_ID_INVALID(app_id)) {
5631 PMD_DRV_LOG(ERR, "Invalid app-id(%d) devargs.\n",
5636 bp->app_id = app_id;
5637 PMD_DRV_LOG(INFO, "app-id=%d feature enabled.\n", (uint16_t)app_id);
5643 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5644 const char *value, void *opaque_arg)
5646 struct bnxt_representor *vfr_bp = opaque_arg;
5647 unsigned long rep_is_pf;
5650 if (!value || !opaque_arg) {
5652 "Invalid parameter passed to rep_is_pf devargs.\n");
5656 rep_is_pf = strtoul(value, &end, 10);
5657 if (end == NULL || *end != '\0' ||
5658 (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5660 "Invalid parameter passed to rep_is_pf devargs.\n");
5664 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5666 "Invalid value passed to rep_is_pf devargs.\n");
5670 vfr_bp->flags |= rep_is_pf;
5671 if (BNXT_REP_PF(vfr_bp))
5672 PMD_DRV_LOG(INFO, "PF representor\n");
5674 PMD_DRV_LOG(INFO, "VF representor\n");
5680 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5681 const char *value, void *opaque_arg)
5683 struct bnxt_representor *vfr_bp = opaque_arg;
5684 unsigned long rep_based_pf;
5687 if (!value || !opaque_arg) {
5689 "Invalid parameter passed to rep_based_pf "
5694 rep_based_pf = strtoul(value, &end, 10);
5695 if (end == NULL || *end != '\0' ||
5696 (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5698 "Invalid parameter passed to rep_based_pf "
5703 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5705 "Invalid value passed to rep_based_pf devargs.\n");
5709 vfr_bp->rep_based_pf = rep_based_pf;
5710 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5712 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5718 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5719 const char *value, void *opaque_arg)
5721 struct bnxt_representor *vfr_bp = opaque_arg;
5722 unsigned long rep_q_r2f;
5725 if (!value || !opaque_arg) {
5727 "Invalid parameter passed to rep_q_r2f "
5732 rep_q_r2f = strtoul(value, &end, 10);
5733 if (end == NULL || *end != '\0' ||
5734 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5736 "Invalid parameter passed to rep_q_r2f "
5741 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5743 "Invalid value passed to rep_q_r2f devargs.\n");
5747 vfr_bp->rep_q_r2f = rep_q_r2f;
5748 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5749 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5755 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5756 const char *value, void *opaque_arg)
5758 struct bnxt_representor *vfr_bp = opaque_arg;
5759 unsigned long rep_q_f2r;
5762 if (!value || !opaque_arg) {
5764 "Invalid parameter passed to rep_q_f2r "
5769 rep_q_f2r = strtoul(value, &end, 10);
5770 if (end == NULL || *end != '\0' ||
5771 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5773 "Invalid parameter passed to rep_q_f2r "
5778 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5780 "Invalid value passed to rep_q_f2r devargs.\n");
5784 vfr_bp->rep_q_f2r = rep_q_f2r;
5785 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5786 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5792 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5793 const char *value, void *opaque_arg)
5795 struct bnxt_representor *vfr_bp = opaque_arg;
5796 unsigned long rep_fc_r2f;
5799 if (!value || !opaque_arg) {
5801 "Invalid parameter passed to rep_fc_r2f "
5806 rep_fc_r2f = strtoul(value, &end, 10);
5807 if (end == NULL || *end != '\0' ||
5808 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5810 "Invalid parameter passed to rep_fc_r2f "
5815 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5817 "Invalid value passed to rep_fc_r2f devargs.\n");
5821 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5822 vfr_bp->rep_fc_r2f = rep_fc_r2f;
5823 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5829 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5830 const char *value, void *opaque_arg)
5832 struct bnxt_representor *vfr_bp = opaque_arg;
5833 unsigned long rep_fc_f2r;
5836 if (!value || !opaque_arg) {
5838 "Invalid parameter passed to rep_fc_f2r "
5843 rep_fc_f2r = strtoul(value, &end, 10);
5844 if (end == NULL || *end != '\0' ||
5845 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5847 "Invalid parameter passed to rep_fc_f2r "
5852 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5854 "Invalid value passed to rep_fc_f2r devargs.\n");
5858 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5859 vfr_bp->rep_fc_f2r = rep_fc_f2r;
5860 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5866 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5868 struct rte_kvargs *kvlist;
5871 if (devargs == NULL)
5874 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5879 * Handler for "flow_xstat" devarg.
5880 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5882 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5883 bnxt_parse_devarg_flow_xstat, bp);
5888 * Handler for "accum-stats" devarg.
5889 * Invoked as for ex: "-a 0000:00:0d.0,accum-stats=1"
5891 rte_kvargs_process(kvlist, BNXT_DEVARG_ACCUM_STATS,
5892 bnxt_parse_devarg_accum_stats, bp);
5894 * Handler for "max_num_kflows" devarg.
5895 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5897 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5898 bnxt_parse_devarg_max_num_kflows, bp);
5904 * Handler for "app-id" devarg.
5905 * Invoked as for ex: "-a 000:00:0d.0,app-id=1"
5907 rte_kvargs_process(kvlist, BNXT_DEVARG_APP_ID,
5908 bnxt_parse_devarg_app_id, bp);
5910 rte_kvargs_free(kvlist);
5914 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5918 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5919 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5922 "Failed to alloc switch domain: %d\n", rc);
5925 "Switch domain allocated %d\n",
5926 bp->switch_domain_id);
5932 /* Allocate and initialize various fields in bnxt struct that
5933 * need to be allocated/destroyed only once in the lifetime of the driver
5935 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5937 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5938 struct bnxt *bp = eth_dev->data->dev_private;
5941 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5943 if (bnxt_vf_pciid(pci_dev->id.device_id))
5944 bp->flags |= BNXT_FLAG_VF;
5946 if (bnxt_p5_device(pci_dev->id.device_id))
5947 bp->flags |= BNXT_FLAG_CHIP_P5;
5949 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5950 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5951 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5952 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5953 bp->flags |= BNXT_FLAG_STINGRAY;
5955 if (BNXT_TRUFLOW_EN(bp)) {
5956 /* extra mbuf field is required to store CFA code from mark */
5957 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5958 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5959 .size = sizeof(bnxt_cfa_code_dynfield_t),
5960 .align = __alignof__(bnxt_cfa_code_dynfield_t),
5962 bnxt_cfa_code_dynfield_offset =
5963 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5964 if (bnxt_cfa_code_dynfield_offset < 0) {
5966 "Failed to register mbuf field for TruFlow mark\n");
5971 rc = bnxt_map_pci_bars(eth_dev);
5974 "Failed to initialize board rc: %x\n", rc);
5978 rc = bnxt_alloc_pf_info(bp);
5982 rc = bnxt_alloc_link_info(bp);
5986 rc = bnxt_alloc_parent_info(bp);
5990 rc = bnxt_alloc_hwrm_resources(bp);
5993 "Failed to allocate response buffer rc: %x\n", rc);
5996 rc = bnxt_alloc_leds_info(bp);
6000 rc = bnxt_alloc_cos_queues(bp);
6004 rc = bnxt_init_locks(bp);
6008 rc = bnxt_alloc_switch_domain(bp);
6016 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
6018 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
6019 static int version_printed;
6023 if (version_printed++ == 0)
6024 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
6026 eth_dev->dev_ops = &bnxt_dev_ops;
6027 eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
6028 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
6029 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
6030 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
6031 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
6034 * For secondary processes, we don't initialise any further
6035 * as primary has already done this work.
6037 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6040 rte_eth_copy_pci_info(eth_dev, pci_dev);
6041 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
6043 bp = eth_dev->data->dev_private;
6045 /* Parse dev arguments passed on when starting the DPDK application. */
6046 rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
6050 rc = bnxt_drv_init(eth_dev);
6054 rc = bnxt_init_resources(bp, false);
6058 rc = bnxt_alloc_stats_mem(bp);
6063 "Found %s device at mem %" PRIX64 ", node addr %pM\n",
6065 pci_dev->mem_resource[0].phys_addr,
6066 pci_dev->mem_resource[0].addr);
6071 bnxt_dev_uninit(eth_dev);
6076 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
6085 ctx->dma = RTE_BAD_IOVA;
6086 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
6089 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
6091 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
6092 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6093 bp->flow_stat->rx_fc_out_tbl.ctx_id,
6094 bp->flow_stat->max_fc,
6097 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
6098 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6099 bp->flow_stat->tx_fc_out_tbl.ctx_id,
6100 bp->flow_stat->max_fc,
6103 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6104 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
6105 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6107 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6108 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
6109 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6111 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6112 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
6113 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6115 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6116 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
6117 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6120 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
6122 bnxt_unregister_fc_ctx_mem(bp);
6124 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
6125 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
6126 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
6127 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
6130 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
6132 if (BNXT_FLOW_XSTATS_EN(bp))
6133 bnxt_uninit_fc_ctx_mem(bp);
6137 bnxt_free_error_recovery_info(struct bnxt *bp)
6139 rte_free(bp->recovery_info);
6140 bp->recovery_info = NULL;
6141 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
6145 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
6150 bnxt_free_mem(bp, reconfig_dev);
6152 bnxt_hwrm_func_buf_unrgtr(bp);
6153 if (bp->pf != NULL) {
6154 rte_free(bp->pf->vf_req_buf);
6155 bp->pf->vf_req_buf = NULL;
6158 rc = bnxt_hwrm_func_driver_unregister(bp);
6159 bp->flags &= ~BNXT_FLAG_REGISTERED;
6160 bnxt_free_ctx_mem(bp);
6161 if (!reconfig_dev) {
6162 bnxt_free_hwrm_resources(bp);
6163 bnxt_free_error_recovery_info(bp);
6166 bnxt_uninit_ctx_mem(bp);
6168 bnxt_free_flow_stats_info(bp);
6169 if (bp->rep_info != NULL)
6170 bnxt_free_switch_domain(bp);
6171 bnxt_free_rep_info(bp);
6172 rte_free(bp->ptp_cfg);
6178 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
6180 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6183 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
6185 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
6186 bnxt_dev_close_op(eth_dev);
6191 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
6193 struct bnxt *bp = eth_dev->data->dev_private;
6194 struct rte_eth_dev *vf_rep_eth_dev;
6200 for (i = 0; i < bp->num_reps; i++) {
6201 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6202 if (!vf_rep_eth_dev)
6204 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6205 vf_rep_eth_dev->data->port_id);
6206 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6208 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6209 eth_dev->data->port_id);
6210 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6215 static void bnxt_free_rep_info(struct bnxt *bp)
6217 rte_free(bp->rep_info);
6218 bp->rep_info = NULL;
6219 rte_free(bp->cfa_code_map);
6220 bp->cfa_code_map = NULL;
6223 static int bnxt_init_rep_info(struct bnxt *bp)
6230 bp->rep_info = rte_zmalloc("bnxt_rep_info",
6231 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
6233 if (!bp->rep_info) {
6234 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6237 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6238 sizeof(*bp->cfa_code_map) *
6239 BNXT_MAX_CFA_CODE, 0);
6240 if (!bp->cfa_code_map) {
6241 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6242 bnxt_free_rep_info(bp);
6246 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6247 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6249 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6251 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6252 bnxt_free_rep_info(bp);
6256 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6258 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6259 bnxt_free_rep_info(bp);
6266 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6267 struct rte_eth_devargs *eth_da,
6268 struct rte_eth_dev *backing_eth_dev,
6269 const char *dev_args)
6271 struct rte_eth_dev *vf_rep_eth_dev;
6272 char name[RTE_ETH_NAME_MAX_LEN];
6273 struct bnxt *backing_bp;
6276 struct rte_kvargs *kvlist = NULL;
6278 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE)
6280 if (eth_da->type != RTE_ETH_REPRESENTOR_VF) {
6281 PMD_DRV_LOG(ERR, "unsupported representor type %d\n",
6285 num_rep = eth_da->nb_representor_ports;
6286 if (num_rep > BNXT_MAX_VF_REPS) {
6287 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6288 num_rep, BNXT_MAX_VF_REPS);
6292 if (num_rep >= RTE_MAX_ETHPORTS) {
6294 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6295 num_rep, RTE_MAX_ETHPORTS);
6299 backing_bp = backing_eth_dev->data->dev_private;
6301 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6303 "Not a PF or trusted VF. No Representor support\n");
6304 /* Returning an error is not an option.
6305 * Applications are not handling this correctly
6310 if (bnxt_init_rep_info(backing_bp))
6313 for (i = 0; i < num_rep; i++) {
6314 struct bnxt_representor representor = {
6315 .vf_id = eth_da->representor_ports[i],
6316 .switch_domain_id = backing_bp->switch_domain_id,
6317 .parent_dev = backing_eth_dev
6320 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6321 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6322 representor.vf_id, BNXT_MAX_VF_REPS);
6326 /* representor port net_bdf_port */
6327 snprintf(name, sizeof(name), "net_%s_representor_%d",
6328 pci_dev->device.name, eth_da->representor_ports[i]);
6330 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6333 * Handler for "rep_is_pf" devarg.
6334 * Invoked as for ex: "-a 000:00:0d.0,
6335 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6337 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6338 bnxt_parse_devarg_rep_is_pf,
6339 (void *)&representor);
6345 * Handler for "rep_based_pf" devarg.
6346 * Invoked as for ex: "-a 000:00:0d.0,
6347 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6349 ret = rte_kvargs_process(kvlist,
6350 BNXT_DEVARG_REP_BASED_PF,
6351 bnxt_parse_devarg_rep_based_pf,
6352 (void *)&representor);
6358 * Handler for "rep_based_pf" devarg.
6359 * Invoked as for ex: "-a 000:00:0d.0,
6360 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6362 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6363 bnxt_parse_devarg_rep_q_r2f,
6364 (void *)&representor);
6370 * Handler for "rep_based_pf" devarg.
6371 * Invoked as for ex: "-a 000:00:0d.0,
6372 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6374 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6375 bnxt_parse_devarg_rep_q_f2r,
6376 (void *)&representor);
6382 * Handler for "rep_based_pf" devarg.
6383 * Invoked as for ex: "-a 000:00:0d.0,
6384 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6386 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6387 bnxt_parse_devarg_rep_fc_r2f,
6388 (void *)&representor);
6394 * Handler for "rep_based_pf" devarg.
6395 * Invoked as for ex: "-a 000:00:0d.0,
6396 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6398 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6399 bnxt_parse_devarg_rep_fc_f2r,
6400 (void *)&representor);
6407 ret = rte_eth_dev_create(&pci_dev->device, name,
6408 sizeof(struct bnxt_representor),
6410 bnxt_representor_init,
6413 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6414 "representor %s.", name);
6418 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6419 if (!vf_rep_eth_dev) {
6420 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6421 " for VF-Rep: %s.", name);
6426 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6427 backing_eth_dev->data->port_id);
6428 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6430 backing_bp->num_reps++;
6434 rte_kvargs_free(kvlist);
6438 /* If num_rep > 1, then rollback already created
6439 * ports, since we'll be failing the probe anyway
6442 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6444 rte_kvargs_free(kvlist);
6449 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6450 struct rte_pci_device *pci_dev)
6452 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6453 struct rte_eth_dev *backing_eth_dev;
6457 if (pci_dev->device.devargs) {
6458 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6464 num_rep = eth_da.nb_representor_ports;
6465 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6468 /* We could come here after first level of probe is already invoked
6469 * as part of an application bringup(OVS-DPDK vswitchd), so first check
6470 * for already allocated eth_dev for the backing device (PF/Trusted VF)
6472 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6473 if (backing_eth_dev == NULL) {
6474 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6475 sizeof(struct bnxt),
6476 eth_dev_pci_specific_init, pci_dev,
6477 bnxt_dev_init, NULL);
6479 if (ret || !num_rep)
6482 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6484 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6485 backing_eth_dev->data->port_id);
6490 /* probe representor ports now */
6491 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev,
6492 pci_dev->device.devargs->args);
6497 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6499 struct rte_eth_dev *eth_dev;
6501 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6503 return 0; /* Invoked typically only by OVS-DPDK, by the
6504 * time it comes here the eth_dev is already
6505 * deleted by rte_eth_dev_close(), so returning
6506 * +ve value will at least help in proper cleanup
6509 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6510 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6511 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6512 return rte_eth_dev_destroy(eth_dev,
6513 bnxt_representor_uninit);
6515 return rte_eth_dev_destroy(eth_dev,
6518 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6522 static struct rte_pci_driver bnxt_rte_pmd = {
6523 .id_table = bnxt_pci_id_map,
6524 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6525 RTE_PCI_DRV_INTR_RMV |
6526 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6529 .probe = bnxt_pci_probe,
6530 .remove = bnxt_pci_remove,
6534 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6536 if (strcmp(dev->device->driver->name, drv->driver.name))
6542 bool is_bnxt_supported(struct rte_eth_dev *dev)
6544 return is_device_supported(dev, &bnxt_rte_pmd);
6547 RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE);
6548 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6549 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);