1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
18 #include "bnxt_filter.h"
19 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_stats.h"
27 #include "bnxt_vnic.h"
28 #include "hsi_struct_def_dpdk.h"
29 #include "bnxt_nvm_defs.h"
30 #include "bnxt_util.h"
32 #define DRV_MODULE_NAME "bnxt"
33 static const char bnxt_version[] =
34 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
35 int bnxt_logtype_driver;
37 #define PCI_VENDOR_ID_BROADCOM 0x14E4
39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
40 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
41 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
42 #define BROADCOM_DEV_ID_57414_VF 0x16c1
43 #define BROADCOM_DEV_ID_57301 0x16c8
44 #define BROADCOM_DEV_ID_57302 0x16c9
45 #define BROADCOM_DEV_ID_57304_PF 0x16ca
46 #define BROADCOM_DEV_ID_57304_VF 0x16cb
47 #define BROADCOM_DEV_ID_57417_MF 0x16cc
48 #define BROADCOM_DEV_ID_NS2 0x16cd
49 #define BROADCOM_DEV_ID_57311 0x16ce
50 #define BROADCOM_DEV_ID_57312 0x16cf
51 #define BROADCOM_DEV_ID_57402 0x16d0
52 #define BROADCOM_DEV_ID_57404 0x16d1
53 #define BROADCOM_DEV_ID_57406_PF 0x16d2
54 #define BROADCOM_DEV_ID_57406_VF 0x16d3
55 #define BROADCOM_DEV_ID_57402_MF 0x16d4
56 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
57 #define BROADCOM_DEV_ID_57412 0x16d6
58 #define BROADCOM_DEV_ID_57414 0x16d7
59 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
60 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
61 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
62 #define BROADCOM_DEV_ID_57412_MF 0x16de
63 #define BROADCOM_DEV_ID_57314 0x16df
64 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
65 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
66 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
67 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
68 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
69 #define BROADCOM_DEV_ID_57404_MF 0x16e7
70 #define BROADCOM_DEV_ID_57406_MF 0x16e8
71 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
72 #define BROADCOM_DEV_ID_57407_MF 0x16ea
73 #define BROADCOM_DEV_ID_57414_MF 0x16ec
74 #define BROADCOM_DEV_ID_57416_MF 0x16ee
75 #define BROADCOM_DEV_ID_57508 0x1750
76 #define BROADCOM_DEV_ID_57504 0x1751
77 #define BROADCOM_DEV_ID_57502 0x1752
78 #define BROADCOM_DEV_ID_57500_VF1 0x1806
79 #define BROADCOM_DEV_ID_57500_VF2 0x1807
80 #define BROADCOM_DEV_ID_58802 0xd802
81 #define BROADCOM_DEV_ID_58804 0xd804
82 #define BROADCOM_DEV_ID_58808 0x16f0
83 #define BROADCOM_DEV_ID_58802_VF 0xd800
85 static const struct rte_pci_id bnxt_pci_id_map[] = {
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
87 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
89 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
130 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
131 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
132 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
133 { .vendor_id = 0, /* sentinel */ },
136 #define BNXT_ETH_RSS_SUPPORT ( \
138 ETH_RSS_NONFRAG_IPV4_TCP | \
139 ETH_RSS_NONFRAG_IPV4_UDP | \
141 ETH_RSS_NONFRAG_IPV6_TCP | \
142 ETH_RSS_NONFRAG_IPV6_UDP)
144 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
145 DEV_TX_OFFLOAD_IPV4_CKSUM | \
146 DEV_TX_OFFLOAD_TCP_CKSUM | \
147 DEV_TX_OFFLOAD_UDP_CKSUM | \
148 DEV_TX_OFFLOAD_TCP_TSO | \
149 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
150 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
151 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
152 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
153 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
154 DEV_TX_OFFLOAD_QINQ_INSERT | \
155 DEV_TX_OFFLOAD_MULTI_SEGS)
157 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
158 DEV_RX_OFFLOAD_VLAN_STRIP | \
159 DEV_RX_OFFLOAD_IPV4_CKSUM | \
160 DEV_RX_OFFLOAD_UDP_CKSUM | \
161 DEV_RX_OFFLOAD_TCP_CKSUM | \
162 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
163 DEV_RX_OFFLOAD_JUMBO_FRAME | \
164 DEV_RX_OFFLOAD_KEEP_CRC | \
165 DEV_RX_OFFLOAD_VLAN_EXTEND | \
166 DEV_RX_OFFLOAD_TCP_LRO | \
167 DEV_RX_OFFLOAD_SCATTER)
169 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
170 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
171 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
172 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
173 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
174 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
175 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
177 int is_bnxt_in_error(struct bnxt *bp)
179 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
181 if (bp->flags & BNXT_FLAG_FW_RESET)
187 /***********************/
190 * High level utility functions
193 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
195 if (!BNXT_CHIP_THOR(bp))
198 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
199 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
200 BNXT_RSS_ENTRIES_PER_CTX_THOR;
203 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
205 if (!BNXT_CHIP_THOR(bp))
206 return HW_HASH_INDEX_SIZE;
208 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
211 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
213 bnxt_free_filter_mem(bp);
214 bnxt_free_vnic_attributes(bp);
215 bnxt_free_vnic_mem(bp);
217 /* tx/rx rings are configured as part of *_queue_setup callbacks.
218 * If the number of rings change across fw update,
219 * we don't have much choice except to warn the user.
223 bnxt_free_tx_rings(bp);
224 bnxt_free_rx_rings(bp);
226 bnxt_free_async_cp_ring(bp);
227 bnxt_free_rxtx_nq_ring(bp);
230 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
234 rc = bnxt_alloc_ring_grps(bp);
238 rc = bnxt_alloc_async_ring_struct(bp);
242 rc = bnxt_alloc_vnic_mem(bp);
246 rc = bnxt_alloc_vnic_attributes(bp);
250 rc = bnxt_alloc_filter_mem(bp);
254 rc = bnxt_alloc_async_cp_ring(bp);
258 rc = bnxt_alloc_rxtx_nq_ring(bp);
265 bnxt_free_mem(bp, reconfig);
269 static int bnxt_init_chip(struct bnxt *bp)
271 struct bnxt_rx_queue *rxq;
272 struct rte_eth_link new;
273 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
274 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
275 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
276 uint64_t rx_offloads = dev_conf->rxmode.offloads;
277 uint32_t intr_vector = 0;
278 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
279 uint32_t vec = BNXT_MISC_VEC_ID;
283 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
284 bp->eth_dev->data->dev_conf.rxmode.offloads |=
285 DEV_RX_OFFLOAD_JUMBO_FRAME;
286 bp->flags |= BNXT_FLAG_JUMBO;
288 bp->eth_dev->data->dev_conf.rxmode.offloads &=
289 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
290 bp->flags &= ~BNXT_FLAG_JUMBO;
293 /* THOR does not support ring groups.
294 * But we will use the array to save RSS context IDs.
296 if (BNXT_CHIP_THOR(bp))
297 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
299 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
301 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
305 rc = bnxt_alloc_hwrm_rings(bp);
307 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
311 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
313 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
317 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
320 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
321 if (bp->rx_cos_queue[i].id != 0xff) {
322 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
326 "Num pools more than FW profile\n");
330 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
336 rc = bnxt_mq_rx_configure(bp);
338 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
342 /* VNIC configuration */
343 for (i = 0; i < bp->nr_vnics; i++) {
344 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
345 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
347 rc = bnxt_vnic_grp_alloc(bp, vnic);
351 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
352 i, vnic, vnic->fw_grp_ids);
354 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
356 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
361 /* Alloc RSS context only if RSS mode is enabled */
362 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
363 int j, nr_ctxs = bnxt_rss_ctxts(bp);
366 for (j = 0; j < nr_ctxs; j++) {
367 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
373 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
377 vnic->num_lb_ctxts = nr_ctxs;
381 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
382 * setting is not available at this time, it will not be
383 * configured correctly in the CFA.
385 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
386 vnic->vlan_strip = true;
388 vnic->vlan_strip = false;
390 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
392 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
397 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
400 "HWRM vnic %d filter failure rc: %x\n",
405 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
406 rxq = bp->eth_dev->data->rx_queues[j];
409 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
410 j, rxq->vnic, rxq->vnic->fw_grp_ids);
412 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
413 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
416 rc = bnxt_vnic_rss_configure(bp, vnic);
419 "HWRM vnic set RSS failure rc: %x\n", rc);
423 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
425 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
426 DEV_RX_OFFLOAD_TCP_LRO)
427 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
429 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
431 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
434 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
438 /* check and configure queue intr-vector mapping */
439 if ((rte_intr_cap_multiple(intr_handle) ||
440 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
441 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
442 intr_vector = bp->eth_dev->data->nb_rx_queues;
443 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
444 if (intr_vector > bp->rx_cp_nr_rings) {
445 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
449 rc = rte_intr_efd_enable(intr_handle, intr_vector);
454 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
455 intr_handle->intr_vec =
456 rte_zmalloc("intr_vec",
457 bp->eth_dev->data->nb_rx_queues *
459 if (intr_handle->intr_vec == NULL) {
460 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
461 " intr_vec", bp->eth_dev->data->nb_rx_queues);
465 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
466 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
467 intr_handle->intr_vec, intr_handle->nb_efd,
468 intr_handle->max_intr);
469 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
471 intr_handle->intr_vec[queue_id] =
472 vec + BNXT_RX_VEC_START;
473 if (vec < base + intr_handle->nb_efd - 1)
478 /* enable uio/vfio intr/eventfd mapping */
479 rc = rte_intr_enable(intr_handle);
483 rc = bnxt_get_hwrm_link_config(bp, &new);
485 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
489 if (!bp->link_info.link_up) {
490 rc = bnxt_set_hwrm_link_config(bp, true);
493 "HWRM link config failure rc: %x\n", rc);
497 bnxt_print_link_info(bp->eth_dev);
502 rte_free(intr_handle->intr_vec);
504 rte_intr_efd_disable(intr_handle);
506 /* Some of the error status returned by FW may not be from errno.h */
513 static int bnxt_shutdown_nic(struct bnxt *bp)
515 bnxt_free_all_hwrm_resources(bp);
516 bnxt_free_all_filters(bp);
517 bnxt_free_all_vnics(bp);
521 static int bnxt_init_nic(struct bnxt *bp)
525 if (BNXT_HAS_RING_GRPS(bp)) {
526 rc = bnxt_init_ring_grps(bp);
532 bnxt_init_filters(bp);
538 * Device configuration and status function
541 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
542 struct rte_eth_dev_info *dev_info)
544 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
545 struct bnxt *bp = eth_dev->data->dev_private;
546 uint16_t max_vnics, i, j, vpool, vrxq;
547 unsigned int max_rx_rings;
550 rc = is_bnxt_in_error(bp);
555 dev_info->max_mac_addrs = bp->max_l2_ctx;
556 dev_info->max_hash_mac_addrs = 0;
558 /* PF/VF specifics */
560 dev_info->max_vfs = pdev->max_vfs;
562 max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
563 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
564 dev_info->max_rx_queues = max_rx_rings;
565 dev_info->max_tx_queues = max_rx_rings;
566 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
567 dev_info->hash_key_size = 40;
568 max_vnics = bp->max_vnics;
571 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
572 dev_info->max_mtu = BNXT_MAX_MTU;
574 /* Fast path specifics */
575 dev_info->min_rx_bufsize = 1;
576 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
578 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
579 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
580 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
581 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
582 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
585 dev_info->default_rxconf = (struct rte_eth_rxconf) {
591 .rx_free_thresh = 32,
592 /* If no descriptors available, pkts are dropped by default */
596 dev_info->default_txconf = (struct rte_eth_txconf) {
602 .tx_free_thresh = 32,
605 eth_dev->data->dev_conf.intr_conf.lsc = 1;
607 eth_dev->data->dev_conf.intr_conf.rxq = 1;
608 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
609 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
610 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
611 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
616 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
617 * need further investigation.
621 vpool = 64; /* ETH_64_POOLS */
622 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
623 for (i = 0; i < 4; vpool >>= 1, i++) {
624 if (max_vnics > vpool) {
625 for (j = 0; j < 5; vrxq >>= 1, j++) {
626 if (dev_info->max_rx_queues > vrxq) {
632 /* Not enough resources to support VMDq */
636 /* Not enough resources to support VMDq */
640 dev_info->max_vmdq_pools = vpool;
641 dev_info->vmdq_queue_num = vrxq;
643 dev_info->vmdq_pool_base = 0;
644 dev_info->vmdq_queue_base = 0;
649 /* Configure the device based on the configuration provided */
650 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
652 struct bnxt *bp = eth_dev->data->dev_private;
653 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
656 bp->rx_queues = (void *)eth_dev->data->rx_queues;
657 bp->tx_queues = (void *)eth_dev->data->tx_queues;
658 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
659 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
661 rc = is_bnxt_in_error(bp);
665 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
666 rc = bnxt_hwrm_check_vf_rings(bp);
668 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
672 /* If a resource has already been allocated - in this case
673 * it is the async completion ring, free it. Reallocate it after
674 * resource reservation. This will ensure the resource counts
675 * are calculated correctly.
677 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
678 bnxt_disable_int(bp);
679 bnxt_free_cp_ring(bp, bp->async_cp_ring);
682 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
684 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
688 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
689 rc = bnxt_alloc_async_cp_ring(bp);
695 /* legacy driver needs to get updated values */
696 rc = bnxt_hwrm_func_qcaps(bp);
698 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
703 /* Inherit new configurations */
704 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
705 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
706 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
707 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
708 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
712 if (BNXT_HAS_RING_GRPS(bp) &&
713 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
716 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
717 bp->max_vnics < eth_dev->data->nb_rx_queues)
720 bp->rx_cp_nr_rings = bp->rx_nr_rings;
721 bp->tx_cp_nr_rings = bp->tx_nr_rings;
723 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
725 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
726 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
728 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
734 "Insufficient resources to support requested config\n");
736 "Num Queues Requested: Tx %d, Rx %d\n",
737 eth_dev->data->nb_tx_queues,
738 eth_dev->data->nb_rx_queues);
740 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
741 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
742 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
746 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
748 struct rte_eth_link *link = ð_dev->data->dev_link;
750 if (link->link_status)
751 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
752 eth_dev->data->port_id,
753 (uint32_t)link->link_speed,
754 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
755 ("full-duplex") : ("half-duplex\n"));
757 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
758 eth_dev->data->port_id);
762 * Determine whether the current configuration requires support for scattered
763 * receive; return 1 if scattered receive is required and 0 if not.
765 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
770 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
773 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
774 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
776 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
777 RTE_PKTMBUF_HEADROOM);
778 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
784 static eth_rx_burst_t
785 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
788 #ifndef RTE_LIBRTE_IEEE1588
790 * Vector mode receive can be enabled only if scatter rx is not
791 * in use and rx offloads are limited to VLAN stripping and
794 if (!eth_dev->data->scattered_rx &&
795 !(eth_dev->data->dev_conf.rxmode.offloads &
796 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
797 DEV_RX_OFFLOAD_KEEP_CRC |
798 DEV_RX_OFFLOAD_JUMBO_FRAME |
799 DEV_RX_OFFLOAD_IPV4_CKSUM |
800 DEV_RX_OFFLOAD_UDP_CKSUM |
801 DEV_RX_OFFLOAD_TCP_CKSUM |
802 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
803 DEV_RX_OFFLOAD_VLAN_FILTER))) {
804 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
805 eth_dev->data->port_id);
806 return bnxt_recv_pkts_vec;
808 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
809 eth_dev->data->port_id);
811 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
812 eth_dev->data->port_id,
813 eth_dev->data->scattered_rx,
814 eth_dev->data->dev_conf.rxmode.offloads);
817 return bnxt_recv_pkts;
820 static eth_tx_burst_t
821 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
824 #ifndef RTE_LIBRTE_IEEE1588
826 * Vector mode transmit can be enabled only if not using scatter rx
829 if (!eth_dev->data->scattered_rx &&
830 !eth_dev->data->dev_conf.txmode.offloads) {
831 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
832 eth_dev->data->port_id);
833 return bnxt_xmit_pkts_vec;
835 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
836 eth_dev->data->port_id);
838 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
839 eth_dev->data->port_id,
840 eth_dev->data->scattered_rx,
841 eth_dev->data->dev_conf.txmode.offloads);
844 return bnxt_xmit_pkts;
847 static int bnxt_handle_if_change_status(struct bnxt *bp)
851 /* Since fw has undergone a reset and lost all contexts,
852 * set fatal flag to not issue hwrm during cleanup
854 bp->flags |= BNXT_FLAG_FATAL_ERROR;
855 bnxt_uninit_resources(bp, true);
857 /* clear fatal flag so that re-init happens */
858 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
859 rc = bnxt_init_resources(bp, true);
861 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
866 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
868 struct bnxt *bp = eth_dev->data->dev_private;
869 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
873 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
875 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
876 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
880 rc = bnxt_hwrm_if_change(bp, 1);
882 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
883 rc = bnxt_handle_if_change_status(bp);
889 rc = bnxt_init_chip(bp);
893 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
895 bnxt_link_update_op(eth_dev, 1);
897 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
898 vlan_mask |= ETH_VLAN_FILTER_MASK;
899 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
900 vlan_mask |= ETH_VLAN_STRIP_MASK;
901 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
905 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
906 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
908 bp->flags |= BNXT_FLAG_INIT_DONE;
909 eth_dev->data->dev_started = 1;
911 bnxt_schedule_fw_health_check(bp);
915 bnxt_hwrm_if_change(bp, 0);
916 bnxt_shutdown_nic(bp);
917 bnxt_free_tx_mbufs(bp);
918 bnxt_free_rx_mbufs(bp);
922 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
924 struct bnxt *bp = eth_dev->data->dev_private;
927 if (!bp->link_info.link_up)
928 rc = bnxt_set_hwrm_link_config(bp, true);
930 eth_dev->data->dev_link.link_status = 1;
932 bnxt_print_link_info(eth_dev);
936 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
938 struct bnxt *bp = eth_dev->data->dev_private;
940 eth_dev->data->dev_link.link_status = 0;
941 bnxt_set_hwrm_link_config(bp, false);
942 bp->link_info.link_up = 0;
947 /* Unload the driver, release resources */
948 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
950 struct bnxt *bp = eth_dev->data->dev_private;
951 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
952 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
954 eth_dev->data->dev_started = 0;
955 /* Prevent crashes when queues are still in use */
956 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
957 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
959 bnxt_disable_int(bp);
961 /* disable uio/vfio intr/eventfd mapping */
962 rte_intr_disable(intr_handle);
964 bnxt_cancel_fw_health_check(bp);
966 bp->flags &= ~BNXT_FLAG_INIT_DONE;
967 if (bp->eth_dev->data->dev_started) {
968 /* TBD: STOP HW queues DMA */
969 eth_dev->data->dev_link.link_status = 0;
971 bnxt_dev_set_link_down_op(eth_dev);
972 /* Wait for link to be reset and the async notification to process. */
973 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
975 /* Clean queue intr-vector mapping */
976 rte_intr_efd_disable(intr_handle);
977 if (intr_handle->intr_vec != NULL) {
978 rte_free(intr_handle->intr_vec);
979 intr_handle->intr_vec = NULL;
982 bnxt_hwrm_port_clr_stats(bp);
983 bnxt_free_tx_mbufs(bp);
984 bnxt_free_rx_mbufs(bp);
985 /* Process any remaining notifications in default completion queue */
986 bnxt_int_handler(eth_dev);
987 bnxt_shutdown_nic(bp);
988 bnxt_hwrm_if_change(bp, 0);
992 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
994 struct bnxt *bp = eth_dev->data->dev_private;
996 if (bp->dev_stopped == 0)
997 bnxt_dev_stop_op(eth_dev);
999 if (eth_dev->data->mac_addrs != NULL) {
1000 rte_free(eth_dev->data->mac_addrs);
1001 eth_dev->data->mac_addrs = NULL;
1003 if (bp->grp_info != NULL) {
1004 rte_free(bp->grp_info);
1005 bp->grp_info = NULL;
1008 bnxt_dev_uninit(eth_dev);
1011 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1014 struct bnxt *bp = eth_dev->data->dev_private;
1015 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1016 struct bnxt_vnic_info *vnic;
1017 struct bnxt_filter_info *filter, *temp_filter;
1020 if (is_bnxt_in_error(bp))
1024 * Loop through all VNICs from the specified filter flow pools to
1025 * remove the corresponding MAC addr filter
1027 for (i = 0; i < bp->nr_vnics; i++) {
1028 if (!(pool_mask & (1ULL << i)))
1031 vnic = &bp->vnic_info[i];
1032 filter = STAILQ_FIRST(&vnic->filter);
1034 temp_filter = STAILQ_NEXT(filter, next);
1035 if (filter->mac_index == index) {
1036 STAILQ_REMOVE(&vnic->filter, filter,
1037 bnxt_filter_info, next);
1038 bnxt_hwrm_clear_l2_filter(bp, filter);
1039 filter->mac_index = INVALID_MAC_INDEX;
1040 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1041 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1044 filter = temp_filter;
1049 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1050 struct rte_ether_addr *mac_addr, uint32_t index)
1052 struct bnxt_filter_info *filter;
1055 filter = STAILQ_FIRST(&vnic->filter);
1056 /* During bnxt_mac_addr_add_op, default MAC is
1057 * already programmed, so skip it. But, when
1058 * hw-vlan-filter is turned OFF from ON, default
1059 * MAC filter should be restored
1064 filter = bnxt_alloc_filter(bp);
1066 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1070 filter->mac_index = index;
1071 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1072 * if the MAC that's been programmed now is a different one, then,
1073 * copy that addr to filter->l2_addr
1076 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1077 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1079 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1081 if (filter->mac_index == 0) {
1082 filter->dflt = true;
1083 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1085 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1088 filter->mac_index = INVALID_MAC_INDEX;
1089 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1090 bnxt_free_filter(bp, filter);
1096 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1097 struct rte_ether_addr *mac_addr,
1098 uint32_t index, uint32_t pool)
1100 struct bnxt *bp = eth_dev->data->dev_private;
1101 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1102 struct bnxt_filter_info *filter;
1105 rc = is_bnxt_in_error(bp);
1109 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1110 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1115 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1118 /* Attach requested MAC address to the new l2_filter */
1119 STAILQ_FOREACH(filter, &vnic->filter, next) {
1120 if (filter->mac_index == index) {
1122 "MAC addr already existed for pool %d\n", pool);
1127 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index);
1132 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1135 struct bnxt *bp = eth_dev->data->dev_private;
1136 struct rte_eth_link new;
1137 unsigned int cnt = BNXT_LINK_WAIT_CNT;
1139 rc = is_bnxt_in_error(bp);
1143 memset(&new, 0, sizeof(new));
1145 /* Retrieve link info from hardware */
1146 rc = bnxt_get_hwrm_link_config(bp, &new);
1148 new.link_speed = ETH_LINK_SPEED_100M;
1149 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1151 "Failed to retrieve link rc = 0x%x!\n", rc);
1155 if (!wait_to_complete || new.link_status)
1158 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1162 /* Timed out or success */
1163 if (new.link_status != eth_dev->data->dev_link.link_status ||
1164 new.link_speed != eth_dev->data->dev_link.link_speed) {
1165 rte_eth_linkstatus_set(eth_dev, &new);
1167 _rte_eth_dev_callback_process(eth_dev,
1168 RTE_ETH_EVENT_INTR_LSC,
1171 bnxt_print_link_info(eth_dev);
1177 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1179 struct bnxt *bp = eth_dev->data->dev_private;
1180 struct bnxt_vnic_info *vnic;
1184 rc = is_bnxt_in_error(bp);
1188 if (bp->vnic_info == NULL)
1191 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1193 old_flags = vnic->flags;
1194 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1195 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1197 vnic->flags = old_flags;
1202 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1204 struct bnxt *bp = eth_dev->data->dev_private;
1205 struct bnxt_vnic_info *vnic;
1209 rc = is_bnxt_in_error(bp);
1213 if (bp->vnic_info == NULL)
1216 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1218 old_flags = vnic->flags;
1219 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1220 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1222 vnic->flags = old_flags;
1227 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1229 struct bnxt *bp = eth_dev->data->dev_private;
1230 struct bnxt_vnic_info *vnic;
1234 rc = is_bnxt_in_error(bp);
1238 if (bp->vnic_info == NULL)
1241 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1243 old_flags = vnic->flags;
1244 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1245 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1247 vnic->flags = old_flags;
1252 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1254 struct bnxt *bp = eth_dev->data->dev_private;
1255 struct bnxt_vnic_info *vnic;
1259 rc = is_bnxt_in_error(bp);
1263 if (bp->vnic_info == NULL)
1266 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1268 old_flags = vnic->flags;
1269 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1270 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1272 vnic->flags = old_flags;
1277 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1278 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1280 if (qid >= bp->rx_nr_rings)
1283 return bp->eth_dev->data->rx_queues[qid];
1286 /* Return rxq corresponding to a given rss table ring/group ID. */
1287 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1289 struct bnxt_rx_queue *rxq;
1292 if (!BNXT_HAS_RING_GRPS(bp)) {
1293 for (i = 0; i < bp->rx_nr_rings; i++) {
1294 rxq = bp->eth_dev->data->rx_queues[i];
1295 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1299 for (i = 0; i < bp->rx_nr_rings; i++) {
1300 if (bp->grp_info[i].fw_grp_id == fwr)
1305 return INVALID_HW_RING_ID;
1308 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1309 struct rte_eth_rss_reta_entry64 *reta_conf,
1312 struct bnxt *bp = eth_dev->data->dev_private;
1313 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1314 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1315 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1319 rc = is_bnxt_in_error(bp);
1323 if (!vnic->rss_table)
1326 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1329 if (reta_size != tbl_size) {
1330 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1331 "(%d) must equal the size supported by the hardware "
1332 "(%d)\n", reta_size, tbl_size);
1336 for (i = 0; i < reta_size; i++) {
1337 struct bnxt_rx_queue *rxq;
1339 idx = i / RTE_RETA_GROUP_SIZE;
1340 sft = i % RTE_RETA_GROUP_SIZE;
1342 if (!(reta_conf[idx].mask & (1ULL << sft)))
1345 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1347 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1351 if (BNXT_CHIP_THOR(bp)) {
1352 vnic->rss_table[i * 2] =
1353 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1354 vnic->rss_table[i * 2 + 1] =
1355 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1357 vnic->rss_table[i] =
1358 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1361 vnic->rss_table[i] =
1362 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1365 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1369 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1370 struct rte_eth_rss_reta_entry64 *reta_conf,
1373 struct bnxt *bp = eth_dev->data->dev_private;
1374 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1375 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1376 uint16_t idx, sft, i;
1379 rc = is_bnxt_in_error(bp);
1383 /* Retrieve from the default VNIC */
1386 if (!vnic->rss_table)
1389 if (reta_size != tbl_size) {
1390 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1391 "(%d) must equal the size supported by the hardware "
1392 "(%d)\n", reta_size, tbl_size);
1396 for (idx = 0, i = 0; i < reta_size; i++) {
1397 idx = i / RTE_RETA_GROUP_SIZE;
1398 sft = i % RTE_RETA_GROUP_SIZE;
1400 if (reta_conf[idx].mask & (1ULL << sft)) {
1403 if (BNXT_CHIP_THOR(bp))
1404 qid = bnxt_rss_to_qid(bp,
1405 vnic->rss_table[i * 2]);
1407 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1409 if (qid == INVALID_HW_RING_ID) {
1410 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1413 reta_conf[idx].reta[sft] = qid;
1420 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1421 struct rte_eth_rss_conf *rss_conf)
1423 struct bnxt *bp = eth_dev->data->dev_private;
1424 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1425 struct bnxt_vnic_info *vnic;
1428 rc = is_bnxt_in_error(bp);
1433 * If RSS enablement were different than dev_configure,
1434 * then return -EINVAL
1436 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1437 if (!rss_conf->rss_hf)
1438 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1440 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1444 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1445 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1447 /* Update the default RSS VNIC(s) */
1448 vnic = &bp->vnic_info[0];
1449 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1452 * If hashkey is not specified, use the previously configured
1455 if (!rss_conf->rss_key)
1458 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1460 "Invalid hashkey length, should be 16 bytes\n");
1463 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1466 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1470 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1471 struct rte_eth_rss_conf *rss_conf)
1473 struct bnxt *bp = eth_dev->data->dev_private;
1474 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1476 uint32_t hash_types;
1478 rc = is_bnxt_in_error(bp);
1482 /* RSS configuration is the same for all VNICs */
1483 if (vnic && vnic->rss_hash_key) {
1484 if (rss_conf->rss_key) {
1485 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1486 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1487 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1490 hash_types = vnic->hash_type;
1491 rss_conf->rss_hf = 0;
1492 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1493 rss_conf->rss_hf |= ETH_RSS_IPV4;
1494 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1496 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1497 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1499 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1501 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1502 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1504 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1506 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1507 rss_conf->rss_hf |= ETH_RSS_IPV6;
1508 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1510 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1511 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1513 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1515 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1516 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1518 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1522 "Unknwon RSS config from firmware (%08x), RSS disabled",
1527 rss_conf->rss_hf = 0;
1532 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1533 struct rte_eth_fc_conf *fc_conf)
1535 struct bnxt *bp = dev->data->dev_private;
1536 struct rte_eth_link link_info;
1539 rc = is_bnxt_in_error(bp);
1543 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1547 memset(fc_conf, 0, sizeof(*fc_conf));
1548 if (bp->link_info.auto_pause)
1549 fc_conf->autoneg = 1;
1550 switch (bp->link_info.pause) {
1552 fc_conf->mode = RTE_FC_NONE;
1554 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1555 fc_conf->mode = RTE_FC_TX_PAUSE;
1557 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1558 fc_conf->mode = RTE_FC_RX_PAUSE;
1560 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1561 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1562 fc_conf->mode = RTE_FC_FULL;
1568 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1569 struct rte_eth_fc_conf *fc_conf)
1571 struct bnxt *bp = dev->data->dev_private;
1574 rc = is_bnxt_in_error(bp);
1578 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1579 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1583 switch (fc_conf->mode) {
1585 bp->link_info.auto_pause = 0;
1586 bp->link_info.force_pause = 0;
1588 case RTE_FC_RX_PAUSE:
1589 if (fc_conf->autoneg) {
1590 bp->link_info.auto_pause =
1591 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1592 bp->link_info.force_pause = 0;
1594 bp->link_info.auto_pause = 0;
1595 bp->link_info.force_pause =
1596 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1599 case RTE_FC_TX_PAUSE:
1600 if (fc_conf->autoneg) {
1601 bp->link_info.auto_pause =
1602 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1603 bp->link_info.force_pause = 0;
1605 bp->link_info.auto_pause = 0;
1606 bp->link_info.force_pause =
1607 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1611 if (fc_conf->autoneg) {
1612 bp->link_info.auto_pause =
1613 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1614 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1615 bp->link_info.force_pause = 0;
1617 bp->link_info.auto_pause = 0;
1618 bp->link_info.force_pause =
1619 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1620 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1624 return bnxt_set_hwrm_link_config(bp, true);
1627 /* Add UDP tunneling port */
1629 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1630 struct rte_eth_udp_tunnel *udp_tunnel)
1632 struct bnxt *bp = eth_dev->data->dev_private;
1633 uint16_t tunnel_type = 0;
1636 rc = is_bnxt_in_error(bp);
1640 switch (udp_tunnel->prot_type) {
1641 case RTE_TUNNEL_TYPE_VXLAN:
1642 if (bp->vxlan_port_cnt) {
1643 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1644 udp_tunnel->udp_port);
1645 if (bp->vxlan_port != udp_tunnel->udp_port) {
1646 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1649 bp->vxlan_port_cnt++;
1653 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1654 bp->vxlan_port_cnt++;
1656 case RTE_TUNNEL_TYPE_GENEVE:
1657 if (bp->geneve_port_cnt) {
1658 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1659 udp_tunnel->udp_port);
1660 if (bp->geneve_port != udp_tunnel->udp_port) {
1661 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1664 bp->geneve_port_cnt++;
1668 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1669 bp->geneve_port_cnt++;
1672 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1675 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1681 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1682 struct rte_eth_udp_tunnel *udp_tunnel)
1684 struct bnxt *bp = eth_dev->data->dev_private;
1685 uint16_t tunnel_type = 0;
1689 rc = is_bnxt_in_error(bp);
1693 switch (udp_tunnel->prot_type) {
1694 case RTE_TUNNEL_TYPE_VXLAN:
1695 if (!bp->vxlan_port_cnt) {
1696 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1699 if (bp->vxlan_port != udp_tunnel->udp_port) {
1700 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1701 udp_tunnel->udp_port, bp->vxlan_port);
1704 if (--bp->vxlan_port_cnt)
1708 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1709 port = bp->vxlan_fw_dst_port_id;
1711 case RTE_TUNNEL_TYPE_GENEVE:
1712 if (!bp->geneve_port_cnt) {
1713 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1716 if (bp->geneve_port != udp_tunnel->udp_port) {
1717 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1718 udp_tunnel->udp_port, bp->geneve_port);
1721 if (--bp->geneve_port_cnt)
1725 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1726 port = bp->geneve_fw_dst_port_id;
1729 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1733 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1736 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1739 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1740 bp->geneve_port = 0;
1745 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1747 struct bnxt_filter_info *filter;
1748 struct bnxt_vnic_info *vnic;
1750 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1752 /* if VLAN exists && VLAN matches vlan_id
1753 * remove the MAC+VLAN filter
1754 * add a new MAC only filter
1756 * VLAN filter doesn't exist, just skip and continue
1758 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1759 filter = STAILQ_FIRST(&vnic->filter);
1761 /* Search for this matching MAC+VLAN filter */
1762 if ((filter->enables & chk) &&
1763 (filter->l2_ivlan == vlan_id &&
1764 filter->l2_ivlan_mask != 0) &&
1765 !memcmp(filter->l2_addr, bp->mac_addr,
1766 RTE_ETHER_ADDR_LEN)) {
1767 /* Delete the filter */
1768 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1771 STAILQ_REMOVE(&vnic->filter, filter,
1772 bnxt_filter_info, next);
1773 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1776 "Del Vlan filter for %d\n",
1780 filter = STAILQ_NEXT(filter, next);
1785 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1787 struct bnxt_filter_info *filter;
1788 struct bnxt_vnic_info *vnic;
1790 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1791 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1792 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1794 /* Implementation notes on the use of VNIC in this command:
1796 * By default, these filters belong to default vnic for the function.
1797 * Once these filters are set up, only destination VNIC can be modified.
1798 * If the destination VNIC is not specified in this command,
1799 * then the HWRM shall only create an l2 context id.
1802 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1803 filter = STAILQ_FIRST(&vnic->filter);
1804 /* Check if the VLAN has already been added */
1806 if ((filter->enables & chk) &&
1807 (filter->l2_ivlan == vlan_id &&
1808 filter->l2_ivlan_mask == 0x0FFF) &&
1809 !memcmp(filter->l2_addr, bp->mac_addr,
1810 RTE_ETHER_ADDR_LEN))
1813 filter = STAILQ_NEXT(filter, next);
1816 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1817 * command to create MAC+VLAN filter with the right flags, enables set.
1819 filter = bnxt_alloc_filter(bp);
1822 "MAC/VLAN filter alloc failed\n");
1825 /* MAC + VLAN ID filter */
1826 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1827 * untagged packets are received
1829 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1830 * packets and only the programmed vlan's packets are received
1832 filter->l2_ivlan = vlan_id;
1833 filter->l2_ivlan_mask = 0x0FFF;
1834 filter->enables |= en;
1835 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1837 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1839 /* Free the newly allocated filter as we were
1840 * not able to create the filter in hardware.
1842 filter->fw_l2_filter_id = UINT64_MAX;
1843 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1846 /* Add this new filter to the list */
1848 filter->dflt = true;
1849 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1851 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1856 "Added Vlan filter for %d\n", vlan_id);
1860 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1861 uint16_t vlan_id, int on)
1863 struct bnxt *bp = eth_dev->data->dev_private;
1866 rc = is_bnxt_in_error(bp);
1870 /* These operations apply to ALL existing MAC/VLAN filters */
1872 return bnxt_add_vlan_filter(bp, vlan_id);
1874 return bnxt_del_vlan_filter(bp, vlan_id);
1877 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1878 struct bnxt_vnic_info *vnic)
1880 struct bnxt_filter_info *filter;
1883 filter = STAILQ_FIRST(&vnic->filter);
1886 !memcmp(filter->l2_addr, bp->mac_addr,
1887 RTE_ETHER_ADDR_LEN)) {
1888 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1891 filter->dflt = false;
1892 STAILQ_REMOVE(&vnic->filter, filter,
1893 bnxt_filter_info, next);
1894 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1896 filter->fw_l2_filter_id = -1;
1899 filter = STAILQ_NEXT(filter, next);
1905 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1907 struct bnxt *bp = dev->data->dev_private;
1908 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1909 struct bnxt_vnic_info *vnic;
1913 rc = is_bnxt_in_error(bp);
1917 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1918 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1919 /* Remove any VLAN filters programmed */
1920 for (i = 0; i < 4095; i++)
1921 bnxt_del_vlan_filter(bp, i);
1923 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0);
1927 /* Default filter will allow packets that match the
1928 * dest mac. So, it has to be deleted, otherwise, we
1929 * will endup receiving vlan packets for which the
1930 * filter is not programmed, when hw-vlan-filter
1931 * configuration is ON
1933 bnxt_del_dflt_mac_filter(bp, vnic);
1934 /* This filter will allow only untagged packets */
1935 bnxt_add_vlan_filter(bp, 0);
1937 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1938 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1940 if (mask & ETH_VLAN_STRIP_MASK) {
1941 /* Enable or disable VLAN stripping */
1942 for (i = 0; i < bp->nr_vnics; i++) {
1943 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1944 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1945 vnic->vlan_strip = true;
1947 vnic->vlan_strip = false;
1948 bnxt_hwrm_vnic_cfg(bp, vnic);
1950 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1951 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1954 if (mask & ETH_VLAN_EXTEND_MASK) {
1955 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1956 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1958 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1965 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1968 struct bnxt *bp = dev->data->dev_private;
1969 int qinq = dev->data->dev_conf.rxmode.offloads &
1970 DEV_RX_OFFLOAD_VLAN_EXTEND;
1972 if (vlan_type != ETH_VLAN_TYPE_INNER &&
1973 vlan_type != ETH_VLAN_TYPE_OUTER) {
1975 "Unsupported vlan type.");
1980 "QinQ not enabled. Needs to be ON as we can "
1981 "accelerate only outer vlan\n");
1985 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1987 case RTE_ETHER_TYPE_QINQ:
1989 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1991 case RTE_ETHER_TYPE_VLAN:
1993 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1997 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2001 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2005 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2008 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2011 bp->outer_tpid_bd |= tpid;
2012 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2013 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2015 "Can accelerate only outer vlan in QinQ\n");
2023 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2024 struct rte_ether_addr *addr)
2026 struct bnxt *bp = dev->data->dev_private;
2027 /* Default Filter is tied to VNIC 0 */
2028 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
2029 struct bnxt_filter_info *filter;
2032 rc = is_bnxt_in_error(bp);
2036 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2039 if (rte_is_zero_ether_addr(addr))
2042 STAILQ_FOREACH(filter, &vnic->filter, next) {
2043 /* Default Filter is at Index 0 */
2044 if (filter->mac_index != 0)
2047 memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN);
2048 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
2049 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX |
2050 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2052 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
2053 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
2055 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2057 memcpy(filter->l2_addr, bp->mac_addr,
2058 RTE_ETHER_ADDR_LEN);
2062 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2063 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2071 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2072 struct rte_ether_addr *mc_addr_set,
2073 uint32_t nb_mc_addr)
2075 struct bnxt *bp = eth_dev->data->dev_private;
2076 char *mc_addr_list = (char *)mc_addr_set;
2077 struct bnxt_vnic_info *vnic;
2078 uint32_t off = 0, i = 0;
2081 rc = is_bnxt_in_error(bp);
2085 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2087 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2088 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2092 /* TODO Check for Duplicate mcast addresses */
2093 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2094 for (i = 0; i < nb_mc_addr; i++) {
2095 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2096 RTE_ETHER_ADDR_LEN);
2097 off += RTE_ETHER_ADDR_LEN;
2100 vnic->mc_addr_cnt = i;
2101 if (vnic->mc_addr_cnt)
2102 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2104 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2107 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2111 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2113 struct bnxt *bp = dev->data->dev_private;
2114 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2115 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2116 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2119 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2120 fw_major, fw_minor, fw_updt);
2122 ret += 1; /* add the size of '\0' */
2123 if (fw_size < (uint32_t)ret)
2130 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2131 struct rte_eth_rxq_info *qinfo)
2133 struct bnxt_rx_queue *rxq;
2135 rxq = dev->data->rx_queues[queue_id];
2137 qinfo->mp = rxq->mb_pool;
2138 qinfo->scattered_rx = dev->data->scattered_rx;
2139 qinfo->nb_desc = rxq->nb_rx_desc;
2141 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2142 qinfo->conf.rx_drop_en = 0;
2143 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2147 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2148 struct rte_eth_txq_info *qinfo)
2150 struct bnxt_tx_queue *txq;
2152 txq = dev->data->tx_queues[queue_id];
2154 qinfo->nb_desc = txq->nb_tx_desc;
2156 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2157 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2158 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2160 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2161 qinfo->conf.tx_rs_thresh = 0;
2162 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2165 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2167 struct bnxt *bp = eth_dev->data->dev_private;
2168 uint32_t new_pkt_size;
2172 rc = is_bnxt_in_error(bp);
2176 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2177 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2181 * If vector-mode tx/rx is active, disallow any MTU change that would
2182 * require scattered receive support.
2184 if (eth_dev->data->dev_started &&
2185 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2186 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2188 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2190 "MTU change would require scattered rx support. ");
2191 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2196 if (new_mtu > RTE_ETHER_MTU) {
2197 bp->flags |= BNXT_FLAG_JUMBO;
2198 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2199 DEV_RX_OFFLOAD_JUMBO_FRAME;
2201 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2202 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2203 bp->flags &= ~BNXT_FLAG_JUMBO;
2206 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2208 for (i = 0; i < bp->nr_vnics; i++) {
2209 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2212 vnic->mru = new_mtu + RTE_ETHER_HDR_LEN +
2213 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
2214 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2218 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2219 size -= RTE_PKTMBUF_HEADROOM;
2221 if (size < new_mtu) {
2222 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2228 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2234 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2236 struct bnxt *bp = dev->data->dev_private;
2237 uint16_t vlan = bp->vlan;
2240 rc = is_bnxt_in_error(bp);
2244 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2246 "PVID cannot be modified for this function\n");
2249 bp->vlan = on ? pvid : 0;
2251 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2258 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2260 struct bnxt *bp = dev->data->dev_private;
2263 rc = is_bnxt_in_error(bp);
2267 return bnxt_hwrm_port_led_cfg(bp, true);
2271 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2273 struct bnxt *bp = dev->data->dev_private;
2276 rc = is_bnxt_in_error(bp);
2280 return bnxt_hwrm_port_led_cfg(bp, false);
2284 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2286 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2287 uint32_t desc = 0, raw_cons = 0, cons;
2288 struct bnxt_cp_ring_info *cpr;
2289 struct bnxt_rx_queue *rxq;
2290 struct rx_pkt_cmpl *rxcmp;
2293 rc = is_bnxt_in_error(bp);
2297 rxq = dev->data->rx_queues[rx_queue_id];
2299 raw_cons = cpr->cp_raw_cons;
2302 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2303 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2304 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2306 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2318 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2320 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2321 struct bnxt_rx_ring_info *rxr;
2322 struct bnxt_cp_ring_info *cpr;
2323 struct bnxt_sw_rx_bd *rx_buf;
2324 struct rx_pkt_cmpl *rxcmp;
2325 uint32_t cons, cp_cons;
2331 rc = is_bnxt_in_error(rxq->bp);
2338 if (offset >= rxq->nb_rx_desc)
2341 cons = RING_CMP(cpr->cp_ring_struct, offset);
2342 cp_cons = cpr->cp_raw_cons;
2343 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2345 if (cons > cp_cons) {
2346 if (CMPL_VALID(rxcmp, cpr->valid))
2347 return RTE_ETH_RX_DESC_DONE;
2349 if (CMPL_VALID(rxcmp, !cpr->valid))
2350 return RTE_ETH_RX_DESC_DONE;
2352 rx_buf = &rxr->rx_buf_ring[cons];
2353 if (rx_buf->mbuf == NULL)
2354 return RTE_ETH_RX_DESC_UNAVAIL;
2357 return RTE_ETH_RX_DESC_AVAIL;
2361 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2363 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2364 struct bnxt_tx_ring_info *txr;
2365 struct bnxt_cp_ring_info *cpr;
2366 struct bnxt_sw_tx_bd *tx_buf;
2367 struct tx_pkt_cmpl *txcmp;
2368 uint32_t cons, cp_cons;
2374 rc = is_bnxt_in_error(txq->bp);
2381 if (offset >= txq->nb_tx_desc)
2384 cons = RING_CMP(cpr->cp_ring_struct, offset);
2385 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2386 cp_cons = cpr->cp_raw_cons;
2388 if (cons > cp_cons) {
2389 if (CMPL_VALID(txcmp, cpr->valid))
2390 return RTE_ETH_TX_DESC_UNAVAIL;
2392 if (CMPL_VALID(txcmp, !cpr->valid))
2393 return RTE_ETH_TX_DESC_UNAVAIL;
2395 tx_buf = &txr->tx_buf_ring[cons];
2396 if (tx_buf->mbuf == NULL)
2397 return RTE_ETH_TX_DESC_DONE;
2399 return RTE_ETH_TX_DESC_FULL;
2402 static struct bnxt_filter_info *
2403 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2404 struct rte_eth_ethertype_filter *efilter,
2405 struct bnxt_vnic_info *vnic0,
2406 struct bnxt_vnic_info *vnic,
2409 struct bnxt_filter_info *mfilter = NULL;
2413 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2414 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2415 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2416 " ethertype filter.", efilter->ether_type);
2420 if (efilter->queue >= bp->rx_nr_rings) {
2421 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2426 vnic0 = &bp->vnic_info[0];
2427 vnic = &bp->vnic_info[efilter->queue];
2429 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2434 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2435 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2436 if ((!memcmp(efilter->mac_addr.addr_bytes,
2437 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2439 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2440 mfilter->ethertype == efilter->ether_type)) {
2446 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2447 if ((!memcmp(efilter->mac_addr.addr_bytes,
2448 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2449 mfilter->ethertype == efilter->ether_type &&
2451 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2465 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2466 enum rte_filter_op filter_op,
2469 struct bnxt *bp = dev->data->dev_private;
2470 struct rte_eth_ethertype_filter *efilter =
2471 (struct rte_eth_ethertype_filter *)arg;
2472 struct bnxt_filter_info *bfilter, *filter1;
2473 struct bnxt_vnic_info *vnic, *vnic0;
2476 if (filter_op == RTE_ETH_FILTER_NOP)
2480 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2485 vnic0 = &bp->vnic_info[0];
2486 vnic = &bp->vnic_info[efilter->queue];
2488 switch (filter_op) {
2489 case RTE_ETH_FILTER_ADD:
2490 bnxt_match_and_validate_ether_filter(bp, efilter,
2495 bfilter = bnxt_get_unused_filter(bp);
2496 if (bfilter == NULL) {
2498 "Not enough resources for a new filter.\n");
2501 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2502 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2503 RTE_ETHER_ADDR_LEN);
2504 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2505 RTE_ETHER_ADDR_LEN);
2506 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2507 bfilter->ethertype = efilter->ether_type;
2508 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2510 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2511 if (filter1 == NULL) {
2516 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2517 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2519 bfilter->dst_id = vnic->fw_vnic_id;
2521 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2523 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2526 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2529 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2531 case RTE_ETH_FILTER_DELETE:
2532 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2534 if (ret == -EEXIST) {
2535 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2537 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2539 bnxt_free_filter(bp, filter1);
2540 } else if (ret == 0) {
2541 PMD_DRV_LOG(ERR, "No matching filter found\n");
2545 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2551 bnxt_free_filter(bp, bfilter);
2557 parse_ntuple_filter(struct bnxt *bp,
2558 struct rte_eth_ntuple_filter *nfilter,
2559 struct bnxt_filter_info *bfilter)
2563 if (nfilter->queue >= bp->rx_nr_rings) {
2564 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2568 switch (nfilter->dst_port_mask) {
2570 bfilter->dst_port_mask = -1;
2571 bfilter->dst_port = nfilter->dst_port;
2572 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2573 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2576 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2580 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2581 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2583 switch (nfilter->proto_mask) {
2585 if (nfilter->proto == 17) /* IPPROTO_UDP */
2586 bfilter->ip_protocol = 17;
2587 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2588 bfilter->ip_protocol = 6;
2591 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2594 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2598 switch (nfilter->dst_ip_mask) {
2600 bfilter->dst_ipaddr_mask[0] = -1;
2601 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2602 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2603 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2606 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2610 switch (nfilter->src_ip_mask) {
2612 bfilter->src_ipaddr_mask[0] = -1;
2613 bfilter->src_ipaddr[0] = nfilter->src_ip;
2614 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2615 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2618 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2622 switch (nfilter->src_port_mask) {
2624 bfilter->src_port_mask = -1;
2625 bfilter->src_port = nfilter->src_port;
2626 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2627 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2630 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2635 //nfilter->priority = (uint8_t)filter->priority;
2637 bfilter->enables = en;
2641 static struct bnxt_filter_info*
2642 bnxt_match_ntuple_filter(struct bnxt *bp,
2643 struct bnxt_filter_info *bfilter,
2644 struct bnxt_vnic_info **mvnic)
2646 struct bnxt_filter_info *mfilter = NULL;
2649 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2650 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2651 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2652 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2653 bfilter->src_ipaddr_mask[0] ==
2654 mfilter->src_ipaddr_mask[0] &&
2655 bfilter->src_port == mfilter->src_port &&
2656 bfilter->src_port_mask == mfilter->src_port_mask &&
2657 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2658 bfilter->dst_ipaddr_mask[0] ==
2659 mfilter->dst_ipaddr_mask[0] &&
2660 bfilter->dst_port == mfilter->dst_port &&
2661 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2662 bfilter->flags == mfilter->flags &&
2663 bfilter->enables == mfilter->enables) {
2674 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2675 struct rte_eth_ntuple_filter *nfilter,
2676 enum rte_filter_op filter_op)
2678 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2679 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2682 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2683 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2687 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2688 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2692 bfilter = bnxt_get_unused_filter(bp);
2693 if (bfilter == NULL) {
2695 "Not enough resources for a new filter.\n");
2698 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2702 vnic = &bp->vnic_info[nfilter->queue];
2703 vnic0 = &bp->vnic_info[0];
2704 filter1 = STAILQ_FIRST(&vnic0->filter);
2705 if (filter1 == NULL) {
2710 bfilter->dst_id = vnic->fw_vnic_id;
2711 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2713 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2714 bfilter->ethertype = 0x800;
2715 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2717 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2719 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2720 bfilter->dst_id == mfilter->dst_id) {
2721 PMD_DRV_LOG(ERR, "filter exists.\n");
2724 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2725 bfilter->dst_id != mfilter->dst_id) {
2726 mfilter->dst_id = vnic->fw_vnic_id;
2727 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2728 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2729 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2730 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2731 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2734 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2735 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2740 if (filter_op == RTE_ETH_FILTER_ADD) {
2741 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2742 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2745 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2747 if (mfilter == NULL) {
2748 /* This should not happen. But for Coverity! */
2752 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2754 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2755 bnxt_free_filter(bp, mfilter);
2756 mfilter->fw_l2_filter_id = -1;
2757 bnxt_free_filter(bp, bfilter);
2758 bfilter->fw_l2_filter_id = -1;
2763 bfilter->fw_l2_filter_id = -1;
2764 bnxt_free_filter(bp, bfilter);
2769 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2770 enum rte_filter_op filter_op,
2773 struct bnxt *bp = dev->data->dev_private;
2776 if (filter_op == RTE_ETH_FILTER_NOP)
2780 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2785 switch (filter_op) {
2786 case RTE_ETH_FILTER_ADD:
2787 ret = bnxt_cfg_ntuple_filter(bp,
2788 (struct rte_eth_ntuple_filter *)arg,
2791 case RTE_ETH_FILTER_DELETE:
2792 ret = bnxt_cfg_ntuple_filter(bp,
2793 (struct rte_eth_ntuple_filter *)arg,
2797 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2805 bnxt_parse_fdir_filter(struct bnxt *bp,
2806 struct rte_eth_fdir_filter *fdir,
2807 struct bnxt_filter_info *filter)
2809 enum rte_fdir_mode fdir_mode =
2810 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2811 struct bnxt_vnic_info *vnic0, *vnic;
2812 struct bnxt_filter_info *filter1;
2816 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2819 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2820 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2822 switch (fdir->input.flow_type) {
2823 case RTE_ETH_FLOW_IPV4:
2824 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2826 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2827 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2828 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2829 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2830 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2831 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2832 filter->ip_addr_type =
2833 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2834 filter->src_ipaddr_mask[0] = 0xffffffff;
2835 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2836 filter->dst_ipaddr_mask[0] = 0xffffffff;
2837 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2838 filter->ethertype = 0x800;
2839 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2841 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2842 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2843 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2844 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2845 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2846 filter->dst_port_mask = 0xffff;
2847 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2848 filter->src_port_mask = 0xffff;
2849 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2850 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2851 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2852 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2853 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2854 filter->ip_protocol = 6;
2855 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2856 filter->ip_addr_type =
2857 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2858 filter->src_ipaddr_mask[0] = 0xffffffff;
2859 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2860 filter->dst_ipaddr_mask[0] = 0xffffffff;
2861 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2862 filter->ethertype = 0x800;
2863 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2865 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2866 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2867 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2868 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2869 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2870 filter->dst_port_mask = 0xffff;
2871 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2872 filter->src_port_mask = 0xffff;
2873 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2874 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2875 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2876 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2877 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2878 filter->ip_protocol = 17;
2879 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2880 filter->ip_addr_type =
2881 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2882 filter->src_ipaddr_mask[0] = 0xffffffff;
2883 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2884 filter->dst_ipaddr_mask[0] = 0xffffffff;
2885 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2886 filter->ethertype = 0x800;
2887 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2889 case RTE_ETH_FLOW_IPV6:
2890 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2892 filter->ip_addr_type =
2893 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2894 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2895 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2896 rte_memcpy(filter->src_ipaddr,
2897 fdir->input.flow.ipv6_flow.src_ip, 16);
2898 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2899 rte_memcpy(filter->dst_ipaddr,
2900 fdir->input.flow.ipv6_flow.dst_ip, 16);
2901 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2902 memset(filter->dst_ipaddr_mask, 0xff, 16);
2903 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2904 memset(filter->src_ipaddr_mask, 0xff, 16);
2905 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2906 filter->ethertype = 0x86dd;
2907 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2909 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2910 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2911 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2912 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2913 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2914 filter->dst_port_mask = 0xffff;
2915 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2916 filter->src_port_mask = 0xffff;
2917 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2918 filter->ip_addr_type =
2919 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2920 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2921 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2922 rte_memcpy(filter->src_ipaddr,
2923 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2924 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2925 rte_memcpy(filter->dst_ipaddr,
2926 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2927 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2928 memset(filter->dst_ipaddr_mask, 0xff, 16);
2929 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2930 memset(filter->src_ipaddr_mask, 0xff, 16);
2931 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2932 filter->ethertype = 0x86dd;
2933 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2935 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2936 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2937 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2938 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2939 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2940 filter->dst_port_mask = 0xffff;
2941 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2942 filter->src_port_mask = 0xffff;
2943 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2944 filter->ip_addr_type =
2945 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2946 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2947 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2948 rte_memcpy(filter->src_ipaddr,
2949 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2950 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2951 rte_memcpy(filter->dst_ipaddr,
2952 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2953 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2954 memset(filter->dst_ipaddr_mask, 0xff, 16);
2955 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2956 memset(filter->src_ipaddr_mask, 0xff, 16);
2957 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2958 filter->ethertype = 0x86dd;
2959 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2961 case RTE_ETH_FLOW_L2_PAYLOAD:
2962 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2963 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2965 case RTE_ETH_FLOW_VXLAN:
2966 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2968 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2969 filter->tunnel_type =
2970 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2971 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2973 case RTE_ETH_FLOW_NVGRE:
2974 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2976 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2977 filter->tunnel_type =
2978 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2979 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2981 case RTE_ETH_FLOW_UNKNOWN:
2982 case RTE_ETH_FLOW_RAW:
2983 case RTE_ETH_FLOW_FRAG_IPV4:
2984 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2985 case RTE_ETH_FLOW_FRAG_IPV6:
2986 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2987 case RTE_ETH_FLOW_IPV6_EX:
2988 case RTE_ETH_FLOW_IPV6_TCP_EX:
2989 case RTE_ETH_FLOW_IPV6_UDP_EX:
2990 case RTE_ETH_FLOW_GENEVE:
2996 vnic0 = &bp->vnic_info[0];
2997 vnic = &bp->vnic_info[fdir->action.rx_queue];
2999 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3004 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3005 rte_memcpy(filter->dst_macaddr,
3006 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3007 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3010 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3011 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3012 filter1 = STAILQ_FIRST(&vnic0->filter);
3013 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3015 filter->dst_id = vnic->fw_vnic_id;
3016 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3017 if (filter->dst_macaddr[i] == 0x00)
3018 filter1 = STAILQ_FIRST(&vnic0->filter);
3020 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3023 if (filter1 == NULL)
3026 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3027 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3029 filter->enables = en;
3034 static struct bnxt_filter_info *
3035 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3036 struct bnxt_vnic_info **mvnic)
3038 struct bnxt_filter_info *mf = NULL;
3041 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3042 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3044 STAILQ_FOREACH(mf, &vnic->filter, next) {
3045 if (mf->filter_type == nf->filter_type &&
3046 mf->flags == nf->flags &&
3047 mf->src_port == nf->src_port &&
3048 mf->src_port_mask == nf->src_port_mask &&
3049 mf->dst_port == nf->dst_port &&
3050 mf->dst_port_mask == nf->dst_port_mask &&
3051 mf->ip_protocol == nf->ip_protocol &&
3052 mf->ip_addr_type == nf->ip_addr_type &&
3053 mf->ethertype == nf->ethertype &&
3054 mf->vni == nf->vni &&
3055 mf->tunnel_type == nf->tunnel_type &&
3056 mf->l2_ovlan == nf->l2_ovlan &&
3057 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3058 mf->l2_ivlan == nf->l2_ivlan &&
3059 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3060 !memcmp(mf->l2_addr, nf->l2_addr,
3061 RTE_ETHER_ADDR_LEN) &&
3062 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3063 RTE_ETHER_ADDR_LEN) &&
3064 !memcmp(mf->src_macaddr, nf->src_macaddr,
3065 RTE_ETHER_ADDR_LEN) &&
3066 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3067 RTE_ETHER_ADDR_LEN) &&
3068 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3069 sizeof(nf->src_ipaddr)) &&
3070 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3071 sizeof(nf->src_ipaddr_mask)) &&
3072 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3073 sizeof(nf->dst_ipaddr)) &&
3074 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3075 sizeof(nf->dst_ipaddr_mask))) {
3086 bnxt_fdir_filter(struct rte_eth_dev *dev,
3087 enum rte_filter_op filter_op,
3090 struct bnxt *bp = dev->data->dev_private;
3091 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3092 struct bnxt_filter_info *filter, *match;
3093 struct bnxt_vnic_info *vnic, *mvnic;
3096 if (filter_op == RTE_ETH_FILTER_NOP)
3099 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3102 switch (filter_op) {
3103 case RTE_ETH_FILTER_ADD:
3104 case RTE_ETH_FILTER_DELETE:
3106 filter = bnxt_get_unused_filter(bp);
3107 if (filter == NULL) {
3109 "Not enough resources for a new flow.\n");
3113 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3116 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3118 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3119 vnic = &bp->vnic_info[0];
3121 vnic = &bp->vnic_info[fdir->action.rx_queue];
3123 match = bnxt_match_fdir(bp, filter, &mvnic);
3124 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3125 if (match->dst_id == vnic->fw_vnic_id) {
3126 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3130 match->dst_id = vnic->fw_vnic_id;
3131 ret = bnxt_hwrm_set_ntuple_filter(bp,
3134 STAILQ_REMOVE(&mvnic->filter, match,
3135 bnxt_filter_info, next);
3136 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3138 "Filter with matching pattern exist\n");
3140 "Updated it to new destination q\n");
3144 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3145 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3150 if (filter_op == RTE_ETH_FILTER_ADD) {
3151 ret = bnxt_hwrm_set_ntuple_filter(bp,
3156 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3158 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3159 STAILQ_REMOVE(&vnic->filter, match,
3160 bnxt_filter_info, next);
3161 bnxt_free_filter(bp, match);
3162 filter->fw_l2_filter_id = -1;
3163 bnxt_free_filter(bp, filter);
3166 case RTE_ETH_FILTER_FLUSH:
3167 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3168 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3170 STAILQ_FOREACH(filter, &vnic->filter, next) {
3171 if (filter->filter_type ==
3172 HWRM_CFA_NTUPLE_FILTER) {
3174 bnxt_hwrm_clear_ntuple_filter(bp,
3176 STAILQ_REMOVE(&vnic->filter, filter,
3177 bnxt_filter_info, next);
3182 case RTE_ETH_FILTER_UPDATE:
3183 case RTE_ETH_FILTER_STATS:
3184 case RTE_ETH_FILTER_INFO:
3185 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3188 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3195 filter->fw_l2_filter_id = -1;
3196 bnxt_free_filter(bp, filter);
3201 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3202 enum rte_filter_type filter_type,
3203 enum rte_filter_op filter_op, void *arg)
3207 ret = is_bnxt_in_error(dev->data->dev_private);
3211 switch (filter_type) {
3212 case RTE_ETH_FILTER_TUNNEL:
3214 "filter type: %d: To be implemented\n", filter_type);
3216 case RTE_ETH_FILTER_FDIR:
3217 ret = bnxt_fdir_filter(dev, filter_op, arg);
3219 case RTE_ETH_FILTER_NTUPLE:
3220 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3222 case RTE_ETH_FILTER_ETHERTYPE:
3223 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3225 case RTE_ETH_FILTER_GENERIC:
3226 if (filter_op != RTE_ETH_FILTER_GET)
3228 *(const void **)arg = &bnxt_flow_ops;
3232 "Filter type (%d) not supported", filter_type);
3239 static const uint32_t *
3240 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3242 static const uint32_t ptypes[] = {
3243 RTE_PTYPE_L2_ETHER_VLAN,
3244 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3245 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3249 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3250 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3251 RTE_PTYPE_INNER_L4_ICMP,
3252 RTE_PTYPE_INNER_L4_TCP,
3253 RTE_PTYPE_INNER_L4_UDP,
3257 if (!dev->rx_pkt_burst)
3263 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3266 uint32_t reg_base = *reg_arr & 0xfffff000;
3270 for (i = 0; i < count; i++) {
3271 if ((reg_arr[i] & 0xfffff000) != reg_base)
3274 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3275 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3279 static int bnxt_map_ptp_regs(struct bnxt *bp)
3281 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3285 reg_arr = ptp->rx_regs;
3286 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3290 reg_arr = ptp->tx_regs;
3291 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3295 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3296 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3298 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3299 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3304 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3306 rte_write32(0, (uint8_t *)bp->bar0 +
3307 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3308 rte_write32(0, (uint8_t *)bp->bar0 +
3309 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3312 static uint64_t bnxt_cc_read(struct bnxt *bp)
3316 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3317 BNXT_GRCPF_REG_SYNC_TIME));
3318 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3319 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3323 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3325 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3328 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3329 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3330 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3333 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3334 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3335 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3336 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3337 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3338 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3343 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3345 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3346 struct bnxt_pf_info *pf = &bp->pf;
3353 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3354 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3355 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3358 port_id = pf->port_id;
3359 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3360 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3362 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3363 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3364 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3365 /* bnxt_clr_rx_ts(bp); TBD */
3369 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3370 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3371 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3372 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3378 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3381 struct bnxt *bp = dev->data->dev_private;
3382 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3387 ns = rte_timespec_to_ns(ts);
3388 /* Set the timecounters to a new value. */
3395 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3397 struct bnxt *bp = dev->data->dev_private;
3398 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3399 uint64_t ns, systime_cycles = 0;
3405 if (BNXT_CHIP_THOR(bp))
3406 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3409 systime_cycles = bnxt_cc_read(bp);
3411 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3412 *ts = rte_ns_to_timespec(ns);
3417 bnxt_timesync_enable(struct rte_eth_dev *dev)
3419 struct bnxt *bp = dev->data->dev_private;
3420 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3428 ptp->tx_tstamp_en = 1;
3429 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3431 rc = bnxt_hwrm_ptp_cfg(bp);
3435 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3436 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3437 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3439 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3440 ptp->tc.cc_shift = shift;
3441 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3443 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3444 ptp->rx_tstamp_tc.cc_shift = shift;
3445 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3447 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3448 ptp->tx_tstamp_tc.cc_shift = shift;
3449 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3451 if (!BNXT_CHIP_THOR(bp))
3452 bnxt_map_ptp_regs(bp);
3458 bnxt_timesync_disable(struct rte_eth_dev *dev)
3460 struct bnxt *bp = dev->data->dev_private;
3461 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3467 ptp->tx_tstamp_en = 0;
3470 bnxt_hwrm_ptp_cfg(bp);
3472 if (!BNXT_CHIP_THOR(bp))
3473 bnxt_unmap_ptp_regs(bp);
3479 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3480 struct timespec *timestamp,
3481 uint32_t flags __rte_unused)
3483 struct bnxt *bp = dev->data->dev_private;
3484 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3485 uint64_t rx_tstamp_cycles = 0;
3491 if (BNXT_CHIP_THOR(bp))
3492 rx_tstamp_cycles = ptp->rx_timestamp;
3494 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3496 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3497 *timestamp = rte_ns_to_timespec(ns);
3502 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3503 struct timespec *timestamp)
3505 struct bnxt *bp = dev->data->dev_private;
3506 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3507 uint64_t tx_tstamp_cycles = 0;
3514 if (BNXT_CHIP_THOR(bp))
3515 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3518 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3520 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3521 *timestamp = rte_ns_to_timespec(ns);
3527 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3529 struct bnxt *bp = dev->data->dev_private;
3530 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3535 ptp->tc.nsec += delta;
3541 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3543 struct bnxt *bp = dev->data->dev_private;
3545 uint32_t dir_entries;
3546 uint32_t entry_length;
3548 rc = is_bnxt_in_error(bp);
3552 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3553 bp->pdev->addr.domain, bp->pdev->addr.bus,
3554 bp->pdev->addr.devid, bp->pdev->addr.function);
3556 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3560 return dir_entries * entry_length;
3564 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3565 struct rte_dev_eeprom_info *in_eeprom)
3567 struct bnxt *bp = dev->data->dev_private;
3572 rc = is_bnxt_in_error(bp);
3576 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3577 "len = %d\n", bp->pdev->addr.domain,
3578 bp->pdev->addr.bus, bp->pdev->addr.devid,
3579 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3581 if (in_eeprom->offset == 0) /* special offset value to get directory */
3582 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3585 index = in_eeprom->offset >> 24;
3586 offset = in_eeprom->offset & 0xffffff;
3589 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3590 in_eeprom->length, in_eeprom->data);
3595 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3598 case BNX_DIR_TYPE_CHIMP_PATCH:
3599 case BNX_DIR_TYPE_BOOTCODE:
3600 case BNX_DIR_TYPE_BOOTCODE_2:
3601 case BNX_DIR_TYPE_APE_FW:
3602 case BNX_DIR_TYPE_APE_PATCH:
3603 case BNX_DIR_TYPE_KONG_FW:
3604 case BNX_DIR_TYPE_KONG_PATCH:
3605 case BNX_DIR_TYPE_BONO_FW:
3606 case BNX_DIR_TYPE_BONO_PATCH:
3614 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3617 case BNX_DIR_TYPE_AVS:
3618 case BNX_DIR_TYPE_EXP_ROM_MBA:
3619 case BNX_DIR_TYPE_PCIE:
3620 case BNX_DIR_TYPE_TSCF_UCODE:
3621 case BNX_DIR_TYPE_EXT_PHY:
3622 case BNX_DIR_TYPE_CCM:
3623 case BNX_DIR_TYPE_ISCSI_BOOT:
3624 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3625 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3633 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3635 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3636 bnxt_dir_type_is_other_exec_format(dir_type);
3640 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3641 struct rte_dev_eeprom_info *in_eeprom)
3643 struct bnxt *bp = dev->data->dev_private;
3644 uint8_t index, dir_op;
3645 uint16_t type, ext, ordinal, attr;
3648 rc = is_bnxt_in_error(bp);
3652 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3653 "len = %d\n", bp->pdev->addr.domain,
3654 bp->pdev->addr.bus, bp->pdev->addr.devid,
3655 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3658 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3662 type = in_eeprom->magic >> 16;
3664 if (type == 0xffff) { /* special value for directory operations */
3665 index = in_eeprom->magic & 0xff;
3666 dir_op = in_eeprom->magic >> 8;
3670 case 0x0e: /* erase */
3671 if (in_eeprom->offset != ~in_eeprom->magic)
3673 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3679 /* Create or re-write an NVM item: */
3680 if (bnxt_dir_type_is_executable(type) == true)
3682 ext = in_eeprom->magic & 0xffff;
3683 ordinal = in_eeprom->offset >> 16;
3684 attr = in_eeprom->offset & 0xffff;
3686 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3687 in_eeprom->data, in_eeprom->length);
3694 static const struct eth_dev_ops bnxt_dev_ops = {
3695 .dev_infos_get = bnxt_dev_info_get_op,
3696 .dev_close = bnxt_dev_close_op,
3697 .dev_configure = bnxt_dev_configure_op,
3698 .dev_start = bnxt_dev_start_op,
3699 .dev_stop = bnxt_dev_stop_op,
3700 .dev_set_link_up = bnxt_dev_set_link_up_op,
3701 .dev_set_link_down = bnxt_dev_set_link_down_op,
3702 .stats_get = bnxt_stats_get_op,
3703 .stats_reset = bnxt_stats_reset_op,
3704 .rx_queue_setup = bnxt_rx_queue_setup_op,
3705 .rx_queue_release = bnxt_rx_queue_release_op,
3706 .tx_queue_setup = bnxt_tx_queue_setup_op,
3707 .tx_queue_release = bnxt_tx_queue_release_op,
3708 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3709 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3710 .reta_update = bnxt_reta_update_op,
3711 .reta_query = bnxt_reta_query_op,
3712 .rss_hash_update = bnxt_rss_hash_update_op,
3713 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3714 .link_update = bnxt_link_update_op,
3715 .promiscuous_enable = bnxt_promiscuous_enable_op,
3716 .promiscuous_disable = bnxt_promiscuous_disable_op,
3717 .allmulticast_enable = bnxt_allmulticast_enable_op,
3718 .allmulticast_disable = bnxt_allmulticast_disable_op,
3719 .mac_addr_add = bnxt_mac_addr_add_op,
3720 .mac_addr_remove = bnxt_mac_addr_remove_op,
3721 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3722 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3723 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3724 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3725 .vlan_filter_set = bnxt_vlan_filter_set_op,
3726 .vlan_offload_set = bnxt_vlan_offload_set_op,
3727 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3728 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3729 .mtu_set = bnxt_mtu_set_op,
3730 .mac_addr_set = bnxt_set_default_mac_addr_op,
3731 .xstats_get = bnxt_dev_xstats_get_op,
3732 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3733 .xstats_reset = bnxt_dev_xstats_reset_op,
3734 .fw_version_get = bnxt_fw_version_get,
3735 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3736 .rxq_info_get = bnxt_rxq_info_get_op,
3737 .txq_info_get = bnxt_txq_info_get_op,
3738 .dev_led_on = bnxt_dev_led_on_op,
3739 .dev_led_off = bnxt_dev_led_off_op,
3740 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3741 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3742 .rx_queue_count = bnxt_rx_queue_count_op,
3743 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3744 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3745 .rx_queue_start = bnxt_rx_queue_start,
3746 .rx_queue_stop = bnxt_rx_queue_stop,
3747 .tx_queue_start = bnxt_tx_queue_start,
3748 .tx_queue_stop = bnxt_tx_queue_stop,
3749 .filter_ctrl = bnxt_filter_ctrl_op,
3750 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3751 .get_eeprom_length = bnxt_get_eeprom_length_op,
3752 .get_eeprom = bnxt_get_eeprom_op,
3753 .set_eeprom = bnxt_set_eeprom_op,
3754 .timesync_enable = bnxt_timesync_enable,
3755 .timesync_disable = bnxt_timesync_disable,
3756 .timesync_read_time = bnxt_timesync_read_time,
3757 .timesync_write_time = bnxt_timesync_write_time,
3758 .timesync_adjust_time = bnxt_timesync_adjust_time,
3759 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3760 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3763 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3767 /* Only pre-map the reset GRC registers using window 3 */
3768 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3769 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3771 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3776 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3778 struct bnxt_error_recovery_info *info = bp->recovery_info;
3779 uint32_t reg_base = 0xffffffff;
3782 /* Only pre-map the monitoring GRC registers using window 2 */
3783 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3784 uint32_t reg = info->status_regs[i];
3786 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3789 if (reg_base == 0xffffffff)
3790 reg_base = reg & 0xfffff000;
3791 if ((reg & 0xfffff000) != reg_base)
3794 /* Use mask 0xffc as the Lower 2 bits indicates
3795 * address space location
3797 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3801 if (reg_base == 0xffffffff)
3804 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3805 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3810 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3812 struct bnxt_error_recovery_info *info = bp->recovery_info;
3813 uint32_t delay = info->delay_after_reset[index];
3814 uint32_t val = info->reset_reg_val[index];
3815 uint32_t reg = info->reset_reg[index];
3816 uint32_t type, offset;
3818 type = BNXT_FW_STATUS_REG_TYPE(reg);
3819 offset = BNXT_FW_STATUS_REG_OFF(reg);
3822 case BNXT_FW_STATUS_REG_TYPE_CFG:
3823 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3825 case BNXT_FW_STATUS_REG_TYPE_GRC:
3826 offset = bnxt_map_reset_regs(bp, offset);
3827 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3829 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3830 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3833 /* wait on a specific interval of time until core reset is complete */
3835 rte_delay_ms(delay);
3838 static void bnxt_dev_cleanup(struct bnxt *bp)
3840 bnxt_set_hwrm_link_config(bp, false);
3841 bp->link_info.link_up = 0;
3842 if (bp->dev_stopped == 0)
3843 bnxt_dev_stop_op(bp->eth_dev);
3845 bnxt_uninit_resources(bp, true);
3848 static int bnxt_restore_filters(struct bnxt *bp)
3850 struct rte_eth_dev *dev = bp->eth_dev;
3853 if (dev->data->all_multicast)
3854 ret = bnxt_allmulticast_enable_op(dev);
3855 if (dev->data->promiscuous)
3856 ret = bnxt_promiscuous_enable_op(dev);
3858 /* TODO restore other filters as well */
3862 static void bnxt_dev_recover(void *arg)
3864 struct bnxt *bp = arg;
3865 int timeout = bp->fw_reset_max_msecs;
3868 /* Clear Error flag so that device re-init should happen */
3869 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3872 rc = bnxt_hwrm_ver_get(bp);
3875 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3876 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3877 } while (rc && timeout);
3880 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3884 rc = bnxt_init_resources(bp, true);
3887 "Failed to initialize resources after reset\n");
3890 /* clear reset flag as the device is initialized now */
3891 bp->flags &= ~BNXT_FLAG_FW_RESET;
3893 rc = bnxt_dev_start_op(bp->eth_dev);
3895 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3899 rc = bnxt_restore_filters(bp);
3903 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3906 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3907 bnxt_uninit_resources(bp, false);
3908 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3911 void bnxt_dev_reset_and_resume(void *arg)
3913 struct bnxt *bp = arg;
3916 bnxt_dev_cleanup(bp);
3918 bnxt_wait_for_device_shutdown(bp);
3920 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3921 bnxt_dev_recover, (void *)bp);
3923 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3926 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3928 struct bnxt_error_recovery_info *info = bp->recovery_info;
3929 uint32_t reg = info->status_regs[index];
3930 uint32_t type, offset, val = 0;
3932 type = BNXT_FW_STATUS_REG_TYPE(reg);
3933 offset = BNXT_FW_STATUS_REG_OFF(reg);
3936 case BNXT_FW_STATUS_REG_TYPE_CFG:
3937 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3939 case BNXT_FW_STATUS_REG_TYPE_GRC:
3940 offset = info->mapped_status_regs[index];
3942 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3943 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3951 static int bnxt_fw_reset_all(struct bnxt *bp)
3953 struct bnxt_error_recovery_info *info = bp->recovery_info;
3957 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3958 /* Reset through master function driver */
3959 for (i = 0; i < info->reg_array_cnt; i++)
3960 bnxt_write_fw_reset_reg(bp, i);
3961 /* Wait for time specified by FW after triggering reset */
3962 rte_delay_ms(info->master_func_wait_period_after_reset);
3963 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3964 /* Reset with the help of Kong processor */
3965 rc = bnxt_hwrm_fw_reset(bp);
3967 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3973 static void bnxt_fw_reset_cb(void *arg)
3975 struct bnxt *bp = arg;
3976 struct bnxt_error_recovery_info *info = bp->recovery_info;
3979 /* Only Master function can do FW reset */
3980 if (bnxt_is_master_func(bp) &&
3981 bnxt_is_recovery_enabled(bp)) {
3982 rc = bnxt_fw_reset_all(bp);
3984 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3989 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3990 * EXCEPTION_FATAL_ASYNC event to all the functions
3991 * (including MASTER FUNC). After receiving this Async, all the active
3992 * drivers should treat this case as FW initiated recovery
3994 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3995 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3996 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3998 /* To recover from error */
3999 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4004 /* Driver should poll FW heartbeat, reset_counter with the frequency
4005 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4006 * When the driver detects heartbeat stop or change in reset_counter,
4007 * it has to trigger a reset to recover from the error condition.
4008 * A “master PF” is the function who will have the privilege to
4009 * initiate the chimp reset. The master PF will be elected by the
4010 * firmware and will be notified through async message.
4012 static void bnxt_check_fw_health(void *arg)
4014 struct bnxt *bp = arg;
4015 struct bnxt_error_recovery_info *info = bp->recovery_info;
4016 uint32_t val = 0, wait_msec;
4018 if (!info || !bnxt_is_recovery_enabled(bp) ||
4019 is_bnxt_in_error(bp))
4022 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4023 if (val == info->last_heart_beat)
4026 info->last_heart_beat = val;
4028 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4029 if (val != info->last_reset_counter)
4032 info->last_reset_counter = val;
4034 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4035 bnxt_check_fw_health, (void *)bp);
4039 /* Stop DMA to/from device */
4040 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4041 bp->flags |= BNXT_FLAG_FW_RESET;
4043 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4045 if (bnxt_is_master_func(bp))
4046 wait_msec = info->master_func_wait_period;
4048 wait_msec = info->normal_func_wait_period;
4050 rte_eal_alarm_set(US_PER_MS * wait_msec,
4051 bnxt_fw_reset_cb, (void *)bp);
4054 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4056 uint32_t polling_freq;
4058 if (!bnxt_is_recovery_enabled(bp))
4061 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4064 polling_freq = bp->recovery_info->driver_polling_freq;
4066 rte_eal_alarm_set(US_PER_MS * polling_freq,
4067 bnxt_check_fw_health, (void *)bp);
4068 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4071 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4073 if (!bnxt_is_recovery_enabled(bp))
4076 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4077 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4080 static bool bnxt_vf_pciid(uint16_t id)
4082 if (id == BROADCOM_DEV_ID_57304_VF ||
4083 id == BROADCOM_DEV_ID_57406_VF ||
4084 id == BROADCOM_DEV_ID_5731X_VF ||
4085 id == BROADCOM_DEV_ID_5741X_VF ||
4086 id == BROADCOM_DEV_ID_57414_VF ||
4087 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4088 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
4089 id == BROADCOM_DEV_ID_58802_VF ||
4090 id == BROADCOM_DEV_ID_57500_VF1 ||
4091 id == BROADCOM_DEV_ID_57500_VF2)
4096 bool bnxt_stratus_device(struct bnxt *bp)
4098 uint16_t id = bp->pdev->id.device_id;
4100 if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
4101 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4102 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
4107 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4109 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4110 struct bnxt *bp = eth_dev->data->dev_private;
4112 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4113 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4114 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4115 if (!bp->bar0 || !bp->doorbell_base) {
4116 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4120 bp->eth_dev = eth_dev;
4126 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
4127 struct bnxt_ctx_pg_info *ctx_pg,
4132 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4133 const struct rte_memzone *mz = NULL;
4134 char mz_name[RTE_MEMZONE_NAMESIZE];
4135 rte_iova_t mz_phys_addr;
4136 uint64_t valid_bits = 0;
4143 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4145 rmem->page_size = BNXT_PAGE_SIZE;
4146 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4147 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4148 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4150 valid_bits = PTU_PTE_VALID;
4152 if (rmem->nr_pages > 1) {
4153 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4154 "bnxt_ctx_pg_tbl%s_%x_%d",
4155 suffix, idx, bp->eth_dev->data->port_id);
4156 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4157 mz = rte_memzone_lookup(mz_name);
4159 mz = rte_memzone_reserve_aligned(mz_name,
4163 RTE_MEMZONE_SIZE_HINT_ONLY |
4164 RTE_MEMZONE_IOVA_CONTIG,
4170 memset(mz->addr, 0, mz->len);
4171 mz_phys_addr = mz->iova;
4172 if ((unsigned long)mz->addr == mz_phys_addr) {
4174 "physical address same as virtual\n");
4175 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4176 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4177 if (mz_phys_addr == RTE_BAD_IOVA) {
4179 "unable to map addr to phys memory\n");
4183 rte_mem_lock_page(((char *)mz->addr));
4185 rmem->pg_tbl = mz->addr;
4186 rmem->pg_tbl_map = mz_phys_addr;
4187 rmem->pg_tbl_mz = mz;
4190 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4191 suffix, idx, bp->eth_dev->data->port_id);
4192 mz = rte_memzone_lookup(mz_name);
4194 mz = rte_memzone_reserve_aligned(mz_name,
4198 RTE_MEMZONE_SIZE_HINT_ONLY |
4199 RTE_MEMZONE_IOVA_CONTIG,
4205 memset(mz->addr, 0, mz->len);
4206 mz_phys_addr = mz->iova;
4207 if ((unsigned long)mz->addr == mz_phys_addr) {
4209 "Memzone physical address same as virtual.\n");
4210 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4211 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4212 rte_mem_lock_page(((char *)mz->addr) + sz);
4213 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4214 if (mz_phys_addr == RTE_BAD_IOVA) {
4216 "unable to map addr to phys memory\n");
4221 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4222 rte_mem_lock_page(((char *)mz->addr) + sz);
4223 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4224 rmem->dma_arr[i] = mz_phys_addr + sz;
4226 if (rmem->nr_pages > 1) {
4227 if (i == rmem->nr_pages - 2 &&
4228 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4229 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4230 else if (i == rmem->nr_pages - 1 &&
4231 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4232 valid_bits |= PTU_PTE_LAST;
4234 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4240 if (rmem->vmem_size)
4241 rmem->vmem = (void **)mz->addr;
4242 rmem->dma_arr[0] = mz_phys_addr;
4246 static void bnxt_free_ctx_mem(struct bnxt *bp)
4250 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4253 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4254 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4255 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4256 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4257 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4258 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4259 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4260 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4261 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4262 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4263 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4265 for (i = 0; i < BNXT_MAX_Q; i++) {
4266 if (bp->ctx->tqm_mem[i])
4267 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4274 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4276 #define min_t(type, x, y) ({ \
4277 type __min1 = (x); \
4278 type __min2 = (y); \
4279 __min1 < __min2 ? __min1 : __min2; })
4281 #define max_t(type, x, y) ({ \
4282 type __max1 = (x); \
4283 type __max2 = (y); \
4284 __max1 > __max2 ? __max1 : __max2; })
4286 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4288 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4290 struct bnxt_ctx_pg_info *ctx_pg;
4291 struct bnxt_ctx_mem_info *ctx;
4292 uint32_t mem_size, ena, entries;
4295 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4297 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4301 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4304 ctx_pg = &ctx->qp_mem;
4305 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4306 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4307 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4311 ctx_pg = &ctx->srq_mem;
4312 ctx_pg->entries = ctx->srq_max_l2_entries;
4313 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4314 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4318 ctx_pg = &ctx->cq_mem;
4319 ctx_pg->entries = ctx->cq_max_l2_entries;
4320 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4321 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4325 ctx_pg = &ctx->vnic_mem;
4326 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4327 ctx->vnic_max_ring_table_entries;
4328 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4329 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4333 ctx_pg = &ctx->stat_mem;
4334 ctx_pg->entries = ctx->stat_max_entries;
4335 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4336 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4340 entries = ctx->qp_max_l2_entries +
4341 ctx->vnic_max_vnic_entries +
4342 ctx->tqm_min_entries_per_ring;
4343 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4344 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4345 ctx->tqm_max_entries_per_ring);
4346 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4347 ctx_pg = ctx->tqm_mem[i];
4348 /* use min tqm entries for now. */
4349 ctx_pg->entries = entries;
4350 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4351 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4354 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4357 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4358 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4361 "Failed to configure context mem: rc = %d\n", rc);
4363 ctx->flags |= BNXT_CTX_FLAG_INITED;
4368 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4370 struct rte_pci_device *pci_dev = bp->pdev;
4371 char mz_name[RTE_MEMZONE_NAMESIZE];
4372 const struct rte_memzone *mz = NULL;
4373 uint32_t total_alloc_len;
4374 rte_iova_t mz_phys_addr;
4376 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4379 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4380 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4381 pci_dev->addr.bus, pci_dev->addr.devid,
4382 pci_dev->addr.function, "rx_port_stats");
4383 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4384 mz = rte_memzone_lookup(mz_name);
4386 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4387 sizeof(struct rx_port_stats_ext) + 512);
4389 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4392 RTE_MEMZONE_SIZE_HINT_ONLY |
4393 RTE_MEMZONE_IOVA_CONTIG);
4397 memset(mz->addr, 0, mz->len);
4398 mz_phys_addr = mz->iova;
4399 if ((unsigned long)mz->addr == mz_phys_addr) {
4401 "Memzone physical address same as virtual.\n");
4403 "Using rte_mem_virt2iova()\n");
4404 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4405 if (mz_phys_addr == RTE_BAD_IOVA) {
4407 "Can't map address to physical memory\n");
4412 bp->rx_mem_zone = (const void *)mz;
4413 bp->hw_rx_port_stats = mz->addr;
4414 bp->hw_rx_port_stats_map = mz_phys_addr;
4416 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4417 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4418 pci_dev->addr.bus, pci_dev->addr.devid,
4419 pci_dev->addr.function, "tx_port_stats");
4420 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4421 mz = rte_memzone_lookup(mz_name);
4423 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4424 sizeof(struct tx_port_stats_ext) + 512);
4426 mz = rte_memzone_reserve(mz_name,
4430 RTE_MEMZONE_SIZE_HINT_ONLY |
4431 RTE_MEMZONE_IOVA_CONTIG);
4435 memset(mz->addr, 0, mz->len);
4436 mz_phys_addr = mz->iova;
4437 if ((unsigned long)mz->addr == mz_phys_addr) {
4439 "Memzone physical address same as virtual\n");
4440 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4441 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4442 if (mz_phys_addr == RTE_BAD_IOVA) {
4444 "Can't map address to physical memory\n");
4449 bp->tx_mem_zone = (const void *)mz;
4450 bp->hw_tx_port_stats = mz->addr;
4451 bp->hw_tx_port_stats_map = mz_phys_addr;
4452 bp->flags |= BNXT_FLAG_PORT_STATS;
4454 /* Display extended statistics if FW supports it */
4455 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4456 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4457 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4460 bp->hw_rx_port_stats_ext = (void *)
4461 ((uint8_t *)bp->hw_rx_port_stats +
4462 sizeof(struct rx_port_stats));
4463 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4464 sizeof(struct rx_port_stats);
4465 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4467 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4468 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4469 bp->hw_tx_port_stats_ext = (void *)
4470 ((uint8_t *)bp->hw_tx_port_stats +
4471 sizeof(struct tx_port_stats));
4472 bp->hw_tx_port_stats_ext_map =
4473 bp->hw_tx_port_stats_map +
4474 sizeof(struct tx_port_stats);
4475 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4481 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4483 struct bnxt *bp = eth_dev->data->dev_private;
4486 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4487 RTE_ETHER_ADDR_LEN *
4490 if (eth_dev->data->mac_addrs == NULL) {
4491 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4495 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4499 /* Generate a random MAC address, if none was assigned by PF */
4500 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4501 bnxt_eth_hw_addr_random(bp->mac_addr);
4503 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4504 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4505 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4507 rc = bnxt_hwrm_set_mac(bp);
4509 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4510 RTE_ETHER_ADDR_LEN);
4514 /* Copy the permanent MAC from the FUNC_QCAPS response */
4515 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4516 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4521 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4525 /* MAC is already configured in FW */
4526 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4529 /* Restore the old MAC configured */
4530 rc = bnxt_hwrm_set_mac(bp);
4532 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4537 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4542 #define ALLOW_FUNC(x) \
4544 uint32_t arg = (x); \
4545 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4546 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4549 /* Forward all requests if firmware is new enough */
4550 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4551 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4552 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4553 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4555 PMD_DRV_LOG(WARNING,
4556 "Firmware too old for VF mailbox functionality\n");
4557 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4561 * The following are used for driver cleanup. If we disallow these,
4562 * VF drivers can't clean up cleanly.
4564 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4565 ALLOW_FUNC(HWRM_VNIC_FREE);
4566 ALLOW_FUNC(HWRM_RING_FREE);
4567 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4568 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4569 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4570 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4571 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4572 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4575 static int bnxt_init_fw(struct bnxt *bp)
4580 rc = bnxt_hwrm_ver_get(bp);
4584 rc = bnxt_hwrm_func_reset(bp);
4588 rc = bnxt_hwrm_vnic_qcaps(bp);
4592 rc = bnxt_hwrm_queue_qportcfg(bp);
4596 /* Get the MAX capabilities for this function.
4597 * This function also allocates context memory for TQM rings and
4598 * informs the firmware about this allocated backing store memory.
4600 rc = bnxt_hwrm_func_qcaps(bp);
4604 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4608 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4612 /* Get the adapter error recovery support info */
4613 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4615 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4617 if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4618 mtu != bp->eth_dev->data->mtu)
4619 bp->eth_dev->data->mtu = mtu;
4621 bnxt_hwrm_port_led_qcaps(bp);
4627 bnxt_init_locks(struct bnxt *bp)
4631 err = pthread_mutex_init(&bp->flow_lock, NULL);
4633 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4637 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4641 rc = bnxt_init_fw(bp);
4645 if (!reconfig_dev) {
4646 rc = bnxt_setup_mac_addr(bp->eth_dev);
4650 rc = bnxt_restore_dflt_mac(bp);
4655 bnxt_config_vf_req_fwd(bp);
4657 rc = bnxt_hwrm_func_driver_register(bp);
4659 PMD_DRV_LOG(ERR, "Failed to register driver");
4664 if (bp->pdev->max_vfs) {
4665 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4667 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4671 rc = bnxt_hwrm_allocate_pf_only(bp);
4674 "Failed to allocate PF resources");
4680 rc = bnxt_alloc_mem(bp, reconfig_dev);
4684 rc = bnxt_setup_int(bp);
4690 rc = bnxt_request_int(bp);
4694 rc = bnxt_init_locks(bp);
4702 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4704 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4705 static int version_printed;
4709 if (version_printed++ == 0)
4710 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4712 eth_dev->dev_ops = &bnxt_dev_ops;
4713 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4714 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4717 * For secondary processes, we don't initialise any further
4718 * as primary has already done this work.
4720 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4723 rte_eth_copy_pci_info(eth_dev, pci_dev);
4725 bp = eth_dev->data->dev_private;
4727 bp->dev_stopped = 1;
4729 if (bnxt_vf_pciid(pci_dev->id.device_id))
4730 bp->flags |= BNXT_FLAG_VF;
4732 if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4733 pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4734 pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4735 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4736 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4737 bp->flags |= BNXT_FLAG_THOR_CHIP;
4739 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4740 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4741 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4742 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4743 bp->flags |= BNXT_FLAG_STINGRAY;
4745 rc = bnxt_init_board(eth_dev);
4748 "Failed to initialize board rc: %x\n", rc);
4752 rc = bnxt_alloc_hwrm_resources(bp);
4755 "Failed to allocate hwrm resource rc: %x\n", rc);
4758 rc = bnxt_init_resources(bp, false);
4762 rc = bnxt_alloc_stats_mem(bp);
4767 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4768 pci_dev->mem_resource[0].phys_addr,
4769 pci_dev->mem_resource[0].addr);
4774 bnxt_dev_uninit(eth_dev);
4779 bnxt_uninit_locks(struct bnxt *bp)
4781 pthread_mutex_destroy(&bp->flow_lock);
4785 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4790 bnxt_free_mem(bp, reconfig_dev);
4791 bnxt_hwrm_func_buf_unrgtr(bp);
4792 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4793 bp->flags &= ~BNXT_FLAG_REGISTERED;
4794 bnxt_free_ctx_mem(bp);
4795 if (!reconfig_dev) {
4796 bnxt_free_hwrm_resources(bp);
4798 if (bp->recovery_info != NULL) {
4799 rte_free(bp->recovery_info);
4800 bp->recovery_info = NULL;
4804 rte_free(bp->ptp_cfg);
4810 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4812 struct bnxt *bp = eth_dev->data->dev_private;
4815 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4818 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4820 rc = bnxt_uninit_resources(bp, false);
4822 if (bp->grp_info != NULL) {
4823 rte_free(bp->grp_info);
4824 bp->grp_info = NULL;
4827 if (bp->tx_mem_zone) {
4828 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4829 bp->tx_mem_zone = NULL;
4832 if (bp->rx_mem_zone) {
4833 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4834 bp->rx_mem_zone = NULL;
4837 if (bp->dev_stopped == 0)
4838 bnxt_dev_close_op(eth_dev);
4840 rte_free(bp->pf.vf_info);
4841 eth_dev->dev_ops = NULL;
4842 eth_dev->rx_pkt_burst = NULL;
4843 eth_dev->tx_pkt_burst = NULL;
4845 bnxt_uninit_locks(bp);
4850 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4851 struct rte_pci_device *pci_dev)
4853 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4857 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4859 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4860 return rte_eth_dev_pci_generic_remove(pci_dev,
4863 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4866 static struct rte_pci_driver bnxt_rte_pmd = {
4867 .id_table = bnxt_pci_id_map,
4868 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4869 .probe = bnxt_pci_probe,
4870 .remove = bnxt_pci_remove,
4874 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4876 if (strcmp(dev->device->driver->name, drv->driver.name))
4882 bool is_bnxt_supported(struct rte_eth_dev *dev)
4884 return is_device_supported(dev, &bnxt_rte_pmd);
4887 RTE_INIT(bnxt_init_log)
4889 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4890 if (bnxt_logtype_driver >= 0)
4891 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4894 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4895 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4896 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");