1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
18 #include "bnxt_filter.h"
19 #include "bnxt_hwrm.h"
21 #include "bnxt_reps.h"
22 #include "bnxt_ring.h"
25 #include "bnxt_stats.h"
28 #include "bnxt_vnic.h"
29 #include "hsi_struct_def_dpdk.h"
30 #include "bnxt_nvm_defs.h"
31 #include "bnxt_tf_common.h"
32 #include "ulp_flow_db.h"
34 #define DRV_MODULE_NAME "bnxt"
35 static const char bnxt_version[] =
36 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
39 * The set of PCI devices this driver supports
41 static const struct rte_pci_id bnxt_pci_id_map[] = {
42 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
43 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
95 { .vendor_id = 0, /* sentinel */ },
98 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
99 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
100 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
101 #define BNXT_DEVARG_REPRESENTOR "representor"
103 static const char *const bnxt_dev_args[] = {
104 BNXT_DEVARG_REPRESENTOR,
106 BNXT_DEVARG_FLOW_XSTAT,
107 BNXT_DEVARG_MAX_NUM_KFLOWS,
112 * truflow == false to disable the feature
113 * truflow == true to enable the feature
115 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
118 * flow_xstat == false to disable the feature
119 * flow_xstat == true to enable the feature
121 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
124 * max_num_kflows must be >= 32
125 * and must be a power-of-2 supported value
126 * return: 1 -> invalid
129 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
131 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
136 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
137 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
138 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
139 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
140 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
141 static int bnxt_restore_vlan_filters(struct bnxt *bp);
142 static void bnxt_dev_recover(void *arg);
143 static void bnxt_free_error_recovery_info(struct bnxt *bp);
144 static void bnxt_free_rep_info(struct bnxt *bp);
146 int is_bnxt_in_error(struct bnxt *bp)
148 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
150 if (bp->flags & BNXT_FLAG_FW_RESET)
156 /***********************/
159 * High level utility functions
162 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
164 if (!BNXT_CHIP_THOR(bp))
167 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
168 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
169 BNXT_RSS_ENTRIES_PER_CTX_THOR;
172 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
174 if (!BNXT_CHIP_THOR(bp))
175 return HW_HASH_INDEX_SIZE;
177 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
180 static void bnxt_free_parent_info(struct bnxt *bp)
182 rte_free(bp->parent);
185 static void bnxt_free_pf_info(struct bnxt *bp)
190 static void bnxt_free_link_info(struct bnxt *bp)
192 rte_free(bp->link_info);
195 static void bnxt_free_leds_info(struct bnxt *bp)
204 static void bnxt_free_flow_stats_info(struct bnxt *bp)
206 rte_free(bp->flow_stat);
207 bp->flow_stat = NULL;
210 static void bnxt_free_cos_queues(struct bnxt *bp)
212 rte_free(bp->rx_cos_queue);
213 rte_free(bp->tx_cos_queue);
216 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
218 bnxt_free_filter_mem(bp);
219 bnxt_free_vnic_attributes(bp);
220 bnxt_free_vnic_mem(bp);
222 /* tx/rx rings are configured as part of *_queue_setup callbacks.
223 * If the number of rings change across fw update,
224 * we don't have much choice except to warn the user.
228 bnxt_free_tx_rings(bp);
229 bnxt_free_rx_rings(bp);
231 bnxt_free_async_cp_ring(bp);
232 bnxt_free_rxtx_nq_ring(bp);
234 rte_free(bp->grp_info);
238 static int bnxt_alloc_parent_info(struct bnxt *bp)
240 bp->parent = rte_zmalloc("bnxt_parent_info",
241 sizeof(struct bnxt_parent_info), 0);
242 if (bp->parent == NULL)
248 static int bnxt_alloc_pf_info(struct bnxt *bp)
250 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
257 static int bnxt_alloc_link_info(struct bnxt *bp)
260 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
261 if (bp->link_info == NULL)
267 static int bnxt_alloc_leds_info(struct bnxt *bp)
272 bp->leds = rte_zmalloc("bnxt_leds",
273 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
275 if (bp->leds == NULL)
281 static int bnxt_alloc_cos_queues(struct bnxt *bp)
284 rte_zmalloc("bnxt_rx_cosq",
285 BNXT_COS_QUEUE_COUNT *
286 sizeof(struct bnxt_cos_queue_info),
288 if (bp->rx_cos_queue == NULL)
292 rte_zmalloc("bnxt_tx_cosq",
293 BNXT_COS_QUEUE_COUNT *
294 sizeof(struct bnxt_cos_queue_info),
296 if (bp->tx_cos_queue == NULL)
302 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
304 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
305 sizeof(struct bnxt_flow_stat_info), 0);
306 if (bp->flow_stat == NULL)
312 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
316 rc = bnxt_alloc_ring_grps(bp);
320 rc = bnxt_alloc_async_ring_struct(bp);
324 rc = bnxt_alloc_vnic_mem(bp);
328 rc = bnxt_alloc_vnic_attributes(bp);
332 rc = bnxt_alloc_filter_mem(bp);
336 rc = bnxt_alloc_async_cp_ring(bp);
340 rc = bnxt_alloc_rxtx_nq_ring(bp);
344 if (BNXT_FLOW_XSTATS_EN(bp)) {
345 rc = bnxt_alloc_flow_stats_info(bp);
353 bnxt_free_mem(bp, reconfig);
357 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
359 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
360 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
361 uint64_t rx_offloads = dev_conf->rxmode.offloads;
362 struct bnxt_rx_queue *rxq;
366 rc = bnxt_vnic_grp_alloc(bp, vnic);
370 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
371 vnic_id, vnic, vnic->fw_grp_ids);
373 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
377 /* Alloc RSS context only if RSS mode is enabled */
378 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
379 int j, nr_ctxs = bnxt_rss_ctxts(bp);
382 for (j = 0; j < nr_ctxs; j++) {
383 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
389 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
393 vnic->num_lb_ctxts = nr_ctxs;
397 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
398 * setting is not available at this time, it will not be
399 * configured correctly in the CFA.
401 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
402 vnic->vlan_strip = true;
404 vnic->vlan_strip = false;
406 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
410 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
414 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
415 rxq = bp->eth_dev->data->rx_queues[j];
418 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
419 j, rxq->vnic, rxq->vnic->fw_grp_ids);
421 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
422 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
424 vnic->rx_queue_cnt++;
427 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
429 rc = bnxt_vnic_rss_configure(bp, vnic);
433 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
435 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
436 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
438 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
442 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
447 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
451 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
452 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
457 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
458 " rx_fc_in_tbl.ctx_id = %d\n",
459 bp->flow_stat->rx_fc_in_tbl.va,
460 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
461 bp->flow_stat->rx_fc_in_tbl.ctx_id);
463 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
464 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
469 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
470 " rx_fc_out_tbl.ctx_id = %d\n",
471 bp->flow_stat->rx_fc_out_tbl.va,
472 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
473 bp->flow_stat->rx_fc_out_tbl.ctx_id);
475 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
476 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
481 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
482 " tx_fc_in_tbl.ctx_id = %d\n",
483 bp->flow_stat->tx_fc_in_tbl.va,
484 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
485 bp->flow_stat->tx_fc_in_tbl.ctx_id);
487 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
488 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
493 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
494 " tx_fc_out_tbl.ctx_id = %d\n",
495 bp->flow_stat->tx_fc_out_tbl.va,
496 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
497 bp->flow_stat->tx_fc_out_tbl.ctx_id);
499 memset(bp->flow_stat->rx_fc_out_tbl.va,
501 bp->flow_stat->rx_fc_out_tbl.size);
502 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
503 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
504 bp->flow_stat->rx_fc_out_tbl.ctx_id,
505 bp->flow_stat->max_fc,
510 memset(bp->flow_stat->tx_fc_out_tbl.va,
512 bp->flow_stat->tx_fc_out_tbl.size);
513 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
514 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
515 bp->flow_stat->tx_fc_out_tbl.ctx_id,
516 bp->flow_stat->max_fc,
522 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
523 struct bnxt_ctx_mem_buf_info *ctx)
528 ctx->va = rte_zmalloc(type, size, 0);
531 rte_mem_lock_page(ctx->va);
533 ctx->dma = rte_mem_virt2iova(ctx->va);
534 if (ctx->dma == RTE_BAD_IOVA)
540 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
542 struct rte_pci_device *pdev = bp->pdev;
543 char type[RTE_MEMZONE_NAMESIZE];
547 max_fc = bp->flow_stat->max_fc;
549 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
550 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
551 /* 4 bytes for each counter-id */
552 rc = bnxt_alloc_ctx_mem_buf(type,
554 &bp->flow_stat->rx_fc_in_tbl);
558 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
559 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
560 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
561 rc = bnxt_alloc_ctx_mem_buf(type,
563 &bp->flow_stat->rx_fc_out_tbl);
567 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
568 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
569 /* 4 bytes for each counter-id */
570 rc = bnxt_alloc_ctx_mem_buf(type,
572 &bp->flow_stat->tx_fc_in_tbl);
576 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
577 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
578 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
579 rc = bnxt_alloc_ctx_mem_buf(type,
581 &bp->flow_stat->tx_fc_out_tbl);
585 rc = bnxt_register_fc_ctx_mem(bp);
590 static int bnxt_init_ctx_mem(struct bnxt *bp)
594 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
595 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
596 !BNXT_FLOW_XSTATS_EN(bp))
599 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
603 rc = bnxt_init_fc_ctx_mem(bp);
608 static int bnxt_update_phy_setting(struct bnxt *bp)
610 struct rte_eth_link new;
613 rc = bnxt_get_hwrm_link_config(bp, &new);
615 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
620 * On BCM957508-N2100 adapters, FW will not allow any user other
621 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
622 * always returns link up. Force phy update always in that case.
624 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
625 rc = bnxt_set_hwrm_link_config(bp, true);
627 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
635 static int bnxt_init_chip(struct bnxt *bp)
637 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
638 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
639 uint32_t intr_vector = 0;
640 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
641 uint32_t vec = BNXT_MISC_VEC_ID;
645 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
646 bp->eth_dev->data->dev_conf.rxmode.offloads |=
647 DEV_RX_OFFLOAD_JUMBO_FRAME;
648 bp->flags |= BNXT_FLAG_JUMBO;
650 bp->eth_dev->data->dev_conf.rxmode.offloads &=
651 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
652 bp->flags &= ~BNXT_FLAG_JUMBO;
655 /* THOR does not support ring groups.
656 * But we will use the array to save RSS context IDs.
658 if (BNXT_CHIP_THOR(bp))
659 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
661 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
663 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
667 rc = bnxt_alloc_hwrm_rings(bp);
669 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
673 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
675 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
679 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
682 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
683 if (bp->rx_cos_queue[i].id != 0xff) {
684 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
688 "Num pools more than FW profile\n");
692 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
698 rc = bnxt_mq_rx_configure(bp);
700 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
704 /* VNIC configuration */
705 for (i = 0; i < bp->nr_vnics; i++) {
706 rc = bnxt_setup_one_vnic(bp, i);
711 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
714 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
718 /* check and configure queue intr-vector mapping */
719 if ((rte_intr_cap_multiple(intr_handle) ||
720 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
721 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
722 intr_vector = bp->eth_dev->data->nb_rx_queues;
723 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
724 if (intr_vector > bp->rx_cp_nr_rings) {
725 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
729 rc = rte_intr_efd_enable(intr_handle, intr_vector);
734 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
735 intr_handle->intr_vec =
736 rte_zmalloc("intr_vec",
737 bp->eth_dev->data->nb_rx_queues *
739 if (intr_handle->intr_vec == NULL) {
740 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
741 " intr_vec", bp->eth_dev->data->nb_rx_queues);
745 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
746 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
747 intr_handle->intr_vec, intr_handle->nb_efd,
748 intr_handle->max_intr);
749 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
751 intr_handle->intr_vec[queue_id] =
752 vec + BNXT_RX_VEC_START;
753 if (vec < base + intr_handle->nb_efd - 1)
758 /* enable uio/vfio intr/eventfd mapping */
759 rc = rte_intr_enable(intr_handle);
760 #ifndef RTE_EXEC_ENV_FREEBSD
761 /* In FreeBSD OS, nic_uio driver does not support interrupts */
766 rc = bnxt_update_phy_setting(bp);
770 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
772 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
777 rte_free(intr_handle->intr_vec);
779 rte_intr_efd_disable(intr_handle);
781 /* Some of the error status returned by FW may not be from errno.h */
788 static int bnxt_shutdown_nic(struct bnxt *bp)
790 bnxt_free_all_hwrm_resources(bp);
791 bnxt_free_all_filters(bp);
792 bnxt_free_all_vnics(bp);
797 * Device configuration and status function
800 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
802 uint32_t link_speed = bp->link_info->support_speeds;
803 uint32_t speed_capa = 0;
805 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
806 speed_capa |= ETH_LINK_SPEED_100M;
807 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
808 speed_capa |= ETH_LINK_SPEED_100M_HD;
809 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
810 speed_capa |= ETH_LINK_SPEED_1G;
811 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
812 speed_capa |= ETH_LINK_SPEED_2_5G;
813 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
814 speed_capa |= ETH_LINK_SPEED_10G;
815 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
816 speed_capa |= ETH_LINK_SPEED_20G;
817 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
818 speed_capa |= ETH_LINK_SPEED_25G;
819 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
820 speed_capa |= ETH_LINK_SPEED_40G;
821 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
822 speed_capa |= ETH_LINK_SPEED_50G;
823 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
824 speed_capa |= ETH_LINK_SPEED_100G;
825 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
826 speed_capa |= ETH_LINK_SPEED_200G;
828 if (bp->link_info->auto_mode ==
829 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
830 speed_capa |= ETH_LINK_SPEED_FIXED;
832 speed_capa |= ETH_LINK_SPEED_AUTONEG;
837 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
838 struct rte_eth_dev_info *dev_info)
840 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
841 struct bnxt *bp = eth_dev->data->dev_private;
842 uint16_t max_vnics, i, j, vpool, vrxq;
843 unsigned int max_rx_rings;
846 rc = is_bnxt_in_error(bp);
851 dev_info->max_mac_addrs = bp->max_l2_ctx;
852 dev_info->max_hash_mac_addrs = 0;
854 /* PF/VF specifics */
856 dev_info->max_vfs = pdev->max_vfs;
858 max_rx_rings = BNXT_MAX_RINGS(bp);
859 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
860 dev_info->max_rx_queues = max_rx_rings;
861 dev_info->max_tx_queues = max_rx_rings;
862 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
863 dev_info->hash_key_size = 40;
864 max_vnics = bp->max_vnics;
867 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
868 dev_info->max_mtu = BNXT_MAX_MTU;
870 /* Fast path specifics */
871 dev_info->min_rx_bufsize = 1;
872 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
874 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
875 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
876 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
877 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
878 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
880 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
883 dev_info->default_rxconf = (struct rte_eth_rxconf) {
889 .rx_free_thresh = 32,
890 /* If no descriptors available, pkts are dropped by default */
894 dev_info->default_txconf = (struct rte_eth_txconf) {
900 .tx_free_thresh = 32,
903 eth_dev->data->dev_conf.intr_conf.lsc = 1;
905 eth_dev->data->dev_conf.intr_conf.rxq = 1;
906 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
907 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
908 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
909 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
914 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
915 * need further investigation.
919 vpool = 64; /* ETH_64_POOLS */
920 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
921 for (i = 0; i < 4; vpool >>= 1, i++) {
922 if (max_vnics > vpool) {
923 for (j = 0; j < 5; vrxq >>= 1, j++) {
924 if (dev_info->max_rx_queues > vrxq) {
930 /* Not enough resources to support VMDq */
934 /* Not enough resources to support VMDq */
938 dev_info->max_vmdq_pools = vpool;
939 dev_info->vmdq_queue_num = vrxq;
941 dev_info->vmdq_pool_base = 0;
942 dev_info->vmdq_queue_base = 0;
947 /* Configure the device based on the configuration provided */
948 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
950 struct bnxt *bp = eth_dev->data->dev_private;
951 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
954 bp->rx_queues = (void *)eth_dev->data->rx_queues;
955 bp->tx_queues = (void *)eth_dev->data->tx_queues;
956 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
957 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
959 rc = is_bnxt_in_error(bp);
963 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
964 rc = bnxt_hwrm_check_vf_rings(bp);
966 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
970 /* If a resource has already been allocated - in this case
971 * it is the async completion ring, free it. Reallocate it after
972 * resource reservation. This will ensure the resource counts
973 * are calculated correctly.
976 pthread_mutex_lock(&bp->def_cp_lock);
978 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
979 bnxt_disable_int(bp);
980 bnxt_free_cp_ring(bp, bp->async_cp_ring);
983 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
985 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
986 pthread_mutex_unlock(&bp->def_cp_lock);
990 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
991 rc = bnxt_alloc_async_cp_ring(bp);
993 pthread_mutex_unlock(&bp->def_cp_lock);
999 pthread_mutex_unlock(&bp->def_cp_lock);
1001 /* legacy driver needs to get updated values */
1002 rc = bnxt_hwrm_func_qcaps(bp);
1004 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
1009 /* Inherit new configurations */
1010 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1011 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1012 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1013 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1014 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1016 goto resource_error;
1018 if (BNXT_HAS_RING_GRPS(bp) &&
1019 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1020 goto resource_error;
1022 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1023 bp->max_vnics < eth_dev->data->nb_rx_queues)
1024 goto resource_error;
1026 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1027 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1029 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1030 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1031 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1033 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1034 eth_dev->data->mtu =
1035 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1036 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1038 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1044 "Insufficient resources to support requested config\n");
1046 "Num Queues Requested: Tx %d, Rx %d\n",
1047 eth_dev->data->nb_tx_queues,
1048 eth_dev->data->nb_rx_queues);
1050 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1051 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1052 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1056 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1058 struct rte_eth_link *link = ð_dev->data->dev_link;
1060 if (link->link_status)
1061 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1062 eth_dev->data->port_id,
1063 (uint32_t)link->link_speed,
1064 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1065 ("full-duplex") : ("half-duplex\n"));
1067 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1068 eth_dev->data->port_id);
1072 * Determine whether the current configuration requires support for scattered
1073 * receive; return 1 if scattered receive is required and 0 if not.
1075 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1080 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1083 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1084 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1086 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1087 RTE_PKTMBUF_HEADROOM);
1088 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1094 static eth_rx_burst_t
1095 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1097 struct bnxt *bp = eth_dev->data->dev_private;
1099 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1100 #ifndef RTE_LIBRTE_IEEE1588
1102 * Vector mode receive can be enabled only if scatter rx is not
1103 * in use and rx offloads are limited to VLAN stripping and
1106 if (!eth_dev->data->scattered_rx &&
1107 !(eth_dev->data->dev_conf.rxmode.offloads &
1108 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1109 DEV_RX_OFFLOAD_KEEP_CRC |
1110 DEV_RX_OFFLOAD_JUMBO_FRAME |
1111 DEV_RX_OFFLOAD_IPV4_CKSUM |
1112 DEV_RX_OFFLOAD_UDP_CKSUM |
1113 DEV_RX_OFFLOAD_TCP_CKSUM |
1114 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1115 DEV_RX_OFFLOAD_RSS_HASH |
1116 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1117 !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp)) {
1118 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1119 eth_dev->data->port_id);
1120 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1121 return bnxt_recv_pkts_vec;
1123 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1124 eth_dev->data->port_id);
1126 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1127 eth_dev->data->port_id,
1128 eth_dev->data->scattered_rx,
1129 eth_dev->data->dev_conf.rxmode.offloads);
1132 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1133 return bnxt_recv_pkts;
1136 static eth_tx_burst_t
1137 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1139 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1140 #ifndef RTE_LIBRTE_IEEE1588
1141 struct bnxt *bp = eth_dev->data->dev_private;
1144 * Vector mode transmit can be enabled only if not using scatter rx
1147 if (!eth_dev->data->scattered_rx &&
1148 !eth_dev->data->dev_conf.txmode.offloads &&
1149 !BNXT_TRUFLOW_EN(bp)) {
1150 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1151 eth_dev->data->port_id);
1152 return bnxt_xmit_pkts_vec;
1154 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1155 eth_dev->data->port_id);
1157 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1158 eth_dev->data->port_id,
1159 eth_dev->data->scattered_rx,
1160 eth_dev->data->dev_conf.txmode.offloads);
1163 return bnxt_xmit_pkts;
1166 static int bnxt_handle_if_change_status(struct bnxt *bp)
1170 /* Since fw has undergone a reset and lost all contexts,
1171 * set fatal flag to not issue hwrm during cleanup
1173 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1174 bnxt_uninit_resources(bp, true);
1176 /* clear fatal flag so that re-init happens */
1177 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1178 rc = bnxt_init_resources(bp, true);
1180 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1185 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1187 struct bnxt *bp = eth_dev->data->dev_private;
1188 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1190 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1192 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1193 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1197 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1199 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1200 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1204 rc = bnxt_hwrm_if_change(bp, true);
1205 if (rc == 0 || rc != -EAGAIN)
1208 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1209 } while (retry_cnt--);
1214 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1215 rc = bnxt_handle_if_change_status(bp);
1220 bnxt_enable_int(bp);
1222 rc = bnxt_init_chip(bp);
1226 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1227 eth_dev->data->dev_started = 1;
1229 bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1231 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1232 vlan_mask |= ETH_VLAN_FILTER_MASK;
1233 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1234 vlan_mask |= ETH_VLAN_STRIP_MASK;
1235 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1239 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1240 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1242 pthread_mutex_lock(&bp->def_cp_lock);
1243 bnxt_schedule_fw_health_check(bp);
1244 pthread_mutex_unlock(&bp->def_cp_lock);
1251 bnxt_shutdown_nic(bp);
1252 bnxt_free_tx_mbufs(bp);
1253 bnxt_free_rx_mbufs(bp);
1254 bnxt_hwrm_if_change(bp, false);
1255 eth_dev->data->dev_started = 0;
1259 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1261 struct bnxt *bp = eth_dev->data->dev_private;
1264 if (!bp->link_info->link_up)
1265 rc = bnxt_set_hwrm_link_config(bp, true);
1267 eth_dev->data->dev_link.link_status = 1;
1269 bnxt_print_link_info(eth_dev);
1273 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1275 struct bnxt *bp = eth_dev->data->dev_private;
1277 eth_dev->data->dev_link.link_status = 0;
1278 bnxt_set_hwrm_link_config(bp, false);
1279 bp->link_info->link_up = 0;
1284 static void bnxt_free_switch_domain(struct bnxt *bp)
1286 if (bp->switch_domain_id)
1287 rte_eth_switch_domain_free(bp->switch_domain_id);
1290 /* Unload the driver, release resources */
1291 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1293 struct bnxt *bp = eth_dev->data->dev_private;
1294 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1295 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1297 eth_dev->data->dev_started = 0;
1298 eth_dev->data->scattered_rx = 0;
1300 /* Prevent crashes when queues are still in use */
1301 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1302 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1304 bnxt_disable_int(bp);
1306 /* disable uio/vfio intr/eventfd mapping */
1307 rte_intr_disable(intr_handle);
1309 bnxt_ulp_destroy_df_rules(bp, false);
1310 bnxt_ulp_deinit(bp);
1312 bnxt_cancel_fw_health_check(bp);
1314 bnxt_dev_set_link_down_op(eth_dev);
1316 /* Wait for link to be reset and the async notification to process.
1317 * During reset recovery, there is no need to wait and
1318 * VF/NPAR functions do not have privilege to change PHY config.
1320 if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1321 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1323 /* Clean queue intr-vector mapping */
1324 rte_intr_efd_disable(intr_handle);
1325 if (intr_handle->intr_vec != NULL) {
1326 rte_free(intr_handle->intr_vec);
1327 intr_handle->intr_vec = NULL;
1330 bnxt_hwrm_port_clr_stats(bp);
1331 bnxt_free_tx_mbufs(bp);
1332 bnxt_free_rx_mbufs(bp);
1333 /* Process any remaining notifications in default completion queue */
1334 bnxt_int_handler(eth_dev);
1335 bnxt_shutdown_nic(bp);
1336 bnxt_hwrm_if_change(bp, false);
1338 rte_free(bp->mark_table);
1339 bp->mark_table = NULL;
1341 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1342 bp->rx_cosq_cnt = 0;
1343 /* All filters are deleted on a port stop. */
1344 if (BNXT_FLOW_XSTATS_EN(bp))
1345 bp->flow_stat->flow_count = 0;
1348 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1350 struct bnxt *bp = eth_dev->data->dev_private;
1352 /* cancel the recovery handler before remove dev */
1353 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1354 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1355 bnxt_cancel_fc_thread(bp);
1357 if (eth_dev->data->dev_started)
1358 bnxt_dev_stop_op(eth_dev);
1360 bnxt_free_switch_domain(bp);
1362 bnxt_uninit_resources(bp, false);
1364 bnxt_free_leds_info(bp);
1365 bnxt_free_cos_queues(bp);
1366 bnxt_free_link_info(bp);
1367 bnxt_free_pf_info(bp);
1368 bnxt_free_parent_info(bp);
1370 eth_dev->dev_ops = NULL;
1371 eth_dev->rx_pkt_burst = NULL;
1372 eth_dev->tx_pkt_burst = NULL;
1374 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1375 bp->tx_mem_zone = NULL;
1376 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1377 bp->rx_mem_zone = NULL;
1379 bnxt_hwrm_free_vf_info(bp);
1381 rte_free(bp->grp_info);
1382 bp->grp_info = NULL;
1385 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1388 struct bnxt *bp = eth_dev->data->dev_private;
1389 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1390 struct bnxt_vnic_info *vnic;
1391 struct bnxt_filter_info *filter, *temp_filter;
1394 if (is_bnxt_in_error(bp))
1398 * Loop through all VNICs from the specified filter flow pools to
1399 * remove the corresponding MAC addr filter
1401 for (i = 0; i < bp->nr_vnics; i++) {
1402 if (!(pool_mask & (1ULL << i)))
1405 vnic = &bp->vnic_info[i];
1406 filter = STAILQ_FIRST(&vnic->filter);
1408 temp_filter = STAILQ_NEXT(filter, next);
1409 if (filter->mac_index == index) {
1410 STAILQ_REMOVE(&vnic->filter, filter,
1411 bnxt_filter_info, next);
1412 bnxt_hwrm_clear_l2_filter(bp, filter);
1413 bnxt_free_filter(bp, filter);
1415 filter = temp_filter;
1420 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1421 struct rte_ether_addr *mac_addr, uint32_t index,
1424 struct bnxt_filter_info *filter;
1427 /* Attach requested MAC address to the new l2_filter */
1428 STAILQ_FOREACH(filter, &vnic->filter, next) {
1429 if (filter->mac_index == index) {
1431 "MAC addr already existed for pool %d\n",
1437 filter = bnxt_alloc_filter(bp);
1439 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1443 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1444 * if the MAC that's been programmed now is a different one, then,
1445 * copy that addr to filter->l2_addr
1448 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1449 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1451 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1453 filter->mac_index = index;
1454 if (filter->mac_index == 0)
1455 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1457 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1459 bnxt_free_filter(bp, filter);
1465 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1466 struct rte_ether_addr *mac_addr,
1467 uint32_t index, uint32_t pool)
1469 struct bnxt *bp = eth_dev->data->dev_private;
1470 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1473 rc = is_bnxt_in_error(bp);
1477 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1478 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1483 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1487 /* Filter settings will get applied when port is started */
1488 if (!eth_dev->data->dev_started)
1491 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1496 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1497 bool exp_link_status)
1500 struct bnxt *bp = eth_dev->data->dev_private;
1501 struct rte_eth_link new;
1502 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1503 BNXT_LINK_DOWN_WAIT_CNT;
1505 rc = is_bnxt_in_error(bp);
1509 memset(&new, 0, sizeof(new));
1511 /* Retrieve link info from hardware */
1512 rc = bnxt_get_hwrm_link_config(bp, &new);
1514 new.link_speed = ETH_LINK_SPEED_100M;
1515 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1517 "Failed to retrieve link rc = 0x%x!\n", rc);
1521 if (!wait_to_complete || new.link_status == exp_link_status)
1524 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1528 /* Timed out or success */
1529 if (new.link_status != eth_dev->data->dev_link.link_status ||
1530 new.link_speed != eth_dev->data->dev_link.link_speed) {
1531 rte_eth_linkstatus_set(eth_dev, &new);
1533 rte_eth_dev_callback_process(eth_dev,
1534 RTE_ETH_EVENT_INTR_LSC,
1537 bnxt_print_link_info(eth_dev);
1543 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1544 int wait_to_complete)
1546 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1549 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1551 struct bnxt *bp = eth_dev->data->dev_private;
1552 struct bnxt_vnic_info *vnic;
1556 rc = is_bnxt_in_error(bp);
1560 /* Filter settings will get applied when port is started */
1561 if (!eth_dev->data->dev_started)
1564 if (bp->vnic_info == NULL)
1567 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1569 old_flags = vnic->flags;
1570 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1571 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1573 vnic->flags = old_flags;
1578 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1580 struct bnxt *bp = eth_dev->data->dev_private;
1581 struct bnxt_vnic_info *vnic;
1585 rc = is_bnxt_in_error(bp);
1589 /* Filter settings will get applied when port is started */
1590 if (!eth_dev->data->dev_started)
1593 if (bp->vnic_info == NULL)
1596 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1598 old_flags = vnic->flags;
1599 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1600 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1602 vnic->flags = old_flags;
1604 bnxt_ulp_create_df_rules(bp);
1609 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1611 struct bnxt *bp = eth_dev->data->dev_private;
1612 struct bnxt_vnic_info *vnic;
1616 rc = is_bnxt_in_error(bp);
1620 /* Filter settings will get applied when port is started */
1621 if (!eth_dev->data->dev_started)
1624 if (bp->vnic_info == NULL)
1627 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1629 old_flags = vnic->flags;
1630 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1631 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1633 vnic->flags = old_flags;
1638 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1640 struct bnxt *bp = eth_dev->data->dev_private;
1641 struct bnxt_vnic_info *vnic;
1645 rc = is_bnxt_in_error(bp);
1649 /* Filter settings will get applied when port is started */
1650 if (!eth_dev->data->dev_started)
1653 if (bp->vnic_info == NULL)
1656 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1658 old_flags = vnic->flags;
1659 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1660 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1662 vnic->flags = old_flags;
1667 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1668 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1670 if (qid >= bp->rx_nr_rings)
1673 return bp->eth_dev->data->rx_queues[qid];
1676 /* Return rxq corresponding to a given rss table ring/group ID. */
1677 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1679 struct bnxt_rx_queue *rxq;
1682 if (!BNXT_HAS_RING_GRPS(bp)) {
1683 for (i = 0; i < bp->rx_nr_rings; i++) {
1684 rxq = bp->eth_dev->data->rx_queues[i];
1685 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1689 for (i = 0; i < bp->rx_nr_rings; i++) {
1690 if (bp->grp_info[i].fw_grp_id == fwr)
1695 return INVALID_HW_RING_ID;
1698 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1699 struct rte_eth_rss_reta_entry64 *reta_conf,
1702 struct bnxt *bp = eth_dev->data->dev_private;
1703 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1704 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1705 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1709 rc = is_bnxt_in_error(bp);
1713 if (!vnic->rss_table)
1716 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1719 if (reta_size != tbl_size) {
1720 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1721 "(%d) must equal the size supported by the hardware "
1722 "(%d)\n", reta_size, tbl_size);
1726 for (i = 0; i < reta_size; i++) {
1727 struct bnxt_rx_queue *rxq;
1729 idx = i / RTE_RETA_GROUP_SIZE;
1730 sft = i % RTE_RETA_GROUP_SIZE;
1732 if (!(reta_conf[idx].mask & (1ULL << sft)))
1735 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1737 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1741 if (BNXT_CHIP_THOR(bp)) {
1742 vnic->rss_table[i * 2] =
1743 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1744 vnic->rss_table[i * 2 + 1] =
1745 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1747 vnic->rss_table[i] =
1748 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1752 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1756 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1757 struct rte_eth_rss_reta_entry64 *reta_conf,
1760 struct bnxt *bp = eth_dev->data->dev_private;
1761 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1762 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1763 uint16_t idx, sft, i;
1766 rc = is_bnxt_in_error(bp);
1770 /* Retrieve from the default VNIC */
1773 if (!vnic->rss_table)
1776 if (reta_size != tbl_size) {
1777 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1778 "(%d) must equal the size supported by the hardware "
1779 "(%d)\n", reta_size, tbl_size);
1783 for (idx = 0, i = 0; i < reta_size; i++) {
1784 idx = i / RTE_RETA_GROUP_SIZE;
1785 sft = i % RTE_RETA_GROUP_SIZE;
1787 if (reta_conf[idx].mask & (1ULL << sft)) {
1790 if (BNXT_CHIP_THOR(bp))
1791 qid = bnxt_rss_to_qid(bp,
1792 vnic->rss_table[i * 2]);
1794 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1796 if (qid == INVALID_HW_RING_ID) {
1797 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1800 reta_conf[idx].reta[sft] = qid;
1807 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1808 struct rte_eth_rss_conf *rss_conf)
1810 struct bnxt *bp = eth_dev->data->dev_private;
1811 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1812 struct bnxt_vnic_info *vnic;
1815 rc = is_bnxt_in_error(bp);
1820 * If RSS enablement were different than dev_configure,
1821 * then return -EINVAL
1823 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1824 if (!rss_conf->rss_hf)
1825 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1827 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1831 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1832 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
1836 /* Update the default RSS VNIC(s) */
1837 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1838 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1841 * If hashkey is not specified, use the previously configured
1844 if (!rss_conf->rss_key)
1847 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1849 "Invalid hashkey length, should be 16 bytes\n");
1852 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1855 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1859 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1860 struct rte_eth_rss_conf *rss_conf)
1862 struct bnxt *bp = eth_dev->data->dev_private;
1863 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1865 uint32_t hash_types;
1867 rc = is_bnxt_in_error(bp);
1871 /* RSS configuration is the same for all VNICs */
1872 if (vnic && vnic->rss_hash_key) {
1873 if (rss_conf->rss_key) {
1874 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1875 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1876 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1879 hash_types = vnic->hash_type;
1880 rss_conf->rss_hf = 0;
1881 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1882 rss_conf->rss_hf |= ETH_RSS_IPV4;
1883 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1885 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1886 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1888 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1890 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1891 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1893 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1895 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1896 rss_conf->rss_hf |= ETH_RSS_IPV6;
1897 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1899 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1900 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1902 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1904 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1905 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1907 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1911 "Unknown RSS config from firmware (%08x), RSS disabled",
1916 rss_conf->rss_hf = 0;
1921 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1922 struct rte_eth_fc_conf *fc_conf)
1924 struct bnxt *bp = dev->data->dev_private;
1925 struct rte_eth_link link_info;
1928 rc = is_bnxt_in_error(bp);
1932 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1936 memset(fc_conf, 0, sizeof(*fc_conf));
1937 if (bp->link_info->auto_pause)
1938 fc_conf->autoneg = 1;
1939 switch (bp->link_info->pause) {
1941 fc_conf->mode = RTE_FC_NONE;
1943 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1944 fc_conf->mode = RTE_FC_TX_PAUSE;
1946 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1947 fc_conf->mode = RTE_FC_RX_PAUSE;
1949 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1950 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1951 fc_conf->mode = RTE_FC_FULL;
1957 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1958 struct rte_eth_fc_conf *fc_conf)
1960 struct bnxt *bp = dev->data->dev_private;
1963 rc = is_bnxt_in_error(bp);
1967 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1968 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1972 switch (fc_conf->mode) {
1974 bp->link_info->auto_pause = 0;
1975 bp->link_info->force_pause = 0;
1977 case RTE_FC_RX_PAUSE:
1978 if (fc_conf->autoneg) {
1979 bp->link_info->auto_pause =
1980 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1981 bp->link_info->force_pause = 0;
1983 bp->link_info->auto_pause = 0;
1984 bp->link_info->force_pause =
1985 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1988 case RTE_FC_TX_PAUSE:
1989 if (fc_conf->autoneg) {
1990 bp->link_info->auto_pause =
1991 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1992 bp->link_info->force_pause = 0;
1994 bp->link_info->auto_pause = 0;
1995 bp->link_info->force_pause =
1996 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2000 if (fc_conf->autoneg) {
2001 bp->link_info->auto_pause =
2002 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2003 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2004 bp->link_info->force_pause = 0;
2006 bp->link_info->auto_pause = 0;
2007 bp->link_info->force_pause =
2008 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2009 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2013 return bnxt_set_hwrm_link_config(bp, true);
2016 /* Add UDP tunneling port */
2018 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2019 struct rte_eth_udp_tunnel *udp_tunnel)
2021 struct bnxt *bp = eth_dev->data->dev_private;
2022 uint16_t tunnel_type = 0;
2025 rc = is_bnxt_in_error(bp);
2029 switch (udp_tunnel->prot_type) {
2030 case RTE_TUNNEL_TYPE_VXLAN:
2031 if (bp->vxlan_port_cnt) {
2032 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2033 udp_tunnel->udp_port);
2034 if (bp->vxlan_port != udp_tunnel->udp_port) {
2035 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2038 bp->vxlan_port_cnt++;
2042 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2043 bp->vxlan_port_cnt++;
2045 case RTE_TUNNEL_TYPE_GENEVE:
2046 if (bp->geneve_port_cnt) {
2047 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2048 udp_tunnel->udp_port);
2049 if (bp->geneve_port != udp_tunnel->udp_port) {
2050 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2053 bp->geneve_port_cnt++;
2057 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2058 bp->geneve_port_cnt++;
2061 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2064 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2070 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2071 struct rte_eth_udp_tunnel *udp_tunnel)
2073 struct bnxt *bp = eth_dev->data->dev_private;
2074 uint16_t tunnel_type = 0;
2078 rc = is_bnxt_in_error(bp);
2082 switch (udp_tunnel->prot_type) {
2083 case RTE_TUNNEL_TYPE_VXLAN:
2084 if (!bp->vxlan_port_cnt) {
2085 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2088 if (bp->vxlan_port != udp_tunnel->udp_port) {
2089 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2090 udp_tunnel->udp_port, bp->vxlan_port);
2093 if (--bp->vxlan_port_cnt)
2097 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2098 port = bp->vxlan_fw_dst_port_id;
2100 case RTE_TUNNEL_TYPE_GENEVE:
2101 if (!bp->geneve_port_cnt) {
2102 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2105 if (bp->geneve_port != udp_tunnel->udp_port) {
2106 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2107 udp_tunnel->udp_port, bp->geneve_port);
2110 if (--bp->geneve_port_cnt)
2114 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2115 port = bp->geneve_fw_dst_port_id;
2118 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2122 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2125 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2128 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2129 bp->geneve_port = 0;
2134 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2136 struct bnxt_filter_info *filter;
2137 struct bnxt_vnic_info *vnic;
2139 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2141 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2142 filter = STAILQ_FIRST(&vnic->filter);
2144 /* Search for this matching MAC+VLAN filter */
2145 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2146 /* Delete the filter */
2147 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2150 STAILQ_REMOVE(&vnic->filter, filter,
2151 bnxt_filter_info, next);
2152 bnxt_free_filter(bp, filter);
2154 "Deleted vlan filter for %d\n",
2158 filter = STAILQ_NEXT(filter, next);
2163 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2165 struct bnxt_filter_info *filter;
2166 struct bnxt_vnic_info *vnic;
2168 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2169 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2170 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2172 /* Implementation notes on the use of VNIC in this command:
2174 * By default, these filters belong to default vnic for the function.
2175 * Once these filters are set up, only destination VNIC can be modified.
2176 * If the destination VNIC is not specified in this command,
2177 * then the HWRM shall only create an l2 context id.
2180 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2181 filter = STAILQ_FIRST(&vnic->filter);
2182 /* Check if the VLAN has already been added */
2184 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2187 filter = STAILQ_NEXT(filter, next);
2190 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2191 * command to create MAC+VLAN filter with the right flags, enables set.
2193 filter = bnxt_alloc_filter(bp);
2196 "MAC/VLAN filter alloc failed\n");
2199 /* MAC + VLAN ID filter */
2200 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2201 * untagged packets are received
2203 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2204 * packets and only the programmed vlan's packets are received
2206 filter->l2_ivlan = vlan_id;
2207 filter->l2_ivlan_mask = 0x0FFF;
2208 filter->enables |= en;
2209 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2211 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2213 /* Free the newly allocated filter as we were
2214 * not able to create the filter in hardware.
2216 bnxt_free_filter(bp, filter);
2220 filter->mac_index = 0;
2221 /* Add this new filter to the list */
2223 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2225 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2228 "Added Vlan filter for %d\n", vlan_id);
2232 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2233 uint16_t vlan_id, int on)
2235 struct bnxt *bp = eth_dev->data->dev_private;
2238 rc = is_bnxt_in_error(bp);
2242 if (!eth_dev->data->dev_started) {
2243 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2247 /* These operations apply to ALL existing MAC/VLAN filters */
2249 return bnxt_add_vlan_filter(bp, vlan_id);
2251 return bnxt_del_vlan_filter(bp, vlan_id);
2254 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2255 struct bnxt_vnic_info *vnic)
2257 struct bnxt_filter_info *filter;
2260 filter = STAILQ_FIRST(&vnic->filter);
2262 if (filter->mac_index == 0 &&
2263 !memcmp(filter->l2_addr, bp->mac_addr,
2264 RTE_ETHER_ADDR_LEN)) {
2265 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2267 STAILQ_REMOVE(&vnic->filter, filter,
2268 bnxt_filter_info, next);
2269 bnxt_free_filter(bp, filter);
2273 filter = STAILQ_NEXT(filter, next);
2279 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2281 struct bnxt_vnic_info *vnic;
2285 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2286 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2287 /* Remove any VLAN filters programmed */
2288 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2289 bnxt_del_vlan_filter(bp, i);
2291 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2295 /* Default filter will allow packets that match the
2296 * dest mac. So, it has to be deleted, otherwise, we
2297 * will endup receiving vlan packets for which the
2298 * filter is not programmed, when hw-vlan-filter
2299 * configuration is ON
2301 bnxt_del_dflt_mac_filter(bp, vnic);
2302 /* This filter will allow only untagged packets */
2303 bnxt_add_vlan_filter(bp, 0);
2305 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2306 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2311 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2313 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2317 /* Destroy vnic filters and vnic */
2318 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2319 DEV_RX_OFFLOAD_VLAN_FILTER) {
2320 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2321 bnxt_del_vlan_filter(bp, i);
2323 bnxt_del_dflt_mac_filter(bp, vnic);
2325 rc = bnxt_hwrm_vnic_free(bp, vnic);
2329 rte_free(vnic->fw_grp_ids);
2330 vnic->fw_grp_ids = NULL;
2332 vnic->rx_queue_cnt = 0;
2338 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2340 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2343 /* Destroy, recreate and reconfigure the default vnic */
2344 rc = bnxt_free_one_vnic(bp, 0);
2348 /* default vnic 0 */
2349 rc = bnxt_setup_one_vnic(bp, 0);
2353 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2354 DEV_RX_OFFLOAD_VLAN_FILTER) {
2355 rc = bnxt_add_vlan_filter(bp, 0);
2358 rc = bnxt_restore_vlan_filters(bp);
2362 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2367 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2371 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2372 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2378 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2380 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2381 struct bnxt *bp = dev->data->dev_private;
2384 rc = is_bnxt_in_error(bp);
2388 /* Filter settings will get applied when port is started */
2389 if (!dev->data->dev_started)
2392 if (mask & ETH_VLAN_FILTER_MASK) {
2393 /* Enable or disable VLAN filtering */
2394 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2399 if (mask & ETH_VLAN_STRIP_MASK) {
2400 /* Enable or disable VLAN stripping */
2401 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2406 if (mask & ETH_VLAN_EXTEND_MASK) {
2407 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2408 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2410 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2417 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2420 struct bnxt *bp = dev->data->dev_private;
2421 int qinq = dev->data->dev_conf.rxmode.offloads &
2422 DEV_RX_OFFLOAD_VLAN_EXTEND;
2424 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2425 vlan_type != ETH_VLAN_TYPE_OUTER) {
2427 "Unsupported vlan type.");
2432 "QinQ not enabled. Needs to be ON as we can "
2433 "accelerate only outer vlan\n");
2437 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2439 case RTE_ETHER_TYPE_QINQ:
2441 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2443 case RTE_ETHER_TYPE_VLAN:
2445 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2447 case RTE_ETHER_TYPE_QINQ1:
2449 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2451 case RTE_ETHER_TYPE_QINQ2:
2453 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2455 case RTE_ETHER_TYPE_QINQ3:
2457 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2460 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2463 bp->outer_tpid_bd |= tpid;
2464 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2465 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2467 "Can accelerate only outer vlan in QinQ\n");
2475 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2476 struct rte_ether_addr *addr)
2478 struct bnxt *bp = dev->data->dev_private;
2479 /* Default Filter is tied to VNIC 0 */
2480 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2483 rc = is_bnxt_in_error(bp);
2487 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2490 if (rte_is_zero_ether_addr(addr))
2493 /* Filter settings will get applied when port is started */
2494 if (!dev->data->dev_started)
2497 /* Check if the requested MAC is already added */
2498 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2501 /* Destroy filter and re-create it */
2502 bnxt_del_dflt_mac_filter(bp, vnic);
2504 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2505 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2506 /* This filter will allow only untagged packets */
2507 rc = bnxt_add_vlan_filter(bp, 0);
2509 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2512 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2517 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2518 struct rte_ether_addr *mc_addr_set,
2519 uint32_t nb_mc_addr)
2521 struct bnxt *bp = eth_dev->data->dev_private;
2522 char *mc_addr_list = (char *)mc_addr_set;
2523 struct bnxt_vnic_info *vnic;
2524 uint32_t off = 0, i = 0;
2527 rc = is_bnxt_in_error(bp);
2531 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2533 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2534 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2538 /* TODO Check for Duplicate mcast addresses */
2539 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2540 for (i = 0; i < nb_mc_addr; i++) {
2541 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2542 RTE_ETHER_ADDR_LEN);
2543 off += RTE_ETHER_ADDR_LEN;
2546 vnic->mc_addr_cnt = i;
2547 if (vnic->mc_addr_cnt)
2548 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2550 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2553 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2557 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2559 struct bnxt *bp = dev->data->dev_private;
2560 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2561 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2562 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2563 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2566 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2567 fw_major, fw_minor, fw_updt, fw_rsvd);
2569 ret += 1; /* add the size of '\0' */
2570 if (fw_size < (uint32_t)ret)
2577 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2578 struct rte_eth_rxq_info *qinfo)
2580 struct bnxt *bp = dev->data->dev_private;
2581 struct bnxt_rx_queue *rxq;
2583 if (is_bnxt_in_error(bp))
2586 rxq = dev->data->rx_queues[queue_id];
2588 qinfo->mp = rxq->mb_pool;
2589 qinfo->scattered_rx = dev->data->scattered_rx;
2590 qinfo->nb_desc = rxq->nb_rx_desc;
2592 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2593 qinfo->conf.rx_drop_en = 0;
2594 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2598 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2599 struct rte_eth_txq_info *qinfo)
2601 struct bnxt *bp = dev->data->dev_private;
2602 struct bnxt_tx_queue *txq;
2604 if (is_bnxt_in_error(bp))
2607 txq = dev->data->tx_queues[queue_id];
2609 qinfo->nb_desc = txq->nb_tx_desc;
2611 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2612 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2613 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2615 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2616 qinfo->conf.tx_rs_thresh = 0;
2617 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2620 static const struct {
2621 eth_rx_burst_t pkt_burst;
2623 } bnxt_rx_burst_info[] = {
2624 {bnxt_recv_pkts, "Scalar"},
2625 #if defined(RTE_ARCH_X86)
2626 {bnxt_recv_pkts_vec, "Vector SSE"},
2627 #elif defined(RTE_ARCH_ARM64)
2628 {bnxt_recv_pkts_vec, "Vector Neon"},
2633 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2634 struct rte_eth_burst_mode *mode)
2636 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2639 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2640 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2641 snprintf(mode->info, sizeof(mode->info), "%s",
2642 bnxt_rx_burst_info[i].info);
2650 static const struct {
2651 eth_tx_burst_t pkt_burst;
2653 } bnxt_tx_burst_info[] = {
2654 {bnxt_xmit_pkts, "Scalar"},
2655 #if defined(RTE_ARCH_X86)
2656 {bnxt_xmit_pkts_vec, "Vector SSE"},
2657 #elif defined(RTE_ARCH_ARM64)
2658 {bnxt_xmit_pkts_vec, "Vector Neon"},
2663 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2664 struct rte_eth_burst_mode *mode)
2666 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2669 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2670 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2671 snprintf(mode->info, sizeof(mode->info), "%s",
2672 bnxt_tx_burst_info[i].info);
2680 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2682 struct bnxt *bp = eth_dev->data->dev_private;
2683 uint32_t new_pkt_size;
2687 rc = is_bnxt_in_error(bp);
2691 /* Exit if receive queues are not configured yet */
2692 if (!eth_dev->data->nb_rx_queues)
2695 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2696 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2699 * Disallow any MTU change that would require scattered receive support
2700 * if it is not already enabled.
2702 if (eth_dev->data->dev_started &&
2703 !eth_dev->data->scattered_rx &&
2705 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2707 "MTU change would require scattered rx support. ");
2708 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2712 if (new_mtu > RTE_ETHER_MTU) {
2713 bp->flags |= BNXT_FLAG_JUMBO;
2714 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2715 DEV_RX_OFFLOAD_JUMBO_FRAME;
2717 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2718 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2719 bp->flags &= ~BNXT_FLAG_JUMBO;
2722 /* Is there a change in mtu setting? */
2723 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2726 for (i = 0; i < bp->nr_vnics; i++) {
2727 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2730 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2731 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2735 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2736 size -= RTE_PKTMBUF_HEADROOM;
2738 if (size < new_mtu) {
2739 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2746 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2748 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2754 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2756 struct bnxt *bp = dev->data->dev_private;
2757 uint16_t vlan = bp->vlan;
2760 rc = is_bnxt_in_error(bp);
2764 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2766 "PVID cannot be modified for this function\n");
2769 bp->vlan = on ? pvid : 0;
2771 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2778 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2780 struct bnxt *bp = dev->data->dev_private;
2783 rc = is_bnxt_in_error(bp);
2787 return bnxt_hwrm_port_led_cfg(bp, true);
2791 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2793 struct bnxt *bp = dev->data->dev_private;
2796 rc = is_bnxt_in_error(bp);
2800 return bnxt_hwrm_port_led_cfg(bp, false);
2804 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2806 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2807 uint32_t desc = 0, raw_cons = 0, cons;
2808 struct bnxt_cp_ring_info *cpr;
2809 struct bnxt_rx_queue *rxq;
2810 struct rx_pkt_cmpl *rxcmp;
2813 rc = is_bnxt_in_error(bp);
2817 rxq = dev->data->rx_queues[rx_queue_id];
2819 raw_cons = cpr->cp_raw_cons;
2822 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2823 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2824 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2826 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2838 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2840 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2841 struct bnxt_rx_ring_info *rxr;
2842 struct bnxt_cp_ring_info *cpr;
2843 struct rte_mbuf *rx_buf;
2844 struct rx_pkt_cmpl *rxcmp;
2845 uint32_t cons, cp_cons;
2851 rc = is_bnxt_in_error(rxq->bp);
2858 if (offset >= rxq->nb_rx_desc)
2861 cons = RING_CMP(cpr->cp_ring_struct, offset);
2862 cp_cons = cpr->cp_raw_cons;
2863 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2865 if (cons > cp_cons) {
2866 if (CMPL_VALID(rxcmp, cpr->valid))
2867 return RTE_ETH_RX_DESC_DONE;
2869 if (CMPL_VALID(rxcmp, !cpr->valid))
2870 return RTE_ETH_RX_DESC_DONE;
2872 rx_buf = rxr->rx_buf_ring[cons];
2874 return RTE_ETH_RX_DESC_UNAVAIL;
2877 return RTE_ETH_RX_DESC_AVAIL;
2881 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2883 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2884 struct bnxt_tx_ring_info *txr;
2885 struct bnxt_cp_ring_info *cpr;
2886 struct bnxt_sw_tx_bd *tx_buf;
2887 struct tx_pkt_cmpl *txcmp;
2888 uint32_t cons, cp_cons;
2894 rc = is_bnxt_in_error(txq->bp);
2901 if (offset >= txq->nb_tx_desc)
2904 cons = RING_CMP(cpr->cp_ring_struct, offset);
2905 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2906 cp_cons = cpr->cp_raw_cons;
2908 if (cons > cp_cons) {
2909 if (CMPL_VALID(txcmp, cpr->valid))
2910 return RTE_ETH_TX_DESC_UNAVAIL;
2912 if (CMPL_VALID(txcmp, !cpr->valid))
2913 return RTE_ETH_TX_DESC_UNAVAIL;
2915 tx_buf = &txr->tx_buf_ring[cons];
2916 if (tx_buf->mbuf == NULL)
2917 return RTE_ETH_TX_DESC_DONE;
2919 return RTE_ETH_TX_DESC_FULL;
2922 static struct bnxt_filter_info *
2923 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2924 struct rte_eth_ethertype_filter *efilter,
2925 struct bnxt_vnic_info *vnic0,
2926 struct bnxt_vnic_info *vnic,
2929 struct bnxt_filter_info *mfilter = NULL;
2933 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2934 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2935 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2936 " ethertype filter.", efilter->ether_type);
2940 if (efilter->queue >= bp->rx_nr_rings) {
2941 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2946 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2947 vnic = &bp->vnic_info[efilter->queue];
2949 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2954 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2955 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2956 if ((!memcmp(efilter->mac_addr.addr_bytes,
2957 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2959 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2960 mfilter->ethertype == efilter->ether_type)) {
2966 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2967 if ((!memcmp(efilter->mac_addr.addr_bytes,
2968 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2969 mfilter->ethertype == efilter->ether_type &&
2971 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2985 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2986 enum rte_filter_op filter_op,
2989 struct bnxt *bp = dev->data->dev_private;
2990 struct rte_eth_ethertype_filter *efilter =
2991 (struct rte_eth_ethertype_filter *)arg;
2992 struct bnxt_filter_info *bfilter, *filter1;
2993 struct bnxt_vnic_info *vnic, *vnic0;
2996 if (filter_op == RTE_ETH_FILTER_NOP)
3000 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3005 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3006 vnic = &bp->vnic_info[efilter->queue];
3008 switch (filter_op) {
3009 case RTE_ETH_FILTER_ADD:
3010 bnxt_match_and_validate_ether_filter(bp, efilter,
3015 bfilter = bnxt_get_unused_filter(bp);
3016 if (bfilter == NULL) {
3018 "Not enough resources for a new filter.\n");
3021 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3022 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
3023 RTE_ETHER_ADDR_LEN);
3024 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
3025 RTE_ETHER_ADDR_LEN);
3026 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3027 bfilter->ethertype = efilter->ether_type;
3028 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3030 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3031 if (filter1 == NULL) {
3036 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3037 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3039 bfilter->dst_id = vnic->fw_vnic_id;
3041 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3043 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3046 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3049 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3051 case RTE_ETH_FILTER_DELETE:
3052 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3054 if (ret == -EEXIST) {
3055 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3057 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3059 bnxt_free_filter(bp, filter1);
3060 } else if (ret == 0) {
3061 PMD_DRV_LOG(ERR, "No matching filter found\n");
3065 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3071 bnxt_free_filter(bp, bfilter);
3077 parse_ntuple_filter(struct bnxt *bp,
3078 struct rte_eth_ntuple_filter *nfilter,
3079 struct bnxt_filter_info *bfilter)
3083 if (nfilter->queue >= bp->rx_nr_rings) {
3084 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3088 switch (nfilter->dst_port_mask) {
3090 bfilter->dst_port_mask = -1;
3091 bfilter->dst_port = nfilter->dst_port;
3092 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3093 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3096 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3100 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3101 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3103 switch (nfilter->proto_mask) {
3105 if (nfilter->proto == 17) /* IPPROTO_UDP */
3106 bfilter->ip_protocol = 17;
3107 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3108 bfilter->ip_protocol = 6;
3111 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3114 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3118 switch (nfilter->dst_ip_mask) {
3120 bfilter->dst_ipaddr_mask[0] = -1;
3121 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3122 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3123 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3126 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3130 switch (nfilter->src_ip_mask) {
3132 bfilter->src_ipaddr_mask[0] = -1;
3133 bfilter->src_ipaddr[0] = nfilter->src_ip;
3134 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3135 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3138 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3142 switch (nfilter->src_port_mask) {
3144 bfilter->src_port_mask = -1;
3145 bfilter->src_port = nfilter->src_port;
3146 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3147 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3150 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3154 bfilter->enables = en;
3158 static struct bnxt_filter_info*
3159 bnxt_match_ntuple_filter(struct bnxt *bp,
3160 struct bnxt_filter_info *bfilter,
3161 struct bnxt_vnic_info **mvnic)
3163 struct bnxt_filter_info *mfilter = NULL;
3166 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3167 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3168 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3169 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3170 bfilter->src_ipaddr_mask[0] ==
3171 mfilter->src_ipaddr_mask[0] &&
3172 bfilter->src_port == mfilter->src_port &&
3173 bfilter->src_port_mask == mfilter->src_port_mask &&
3174 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3175 bfilter->dst_ipaddr_mask[0] ==
3176 mfilter->dst_ipaddr_mask[0] &&
3177 bfilter->dst_port == mfilter->dst_port &&
3178 bfilter->dst_port_mask == mfilter->dst_port_mask &&
3179 bfilter->flags == mfilter->flags &&
3180 bfilter->enables == mfilter->enables) {
3191 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3192 struct rte_eth_ntuple_filter *nfilter,
3193 enum rte_filter_op filter_op)
3195 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3196 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3199 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3200 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3204 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3205 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3209 bfilter = bnxt_get_unused_filter(bp);
3210 if (bfilter == NULL) {
3212 "Not enough resources for a new filter.\n");
3215 ret = parse_ntuple_filter(bp, nfilter, bfilter);
3219 vnic = &bp->vnic_info[nfilter->queue];
3220 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3221 filter1 = STAILQ_FIRST(&vnic0->filter);
3222 if (filter1 == NULL) {
3227 bfilter->dst_id = vnic->fw_vnic_id;
3228 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3230 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3231 bfilter->ethertype = 0x800;
3232 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3234 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3236 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3237 bfilter->dst_id == mfilter->dst_id) {
3238 PMD_DRV_LOG(ERR, "filter exists.\n");
3241 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3242 bfilter->dst_id != mfilter->dst_id) {
3243 mfilter->dst_id = vnic->fw_vnic_id;
3244 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3245 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3246 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3247 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3248 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3251 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3252 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3257 if (filter_op == RTE_ETH_FILTER_ADD) {
3258 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3259 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3262 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3264 if (mfilter == NULL) {
3265 /* This should not happen. But for Coverity! */
3269 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3271 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3272 bnxt_free_filter(bp, mfilter);
3273 bnxt_free_filter(bp, bfilter);
3278 bnxt_free_filter(bp, bfilter);
3283 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3284 enum rte_filter_op filter_op,
3287 struct bnxt *bp = dev->data->dev_private;
3290 if (filter_op == RTE_ETH_FILTER_NOP)
3294 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3299 switch (filter_op) {
3300 case RTE_ETH_FILTER_ADD:
3301 ret = bnxt_cfg_ntuple_filter(bp,
3302 (struct rte_eth_ntuple_filter *)arg,
3305 case RTE_ETH_FILTER_DELETE:
3306 ret = bnxt_cfg_ntuple_filter(bp,
3307 (struct rte_eth_ntuple_filter *)arg,
3311 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3319 bnxt_parse_fdir_filter(struct bnxt *bp,
3320 struct rte_eth_fdir_filter *fdir,
3321 struct bnxt_filter_info *filter)
3323 enum rte_fdir_mode fdir_mode =
3324 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3325 struct bnxt_vnic_info *vnic0, *vnic;
3326 struct bnxt_filter_info *filter1;
3330 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3333 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3334 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3336 switch (fdir->input.flow_type) {
3337 case RTE_ETH_FLOW_IPV4:
3338 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3340 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3341 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3342 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3343 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3344 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3345 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3346 filter->ip_addr_type =
3347 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3348 filter->src_ipaddr_mask[0] = 0xffffffff;
3349 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3350 filter->dst_ipaddr_mask[0] = 0xffffffff;
3351 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3352 filter->ethertype = 0x800;
3353 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3355 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3356 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3357 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3358 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3359 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3360 filter->dst_port_mask = 0xffff;
3361 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3362 filter->src_port_mask = 0xffff;
3363 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3364 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3365 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3366 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3367 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3368 filter->ip_protocol = 6;
3369 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3370 filter->ip_addr_type =
3371 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3372 filter->src_ipaddr_mask[0] = 0xffffffff;
3373 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3374 filter->dst_ipaddr_mask[0] = 0xffffffff;
3375 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3376 filter->ethertype = 0x800;
3377 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3379 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3380 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3381 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3382 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3383 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3384 filter->dst_port_mask = 0xffff;
3385 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3386 filter->src_port_mask = 0xffff;
3387 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3388 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3389 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3390 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3391 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3392 filter->ip_protocol = 17;
3393 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3394 filter->ip_addr_type =
3395 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3396 filter->src_ipaddr_mask[0] = 0xffffffff;
3397 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3398 filter->dst_ipaddr_mask[0] = 0xffffffff;
3399 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3400 filter->ethertype = 0x800;
3401 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3403 case RTE_ETH_FLOW_IPV6:
3404 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3406 filter->ip_addr_type =
3407 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3408 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3409 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3410 rte_memcpy(filter->src_ipaddr,
3411 fdir->input.flow.ipv6_flow.src_ip, 16);
3412 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3413 rte_memcpy(filter->dst_ipaddr,
3414 fdir->input.flow.ipv6_flow.dst_ip, 16);
3415 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3416 memset(filter->dst_ipaddr_mask, 0xff, 16);
3417 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3418 memset(filter->src_ipaddr_mask, 0xff, 16);
3419 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3420 filter->ethertype = 0x86dd;
3421 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3423 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3424 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3425 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3426 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3427 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3428 filter->dst_port_mask = 0xffff;
3429 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3430 filter->src_port_mask = 0xffff;
3431 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3432 filter->ip_addr_type =
3433 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3434 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3435 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3436 rte_memcpy(filter->src_ipaddr,
3437 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3438 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3439 rte_memcpy(filter->dst_ipaddr,
3440 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3441 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3442 memset(filter->dst_ipaddr_mask, 0xff, 16);
3443 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3444 memset(filter->src_ipaddr_mask, 0xff, 16);
3445 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3446 filter->ethertype = 0x86dd;
3447 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3449 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3450 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3451 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3452 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3453 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3454 filter->dst_port_mask = 0xffff;
3455 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3456 filter->src_port_mask = 0xffff;
3457 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3458 filter->ip_addr_type =
3459 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3460 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3461 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3462 rte_memcpy(filter->src_ipaddr,
3463 fdir->input.flow.udp6_flow.ip.src_ip, 16);
3464 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3465 rte_memcpy(filter->dst_ipaddr,
3466 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3467 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3468 memset(filter->dst_ipaddr_mask, 0xff, 16);
3469 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3470 memset(filter->src_ipaddr_mask, 0xff, 16);
3471 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3472 filter->ethertype = 0x86dd;
3473 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3475 case RTE_ETH_FLOW_L2_PAYLOAD:
3476 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3477 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3479 case RTE_ETH_FLOW_VXLAN:
3480 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3482 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3483 filter->tunnel_type =
3484 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3485 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3487 case RTE_ETH_FLOW_NVGRE:
3488 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3490 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3491 filter->tunnel_type =
3492 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3493 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3495 case RTE_ETH_FLOW_UNKNOWN:
3496 case RTE_ETH_FLOW_RAW:
3497 case RTE_ETH_FLOW_FRAG_IPV4:
3498 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3499 case RTE_ETH_FLOW_FRAG_IPV6:
3500 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3501 case RTE_ETH_FLOW_IPV6_EX:
3502 case RTE_ETH_FLOW_IPV6_TCP_EX:
3503 case RTE_ETH_FLOW_IPV6_UDP_EX:
3504 case RTE_ETH_FLOW_GENEVE:
3510 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3511 vnic = &bp->vnic_info[fdir->action.rx_queue];
3513 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3517 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3518 rte_memcpy(filter->dst_macaddr,
3519 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3520 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3523 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3524 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3525 filter1 = STAILQ_FIRST(&vnic0->filter);
3526 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3528 filter->dst_id = vnic->fw_vnic_id;
3529 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3530 if (filter->dst_macaddr[i] == 0x00)
3531 filter1 = STAILQ_FIRST(&vnic0->filter);
3533 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3536 if (filter1 == NULL)
3539 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3540 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3542 filter->enables = en;
3547 static struct bnxt_filter_info *
3548 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3549 struct bnxt_vnic_info **mvnic)
3551 struct bnxt_filter_info *mf = NULL;
3554 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3555 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3557 STAILQ_FOREACH(mf, &vnic->filter, next) {
3558 if (mf->filter_type == nf->filter_type &&
3559 mf->flags == nf->flags &&
3560 mf->src_port == nf->src_port &&
3561 mf->src_port_mask == nf->src_port_mask &&
3562 mf->dst_port == nf->dst_port &&
3563 mf->dst_port_mask == nf->dst_port_mask &&
3564 mf->ip_protocol == nf->ip_protocol &&
3565 mf->ip_addr_type == nf->ip_addr_type &&
3566 mf->ethertype == nf->ethertype &&
3567 mf->vni == nf->vni &&
3568 mf->tunnel_type == nf->tunnel_type &&
3569 mf->l2_ovlan == nf->l2_ovlan &&
3570 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3571 mf->l2_ivlan == nf->l2_ivlan &&
3572 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3573 !memcmp(mf->l2_addr, nf->l2_addr,
3574 RTE_ETHER_ADDR_LEN) &&
3575 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3576 RTE_ETHER_ADDR_LEN) &&
3577 !memcmp(mf->src_macaddr, nf->src_macaddr,
3578 RTE_ETHER_ADDR_LEN) &&
3579 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3580 RTE_ETHER_ADDR_LEN) &&
3581 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3582 sizeof(nf->src_ipaddr)) &&
3583 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3584 sizeof(nf->src_ipaddr_mask)) &&
3585 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3586 sizeof(nf->dst_ipaddr)) &&
3587 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3588 sizeof(nf->dst_ipaddr_mask))) {
3599 bnxt_fdir_filter(struct rte_eth_dev *dev,
3600 enum rte_filter_op filter_op,
3603 struct bnxt *bp = dev->data->dev_private;
3604 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3605 struct bnxt_filter_info *filter, *match;
3606 struct bnxt_vnic_info *vnic, *mvnic;
3609 if (filter_op == RTE_ETH_FILTER_NOP)
3612 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3615 switch (filter_op) {
3616 case RTE_ETH_FILTER_ADD:
3617 case RTE_ETH_FILTER_DELETE:
3619 filter = bnxt_get_unused_filter(bp);
3620 if (filter == NULL) {
3622 "Not enough resources for a new flow.\n");
3626 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3629 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3631 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3632 vnic = &bp->vnic_info[0];
3634 vnic = &bp->vnic_info[fdir->action.rx_queue];
3636 match = bnxt_match_fdir(bp, filter, &mvnic);
3637 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3638 if (match->dst_id == vnic->fw_vnic_id) {
3639 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3643 match->dst_id = vnic->fw_vnic_id;
3644 ret = bnxt_hwrm_set_ntuple_filter(bp,
3647 STAILQ_REMOVE(&mvnic->filter, match,
3648 bnxt_filter_info, next);
3649 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3651 "Filter with matching pattern exist\n");
3653 "Updated it to new destination q\n");
3657 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3658 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3663 if (filter_op == RTE_ETH_FILTER_ADD) {
3664 ret = bnxt_hwrm_set_ntuple_filter(bp,
3669 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3671 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3672 STAILQ_REMOVE(&vnic->filter, match,
3673 bnxt_filter_info, next);
3674 bnxt_free_filter(bp, match);
3675 bnxt_free_filter(bp, filter);
3678 case RTE_ETH_FILTER_FLUSH:
3679 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3680 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3682 STAILQ_FOREACH(filter, &vnic->filter, next) {
3683 if (filter->filter_type ==
3684 HWRM_CFA_NTUPLE_FILTER) {
3686 bnxt_hwrm_clear_ntuple_filter(bp,
3688 STAILQ_REMOVE(&vnic->filter, filter,
3689 bnxt_filter_info, next);
3694 case RTE_ETH_FILTER_UPDATE:
3695 case RTE_ETH_FILTER_STATS:
3696 case RTE_ETH_FILTER_INFO:
3697 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3700 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3707 bnxt_free_filter(bp, filter);
3712 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3713 enum rte_filter_type filter_type,
3714 enum rte_filter_op filter_op, void *arg)
3716 struct bnxt *bp = dev->data->dev_private;
3719 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3720 struct bnxt_vf_representor *vfr = dev->data->dev_private;
3721 bp = vfr->parent_dev->data->dev_private;
3724 ret = is_bnxt_in_error(bp);
3728 switch (filter_type) {
3729 case RTE_ETH_FILTER_TUNNEL:
3731 "filter type: %d: To be implemented\n", filter_type);
3733 case RTE_ETH_FILTER_FDIR:
3734 ret = bnxt_fdir_filter(dev, filter_op, arg);
3736 case RTE_ETH_FILTER_NTUPLE:
3737 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3739 case RTE_ETH_FILTER_ETHERTYPE:
3740 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3742 case RTE_ETH_FILTER_GENERIC:
3743 if (filter_op != RTE_ETH_FILTER_GET)
3745 if (BNXT_TRUFLOW_EN(bp))
3746 *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3748 *(const void **)arg = &bnxt_flow_ops;
3752 "Filter type (%d) not supported", filter_type);
3759 static const uint32_t *
3760 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3762 static const uint32_t ptypes[] = {
3763 RTE_PTYPE_L2_ETHER_VLAN,
3764 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3765 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3769 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3770 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3771 RTE_PTYPE_INNER_L4_ICMP,
3772 RTE_PTYPE_INNER_L4_TCP,
3773 RTE_PTYPE_INNER_L4_UDP,
3777 if (!dev->rx_pkt_burst)
3783 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3786 uint32_t reg_base = *reg_arr & 0xfffff000;
3790 for (i = 0; i < count; i++) {
3791 if ((reg_arr[i] & 0xfffff000) != reg_base)
3794 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3795 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3799 static int bnxt_map_ptp_regs(struct bnxt *bp)
3801 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3805 reg_arr = ptp->rx_regs;
3806 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3810 reg_arr = ptp->tx_regs;
3811 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3815 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3816 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3818 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3819 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3824 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3826 rte_write32(0, (uint8_t *)bp->bar0 +
3827 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3828 rte_write32(0, (uint8_t *)bp->bar0 +
3829 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3832 static uint64_t bnxt_cc_read(struct bnxt *bp)
3836 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3837 BNXT_GRCPF_REG_SYNC_TIME));
3838 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3839 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3843 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3845 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3848 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3849 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3850 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3853 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3854 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3855 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3856 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3857 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3858 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3863 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3865 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3866 struct bnxt_pf_info *pf = bp->pf;
3873 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3874 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3875 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3878 port_id = pf->port_id;
3879 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3880 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3882 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3883 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3884 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3885 /* bnxt_clr_rx_ts(bp); TBD */
3889 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3890 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3891 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3892 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3898 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3901 struct bnxt *bp = dev->data->dev_private;
3902 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3907 ns = rte_timespec_to_ns(ts);
3908 /* Set the timecounters to a new value. */
3915 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3917 struct bnxt *bp = dev->data->dev_private;
3918 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3919 uint64_t ns, systime_cycles = 0;
3925 if (BNXT_CHIP_THOR(bp))
3926 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3929 systime_cycles = bnxt_cc_read(bp);
3931 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3932 *ts = rte_ns_to_timespec(ns);
3937 bnxt_timesync_enable(struct rte_eth_dev *dev)
3939 struct bnxt *bp = dev->data->dev_private;
3940 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3948 ptp->tx_tstamp_en = 1;
3949 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3951 rc = bnxt_hwrm_ptp_cfg(bp);
3955 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3956 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3957 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3959 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3960 ptp->tc.cc_shift = shift;
3961 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3963 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3964 ptp->rx_tstamp_tc.cc_shift = shift;
3965 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3967 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3968 ptp->tx_tstamp_tc.cc_shift = shift;
3969 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3971 if (!BNXT_CHIP_THOR(bp))
3972 bnxt_map_ptp_regs(bp);
3978 bnxt_timesync_disable(struct rte_eth_dev *dev)
3980 struct bnxt *bp = dev->data->dev_private;
3981 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3987 ptp->tx_tstamp_en = 0;
3990 bnxt_hwrm_ptp_cfg(bp);
3992 if (!BNXT_CHIP_THOR(bp))
3993 bnxt_unmap_ptp_regs(bp);
3999 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4000 struct timespec *timestamp,
4001 uint32_t flags __rte_unused)
4003 struct bnxt *bp = dev->data->dev_private;
4004 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4005 uint64_t rx_tstamp_cycles = 0;
4011 if (BNXT_CHIP_THOR(bp))
4012 rx_tstamp_cycles = ptp->rx_timestamp;
4014 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
4016 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
4017 *timestamp = rte_ns_to_timespec(ns);
4022 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4023 struct timespec *timestamp)
4025 struct bnxt *bp = dev->data->dev_private;
4026 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4027 uint64_t tx_tstamp_cycles = 0;
4034 if (BNXT_CHIP_THOR(bp))
4035 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4038 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4040 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4041 *timestamp = rte_ns_to_timespec(ns);
4047 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4049 struct bnxt *bp = dev->data->dev_private;
4050 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4055 ptp->tc.nsec += delta;
4061 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4063 struct bnxt *bp = dev->data->dev_private;
4065 uint32_t dir_entries;
4066 uint32_t entry_length;
4068 rc = is_bnxt_in_error(bp);
4072 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4073 bp->pdev->addr.domain, bp->pdev->addr.bus,
4074 bp->pdev->addr.devid, bp->pdev->addr.function);
4076 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4080 return dir_entries * entry_length;
4084 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4085 struct rte_dev_eeprom_info *in_eeprom)
4087 struct bnxt *bp = dev->data->dev_private;
4092 rc = is_bnxt_in_error(bp);
4096 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4097 bp->pdev->addr.domain, bp->pdev->addr.bus,
4098 bp->pdev->addr.devid, bp->pdev->addr.function,
4099 in_eeprom->offset, in_eeprom->length);
4101 if (in_eeprom->offset == 0) /* special offset value to get directory */
4102 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4105 index = in_eeprom->offset >> 24;
4106 offset = in_eeprom->offset & 0xffffff;
4109 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4110 in_eeprom->length, in_eeprom->data);
4115 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4118 case BNX_DIR_TYPE_CHIMP_PATCH:
4119 case BNX_DIR_TYPE_BOOTCODE:
4120 case BNX_DIR_TYPE_BOOTCODE_2:
4121 case BNX_DIR_TYPE_APE_FW:
4122 case BNX_DIR_TYPE_APE_PATCH:
4123 case BNX_DIR_TYPE_KONG_FW:
4124 case BNX_DIR_TYPE_KONG_PATCH:
4125 case BNX_DIR_TYPE_BONO_FW:
4126 case BNX_DIR_TYPE_BONO_PATCH:
4134 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4137 case BNX_DIR_TYPE_AVS:
4138 case BNX_DIR_TYPE_EXP_ROM_MBA:
4139 case BNX_DIR_TYPE_PCIE:
4140 case BNX_DIR_TYPE_TSCF_UCODE:
4141 case BNX_DIR_TYPE_EXT_PHY:
4142 case BNX_DIR_TYPE_CCM:
4143 case BNX_DIR_TYPE_ISCSI_BOOT:
4144 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4145 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4153 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4155 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4156 bnxt_dir_type_is_other_exec_format(dir_type);
4160 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4161 struct rte_dev_eeprom_info *in_eeprom)
4163 struct bnxt *bp = dev->data->dev_private;
4164 uint8_t index, dir_op;
4165 uint16_t type, ext, ordinal, attr;
4168 rc = is_bnxt_in_error(bp);
4172 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4173 bp->pdev->addr.domain, bp->pdev->addr.bus,
4174 bp->pdev->addr.devid, bp->pdev->addr.function,
4175 in_eeprom->offset, in_eeprom->length);
4178 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4182 type = in_eeprom->magic >> 16;
4184 if (type == 0xffff) { /* special value for directory operations */
4185 index = in_eeprom->magic & 0xff;
4186 dir_op = in_eeprom->magic >> 8;
4190 case 0x0e: /* erase */
4191 if (in_eeprom->offset != ~in_eeprom->magic)
4193 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4199 /* Create or re-write an NVM item: */
4200 if (bnxt_dir_type_is_executable(type) == true)
4202 ext = in_eeprom->magic & 0xffff;
4203 ordinal = in_eeprom->offset >> 16;
4204 attr = in_eeprom->offset & 0xffff;
4206 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4207 in_eeprom->data, in_eeprom->length);
4214 static const struct eth_dev_ops bnxt_dev_ops = {
4215 .dev_infos_get = bnxt_dev_info_get_op,
4216 .dev_close = bnxt_dev_close_op,
4217 .dev_configure = bnxt_dev_configure_op,
4218 .dev_start = bnxt_dev_start_op,
4219 .dev_stop = bnxt_dev_stop_op,
4220 .dev_set_link_up = bnxt_dev_set_link_up_op,
4221 .dev_set_link_down = bnxt_dev_set_link_down_op,
4222 .stats_get = bnxt_stats_get_op,
4223 .stats_reset = bnxt_stats_reset_op,
4224 .rx_queue_setup = bnxt_rx_queue_setup_op,
4225 .rx_queue_release = bnxt_rx_queue_release_op,
4226 .tx_queue_setup = bnxt_tx_queue_setup_op,
4227 .tx_queue_release = bnxt_tx_queue_release_op,
4228 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4229 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4230 .reta_update = bnxt_reta_update_op,
4231 .reta_query = bnxt_reta_query_op,
4232 .rss_hash_update = bnxt_rss_hash_update_op,
4233 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4234 .link_update = bnxt_link_update_op,
4235 .promiscuous_enable = bnxt_promiscuous_enable_op,
4236 .promiscuous_disable = bnxt_promiscuous_disable_op,
4237 .allmulticast_enable = bnxt_allmulticast_enable_op,
4238 .allmulticast_disable = bnxt_allmulticast_disable_op,
4239 .mac_addr_add = bnxt_mac_addr_add_op,
4240 .mac_addr_remove = bnxt_mac_addr_remove_op,
4241 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4242 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4243 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
4244 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
4245 .vlan_filter_set = bnxt_vlan_filter_set_op,
4246 .vlan_offload_set = bnxt_vlan_offload_set_op,
4247 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4248 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4249 .mtu_set = bnxt_mtu_set_op,
4250 .mac_addr_set = bnxt_set_default_mac_addr_op,
4251 .xstats_get = bnxt_dev_xstats_get_op,
4252 .xstats_get_names = bnxt_dev_xstats_get_names_op,
4253 .xstats_reset = bnxt_dev_xstats_reset_op,
4254 .fw_version_get = bnxt_fw_version_get,
4255 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4256 .rxq_info_get = bnxt_rxq_info_get_op,
4257 .txq_info_get = bnxt_txq_info_get_op,
4258 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4259 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4260 .dev_led_on = bnxt_dev_led_on_op,
4261 .dev_led_off = bnxt_dev_led_off_op,
4262 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4263 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4264 .rx_queue_start = bnxt_rx_queue_start,
4265 .rx_queue_stop = bnxt_rx_queue_stop,
4266 .tx_queue_start = bnxt_tx_queue_start,
4267 .tx_queue_stop = bnxt_tx_queue_stop,
4268 .filter_ctrl = bnxt_filter_ctrl_op,
4269 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4270 .get_eeprom_length = bnxt_get_eeprom_length_op,
4271 .get_eeprom = bnxt_get_eeprom_op,
4272 .set_eeprom = bnxt_set_eeprom_op,
4273 .timesync_enable = bnxt_timesync_enable,
4274 .timesync_disable = bnxt_timesync_disable,
4275 .timesync_read_time = bnxt_timesync_read_time,
4276 .timesync_write_time = bnxt_timesync_write_time,
4277 .timesync_adjust_time = bnxt_timesync_adjust_time,
4278 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4279 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4282 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4286 /* Only pre-map the reset GRC registers using window 3 */
4287 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4288 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4290 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4295 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4297 struct bnxt_error_recovery_info *info = bp->recovery_info;
4298 uint32_t reg_base = 0xffffffff;
4301 /* Only pre-map the monitoring GRC registers using window 2 */
4302 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4303 uint32_t reg = info->status_regs[i];
4305 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4308 if (reg_base == 0xffffffff)
4309 reg_base = reg & 0xfffff000;
4310 if ((reg & 0xfffff000) != reg_base)
4313 /* Use mask 0xffc as the Lower 2 bits indicates
4314 * address space location
4316 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4320 if (reg_base == 0xffffffff)
4323 rte_write32(reg_base, (uint8_t *)bp->bar0 +
4324 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4329 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4331 struct bnxt_error_recovery_info *info = bp->recovery_info;
4332 uint32_t delay = info->delay_after_reset[index];
4333 uint32_t val = info->reset_reg_val[index];
4334 uint32_t reg = info->reset_reg[index];
4335 uint32_t type, offset;
4337 type = BNXT_FW_STATUS_REG_TYPE(reg);
4338 offset = BNXT_FW_STATUS_REG_OFF(reg);
4341 case BNXT_FW_STATUS_REG_TYPE_CFG:
4342 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4344 case BNXT_FW_STATUS_REG_TYPE_GRC:
4345 offset = bnxt_map_reset_regs(bp, offset);
4346 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4348 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4349 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4352 /* wait on a specific interval of time until core reset is complete */
4354 rte_delay_ms(delay);
4357 static void bnxt_dev_cleanup(struct bnxt *bp)
4359 bnxt_set_hwrm_link_config(bp, false);
4360 bp->link_info->link_up = 0;
4361 if (bp->eth_dev->data->dev_started)
4362 bnxt_dev_stop_op(bp->eth_dev);
4364 bnxt_uninit_resources(bp, true);
4367 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4369 struct rte_eth_dev *dev = bp->eth_dev;
4370 struct rte_vlan_filter_conf *vfc;
4374 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4375 vfc = &dev->data->vlan_filter_conf;
4376 vidx = vlan_id / 64;
4377 vbit = vlan_id % 64;
4379 /* Each bit corresponds to a VLAN id */
4380 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4381 rc = bnxt_add_vlan_filter(bp, vlan_id);
4390 static int bnxt_restore_mac_filters(struct bnxt *bp)
4392 struct rte_eth_dev *dev = bp->eth_dev;
4393 struct rte_eth_dev_info dev_info;
4394 struct rte_ether_addr *addr;
4400 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4403 rc = bnxt_dev_info_get_op(dev, &dev_info);
4407 /* replay MAC address configuration */
4408 for (i = 1; i < dev_info.max_mac_addrs; i++) {
4409 addr = &dev->data->mac_addrs[i];
4411 /* skip zero address */
4412 if (rte_is_zero_ether_addr(addr))
4416 pool_mask = dev->data->mac_pool_sel[i];
4419 if (pool_mask & 1ULL) {
4420 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4426 } while (pool_mask);
4432 static int bnxt_restore_filters(struct bnxt *bp)
4434 struct rte_eth_dev *dev = bp->eth_dev;
4437 if (dev->data->all_multicast) {
4438 ret = bnxt_allmulticast_enable_op(dev);
4442 if (dev->data->promiscuous) {
4443 ret = bnxt_promiscuous_enable_op(dev);
4448 ret = bnxt_restore_mac_filters(bp);
4452 ret = bnxt_restore_vlan_filters(bp);
4453 /* TODO restore other filters as well */
4457 static void bnxt_dev_recover(void *arg)
4459 struct bnxt *bp = arg;
4460 int timeout = bp->fw_reset_max_msecs;
4463 /* Clear Error flag so that device re-init should happen */
4464 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4467 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4470 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4471 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4472 } while (rc && timeout);
4475 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4479 rc = bnxt_init_resources(bp, true);
4482 "Failed to initialize resources after reset\n");
4485 /* clear reset flag as the device is initialized now */
4486 bp->flags &= ~BNXT_FLAG_FW_RESET;
4488 rc = bnxt_dev_start_op(bp->eth_dev);
4490 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4494 rc = bnxt_restore_filters(bp);
4498 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4501 bnxt_dev_stop_op(bp->eth_dev);
4503 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4504 bnxt_uninit_resources(bp, false);
4505 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4508 void bnxt_dev_reset_and_resume(void *arg)
4510 struct bnxt *bp = arg;
4513 bnxt_dev_cleanup(bp);
4515 bnxt_wait_for_device_shutdown(bp);
4517 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4518 bnxt_dev_recover, (void *)bp);
4520 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4523 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4525 struct bnxt_error_recovery_info *info = bp->recovery_info;
4526 uint32_t reg = info->status_regs[index];
4527 uint32_t type, offset, val = 0;
4529 type = BNXT_FW_STATUS_REG_TYPE(reg);
4530 offset = BNXT_FW_STATUS_REG_OFF(reg);
4533 case BNXT_FW_STATUS_REG_TYPE_CFG:
4534 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4536 case BNXT_FW_STATUS_REG_TYPE_GRC:
4537 offset = info->mapped_status_regs[index];
4539 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4540 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4548 static int bnxt_fw_reset_all(struct bnxt *bp)
4550 struct bnxt_error_recovery_info *info = bp->recovery_info;
4554 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4555 /* Reset through master function driver */
4556 for (i = 0; i < info->reg_array_cnt; i++)
4557 bnxt_write_fw_reset_reg(bp, i);
4558 /* Wait for time specified by FW after triggering reset */
4559 rte_delay_ms(info->master_func_wait_period_after_reset);
4560 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4561 /* Reset with the help of Kong processor */
4562 rc = bnxt_hwrm_fw_reset(bp);
4564 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4570 static void bnxt_fw_reset_cb(void *arg)
4572 struct bnxt *bp = arg;
4573 struct bnxt_error_recovery_info *info = bp->recovery_info;
4576 /* Only Master function can do FW reset */
4577 if (bnxt_is_master_func(bp) &&
4578 bnxt_is_recovery_enabled(bp)) {
4579 rc = bnxt_fw_reset_all(bp);
4581 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4586 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4587 * EXCEPTION_FATAL_ASYNC event to all the functions
4588 * (including MASTER FUNC). After receiving this Async, all the active
4589 * drivers should treat this case as FW initiated recovery
4591 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4592 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4593 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4595 /* To recover from error */
4596 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4601 /* Driver should poll FW heartbeat, reset_counter with the frequency
4602 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4603 * When the driver detects heartbeat stop or change in reset_counter,
4604 * it has to trigger a reset to recover from the error condition.
4605 * A “master PF” is the function who will have the privilege to
4606 * initiate the chimp reset. The master PF will be elected by the
4607 * firmware and will be notified through async message.
4609 static void bnxt_check_fw_health(void *arg)
4611 struct bnxt *bp = arg;
4612 struct bnxt_error_recovery_info *info = bp->recovery_info;
4613 uint32_t val = 0, wait_msec;
4615 if (!info || !bnxt_is_recovery_enabled(bp) ||
4616 is_bnxt_in_error(bp))
4619 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4620 if (val == info->last_heart_beat)
4623 info->last_heart_beat = val;
4625 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4626 if (val != info->last_reset_counter)
4629 info->last_reset_counter = val;
4631 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4632 bnxt_check_fw_health, (void *)bp);
4636 /* Stop DMA to/from device */
4637 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4638 bp->flags |= BNXT_FLAG_FW_RESET;
4640 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4642 if (bnxt_is_master_func(bp))
4643 wait_msec = info->master_func_wait_period;
4645 wait_msec = info->normal_func_wait_period;
4647 rte_eal_alarm_set(US_PER_MS * wait_msec,
4648 bnxt_fw_reset_cb, (void *)bp);
4651 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4653 uint32_t polling_freq;
4655 if (!bnxt_is_recovery_enabled(bp))
4658 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4661 polling_freq = bp->recovery_info->driver_polling_freq;
4663 rte_eal_alarm_set(US_PER_MS * polling_freq,
4664 bnxt_check_fw_health, (void *)bp);
4665 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4668 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4670 if (!bnxt_is_recovery_enabled(bp))
4673 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4674 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4677 static bool bnxt_vf_pciid(uint16_t device_id)
4679 switch (device_id) {
4680 case BROADCOM_DEV_ID_57304_VF:
4681 case BROADCOM_DEV_ID_57406_VF:
4682 case BROADCOM_DEV_ID_5731X_VF:
4683 case BROADCOM_DEV_ID_5741X_VF:
4684 case BROADCOM_DEV_ID_57414_VF:
4685 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4686 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4687 case BROADCOM_DEV_ID_58802_VF:
4688 case BROADCOM_DEV_ID_57500_VF1:
4689 case BROADCOM_DEV_ID_57500_VF2:
4697 static bool bnxt_thor_device(uint16_t device_id)
4699 switch (device_id) {
4700 case BROADCOM_DEV_ID_57508:
4701 case BROADCOM_DEV_ID_57504:
4702 case BROADCOM_DEV_ID_57502:
4703 case BROADCOM_DEV_ID_57508_MF1:
4704 case BROADCOM_DEV_ID_57504_MF1:
4705 case BROADCOM_DEV_ID_57502_MF1:
4706 case BROADCOM_DEV_ID_57508_MF2:
4707 case BROADCOM_DEV_ID_57504_MF2:
4708 case BROADCOM_DEV_ID_57502_MF2:
4709 case BROADCOM_DEV_ID_57500_VF1:
4710 case BROADCOM_DEV_ID_57500_VF2:
4718 bool bnxt_stratus_device(struct bnxt *bp)
4720 uint16_t device_id = bp->pdev->id.device_id;
4722 switch (device_id) {
4723 case BROADCOM_DEV_ID_STRATUS_NIC:
4724 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4725 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4733 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4735 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4736 struct bnxt *bp = eth_dev->data->dev_private;
4738 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4739 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4740 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4741 if (!bp->bar0 || !bp->doorbell_base) {
4742 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4746 bp->eth_dev = eth_dev;
4752 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4753 struct bnxt_ctx_pg_info *ctx_pg,
4758 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4759 const struct rte_memzone *mz = NULL;
4760 char mz_name[RTE_MEMZONE_NAMESIZE];
4761 rte_iova_t mz_phys_addr;
4762 uint64_t valid_bits = 0;
4769 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4771 rmem->page_size = BNXT_PAGE_SIZE;
4772 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4773 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4774 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4776 valid_bits = PTU_PTE_VALID;
4778 if (rmem->nr_pages > 1) {
4779 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4780 "bnxt_ctx_pg_tbl%s_%x_%d",
4781 suffix, idx, bp->eth_dev->data->port_id);
4782 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4783 mz = rte_memzone_lookup(mz_name);
4785 mz = rte_memzone_reserve_aligned(mz_name,
4789 RTE_MEMZONE_SIZE_HINT_ONLY |
4790 RTE_MEMZONE_IOVA_CONTIG,
4796 memset(mz->addr, 0, mz->len);
4797 mz_phys_addr = mz->iova;
4799 rmem->pg_tbl = mz->addr;
4800 rmem->pg_tbl_map = mz_phys_addr;
4801 rmem->pg_tbl_mz = mz;
4804 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4805 suffix, idx, bp->eth_dev->data->port_id);
4806 mz = rte_memzone_lookup(mz_name);
4808 mz = rte_memzone_reserve_aligned(mz_name,
4812 RTE_MEMZONE_SIZE_HINT_ONLY |
4813 RTE_MEMZONE_IOVA_CONTIG,
4819 memset(mz->addr, 0, mz->len);
4820 mz_phys_addr = mz->iova;
4822 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4823 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4824 rmem->dma_arr[i] = mz_phys_addr + sz;
4826 if (rmem->nr_pages > 1) {
4827 if (i == rmem->nr_pages - 2 &&
4828 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4829 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4830 else if (i == rmem->nr_pages - 1 &&
4831 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4832 valid_bits |= PTU_PTE_LAST;
4834 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4840 if (rmem->vmem_size)
4841 rmem->vmem = (void **)mz->addr;
4842 rmem->dma_arr[0] = mz_phys_addr;
4846 static void bnxt_free_ctx_mem(struct bnxt *bp)
4850 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4853 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4854 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4855 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4856 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4857 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4858 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4859 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4860 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4861 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4862 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4863 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4865 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4866 if (bp->ctx->tqm_mem[i])
4867 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4874 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4876 #define min_t(type, x, y) ({ \
4877 type __min1 = (x); \
4878 type __min2 = (y); \
4879 __min1 < __min2 ? __min1 : __min2; })
4881 #define max_t(type, x, y) ({ \
4882 type __max1 = (x); \
4883 type __max2 = (y); \
4884 __max1 > __max2 ? __max1 : __max2; })
4886 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4888 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4890 struct bnxt_ctx_pg_info *ctx_pg;
4891 struct bnxt_ctx_mem_info *ctx;
4892 uint32_t mem_size, ena, entries;
4893 uint32_t entries_sp, min;
4896 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4898 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4902 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4905 ctx_pg = &ctx->qp_mem;
4906 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4907 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4908 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4912 ctx_pg = &ctx->srq_mem;
4913 ctx_pg->entries = ctx->srq_max_l2_entries;
4914 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4915 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4919 ctx_pg = &ctx->cq_mem;
4920 ctx_pg->entries = ctx->cq_max_l2_entries;
4921 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4922 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4926 ctx_pg = &ctx->vnic_mem;
4927 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4928 ctx->vnic_max_ring_table_entries;
4929 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4930 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4934 ctx_pg = &ctx->stat_mem;
4935 ctx_pg->entries = ctx->stat_max_entries;
4936 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4937 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4941 min = ctx->tqm_min_entries_per_ring;
4943 entries_sp = ctx->qp_max_l2_entries +
4944 ctx->vnic_max_vnic_entries +
4945 2 * ctx->qp_min_qp1_entries + min;
4946 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4948 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4949 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4950 entries = clamp_t(uint32_t, entries, min,
4951 ctx->tqm_max_entries_per_ring);
4952 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4953 ctx_pg = ctx->tqm_mem[i];
4954 ctx_pg->entries = i ? entries : entries_sp;
4955 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4956 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4959 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4962 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4963 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4966 "Failed to configure context mem: rc = %d\n", rc);
4968 ctx->flags |= BNXT_CTX_FLAG_INITED;
4973 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4975 struct rte_pci_device *pci_dev = bp->pdev;
4976 char mz_name[RTE_MEMZONE_NAMESIZE];
4977 const struct rte_memzone *mz = NULL;
4978 uint32_t total_alloc_len;
4979 rte_iova_t mz_phys_addr;
4981 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4984 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4985 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4986 pci_dev->addr.bus, pci_dev->addr.devid,
4987 pci_dev->addr.function, "rx_port_stats");
4988 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4989 mz = rte_memzone_lookup(mz_name);
4991 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4992 sizeof(struct rx_port_stats_ext) + 512);
4994 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4997 RTE_MEMZONE_SIZE_HINT_ONLY |
4998 RTE_MEMZONE_IOVA_CONTIG);
5002 memset(mz->addr, 0, mz->len);
5003 mz_phys_addr = mz->iova;
5005 bp->rx_mem_zone = (const void *)mz;
5006 bp->hw_rx_port_stats = mz->addr;
5007 bp->hw_rx_port_stats_map = mz_phys_addr;
5009 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5010 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5011 pci_dev->addr.bus, pci_dev->addr.devid,
5012 pci_dev->addr.function, "tx_port_stats");
5013 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5014 mz = rte_memzone_lookup(mz_name);
5016 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
5017 sizeof(struct tx_port_stats_ext) + 512);
5019 mz = rte_memzone_reserve(mz_name,
5023 RTE_MEMZONE_SIZE_HINT_ONLY |
5024 RTE_MEMZONE_IOVA_CONTIG);
5028 memset(mz->addr, 0, mz->len);
5029 mz_phys_addr = mz->iova;
5031 bp->tx_mem_zone = (const void *)mz;
5032 bp->hw_tx_port_stats = mz->addr;
5033 bp->hw_tx_port_stats_map = mz_phys_addr;
5034 bp->flags |= BNXT_FLAG_PORT_STATS;
5036 /* Display extended statistics if FW supports it */
5037 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5038 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5039 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5042 bp->hw_rx_port_stats_ext = (void *)
5043 ((uint8_t *)bp->hw_rx_port_stats +
5044 sizeof(struct rx_port_stats));
5045 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5046 sizeof(struct rx_port_stats);
5047 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5049 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5050 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5051 bp->hw_tx_port_stats_ext = (void *)
5052 ((uint8_t *)bp->hw_tx_port_stats +
5053 sizeof(struct tx_port_stats));
5054 bp->hw_tx_port_stats_ext_map =
5055 bp->hw_tx_port_stats_map +
5056 sizeof(struct tx_port_stats);
5057 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5063 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5065 struct bnxt *bp = eth_dev->data->dev_private;
5068 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5069 RTE_ETHER_ADDR_LEN *
5072 if (eth_dev->data->mac_addrs == NULL) {
5073 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5077 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5081 /* Generate a random MAC address, if none was assigned by PF */
5082 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5083 bnxt_eth_hw_addr_random(bp->mac_addr);
5085 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5086 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5087 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5089 rc = bnxt_hwrm_set_mac(bp);
5094 /* Copy the permanent MAC from the FUNC_QCAPS response */
5095 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5100 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5104 /* MAC is already configured in FW */
5105 if (BNXT_HAS_DFLT_MAC_SET(bp))
5108 /* Restore the old MAC configured */
5109 rc = bnxt_hwrm_set_mac(bp);
5111 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5116 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5121 #define ALLOW_FUNC(x) \
5123 uint32_t arg = (x); \
5124 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5125 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5128 /* Forward all requests if firmware is new enough */
5129 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5130 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5131 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5132 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5134 PMD_DRV_LOG(WARNING,
5135 "Firmware too old for VF mailbox functionality\n");
5136 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5140 * The following are used for driver cleanup. If we disallow these,
5141 * VF drivers can't clean up cleanly.
5143 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5144 ALLOW_FUNC(HWRM_VNIC_FREE);
5145 ALLOW_FUNC(HWRM_RING_FREE);
5146 ALLOW_FUNC(HWRM_RING_GRP_FREE);
5147 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5148 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5149 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5150 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5151 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5155 bnxt_get_svif(uint16_t port_id, bool func_svif,
5156 enum bnxt_ulp_intf_type type)
5158 struct rte_eth_dev *eth_dev;
5161 eth_dev = &rte_eth_devices[port_id];
5162 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5163 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5167 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5170 eth_dev = vfr->parent_dev;
5173 bp = eth_dev->data->dev_private;
5175 return func_svif ? bp->func_svif : bp->port_svif;
5179 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5181 struct rte_eth_dev *eth_dev;
5182 struct bnxt_vnic_info *vnic;
5185 eth_dev = &rte_eth_devices[port];
5186 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5187 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5191 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5192 return vfr->dflt_vnic_id;
5194 eth_dev = vfr->parent_dev;
5197 bp = eth_dev->data->dev_private;
5199 vnic = BNXT_GET_DEFAULT_VNIC(bp);
5201 return vnic->fw_vnic_id;
5205 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5207 struct rte_eth_dev *eth_dev;
5210 eth_dev = &rte_eth_devices[port];
5211 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5212 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5216 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5219 eth_dev = vfr->parent_dev;
5222 bp = eth_dev->data->dev_private;
5227 enum bnxt_ulp_intf_type
5228 bnxt_get_interface_type(uint16_t port)
5230 struct rte_eth_dev *eth_dev;
5233 eth_dev = &rte_eth_devices[port];
5234 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5235 return BNXT_ULP_INTF_TYPE_VF_REP;
5237 bp = eth_dev->data->dev_private;
5239 return BNXT_ULP_INTF_TYPE_PF;
5240 else if (BNXT_VF_IS_TRUSTED(bp))
5241 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5242 else if (BNXT_VF(bp))
5243 return BNXT_ULP_INTF_TYPE_VF;
5245 return BNXT_ULP_INTF_TYPE_INVALID;
5249 bnxt_get_phy_port_id(uint16_t port_id)
5251 struct bnxt_vf_representor *vfr;
5252 struct rte_eth_dev *eth_dev;
5255 eth_dev = &rte_eth_devices[port_id];
5256 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5257 vfr = eth_dev->data->dev_private;
5261 eth_dev = vfr->parent_dev;
5264 bp = eth_dev->data->dev_private;
5266 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5270 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5272 struct rte_eth_dev *eth_dev;
5275 eth_dev = &rte_eth_devices[port_id];
5276 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5277 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5281 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5282 return vfr->fw_fid - 1;
5284 eth_dev = vfr->parent_dev;
5287 bp = eth_dev->data->dev_private;
5289 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5293 bnxt_get_vport(uint16_t port_id)
5295 return (1 << bnxt_get_phy_port_id(port_id));
5298 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5300 struct bnxt_error_recovery_info *info = bp->recovery_info;
5303 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5304 memset(info, 0, sizeof(*info));
5308 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5311 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5314 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5316 bp->recovery_info = info;
5319 static void bnxt_check_fw_status(struct bnxt *bp)
5323 if (!(bp->recovery_info &&
5324 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5327 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5328 if (fw_status != BNXT_FW_STATUS_HEALTHY)
5329 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5333 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5335 struct bnxt_error_recovery_info *info = bp->recovery_info;
5336 uint32_t status_loc;
5339 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5340 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5341 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5342 BNXT_GRCP_WINDOW_2_BASE +
5343 offsetof(struct hcomm_status,
5345 /* If the signature is absent, then FW does not support this feature */
5346 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5347 HCOMM_STATUS_SIGNATURE_VAL)
5351 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5355 bp->recovery_info = info;
5357 memset(info, 0, sizeof(*info));
5360 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5361 BNXT_GRCP_WINDOW_2_BASE +
5362 offsetof(struct hcomm_status,
5365 /* Only pre-map the FW health status GRC register */
5366 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5369 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5370 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5371 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5373 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5374 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5376 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5381 static int bnxt_init_fw(struct bnxt *bp)
5388 rc = bnxt_map_hcomm_fw_status_reg(bp);
5392 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5394 bnxt_check_fw_status(bp);
5398 rc = bnxt_hwrm_func_reset(bp);
5402 rc = bnxt_hwrm_vnic_qcaps(bp);
5406 rc = bnxt_hwrm_queue_qportcfg(bp);
5410 /* Get the MAX capabilities for this function.
5411 * This function also allocates context memory for TQM rings and
5412 * informs the firmware about this allocated backing store memory.
5414 rc = bnxt_hwrm_func_qcaps(bp);
5418 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5422 bnxt_hwrm_port_mac_qcfg(bp);
5424 bnxt_hwrm_parent_pf_qcfg(bp);
5426 bnxt_hwrm_port_phy_qcaps(bp);
5428 bnxt_alloc_error_recovery_info(bp);
5429 /* Get the adapter error recovery support info */
5430 rc = bnxt_hwrm_error_recovery_qcfg(bp);
5432 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5434 bnxt_hwrm_port_led_qcaps(bp);
5440 bnxt_init_locks(struct bnxt *bp)
5444 err = pthread_mutex_init(&bp->flow_lock, NULL);
5446 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5450 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5452 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5456 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5460 rc = bnxt_init_fw(bp);
5464 if (!reconfig_dev) {
5465 rc = bnxt_setup_mac_addr(bp->eth_dev);
5469 rc = bnxt_restore_dflt_mac(bp);
5474 bnxt_config_vf_req_fwd(bp);
5476 rc = bnxt_hwrm_func_driver_register(bp);
5478 PMD_DRV_LOG(ERR, "Failed to register driver");
5483 if (bp->pdev->max_vfs) {
5484 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5486 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5490 rc = bnxt_hwrm_allocate_pf_only(bp);
5493 "Failed to allocate PF resources");
5499 rc = bnxt_alloc_mem(bp, reconfig_dev);
5503 rc = bnxt_setup_int(bp);
5507 rc = bnxt_request_int(bp);
5511 rc = bnxt_init_ctx_mem(bp);
5513 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5517 rc = bnxt_init_locks(bp);
5525 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5526 const char *value, void *opaque_arg)
5528 struct bnxt *bp = opaque_arg;
5529 unsigned long truflow;
5532 if (!value || !opaque_arg) {
5534 "Invalid parameter passed to truflow devargs.\n");
5538 truflow = strtoul(value, &end, 10);
5539 if (end == NULL || *end != '\0' ||
5540 (truflow == ULONG_MAX && errno == ERANGE)) {
5542 "Invalid parameter passed to truflow devargs.\n");
5546 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5548 "Invalid value passed to truflow devargs.\n");
5552 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5553 if (BNXT_TRUFLOW_EN(bp))
5554 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5560 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5561 const char *value, void *opaque_arg)
5563 struct bnxt *bp = opaque_arg;
5564 unsigned long flow_xstat;
5567 if (!value || !opaque_arg) {
5569 "Invalid parameter passed to flow_xstat devarg.\n");
5573 flow_xstat = strtoul(value, &end, 10);
5574 if (end == NULL || *end != '\0' ||
5575 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5577 "Invalid parameter passed to flow_xstat devarg.\n");
5581 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5583 "Invalid value passed to flow_xstat devarg.\n");
5587 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5588 if (BNXT_FLOW_XSTATS_EN(bp))
5589 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5595 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5596 const char *value, void *opaque_arg)
5598 struct bnxt *bp = opaque_arg;
5599 unsigned long max_num_kflows;
5602 if (!value || !opaque_arg) {
5604 "Invalid parameter passed to max_num_kflows devarg.\n");
5608 max_num_kflows = strtoul(value, &end, 10);
5609 if (end == NULL || *end != '\0' ||
5610 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5612 "Invalid parameter passed to max_num_kflows devarg.\n");
5616 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5618 "Invalid value passed to max_num_kflows devarg.\n");
5622 bp->max_num_kflows = max_num_kflows;
5623 if (bp->max_num_kflows)
5624 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5631 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5633 struct rte_kvargs *kvlist;
5635 if (devargs == NULL)
5638 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5643 * Handler for "truflow" devarg.
5644 * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5646 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5647 bnxt_parse_devarg_truflow, bp);
5650 * Handler for "flow_xstat" devarg.
5651 * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5653 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5654 bnxt_parse_devarg_flow_xstat, bp);
5657 * Handler for "max_num_kflows" devarg.
5658 * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5660 rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5661 bnxt_parse_devarg_max_num_kflows, bp);
5663 rte_kvargs_free(kvlist);
5666 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5670 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5671 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5674 "Failed to alloc switch domain: %d\n", rc);
5677 "Switch domain allocated %d\n",
5678 bp->switch_domain_id);
5685 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5687 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5688 static int version_printed;
5692 if (version_printed++ == 0)
5693 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5695 eth_dev->dev_ops = &bnxt_dev_ops;
5696 eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5697 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5698 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5699 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5700 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5703 * For secondary processes, we don't initialise any further
5704 * as primary has already done this work.
5706 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5709 rte_eth_copy_pci_info(eth_dev, pci_dev);
5711 bp = eth_dev->data->dev_private;
5713 /* Parse dev arguments passed on when starting the DPDK application. */
5714 bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5716 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5718 if (bnxt_vf_pciid(pci_dev->id.device_id))
5719 bp->flags |= BNXT_FLAG_VF;
5721 if (bnxt_thor_device(pci_dev->id.device_id))
5722 bp->flags |= BNXT_FLAG_THOR_CHIP;
5724 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5725 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5726 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5727 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5728 bp->flags |= BNXT_FLAG_STINGRAY;
5730 rc = bnxt_init_board(eth_dev);
5733 "Failed to initialize board rc: %x\n", rc);
5737 rc = bnxt_alloc_pf_info(bp);
5741 rc = bnxt_alloc_link_info(bp);
5745 rc = bnxt_alloc_parent_info(bp);
5749 rc = bnxt_alloc_hwrm_resources(bp);
5752 "Failed to allocate hwrm resource rc: %x\n", rc);
5755 rc = bnxt_alloc_leds_info(bp);
5759 rc = bnxt_alloc_cos_queues(bp);
5763 rc = bnxt_init_resources(bp, false);
5767 rc = bnxt_alloc_stats_mem(bp);
5771 bnxt_alloc_switch_domain(bp);
5773 /* Pass the information to the rte_eth_dev_close() that it should also
5774 * release the private port resources.
5776 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5779 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5780 pci_dev->mem_resource[0].phys_addr,
5781 pci_dev->mem_resource[0].addr);
5786 bnxt_dev_uninit(eth_dev);
5791 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5800 ctx->dma = RTE_BAD_IOVA;
5801 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5804 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5806 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5807 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5808 bp->flow_stat->rx_fc_out_tbl.ctx_id,
5809 bp->flow_stat->max_fc,
5812 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5813 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5814 bp->flow_stat->tx_fc_out_tbl.ctx_id,
5815 bp->flow_stat->max_fc,
5818 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5819 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5820 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5822 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5823 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5824 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5826 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5827 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5828 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5830 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5831 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5832 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5835 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5837 bnxt_unregister_fc_ctx_mem(bp);
5839 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5840 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5841 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5842 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5845 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5847 if (BNXT_FLOW_XSTATS_EN(bp))
5848 bnxt_uninit_fc_ctx_mem(bp);
5852 bnxt_free_error_recovery_info(struct bnxt *bp)
5854 rte_free(bp->recovery_info);
5855 bp->recovery_info = NULL;
5856 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5860 bnxt_uninit_locks(struct bnxt *bp)
5862 pthread_mutex_destroy(&bp->flow_lock);
5863 pthread_mutex_destroy(&bp->def_cp_lock);
5865 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5866 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
5871 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5876 bnxt_free_mem(bp, reconfig_dev);
5877 bnxt_hwrm_func_buf_unrgtr(bp);
5878 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5879 bp->flags &= ~BNXT_FLAG_REGISTERED;
5880 bnxt_free_ctx_mem(bp);
5881 if (!reconfig_dev) {
5882 bnxt_free_hwrm_resources(bp);
5883 bnxt_free_error_recovery_info(bp);
5886 bnxt_uninit_ctx_mem(bp);
5888 bnxt_uninit_locks(bp);
5889 bnxt_free_flow_stats_info(bp);
5890 bnxt_free_rep_info(bp);
5891 rte_free(bp->ptp_cfg);
5897 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5899 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5902 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5904 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5905 bnxt_dev_close_op(eth_dev);
5910 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5912 struct bnxt *bp = eth_dev->data->dev_private;
5913 struct rte_eth_dev *vf_rep_eth_dev;
5919 for (i = 0; i < bp->num_reps; i++) {
5920 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5921 if (!vf_rep_eth_dev)
5923 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_vf_representor_uninit);
5925 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5930 static void bnxt_free_rep_info(struct bnxt *bp)
5932 rte_free(bp->rep_info);
5933 bp->rep_info = NULL;
5934 rte_free(bp->cfa_code_map);
5935 bp->cfa_code_map = NULL;
5938 static int bnxt_init_rep_info(struct bnxt *bp)
5945 bp->rep_info = rte_zmalloc("bnxt_rep_info",
5946 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5948 if (!bp->rep_info) {
5949 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5952 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5953 sizeof(*bp->cfa_code_map) *
5954 BNXT_MAX_CFA_CODE, 0);
5955 if (!bp->cfa_code_map) {
5956 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5957 bnxt_free_rep_info(bp);
5961 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5962 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5964 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5966 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5967 bnxt_free_rep_info(bp);
5971 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5973 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5974 bnxt_free_rep_info(bp);
5981 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5982 struct rte_eth_devargs eth_da,
5983 struct rte_eth_dev *backing_eth_dev)
5985 struct rte_eth_dev *vf_rep_eth_dev;
5986 char name[RTE_ETH_NAME_MAX_LEN];
5987 struct bnxt *backing_bp;
5991 num_rep = eth_da.nb_representor_ports;
5992 if (num_rep > BNXT_MAX_VF_REPS) {
5993 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5994 num_rep, BNXT_MAX_VF_REPS);
5998 if (num_rep > RTE_MAX_ETHPORTS) {
6000 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6001 num_rep, RTE_MAX_ETHPORTS);
6005 backing_bp = backing_eth_dev->data->dev_private;
6007 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6009 "Not a PF or trusted VF. No Representor support\n");
6010 /* Returning an error is not an option.
6011 * Applications are not handling this correctly
6016 if (bnxt_init_rep_info(backing_bp))
6019 for (i = 0; i < num_rep; i++) {
6020 struct bnxt_vf_representor representor = {
6021 .vf_id = eth_da.representor_ports[i],
6022 .switch_domain_id = backing_bp->switch_domain_id,
6023 .parent_dev = backing_eth_dev
6026 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6027 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6028 representor.vf_id, BNXT_MAX_VF_REPS);
6032 /* representor port net_bdf_port */
6033 snprintf(name, sizeof(name), "net_%s_representor_%d",
6034 pci_dev->device.name, eth_da.representor_ports[i]);
6036 ret = rte_eth_dev_create(&pci_dev->device, name,
6037 sizeof(struct bnxt_vf_representor),
6039 bnxt_vf_representor_init,
6043 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6044 if (!vf_rep_eth_dev) {
6045 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6046 " for VF-Rep: %s.", name);
6047 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6051 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6053 backing_bp->num_reps++;
6055 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6056 "representor %s.", name);
6057 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6064 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6065 struct rte_pci_device *pci_dev)
6067 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6068 struct rte_eth_dev *backing_eth_dev;
6072 if (pci_dev->device.devargs) {
6073 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6079 num_rep = eth_da.nb_representor_ports;
6080 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6083 /* We could come here after first level of probe is already invoked
6084 * as part of an application bringup(OVS-DPDK vswitchd), so first check
6085 * for already allocated eth_dev for the backing device (PF/Trusted VF)
6087 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6088 if (backing_eth_dev == NULL) {
6089 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6090 sizeof(struct bnxt),
6091 eth_dev_pci_specific_init, pci_dev,
6092 bnxt_dev_init, NULL);
6094 if (ret || !num_rep)
6097 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6100 /* probe representor ports now */
6101 ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev);
6106 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6108 struct rte_eth_dev *eth_dev;
6110 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6112 return 0; /* Invoked typically only by OVS-DPDK, by the
6113 * time it comes here the eth_dev is already
6114 * deleted by rte_eth_dev_close(), so returning
6115 * +ve value will at least help in proper cleanup
6118 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6119 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6120 return rte_eth_dev_destroy(eth_dev,
6121 bnxt_vf_representor_uninit);
6123 return rte_eth_dev_destroy(eth_dev,
6126 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6130 static struct rte_pci_driver bnxt_rte_pmd = {
6131 .id_table = bnxt_pci_id_map,
6132 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6133 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6136 .probe = bnxt_pci_probe,
6137 .remove = bnxt_pci_remove,
6141 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6143 if (strcmp(dev->device->driver->name, drv->driver.name))
6149 bool is_bnxt_supported(struct rte_eth_dev *dev)
6151 return is_device_supported(dev, &bnxt_rte_pmd);
6154 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6155 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6156 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6157 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");