1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
18 #include "bnxt_filter.h"
19 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_stats.h"
27 #include "bnxt_vnic.h"
28 #include "hsi_struct_def_dpdk.h"
29 #include "bnxt_nvm_defs.h"
31 #define DRV_MODULE_NAME "bnxt"
32 static const char bnxt_version[] =
33 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
34 int bnxt_logtype_driver;
37 * The set of PCI devices this driver supports
39 static const struct rte_pci_id bnxt_pci_id_map[] = {
40 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
41 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
42 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
43 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
45 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
93 { .vendor_id = 0, /* sentinel */ },
96 #define BNXT_ETH_RSS_SUPPORT ( \
98 ETH_RSS_NONFRAG_IPV4_TCP | \
99 ETH_RSS_NONFRAG_IPV4_UDP | \
101 ETH_RSS_NONFRAG_IPV6_TCP | \
102 ETH_RSS_NONFRAG_IPV6_UDP)
104 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
105 DEV_TX_OFFLOAD_IPV4_CKSUM | \
106 DEV_TX_OFFLOAD_TCP_CKSUM | \
107 DEV_TX_OFFLOAD_UDP_CKSUM | \
108 DEV_TX_OFFLOAD_TCP_TSO | \
109 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
110 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
111 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
112 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
113 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
114 DEV_TX_OFFLOAD_QINQ_INSERT | \
115 DEV_TX_OFFLOAD_MULTI_SEGS)
117 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
118 DEV_RX_OFFLOAD_VLAN_STRIP | \
119 DEV_RX_OFFLOAD_IPV4_CKSUM | \
120 DEV_RX_OFFLOAD_UDP_CKSUM | \
121 DEV_RX_OFFLOAD_TCP_CKSUM | \
122 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
123 DEV_RX_OFFLOAD_JUMBO_FRAME | \
124 DEV_RX_OFFLOAD_KEEP_CRC | \
125 DEV_RX_OFFLOAD_VLAN_EXTEND | \
126 DEV_RX_OFFLOAD_TCP_LRO | \
127 DEV_RX_OFFLOAD_SCATTER | \
128 DEV_RX_OFFLOAD_RSS_HASH)
130 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
131 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
132 static const char *const bnxt_dev_args[] = {
134 BNXT_DEVARG_FLOW_XSTAT,
139 * truflow == false to disable the feature
140 * truflow == true to enable the feature
142 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
145 * flow_xstat == false to disable the feature
146 * flow_xstat == true to enable the feature
148 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
150 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
151 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
152 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
153 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
154 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
155 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
156 static int bnxt_restore_vlan_filters(struct bnxt *bp);
157 static void bnxt_dev_recover(void *arg);
158 static void bnxt_free_error_recovery_info(struct bnxt *bp);
160 int is_bnxt_in_error(struct bnxt *bp)
162 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
164 if (bp->flags & BNXT_FLAG_FW_RESET)
170 /***********************/
173 * High level utility functions
176 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
178 if (!BNXT_CHIP_THOR(bp))
181 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
182 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
183 BNXT_RSS_ENTRIES_PER_CTX_THOR;
186 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
188 if (!BNXT_CHIP_THOR(bp))
189 return HW_HASH_INDEX_SIZE;
191 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
194 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
196 bnxt_free_filter_mem(bp);
197 bnxt_free_vnic_attributes(bp);
198 bnxt_free_vnic_mem(bp);
200 /* tx/rx rings are configured as part of *_queue_setup callbacks.
201 * If the number of rings change across fw update,
202 * we don't have much choice except to warn the user.
206 bnxt_free_tx_rings(bp);
207 bnxt_free_rx_rings(bp);
209 bnxt_free_async_cp_ring(bp);
210 bnxt_free_rxtx_nq_ring(bp);
212 rte_free(bp->grp_info);
216 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
220 rc = bnxt_alloc_ring_grps(bp);
224 rc = bnxt_alloc_async_ring_struct(bp);
228 rc = bnxt_alloc_vnic_mem(bp);
232 rc = bnxt_alloc_vnic_attributes(bp);
236 rc = bnxt_alloc_filter_mem(bp);
240 rc = bnxt_alloc_async_cp_ring(bp);
244 rc = bnxt_alloc_rxtx_nq_ring(bp);
251 bnxt_free_mem(bp, reconfig);
255 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
257 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
258 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
259 uint64_t rx_offloads = dev_conf->rxmode.offloads;
260 struct bnxt_rx_queue *rxq;
264 rc = bnxt_vnic_grp_alloc(bp, vnic);
268 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
269 vnic_id, vnic, vnic->fw_grp_ids);
271 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
275 /* Alloc RSS context only if RSS mode is enabled */
276 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
277 int j, nr_ctxs = bnxt_rss_ctxts(bp);
280 for (j = 0; j < nr_ctxs; j++) {
281 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
287 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
291 vnic->num_lb_ctxts = nr_ctxs;
295 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
296 * setting is not available at this time, it will not be
297 * configured correctly in the CFA.
299 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
300 vnic->vlan_strip = true;
302 vnic->vlan_strip = false;
304 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
308 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
312 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
313 rxq = bp->eth_dev->data->rx_queues[j];
316 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
317 j, rxq->vnic, rxq->vnic->fw_grp_ids);
319 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
320 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
322 vnic->rx_queue_cnt++;
325 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
327 rc = bnxt_vnic_rss_configure(bp, vnic);
331 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
333 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
334 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
336 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
340 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
345 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
349 rc = bnxt_hwrm_ctx_rgtr(bp, bp->rx_fc_in_tbl.dma,
350 &bp->rx_fc_in_tbl.ctx_id);
355 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
356 " rx_fc_in_tbl.ctx_id = %d\n",
358 (void *)((uintptr_t)bp->rx_fc_in_tbl.dma),
359 bp->rx_fc_in_tbl.ctx_id);
361 rc = bnxt_hwrm_ctx_rgtr(bp, bp->rx_fc_out_tbl.dma,
362 &bp->rx_fc_out_tbl.ctx_id);
367 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
368 " rx_fc_out_tbl.ctx_id = %d\n",
369 bp->rx_fc_out_tbl.va,
370 (void *)((uintptr_t)bp->rx_fc_out_tbl.dma),
371 bp->rx_fc_out_tbl.ctx_id);
373 rc = bnxt_hwrm_ctx_rgtr(bp, bp->tx_fc_in_tbl.dma,
374 &bp->tx_fc_in_tbl.ctx_id);
379 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
380 " tx_fc_in_tbl.ctx_id = %d\n",
382 (void *)((uintptr_t)bp->tx_fc_in_tbl.dma),
383 bp->tx_fc_in_tbl.ctx_id);
385 rc = bnxt_hwrm_ctx_rgtr(bp, bp->tx_fc_out_tbl.dma,
386 &bp->tx_fc_out_tbl.ctx_id);
391 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
392 " tx_fc_out_tbl.ctx_id = %d\n",
393 bp->tx_fc_out_tbl.va,
394 (void *)((uintptr_t)bp->tx_fc_out_tbl.dma),
395 bp->tx_fc_out_tbl.ctx_id);
397 memset(bp->rx_fc_out_tbl.va, 0, bp->rx_fc_out_tbl.size);
398 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
399 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
400 bp->rx_fc_out_tbl.ctx_id,
406 memset(bp->tx_fc_out_tbl.va, 0, bp->tx_fc_out_tbl.size);
407 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
408 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
409 bp->tx_fc_out_tbl.ctx_id,
416 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
417 struct bnxt_ctx_mem_buf_info *ctx)
422 ctx->va = rte_zmalloc(type, size, 0);
425 rte_mem_lock_page(ctx->va);
427 ctx->dma = rte_mem_virt2iova(ctx->va);
428 if (ctx->dma == RTE_BAD_IOVA)
434 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
436 struct rte_pci_device *pdev = bp->pdev;
437 char type[RTE_MEMZONE_NAMESIZE];
443 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
444 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
445 /* 4 bytes for each counter-id */
446 rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 4, &bp->rx_fc_in_tbl);
450 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
451 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
452 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
453 rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 16, &bp->rx_fc_out_tbl);
457 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
458 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
459 /* 4 bytes for each counter-id */
460 rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 4, &bp->tx_fc_in_tbl);
464 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
465 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
466 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
467 rc = bnxt_alloc_ctx_mem_buf(type, max_fc * 16, &bp->tx_fc_out_tbl);
471 rc = bnxt_register_fc_ctx_mem(bp);
476 static int bnxt_init_ctx_mem(struct bnxt *bp)
480 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
481 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
484 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->max_fc);
488 rc = bnxt_init_fc_ctx_mem(bp);
493 static int bnxt_init_chip(struct bnxt *bp)
495 struct rte_eth_link new;
496 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
497 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
498 uint32_t intr_vector = 0;
499 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
500 uint32_t vec = BNXT_MISC_VEC_ID;
504 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
505 bp->eth_dev->data->dev_conf.rxmode.offloads |=
506 DEV_RX_OFFLOAD_JUMBO_FRAME;
507 bp->flags |= BNXT_FLAG_JUMBO;
509 bp->eth_dev->data->dev_conf.rxmode.offloads &=
510 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
511 bp->flags &= ~BNXT_FLAG_JUMBO;
514 /* THOR does not support ring groups.
515 * But we will use the array to save RSS context IDs.
517 if (BNXT_CHIP_THOR(bp))
518 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
520 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
522 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
526 rc = bnxt_alloc_hwrm_rings(bp);
528 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
532 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
534 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
538 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
541 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
542 if (bp->rx_cos_queue[i].id != 0xff) {
543 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
547 "Num pools more than FW profile\n");
551 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
557 rc = bnxt_mq_rx_configure(bp);
559 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
563 /* VNIC configuration */
564 for (i = 0; i < bp->nr_vnics; i++) {
565 rc = bnxt_setup_one_vnic(bp, i);
570 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
573 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
577 /* check and configure queue intr-vector mapping */
578 if ((rte_intr_cap_multiple(intr_handle) ||
579 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
580 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
581 intr_vector = bp->eth_dev->data->nb_rx_queues;
582 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
583 if (intr_vector > bp->rx_cp_nr_rings) {
584 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
588 rc = rte_intr_efd_enable(intr_handle, intr_vector);
593 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
594 intr_handle->intr_vec =
595 rte_zmalloc("intr_vec",
596 bp->eth_dev->data->nb_rx_queues *
598 if (intr_handle->intr_vec == NULL) {
599 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
600 " intr_vec", bp->eth_dev->data->nb_rx_queues);
604 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
605 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
606 intr_handle->intr_vec, intr_handle->nb_efd,
607 intr_handle->max_intr);
608 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
610 intr_handle->intr_vec[queue_id] =
611 vec + BNXT_RX_VEC_START;
612 if (vec < base + intr_handle->nb_efd - 1)
617 /* enable uio/vfio intr/eventfd mapping */
618 rc = rte_intr_enable(intr_handle);
619 #ifndef RTE_EXEC_ENV_FREEBSD
620 /* In FreeBSD OS, nic_uio driver does not support interrupts */
625 rc = bnxt_get_hwrm_link_config(bp, &new);
627 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
631 if (!bp->link_info.link_up) {
632 rc = bnxt_set_hwrm_link_config(bp, true);
635 "HWRM link config failure rc: %x\n", rc);
639 bnxt_print_link_info(bp->eth_dev);
641 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
643 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
648 rte_free(intr_handle->intr_vec);
650 rte_intr_efd_disable(intr_handle);
652 /* Some of the error status returned by FW may not be from errno.h */
659 static int bnxt_shutdown_nic(struct bnxt *bp)
661 bnxt_free_all_hwrm_resources(bp);
662 bnxt_free_all_filters(bp);
663 bnxt_free_all_vnics(bp);
668 * Device configuration and status function
671 static uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
673 uint32_t link_speed = bp->link_info.support_speeds;
674 uint32_t speed_capa = 0;
676 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
677 speed_capa |= ETH_LINK_SPEED_100M;
678 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
679 speed_capa |= ETH_LINK_SPEED_100M_HD;
680 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
681 speed_capa |= ETH_LINK_SPEED_1G;
682 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
683 speed_capa |= ETH_LINK_SPEED_2_5G;
684 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
685 speed_capa |= ETH_LINK_SPEED_10G;
686 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
687 speed_capa |= ETH_LINK_SPEED_20G;
688 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
689 speed_capa |= ETH_LINK_SPEED_25G;
690 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
691 speed_capa |= ETH_LINK_SPEED_40G;
692 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
693 speed_capa |= ETH_LINK_SPEED_50G;
694 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
695 speed_capa |= ETH_LINK_SPEED_100G;
696 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
697 speed_capa |= ETH_LINK_SPEED_200G;
699 if (bp->link_info.auto_mode == HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
700 speed_capa |= ETH_LINK_SPEED_FIXED;
702 speed_capa |= ETH_LINK_SPEED_AUTONEG;
707 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
708 struct rte_eth_dev_info *dev_info)
710 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
711 struct bnxt *bp = eth_dev->data->dev_private;
712 uint16_t max_vnics, i, j, vpool, vrxq;
713 unsigned int max_rx_rings;
716 rc = is_bnxt_in_error(bp);
721 dev_info->max_mac_addrs = bp->max_l2_ctx;
722 dev_info->max_hash_mac_addrs = 0;
724 /* PF/VF specifics */
726 dev_info->max_vfs = pdev->max_vfs;
728 max_rx_rings = BNXT_MAX_RINGS(bp);
729 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
730 dev_info->max_rx_queues = max_rx_rings;
731 dev_info->max_tx_queues = max_rx_rings;
732 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
733 dev_info->hash_key_size = 40;
734 max_vnics = bp->max_vnics;
737 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
738 dev_info->max_mtu = BNXT_MAX_MTU;
740 /* Fast path specifics */
741 dev_info->min_rx_bufsize = 1;
742 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
744 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
745 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
746 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
747 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
748 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
750 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
753 dev_info->default_rxconf = (struct rte_eth_rxconf) {
759 .rx_free_thresh = 32,
760 /* If no descriptors available, pkts are dropped by default */
764 dev_info->default_txconf = (struct rte_eth_txconf) {
770 .tx_free_thresh = 32,
773 eth_dev->data->dev_conf.intr_conf.lsc = 1;
775 eth_dev->data->dev_conf.intr_conf.rxq = 1;
776 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
777 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
778 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
779 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
784 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
785 * need further investigation.
789 vpool = 64; /* ETH_64_POOLS */
790 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
791 for (i = 0; i < 4; vpool >>= 1, i++) {
792 if (max_vnics > vpool) {
793 for (j = 0; j < 5; vrxq >>= 1, j++) {
794 if (dev_info->max_rx_queues > vrxq) {
800 /* Not enough resources to support VMDq */
804 /* Not enough resources to support VMDq */
808 dev_info->max_vmdq_pools = vpool;
809 dev_info->vmdq_queue_num = vrxq;
811 dev_info->vmdq_pool_base = 0;
812 dev_info->vmdq_queue_base = 0;
817 /* Configure the device based on the configuration provided */
818 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
820 struct bnxt *bp = eth_dev->data->dev_private;
821 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
824 bp->rx_queues = (void *)eth_dev->data->rx_queues;
825 bp->tx_queues = (void *)eth_dev->data->tx_queues;
826 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
827 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
829 rc = is_bnxt_in_error(bp);
833 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
834 rc = bnxt_hwrm_check_vf_rings(bp);
836 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
840 /* If a resource has already been allocated - in this case
841 * it is the async completion ring, free it. Reallocate it after
842 * resource reservation. This will ensure the resource counts
843 * are calculated correctly.
846 pthread_mutex_lock(&bp->def_cp_lock);
848 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
849 bnxt_disable_int(bp);
850 bnxt_free_cp_ring(bp, bp->async_cp_ring);
853 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
855 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
856 pthread_mutex_unlock(&bp->def_cp_lock);
860 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
861 rc = bnxt_alloc_async_cp_ring(bp);
863 pthread_mutex_unlock(&bp->def_cp_lock);
869 pthread_mutex_unlock(&bp->def_cp_lock);
871 /* legacy driver needs to get updated values */
872 rc = bnxt_hwrm_func_qcaps(bp);
874 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
879 /* Inherit new configurations */
880 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
881 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
882 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
883 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
884 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
888 if (BNXT_HAS_RING_GRPS(bp) &&
889 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
892 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
893 bp->max_vnics < eth_dev->data->nb_rx_queues)
896 bp->rx_cp_nr_rings = bp->rx_nr_rings;
897 bp->tx_cp_nr_rings = bp->tx_nr_rings;
899 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
900 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
901 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
903 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
905 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
906 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
908 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
914 "Insufficient resources to support requested config\n");
916 "Num Queues Requested: Tx %d, Rx %d\n",
917 eth_dev->data->nb_tx_queues,
918 eth_dev->data->nb_rx_queues);
920 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
921 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
922 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
926 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
928 struct rte_eth_link *link = ð_dev->data->dev_link;
930 if (link->link_status)
931 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
932 eth_dev->data->port_id,
933 (uint32_t)link->link_speed,
934 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
935 ("full-duplex") : ("half-duplex\n"));
937 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
938 eth_dev->data->port_id);
942 * Determine whether the current configuration requires support for scattered
943 * receive; return 1 if scattered receive is required and 0 if not.
945 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
950 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
953 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
954 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
956 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
957 RTE_PKTMBUF_HEADROOM);
958 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
964 static eth_rx_burst_t
965 bnxt_receive_function(struct rte_eth_dev *eth_dev)
967 struct bnxt *bp = eth_dev->data->dev_private;
970 #ifndef RTE_LIBRTE_IEEE1588
972 * Vector mode receive can be enabled only if scatter rx is not
973 * in use and rx offloads are limited to VLAN stripping and
976 if (!eth_dev->data->scattered_rx &&
977 !(eth_dev->data->dev_conf.rxmode.offloads &
978 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
979 DEV_RX_OFFLOAD_KEEP_CRC |
980 DEV_RX_OFFLOAD_JUMBO_FRAME |
981 DEV_RX_OFFLOAD_IPV4_CKSUM |
982 DEV_RX_OFFLOAD_UDP_CKSUM |
983 DEV_RX_OFFLOAD_TCP_CKSUM |
984 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
985 DEV_RX_OFFLOAD_RSS_HASH |
986 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
988 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
989 eth_dev->data->port_id);
990 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
991 return bnxt_recv_pkts_vec;
993 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
994 eth_dev->data->port_id);
996 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
997 eth_dev->data->port_id,
998 eth_dev->data->scattered_rx,
999 eth_dev->data->dev_conf.rxmode.offloads);
1002 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1003 return bnxt_recv_pkts;
1006 static eth_tx_burst_t
1007 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1010 #ifndef RTE_LIBRTE_IEEE1588
1012 * Vector mode transmit can be enabled only if not using scatter rx
1015 if (!eth_dev->data->scattered_rx &&
1016 !eth_dev->data->dev_conf.txmode.offloads) {
1017 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1018 eth_dev->data->port_id);
1019 return bnxt_xmit_pkts_vec;
1021 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1022 eth_dev->data->port_id);
1024 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1025 eth_dev->data->port_id,
1026 eth_dev->data->scattered_rx,
1027 eth_dev->data->dev_conf.txmode.offloads);
1030 return bnxt_xmit_pkts;
1033 static int bnxt_handle_if_change_status(struct bnxt *bp)
1037 /* Since fw has undergone a reset and lost all contexts,
1038 * set fatal flag to not issue hwrm during cleanup
1040 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1041 bnxt_uninit_resources(bp, true);
1043 /* clear fatal flag so that re-init happens */
1044 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1045 rc = bnxt_init_resources(bp, true);
1047 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1052 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1054 struct bnxt *bp = eth_dev->data->dev_private;
1055 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1057 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1059 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1060 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1064 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1066 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1067 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1071 rc = bnxt_hwrm_if_change(bp, true);
1072 if (rc == 0 || rc != -EAGAIN)
1075 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1076 } while (retry_cnt--);
1081 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1082 rc = bnxt_handle_if_change_status(bp);
1087 bnxt_enable_int(bp);
1089 rc = bnxt_init_chip(bp);
1093 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1094 eth_dev->data->dev_started = 1;
1096 bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1098 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1099 vlan_mask |= ETH_VLAN_FILTER_MASK;
1100 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1101 vlan_mask |= ETH_VLAN_STRIP_MASK;
1102 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1106 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1107 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1109 pthread_mutex_lock(&bp->def_cp_lock);
1110 bnxt_schedule_fw_health_check(bp);
1111 pthread_mutex_unlock(&bp->def_cp_lock);
1119 bnxt_shutdown_nic(bp);
1120 bnxt_free_tx_mbufs(bp);
1121 bnxt_free_rx_mbufs(bp);
1122 bnxt_hwrm_if_change(bp, false);
1123 eth_dev->data->dev_started = 0;
1127 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1129 struct bnxt *bp = eth_dev->data->dev_private;
1132 if (!bp->link_info.link_up)
1133 rc = bnxt_set_hwrm_link_config(bp, true);
1135 eth_dev->data->dev_link.link_status = 1;
1137 bnxt_print_link_info(eth_dev);
1141 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1143 struct bnxt *bp = eth_dev->data->dev_private;
1145 eth_dev->data->dev_link.link_status = 0;
1146 bnxt_set_hwrm_link_config(bp, false);
1147 bp->link_info.link_up = 0;
1152 /* Unload the driver, release resources */
1153 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1155 struct bnxt *bp = eth_dev->data->dev_private;
1156 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1157 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1160 bnxt_ulp_deinit(bp);
1162 eth_dev->data->dev_started = 0;
1163 /* Prevent crashes when queues are still in use */
1164 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1165 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1167 bnxt_disable_int(bp);
1169 /* disable uio/vfio intr/eventfd mapping */
1170 rte_intr_disable(intr_handle);
1172 bnxt_cancel_fw_health_check(bp);
1174 bnxt_dev_set_link_down_op(eth_dev);
1176 /* Wait for link to be reset and the async notification to process.
1177 * During reset recovery, there is no need to wait and
1178 * VF/NPAR functions do not have privilege to change PHY config.
1180 if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1181 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1183 /* Clean queue intr-vector mapping */
1184 rte_intr_efd_disable(intr_handle);
1185 if (intr_handle->intr_vec != NULL) {
1186 rte_free(intr_handle->intr_vec);
1187 intr_handle->intr_vec = NULL;
1190 bnxt_hwrm_port_clr_stats(bp);
1191 bnxt_free_tx_mbufs(bp);
1192 bnxt_free_rx_mbufs(bp);
1193 /* Process any remaining notifications in default completion queue */
1194 bnxt_int_handler(eth_dev);
1195 bnxt_shutdown_nic(bp);
1196 bnxt_hwrm_if_change(bp, false);
1198 rte_free(bp->mark_table);
1199 bp->mark_table = NULL;
1201 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1202 bp->rx_cosq_cnt = 0;
1205 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1207 struct bnxt *bp = eth_dev->data->dev_private;
1209 /* cancel the recovery handler before remove dev */
1210 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1211 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1212 bnxt_cancel_fc_thread(bp);
1214 if (eth_dev->data->dev_started)
1215 bnxt_dev_stop_op(eth_dev);
1217 bnxt_uninit_resources(bp, false);
1219 eth_dev->dev_ops = NULL;
1220 eth_dev->rx_pkt_burst = NULL;
1221 eth_dev->tx_pkt_burst = NULL;
1223 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1224 bp->tx_mem_zone = NULL;
1225 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1226 bp->rx_mem_zone = NULL;
1228 rte_free(bp->pf.vf_info);
1229 bp->pf.vf_info = NULL;
1231 rte_free(bp->grp_info);
1232 bp->grp_info = NULL;
1235 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1238 struct bnxt *bp = eth_dev->data->dev_private;
1239 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1240 struct bnxt_vnic_info *vnic;
1241 struct bnxt_filter_info *filter, *temp_filter;
1244 if (is_bnxt_in_error(bp))
1248 * Loop through all VNICs from the specified filter flow pools to
1249 * remove the corresponding MAC addr filter
1251 for (i = 0; i < bp->nr_vnics; i++) {
1252 if (!(pool_mask & (1ULL << i)))
1255 vnic = &bp->vnic_info[i];
1256 filter = STAILQ_FIRST(&vnic->filter);
1258 temp_filter = STAILQ_NEXT(filter, next);
1259 if (filter->mac_index == index) {
1260 STAILQ_REMOVE(&vnic->filter, filter,
1261 bnxt_filter_info, next);
1262 bnxt_hwrm_clear_l2_filter(bp, filter);
1263 bnxt_free_filter(bp, filter);
1265 filter = temp_filter;
1270 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1271 struct rte_ether_addr *mac_addr, uint32_t index,
1274 struct bnxt_filter_info *filter;
1277 /* Attach requested MAC address to the new l2_filter */
1278 STAILQ_FOREACH(filter, &vnic->filter, next) {
1279 if (filter->mac_index == index) {
1281 "MAC addr already existed for pool %d\n",
1287 filter = bnxt_alloc_filter(bp);
1289 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1293 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1294 * if the MAC that's been programmed now is a different one, then,
1295 * copy that addr to filter->l2_addr
1298 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1299 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1301 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1303 filter->mac_index = index;
1304 if (filter->mac_index == 0)
1305 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1307 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1309 bnxt_free_filter(bp, filter);
1315 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1316 struct rte_ether_addr *mac_addr,
1317 uint32_t index, uint32_t pool)
1319 struct bnxt *bp = eth_dev->data->dev_private;
1320 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1323 rc = is_bnxt_in_error(bp);
1327 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1328 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1333 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1337 /* Filter settings will get applied when port is started */
1338 if (!eth_dev->data->dev_started)
1341 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1346 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1347 bool exp_link_status)
1350 struct bnxt *bp = eth_dev->data->dev_private;
1351 struct rte_eth_link new;
1352 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1353 BNXT_LINK_DOWN_WAIT_CNT;
1355 rc = is_bnxt_in_error(bp);
1359 memset(&new, 0, sizeof(new));
1361 /* Retrieve link info from hardware */
1362 rc = bnxt_get_hwrm_link_config(bp, &new);
1364 new.link_speed = ETH_LINK_SPEED_100M;
1365 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1367 "Failed to retrieve link rc = 0x%x!\n", rc);
1371 if (!wait_to_complete || new.link_status == exp_link_status)
1374 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1378 /* Timed out or success */
1379 if (new.link_status != eth_dev->data->dev_link.link_status ||
1380 new.link_speed != eth_dev->data->dev_link.link_speed) {
1381 rte_eth_linkstatus_set(eth_dev, &new);
1383 _rte_eth_dev_callback_process(eth_dev,
1384 RTE_ETH_EVENT_INTR_LSC,
1387 bnxt_print_link_info(eth_dev);
1393 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1394 int wait_to_complete)
1396 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1399 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1401 struct bnxt *bp = eth_dev->data->dev_private;
1402 struct bnxt_vnic_info *vnic;
1406 rc = is_bnxt_in_error(bp);
1410 /* Filter settings will get applied when port is started */
1411 if (!eth_dev->data->dev_started)
1414 if (bp->vnic_info == NULL)
1417 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1419 old_flags = vnic->flags;
1420 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1421 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1423 vnic->flags = old_flags;
1428 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1430 struct bnxt *bp = eth_dev->data->dev_private;
1431 struct bnxt_vnic_info *vnic;
1435 rc = is_bnxt_in_error(bp);
1439 /* Filter settings will get applied when port is started */
1440 if (!eth_dev->data->dev_started)
1443 if (bp->vnic_info == NULL)
1446 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1448 old_flags = vnic->flags;
1449 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1450 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1452 vnic->flags = old_flags;
1457 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1459 struct bnxt *bp = eth_dev->data->dev_private;
1460 struct bnxt_vnic_info *vnic;
1464 rc = is_bnxt_in_error(bp);
1468 /* Filter settings will get applied when port is started */
1469 if (!eth_dev->data->dev_started)
1472 if (bp->vnic_info == NULL)
1475 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1477 old_flags = vnic->flags;
1478 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1479 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1481 vnic->flags = old_flags;
1486 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1488 struct bnxt *bp = eth_dev->data->dev_private;
1489 struct bnxt_vnic_info *vnic;
1493 rc = is_bnxt_in_error(bp);
1497 /* Filter settings will get applied when port is started */
1498 if (!eth_dev->data->dev_started)
1501 if (bp->vnic_info == NULL)
1504 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1506 old_flags = vnic->flags;
1507 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1508 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1510 vnic->flags = old_flags;
1515 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1516 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1518 if (qid >= bp->rx_nr_rings)
1521 return bp->eth_dev->data->rx_queues[qid];
1524 /* Return rxq corresponding to a given rss table ring/group ID. */
1525 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1527 struct bnxt_rx_queue *rxq;
1530 if (!BNXT_HAS_RING_GRPS(bp)) {
1531 for (i = 0; i < bp->rx_nr_rings; i++) {
1532 rxq = bp->eth_dev->data->rx_queues[i];
1533 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1537 for (i = 0; i < bp->rx_nr_rings; i++) {
1538 if (bp->grp_info[i].fw_grp_id == fwr)
1543 return INVALID_HW_RING_ID;
1546 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1547 struct rte_eth_rss_reta_entry64 *reta_conf,
1550 struct bnxt *bp = eth_dev->data->dev_private;
1551 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1552 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1553 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1557 rc = is_bnxt_in_error(bp);
1561 if (!vnic->rss_table)
1564 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1567 if (reta_size != tbl_size) {
1568 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1569 "(%d) must equal the size supported by the hardware "
1570 "(%d)\n", reta_size, tbl_size);
1574 for (i = 0; i < reta_size; i++) {
1575 struct bnxt_rx_queue *rxq;
1577 idx = i / RTE_RETA_GROUP_SIZE;
1578 sft = i % RTE_RETA_GROUP_SIZE;
1580 if (!(reta_conf[idx].mask & (1ULL << sft)))
1583 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1585 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1589 if (BNXT_CHIP_THOR(bp)) {
1590 vnic->rss_table[i * 2] =
1591 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1592 vnic->rss_table[i * 2 + 1] =
1593 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1595 vnic->rss_table[i] =
1596 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1600 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1604 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1605 struct rte_eth_rss_reta_entry64 *reta_conf,
1608 struct bnxt *bp = eth_dev->data->dev_private;
1609 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1610 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1611 uint16_t idx, sft, i;
1614 rc = is_bnxt_in_error(bp);
1618 /* Retrieve from the default VNIC */
1621 if (!vnic->rss_table)
1624 if (reta_size != tbl_size) {
1625 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1626 "(%d) must equal the size supported by the hardware "
1627 "(%d)\n", reta_size, tbl_size);
1631 for (idx = 0, i = 0; i < reta_size; i++) {
1632 idx = i / RTE_RETA_GROUP_SIZE;
1633 sft = i % RTE_RETA_GROUP_SIZE;
1635 if (reta_conf[idx].mask & (1ULL << sft)) {
1638 if (BNXT_CHIP_THOR(bp))
1639 qid = bnxt_rss_to_qid(bp,
1640 vnic->rss_table[i * 2]);
1642 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1644 if (qid == INVALID_HW_RING_ID) {
1645 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1648 reta_conf[idx].reta[sft] = qid;
1655 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1656 struct rte_eth_rss_conf *rss_conf)
1658 struct bnxt *bp = eth_dev->data->dev_private;
1659 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1660 struct bnxt_vnic_info *vnic;
1663 rc = is_bnxt_in_error(bp);
1668 * If RSS enablement were different than dev_configure,
1669 * then return -EINVAL
1671 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1672 if (!rss_conf->rss_hf)
1673 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1675 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1679 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1680 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1682 /* Update the default RSS VNIC(s) */
1683 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1684 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1687 * If hashkey is not specified, use the previously configured
1690 if (!rss_conf->rss_key)
1693 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1695 "Invalid hashkey length, should be 16 bytes\n");
1698 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1701 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1705 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1706 struct rte_eth_rss_conf *rss_conf)
1708 struct bnxt *bp = eth_dev->data->dev_private;
1709 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1711 uint32_t hash_types;
1713 rc = is_bnxt_in_error(bp);
1717 /* RSS configuration is the same for all VNICs */
1718 if (vnic && vnic->rss_hash_key) {
1719 if (rss_conf->rss_key) {
1720 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1721 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1722 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1725 hash_types = vnic->hash_type;
1726 rss_conf->rss_hf = 0;
1727 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1728 rss_conf->rss_hf |= ETH_RSS_IPV4;
1729 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1731 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1732 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1734 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1736 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1737 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1739 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1741 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1742 rss_conf->rss_hf |= ETH_RSS_IPV6;
1743 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1745 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1746 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1748 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1750 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1751 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1753 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1757 "Unknown RSS config from firmware (%08x), RSS disabled",
1762 rss_conf->rss_hf = 0;
1767 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1768 struct rte_eth_fc_conf *fc_conf)
1770 struct bnxt *bp = dev->data->dev_private;
1771 struct rte_eth_link link_info;
1774 rc = is_bnxt_in_error(bp);
1778 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1782 memset(fc_conf, 0, sizeof(*fc_conf));
1783 if (bp->link_info.auto_pause)
1784 fc_conf->autoneg = 1;
1785 switch (bp->link_info.pause) {
1787 fc_conf->mode = RTE_FC_NONE;
1789 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1790 fc_conf->mode = RTE_FC_TX_PAUSE;
1792 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1793 fc_conf->mode = RTE_FC_RX_PAUSE;
1795 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1796 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1797 fc_conf->mode = RTE_FC_FULL;
1803 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1804 struct rte_eth_fc_conf *fc_conf)
1806 struct bnxt *bp = dev->data->dev_private;
1809 rc = is_bnxt_in_error(bp);
1813 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1814 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1818 switch (fc_conf->mode) {
1820 bp->link_info.auto_pause = 0;
1821 bp->link_info.force_pause = 0;
1823 case RTE_FC_RX_PAUSE:
1824 if (fc_conf->autoneg) {
1825 bp->link_info.auto_pause =
1826 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1827 bp->link_info.force_pause = 0;
1829 bp->link_info.auto_pause = 0;
1830 bp->link_info.force_pause =
1831 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1834 case RTE_FC_TX_PAUSE:
1835 if (fc_conf->autoneg) {
1836 bp->link_info.auto_pause =
1837 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1838 bp->link_info.force_pause = 0;
1840 bp->link_info.auto_pause = 0;
1841 bp->link_info.force_pause =
1842 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1846 if (fc_conf->autoneg) {
1847 bp->link_info.auto_pause =
1848 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1849 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1850 bp->link_info.force_pause = 0;
1852 bp->link_info.auto_pause = 0;
1853 bp->link_info.force_pause =
1854 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1855 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1859 return bnxt_set_hwrm_link_config(bp, true);
1862 /* Add UDP tunneling port */
1864 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1865 struct rte_eth_udp_tunnel *udp_tunnel)
1867 struct bnxt *bp = eth_dev->data->dev_private;
1868 uint16_t tunnel_type = 0;
1871 rc = is_bnxt_in_error(bp);
1875 switch (udp_tunnel->prot_type) {
1876 case RTE_TUNNEL_TYPE_VXLAN:
1877 if (bp->vxlan_port_cnt) {
1878 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1879 udp_tunnel->udp_port);
1880 if (bp->vxlan_port != udp_tunnel->udp_port) {
1881 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1884 bp->vxlan_port_cnt++;
1888 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1889 bp->vxlan_port_cnt++;
1891 case RTE_TUNNEL_TYPE_GENEVE:
1892 if (bp->geneve_port_cnt) {
1893 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1894 udp_tunnel->udp_port);
1895 if (bp->geneve_port != udp_tunnel->udp_port) {
1896 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1899 bp->geneve_port_cnt++;
1903 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1904 bp->geneve_port_cnt++;
1907 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1910 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1916 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1917 struct rte_eth_udp_tunnel *udp_tunnel)
1919 struct bnxt *bp = eth_dev->data->dev_private;
1920 uint16_t tunnel_type = 0;
1924 rc = is_bnxt_in_error(bp);
1928 switch (udp_tunnel->prot_type) {
1929 case RTE_TUNNEL_TYPE_VXLAN:
1930 if (!bp->vxlan_port_cnt) {
1931 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1934 if (bp->vxlan_port != udp_tunnel->udp_port) {
1935 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1936 udp_tunnel->udp_port, bp->vxlan_port);
1939 if (--bp->vxlan_port_cnt)
1943 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1944 port = bp->vxlan_fw_dst_port_id;
1946 case RTE_TUNNEL_TYPE_GENEVE:
1947 if (!bp->geneve_port_cnt) {
1948 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1951 if (bp->geneve_port != udp_tunnel->udp_port) {
1952 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1953 udp_tunnel->udp_port, bp->geneve_port);
1956 if (--bp->geneve_port_cnt)
1960 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1961 port = bp->geneve_fw_dst_port_id;
1964 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1968 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1971 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1974 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1975 bp->geneve_port = 0;
1980 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1982 struct bnxt_filter_info *filter;
1983 struct bnxt_vnic_info *vnic;
1985 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1987 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1988 filter = STAILQ_FIRST(&vnic->filter);
1990 /* Search for this matching MAC+VLAN filter */
1991 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1992 /* Delete the filter */
1993 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1996 STAILQ_REMOVE(&vnic->filter, filter,
1997 bnxt_filter_info, next);
1998 bnxt_free_filter(bp, filter);
2000 "Deleted vlan filter for %d\n",
2004 filter = STAILQ_NEXT(filter, next);
2009 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2011 struct bnxt_filter_info *filter;
2012 struct bnxt_vnic_info *vnic;
2014 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2015 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2016 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2018 /* Implementation notes on the use of VNIC in this command:
2020 * By default, these filters belong to default vnic for the function.
2021 * Once these filters are set up, only destination VNIC can be modified.
2022 * If the destination VNIC is not specified in this command,
2023 * then the HWRM shall only create an l2 context id.
2026 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2027 filter = STAILQ_FIRST(&vnic->filter);
2028 /* Check if the VLAN has already been added */
2030 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2033 filter = STAILQ_NEXT(filter, next);
2036 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2037 * command to create MAC+VLAN filter with the right flags, enables set.
2039 filter = bnxt_alloc_filter(bp);
2042 "MAC/VLAN filter alloc failed\n");
2045 /* MAC + VLAN ID filter */
2046 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2047 * untagged packets are received
2049 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2050 * packets and only the programmed vlan's packets are received
2052 filter->l2_ivlan = vlan_id;
2053 filter->l2_ivlan_mask = 0x0FFF;
2054 filter->enables |= en;
2055 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2057 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2059 /* Free the newly allocated filter as we were
2060 * not able to create the filter in hardware.
2062 bnxt_free_filter(bp, filter);
2066 filter->mac_index = 0;
2067 /* Add this new filter to the list */
2069 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2071 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2074 "Added Vlan filter for %d\n", vlan_id);
2078 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2079 uint16_t vlan_id, int on)
2081 struct bnxt *bp = eth_dev->data->dev_private;
2084 rc = is_bnxt_in_error(bp);
2088 if (!eth_dev->data->dev_started) {
2089 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2093 /* These operations apply to ALL existing MAC/VLAN filters */
2095 return bnxt_add_vlan_filter(bp, vlan_id);
2097 return bnxt_del_vlan_filter(bp, vlan_id);
2100 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2101 struct bnxt_vnic_info *vnic)
2103 struct bnxt_filter_info *filter;
2106 filter = STAILQ_FIRST(&vnic->filter);
2108 if (filter->mac_index == 0 &&
2109 !memcmp(filter->l2_addr, bp->mac_addr,
2110 RTE_ETHER_ADDR_LEN)) {
2111 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2113 STAILQ_REMOVE(&vnic->filter, filter,
2114 bnxt_filter_info, next);
2115 bnxt_free_filter(bp, filter);
2119 filter = STAILQ_NEXT(filter, next);
2125 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2127 struct bnxt_vnic_info *vnic;
2131 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2132 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2133 /* Remove any VLAN filters programmed */
2134 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2135 bnxt_del_vlan_filter(bp, i);
2137 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2141 /* Default filter will allow packets that match the
2142 * dest mac. So, it has to be deleted, otherwise, we
2143 * will endup receiving vlan packets for which the
2144 * filter is not programmed, when hw-vlan-filter
2145 * configuration is ON
2147 bnxt_del_dflt_mac_filter(bp, vnic);
2148 /* This filter will allow only untagged packets */
2149 bnxt_add_vlan_filter(bp, 0);
2151 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2152 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2157 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2159 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2163 /* Destroy vnic filters and vnic */
2164 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2165 DEV_RX_OFFLOAD_VLAN_FILTER) {
2166 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2167 bnxt_del_vlan_filter(bp, i);
2169 bnxt_del_dflt_mac_filter(bp, vnic);
2171 rc = bnxt_hwrm_vnic_free(bp, vnic);
2175 rte_free(vnic->fw_grp_ids);
2176 vnic->fw_grp_ids = NULL;
2178 vnic->rx_queue_cnt = 0;
2184 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2186 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2189 /* Destroy, recreate and reconfigure the default vnic */
2190 rc = bnxt_free_one_vnic(bp, 0);
2194 /* default vnic 0 */
2195 rc = bnxt_setup_one_vnic(bp, 0);
2199 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2200 DEV_RX_OFFLOAD_VLAN_FILTER) {
2201 rc = bnxt_add_vlan_filter(bp, 0);
2204 rc = bnxt_restore_vlan_filters(bp);
2208 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2213 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2217 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2218 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2224 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2226 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2227 struct bnxt *bp = dev->data->dev_private;
2230 rc = is_bnxt_in_error(bp);
2234 /* Filter settings will get applied when port is started */
2235 if (!dev->data->dev_started)
2238 if (mask & ETH_VLAN_FILTER_MASK) {
2239 /* Enable or disable VLAN filtering */
2240 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2245 if (mask & ETH_VLAN_STRIP_MASK) {
2246 /* Enable or disable VLAN stripping */
2247 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2252 if (mask & ETH_VLAN_EXTEND_MASK) {
2253 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2254 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2256 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2263 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2266 struct bnxt *bp = dev->data->dev_private;
2267 int qinq = dev->data->dev_conf.rxmode.offloads &
2268 DEV_RX_OFFLOAD_VLAN_EXTEND;
2270 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2271 vlan_type != ETH_VLAN_TYPE_OUTER) {
2273 "Unsupported vlan type.");
2278 "QinQ not enabled. Needs to be ON as we can "
2279 "accelerate only outer vlan\n");
2283 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2285 case RTE_ETHER_TYPE_QINQ:
2287 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2289 case RTE_ETHER_TYPE_VLAN:
2291 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2295 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2299 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2303 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2306 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2309 bp->outer_tpid_bd |= tpid;
2310 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2311 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2313 "Can accelerate only outer vlan in QinQ\n");
2321 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2322 struct rte_ether_addr *addr)
2324 struct bnxt *bp = dev->data->dev_private;
2325 /* Default Filter is tied to VNIC 0 */
2326 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2329 rc = is_bnxt_in_error(bp);
2333 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2336 if (rte_is_zero_ether_addr(addr))
2339 /* Filter settings will get applied when port is started */
2340 if (!dev->data->dev_started)
2343 /* Check if the requested MAC is already added */
2344 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2347 /* Destroy filter and re-create it */
2348 bnxt_del_dflt_mac_filter(bp, vnic);
2350 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2351 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2352 /* This filter will allow only untagged packets */
2353 rc = bnxt_add_vlan_filter(bp, 0);
2355 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2358 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2363 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2364 struct rte_ether_addr *mc_addr_set,
2365 uint32_t nb_mc_addr)
2367 struct bnxt *bp = eth_dev->data->dev_private;
2368 char *mc_addr_list = (char *)mc_addr_set;
2369 struct bnxt_vnic_info *vnic;
2370 uint32_t off = 0, i = 0;
2373 rc = is_bnxt_in_error(bp);
2377 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2379 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2380 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2384 /* TODO Check for Duplicate mcast addresses */
2385 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2386 for (i = 0; i < nb_mc_addr; i++) {
2387 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2388 RTE_ETHER_ADDR_LEN);
2389 off += RTE_ETHER_ADDR_LEN;
2392 vnic->mc_addr_cnt = i;
2393 if (vnic->mc_addr_cnt)
2394 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2396 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2399 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2403 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2405 struct bnxt *bp = dev->data->dev_private;
2406 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2407 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2408 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2409 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2412 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2413 fw_major, fw_minor, fw_updt, fw_rsvd);
2415 ret += 1; /* add the size of '\0' */
2416 if (fw_size < (uint32_t)ret)
2423 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2424 struct rte_eth_rxq_info *qinfo)
2426 struct bnxt *bp = dev->data->dev_private;
2427 struct bnxt_rx_queue *rxq;
2429 if (is_bnxt_in_error(bp))
2432 rxq = dev->data->rx_queues[queue_id];
2434 qinfo->mp = rxq->mb_pool;
2435 qinfo->scattered_rx = dev->data->scattered_rx;
2436 qinfo->nb_desc = rxq->nb_rx_desc;
2438 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2439 qinfo->conf.rx_drop_en = 0;
2440 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2444 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2445 struct rte_eth_txq_info *qinfo)
2447 struct bnxt *bp = dev->data->dev_private;
2448 struct bnxt_tx_queue *txq;
2450 if (is_bnxt_in_error(bp))
2453 txq = dev->data->tx_queues[queue_id];
2455 qinfo->nb_desc = txq->nb_tx_desc;
2457 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2458 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2459 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2461 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2462 qinfo->conf.tx_rs_thresh = 0;
2463 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2466 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2468 struct bnxt *bp = eth_dev->data->dev_private;
2469 uint32_t new_pkt_size;
2473 rc = is_bnxt_in_error(bp);
2477 /* Exit if receive queues are not configured yet */
2478 if (!eth_dev->data->nb_rx_queues)
2481 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2482 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2486 * If vector-mode tx/rx is active, disallow any MTU change that would
2487 * require scattered receive support.
2489 if (eth_dev->data->dev_started &&
2490 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2491 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2493 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2495 "MTU change would require scattered rx support. ");
2496 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2501 if (new_mtu > RTE_ETHER_MTU) {
2502 bp->flags |= BNXT_FLAG_JUMBO;
2503 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2504 DEV_RX_OFFLOAD_JUMBO_FRAME;
2506 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2507 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2508 bp->flags &= ~BNXT_FLAG_JUMBO;
2511 /* Is there a change in mtu setting? */
2512 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2515 for (i = 0; i < bp->nr_vnics; i++) {
2516 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2519 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2520 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2524 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2525 size -= RTE_PKTMBUF_HEADROOM;
2527 if (size < new_mtu) {
2528 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2535 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2537 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2543 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2545 struct bnxt *bp = dev->data->dev_private;
2546 uint16_t vlan = bp->vlan;
2549 rc = is_bnxt_in_error(bp);
2553 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2555 "PVID cannot be modified for this function\n");
2558 bp->vlan = on ? pvid : 0;
2560 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2567 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2569 struct bnxt *bp = dev->data->dev_private;
2572 rc = is_bnxt_in_error(bp);
2576 return bnxt_hwrm_port_led_cfg(bp, true);
2580 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2582 struct bnxt *bp = dev->data->dev_private;
2585 rc = is_bnxt_in_error(bp);
2589 return bnxt_hwrm_port_led_cfg(bp, false);
2593 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2595 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2596 uint32_t desc = 0, raw_cons = 0, cons;
2597 struct bnxt_cp_ring_info *cpr;
2598 struct bnxt_rx_queue *rxq;
2599 struct rx_pkt_cmpl *rxcmp;
2602 rc = is_bnxt_in_error(bp);
2606 rxq = dev->data->rx_queues[rx_queue_id];
2608 raw_cons = cpr->cp_raw_cons;
2611 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2612 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2613 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2615 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2627 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2629 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2630 struct bnxt_rx_ring_info *rxr;
2631 struct bnxt_cp_ring_info *cpr;
2632 struct bnxt_sw_rx_bd *rx_buf;
2633 struct rx_pkt_cmpl *rxcmp;
2634 uint32_t cons, cp_cons;
2640 rc = is_bnxt_in_error(rxq->bp);
2647 if (offset >= rxq->nb_rx_desc)
2650 cons = RING_CMP(cpr->cp_ring_struct, offset);
2651 cp_cons = cpr->cp_raw_cons;
2652 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2654 if (cons > cp_cons) {
2655 if (CMPL_VALID(rxcmp, cpr->valid))
2656 return RTE_ETH_RX_DESC_DONE;
2658 if (CMPL_VALID(rxcmp, !cpr->valid))
2659 return RTE_ETH_RX_DESC_DONE;
2661 rx_buf = &rxr->rx_buf_ring[cons];
2662 if (rx_buf->mbuf == NULL)
2663 return RTE_ETH_RX_DESC_UNAVAIL;
2666 return RTE_ETH_RX_DESC_AVAIL;
2670 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2672 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2673 struct bnxt_tx_ring_info *txr;
2674 struct bnxt_cp_ring_info *cpr;
2675 struct bnxt_sw_tx_bd *tx_buf;
2676 struct tx_pkt_cmpl *txcmp;
2677 uint32_t cons, cp_cons;
2683 rc = is_bnxt_in_error(txq->bp);
2690 if (offset >= txq->nb_tx_desc)
2693 cons = RING_CMP(cpr->cp_ring_struct, offset);
2694 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2695 cp_cons = cpr->cp_raw_cons;
2697 if (cons > cp_cons) {
2698 if (CMPL_VALID(txcmp, cpr->valid))
2699 return RTE_ETH_TX_DESC_UNAVAIL;
2701 if (CMPL_VALID(txcmp, !cpr->valid))
2702 return RTE_ETH_TX_DESC_UNAVAIL;
2704 tx_buf = &txr->tx_buf_ring[cons];
2705 if (tx_buf->mbuf == NULL)
2706 return RTE_ETH_TX_DESC_DONE;
2708 return RTE_ETH_TX_DESC_FULL;
2711 static struct bnxt_filter_info *
2712 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2713 struct rte_eth_ethertype_filter *efilter,
2714 struct bnxt_vnic_info *vnic0,
2715 struct bnxt_vnic_info *vnic,
2718 struct bnxt_filter_info *mfilter = NULL;
2722 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2723 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2724 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2725 " ethertype filter.", efilter->ether_type);
2729 if (efilter->queue >= bp->rx_nr_rings) {
2730 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2735 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2736 vnic = &bp->vnic_info[efilter->queue];
2738 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2743 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2744 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2745 if ((!memcmp(efilter->mac_addr.addr_bytes,
2746 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2748 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2749 mfilter->ethertype == efilter->ether_type)) {
2755 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2756 if ((!memcmp(efilter->mac_addr.addr_bytes,
2757 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2758 mfilter->ethertype == efilter->ether_type &&
2760 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2774 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2775 enum rte_filter_op filter_op,
2778 struct bnxt *bp = dev->data->dev_private;
2779 struct rte_eth_ethertype_filter *efilter =
2780 (struct rte_eth_ethertype_filter *)arg;
2781 struct bnxt_filter_info *bfilter, *filter1;
2782 struct bnxt_vnic_info *vnic, *vnic0;
2785 if (filter_op == RTE_ETH_FILTER_NOP)
2789 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2794 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2795 vnic = &bp->vnic_info[efilter->queue];
2797 switch (filter_op) {
2798 case RTE_ETH_FILTER_ADD:
2799 bnxt_match_and_validate_ether_filter(bp, efilter,
2804 bfilter = bnxt_get_unused_filter(bp);
2805 if (bfilter == NULL) {
2807 "Not enough resources for a new filter.\n");
2810 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2811 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2812 RTE_ETHER_ADDR_LEN);
2813 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2814 RTE_ETHER_ADDR_LEN);
2815 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2816 bfilter->ethertype = efilter->ether_type;
2817 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2819 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2820 if (filter1 == NULL) {
2825 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2826 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2828 bfilter->dst_id = vnic->fw_vnic_id;
2830 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2832 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2835 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2838 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2840 case RTE_ETH_FILTER_DELETE:
2841 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2843 if (ret == -EEXIST) {
2844 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2846 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2848 bnxt_free_filter(bp, filter1);
2849 } else if (ret == 0) {
2850 PMD_DRV_LOG(ERR, "No matching filter found\n");
2854 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2860 bnxt_free_filter(bp, bfilter);
2866 parse_ntuple_filter(struct bnxt *bp,
2867 struct rte_eth_ntuple_filter *nfilter,
2868 struct bnxt_filter_info *bfilter)
2872 if (nfilter->queue >= bp->rx_nr_rings) {
2873 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2877 switch (nfilter->dst_port_mask) {
2879 bfilter->dst_port_mask = -1;
2880 bfilter->dst_port = nfilter->dst_port;
2881 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2882 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2885 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2889 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2890 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2892 switch (nfilter->proto_mask) {
2894 if (nfilter->proto == 17) /* IPPROTO_UDP */
2895 bfilter->ip_protocol = 17;
2896 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2897 bfilter->ip_protocol = 6;
2900 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2903 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2907 switch (nfilter->dst_ip_mask) {
2909 bfilter->dst_ipaddr_mask[0] = -1;
2910 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2911 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2912 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2915 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2919 switch (nfilter->src_ip_mask) {
2921 bfilter->src_ipaddr_mask[0] = -1;
2922 bfilter->src_ipaddr[0] = nfilter->src_ip;
2923 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2924 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2927 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2931 switch (nfilter->src_port_mask) {
2933 bfilter->src_port_mask = -1;
2934 bfilter->src_port = nfilter->src_port;
2935 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2936 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2939 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2943 bfilter->enables = en;
2947 static struct bnxt_filter_info*
2948 bnxt_match_ntuple_filter(struct bnxt *bp,
2949 struct bnxt_filter_info *bfilter,
2950 struct bnxt_vnic_info **mvnic)
2952 struct bnxt_filter_info *mfilter = NULL;
2955 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2956 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2957 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2958 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2959 bfilter->src_ipaddr_mask[0] ==
2960 mfilter->src_ipaddr_mask[0] &&
2961 bfilter->src_port == mfilter->src_port &&
2962 bfilter->src_port_mask == mfilter->src_port_mask &&
2963 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2964 bfilter->dst_ipaddr_mask[0] ==
2965 mfilter->dst_ipaddr_mask[0] &&
2966 bfilter->dst_port == mfilter->dst_port &&
2967 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2968 bfilter->flags == mfilter->flags &&
2969 bfilter->enables == mfilter->enables) {
2980 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2981 struct rte_eth_ntuple_filter *nfilter,
2982 enum rte_filter_op filter_op)
2984 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2985 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2988 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2989 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2993 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2994 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2998 bfilter = bnxt_get_unused_filter(bp);
2999 if (bfilter == NULL) {
3001 "Not enough resources for a new filter.\n");
3004 ret = parse_ntuple_filter(bp, nfilter, bfilter);
3008 vnic = &bp->vnic_info[nfilter->queue];
3009 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3010 filter1 = STAILQ_FIRST(&vnic0->filter);
3011 if (filter1 == NULL) {
3016 bfilter->dst_id = vnic->fw_vnic_id;
3017 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3019 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3020 bfilter->ethertype = 0x800;
3021 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3023 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3025 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3026 bfilter->dst_id == mfilter->dst_id) {
3027 PMD_DRV_LOG(ERR, "filter exists.\n");
3030 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3031 bfilter->dst_id != mfilter->dst_id) {
3032 mfilter->dst_id = vnic->fw_vnic_id;
3033 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3034 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3035 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3036 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3037 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3040 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3041 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3046 if (filter_op == RTE_ETH_FILTER_ADD) {
3047 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3048 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3051 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3053 if (mfilter == NULL) {
3054 /* This should not happen. But for Coverity! */
3058 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3060 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3061 bnxt_free_filter(bp, mfilter);
3062 bnxt_free_filter(bp, bfilter);
3067 bnxt_free_filter(bp, bfilter);
3072 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3073 enum rte_filter_op filter_op,
3076 struct bnxt *bp = dev->data->dev_private;
3079 if (filter_op == RTE_ETH_FILTER_NOP)
3083 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3088 switch (filter_op) {
3089 case RTE_ETH_FILTER_ADD:
3090 ret = bnxt_cfg_ntuple_filter(bp,
3091 (struct rte_eth_ntuple_filter *)arg,
3094 case RTE_ETH_FILTER_DELETE:
3095 ret = bnxt_cfg_ntuple_filter(bp,
3096 (struct rte_eth_ntuple_filter *)arg,
3100 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3108 bnxt_parse_fdir_filter(struct bnxt *bp,
3109 struct rte_eth_fdir_filter *fdir,
3110 struct bnxt_filter_info *filter)
3112 enum rte_fdir_mode fdir_mode =
3113 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3114 struct bnxt_vnic_info *vnic0, *vnic;
3115 struct bnxt_filter_info *filter1;
3119 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3122 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3123 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3125 switch (fdir->input.flow_type) {
3126 case RTE_ETH_FLOW_IPV4:
3127 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3129 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3130 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3131 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3132 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3133 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3134 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3135 filter->ip_addr_type =
3136 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3137 filter->src_ipaddr_mask[0] = 0xffffffff;
3138 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3139 filter->dst_ipaddr_mask[0] = 0xffffffff;
3140 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3141 filter->ethertype = 0x800;
3142 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3144 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3145 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3146 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3147 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3148 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3149 filter->dst_port_mask = 0xffff;
3150 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3151 filter->src_port_mask = 0xffff;
3152 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3153 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3154 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3155 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3156 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3157 filter->ip_protocol = 6;
3158 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3159 filter->ip_addr_type =
3160 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3161 filter->src_ipaddr_mask[0] = 0xffffffff;
3162 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3163 filter->dst_ipaddr_mask[0] = 0xffffffff;
3164 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3165 filter->ethertype = 0x800;
3166 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3168 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3169 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3170 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3171 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3172 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3173 filter->dst_port_mask = 0xffff;
3174 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3175 filter->src_port_mask = 0xffff;
3176 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3177 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3178 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3179 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3180 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3181 filter->ip_protocol = 17;
3182 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3183 filter->ip_addr_type =
3184 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3185 filter->src_ipaddr_mask[0] = 0xffffffff;
3186 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3187 filter->dst_ipaddr_mask[0] = 0xffffffff;
3188 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3189 filter->ethertype = 0x800;
3190 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3192 case RTE_ETH_FLOW_IPV6:
3193 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3195 filter->ip_addr_type =
3196 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3197 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3198 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3199 rte_memcpy(filter->src_ipaddr,
3200 fdir->input.flow.ipv6_flow.src_ip, 16);
3201 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3202 rte_memcpy(filter->dst_ipaddr,
3203 fdir->input.flow.ipv6_flow.dst_ip, 16);
3204 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3205 memset(filter->dst_ipaddr_mask, 0xff, 16);
3206 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3207 memset(filter->src_ipaddr_mask, 0xff, 16);
3208 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3209 filter->ethertype = 0x86dd;
3210 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3212 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3213 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3214 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3215 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3216 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3217 filter->dst_port_mask = 0xffff;
3218 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3219 filter->src_port_mask = 0xffff;
3220 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3221 filter->ip_addr_type =
3222 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3223 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3224 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3225 rte_memcpy(filter->src_ipaddr,
3226 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3227 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3228 rte_memcpy(filter->dst_ipaddr,
3229 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3230 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3231 memset(filter->dst_ipaddr_mask, 0xff, 16);
3232 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3233 memset(filter->src_ipaddr_mask, 0xff, 16);
3234 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3235 filter->ethertype = 0x86dd;
3236 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3238 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3239 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3240 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3241 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3242 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3243 filter->dst_port_mask = 0xffff;
3244 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3245 filter->src_port_mask = 0xffff;
3246 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3247 filter->ip_addr_type =
3248 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3249 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3250 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3251 rte_memcpy(filter->src_ipaddr,
3252 fdir->input.flow.udp6_flow.ip.src_ip, 16);
3253 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3254 rte_memcpy(filter->dst_ipaddr,
3255 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3256 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3257 memset(filter->dst_ipaddr_mask, 0xff, 16);
3258 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3259 memset(filter->src_ipaddr_mask, 0xff, 16);
3260 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3261 filter->ethertype = 0x86dd;
3262 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3264 case RTE_ETH_FLOW_L2_PAYLOAD:
3265 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3266 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3268 case RTE_ETH_FLOW_VXLAN:
3269 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3271 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3272 filter->tunnel_type =
3273 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3274 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3276 case RTE_ETH_FLOW_NVGRE:
3277 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3279 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3280 filter->tunnel_type =
3281 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3282 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3284 case RTE_ETH_FLOW_UNKNOWN:
3285 case RTE_ETH_FLOW_RAW:
3286 case RTE_ETH_FLOW_FRAG_IPV4:
3287 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3288 case RTE_ETH_FLOW_FRAG_IPV6:
3289 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3290 case RTE_ETH_FLOW_IPV6_EX:
3291 case RTE_ETH_FLOW_IPV6_TCP_EX:
3292 case RTE_ETH_FLOW_IPV6_UDP_EX:
3293 case RTE_ETH_FLOW_GENEVE:
3299 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3300 vnic = &bp->vnic_info[fdir->action.rx_queue];
3302 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3306 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3307 rte_memcpy(filter->dst_macaddr,
3308 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3309 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3312 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3313 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3314 filter1 = STAILQ_FIRST(&vnic0->filter);
3315 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3317 filter->dst_id = vnic->fw_vnic_id;
3318 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3319 if (filter->dst_macaddr[i] == 0x00)
3320 filter1 = STAILQ_FIRST(&vnic0->filter);
3322 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3325 if (filter1 == NULL)
3328 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3329 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3331 filter->enables = en;
3336 static struct bnxt_filter_info *
3337 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3338 struct bnxt_vnic_info **mvnic)
3340 struct bnxt_filter_info *mf = NULL;
3343 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3344 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3346 STAILQ_FOREACH(mf, &vnic->filter, next) {
3347 if (mf->filter_type == nf->filter_type &&
3348 mf->flags == nf->flags &&
3349 mf->src_port == nf->src_port &&
3350 mf->src_port_mask == nf->src_port_mask &&
3351 mf->dst_port == nf->dst_port &&
3352 mf->dst_port_mask == nf->dst_port_mask &&
3353 mf->ip_protocol == nf->ip_protocol &&
3354 mf->ip_addr_type == nf->ip_addr_type &&
3355 mf->ethertype == nf->ethertype &&
3356 mf->vni == nf->vni &&
3357 mf->tunnel_type == nf->tunnel_type &&
3358 mf->l2_ovlan == nf->l2_ovlan &&
3359 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3360 mf->l2_ivlan == nf->l2_ivlan &&
3361 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3362 !memcmp(mf->l2_addr, nf->l2_addr,
3363 RTE_ETHER_ADDR_LEN) &&
3364 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3365 RTE_ETHER_ADDR_LEN) &&
3366 !memcmp(mf->src_macaddr, nf->src_macaddr,
3367 RTE_ETHER_ADDR_LEN) &&
3368 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3369 RTE_ETHER_ADDR_LEN) &&
3370 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3371 sizeof(nf->src_ipaddr)) &&
3372 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3373 sizeof(nf->src_ipaddr_mask)) &&
3374 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3375 sizeof(nf->dst_ipaddr)) &&
3376 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3377 sizeof(nf->dst_ipaddr_mask))) {
3388 bnxt_fdir_filter(struct rte_eth_dev *dev,
3389 enum rte_filter_op filter_op,
3392 struct bnxt *bp = dev->data->dev_private;
3393 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3394 struct bnxt_filter_info *filter, *match;
3395 struct bnxt_vnic_info *vnic, *mvnic;
3398 if (filter_op == RTE_ETH_FILTER_NOP)
3401 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3404 switch (filter_op) {
3405 case RTE_ETH_FILTER_ADD:
3406 case RTE_ETH_FILTER_DELETE:
3408 filter = bnxt_get_unused_filter(bp);
3409 if (filter == NULL) {
3411 "Not enough resources for a new flow.\n");
3415 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3418 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3420 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3421 vnic = &bp->vnic_info[0];
3423 vnic = &bp->vnic_info[fdir->action.rx_queue];
3425 match = bnxt_match_fdir(bp, filter, &mvnic);
3426 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3427 if (match->dst_id == vnic->fw_vnic_id) {
3428 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3432 match->dst_id = vnic->fw_vnic_id;
3433 ret = bnxt_hwrm_set_ntuple_filter(bp,
3436 STAILQ_REMOVE(&mvnic->filter, match,
3437 bnxt_filter_info, next);
3438 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3440 "Filter with matching pattern exist\n");
3442 "Updated it to new destination q\n");
3446 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3447 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3452 if (filter_op == RTE_ETH_FILTER_ADD) {
3453 ret = bnxt_hwrm_set_ntuple_filter(bp,
3458 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3460 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3461 STAILQ_REMOVE(&vnic->filter, match,
3462 bnxt_filter_info, next);
3463 bnxt_free_filter(bp, match);
3464 bnxt_free_filter(bp, filter);
3467 case RTE_ETH_FILTER_FLUSH:
3468 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3469 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3471 STAILQ_FOREACH(filter, &vnic->filter, next) {
3472 if (filter->filter_type ==
3473 HWRM_CFA_NTUPLE_FILTER) {
3475 bnxt_hwrm_clear_ntuple_filter(bp,
3477 STAILQ_REMOVE(&vnic->filter, filter,
3478 bnxt_filter_info, next);
3483 case RTE_ETH_FILTER_UPDATE:
3484 case RTE_ETH_FILTER_STATS:
3485 case RTE_ETH_FILTER_INFO:
3486 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3489 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3496 bnxt_free_filter(bp, filter);
3501 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3502 enum rte_filter_type filter_type,
3503 enum rte_filter_op filter_op, void *arg)
3505 struct bnxt *bp = dev->data->dev_private;
3508 ret = is_bnxt_in_error(dev->data->dev_private);
3512 switch (filter_type) {
3513 case RTE_ETH_FILTER_TUNNEL:
3515 "filter type: %d: To be implemented\n", filter_type);
3517 case RTE_ETH_FILTER_FDIR:
3518 ret = bnxt_fdir_filter(dev, filter_op, arg);
3520 case RTE_ETH_FILTER_NTUPLE:
3521 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3523 case RTE_ETH_FILTER_ETHERTYPE:
3524 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3526 case RTE_ETH_FILTER_GENERIC:
3527 if (filter_op != RTE_ETH_FILTER_GET)
3530 *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3532 *(const void **)arg = &bnxt_flow_ops;
3536 "Filter type (%d) not supported", filter_type);
3543 static const uint32_t *
3544 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3546 static const uint32_t ptypes[] = {
3547 RTE_PTYPE_L2_ETHER_VLAN,
3548 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3549 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3553 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3554 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3555 RTE_PTYPE_INNER_L4_ICMP,
3556 RTE_PTYPE_INNER_L4_TCP,
3557 RTE_PTYPE_INNER_L4_UDP,
3561 if (!dev->rx_pkt_burst)
3567 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3570 uint32_t reg_base = *reg_arr & 0xfffff000;
3574 for (i = 0; i < count; i++) {
3575 if ((reg_arr[i] & 0xfffff000) != reg_base)
3578 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3579 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3583 static int bnxt_map_ptp_regs(struct bnxt *bp)
3585 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3589 reg_arr = ptp->rx_regs;
3590 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3594 reg_arr = ptp->tx_regs;
3595 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3599 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3600 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3602 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3603 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3608 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3610 rte_write32(0, (uint8_t *)bp->bar0 +
3611 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3612 rte_write32(0, (uint8_t *)bp->bar0 +
3613 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3616 static uint64_t bnxt_cc_read(struct bnxt *bp)
3620 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3621 BNXT_GRCPF_REG_SYNC_TIME));
3622 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3623 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3627 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3629 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3632 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3633 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3634 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3637 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3638 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3639 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3640 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3641 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3642 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3647 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3649 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3650 struct bnxt_pf_info *pf = &bp->pf;
3657 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3658 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3659 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3662 port_id = pf->port_id;
3663 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3664 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3666 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3667 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3668 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3669 /* bnxt_clr_rx_ts(bp); TBD */
3673 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3674 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3675 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3676 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3682 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3685 struct bnxt *bp = dev->data->dev_private;
3686 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3691 ns = rte_timespec_to_ns(ts);
3692 /* Set the timecounters to a new value. */
3699 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3701 struct bnxt *bp = dev->data->dev_private;
3702 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3703 uint64_t ns, systime_cycles = 0;
3709 if (BNXT_CHIP_THOR(bp))
3710 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3713 systime_cycles = bnxt_cc_read(bp);
3715 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3716 *ts = rte_ns_to_timespec(ns);
3721 bnxt_timesync_enable(struct rte_eth_dev *dev)
3723 struct bnxt *bp = dev->data->dev_private;
3724 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3732 ptp->tx_tstamp_en = 1;
3733 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3735 rc = bnxt_hwrm_ptp_cfg(bp);
3739 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3740 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3741 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3743 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3744 ptp->tc.cc_shift = shift;
3745 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3747 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3748 ptp->rx_tstamp_tc.cc_shift = shift;
3749 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3751 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3752 ptp->tx_tstamp_tc.cc_shift = shift;
3753 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3755 if (!BNXT_CHIP_THOR(bp))
3756 bnxt_map_ptp_regs(bp);
3762 bnxt_timesync_disable(struct rte_eth_dev *dev)
3764 struct bnxt *bp = dev->data->dev_private;
3765 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3771 ptp->tx_tstamp_en = 0;
3774 bnxt_hwrm_ptp_cfg(bp);
3776 if (!BNXT_CHIP_THOR(bp))
3777 bnxt_unmap_ptp_regs(bp);
3783 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3784 struct timespec *timestamp,
3785 uint32_t flags __rte_unused)
3787 struct bnxt *bp = dev->data->dev_private;
3788 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3789 uint64_t rx_tstamp_cycles = 0;
3795 if (BNXT_CHIP_THOR(bp))
3796 rx_tstamp_cycles = ptp->rx_timestamp;
3798 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3800 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3801 *timestamp = rte_ns_to_timespec(ns);
3806 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3807 struct timespec *timestamp)
3809 struct bnxt *bp = dev->data->dev_private;
3810 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3811 uint64_t tx_tstamp_cycles = 0;
3818 if (BNXT_CHIP_THOR(bp))
3819 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3822 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3824 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3825 *timestamp = rte_ns_to_timespec(ns);
3831 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3833 struct bnxt *bp = dev->data->dev_private;
3834 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3839 ptp->tc.nsec += delta;
3845 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3847 struct bnxt *bp = dev->data->dev_private;
3849 uint32_t dir_entries;
3850 uint32_t entry_length;
3852 rc = is_bnxt_in_error(bp);
3856 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3857 bp->pdev->addr.domain, bp->pdev->addr.bus,
3858 bp->pdev->addr.devid, bp->pdev->addr.function);
3860 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3864 return dir_entries * entry_length;
3868 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3869 struct rte_dev_eeprom_info *in_eeprom)
3871 struct bnxt *bp = dev->data->dev_private;
3876 rc = is_bnxt_in_error(bp);
3880 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3881 bp->pdev->addr.domain, bp->pdev->addr.bus,
3882 bp->pdev->addr.devid, bp->pdev->addr.function,
3883 in_eeprom->offset, in_eeprom->length);
3885 if (in_eeprom->offset == 0) /* special offset value to get directory */
3886 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3889 index = in_eeprom->offset >> 24;
3890 offset = in_eeprom->offset & 0xffffff;
3893 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3894 in_eeprom->length, in_eeprom->data);
3899 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3902 case BNX_DIR_TYPE_CHIMP_PATCH:
3903 case BNX_DIR_TYPE_BOOTCODE:
3904 case BNX_DIR_TYPE_BOOTCODE_2:
3905 case BNX_DIR_TYPE_APE_FW:
3906 case BNX_DIR_TYPE_APE_PATCH:
3907 case BNX_DIR_TYPE_KONG_FW:
3908 case BNX_DIR_TYPE_KONG_PATCH:
3909 case BNX_DIR_TYPE_BONO_FW:
3910 case BNX_DIR_TYPE_BONO_PATCH:
3918 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3921 case BNX_DIR_TYPE_AVS:
3922 case BNX_DIR_TYPE_EXP_ROM_MBA:
3923 case BNX_DIR_TYPE_PCIE:
3924 case BNX_DIR_TYPE_TSCF_UCODE:
3925 case BNX_DIR_TYPE_EXT_PHY:
3926 case BNX_DIR_TYPE_CCM:
3927 case BNX_DIR_TYPE_ISCSI_BOOT:
3928 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3929 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3937 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3939 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3940 bnxt_dir_type_is_other_exec_format(dir_type);
3944 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3945 struct rte_dev_eeprom_info *in_eeprom)
3947 struct bnxt *bp = dev->data->dev_private;
3948 uint8_t index, dir_op;
3949 uint16_t type, ext, ordinal, attr;
3952 rc = is_bnxt_in_error(bp);
3956 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3957 bp->pdev->addr.domain, bp->pdev->addr.bus,
3958 bp->pdev->addr.devid, bp->pdev->addr.function,
3959 in_eeprom->offset, in_eeprom->length);
3962 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3966 type = in_eeprom->magic >> 16;
3968 if (type == 0xffff) { /* special value for directory operations */
3969 index = in_eeprom->magic & 0xff;
3970 dir_op = in_eeprom->magic >> 8;
3974 case 0x0e: /* erase */
3975 if (in_eeprom->offset != ~in_eeprom->magic)
3977 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3983 /* Create or re-write an NVM item: */
3984 if (bnxt_dir_type_is_executable(type) == true)
3986 ext = in_eeprom->magic & 0xffff;
3987 ordinal = in_eeprom->offset >> 16;
3988 attr = in_eeprom->offset & 0xffff;
3990 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3991 in_eeprom->data, in_eeprom->length);
3998 static const struct eth_dev_ops bnxt_dev_ops = {
3999 .dev_infos_get = bnxt_dev_info_get_op,
4000 .dev_close = bnxt_dev_close_op,
4001 .dev_configure = bnxt_dev_configure_op,
4002 .dev_start = bnxt_dev_start_op,
4003 .dev_stop = bnxt_dev_stop_op,
4004 .dev_set_link_up = bnxt_dev_set_link_up_op,
4005 .dev_set_link_down = bnxt_dev_set_link_down_op,
4006 .stats_get = bnxt_stats_get_op,
4007 .stats_reset = bnxt_stats_reset_op,
4008 .rx_queue_setup = bnxt_rx_queue_setup_op,
4009 .rx_queue_release = bnxt_rx_queue_release_op,
4010 .tx_queue_setup = bnxt_tx_queue_setup_op,
4011 .tx_queue_release = bnxt_tx_queue_release_op,
4012 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4013 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4014 .reta_update = bnxt_reta_update_op,
4015 .reta_query = bnxt_reta_query_op,
4016 .rss_hash_update = bnxt_rss_hash_update_op,
4017 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4018 .link_update = bnxt_link_update_op,
4019 .promiscuous_enable = bnxt_promiscuous_enable_op,
4020 .promiscuous_disable = bnxt_promiscuous_disable_op,
4021 .allmulticast_enable = bnxt_allmulticast_enable_op,
4022 .allmulticast_disable = bnxt_allmulticast_disable_op,
4023 .mac_addr_add = bnxt_mac_addr_add_op,
4024 .mac_addr_remove = bnxt_mac_addr_remove_op,
4025 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4026 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4027 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
4028 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
4029 .vlan_filter_set = bnxt_vlan_filter_set_op,
4030 .vlan_offload_set = bnxt_vlan_offload_set_op,
4031 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4032 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4033 .mtu_set = bnxt_mtu_set_op,
4034 .mac_addr_set = bnxt_set_default_mac_addr_op,
4035 .xstats_get = bnxt_dev_xstats_get_op,
4036 .xstats_get_names = bnxt_dev_xstats_get_names_op,
4037 .xstats_reset = bnxt_dev_xstats_reset_op,
4038 .fw_version_get = bnxt_fw_version_get,
4039 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4040 .rxq_info_get = bnxt_rxq_info_get_op,
4041 .txq_info_get = bnxt_txq_info_get_op,
4042 .dev_led_on = bnxt_dev_led_on_op,
4043 .dev_led_off = bnxt_dev_led_off_op,
4044 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4045 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4046 .rx_queue_count = bnxt_rx_queue_count_op,
4047 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
4048 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
4049 .rx_queue_start = bnxt_rx_queue_start,
4050 .rx_queue_stop = bnxt_rx_queue_stop,
4051 .tx_queue_start = bnxt_tx_queue_start,
4052 .tx_queue_stop = bnxt_tx_queue_stop,
4053 .filter_ctrl = bnxt_filter_ctrl_op,
4054 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4055 .get_eeprom_length = bnxt_get_eeprom_length_op,
4056 .get_eeprom = bnxt_get_eeprom_op,
4057 .set_eeprom = bnxt_set_eeprom_op,
4058 .timesync_enable = bnxt_timesync_enable,
4059 .timesync_disable = bnxt_timesync_disable,
4060 .timesync_read_time = bnxt_timesync_read_time,
4061 .timesync_write_time = bnxt_timesync_write_time,
4062 .timesync_adjust_time = bnxt_timesync_adjust_time,
4063 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4064 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4067 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4071 /* Only pre-map the reset GRC registers using window 3 */
4072 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4073 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4075 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4080 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4082 struct bnxt_error_recovery_info *info = bp->recovery_info;
4083 uint32_t reg_base = 0xffffffff;
4086 /* Only pre-map the monitoring GRC registers using window 2 */
4087 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4088 uint32_t reg = info->status_regs[i];
4090 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4093 if (reg_base == 0xffffffff)
4094 reg_base = reg & 0xfffff000;
4095 if ((reg & 0xfffff000) != reg_base)
4098 /* Use mask 0xffc as the Lower 2 bits indicates
4099 * address space location
4101 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4105 if (reg_base == 0xffffffff)
4108 rte_write32(reg_base, (uint8_t *)bp->bar0 +
4109 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4114 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4116 struct bnxt_error_recovery_info *info = bp->recovery_info;
4117 uint32_t delay = info->delay_after_reset[index];
4118 uint32_t val = info->reset_reg_val[index];
4119 uint32_t reg = info->reset_reg[index];
4120 uint32_t type, offset;
4122 type = BNXT_FW_STATUS_REG_TYPE(reg);
4123 offset = BNXT_FW_STATUS_REG_OFF(reg);
4126 case BNXT_FW_STATUS_REG_TYPE_CFG:
4127 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4129 case BNXT_FW_STATUS_REG_TYPE_GRC:
4130 offset = bnxt_map_reset_regs(bp, offset);
4131 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4133 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4134 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4137 /* wait on a specific interval of time until core reset is complete */
4139 rte_delay_ms(delay);
4142 static void bnxt_dev_cleanup(struct bnxt *bp)
4144 bnxt_set_hwrm_link_config(bp, false);
4145 bp->link_info.link_up = 0;
4146 if (bp->eth_dev->data->dev_started)
4147 bnxt_dev_stop_op(bp->eth_dev);
4149 bnxt_uninit_resources(bp, true);
4152 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4154 struct rte_eth_dev *dev = bp->eth_dev;
4155 struct rte_vlan_filter_conf *vfc;
4159 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4160 vfc = &dev->data->vlan_filter_conf;
4161 vidx = vlan_id / 64;
4162 vbit = vlan_id % 64;
4164 /* Each bit corresponds to a VLAN id */
4165 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4166 rc = bnxt_add_vlan_filter(bp, vlan_id);
4175 static int bnxt_restore_mac_filters(struct bnxt *bp)
4177 struct rte_eth_dev *dev = bp->eth_dev;
4178 struct rte_eth_dev_info dev_info;
4179 struct rte_ether_addr *addr;
4185 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
4188 rc = bnxt_dev_info_get_op(dev, &dev_info);
4192 /* replay MAC address configuration */
4193 for (i = 1; i < dev_info.max_mac_addrs; i++) {
4194 addr = &dev->data->mac_addrs[i];
4196 /* skip zero address */
4197 if (rte_is_zero_ether_addr(addr))
4201 pool_mask = dev->data->mac_pool_sel[i];
4204 if (pool_mask & 1ULL) {
4205 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4211 } while (pool_mask);
4217 static int bnxt_restore_filters(struct bnxt *bp)
4219 struct rte_eth_dev *dev = bp->eth_dev;
4222 if (dev->data->all_multicast) {
4223 ret = bnxt_allmulticast_enable_op(dev);
4227 if (dev->data->promiscuous) {
4228 ret = bnxt_promiscuous_enable_op(dev);
4233 ret = bnxt_restore_mac_filters(bp);
4237 ret = bnxt_restore_vlan_filters(bp);
4238 /* TODO restore other filters as well */
4242 static void bnxt_dev_recover(void *arg)
4244 struct bnxt *bp = arg;
4245 int timeout = bp->fw_reset_max_msecs;
4248 /* Clear Error flag so that device re-init should happen */
4249 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4252 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4255 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4256 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4257 } while (rc && timeout);
4260 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4264 rc = bnxt_init_resources(bp, true);
4267 "Failed to initialize resources after reset\n");
4270 /* clear reset flag as the device is initialized now */
4271 bp->flags &= ~BNXT_FLAG_FW_RESET;
4273 rc = bnxt_dev_start_op(bp->eth_dev);
4275 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4279 rc = bnxt_restore_filters(bp);
4283 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4286 bnxt_dev_stop_op(bp->eth_dev);
4288 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4289 bnxt_uninit_resources(bp, false);
4290 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4293 void bnxt_dev_reset_and_resume(void *arg)
4295 struct bnxt *bp = arg;
4298 bnxt_dev_cleanup(bp);
4300 bnxt_wait_for_device_shutdown(bp);
4302 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4303 bnxt_dev_recover, (void *)bp);
4305 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4308 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4310 struct bnxt_error_recovery_info *info = bp->recovery_info;
4311 uint32_t reg = info->status_regs[index];
4312 uint32_t type, offset, val = 0;
4314 type = BNXT_FW_STATUS_REG_TYPE(reg);
4315 offset = BNXT_FW_STATUS_REG_OFF(reg);
4318 case BNXT_FW_STATUS_REG_TYPE_CFG:
4319 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4321 case BNXT_FW_STATUS_REG_TYPE_GRC:
4322 offset = info->mapped_status_regs[index];
4324 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4325 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4333 static int bnxt_fw_reset_all(struct bnxt *bp)
4335 struct bnxt_error_recovery_info *info = bp->recovery_info;
4339 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4340 /* Reset through master function driver */
4341 for (i = 0; i < info->reg_array_cnt; i++)
4342 bnxt_write_fw_reset_reg(bp, i);
4343 /* Wait for time specified by FW after triggering reset */
4344 rte_delay_ms(info->master_func_wait_period_after_reset);
4345 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4346 /* Reset with the help of Kong processor */
4347 rc = bnxt_hwrm_fw_reset(bp);
4349 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4355 static void bnxt_fw_reset_cb(void *arg)
4357 struct bnxt *bp = arg;
4358 struct bnxt_error_recovery_info *info = bp->recovery_info;
4361 /* Only Master function can do FW reset */
4362 if (bnxt_is_master_func(bp) &&
4363 bnxt_is_recovery_enabled(bp)) {
4364 rc = bnxt_fw_reset_all(bp);
4366 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4371 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4372 * EXCEPTION_FATAL_ASYNC event to all the functions
4373 * (including MASTER FUNC). After receiving this Async, all the active
4374 * drivers should treat this case as FW initiated recovery
4376 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4377 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4378 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4380 /* To recover from error */
4381 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4386 /* Driver should poll FW heartbeat, reset_counter with the frequency
4387 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4388 * When the driver detects heartbeat stop or change in reset_counter,
4389 * it has to trigger a reset to recover from the error condition.
4390 * A “master PF” is the function who will have the privilege to
4391 * initiate the chimp reset. The master PF will be elected by the
4392 * firmware and will be notified through async message.
4394 static void bnxt_check_fw_health(void *arg)
4396 struct bnxt *bp = arg;
4397 struct bnxt_error_recovery_info *info = bp->recovery_info;
4398 uint32_t val = 0, wait_msec;
4400 if (!info || !bnxt_is_recovery_enabled(bp) ||
4401 is_bnxt_in_error(bp))
4404 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4405 if (val == info->last_heart_beat)
4408 info->last_heart_beat = val;
4410 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4411 if (val != info->last_reset_counter)
4414 info->last_reset_counter = val;
4416 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4417 bnxt_check_fw_health, (void *)bp);
4421 /* Stop DMA to/from device */
4422 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4423 bp->flags |= BNXT_FLAG_FW_RESET;
4425 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4427 if (bnxt_is_master_func(bp))
4428 wait_msec = info->master_func_wait_period;
4430 wait_msec = info->normal_func_wait_period;
4432 rte_eal_alarm_set(US_PER_MS * wait_msec,
4433 bnxt_fw_reset_cb, (void *)bp);
4436 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4438 uint32_t polling_freq;
4440 if (!bnxt_is_recovery_enabled(bp))
4443 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4446 polling_freq = bp->recovery_info->driver_polling_freq;
4448 rte_eal_alarm_set(US_PER_MS * polling_freq,
4449 bnxt_check_fw_health, (void *)bp);
4450 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4453 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4455 if (!bnxt_is_recovery_enabled(bp))
4458 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4459 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4462 static bool bnxt_vf_pciid(uint16_t device_id)
4464 switch (device_id) {
4465 case BROADCOM_DEV_ID_57304_VF:
4466 case BROADCOM_DEV_ID_57406_VF:
4467 case BROADCOM_DEV_ID_5731X_VF:
4468 case BROADCOM_DEV_ID_5741X_VF:
4469 case BROADCOM_DEV_ID_57414_VF:
4470 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4471 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4472 case BROADCOM_DEV_ID_58802_VF:
4473 case BROADCOM_DEV_ID_57500_VF1:
4474 case BROADCOM_DEV_ID_57500_VF2:
4482 static bool bnxt_thor_device(uint16_t device_id)
4484 switch (device_id) {
4485 case BROADCOM_DEV_ID_57508:
4486 case BROADCOM_DEV_ID_57504:
4487 case BROADCOM_DEV_ID_57502:
4488 case BROADCOM_DEV_ID_57508_MF1:
4489 case BROADCOM_DEV_ID_57504_MF1:
4490 case BROADCOM_DEV_ID_57502_MF1:
4491 case BROADCOM_DEV_ID_57508_MF2:
4492 case BROADCOM_DEV_ID_57504_MF2:
4493 case BROADCOM_DEV_ID_57502_MF2:
4494 case BROADCOM_DEV_ID_57500_VF1:
4495 case BROADCOM_DEV_ID_57500_VF2:
4503 bool bnxt_stratus_device(struct bnxt *bp)
4505 uint16_t device_id = bp->pdev->id.device_id;
4507 switch (device_id) {
4508 case BROADCOM_DEV_ID_STRATUS_NIC:
4509 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4510 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4518 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4520 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4521 struct bnxt *bp = eth_dev->data->dev_private;
4523 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4524 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4525 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4526 if (!bp->bar0 || !bp->doorbell_base) {
4527 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4531 bp->eth_dev = eth_dev;
4537 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4538 struct bnxt_ctx_pg_info *ctx_pg,
4543 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4544 const struct rte_memzone *mz = NULL;
4545 char mz_name[RTE_MEMZONE_NAMESIZE];
4546 rte_iova_t mz_phys_addr;
4547 uint64_t valid_bits = 0;
4554 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4556 rmem->page_size = BNXT_PAGE_SIZE;
4557 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4558 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4559 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4561 valid_bits = PTU_PTE_VALID;
4563 if (rmem->nr_pages > 1) {
4564 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4565 "bnxt_ctx_pg_tbl%s_%x_%d",
4566 suffix, idx, bp->eth_dev->data->port_id);
4567 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4568 mz = rte_memzone_lookup(mz_name);
4570 mz = rte_memzone_reserve_aligned(mz_name,
4574 RTE_MEMZONE_SIZE_HINT_ONLY |
4575 RTE_MEMZONE_IOVA_CONTIG,
4581 memset(mz->addr, 0, mz->len);
4582 mz_phys_addr = mz->iova;
4584 rmem->pg_tbl = mz->addr;
4585 rmem->pg_tbl_map = mz_phys_addr;
4586 rmem->pg_tbl_mz = mz;
4589 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4590 suffix, idx, bp->eth_dev->data->port_id);
4591 mz = rte_memzone_lookup(mz_name);
4593 mz = rte_memzone_reserve_aligned(mz_name,
4597 RTE_MEMZONE_SIZE_HINT_ONLY |
4598 RTE_MEMZONE_IOVA_CONTIG,
4604 memset(mz->addr, 0, mz->len);
4605 mz_phys_addr = mz->iova;
4607 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4608 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4609 rmem->dma_arr[i] = mz_phys_addr + sz;
4611 if (rmem->nr_pages > 1) {
4612 if (i == rmem->nr_pages - 2 &&
4613 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4614 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4615 else if (i == rmem->nr_pages - 1 &&
4616 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4617 valid_bits |= PTU_PTE_LAST;
4619 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4625 if (rmem->vmem_size)
4626 rmem->vmem = (void **)mz->addr;
4627 rmem->dma_arr[0] = mz_phys_addr;
4631 static void bnxt_free_ctx_mem(struct bnxt *bp)
4635 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4638 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4639 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4640 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4641 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4642 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4643 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4644 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4645 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4646 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4647 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4648 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4650 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4651 if (bp->ctx->tqm_mem[i])
4652 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4659 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4661 #define min_t(type, x, y) ({ \
4662 type __min1 = (x); \
4663 type __min2 = (y); \
4664 __min1 < __min2 ? __min1 : __min2; })
4666 #define max_t(type, x, y) ({ \
4667 type __max1 = (x); \
4668 type __max2 = (y); \
4669 __max1 > __max2 ? __max1 : __max2; })
4671 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4673 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4675 struct bnxt_ctx_pg_info *ctx_pg;
4676 struct bnxt_ctx_mem_info *ctx;
4677 uint32_t mem_size, ena, entries;
4678 uint32_t entries_sp, min;
4681 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4683 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4687 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4690 ctx_pg = &ctx->qp_mem;
4691 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4692 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4693 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4697 ctx_pg = &ctx->srq_mem;
4698 ctx_pg->entries = ctx->srq_max_l2_entries;
4699 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4700 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4704 ctx_pg = &ctx->cq_mem;
4705 ctx_pg->entries = ctx->cq_max_l2_entries;
4706 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4707 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4711 ctx_pg = &ctx->vnic_mem;
4712 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4713 ctx->vnic_max_ring_table_entries;
4714 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4715 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4719 ctx_pg = &ctx->stat_mem;
4720 ctx_pg->entries = ctx->stat_max_entries;
4721 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4722 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4726 min = ctx->tqm_min_entries_per_ring;
4728 entries_sp = ctx->qp_max_l2_entries +
4729 ctx->vnic_max_vnic_entries +
4730 2 * ctx->qp_min_qp1_entries + min;
4731 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4733 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4734 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4735 entries = clamp_t(uint32_t, entries, min,
4736 ctx->tqm_max_entries_per_ring);
4737 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4738 ctx_pg = ctx->tqm_mem[i];
4739 ctx_pg->entries = i ? entries : entries_sp;
4740 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4741 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4744 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4747 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4748 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4751 "Failed to configure context mem: rc = %d\n", rc);
4753 ctx->flags |= BNXT_CTX_FLAG_INITED;
4758 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4760 struct rte_pci_device *pci_dev = bp->pdev;
4761 char mz_name[RTE_MEMZONE_NAMESIZE];
4762 const struct rte_memzone *mz = NULL;
4763 uint32_t total_alloc_len;
4764 rte_iova_t mz_phys_addr;
4766 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4769 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4770 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4771 pci_dev->addr.bus, pci_dev->addr.devid,
4772 pci_dev->addr.function, "rx_port_stats");
4773 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4774 mz = rte_memzone_lookup(mz_name);
4776 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4777 sizeof(struct rx_port_stats_ext) + 512);
4779 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4782 RTE_MEMZONE_SIZE_HINT_ONLY |
4783 RTE_MEMZONE_IOVA_CONTIG);
4787 memset(mz->addr, 0, mz->len);
4788 mz_phys_addr = mz->iova;
4790 bp->rx_mem_zone = (const void *)mz;
4791 bp->hw_rx_port_stats = mz->addr;
4792 bp->hw_rx_port_stats_map = mz_phys_addr;
4794 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4795 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4796 pci_dev->addr.bus, pci_dev->addr.devid,
4797 pci_dev->addr.function, "tx_port_stats");
4798 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4799 mz = rte_memzone_lookup(mz_name);
4801 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4802 sizeof(struct tx_port_stats_ext) + 512);
4804 mz = rte_memzone_reserve(mz_name,
4808 RTE_MEMZONE_SIZE_HINT_ONLY |
4809 RTE_MEMZONE_IOVA_CONTIG);
4813 memset(mz->addr, 0, mz->len);
4814 mz_phys_addr = mz->iova;
4816 bp->tx_mem_zone = (const void *)mz;
4817 bp->hw_tx_port_stats = mz->addr;
4818 bp->hw_tx_port_stats_map = mz_phys_addr;
4819 bp->flags |= BNXT_FLAG_PORT_STATS;
4821 /* Display extended statistics if FW supports it */
4822 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4823 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4824 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4827 bp->hw_rx_port_stats_ext = (void *)
4828 ((uint8_t *)bp->hw_rx_port_stats +
4829 sizeof(struct rx_port_stats));
4830 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4831 sizeof(struct rx_port_stats);
4832 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4834 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4835 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4836 bp->hw_tx_port_stats_ext = (void *)
4837 ((uint8_t *)bp->hw_tx_port_stats +
4838 sizeof(struct tx_port_stats));
4839 bp->hw_tx_port_stats_ext_map =
4840 bp->hw_tx_port_stats_map +
4841 sizeof(struct tx_port_stats);
4842 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4848 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4850 struct bnxt *bp = eth_dev->data->dev_private;
4853 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4854 RTE_ETHER_ADDR_LEN *
4857 if (eth_dev->data->mac_addrs == NULL) {
4858 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4862 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4866 /* Generate a random MAC address, if none was assigned by PF */
4867 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4868 bnxt_eth_hw_addr_random(bp->mac_addr);
4870 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4871 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4872 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4874 rc = bnxt_hwrm_set_mac(bp);
4876 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4877 RTE_ETHER_ADDR_LEN);
4881 /* Copy the permanent MAC from the FUNC_QCAPS response */
4882 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4883 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4888 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4892 /* MAC is already configured in FW */
4893 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4896 /* Restore the old MAC configured */
4897 rc = bnxt_hwrm_set_mac(bp);
4899 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4904 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4909 #define ALLOW_FUNC(x) \
4911 uint32_t arg = (x); \
4912 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4913 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4916 /* Forward all requests if firmware is new enough */
4917 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4918 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4919 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4920 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4922 PMD_DRV_LOG(WARNING,
4923 "Firmware too old for VF mailbox functionality\n");
4924 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4928 * The following are used for driver cleanup. If we disallow these,
4929 * VF drivers can't clean up cleanly.
4931 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4932 ALLOW_FUNC(HWRM_VNIC_FREE);
4933 ALLOW_FUNC(HWRM_RING_FREE);
4934 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4935 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4936 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4937 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4938 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4939 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4943 bnxt_get_svif(uint16_t port_id, bool func_svif)
4945 struct rte_eth_dev *eth_dev;
4948 eth_dev = &rte_eth_devices[port_id];
4949 bp = eth_dev->data->dev_private;
4951 return func_svif ? bp->func_svif : bp->port_svif;
4955 bnxt_get_vnic_id(uint16_t port)
4957 struct rte_eth_dev *eth_dev;
4958 struct bnxt_vnic_info *vnic;
4961 eth_dev = &rte_eth_devices[port];
4962 bp = eth_dev->data->dev_private;
4964 vnic = BNXT_GET_DEFAULT_VNIC(bp);
4966 return vnic->fw_vnic_id;
4970 bnxt_get_fw_func_id(uint16_t port)
4972 struct rte_eth_dev *eth_dev;
4975 eth_dev = &rte_eth_devices[port];
4976 bp = eth_dev->data->dev_private;
4981 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4983 struct bnxt_error_recovery_info *info = bp->recovery_info;
4986 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4987 memset(info, 0, sizeof(*info));
4991 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4994 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4997 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4999 bp->recovery_info = info;
5002 static void bnxt_check_fw_status(struct bnxt *bp)
5006 if (!(bp->recovery_info &&
5007 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5010 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5011 if (fw_status != BNXT_FW_STATUS_HEALTHY)
5012 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5016 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5018 struct bnxt_error_recovery_info *info = bp->recovery_info;
5019 uint32_t status_loc;
5022 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5023 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5024 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5025 BNXT_GRCP_WINDOW_2_BASE +
5026 offsetof(struct hcomm_status,
5028 /* If the signature is absent, then FW does not support this feature */
5029 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5030 HCOMM_STATUS_SIGNATURE_VAL)
5034 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5038 bp->recovery_info = info;
5040 memset(info, 0, sizeof(*info));
5043 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5044 BNXT_GRCP_WINDOW_2_BASE +
5045 offsetof(struct hcomm_status,
5048 /* Only pre-map the FW health status GRC register */
5049 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5052 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5053 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5054 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5056 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5057 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5059 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5064 static int bnxt_init_fw(struct bnxt *bp)
5071 rc = bnxt_map_hcomm_fw_status_reg(bp);
5075 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5077 bnxt_check_fw_status(bp);
5081 rc = bnxt_hwrm_func_reset(bp);
5085 rc = bnxt_hwrm_vnic_qcaps(bp);
5089 rc = bnxt_hwrm_queue_qportcfg(bp);
5093 /* Get the MAX capabilities for this function.
5094 * This function also allocates context memory for TQM rings and
5095 * informs the firmware about this allocated backing store memory.
5097 rc = bnxt_hwrm_func_qcaps(bp);
5101 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5105 bnxt_hwrm_port_mac_qcfg(bp);
5107 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5111 bnxt_alloc_error_recovery_info(bp);
5112 /* Get the adapter error recovery support info */
5113 rc = bnxt_hwrm_error_recovery_qcfg(bp);
5115 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5117 bnxt_hwrm_port_led_qcaps(bp);
5123 bnxt_init_locks(struct bnxt *bp)
5127 err = pthread_mutex_init(&bp->flow_lock, NULL);
5129 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5133 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5135 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5139 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5143 rc = bnxt_init_fw(bp);
5147 if (!reconfig_dev) {
5148 rc = bnxt_setup_mac_addr(bp->eth_dev);
5152 rc = bnxt_restore_dflt_mac(bp);
5157 bnxt_config_vf_req_fwd(bp);
5159 rc = bnxt_hwrm_func_driver_register(bp);
5161 PMD_DRV_LOG(ERR, "Failed to register driver");
5166 if (bp->pdev->max_vfs) {
5167 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5169 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5173 rc = bnxt_hwrm_allocate_pf_only(bp);
5176 "Failed to allocate PF resources");
5182 rc = bnxt_alloc_mem(bp, reconfig_dev);
5186 rc = bnxt_setup_int(bp);
5190 rc = bnxt_request_int(bp);
5194 rc = bnxt_init_ctx_mem(bp);
5196 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5200 rc = bnxt_init_locks(bp);
5208 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5209 const char *value, void *opaque_arg)
5211 struct bnxt *bp = opaque_arg;
5212 unsigned long truflow;
5215 if (!value || !opaque_arg) {
5217 "Invalid parameter passed to truflow devargs.\n");
5221 truflow = strtoul(value, &end, 10);
5222 if (end == NULL || *end != '\0' ||
5223 (truflow == ULONG_MAX && errno == ERANGE)) {
5225 "Invalid parameter passed to truflow devargs.\n");
5229 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5231 "Invalid value passed to truflow devargs.\n");
5235 bp->truflow = truflow;
5237 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5243 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5244 const char *value, void *opaque_arg)
5246 struct bnxt *bp = opaque_arg;
5247 unsigned long flow_xstat;
5250 if (!value || !opaque_arg) {
5252 "Invalid parameter passed to flow_xstat devarg.\n");
5256 flow_xstat = strtoul(value, &end, 10);
5257 if (end == NULL || *end != '\0' ||
5258 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5260 "Invalid parameter passed to flow_xstat devarg.\n");
5264 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5266 "Invalid value passed to flow_xstat devarg.\n");
5270 bp->flow_xstat = flow_xstat;
5272 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5278 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5280 struct rte_kvargs *kvlist;
5282 if (devargs == NULL)
5285 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5290 * Handler for "truflow" devarg.
5291 * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1”
5293 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5294 bnxt_parse_devarg_truflow, bp);
5297 * Handler for "flow_xstat" devarg.
5298 * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1”
5300 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5301 bnxt_parse_devarg_flow_xstat, bp);
5303 rte_kvargs_free(kvlist);
5307 bnxt_dev_init(struct rte_eth_dev *eth_dev)
5309 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5310 static int version_printed;
5314 if (version_printed++ == 0)
5315 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5317 eth_dev->dev_ops = &bnxt_dev_ops;
5318 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5319 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5322 * For secondary processes, we don't initialise any further
5323 * as primary has already done this work.
5325 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5328 rte_eth_copy_pci_info(eth_dev, pci_dev);
5330 bp = eth_dev->data->dev_private;
5332 /* Parse dev arguments passed on when starting the DPDK application. */
5333 bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5335 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5337 if (bnxt_vf_pciid(pci_dev->id.device_id))
5338 bp->flags |= BNXT_FLAG_VF;
5340 if (bnxt_thor_device(pci_dev->id.device_id))
5341 bp->flags |= BNXT_FLAG_THOR_CHIP;
5343 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5344 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5345 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5346 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5347 bp->flags |= BNXT_FLAG_STINGRAY;
5349 rc = bnxt_init_board(eth_dev);
5352 "Failed to initialize board rc: %x\n", rc);
5356 rc = bnxt_alloc_hwrm_resources(bp);
5359 "Failed to allocate hwrm resource rc: %x\n", rc);
5362 rc = bnxt_init_resources(bp, false);
5366 rc = bnxt_alloc_stats_mem(bp);
5370 /* Pass the information to the rte_eth_dev_close() that it should also
5371 * release the private port resources.
5373 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5376 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5377 pci_dev->mem_resource[0].phys_addr,
5378 pci_dev->mem_resource[0].addr);
5383 bnxt_dev_uninit(eth_dev);
5388 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5397 ctx->dma = RTE_BAD_IOVA;
5398 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5401 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5403 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5404 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5405 bp->rx_fc_out_tbl.ctx_id,
5409 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5410 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5411 bp->tx_fc_out_tbl.ctx_id,
5415 if (bp->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5416 bnxt_hwrm_ctx_unrgtr(bp, bp->rx_fc_in_tbl.ctx_id);
5417 bp->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5419 if (bp->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5420 bnxt_hwrm_ctx_unrgtr(bp, bp->rx_fc_out_tbl.ctx_id);
5421 bp->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5423 if (bp->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5424 bnxt_hwrm_ctx_unrgtr(bp, bp->tx_fc_in_tbl.ctx_id);
5425 bp->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5427 if (bp->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5428 bnxt_hwrm_ctx_unrgtr(bp, bp->tx_fc_out_tbl.ctx_id);
5429 bp->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5432 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5434 bnxt_unregister_fc_ctx_mem(bp);
5436 bnxt_free_ctx_mem_buf(&bp->rx_fc_in_tbl);
5437 bnxt_free_ctx_mem_buf(&bp->rx_fc_out_tbl);
5438 bnxt_free_ctx_mem_buf(&bp->tx_fc_in_tbl);
5439 bnxt_free_ctx_mem_buf(&bp->tx_fc_out_tbl);
5442 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5444 bnxt_uninit_fc_ctx_mem(bp);
5448 bnxt_free_error_recovery_info(struct bnxt *bp)
5450 rte_free(bp->recovery_info);
5451 bp->recovery_info = NULL;
5452 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5456 bnxt_uninit_locks(struct bnxt *bp)
5458 pthread_mutex_destroy(&bp->flow_lock);
5459 pthread_mutex_destroy(&bp->def_cp_lock);
5463 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5468 bnxt_free_mem(bp, reconfig_dev);
5469 bnxt_hwrm_func_buf_unrgtr(bp);
5470 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5471 bp->flags &= ~BNXT_FLAG_REGISTERED;
5472 bnxt_free_ctx_mem(bp);
5473 if (!reconfig_dev) {
5474 bnxt_free_hwrm_resources(bp);
5475 bnxt_free_error_recovery_info(bp);
5478 bnxt_uninit_ctx_mem(bp);
5480 bnxt_uninit_locks(bp);
5481 rte_free(bp->ptp_cfg);
5487 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5489 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5492 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5494 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5495 bnxt_dev_close_op(eth_dev);
5500 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5501 struct rte_pci_device *pci_dev)
5503 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
5507 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5509 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
5510 return rte_eth_dev_pci_generic_remove(pci_dev,
5513 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5516 static struct rte_pci_driver bnxt_rte_pmd = {
5517 .id_table = bnxt_pci_id_map,
5518 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5519 .probe = bnxt_pci_probe,
5520 .remove = bnxt_pci_remove,
5524 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5526 if (strcmp(dev->device->driver->name, drv->driver.name))
5532 bool is_bnxt_supported(struct rte_eth_dev *dev)
5534 return is_device_supported(dev, &bnxt_rte_pmd);
5537 RTE_INIT(bnxt_init_log)
5539 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
5540 if (bnxt_logtype_driver >= 0)
5541 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
5544 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5545 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5546 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");