1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
30 #define DRV_MODULE_NAME "bnxt"
31 static const char bnxt_version[] =
32 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
33 int bnxt_logtype_driver;
36 * The set of PCI devices this driver supports
38 static const struct rte_pci_id bnxt_pci_id_map[] = {
39 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
40 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
41 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
42 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
43 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
45 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
92 { .vendor_id = 0, /* sentinel */ },
95 #define BNXT_ETH_RSS_SUPPORT ( \
97 ETH_RSS_NONFRAG_IPV4_TCP | \
98 ETH_RSS_NONFRAG_IPV4_UDP | \
100 ETH_RSS_NONFRAG_IPV6_TCP | \
101 ETH_RSS_NONFRAG_IPV6_UDP)
103 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
104 DEV_TX_OFFLOAD_IPV4_CKSUM | \
105 DEV_TX_OFFLOAD_TCP_CKSUM | \
106 DEV_TX_OFFLOAD_UDP_CKSUM | \
107 DEV_TX_OFFLOAD_TCP_TSO | \
108 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
109 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
110 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
111 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
112 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
113 DEV_TX_OFFLOAD_QINQ_INSERT | \
114 DEV_TX_OFFLOAD_MULTI_SEGS)
116 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
117 DEV_RX_OFFLOAD_VLAN_STRIP | \
118 DEV_RX_OFFLOAD_IPV4_CKSUM | \
119 DEV_RX_OFFLOAD_UDP_CKSUM | \
120 DEV_RX_OFFLOAD_TCP_CKSUM | \
121 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
122 DEV_RX_OFFLOAD_JUMBO_FRAME | \
123 DEV_RX_OFFLOAD_KEEP_CRC | \
124 DEV_RX_OFFLOAD_VLAN_EXTEND | \
125 DEV_RX_OFFLOAD_TCP_LRO | \
126 DEV_RX_OFFLOAD_SCATTER | \
127 DEV_RX_OFFLOAD_RSS_HASH)
129 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
130 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
131 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
132 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
133 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
134 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
135 static int bnxt_restore_vlan_filters(struct bnxt *bp);
137 int is_bnxt_in_error(struct bnxt *bp)
139 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
141 if (bp->flags & BNXT_FLAG_FW_RESET)
147 /***********************/
150 * High level utility functions
153 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
155 if (!BNXT_CHIP_THOR(bp))
158 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
159 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
160 BNXT_RSS_ENTRIES_PER_CTX_THOR;
163 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
165 if (!BNXT_CHIP_THOR(bp))
166 return HW_HASH_INDEX_SIZE;
168 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
171 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
173 bnxt_free_filter_mem(bp);
174 bnxt_free_vnic_attributes(bp);
175 bnxt_free_vnic_mem(bp);
177 /* tx/rx rings are configured as part of *_queue_setup callbacks.
178 * If the number of rings change across fw update,
179 * we don't have much choice except to warn the user.
183 bnxt_free_tx_rings(bp);
184 bnxt_free_rx_rings(bp);
186 bnxt_free_async_cp_ring(bp);
187 bnxt_free_rxtx_nq_ring(bp);
189 rte_free(bp->grp_info);
193 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
197 rc = bnxt_alloc_ring_grps(bp);
201 rc = bnxt_alloc_async_ring_struct(bp);
205 rc = bnxt_alloc_vnic_mem(bp);
209 rc = bnxt_alloc_vnic_attributes(bp);
213 rc = bnxt_alloc_filter_mem(bp);
217 rc = bnxt_alloc_async_cp_ring(bp);
221 rc = bnxt_alloc_rxtx_nq_ring(bp);
228 bnxt_free_mem(bp, reconfig);
232 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
234 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
235 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
236 uint64_t rx_offloads = dev_conf->rxmode.offloads;
237 struct bnxt_rx_queue *rxq;
241 rc = bnxt_vnic_grp_alloc(bp, vnic);
245 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
246 vnic_id, vnic, vnic->fw_grp_ids);
248 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
252 /* Alloc RSS context only if RSS mode is enabled */
253 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
254 int j, nr_ctxs = bnxt_rss_ctxts(bp);
257 for (j = 0; j < nr_ctxs; j++) {
258 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
264 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
268 vnic->num_lb_ctxts = nr_ctxs;
272 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
273 * setting is not available at this time, it will not be
274 * configured correctly in the CFA.
276 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
277 vnic->vlan_strip = true;
279 vnic->vlan_strip = false;
281 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
285 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
289 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
290 rxq = bp->eth_dev->data->rx_queues[j];
293 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
294 j, rxq->vnic, rxq->vnic->fw_grp_ids);
296 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
297 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
300 rc = bnxt_vnic_rss_configure(bp, vnic);
304 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
306 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
307 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
309 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
313 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
318 static int bnxt_init_chip(struct bnxt *bp)
320 struct rte_eth_link new;
321 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
322 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
323 uint32_t intr_vector = 0;
324 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
325 uint32_t vec = BNXT_MISC_VEC_ID;
329 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
330 bp->eth_dev->data->dev_conf.rxmode.offloads |=
331 DEV_RX_OFFLOAD_JUMBO_FRAME;
332 bp->flags |= BNXT_FLAG_JUMBO;
334 bp->eth_dev->data->dev_conf.rxmode.offloads &=
335 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
336 bp->flags &= ~BNXT_FLAG_JUMBO;
339 /* THOR does not support ring groups.
340 * But we will use the array to save RSS context IDs.
342 if (BNXT_CHIP_THOR(bp))
343 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
345 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
347 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
351 rc = bnxt_alloc_hwrm_rings(bp);
353 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
357 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
359 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
363 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
366 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
367 if (bp->rx_cos_queue[i].id != 0xff) {
368 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
372 "Num pools more than FW profile\n");
376 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
382 rc = bnxt_mq_rx_configure(bp);
384 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
388 /* VNIC configuration */
389 for (i = 0; i < bp->nr_vnics; i++) {
390 rc = bnxt_setup_one_vnic(bp, i);
395 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
398 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
402 /* check and configure queue intr-vector mapping */
403 if ((rte_intr_cap_multiple(intr_handle) ||
404 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
405 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
406 intr_vector = bp->eth_dev->data->nb_rx_queues;
407 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
408 if (intr_vector > bp->rx_cp_nr_rings) {
409 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
413 rc = rte_intr_efd_enable(intr_handle, intr_vector);
418 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
419 intr_handle->intr_vec =
420 rte_zmalloc("intr_vec",
421 bp->eth_dev->data->nb_rx_queues *
423 if (intr_handle->intr_vec == NULL) {
424 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
425 " intr_vec", bp->eth_dev->data->nb_rx_queues);
429 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
430 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
431 intr_handle->intr_vec, intr_handle->nb_efd,
432 intr_handle->max_intr);
433 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
435 intr_handle->intr_vec[queue_id] =
436 vec + BNXT_RX_VEC_START;
437 if (vec < base + intr_handle->nb_efd - 1)
442 /* enable uio/vfio intr/eventfd mapping */
443 rc = rte_intr_enable(intr_handle);
444 #ifndef RTE_EXEC_ENV_FREEBSD
445 /* In FreeBSD OS, nic_uio driver does not support interrupts */
450 rc = bnxt_get_hwrm_link_config(bp, &new);
452 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
456 if (!bp->link_info.link_up) {
457 rc = bnxt_set_hwrm_link_config(bp, true);
460 "HWRM link config failure rc: %x\n", rc);
464 bnxt_print_link_info(bp->eth_dev);
466 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
468 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
473 rte_free(intr_handle->intr_vec);
475 rte_intr_efd_disable(intr_handle);
477 /* Some of the error status returned by FW may not be from errno.h */
484 static int bnxt_shutdown_nic(struct bnxt *bp)
486 bnxt_free_all_hwrm_resources(bp);
487 bnxt_free_all_filters(bp);
488 bnxt_free_all_vnics(bp);
493 * Device configuration and status function
496 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
497 struct rte_eth_dev_info *dev_info)
499 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
500 struct bnxt *bp = eth_dev->data->dev_private;
501 uint16_t max_vnics, i, j, vpool, vrxq;
502 unsigned int max_rx_rings;
505 rc = is_bnxt_in_error(bp);
510 dev_info->max_mac_addrs = bp->max_l2_ctx;
511 dev_info->max_hash_mac_addrs = 0;
513 /* PF/VF specifics */
515 dev_info->max_vfs = pdev->max_vfs;
517 max_rx_rings = BNXT_MAX_RINGS(bp);
518 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
519 dev_info->max_rx_queues = max_rx_rings;
520 dev_info->max_tx_queues = max_rx_rings;
521 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
522 dev_info->hash_key_size = 40;
523 max_vnics = bp->max_vnics;
526 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
527 dev_info->max_mtu = BNXT_MAX_MTU;
529 /* Fast path specifics */
530 dev_info->min_rx_bufsize = 1;
531 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
533 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
534 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
535 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
536 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
537 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
540 dev_info->default_rxconf = (struct rte_eth_rxconf) {
546 .rx_free_thresh = 32,
547 /* If no descriptors available, pkts are dropped by default */
551 dev_info->default_txconf = (struct rte_eth_txconf) {
557 .tx_free_thresh = 32,
560 eth_dev->data->dev_conf.intr_conf.lsc = 1;
562 eth_dev->data->dev_conf.intr_conf.rxq = 1;
563 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
564 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
565 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
566 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
571 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
572 * need further investigation.
576 vpool = 64; /* ETH_64_POOLS */
577 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
578 for (i = 0; i < 4; vpool >>= 1, i++) {
579 if (max_vnics > vpool) {
580 for (j = 0; j < 5; vrxq >>= 1, j++) {
581 if (dev_info->max_rx_queues > vrxq) {
587 /* Not enough resources to support VMDq */
591 /* Not enough resources to support VMDq */
595 dev_info->max_vmdq_pools = vpool;
596 dev_info->vmdq_queue_num = vrxq;
598 dev_info->vmdq_pool_base = 0;
599 dev_info->vmdq_queue_base = 0;
604 /* Configure the device based on the configuration provided */
605 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
607 struct bnxt *bp = eth_dev->data->dev_private;
608 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
611 bp->rx_queues = (void *)eth_dev->data->rx_queues;
612 bp->tx_queues = (void *)eth_dev->data->tx_queues;
613 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
614 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
616 rc = is_bnxt_in_error(bp);
620 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
621 rc = bnxt_hwrm_check_vf_rings(bp);
623 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
627 /* If a resource has already been allocated - in this case
628 * it is the async completion ring, free it. Reallocate it after
629 * resource reservation. This will ensure the resource counts
630 * are calculated correctly.
633 pthread_mutex_lock(&bp->def_cp_lock);
635 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
636 bnxt_disable_int(bp);
637 bnxt_free_cp_ring(bp, bp->async_cp_ring);
640 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
642 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
643 pthread_mutex_unlock(&bp->def_cp_lock);
647 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
648 rc = bnxt_alloc_async_cp_ring(bp);
650 pthread_mutex_unlock(&bp->def_cp_lock);
656 pthread_mutex_unlock(&bp->def_cp_lock);
658 /* legacy driver needs to get updated values */
659 rc = bnxt_hwrm_func_qcaps(bp);
661 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
666 /* Inherit new configurations */
667 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
668 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
669 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
670 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
671 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
675 if (BNXT_HAS_RING_GRPS(bp) &&
676 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
679 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
680 bp->max_vnics < eth_dev->data->nb_rx_queues)
683 bp->rx_cp_nr_rings = bp->rx_nr_rings;
684 bp->tx_cp_nr_rings = bp->tx_nr_rings;
686 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
687 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
688 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
690 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
692 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
693 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
695 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
701 "Insufficient resources to support requested config\n");
703 "Num Queues Requested: Tx %d, Rx %d\n",
704 eth_dev->data->nb_tx_queues,
705 eth_dev->data->nb_rx_queues);
707 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
708 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
709 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
713 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
715 struct rte_eth_link *link = ð_dev->data->dev_link;
717 if (link->link_status)
718 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
719 eth_dev->data->port_id,
720 (uint32_t)link->link_speed,
721 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
722 ("full-duplex") : ("half-duplex\n"));
724 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
725 eth_dev->data->port_id);
729 * Determine whether the current configuration requires support for scattered
730 * receive; return 1 if scattered receive is required and 0 if not.
732 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
737 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
740 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
741 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
743 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
744 RTE_PKTMBUF_HEADROOM);
745 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
751 static eth_rx_burst_t
752 bnxt_receive_function(struct rte_eth_dev *eth_dev)
754 struct bnxt *bp = eth_dev->data->dev_private;
757 #ifndef RTE_LIBRTE_IEEE1588
759 * Vector mode receive can be enabled only if scatter rx is not
760 * in use and rx offloads are limited to VLAN stripping and
763 if (!eth_dev->data->scattered_rx &&
764 !(eth_dev->data->dev_conf.rxmode.offloads &
765 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
766 DEV_RX_OFFLOAD_KEEP_CRC |
767 DEV_RX_OFFLOAD_JUMBO_FRAME |
768 DEV_RX_OFFLOAD_IPV4_CKSUM |
769 DEV_RX_OFFLOAD_UDP_CKSUM |
770 DEV_RX_OFFLOAD_TCP_CKSUM |
771 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
772 DEV_RX_OFFLOAD_RSS_HASH |
773 DEV_RX_OFFLOAD_VLAN_FILTER))) {
774 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
775 eth_dev->data->port_id);
776 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
777 return bnxt_recv_pkts_vec;
779 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
780 eth_dev->data->port_id);
782 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
783 eth_dev->data->port_id,
784 eth_dev->data->scattered_rx,
785 eth_dev->data->dev_conf.rxmode.offloads);
788 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
789 return bnxt_recv_pkts;
792 static eth_tx_burst_t
793 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
796 #ifndef RTE_LIBRTE_IEEE1588
798 * Vector mode transmit can be enabled only if not using scatter rx
801 if (!eth_dev->data->scattered_rx &&
802 !eth_dev->data->dev_conf.txmode.offloads) {
803 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
804 eth_dev->data->port_id);
805 return bnxt_xmit_pkts_vec;
807 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
808 eth_dev->data->port_id);
810 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
811 eth_dev->data->port_id,
812 eth_dev->data->scattered_rx,
813 eth_dev->data->dev_conf.txmode.offloads);
816 return bnxt_xmit_pkts;
819 static int bnxt_handle_if_change_status(struct bnxt *bp)
823 /* Since fw has undergone a reset and lost all contexts,
824 * set fatal flag to not issue hwrm during cleanup
826 bp->flags |= BNXT_FLAG_FATAL_ERROR;
827 bnxt_uninit_resources(bp, true);
829 /* clear fatal flag so that re-init happens */
830 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
831 rc = bnxt_init_resources(bp, true);
833 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
838 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
840 struct bnxt *bp = eth_dev->data->dev_private;
841 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
845 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
846 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
850 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
852 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
853 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
856 rc = bnxt_hwrm_if_change(bp, 1);
858 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
859 rc = bnxt_handle_if_change_status(bp);
866 rc = bnxt_init_chip(bp);
870 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
872 bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
875 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
876 vlan_mask |= ETH_VLAN_FILTER_MASK;
877 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
878 vlan_mask |= ETH_VLAN_STRIP_MASK;
879 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
883 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
884 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
886 bp->flags |= BNXT_FLAG_INIT_DONE;
887 eth_dev->data->dev_started = 1;
888 pthread_mutex_lock(&bp->def_cp_lock);
889 bnxt_schedule_fw_health_check(bp);
890 pthread_mutex_unlock(&bp->def_cp_lock);
894 bnxt_hwrm_if_change(bp, 0);
895 bnxt_shutdown_nic(bp);
896 bnxt_free_tx_mbufs(bp);
897 bnxt_free_rx_mbufs(bp);
902 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
904 struct bnxt *bp = eth_dev->data->dev_private;
907 if (!bp->link_info.link_up)
908 rc = bnxt_set_hwrm_link_config(bp, true);
910 eth_dev->data->dev_link.link_status = 1;
912 bnxt_print_link_info(eth_dev);
916 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
918 struct bnxt *bp = eth_dev->data->dev_private;
920 eth_dev->data->dev_link.link_status = 0;
921 bnxt_set_hwrm_link_config(bp, false);
922 bp->link_info.link_up = 0;
927 /* Unload the driver, release resources */
928 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
930 struct bnxt *bp = eth_dev->data->dev_private;
931 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
932 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
934 eth_dev->data->dev_started = 0;
935 /* Prevent crashes when queues are still in use */
936 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
937 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
939 bnxt_disable_int(bp);
941 /* disable uio/vfio intr/eventfd mapping */
942 rte_intr_disable(intr_handle);
944 bnxt_cancel_fw_health_check(bp);
946 bp->flags &= ~BNXT_FLAG_INIT_DONE;
947 if (bp->eth_dev->data->dev_started) {
948 /* TBD: STOP HW queues DMA */
949 eth_dev->data->dev_link.link_status = 0;
951 bnxt_dev_set_link_down_op(eth_dev);
953 /* Wait for link to be reset and the async notification to process.
954 * During reset recovery, there is no need to wait
956 if (!is_bnxt_in_error(bp))
957 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
959 /* Clean queue intr-vector mapping */
960 rte_intr_efd_disable(intr_handle);
961 if (intr_handle->intr_vec != NULL) {
962 rte_free(intr_handle->intr_vec);
963 intr_handle->intr_vec = NULL;
966 bnxt_hwrm_port_clr_stats(bp);
967 bnxt_free_tx_mbufs(bp);
968 bnxt_free_rx_mbufs(bp);
969 /* Process any remaining notifications in default completion queue */
970 bnxt_int_handler(eth_dev);
971 bnxt_shutdown_nic(bp);
972 bnxt_hwrm_if_change(bp, 0);
974 rte_free(bp->mark_table);
975 bp->mark_table = NULL;
977 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
982 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
984 struct bnxt *bp = eth_dev->data->dev_private;
986 if (bp->dev_stopped == 0)
987 bnxt_dev_stop_op(eth_dev);
989 bnxt_uninit_resources(bp, false);
991 eth_dev->dev_ops = NULL;
992 eth_dev->rx_pkt_burst = NULL;
993 eth_dev->tx_pkt_burst = NULL;
995 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
996 bp->tx_mem_zone = NULL;
997 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
998 bp->rx_mem_zone = NULL;
1000 rte_free(bp->pf.vf_info);
1001 bp->pf.vf_info = NULL;
1003 rte_free(bp->grp_info);
1004 bp->grp_info = NULL;
1007 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1010 struct bnxt *bp = eth_dev->data->dev_private;
1011 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1012 struct bnxt_vnic_info *vnic;
1013 struct bnxt_filter_info *filter, *temp_filter;
1016 if (is_bnxt_in_error(bp))
1020 * Loop through all VNICs from the specified filter flow pools to
1021 * remove the corresponding MAC addr filter
1023 for (i = 0; i < bp->nr_vnics; i++) {
1024 if (!(pool_mask & (1ULL << i)))
1027 vnic = &bp->vnic_info[i];
1028 filter = STAILQ_FIRST(&vnic->filter);
1030 temp_filter = STAILQ_NEXT(filter, next);
1031 if (filter->mac_index == index) {
1032 STAILQ_REMOVE(&vnic->filter, filter,
1033 bnxt_filter_info, next);
1034 bnxt_hwrm_clear_l2_filter(bp, filter);
1035 bnxt_free_filter(bp, filter);
1037 filter = temp_filter;
1042 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1043 struct rte_ether_addr *mac_addr, uint32_t index,
1046 struct bnxt_filter_info *filter;
1049 /* Attach requested MAC address to the new l2_filter */
1050 STAILQ_FOREACH(filter, &vnic->filter, next) {
1051 if (filter->mac_index == index) {
1053 "MAC addr already existed for pool %d\n",
1059 filter = bnxt_alloc_filter(bp);
1061 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1065 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1066 * if the MAC that's been programmed now is a different one, then,
1067 * copy that addr to filter->l2_addr
1070 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1071 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1073 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1075 filter->mac_index = index;
1076 if (filter->mac_index == 0)
1077 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1079 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1081 bnxt_free_filter(bp, filter);
1087 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1088 struct rte_ether_addr *mac_addr,
1089 uint32_t index, uint32_t pool)
1091 struct bnxt *bp = eth_dev->data->dev_private;
1092 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1095 rc = is_bnxt_in_error(bp);
1099 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1100 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1105 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1109 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1114 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1115 bool exp_link_status)
1118 struct bnxt *bp = eth_dev->data->dev_private;
1119 struct rte_eth_link new;
1120 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1121 BNXT_LINK_DOWN_WAIT_CNT;
1123 rc = is_bnxt_in_error(bp);
1127 memset(&new, 0, sizeof(new));
1129 /* Retrieve link info from hardware */
1130 rc = bnxt_get_hwrm_link_config(bp, &new);
1132 new.link_speed = ETH_LINK_SPEED_100M;
1133 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1135 "Failed to retrieve link rc = 0x%x!\n", rc);
1139 if (!wait_to_complete || new.link_status == exp_link_status)
1142 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1146 /* Timed out or success */
1147 if (new.link_status != eth_dev->data->dev_link.link_status ||
1148 new.link_speed != eth_dev->data->dev_link.link_speed) {
1149 rte_eth_linkstatus_set(eth_dev, &new);
1151 _rte_eth_dev_callback_process(eth_dev,
1152 RTE_ETH_EVENT_INTR_LSC,
1155 bnxt_print_link_info(eth_dev);
1161 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1162 int wait_to_complete)
1164 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1167 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1169 struct bnxt *bp = eth_dev->data->dev_private;
1170 struct bnxt_vnic_info *vnic;
1174 rc = is_bnxt_in_error(bp);
1178 /* Filter settings will get applied when port is started */
1179 if (bp->dev_stopped == 1)
1182 if (bp->vnic_info == NULL)
1185 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1187 old_flags = vnic->flags;
1188 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1189 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1191 vnic->flags = old_flags;
1196 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1198 struct bnxt *bp = eth_dev->data->dev_private;
1199 struct bnxt_vnic_info *vnic;
1203 rc = is_bnxt_in_error(bp);
1207 /* Filter settings will get applied when port is started */
1208 if (bp->dev_stopped == 1)
1211 if (bp->vnic_info == NULL)
1214 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1216 old_flags = vnic->flags;
1217 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1218 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1220 vnic->flags = old_flags;
1225 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1227 struct bnxt *bp = eth_dev->data->dev_private;
1228 struct bnxt_vnic_info *vnic;
1232 rc = is_bnxt_in_error(bp);
1236 /* Filter settings will get applied when port is started */
1237 if (bp->dev_stopped == 1)
1240 if (bp->vnic_info == NULL)
1243 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1245 old_flags = vnic->flags;
1246 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1247 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1249 vnic->flags = old_flags;
1254 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1256 struct bnxt *bp = eth_dev->data->dev_private;
1257 struct bnxt_vnic_info *vnic;
1261 rc = is_bnxt_in_error(bp);
1265 /* Filter settings will get applied when port is started */
1266 if (bp->dev_stopped == 1)
1269 if (bp->vnic_info == NULL)
1272 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1274 old_flags = vnic->flags;
1275 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1276 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1278 vnic->flags = old_flags;
1283 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1284 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1286 if (qid >= bp->rx_nr_rings)
1289 return bp->eth_dev->data->rx_queues[qid];
1292 /* Return rxq corresponding to a given rss table ring/group ID. */
1293 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1295 struct bnxt_rx_queue *rxq;
1298 if (!BNXT_HAS_RING_GRPS(bp)) {
1299 for (i = 0; i < bp->rx_nr_rings; i++) {
1300 rxq = bp->eth_dev->data->rx_queues[i];
1301 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1305 for (i = 0; i < bp->rx_nr_rings; i++) {
1306 if (bp->grp_info[i].fw_grp_id == fwr)
1311 return INVALID_HW_RING_ID;
1314 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1315 struct rte_eth_rss_reta_entry64 *reta_conf,
1318 struct bnxt *bp = eth_dev->data->dev_private;
1319 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1320 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1321 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1325 rc = is_bnxt_in_error(bp);
1329 if (!vnic->rss_table)
1332 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1335 if (reta_size != tbl_size) {
1336 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1337 "(%d) must equal the size supported by the hardware "
1338 "(%d)\n", reta_size, tbl_size);
1342 for (i = 0; i < reta_size; i++) {
1343 struct bnxt_rx_queue *rxq;
1345 idx = i / RTE_RETA_GROUP_SIZE;
1346 sft = i % RTE_RETA_GROUP_SIZE;
1348 if (!(reta_conf[idx].mask & (1ULL << sft)))
1351 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1353 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1357 if (BNXT_CHIP_THOR(bp)) {
1358 vnic->rss_table[i * 2] =
1359 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1360 vnic->rss_table[i * 2 + 1] =
1361 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1363 vnic->rss_table[i] =
1364 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1368 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1372 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1373 struct rte_eth_rss_reta_entry64 *reta_conf,
1376 struct bnxt *bp = eth_dev->data->dev_private;
1377 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1378 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1379 uint16_t idx, sft, i;
1382 rc = is_bnxt_in_error(bp);
1386 /* Retrieve from the default VNIC */
1389 if (!vnic->rss_table)
1392 if (reta_size != tbl_size) {
1393 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1394 "(%d) must equal the size supported by the hardware "
1395 "(%d)\n", reta_size, tbl_size);
1399 for (idx = 0, i = 0; i < reta_size; i++) {
1400 idx = i / RTE_RETA_GROUP_SIZE;
1401 sft = i % RTE_RETA_GROUP_SIZE;
1403 if (reta_conf[idx].mask & (1ULL << sft)) {
1406 if (BNXT_CHIP_THOR(bp))
1407 qid = bnxt_rss_to_qid(bp,
1408 vnic->rss_table[i * 2]);
1410 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1412 if (qid == INVALID_HW_RING_ID) {
1413 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1416 reta_conf[idx].reta[sft] = qid;
1423 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1424 struct rte_eth_rss_conf *rss_conf)
1426 struct bnxt *bp = eth_dev->data->dev_private;
1427 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1428 struct bnxt_vnic_info *vnic;
1431 rc = is_bnxt_in_error(bp);
1436 * If RSS enablement were different than dev_configure,
1437 * then return -EINVAL
1439 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1440 if (!rss_conf->rss_hf)
1441 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1443 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1447 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1448 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1450 /* Update the default RSS VNIC(s) */
1451 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1452 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1455 * If hashkey is not specified, use the previously configured
1458 if (!rss_conf->rss_key)
1461 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1463 "Invalid hashkey length, should be 16 bytes\n");
1466 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1469 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1473 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1474 struct rte_eth_rss_conf *rss_conf)
1476 struct bnxt *bp = eth_dev->data->dev_private;
1477 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1479 uint32_t hash_types;
1481 rc = is_bnxt_in_error(bp);
1485 /* RSS configuration is the same for all VNICs */
1486 if (vnic && vnic->rss_hash_key) {
1487 if (rss_conf->rss_key) {
1488 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1489 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1490 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1493 hash_types = vnic->hash_type;
1494 rss_conf->rss_hf = 0;
1495 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1496 rss_conf->rss_hf |= ETH_RSS_IPV4;
1497 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1499 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1500 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1502 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1504 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1505 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1507 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1509 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1510 rss_conf->rss_hf |= ETH_RSS_IPV6;
1511 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1513 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1514 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1516 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1518 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1519 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1521 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1525 "Unknwon RSS config from firmware (%08x), RSS disabled",
1530 rss_conf->rss_hf = 0;
1535 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1536 struct rte_eth_fc_conf *fc_conf)
1538 struct bnxt *bp = dev->data->dev_private;
1539 struct rte_eth_link link_info;
1542 rc = is_bnxt_in_error(bp);
1546 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1550 memset(fc_conf, 0, sizeof(*fc_conf));
1551 if (bp->link_info.auto_pause)
1552 fc_conf->autoneg = 1;
1553 switch (bp->link_info.pause) {
1555 fc_conf->mode = RTE_FC_NONE;
1557 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1558 fc_conf->mode = RTE_FC_TX_PAUSE;
1560 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1561 fc_conf->mode = RTE_FC_RX_PAUSE;
1563 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1564 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1565 fc_conf->mode = RTE_FC_FULL;
1571 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1572 struct rte_eth_fc_conf *fc_conf)
1574 struct bnxt *bp = dev->data->dev_private;
1577 rc = is_bnxt_in_error(bp);
1581 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1582 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1586 switch (fc_conf->mode) {
1588 bp->link_info.auto_pause = 0;
1589 bp->link_info.force_pause = 0;
1591 case RTE_FC_RX_PAUSE:
1592 if (fc_conf->autoneg) {
1593 bp->link_info.auto_pause =
1594 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1595 bp->link_info.force_pause = 0;
1597 bp->link_info.auto_pause = 0;
1598 bp->link_info.force_pause =
1599 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1602 case RTE_FC_TX_PAUSE:
1603 if (fc_conf->autoneg) {
1604 bp->link_info.auto_pause =
1605 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1606 bp->link_info.force_pause = 0;
1608 bp->link_info.auto_pause = 0;
1609 bp->link_info.force_pause =
1610 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1614 if (fc_conf->autoneg) {
1615 bp->link_info.auto_pause =
1616 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1617 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1618 bp->link_info.force_pause = 0;
1620 bp->link_info.auto_pause = 0;
1621 bp->link_info.force_pause =
1622 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1623 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1627 return bnxt_set_hwrm_link_config(bp, true);
1630 /* Add UDP tunneling port */
1632 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1633 struct rte_eth_udp_tunnel *udp_tunnel)
1635 struct bnxt *bp = eth_dev->data->dev_private;
1636 uint16_t tunnel_type = 0;
1639 rc = is_bnxt_in_error(bp);
1643 switch (udp_tunnel->prot_type) {
1644 case RTE_TUNNEL_TYPE_VXLAN:
1645 if (bp->vxlan_port_cnt) {
1646 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1647 udp_tunnel->udp_port);
1648 if (bp->vxlan_port != udp_tunnel->udp_port) {
1649 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1652 bp->vxlan_port_cnt++;
1656 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1657 bp->vxlan_port_cnt++;
1659 case RTE_TUNNEL_TYPE_GENEVE:
1660 if (bp->geneve_port_cnt) {
1661 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1662 udp_tunnel->udp_port);
1663 if (bp->geneve_port != udp_tunnel->udp_port) {
1664 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1667 bp->geneve_port_cnt++;
1671 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1672 bp->geneve_port_cnt++;
1675 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1678 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1684 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1685 struct rte_eth_udp_tunnel *udp_tunnel)
1687 struct bnxt *bp = eth_dev->data->dev_private;
1688 uint16_t tunnel_type = 0;
1692 rc = is_bnxt_in_error(bp);
1696 switch (udp_tunnel->prot_type) {
1697 case RTE_TUNNEL_TYPE_VXLAN:
1698 if (!bp->vxlan_port_cnt) {
1699 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1702 if (bp->vxlan_port != udp_tunnel->udp_port) {
1703 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1704 udp_tunnel->udp_port, bp->vxlan_port);
1707 if (--bp->vxlan_port_cnt)
1711 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1712 port = bp->vxlan_fw_dst_port_id;
1714 case RTE_TUNNEL_TYPE_GENEVE:
1715 if (!bp->geneve_port_cnt) {
1716 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1719 if (bp->geneve_port != udp_tunnel->udp_port) {
1720 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1721 udp_tunnel->udp_port, bp->geneve_port);
1724 if (--bp->geneve_port_cnt)
1728 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1729 port = bp->geneve_fw_dst_port_id;
1732 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1736 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1739 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1742 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1743 bp->geneve_port = 0;
1748 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1750 struct bnxt_filter_info *filter;
1751 struct bnxt_vnic_info *vnic;
1753 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1755 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1756 filter = STAILQ_FIRST(&vnic->filter);
1758 /* Search for this matching MAC+VLAN filter */
1759 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1760 /* Delete the filter */
1761 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1764 STAILQ_REMOVE(&vnic->filter, filter,
1765 bnxt_filter_info, next);
1766 bnxt_free_filter(bp, filter);
1768 "Deleted vlan filter for %d\n",
1772 filter = STAILQ_NEXT(filter, next);
1777 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1779 struct bnxt_filter_info *filter;
1780 struct bnxt_vnic_info *vnic;
1782 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1783 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1784 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1786 /* Implementation notes on the use of VNIC in this command:
1788 * By default, these filters belong to default vnic for the function.
1789 * Once these filters are set up, only destination VNIC can be modified.
1790 * If the destination VNIC is not specified in this command,
1791 * then the HWRM shall only create an l2 context id.
1794 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1795 filter = STAILQ_FIRST(&vnic->filter);
1796 /* Check if the VLAN has already been added */
1798 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
1801 filter = STAILQ_NEXT(filter, next);
1804 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1805 * command to create MAC+VLAN filter with the right flags, enables set.
1807 filter = bnxt_alloc_filter(bp);
1810 "MAC/VLAN filter alloc failed\n");
1813 /* MAC + VLAN ID filter */
1814 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1815 * untagged packets are received
1817 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1818 * packets and only the programmed vlan's packets are received
1820 filter->l2_ivlan = vlan_id;
1821 filter->l2_ivlan_mask = 0x0FFF;
1822 filter->enables |= en;
1823 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1825 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1827 /* Free the newly allocated filter as we were
1828 * not able to create the filter in hardware.
1830 bnxt_free_filter(bp, filter);
1834 filter->mac_index = 0;
1835 /* Add this new filter to the list */
1837 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1839 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1842 "Added Vlan filter for %d\n", vlan_id);
1846 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1847 uint16_t vlan_id, int on)
1849 struct bnxt *bp = eth_dev->data->dev_private;
1852 rc = is_bnxt_in_error(bp);
1856 /* These operations apply to ALL existing MAC/VLAN filters */
1858 return bnxt_add_vlan_filter(bp, vlan_id);
1860 return bnxt_del_vlan_filter(bp, vlan_id);
1863 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1864 struct bnxt_vnic_info *vnic)
1866 struct bnxt_filter_info *filter;
1869 filter = STAILQ_FIRST(&vnic->filter);
1871 if (filter->mac_index == 0 &&
1872 !memcmp(filter->l2_addr, bp->mac_addr,
1873 RTE_ETHER_ADDR_LEN)) {
1874 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1876 STAILQ_REMOVE(&vnic->filter, filter,
1877 bnxt_filter_info, next);
1878 bnxt_free_filter(bp, filter);
1882 filter = STAILQ_NEXT(filter, next);
1888 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
1890 struct bnxt_vnic_info *vnic;
1894 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1895 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1896 /* Remove any VLAN filters programmed */
1897 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1898 bnxt_del_vlan_filter(bp, i);
1900 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1904 /* Default filter will allow packets that match the
1905 * dest mac. So, it has to be deleted, otherwise, we
1906 * will endup receiving vlan packets for which the
1907 * filter is not programmed, when hw-vlan-filter
1908 * configuration is ON
1910 bnxt_del_dflt_mac_filter(bp, vnic);
1911 /* This filter will allow only untagged packets */
1912 bnxt_add_vlan_filter(bp, 0);
1914 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1915 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1920 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
1922 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
1926 /* Destroy vnic filters and vnic */
1927 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1928 DEV_RX_OFFLOAD_VLAN_FILTER) {
1929 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1930 bnxt_del_vlan_filter(bp, i);
1932 bnxt_del_dflt_mac_filter(bp, vnic);
1934 rc = bnxt_hwrm_vnic_free(bp, vnic);
1938 rte_free(vnic->fw_grp_ids);
1939 vnic->fw_grp_ids = NULL;
1945 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
1947 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1950 /* Destroy, recreate and reconfigure the default vnic */
1951 rc = bnxt_free_one_vnic(bp, 0);
1955 /* default vnic 0 */
1956 rc = bnxt_setup_one_vnic(bp, 0);
1960 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1961 DEV_RX_OFFLOAD_VLAN_FILTER) {
1962 rc = bnxt_add_vlan_filter(bp, 0);
1963 bnxt_restore_vlan_filters(bp);
1965 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1968 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1972 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1973 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1979 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1981 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1982 struct bnxt *bp = dev->data->dev_private;
1985 rc = is_bnxt_in_error(bp);
1989 /* Filter settings will get applied when port is started */
1990 if (bp->dev_stopped == 1)
1993 if (mask & ETH_VLAN_FILTER_MASK) {
1994 /* Enable or disable VLAN filtering */
1995 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2000 if (mask & ETH_VLAN_STRIP_MASK) {
2001 /* Enable or disable VLAN stripping */
2002 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2007 if (mask & ETH_VLAN_EXTEND_MASK) {
2008 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2009 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2011 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2018 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2021 struct bnxt *bp = dev->data->dev_private;
2022 int qinq = dev->data->dev_conf.rxmode.offloads &
2023 DEV_RX_OFFLOAD_VLAN_EXTEND;
2025 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2026 vlan_type != ETH_VLAN_TYPE_OUTER) {
2028 "Unsupported vlan type.");
2033 "QinQ not enabled. Needs to be ON as we can "
2034 "accelerate only outer vlan\n");
2038 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2040 case RTE_ETHER_TYPE_QINQ:
2042 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2044 case RTE_ETHER_TYPE_VLAN:
2046 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2050 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2054 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2058 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2061 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2064 bp->outer_tpid_bd |= tpid;
2065 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2066 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2068 "Can accelerate only outer vlan in QinQ\n");
2076 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2077 struct rte_ether_addr *addr)
2079 struct bnxt *bp = dev->data->dev_private;
2080 /* Default Filter is tied to VNIC 0 */
2081 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2084 rc = is_bnxt_in_error(bp);
2088 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2091 if (rte_is_zero_ether_addr(addr))
2094 /* Check if the requested MAC is already added */
2095 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2098 /* Destroy filter and re-create it */
2099 bnxt_del_dflt_mac_filter(bp, vnic);
2101 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2102 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2103 /* This filter will allow only untagged packets */
2104 rc = bnxt_add_vlan_filter(bp, 0);
2106 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2109 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2114 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2115 struct rte_ether_addr *mc_addr_set,
2116 uint32_t nb_mc_addr)
2118 struct bnxt *bp = eth_dev->data->dev_private;
2119 char *mc_addr_list = (char *)mc_addr_set;
2120 struct bnxt_vnic_info *vnic;
2121 uint32_t off = 0, i = 0;
2124 rc = is_bnxt_in_error(bp);
2128 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2130 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2131 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2135 /* TODO Check for Duplicate mcast addresses */
2136 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2137 for (i = 0; i < nb_mc_addr; i++) {
2138 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2139 RTE_ETHER_ADDR_LEN);
2140 off += RTE_ETHER_ADDR_LEN;
2143 vnic->mc_addr_cnt = i;
2144 if (vnic->mc_addr_cnt)
2145 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2147 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2150 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2154 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2156 struct bnxt *bp = dev->data->dev_private;
2157 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2158 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2159 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2162 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2163 fw_major, fw_minor, fw_updt);
2165 ret += 1; /* add the size of '\0' */
2166 if (fw_size < (uint32_t)ret)
2173 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2174 struct rte_eth_rxq_info *qinfo)
2176 struct bnxt *bp = dev->data->dev_private;
2177 struct bnxt_rx_queue *rxq;
2179 if (is_bnxt_in_error(bp))
2182 rxq = dev->data->rx_queues[queue_id];
2184 qinfo->mp = rxq->mb_pool;
2185 qinfo->scattered_rx = dev->data->scattered_rx;
2186 qinfo->nb_desc = rxq->nb_rx_desc;
2188 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2189 qinfo->conf.rx_drop_en = 0;
2190 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2194 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2195 struct rte_eth_txq_info *qinfo)
2197 struct bnxt *bp = dev->data->dev_private;
2198 struct bnxt_tx_queue *txq;
2200 if (is_bnxt_in_error(bp))
2203 txq = dev->data->tx_queues[queue_id];
2205 qinfo->nb_desc = txq->nb_tx_desc;
2207 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2208 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2209 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2211 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2212 qinfo->conf.tx_rs_thresh = 0;
2213 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2216 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2218 struct bnxt *bp = eth_dev->data->dev_private;
2219 uint32_t new_pkt_size;
2223 rc = is_bnxt_in_error(bp);
2227 /* Exit if receive queues are not configured yet */
2228 if (!eth_dev->data->nb_rx_queues)
2231 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2232 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2236 * If vector-mode tx/rx is active, disallow any MTU change that would
2237 * require scattered receive support.
2239 if (eth_dev->data->dev_started &&
2240 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2241 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2243 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2245 "MTU change would require scattered rx support. ");
2246 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2251 if (new_mtu > RTE_ETHER_MTU) {
2252 bp->flags |= BNXT_FLAG_JUMBO;
2253 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2254 DEV_RX_OFFLOAD_JUMBO_FRAME;
2256 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2257 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2258 bp->flags &= ~BNXT_FLAG_JUMBO;
2261 /* Is there a change in mtu setting? */
2262 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2265 for (i = 0; i < bp->nr_vnics; i++) {
2266 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2269 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2270 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2274 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2275 size -= RTE_PKTMBUF_HEADROOM;
2277 if (size < new_mtu) {
2278 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2285 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2287 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2293 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2295 struct bnxt *bp = dev->data->dev_private;
2296 uint16_t vlan = bp->vlan;
2299 rc = is_bnxt_in_error(bp);
2303 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2305 "PVID cannot be modified for this function\n");
2308 bp->vlan = on ? pvid : 0;
2310 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2317 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2319 struct bnxt *bp = dev->data->dev_private;
2322 rc = is_bnxt_in_error(bp);
2326 return bnxt_hwrm_port_led_cfg(bp, true);
2330 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2332 struct bnxt *bp = dev->data->dev_private;
2335 rc = is_bnxt_in_error(bp);
2339 return bnxt_hwrm_port_led_cfg(bp, false);
2343 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2345 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2346 uint32_t desc = 0, raw_cons = 0, cons;
2347 struct bnxt_cp_ring_info *cpr;
2348 struct bnxt_rx_queue *rxq;
2349 struct rx_pkt_cmpl *rxcmp;
2352 rc = is_bnxt_in_error(bp);
2356 rxq = dev->data->rx_queues[rx_queue_id];
2358 raw_cons = cpr->cp_raw_cons;
2361 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2362 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2363 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2365 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2377 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2379 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2380 struct bnxt_rx_ring_info *rxr;
2381 struct bnxt_cp_ring_info *cpr;
2382 struct bnxt_sw_rx_bd *rx_buf;
2383 struct rx_pkt_cmpl *rxcmp;
2384 uint32_t cons, cp_cons;
2390 rc = is_bnxt_in_error(rxq->bp);
2397 if (offset >= rxq->nb_rx_desc)
2400 cons = RING_CMP(cpr->cp_ring_struct, offset);
2401 cp_cons = cpr->cp_raw_cons;
2402 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2404 if (cons > cp_cons) {
2405 if (CMPL_VALID(rxcmp, cpr->valid))
2406 return RTE_ETH_RX_DESC_DONE;
2408 if (CMPL_VALID(rxcmp, !cpr->valid))
2409 return RTE_ETH_RX_DESC_DONE;
2411 rx_buf = &rxr->rx_buf_ring[cons];
2412 if (rx_buf->mbuf == NULL)
2413 return RTE_ETH_RX_DESC_UNAVAIL;
2416 return RTE_ETH_RX_DESC_AVAIL;
2420 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2422 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2423 struct bnxt_tx_ring_info *txr;
2424 struct bnxt_cp_ring_info *cpr;
2425 struct bnxt_sw_tx_bd *tx_buf;
2426 struct tx_pkt_cmpl *txcmp;
2427 uint32_t cons, cp_cons;
2433 rc = is_bnxt_in_error(txq->bp);
2440 if (offset >= txq->nb_tx_desc)
2443 cons = RING_CMP(cpr->cp_ring_struct, offset);
2444 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2445 cp_cons = cpr->cp_raw_cons;
2447 if (cons > cp_cons) {
2448 if (CMPL_VALID(txcmp, cpr->valid))
2449 return RTE_ETH_TX_DESC_UNAVAIL;
2451 if (CMPL_VALID(txcmp, !cpr->valid))
2452 return RTE_ETH_TX_DESC_UNAVAIL;
2454 tx_buf = &txr->tx_buf_ring[cons];
2455 if (tx_buf->mbuf == NULL)
2456 return RTE_ETH_TX_DESC_DONE;
2458 return RTE_ETH_TX_DESC_FULL;
2461 static struct bnxt_filter_info *
2462 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2463 struct rte_eth_ethertype_filter *efilter,
2464 struct bnxt_vnic_info *vnic0,
2465 struct bnxt_vnic_info *vnic,
2468 struct bnxt_filter_info *mfilter = NULL;
2472 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2473 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2474 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2475 " ethertype filter.", efilter->ether_type);
2479 if (efilter->queue >= bp->rx_nr_rings) {
2480 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2485 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2486 vnic = &bp->vnic_info[efilter->queue];
2488 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2493 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2494 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2495 if ((!memcmp(efilter->mac_addr.addr_bytes,
2496 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2498 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2499 mfilter->ethertype == efilter->ether_type)) {
2505 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2506 if ((!memcmp(efilter->mac_addr.addr_bytes,
2507 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2508 mfilter->ethertype == efilter->ether_type &&
2510 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2524 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2525 enum rte_filter_op filter_op,
2528 struct bnxt *bp = dev->data->dev_private;
2529 struct rte_eth_ethertype_filter *efilter =
2530 (struct rte_eth_ethertype_filter *)arg;
2531 struct bnxt_filter_info *bfilter, *filter1;
2532 struct bnxt_vnic_info *vnic, *vnic0;
2535 if (filter_op == RTE_ETH_FILTER_NOP)
2539 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2544 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2545 vnic = &bp->vnic_info[efilter->queue];
2547 switch (filter_op) {
2548 case RTE_ETH_FILTER_ADD:
2549 bnxt_match_and_validate_ether_filter(bp, efilter,
2554 bfilter = bnxt_get_unused_filter(bp);
2555 if (bfilter == NULL) {
2557 "Not enough resources for a new filter.\n");
2560 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2561 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2562 RTE_ETHER_ADDR_LEN);
2563 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2564 RTE_ETHER_ADDR_LEN);
2565 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2566 bfilter->ethertype = efilter->ether_type;
2567 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2569 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2570 if (filter1 == NULL) {
2575 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2576 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2578 bfilter->dst_id = vnic->fw_vnic_id;
2580 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2582 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2585 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2588 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2590 case RTE_ETH_FILTER_DELETE:
2591 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2593 if (ret == -EEXIST) {
2594 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2596 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2598 bnxt_free_filter(bp, filter1);
2599 } else if (ret == 0) {
2600 PMD_DRV_LOG(ERR, "No matching filter found\n");
2604 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2610 bnxt_free_filter(bp, bfilter);
2616 parse_ntuple_filter(struct bnxt *bp,
2617 struct rte_eth_ntuple_filter *nfilter,
2618 struct bnxt_filter_info *bfilter)
2622 if (nfilter->queue >= bp->rx_nr_rings) {
2623 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2627 switch (nfilter->dst_port_mask) {
2629 bfilter->dst_port_mask = -1;
2630 bfilter->dst_port = nfilter->dst_port;
2631 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2632 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2635 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2639 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2640 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2642 switch (nfilter->proto_mask) {
2644 if (nfilter->proto == 17) /* IPPROTO_UDP */
2645 bfilter->ip_protocol = 17;
2646 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2647 bfilter->ip_protocol = 6;
2650 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2653 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2657 switch (nfilter->dst_ip_mask) {
2659 bfilter->dst_ipaddr_mask[0] = -1;
2660 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2661 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2662 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2665 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2669 switch (nfilter->src_ip_mask) {
2671 bfilter->src_ipaddr_mask[0] = -1;
2672 bfilter->src_ipaddr[0] = nfilter->src_ip;
2673 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2674 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2677 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2681 switch (nfilter->src_port_mask) {
2683 bfilter->src_port_mask = -1;
2684 bfilter->src_port = nfilter->src_port;
2685 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2686 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2689 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2693 bfilter->enables = en;
2697 static struct bnxt_filter_info*
2698 bnxt_match_ntuple_filter(struct bnxt *bp,
2699 struct bnxt_filter_info *bfilter,
2700 struct bnxt_vnic_info **mvnic)
2702 struct bnxt_filter_info *mfilter = NULL;
2705 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2706 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2707 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2708 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2709 bfilter->src_ipaddr_mask[0] ==
2710 mfilter->src_ipaddr_mask[0] &&
2711 bfilter->src_port == mfilter->src_port &&
2712 bfilter->src_port_mask == mfilter->src_port_mask &&
2713 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2714 bfilter->dst_ipaddr_mask[0] ==
2715 mfilter->dst_ipaddr_mask[0] &&
2716 bfilter->dst_port == mfilter->dst_port &&
2717 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2718 bfilter->flags == mfilter->flags &&
2719 bfilter->enables == mfilter->enables) {
2730 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2731 struct rte_eth_ntuple_filter *nfilter,
2732 enum rte_filter_op filter_op)
2734 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2735 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2738 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2739 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2743 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2744 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2748 bfilter = bnxt_get_unused_filter(bp);
2749 if (bfilter == NULL) {
2751 "Not enough resources for a new filter.\n");
2754 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2758 vnic = &bp->vnic_info[nfilter->queue];
2759 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2760 filter1 = STAILQ_FIRST(&vnic0->filter);
2761 if (filter1 == NULL) {
2766 bfilter->dst_id = vnic->fw_vnic_id;
2767 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2769 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2770 bfilter->ethertype = 0x800;
2771 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2773 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2775 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2776 bfilter->dst_id == mfilter->dst_id) {
2777 PMD_DRV_LOG(ERR, "filter exists.\n");
2780 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2781 bfilter->dst_id != mfilter->dst_id) {
2782 mfilter->dst_id = vnic->fw_vnic_id;
2783 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2784 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2785 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2786 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2787 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2790 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2791 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2796 if (filter_op == RTE_ETH_FILTER_ADD) {
2797 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2798 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2801 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2803 if (mfilter == NULL) {
2804 /* This should not happen. But for Coverity! */
2808 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2810 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2811 bnxt_free_filter(bp, mfilter);
2812 bnxt_free_filter(bp, bfilter);
2817 bnxt_free_filter(bp, bfilter);
2822 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2823 enum rte_filter_op filter_op,
2826 struct bnxt *bp = dev->data->dev_private;
2829 if (filter_op == RTE_ETH_FILTER_NOP)
2833 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2838 switch (filter_op) {
2839 case RTE_ETH_FILTER_ADD:
2840 ret = bnxt_cfg_ntuple_filter(bp,
2841 (struct rte_eth_ntuple_filter *)arg,
2844 case RTE_ETH_FILTER_DELETE:
2845 ret = bnxt_cfg_ntuple_filter(bp,
2846 (struct rte_eth_ntuple_filter *)arg,
2850 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2858 bnxt_parse_fdir_filter(struct bnxt *bp,
2859 struct rte_eth_fdir_filter *fdir,
2860 struct bnxt_filter_info *filter)
2862 enum rte_fdir_mode fdir_mode =
2863 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2864 struct bnxt_vnic_info *vnic0, *vnic;
2865 struct bnxt_filter_info *filter1;
2869 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2872 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2873 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2875 switch (fdir->input.flow_type) {
2876 case RTE_ETH_FLOW_IPV4:
2877 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2879 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2880 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2881 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2882 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2883 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2884 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2885 filter->ip_addr_type =
2886 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2887 filter->src_ipaddr_mask[0] = 0xffffffff;
2888 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2889 filter->dst_ipaddr_mask[0] = 0xffffffff;
2890 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2891 filter->ethertype = 0x800;
2892 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2894 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2895 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2896 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2897 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2898 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2899 filter->dst_port_mask = 0xffff;
2900 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2901 filter->src_port_mask = 0xffff;
2902 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2903 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2904 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2905 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2906 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2907 filter->ip_protocol = 6;
2908 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2909 filter->ip_addr_type =
2910 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2911 filter->src_ipaddr_mask[0] = 0xffffffff;
2912 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2913 filter->dst_ipaddr_mask[0] = 0xffffffff;
2914 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2915 filter->ethertype = 0x800;
2916 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2918 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2919 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2920 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2921 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2922 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2923 filter->dst_port_mask = 0xffff;
2924 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2925 filter->src_port_mask = 0xffff;
2926 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2927 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2928 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2929 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2930 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2931 filter->ip_protocol = 17;
2932 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2933 filter->ip_addr_type =
2934 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2935 filter->src_ipaddr_mask[0] = 0xffffffff;
2936 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2937 filter->dst_ipaddr_mask[0] = 0xffffffff;
2938 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2939 filter->ethertype = 0x800;
2940 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2942 case RTE_ETH_FLOW_IPV6:
2943 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2945 filter->ip_addr_type =
2946 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2947 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2948 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2949 rte_memcpy(filter->src_ipaddr,
2950 fdir->input.flow.ipv6_flow.src_ip, 16);
2951 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2952 rte_memcpy(filter->dst_ipaddr,
2953 fdir->input.flow.ipv6_flow.dst_ip, 16);
2954 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2955 memset(filter->dst_ipaddr_mask, 0xff, 16);
2956 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2957 memset(filter->src_ipaddr_mask, 0xff, 16);
2958 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2959 filter->ethertype = 0x86dd;
2960 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2962 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2963 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2964 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2965 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2966 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2967 filter->dst_port_mask = 0xffff;
2968 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2969 filter->src_port_mask = 0xffff;
2970 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2971 filter->ip_addr_type =
2972 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2973 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2974 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2975 rte_memcpy(filter->src_ipaddr,
2976 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2977 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2978 rte_memcpy(filter->dst_ipaddr,
2979 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2980 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2981 memset(filter->dst_ipaddr_mask, 0xff, 16);
2982 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2983 memset(filter->src_ipaddr_mask, 0xff, 16);
2984 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2985 filter->ethertype = 0x86dd;
2986 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2988 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2989 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2990 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2991 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2992 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2993 filter->dst_port_mask = 0xffff;
2994 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2995 filter->src_port_mask = 0xffff;
2996 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2997 filter->ip_addr_type =
2998 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2999 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3000 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3001 rte_memcpy(filter->src_ipaddr,
3002 fdir->input.flow.udp6_flow.ip.src_ip, 16);
3003 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3004 rte_memcpy(filter->dst_ipaddr,
3005 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3006 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3007 memset(filter->dst_ipaddr_mask, 0xff, 16);
3008 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3009 memset(filter->src_ipaddr_mask, 0xff, 16);
3010 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3011 filter->ethertype = 0x86dd;
3012 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3014 case RTE_ETH_FLOW_L2_PAYLOAD:
3015 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3016 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3018 case RTE_ETH_FLOW_VXLAN:
3019 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3021 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3022 filter->tunnel_type =
3023 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3024 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3026 case RTE_ETH_FLOW_NVGRE:
3027 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3029 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3030 filter->tunnel_type =
3031 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3032 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3034 case RTE_ETH_FLOW_UNKNOWN:
3035 case RTE_ETH_FLOW_RAW:
3036 case RTE_ETH_FLOW_FRAG_IPV4:
3037 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3038 case RTE_ETH_FLOW_FRAG_IPV6:
3039 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3040 case RTE_ETH_FLOW_IPV6_EX:
3041 case RTE_ETH_FLOW_IPV6_TCP_EX:
3042 case RTE_ETH_FLOW_IPV6_UDP_EX:
3043 case RTE_ETH_FLOW_GENEVE:
3049 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3050 vnic = &bp->vnic_info[fdir->action.rx_queue];
3052 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3056 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3057 rte_memcpy(filter->dst_macaddr,
3058 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3059 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3062 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3063 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3064 filter1 = STAILQ_FIRST(&vnic0->filter);
3065 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3067 filter->dst_id = vnic->fw_vnic_id;
3068 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3069 if (filter->dst_macaddr[i] == 0x00)
3070 filter1 = STAILQ_FIRST(&vnic0->filter);
3072 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3075 if (filter1 == NULL)
3078 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3079 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3081 filter->enables = en;
3086 static struct bnxt_filter_info *
3087 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3088 struct bnxt_vnic_info **mvnic)
3090 struct bnxt_filter_info *mf = NULL;
3093 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3094 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3096 STAILQ_FOREACH(mf, &vnic->filter, next) {
3097 if (mf->filter_type == nf->filter_type &&
3098 mf->flags == nf->flags &&
3099 mf->src_port == nf->src_port &&
3100 mf->src_port_mask == nf->src_port_mask &&
3101 mf->dst_port == nf->dst_port &&
3102 mf->dst_port_mask == nf->dst_port_mask &&
3103 mf->ip_protocol == nf->ip_protocol &&
3104 mf->ip_addr_type == nf->ip_addr_type &&
3105 mf->ethertype == nf->ethertype &&
3106 mf->vni == nf->vni &&
3107 mf->tunnel_type == nf->tunnel_type &&
3108 mf->l2_ovlan == nf->l2_ovlan &&
3109 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3110 mf->l2_ivlan == nf->l2_ivlan &&
3111 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3112 !memcmp(mf->l2_addr, nf->l2_addr,
3113 RTE_ETHER_ADDR_LEN) &&
3114 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3115 RTE_ETHER_ADDR_LEN) &&
3116 !memcmp(mf->src_macaddr, nf->src_macaddr,
3117 RTE_ETHER_ADDR_LEN) &&
3118 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3119 RTE_ETHER_ADDR_LEN) &&
3120 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3121 sizeof(nf->src_ipaddr)) &&
3122 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3123 sizeof(nf->src_ipaddr_mask)) &&
3124 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3125 sizeof(nf->dst_ipaddr)) &&
3126 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3127 sizeof(nf->dst_ipaddr_mask))) {
3138 bnxt_fdir_filter(struct rte_eth_dev *dev,
3139 enum rte_filter_op filter_op,
3142 struct bnxt *bp = dev->data->dev_private;
3143 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3144 struct bnxt_filter_info *filter, *match;
3145 struct bnxt_vnic_info *vnic, *mvnic;
3148 if (filter_op == RTE_ETH_FILTER_NOP)
3151 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3154 switch (filter_op) {
3155 case RTE_ETH_FILTER_ADD:
3156 case RTE_ETH_FILTER_DELETE:
3158 filter = bnxt_get_unused_filter(bp);
3159 if (filter == NULL) {
3161 "Not enough resources for a new flow.\n");
3165 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3168 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3170 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3171 vnic = &bp->vnic_info[0];
3173 vnic = &bp->vnic_info[fdir->action.rx_queue];
3175 match = bnxt_match_fdir(bp, filter, &mvnic);
3176 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3177 if (match->dst_id == vnic->fw_vnic_id) {
3178 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3182 match->dst_id = vnic->fw_vnic_id;
3183 ret = bnxt_hwrm_set_ntuple_filter(bp,
3186 STAILQ_REMOVE(&mvnic->filter, match,
3187 bnxt_filter_info, next);
3188 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3190 "Filter with matching pattern exist\n");
3192 "Updated it to new destination q\n");
3196 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3197 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3202 if (filter_op == RTE_ETH_FILTER_ADD) {
3203 ret = bnxt_hwrm_set_ntuple_filter(bp,
3208 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3210 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3211 STAILQ_REMOVE(&vnic->filter, match,
3212 bnxt_filter_info, next);
3213 bnxt_free_filter(bp, match);
3214 bnxt_free_filter(bp, filter);
3217 case RTE_ETH_FILTER_FLUSH:
3218 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3219 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3221 STAILQ_FOREACH(filter, &vnic->filter, next) {
3222 if (filter->filter_type ==
3223 HWRM_CFA_NTUPLE_FILTER) {
3225 bnxt_hwrm_clear_ntuple_filter(bp,
3227 STAILQ_REMOVE(&vnic->filter, filter,
3228 bnxt_filter_info, next);
3233 case RTE_ETH_FILTER_UPDATE:
3234 case RTE_ETH_FILTER_STATS:
3235 case RTE_ETH_FILTER_INFO:
3236 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3239 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3246 bnxt_free_filter(bp, filter);
3251 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3252 enum rte_filter_type filter_type,
3253 enum rte_filter_op filter_op, void *arg)
3257 ret = is_bnxt_in_error(dev->data->dev_private);
3261 switch (filter_type) {
3262 case RTE_ETH_FILTER_TUNNEL:
3264 "filter type: %d: To be implemented\n", filter_type);
3266 case RTE_ETH_FILTER_FDIR:
3267 ret = bnxt_fdir_filter(dev, filter_op, arg);
3269 case RTE_ETH_FILTER_NTUPLE:
3270 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3272 case RTE_ETH_FILTER_ETHERTYPE:
3273 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3275 case RTE_ETH_FILTER_GENERIC:
3276 if (filter_op != RTE_ETH_FILTER_GET)
3278 *(const void **)arg = &bnxt_flow_ops;
3282 "Filter type (%d) not supported", filter_type);
3289 static const uint32_t *
3290 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3292 static const uint32_t ptypes[] = {
3293 RTE_PTYPE_L2_ETHER_VLAN,
3294 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3295 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3299 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3300 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3301 RTE_PTYPE_INNER_L4_ICMP,
3302 RTE_PTYPE_INNER_L4_TCP,
3303 RTE_PTYPE_INNER_L4_UDP,
3307 if (!dev->rx_pkt_burst)
3313 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3316 uint32_t reg_base = *reg_arr & 0xfffff000;
3320 for (i = 0; i < count; i++) {
3321 if ((reg_arr[i] & 0xfffff000) != reg_base)
3324 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3325 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3329 static int bnxt_map_ptp_regs(struct bnxt *bp)
3331 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3335 reg_arr = ptp->rx_regs;
3336 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3340 reg_arr = ptp->tx_regs;
3341 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3345 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3346 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3348 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3349 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3354 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3356 rte_write32(0, (uint8_t *)bp->bar0 +
3357 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3358 rte_write32(0, (uint8_t *)bp->bar0 +
3359 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3362 static uint64_t bnxt_cc_read(struct bnxt *bp)
3366 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3367 BNXT_GRCPF_REG_SYNC_TIME));
3368 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3369 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3373 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3375 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3378 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3379 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3380 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3383 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3384 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3385 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3386 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3387 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3388 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3393 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3395 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3396 struct bnxt_pf_info *pf = &bp->pf;
3403 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3404 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3405 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3408 port_id = pf->port_id;
3409 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3410 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3412 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3413 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3414 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3415 /* bnxt_clr_rx_ts(bp); TBD */
3419 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3420 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3421 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3422 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3428 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3431 struct bnxt *bp = dev->data->dev_private;
3432 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3437 ns = rte_timespec_to_ns(ts);
3438 /* Set the timecounters to a new value. */
3445 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3447 struct bnxt *bp = dev->data->dev_private;
3448 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3449 uint64_t ns, systime_cycles = 0;
3455 if (BNXT_CHIP_THOR(bp))
3456 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3459 systime_cycles = bnxt_cc_read(bp);
3461 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3462 *ts = rte_ns_to_timespec(ns);
3467 bnxt_timesync_enable(struct rte_eth_dev *dev)
3469 struct bnxt *bp = dev->data->dev_private;
3470 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3478 ptp->tx_tstamp_en = 1;
3479 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3481 rc = bnxt_hwrm_ptp_cfg(bp);
3485 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3486 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3487 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3489 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3490 ptp->tc.cc_shift = shift;
3491 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3493 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3494 ptp->rx_tstamp_tc.cc_shift = shift;
3495 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3497 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3498 ptp->tx_tstamp_tc.cc_shift = shift;
3499 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3501 if (!BNXT_CHIP_THOR(bp))
3502 bnxt_map_ptp_regs(bp);
3508 bnxt_timesync_disable(struct rte_eth_dev *dev)
3510 struct bnxt *bp = dev->data->dev_private;
3511 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3517 ptp->tx_tstamp_en = 0;
3520 bnxt_hwrm_ptp_cfg(bp);
3522 if (!BNXT_CHIP_THOR(bp))
3523 bnxt_unmap_ptp_regs(bp);
3529 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3530 struct timespec *timestamp,
3531 uint32_t flags __rte_unused)
3533 struct bnxt *bp = dev->data->dev_private;
3534 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3535 uint64_t rx_tstamp_cycles = 0;
3541 if (BNXT_CHIP_THOR(bp))
3542 rx_tstamp_cycles = ptp->rx_timestamp;
3544 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3546 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3547 *timestamp = rte_ns_to_timespec(ns);
3552 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3553 struct timespec *timestamp)
3555 struct bnxt *bp = dev->data->dev_private;
3556 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3557 uint64_t tx_tstamp_cycles = 0;
3564 if (BNXT_CHIP_THOR(bp))
3565 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3568 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3570 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3571 *timestamp = rte_ns_to_timespec(ns);
3577 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3579 struct bnxt *bp = dev->data->dev_private;
3580 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3585 ptp->tc.nsec += delta;
3591 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3593 struct bnxt *bp = dev->data->dev_private;
3595 uint32_t dir_entries;
3596 uint32_t entry_length;
3598 rc = is_bnxt_in_error(bp);
3602 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3603 bp->pdev->addr.domain, bp->pdev->addr.bus,
3604 bp->pdev->addr.devid, bp->pdev->addr.function);
3606 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3610 return dir_entries * entry_length;
3614 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3615 struct rte_dev_eeprom_info *in_eeprom)
3617 struct bnxt *bp = dev->data->dev_private;
3622 rc = is_bnxt_in_error(bp);
3626 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3627 bp->pdev->addr.domain, bp->pdev->addr.bus,
3628 bp->pdev->addr.devid, bp->pdev->addr.function,
3629 in_eeprom->offset, in_eeprom->length);
3631 if (in_eeprom->offset == 0) /* special offset value to get directory */
3632 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3635 index = in_eeprom->offset >> 24;
3636 offset = in_eeprom->offset & 0xffffff;
3639 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3640 in_eeprom->length, in_eeprom->data);
3645 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3648 case BNX_DIR_TYPE_CHIMP_PATCH:
3649 case BNX_DIR_TYPE_BOOTCODE:
3650 case BNX_DIR_TYPE_BOOTCODE_2:
3651 case BNX_DIR_TYPE_APE_FW:
3652 case BNX_DIR_TYPE_APE_PATCH:
3653 case BNX_DIR_TYPE_KONG_FW:
3654 case BNX_DIR_TYPE_KONG_PATCH:
3655 case BNX_DIR_TYPE_BONO_FW:
3656 case BNX_DIR_TYPE_BONO_PATCH:
3664 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3667 case BNX_DIR_TYPE_AVS:
3668 case BNX_DIR_TYPE_EXP_ROM_MBA:
3669 case BNX_DIR_TYPE_PCIE:
3670 case BNX_DIR_TYPE_TSCF_UCODE:
3671 case BNX_DIR_TYPE_EXT_PHY:
3672 case BNX_DIR_TYPE_CCM:
3673 case BNX_DIR_TYPE_ISCSI_BOOT:
3674 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3675 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3683 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3685 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3686 bnxt_dir_type_is_other_exec_format(dir_type);
3690 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3691 struct rte_dev_eeprom_info *in_eeprom)
3693 struct bnxt *bp = dev->data->dev_private;
3694 uint8_t index, dir_op;
3695 uint16_t type, ext, ordinal, attr;
3698 rc = is_bnxt_in_error(bp);
3702 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3703 bp->pdev->addr.domain, bp->pdev->addr.bus,
3704 bp->pdev->addr.devid, bp->pdev->addr.function,
3705 in_eeprom->offset, in_eeprom->length);
3708 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3712 type = in_eeprom->magic >> 16;
3714 if (type == 0xffff) { /* special value for directory operations */
3715 index = in_eeprom->magic & 0xff;
3716 dir_op = in_eeprom->magic >> 8;
3720 case 0x0e: /* erase */
3721 if (in_eeprom->offset != ~in_eeprom->magic)
3723 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3729 /* Create or re-write an NVM item: */
3730 if (bnxt_dir_type_is_executable(type) == true)
3732 ext = in_eeprom->magic & 0xffff;
3733 ordinal = in_eeprom->offset >> 16;
3734 attr = in_eeprom->offset & 0xffff;
3736 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3737 in_eeprom->data, in_eeprom->length);
3744 static const struct eth_dev_ops bnxt_dev_ops = {
3745 .dev_infos_get = bnxt_dev_info_get_op,
3746 .dev_close = bnxt_dev_close_op,
3747 .dev_configure = bnxt_dev_configure_op,
3748 .dev_start = bnxt_dev_start_op,
3749 .dev_stop = bnxt_dev_stop_op,
3750 .dev_set_link_up = bnxt_dev_set_link_up_op,
3751 .dev_set_link_down = bnxt_dev_set_link_down_op,
3752 .stats_get = bnxt_stats_get_op,
3753 .stats_reset = bnxt_stats_reset_op,
3754 .rx_queue_setup = bnxt_rx_queue_setup_op,
3755 .rx_queue_release = bnxt_rx_queue_release_op,
3756 .tx_queue_setup = bnxt_tx_queue_setup_op,
3757 .tx_queue_release = bnxt_tx_queue_release_op,
3758 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3759 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3760 .reta_update = bnxt_reta_update_op,
3761 .reta_query = bnxt_reta_query_op,
3762 .rss_hash_update = bnxt_rss_hash_update_op,
3763 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3764 .link_update = bnxt_link_update_op,
3765 .promiscuous_enable = bnxt_promiscuous_enable_op,
3766 .promiscuous_disable = bnxt_promiscuous_disable_op,
3767 .allmulticast_enable = bnxt_allmulticast_enable_op,
3768 .allmulticast_disable = bnxt_allmulticast_disable_op,
3769 .mac_addr_add = bnxt_mac_addr_add_op,
3770 .mac_addr_remove = bnxt_mac_addr_remove_op,
3771 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3772 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3773 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3774 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3775 .vlan_filter_set = bnxt_vlan_filter_set_op,
3776 .vlan_offload_set = bnxt_vlan_offload_set_op,
3777 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3778 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3779 .mtu_set = bnxt_mtu_set_op,
3780 .mac_addr_set = bnxt_set_default_mac_addr_op,
3781 .xstats_get = bnxt_dev_xstats_get_op,
3782 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3783 .xstats_reset = bnxt_dev_xstats_reset_op,
3784 .fw_version_get = bnxt_fw_version_get,
3785 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3786 .rxq_info_get = bnxt_rxq_info_get_op,
3787 .txq_info_get = bnxt_txq_info_get_op,
3788 .dev_led_on = bnxt_dev_led_on_op,
3789 .dev_led_off = bnxt_dev_led_off_op,
3790 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3791 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3792 .rx_queue_count = bnxt_rx_queue_count_op,
3793 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3794 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3795 .rx_queue_start = bnxt_rx_queue_start,
3796 .rx_queue_stop = bnxt_rx_queue_stop,
3797 .tx_queue_start = bnxt_tx_queue_start,
3798 .tx_queue_stop = bnxt_tx_queue_stop,
3799 .filter_ctrl = bnxt_filter_ctrl_op,
3800 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3801 .get_eeprom_length = bnxt_get_eeprom_length_op,
3802 .get_eeprom = bnxt_get_eeprom_op,
3803 .set_eeprom = bnxt_set_eeprom_op,
3804 .timesync_enable = bnxt_timesync_enable,
3805 .timesync_disable = bnxt_timesync_disable,
3806 .timesync_read_time = bnxt_timesync_read_time,
3807 .timesync_write_time = bnxt_timesync_write_time,
3808 .timesync_adjust_time = bnxt_timesync_adjust_time,
3809 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3810 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3813 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3817 /* Only pre-map the reset GRC registers using window 3 */
3818 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3819 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3821 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3826 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3828 struct bnxt_error_recovery_info *info = bp->recovery_info;
3829 uint32_t reg_base = 0xffffffff;
3832 /* Only pre-map the monitoring GRC registers using window 2 */
3833 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3834 uint32_t reg = info->status_regs[i];
3836 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3839 if (reg_base == 0xffffffff)
3840 reg_base = reg & 0xfffff000;
3841 if ((reg & 0xfffff000) != reg_base)
3844 /* Use mask 0xffc as the Lower 2 bits indicates
3845 * address space location
3847 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3851 if (reg_base == 0xffffffff)
3854 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3855 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3860 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3862 struct bnxt_error_recovery_info *info = bp->recovery_info;
3863 uint32_t delay = info->delay_after_reset[index];
3864 uint32_t val = info->reset_reg_val[index];
3865 uint32_t reg = info->reset_reg[index];
3866 uint32_t type, offset;
3868 type = BNXT_FW_STATUS_REG_TYPE(reg);
3869 offset = BNXT_FW_STATUS_REG_OFF(reg);
3872 case BNXT_FW_STATUS_REG_TYPE_CFG:
3873 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3875 case BNXT_FW_STATUS_REG_TYPE_GRC:
3876 offset = bnxt_map_reset_regs(bp, offset);
3877 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3879 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3880 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3883 /* wait on a specific interval of time until core reset is complete */
3885 rte_delay_ms(delay);
3888 static void bnxt_dev_cleanup(struct bnxt *bp)
3890 bnxt_set_hwrm_link_config(bp, false);
3891 bp->link_info.link_up = 0;
3892 if (bp->dev_stopped == 0)
3893 bnxt_dev_stop_op(bp->eth_dev);
3895 bnxt_uninit_resources(bp, true);
3898 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3900 struct rte_eth_dev *dev = bp->eth_dev;
3901 struct rte_vlan_filter_conf *vfc;
3905 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3906 vfc = &dev->data->vlan_filter_conf;
3907 vidx = vlan_id / 64;
3908 vbit = vlan_id % 64;
3910 /* Each bit corresponds to a VLAN id */
3911 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3912 rc = bnxt_add_vlan_filter(bp, vlan_id);
3921 static int bnxt_restore_mac_filters(struct bnxt *bp)
3923 struct rte_eth_dev *dev = bp->eth_dev;
3924 struct rte_eth_dev_info dev_info;
3925 struct rte_ether_addr *addr;
3931 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
3934 rc = bnxt_dev_info_get_op(dev, &dev_info);
3938 /* replay MAC address configuration */
3939 for (i = 1; i < dev_info.max_mac_addrs; i++) {
3940 addr = &dev->data->mac_addrs[i];
3942 /* skip zero address */
3943 if (rte_is_zero_ether_addr(addr))
3947 pool_mask = dev->data->mac_pool_sel[i];
3950 if (pool_mask & 1ULL) {
3951 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3957 } while (pool_mask);
3963 static int bnxt_restore_filters(struct bnxt *bp)
3965 struct rte_eth_dev *dev = bp->eth_dev;
3968 if (dev->data->all_multicast)
3969 ret = bnxt_allmulticast_enable_op(dev);
3970 if (dev->data->promiscuous)
3971 ret = bnxt_promiscuous_enable_op(dev);
3973 ret = bnxt_restore_mac_filters(bp);
3977 ret = bnxt_restore_vlan_filters(bp);
3978 /* TODO restore other filters as well */
3982 static void bnxt_dev_recover(void *arg)
3984 struct bnxt *bp = arg;
3985 int timeout = bp->fw_reset_max_msecs;
3988 /* Clear Error flag so that device re-init should happen */
3989 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3992 rc = bnxt_hwrm_ver_get(bp);
3995 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3996 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3997 } while (rc && timeout);
4000 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4004 rc = bnxt_init_resources(bp, true);
4007 "Failed to initialize resources after reset\n");
4010 /* clear reset flag as the device is initialized now */
4011 bp->flags &= ~BNXT_FLAG_FW_RESET;
4013 rc = bnxt_dev_start_op(bp->eth_dev);
4015 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4019 rc = bnxt_restore_filters(bp);
4023 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4026 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4027 bnxt_uninit_resources(bp, false);
4028 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4031 void bnxt_dev_reset_and_resume(void *arg)
4033 struct bnxt *bp = arg;
4036 bnxt_dev_cleanup(bp);
4038 bnxt_wait_for_device_shutdown(bp);
4040 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4041 bnxt_dev_recover, (void *)bp);
4043 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4046 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4048 struct bnxt_error_recovery_info *info = bp->recovery_info;
4049 uint32_t reg = info->status_regs[index];
4050 uint32_t type, offset, val = 0;
4052 type = BNXT_FW_STATUS_REG_TYPE(reg);
4053 offset = BNXT_FW_STATUS_REG_OFF(reg);
4056 case BNXT_FW_STATUS_REG_TYPE_CFG:
4057 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4059 case BNXT_FW_STATUS_REG_TYPE_GRC:
4060 offset = info->mapped_status_regs[index];
4062 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4063 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4071 static int bnxt_fw_reset_all(struct bnxt *bp)
4073 struct bnxt_error_recovery_info *info = bp->recovery_info;
4077 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4078 /* Reset through master function driver */
4079 for (i = 0; i < info->reg_array_cnt; i++)
4080 bnxt_write_fw_reset_reg(bp, i);
4081 /* Wait for time specified by FW after triggering reset */
4082 rte_delay_ms(info->master_func_wait_period_after_reset);
4083 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4084 /* Reset with the help of Kong processor */
4085 rc = bnxt_hwrm_fw_reset(bp);
4087 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4093 static void bnxt_fw_reset_cb(void *arg)
4095 struct bnxt *bp = arg;
4096 struct bnxt_error_recovery_info *info = bp->recovery_info;
4099 /* Only Master function can do FW reset */
4100 if (bnxt_is_master_func(bp) &&
4101 bnxt_is_recovery_enabled(bp)) {
4102 rc = bnxt_fw_reset_all(bp);
4104 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4109 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4110 * EXCEPTION_FATAL_ASYNC event to all the functions
4111 * (including MASTER FUNC). After receiving this Async, all the active
4112 * drivers should treat this case as FW initiated recovery
4114 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4115 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4116 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4118 /* To recover from error */
4119 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4124 /* Driver should poll FW heartbeat, reset_counter with the frequency
4125 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4126 * When the driver detects heartbeat stop or change in reset_counter,
4127 * it has to trigger a reset to recover from the error condition.
4128 * A “master PF” is the function who will have the privilege to
4129 * initiate the chimp reset. The master PF will be elected by the
4130 * firmware and will be notified through async message.
4132 static void bnxt_check_fw_health(void *arg)
4134 struct bnxt *bp = arg;
4135 struct bnxt_error_recovery_info *info = bp->recovery_info;
4136 uint32_t val = 0, wait_msec;
4138 if (!info || !bnxt_is_recovery_enabled(bp) ||
4139 is_bnxt_in_error(bp))
4142 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4143 if (val == info->last_heart_beat)
4146 info->last_heart_beat = val;
4148 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4149 if (val != info->last_reset_counter)
4152 info->last_reset_counter = val;
4154 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4155 bnxt_check_fw_health, (void *)bp);
4159 /* Stop DMA to/from device */
4160 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4161 bp->flags |= BNXT_FLAG_FW_RESET;
4163 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4165 if (bnxt_is_master_func(bp))
4166 wait_msec = info->master_func_wait_period;
4168 wait_msec = info->normal_func_wait_period;
4170 rte_eal_alarm_set(US_PER_MS * wait_msec,
4171 bnxt_fw_reset_cb, (void *)bp);
4174 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4176 uint32_t polling_freq;
4178 if (!bnxt_is_recovery_enabled(bp))
4181 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4184 polling_freq = bp->recovery_info->driver_polling_freq;
4186 rte_eal_alarm_set(US_PER_MS * polling_freq,
4187 bnxt_check_fw_health, (void *)bp);
4188 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4191 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4193 if (!bnxt_is_recovery_enabled(bp))
4196 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4197 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4200 static bool bnxt_vf_pciid(uint16_t device_id)
4202 switch (device_id) {
4203 case BROADCOM_DEV_ID_57304_VF:
4204 case BROADCOM_DEV_ID_57406_VF:
4205 case BROADCOM_DEV_ID_5731X_VF:
4206 case BROADCOM_DEV_ID_5741X_VF:
4207 case BROADCOM_DEV_ID_57414_VF:
4208 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4209 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4210 case BROADCOM_DEV_ID_58802_VF:
4211 case BROADCOM_DEV_ID_57500_VF1:
4212 case BROADCOM_DEV_ID_57500_VF2:
4220 static bool bnxt_thor_device(uint16_t device_id)
4222 switch (device_id) {
4223 case BROADCOM_DEV_ID_57508:
4224 case BROADCOM_DEV_ID_57504:
4225 case BROADCOM_DEV_ID_57502:
4226 case BROADCOM_DEV_ID_57508_MF1:
4227 case BROADCOM_DEV_ID_57504_MF1:
4228 case BROADCOM_DEV_ID_57502_MF1:
4229 case BROADCOM_DEV_ID_57508_MF2:
4230 case BROADCOM_DEV_ID_57504_MF2:
4231 case BROADCOM_DEV_ID_57502_MF2:
4232 case BROADCOM_DEV_ID_57500_VF1:
4233 case BROADCOM_DEV_ID_57500_VF2:
4241 bool bnxt_stratus_device(struct bnxt *bp)
4243 uint16_t device_id = bp->pdev->id.device_id;
4245 switch (device_id) {
4246 case BROADCOM_DEV_ID_STRATUS_NIC:
4247 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4248 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4256 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4258 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4259 struct bnxt *bp = eth_dev->data->dev_private;
4261 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4262 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4263 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4264 if (!bp->bar0 || !bp->doorbell_base) {
4265 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4269 bp->eth_dev = eth_dev;
4275 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4276 struct bnxt_ctx_pg_info *ctx_pg,
4281 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4282 const struct rte_memzone *mz = NULL;
4283 char mz_name[RTE_MEMZONE_NAMESIZE];
4284 rte_iova_t mz_phys_addr;
4285 uint64_t valid_bits = 0;
4292 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4294 rmem->page_size = BNXT_PAGE_SIZE;
4295 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4296 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4297 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4299 valid_bits = PTU_PTE_VALID;
4301 if (rmem->nr_pages > 1) {
4302 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4303 "bnxt_ctx_pg_tbl%s_%x_%d",
4304 suffix, idx, bp->eth_dev->data->port_id);
4305 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4306 mz = rte_memzone_lookup(mz_name);
4308 mz = rte_memzone_reserve_aligned(mz_name,
4312 RTE_MEMZONE_SIZE_HINT_ONLY |
4313 RTE_MEMZONE_IOVA_CONTIG,
4319 memset(mz->addr, 0, mz->len);
4320 mz_phys_addr = mz->iova;
4322 rmem->pg_tbl = mz->addr;
4323 rmem->pg_tbl_map = mz_phys_addr;
4324 rmem->pg_tbl_mz = mz;
4327 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4328 suffix, idx, bp->eth_dev->data->port_id);
4329 mz = rte_memzone_lookup(mz_name);
4331 mz = rte_memzone_reserve_aligned(mz_name,
4335 RTE_MEMZONE_SIZE_HINT_ONLY |
4336 RTE_MEMZONE_IOVA_CONTIG,
4342 memset(mz->addr, 0, mz->len);
4343 mz_phys_addr = mz->iova;
4345 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4346 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4347 rmem->dma_arr[i] = mz_phys_addr + sz;
4349 if (rmem->nr_pages > 1) {
4350 if (i == rmem->nr_pages - 2 &&
4351 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4352 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4353 else if (i == rmem->nr_pages - 1 &&
4354 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4355 valid_bits |= PTU_PTE_LAST;
4357 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4363 if (rmem->vmem_size)
4364 rmem->vmem = (void **)mz->addr;
4365 rmem->dma_arr[0] = mz_phys_addr;
4369 static void bnxt_free_ctx_mem(struct bnxt *bp)
4373 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4376 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4377 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4378 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4379 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4380 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4381 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4382 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4383 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4384 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4385 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4386 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4388 for (i = 0; i < BNXT_MAX_Q; i++) {
4389 if (bp->ctx->tqm_mem[i])
4390 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4397 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4399 #define min_t(type, x, y) ({ \
4400 type __min1 = (x); \
4401 type __min2 = (y); \
4402 __min1 < __min2 ? __min1 : __min2; })
4404 #define max_t(type, x, y) ({ \
4405 type __max1 = (x); \
4406 type __max2 = (y); \
4407 __max1 > __max2 ? __max1 : __max2; })
4409 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4411 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4413 struct bnxt_ctx_pg_info *ctx_pg;
4414 struct bnxt_ctx_mem_info *ctx;
4415 uint32_t mem_size, ena, entries;
4418 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4420 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4424 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4427 ctx_pg = &ctx->qp_mem;
4428 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4429 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4430 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4434 ctx_pg = &ctx->srq_mem;
4435 ctx_pg->entries = ctx->srq_max_l2_entries;
4436 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4437 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4441 ctx_pg = &ctx->cq_mem;
4442 ctx_pg->entries = ctx->cq_max_l2_entries;
4443 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4444 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4448 ctx_pg = &ctx->vnic_mem;
4449 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4450 ctx->vnic_max_ring_table_entries;
4451 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4452 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4456 ctx_pg = &ctx->stat_mem;
4457 ctx_pg->entries = ctx->stat_max_entries;
4458 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4459 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4463 entries = ctx->qp_max_l2_entries +
4464 ctx->vnic_max_vnic_entries +
4465 ctx->tqm_min_entries_per_ring;
4466 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4467 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4468 ctx->tqm_max_entries_per_ring);
4469 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4470 ctx_pg = ctx->tqm_mem[i];
4471 /* use min tqm entries for now. */
4472 ctx_pg->entries = entries;
4473 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4474 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4477 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4480 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4481 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4484 "Failed to configure context mem: rc = %d\n", rc);
4486 ctx->flags |= BNXT_CTX_FLAG_INITED;
4491 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4493 struct rte_pci_device *pci_dev = bp->pdev;
4494 char mz_name[RTE_MEMZONE_NAMESIZE];
4495 const struct rte_memzone *mz = NULL;
4496 uint32_t total_alloc_len;
4497 rte_iova_t mz_phys_addr;
4499 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4502 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4503 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4504 pci_dev->addr.bus, pci_dev->addr.devid,
4505 pci_dev->addr.function, "rx_port_stats");
4506 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4507 mz = rte_memzone_lookup(mz_name);
4509 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4510 sizeof(struct rx_port_stats_ext) + 512);
4512 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4515 RTE_MEMZONE_SIZE_HINT_ONLY |
4516 RTE_MEMZONE_IOVA_CONTIG);
4520 memset(mz->addr, 0, mz->len);
4521 mz_phys_addr = mz->iova;
4523 bp->rx_mem_zone = (const void *)mz;
4524 bp->hw_rx_port_stats = mz->addr;
4525 bp->hw_rx_port_stats_map = mz_phys_addr;
4527 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4528 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4529 pci_dev->addr.bus, pci_dev->addr.devid,
4530 pci_dev->addr.function, "tx_port_stats");
4531 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4532 mz = rte_memzone_lookup(mz_name);
4534 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4535 sizeof(struct tx_port_stats_ext) + 512);
4537 mz = rte_memzone_reserve(mz_name,
4541 RTE_MEMZONE_SIZE_HINT_ONLY |
4542 RTE_MEMZONE_IOVA_CONTIG);
4546 memset(mz->addr, 0, mz->len);
4547 mz_phys_addr = mz->iova;
4549 bp->tx_mem_zone = (const void *)mz;
4550 bp->hw_tx_port_stats = mz->addr;
4551 bp->hw_tx_port_stats_map = mz_phys_addr;
4552 bp->flags |= BNXT_FLAG_PORT_STATS;
4554 /* Display extended statistics if FW supports it */
4555 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4556 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4557 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4560 bp->hw_rx_port_stats_ext = (void *)
4561 ((uint8_t *)bp->hw_rx_port_stats +
4562 sizeof(struct rx_port_stats));
4563 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4564 sizeof(struct rx_port_stats);
4565 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4567 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4568 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4569 bp->hw_tx_port_stats_ext = (void *)
4570 ((uint8_t *)bp->hw_tx_port_stats +
4571 sizeof(struct tx_port_stats));
4572 bp->hw_tx_port_stats_ext_map =
4573 bp->hw_tx_port_stats_map +
4574 sizeof(struct tx_port_stats);
4575 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4581 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4583 struct bnxt *bp = eth_dev->data->dev_private;
4586 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4587 RTE_ETHER_ADDR_LEN *
4590 if (eth_dev->data->mac_addrs == NULL) {
4591 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4595 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4599 /* Generate a random MAC address, if none was assigned by PF */
4600 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4601 bnxt_eth_hw_addr_random(bp->mac_addr);
4603 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4604 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4605 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4607 rc = bnxt_hwrm_set_mac(bp);
4609 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4610 RTE_ETHER_ADDR_LEN);
4614 /* Copy the permanent MAC from the FUNC_QCAPS response */
4615 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4616 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4621 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4625 /* MAC is already configured in FW */
4626 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4629 /* Restore the old MAC configured */
4630 rc = bnxt_hwrm_set_mac(bp);
4632 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4637 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4642 #define ALLOW_FUNC(x) \
4644 uint32_t arg = (x); \
4645 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4646 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4649 /* Forward all requests if firmware is new enough */
4650 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4651 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4652 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4653 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4655 PMD_DRV_LOG(WARNING,
4656 "Firmware too old for VF mailbox functionality\n");
4657 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4661 * The following are used for driver cleanup. If we disallow these,
4662 * VF drivers can't clean up cleanly.
4664 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4665 ALLOW_FUNC(HWRM_VNIC_FREE);
4666 ALLOW_FUNC(HWRM_RING_FREE);
4667 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4668 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4669 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4670 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4671 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4672 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4675 static int bnxt_init_fw(struct bnxt *bp)
4682 rc = bnxt_hwrm_ver_get(bp);
4686 rc = bnxt_hwrm_func_reset(bp);
4690 rc = bnxt_hwrm_vnic_qcaps(bp);
4694 rc = bnxt_hwrm_queue_qportcfg(bp);
4698 /* Get the MAX capabilities for this function.
4699 * This function also allocates context memory for TQM rings and
4700 * informs the firmware about this allocated backing store memory.
4702 rc = bnxt_hwrm_func_qcaps(bp);
4706 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4710 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4714 /* Get the adapter error recovery support info */
4715 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4717 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4719 bnxt_hwrm_port_led_qcaps(bp);
4725 bnxt_init_locks(struct bnxt *bp)
4729 err = pthread_mutex_init(&bp->flow_lock, NULL);
4731 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4735 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4737 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4741 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4745 rc = bnxt_init_fw(bp);
4749 if (!reconfig_dev) {
4750 rc = bnxt_setup_mac_addr(bp->eth_dev);
4754 rc = bnxt_restore_dflt_mac(bp);
4759 bnxt_config_vf_req_fwd(bp);
4761 rc = bnxt_hwrm_func_driver_register(bp);
4763 PMD_DRV_LOG(ERR, "Failed to register driver");
4768 if (bp->pdev->max_vfs) {
4769 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4771 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4775 rc = bnxt_hwrm_allocate_pf_only(bp);
4778 "Failed to allocate PF resources");
4784 rc = bnxt_alloc_mem(bp, reconfig_dev);
4788 rc = bnxt_setup_int(bp);
4792 rc = bnxt_request_int(bp);
4796 rc = bnxt_init_locks(bp);
4804 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4806 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4807 static int version_printed;
4811 if (version_printed++ == 0)
4812 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4814 eth_dev->dev_ops = &bnxt_dev_ops;
4815 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4816 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4819 * For secondary processes, we don't initialise any further
4820 * as primary has already done this work.
4822 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4825 rte_eth_copy_pci_info(eth_dev, pci_dev);
4827 bp = eth_dev->data->dev_private;
4829 bp->dev_stopped = 1;
4830 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
4832 if (bnxt_vf_pciid(pci_dev->id.device_id))
4833 bp->flags |= BNXT_FLAG_VF;
4835 if (bnxt_thor_device(pci_dev->id.device_id))
4836 bp->flags |= BNXT_FLAG_THOR_CHIP;
4838 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4839 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4840 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4841 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4842 bp->flags |= BNXT_FLAG_STINGRAY;
4844 rc = bnxt_init_board(eth_dev);
4847 "Failed to initialize board rc: %x\n", rc);
4851 rc = bnxt_alloc_hwrm_resources(bp);
4854 "Failed to allocate hwrm resource rc: %x\n", rc);
4857 rc = bnxt_init_resources(bp, false);
4861 rc = bnxt_alloc_stats_mem(bp);
4865 /* Pass the information to the rte_eth_dev_close() that it should also
4866 * release the private port resources.
4868 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
4871 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4872 pci_dev->mem_resource[0].phys_addr,
4873 pci_dev->mem_resource[0].addr);
4878 bnxt_dev_uninit(eth_dev);
4883 bnxt_uninit_locks(struct bnxt *bp)
4885 pthread_mutex_destroy(&bp->flow_lock);
4886 pthread_mutex_destroy(&bp->def_cp_lock);
4890 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4895 bnxt_free_mem(bp, reconfig_dev);
4896 bnxt_hwrm_func_buf_unrgtr(bp);
4897 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4898 bp->flags &= ~BNXT_FLAG_REGISTERED;
4899 bnxt_free_ctx_mem(bp);
4900 if (!reconfig_dev) {
4901 bnxt_free_hwrm_resources(bp);
4903 if (bp->recovery_info != NULL) {
4904 rte_free(bp->recovery_info);
4905 bp->recovery_info = NULL;
4909 bnxt_uninit_locks(bp);
4910 rte_free(bp->ptp_cfg);
4916 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4918 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4921 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4923 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
4924 bnxt_dev_close_op(eth_dev);
4929 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4930 struct rte_pci_device *pci_dev)
4932 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4936 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4938 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4939 return rte_eth_dev_pci_generic_remove(pci_dev,
4942 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4945 static struct rte_pci_driver bnxt_rte_pmd = {
4946 .id_table = bnxt_pci_id_map,
4947 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4948 .probe = bnxt_pci_probe,
4949 .remove = bnxt_pci_remove,
4953 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4955 if (strcmp(dev->device->driver->name, drv->driver.name))
4961 bool is_bnxt_supported(struct rte_eth_dev *dev)
4963 return is_device_supported(dev, &bnxt_rte_pmd);
4966 RTE_INIT(bnxt_init_log)
4968 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4969 if (bnxt_logtype_driver >= 0)
4970 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4973 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4974 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4975 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");