1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
30 #define DRV_MODULE_NAME "bnxt"
31 static const char bnxt_version[] =
32 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
33 int bnxt_logtype_driver;
36 * The set of PCI devices this driver supports
38 static const struct rte_pci_id bnxt_pci_id_map[] = {
39 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
40 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
41 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
42 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
43 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
45 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
92 { .vendor_id = 0, /* sentinel */ },
95 #define BNXT_ETH_RSS_SUPPORT ( \
97 ETH_RSS_NONFRAG_IPV4_TCP | \
98 ETH_RSS_NONFRAG_IPV4_UDP | \
100 ETH_RSS_NONFRAG_IPV6_TCP | \
101 ETH_RSS_NONFRAG_IPV6_UDP)
103 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
104 DEV_TX_OFFLOAD_IPV4_CKSUM | \
105 DEV_TX_OFFLOAD_TCP_CKSUM | \
106 DEV_TX_OFFLOAD_UDP_CKSUM | \
107 DEV_TX_OFFLOAD_TCP_TSO | \
108 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
109 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
110 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
111 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
112 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
113 DEV_TX_OFFLOAD_QINQ_INSERT | \
114 DEV_TX_OFFLOAD_MULTI_SEGS)
116 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
117 DEV_RX_OFFLOAD_VLAN_STRIP | \
118 DEV_RX_OFFLOAD_IPV4_CKSUM | \
119 DEV_RX_OFFLOAD_UDP_CKSUM | \
120 DEV_RX_OFFLOAD_TCP_CKSUM | \
121 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
122 DEV_RX_OFFLOAD_JUMBO_FRAME | \
123 DEV_RX_OFFLOAD_KEEP_CRC | \
124 DEV_RX_OFFLOAD_VLAN_EXTEND | \
125 DEV_RX_OFFLOAD_TCP_LRO | \
126 DEV_RX_OFFLOAD_SCATTER | \
127 DEV_RX_OFFLOAD_RSS_HASH)
129 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
130 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
131 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
132 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
133 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
134 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
136 int is_bnxt_in_error(struct bnxt *bp)
138 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
140 if (bp->flags & BNXT_FLAG_FW_RESET)
146 /***********************/
149 * High level utility functions
152 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
154 if (!BNXT_CHIP_THOR(bp))
157 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
158 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
159 BNXT_RSS_ENTRIES_PER_CTX_THOR;
162 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
164 if (!BNXT_CHIP_THOR(bp))
165 return HW_HASH_INDEX_SIZE;
167 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
170 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
172 bnxt_free_filter_mem(bp);
173 bnxt_free_vnic_attributes(bp);
174 bnxt_free_vnic_mem(bp);
176 /* tx/rx rings are configured as part of *_queue_setup callbacks.
177 * If the number of rings change across fw update,
178 * we don't have much choice except to warn the user.
182 bnxt_free_tx_rings(bp);
183 bnxt_free_rx_rings(bp);
185 bnxt_free_async_cp_ring(bp);
186 bnxt_free_rxtx_nq_ring(bp);
188 rte_free(bp->grp_info);
192 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
196 rc = bnxt_alloc_ring_grps(bp);
200 rc = bnxt_alloc_async_ring_struct(bp);
204 rc = bnxt_alloc_vnic_mem(bp);
208 rc = bnxt_alloc_vnic_attributes(bp);
212 rc = bnxt_alloc_filter_mem(bp);
216 rc = bnxt_alloc_async_cp_ring(bp);
220 rc = bnxt_alloc_rxtx_nq_ring(bp);
227 bnxt_free_mem(bp, reconfig);
231 static int bnxt_init_chip(struct bnxt *bp)
233 struct bnxt_rx_queue *rxq;
234 struct rte_eth_link new;
235 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
236 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
237 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
238 uint64_t rx_offloads = dev_conf->rxmode.offloads;
239 uint32_t intr_vector = 0;
240 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
241 uint32_t vec = BNXT_MISC_VEC_ID;
245 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
246 bp->eth_dev->data->dev_conf.rxmode.offloads |=
247 DEV_RX_OFFLOAD_JUMBO_FRAME;
248 bp->flags |= BNXT_FLAG_JUMBO;
250 bp->eth_dev->data->dev_conf.rxmode.offloads &=
251 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
252 bp->flags &= ~BNXT_FLAG_JUMBO;
255 /* THOR does not support ring groups.
256 * But we will use the array to save RSS context IDs.
258 if (BNXT_CHIP_THOR(bp))
259 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
261 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
263 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
267 rc = bnxt_alloc_hwrm_rings(bp);
269 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
273 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
275 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
279 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
282 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
283 if (bp->rx_cos_queue[i].id != 0xff) {
284 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
288 "Num pools more than FW profile\n");
292 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
298 rc = bnxt_mq_rx_configure(bp);
300 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
304 /* VNIC configuration */
305 for (i = 0; i < bp->nr_vnics; i++) {
306 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
307 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
309 rc = bnxt_vnic_grp_alloc(bp, vnic);
313 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
314 i, vnic, vnic->fw_grp_ids);
316 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
318 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
323 /* Alloc RSS context only if RSS mode is enabled */
324 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
325 int j, nr_ctxs = bnxt_rss_ctxts(bp);
328 for (j = 0; j < nr_ctxs; j++) {
329 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
335 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
339 vnic->num_lb_ctxts = nr_ctxs;
343 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
344 * setting is not available at this time, it will not be
345 * configured correctly in the CFA.
347 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
348 vnic->vlan_strip = true;
350 vnic->vlan_strip = false;
352 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
354 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
359 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
362 "HWRM vnic %d filter failure rc: %x\n",
367 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
368 rxq = bp->eth_dev->data->rx_queues[j];
371 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
372 j, rxq->vnic, rxq->vnic->fw_grp_ids);
374 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
375 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
378 rc = bnxt_vnic_rss_configure(bp, vnic);
381 "HWRM vnic set RSS failure rc: %x\n", rc);
385 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
387 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
388 DEV_RX_OFFLOAD_TCP_LRO)
389 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
391 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
393 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
396 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
400 /* check and configure queue intr-vector mapping */
401 if ((rte_intr_cap_multiple(intr_handle) ||
402 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
403 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
404 intr_vector = bp->eth_dev->data->nb_rx_queues;
405 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
406 if (intr_vector > bp->rx_cp_nr_rings) {
407 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
411 rc = rte_intr_efd_enable(intr_handle, intr_vector);
416 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
417 intr_handle->intr_vec =
418 rte_zmalloc("intr_vec",
419 bp->eth_dev->data->nb_rx_queues *
421 if (intr_handle->intr_vec == NULL) {
422 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
423 " intr_vec", bp->eth_dev->data->nb_rx_queues);
427 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
428 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
429 intr_handle->intr_vec, intr_handle->nb_efd,
430 intr_handle->max_intr);
431 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
433 intr_handle->intr_vec[queue_id] =
434 vec + BNXT_RX_VEC_START;
435 if (vec < base + intr_handle->nb_efd - 1)
440 /* enable uio/vfio intr/eventfd mapping */
441 rc = rte_intr_enable(intr_handle);
445 rc = bnxt_get_hwrm_link_config(bp, &new);
447 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
451 if (!bp->link_info.link_up) {
452 rc = bnxt_set_hwrm_link_config(bp, true);
455 "HWRM link config failure rc: %x\n", rc);
459 bnxt_print_link_info(bp->eth_dev);
464 rte_free(intr_handle->intr_vec);
466 rte_intr_efd_disable(intr_handle);
468 /* Some of the error status returned by FW may not be from errno.h */
475 static int bnxt_shutdown_nic(struct bnxt *bp)
477 bnxt_free_all_hwrm_resources(bp);
478 bnxt_free_all_filters(bp);
479 bnxt_free_all_vnics(bp);
484 * Device configuration and status function
487 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
488 struct rte_eth_dev_info *dev_info)
490 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
491 struct bnxt *bp = eth_dev->data->dev_private;
492 uint16_t max_vnics, i, j, vpool, vrxq;
493 unsigned int max_rx_rings;
496 rc = is_bnxt_in_error(bp);
501 dev_info->max_mac_addrs = bp->max_l2_ctx;
502 dev_info->max_hash_mac_addrs = 0;
504 /* PF/VF specifics */
506 dev_info->max_vfs = pdev->max_vfs;
508 max_rx_rings = BNXT_MAX_RINGS(bp);
509 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
510 dev_info->max_rx_queues = max_rx_rings;
511 dev_info->max_tx_queues = max_rx_rings;
512 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
513 dev_info->hash_key_size = 40;
514 max_vnics = bp->max_vnics;
517 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
518 dev_info->max_mtu = BNXT_MAX_MTU;
520 /* Fast path specifics */
521 dev_info->min_rx_bufsize = 1;
522 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
524 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
525 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
526 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
527 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
528 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
531 dev_info->default_rxconf = (struct rte_eth_rxconf) {
537 .rx_free_thresh = 32,
538 /* If no descriptors available, pkts are dropped by default */
542 dev_info->default_txconf = (struct rte_eth_txconf) {
548 .tx_free_thresh = 32,
551 eth_dev->data->dev_conf.intr_conf.lsc = 1;
553 eth_dev->data->dev_conf.intr_conf.rxq = 1;
554 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
555 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
556 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
557 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
562 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
563 * need further investigation.
567 vpool = 64; /* ETH_64_POOLS */
568 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
569 for (i = 0; i < 4; vpool >>= 1, i++) {
570 if (max_vnics > vpool) {
571 for (j = 0; j < 5; vrxq >>= 1, j++) {
572 if (dev_info->max_rx_queues > vrxq) {
578 /* Not enough resources to support VMDq */
582 /* Not enough resources to support VMDq */
586 dev_info->max_vmdq_pools = vpool;
587 dev_info->vmdq_queue_num = vrxq;
589 dev_info->vmdq_pool_base = 0;
590 dev_info->vmdq_queue_base = 0;
595 /* Configure the device based on the configuration provided */
596 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
598 struct bnxt *bp = eth_dev->data->dev_private;
599 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
602 bp->rx_queues = (void *)eth_dev->data->rx_queues;
603 bp->tx_queues = (void *)eth_dev->data->tx_queues;
604 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
605 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
607 rc = is_bnxt_in_error(bp);
611 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
612 rc = bnxt_hwrm_check_vf_rings(bp);
614 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
618 /* If a resource has already been allocated - in this case
619 * it is the async completion ring, free it. Reallocate it after
620 * resource reservation. This will ensure the resource counts
621 * are calculated correctly.
624 pthread_mutex_lock(&bp->def_cp_lock);
626 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
627 bnxt_disable_int(bp);
628 bnxt_free_cp_ring(bp, bp->async_cp_ring);
631 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
633 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
634 pthread_mutex_unlock(&bp->def_cp_lock);
638 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
639 rc = bnxt_alloc_async_cp_ring(bp);
641 pthread_mutex_unlock(&bp->def_cp_lock);
647 pthread_mutex_unlock(&bp->def_cp_lock);
649 /* legacy driver needs to get updated values */
650 rc = bnxt_hwrm_func_qcaps(bp);
652 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
657 /* Inherit new configurations */
658 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
659 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
660 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
661 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
662 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
666 if (BNXT_HAS_RING_GRPS(bp) &&
667 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
670 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
671 bp->max_vnics < eth_dev->data->nb_rx_queues)
674 bp->rx_cp_nr_rings = bp->rx_nr_rings;
675 bp->tx_cp_nr_rings = bp->tx_nr_rings;
677 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
678 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
679 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
681 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
683 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
684 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
686 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
692 "Insufficient resources to support requested config\n");
694 "Num Queues Requested: Tx %d, Rx %d\n",
695 eth_dev->data->nb_tx_queues,
696 eth_dev->data->nb_rx_queues);
698 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
699 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
700 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
704 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
706 struct rte_eth_link *link = ð_dev->data->dev_link;
708 if (link->link_status)
709 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
710 eth_dev->data->port_id,
711 (uint32_t)link->link_speed,
712 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
713 ("full-duplex") : ("half-duplex\n"));
715 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
716 eth_dev->data->port_id);
720 * Determine whether the current configuration requires support for scattered
721 * receive; return 1 if scattered receive is required and 0 if not.
723 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
728 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
731 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
732 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
734 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
735 RTE_PKTMBUF_HEADROOM);
736 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
742 static eth_rx_burst_t
743 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
746 #ifndef RTE_LIBRTE_IEEE1588
748 * Vector mode receive can be enabled only if scatter rx is not
749 * in use and rx offloads are limited to VLAN stripping and
752 if (!eth_dev->data->scattered_rx &&
753 !(eth_dev->data->dev_conf.rxmode.offloads &
754 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
755 DEV_RX_OFFLOAD_KEEP_CRC |
756 DEV_RX_OFFLOAD_JUMBO_FRAME |
757 DEV_RX_OFFLOAD_IPV4_CKSUM |
758 DEV_RX_OFFLOAD_UDP_CKSUM |
759 DEV_RX_OFFLOAD_TCP_CKSUM |
760 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
761 DEV_RX_OFFLOAD_RSS_HASH |
762 DEV_RX_OFFLOAD_VLAN_FILTER))) {
763 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
764 eth_dev->data->port_id);
765 return bnxt_recv_pkts_vec;
767 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
768 eth_dev->data->port_id);
770 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
771 eth_dev->data->port_id,
772 eth_dev->data->scattered_rx,
773 eth_dev->data->dev_conf.rxmode.offloads);
776 return bnxt_recv_pkts;
779 static eth_tx_burst_t
780 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
783 #ifndef RTE_LIBRTE_IEEE1588
785 * Vector mode transmit can be enabled only if not using scatter rx
788 if (!eth_dev->data->scattered_rx &&
789 !eth_dev->data->dev_conf.txmode.offloads) {
790 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
791 eth_dev->data->port_id);
792 return bnxt_xmit_pkts_vec;
794 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
795 eth_dev->data->port_id);
797 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
798 eth_dev->data->port_id,
799 eth_dev->data->scattered_rx,
800 eth_dev->data->dev_conf.txmode.offloads);
803 return bnxt_xmit_pkts;
806 static int bnxt_handle_if_change_status(struct bnxt *bp)
810 /* Since fw has undergone a reset and lost all contexts,
811 * set fatal flag to not issue hwrm during cleanup
813 bp->flags |= BNXT_FLAG_FATAL_ERROR;
814 bnxt_uninit_resources(bp, true);
816 /* clear fatal flag so that re-init happens */
817 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
818 rc = bnxt_init_resources(bp, true);
820 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
825 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
827 struct bnxt *bp = eth_dev->data->dev_private;
828 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
832 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
833 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
837 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
839 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
840 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
843 rc = bnxt_hwrm_if_change(bp, 1);
845 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
846 rc = bnxt_handle_if_change_status(bp);
853 rc = bnxt_init_chip(bp);
857 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
859 bnxt_link_update_op(eth_dev, 1);
861 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
862 vlan_mask |= ETH_VLAN_FILTER_MASK;
863 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
864 vlan_mask |= ETH_VLAN_STRIP_MASK;
865 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
869 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
870 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
872 bp->flags |= BNXT_FLAG_INIT_DONE;
873 eth_dev->data->dev_started = 1;
875 pthread_mutex_lock(&bp->def_cp_lock);
876 bnxt_schedule_fw_health_check(bp);
877 pthread_mutex_unlock(&bp->def_cp_lock);
881 bnxt_hwrm_if_change(bp, 0);
882 bnxt_shutdown_nic(bp);
883 bnxt_free_tx_mbufs(bp);
884 bnxt_free_rx_mbufs(bp);
888 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
890 struct bnxt *bp = eth_dev->data->dev_private;
893 if (!bp->link_info.link_up)
894 rc = bnxt_set_hwrm_link_config(bp, true);
896 eth_dev->data->dev_link.link_status = 1;
898 bnxt_print_link_info(eth_dev);
902 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
904 struct bnxt *bp = eth_dev->data->dev_private;
906 eth_dev->data->dev_link.link_status = 0;
907 bnxt_set_hwrm_link_config(bp, false);
908 bp->link_info.link_up = 0;
913 /* Unload the driver, release resources */
914 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
916 struct bnxt *bp = eth_dev->data->dev_private;
917 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
918 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
920 eth_dev->data->dev_started = 0;
921 /* Prevent crashes when queues are still in use */
922 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
923 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
925 bnxt_disable_int(bp);
927 /* disable uio/vfio intr/eventfd mapping */
928 rte_intr_disable(intr_handle);
930 bnxt_cancel_fw_health_check(bp);
932 bp->flags &= ~BNXT_FLAG_INIT_DONE;
933 if (bp->eth_dev->data->dev_started) {
934 /* TBD: STOP HW queues DMA */
935 eth_dev->data->dev_link.link_status = 0;
937 bnxt_dev_set_link_down_op(eth_dev);
939 /* Wait for link to be reset and the async notification to process.
940 * During reset recovery, there is no need to wait
942 if (!is_bnxt_in_error(bp))
943 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
945 /* Clean queue intr-vector mapping */
946 rte_intr_efd_disable(intr_handle);
947 if (intr_handle->intr_vec != NULL) {
948 rte_free(intr_handle->intr_vec);
949 intr_handle->intr_vec = NULL;
952 bnxt_hwrm_port_clr_stats(bp);
953 bnxt_free_tx_mbufs(bp);
954 bnxt_free_rx_mbufs(bp);
955 /* Process any remaining notifications in default completion queue */
956 bnxt_int_handler(eth_dev);
957 bnxt_shutdown_nic(bp);
958 bnxt_hwrm_if_change(bp, 0);
963 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
965 struct bnxt *bp = eth_dev->data->dev_private;
967 if (bp->dev_stopped == 0)
968 bnxt_dev_stop_op(eth_dev);
970 if (eth_dev->data->mac_addrs != NULL) {
971 rte_free(eth_dev->data->mac_addrs);
972 eth_dev->data->mac_addrs = NULL;
974 if (bp->grp_info != NULL) {
975 rte_free(bp->grp_info);
979 bnxt_dev_uninit(eth_dev);
982 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
985 struct bnxt *bp = eth_dev->data->dev_private;
986 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
987 struct bnxt_vnic_info *vnic;
988 struct bnxt_filter_info *filter, *temp_filter;
991 if (is_bnxt_in_error(bp))
995 * Loop through all VNICs from the specified filter flow pools to
996 * remove the corresponding MAC addr filter
998 for (i = 0; i < bp->nr_vnics; i++) {
999 if (!(pool_mask & (1ULL << i)))
1002 vnic = &bp->vnic_info[i];
1003 filter = STAILQ_FIRST(&vnic->filter);
1005 temp_filter = STAILQ_NEXT(filter, next);
1006 if (filter->mac_index == index) {
1007 STAILQ_REMOVE(&vnic->filter, filter,
1008 bnxt_filter_info, next);
1009 bnxt_hwrm_clear_l2_filter(bp, filter);
1010 filter->mac_index = INVALID_MAC_INDEX;
1011 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1012 bnxt_free_filter(bp, filter);
1014 filter = temp_filter;
1019 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1020 struct rte_ether_addr *mac_addr, uint32_t index,
1023 struct bnxt_filter_info *filter;
1026 /* Attach requested MAC address to the new l2_filter */
1027 STAILQ_FOREACH(filter, &vnic->filter, next) {
1028 if (filter->mac_index == index) {
1030 "MAC addr already existed for pool %d\n",
1036 filter = bnxt_alloc_filter(bp);
1038 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1042 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1043 * if the MAC that's been programmed now is a different one, then,
1044 * copy that addr to filter->l2_addr
1047 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1048 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1050 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1052 filter->mac_index = index;
1053 if (filter->mac_index == 0)
1054 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1056 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1058 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1059 bnxt_free_filter(bp, filter);
1065 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1066 struct rte_ether_addr *mac_addr,
1067 uint32_t index, uint32_t pool)
1069 struct bnxt *bp = eth_dev->data->dev_private;
1070 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1073 rc = is_bnxt_in_error(bp);
1077 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1078 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1083 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1087 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1092 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1095 struct bnxt *bp = eth_dev->data->dev_private;
1096 struct rte_eth_link new;
1097 unsigned int cnt = BNXT_LINK_WAIT_CNT;
1099 rc = is_bnxt_in_error(bp);
1103 memset(&new, 0, sizeof(new));
1105 /* Retrieve link info from hardware */
1106 rc = bnxt_get_hwrm_link_config(bp, &new);
1108 new.link_speed = ETH_LINK_SPEED_100M;
1109 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1111 "Failed to retrieve link rc = 0x%x!\n", rc);
1115 if (!wait_to_complete || new.link_status)
1118 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1122 /* Timed out or success */
1123 if (new.link_status != eth_dev->data->dev_link.link_status ||
1124 new.link_speed != eth_dev->data->dev_link.link_speed) {
1125 rte_eth_linkstatus_set(eth_dev, &new);
1127 _rte_eth_dev_callback_process(eth_dev,
1128 RTE_ETH_EVENT_INTR_LSC,
1131 bnxt_print_link_info(eth_dev);
1137 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1139 struct bnxt *bp = eth_dev->data->dev_private;
1140 struct bnxt_vnic_info *vnic;
1144 rc = is_bnxt_in_error(bp);
1148 if (bp->vnic_info == NULL)
1151 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1153 old_flags = vnic->flags;
1154 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1155 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1157 vnic->flags = old_flags;
1162 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1164 struct bnxt *bp = eth_dev->data->dev_private;
1165 struct bnxt_vnic_info *vnic;
1169 rc = is_bnxt_in_error(bp);
1173 if (bp->vnic_info == NULL)
1176 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1178 old_flags = vnic->flags;
1179 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1180 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1182 vnic->flags = old_flags;
1187 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1189 struct bnxt *bp = eth_dev->data->dev_private;
1190 struct bnxt_vnic_info *vnic;
1194 rc = is_bnxt_in_error(bp);
1198 if (bp->vnic_info == NULL)
1201 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1203 old_flags = vnic->flags;
1204 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1205 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1207 vnic->flags = old_flags;
1212 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1214 struct bnxt *bp = eth_dev->data->dev_private;
1215 struct bnxt_vnic_info *vnic;
1219 rc = is_bnxt_in_error(bp);
1223 if (bp->vnic_info == NULL)
1226 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1228 old_flags = vnic->flags;
1229 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1230 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1232 vnic->flags = old_flags;
1237 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1238 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1240 if (qid >= bp->rx_nr_rings)
1243 return bp->eth_dev->data->rx_queues[qid];
1246 /* Return rxq corresponding to a given rss table ring/group ID. */
1247 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1249 struct bnxt_rx_queue *rxq;
1252 if (!BNXT_HAS_RING_GRPS(bp)) {
1253 for (i = 0; i < bp->rx_nr_rings; i++) {
1254 rxq = bp->eth_dev->data->rx_queues[i];
1255 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1259 for (i = 0; i < bp->rx_nr_rings; i++) {
1260 if (bp->grp_info[i].fw_grp_id == fwr)
1265 return INVALID_HW_RING_ID;
1268 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1269 struct rte_eth_rss_reta_entry64 *reta_conf,
1272 struct bnxt *bp = eth_dev->data->dev_private;
1273 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1274 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1275 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1279 rc = is_bnxt_in_error(bp);
1283 if (!vnic->rss_table)
1286 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1289 if (reta_size != tbl_size) {
1290 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1291 "(%d) must equal the size supported by the hardware "
1292 "(%d)\n", reta_size, tbl_size);
1296 for (i = 0; i < reta_size; i++) {
1297 struct bnxt_rx_queue *rxq;
1299 idx = i / RTE_RETA_GROUP_SIZE;
1300 sft = i % RTE_RETA_GROUP_SIZE;
1302 if (!(reta_conf[idx].mask & (1ULL << sft)))
1305 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1307 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1311 if (BNXT_CHIP_THOR(bp)) {
1312 vnic->rss_table[i * 2] =
1313 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1314 vnic->rss_table[i * 2 + 1] =
1315 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1317 vnic->rss_table[i] =
1318 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1322 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1326 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1327 struct rte_eth_rss_reta_entry64 *reta_conf,
1330 struct bnxt *bp = eth_dev->data->dev_private;
1331 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1332 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1333 uint16_t idx, sft, i;
1336 rc = is_bnxt_in_error(bp);
1340 /* Retrieve from the default VNIC */
1343 if (!vnic->rss_table)
1346 if (reta_size != tbl_size) {
1347 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1348 "(%d) must equal the size supported by the hardware "
1349 "(%d)\n", reta_size, tbl_size);
1353 for (idx = 0, i = 0; i < reta_size; i++) {
1354 idx = i / RTE_RETA_GROUP_SIZE;
1355 sft = i % RTE_RETA_GROUP_SIZE;
1357 if (reta_conf[idx].mask & (1ULL << sft)) {
1360 if (BNXT_CHIP_THOR(bp))
1361 qid = bnxt_rss_to_qid(bp,
1362 vnic->rss_table[i * 2]);
1364 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1366 if (qid == INVALID_HW_RING_ID) {
1367 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1370 reta_conf[idx].reta[sft] = qid;
1377 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1378 struct rte_eth_rss_conf *rss_conf)
1380 struct bnxt *bp = eth_dev->data->dev_private;
1381 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1382 struct bnxt_vnic_info *vnic;
1385 rc = is_bnxt_in_error(bp);
1390 * If RSS enablement were different than dev_configure,
1391 * then return -EINVAL
1393 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1394 if (!rss_conf->rss_hf)
1395 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1397 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1401 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1402 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1404 /* Update the default RSS VNIC(s) */
1405 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1406 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1409 * If hashkey is not specified, use the previously configured
1412 if (!rss_conf->rss_key)
1415 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1417 "Invalid hashkey length, should be 16 bytes\n");
1420 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1423 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1427 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1428 struct rte_eth_rss_conf *rss_conf)
1430 struct bnxt *bp = eth_dev->data->dev_private;
1431 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1433 uint32_t hash_types;
1435 rc = is_bnxt_in_error(bp);
1439 /* RSS configuration is the same for all VNICs */
1440 if (vnic && vnic->rss_hash_key) {
1441 if (rss_conf->rss_key) {
1442 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1443 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1444 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1447 hash_types = vnic->hash_type;
1448 rss_conf->rss_hf = 0;
1449 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1450 rss_conf->rss_hf |= ETH_RSS_IPV4;
1451 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1453 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1454 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1456 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1458 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1459 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1461 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1463 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1464 rss_conf->rss_hf |= ETH_RSS_IPV6;
1465 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1467 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1468 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1470 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1472 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1473 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1475 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1479 "Unknwon RSS config from firmware (%08x), RSS disabled",
1484 rss_conf->rss_hf = 0;
1489 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1490 struct rte_eth_fc_conf *fc_conf)
1492 struct bnxt *bp = dev->data->dev_private;
1493 struct rte_eth_link link_info;
1496 rc = is_bnxt_in_error(bp);
1500 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1504 memset(fc_conf, 0, sizeof(*fc_conf));
1505 if (bp->link_info.auto_pause)
1506 fc_conf->autoneg = 1;
1507 switch (bp->link_info.pause) {
1509 fc_conf->mode = RTE_FC_NONE;
1511 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1512 fc_conf->mode = RTE_FC_TX_PAUSE;
1514 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1515 fc_conf->mode = RTE_FC_RX_PAUSE;
1517 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1518 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1519 fc_conf->mode = RTE_FC_FULL;
1525 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1526 struct rte_eth_fc_conf *fc_conf)
1528 struct bnxt *bp = dev->data->dev_private;
1531 rc = is_bnxt_in_error(bp);
1535 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1536 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1540 switch (fc_conf->mode) {
1542 bp->link_info.auto_pause = 0;
1543 bp->link_info.force_pause = 0;
1545 case RTE_FC_RX_PAUSE:
1546 if (fc_conf->autoneg) {
1547 bp->link_info.auto_pause =
1548 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1549 bp->link_info.force_pause = 0;
1551 bp->link_info.auto_pause = 0;
1552 bp->link_info.force_pause =
1553 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1556 case RTE_FC_TX_PAUSE:
1557 if (fc_conf->autoneg) {
1558 bp->link_info.auto_pause =
1559 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1560 bp->link_info.force_pause = 0;
1562 bp->link_info.auto_pause = 0;
1563 bp->link_info.force_pause =
1564 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1568 if (fc_conf->autoneg) {
1569 bp->link_info.auto_pause =
1570 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1571 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1572 bp->link_info.force_pause = 0;
1574 bp->link_info.auto_pause = 0;
1575 bp->link_info.force_pause =
1576 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1577 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1581 return bnxt_set_hwrm_link_config(bp, true);
1584 /* Add UDP tunneling port */
1586 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1587 struct rte_eth_udp_tunnel *udp_tunnel)
1589 struct bnxt *bp = eth_dev->data->dev_private;
1590 uint16_t tunnel_type = 0;
1593 rc = is_bnxt_in_error(bp);
1597 switch (udp_tunnel->prot_type) {
1598 case RTE_TUNNEL_TYPE_VXLAN:
1599 if (bp->vxlan_port_cnt) {
1600 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1601 udp_tunnel->udp_port);
1602 if (bp->vxlan_port != udp_tunnel->udp_port) {
1603 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1606 bp->vxlan_port_cnt++;
1610 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1611 bp->vxlan_port_cnt++;
1613 case RTE_TUNNEL_TYPE_GENEVE:
1614 if (bp->geneve_port_cnt) {
1615 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1616 udp_tunnel->udp_port);
1617 if (bp->geneve_port != udp_tunnel->udp_port) {
1618 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1621 bp->geneve_port_cnt++;
1625 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1626 bp->geneve_port_cnt++;
1629 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1632 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1638 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1639 struct rte_eth_udp_tunnel *udp_tunnel)
1641 struct bnxt *bp = eth_dev->data->dev_private;
1642 uint16_t tunnel_type = 0;
1646 rc = is_bnxt_in_error(bp);
1650 switch (udp_tunnel->prot_type) {
1651 case RTE_TUNNEL_TYPE_VXLAN:
1652 if (!bp->vxlan_port_cnt) {
1653 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1656 if (bp->vxlan_port != udp_tunnel->udp_port) {
1657 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1658 udp_tunnel->udp_port, bp->vxlan_port);
1661 if (--bp->vxlan_port_cnt)
1665 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1666 port = bp->vxlan_fw_dst_port_id;
1668 case RTE_TUNNEL_TYPE_GENEVE:
1669 if (!bp->geneve_port_cnt) {
1670 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1673 if (bp->geneve_port != udp_tunnel->udp_port) {
1674 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1675 udp_tunnel->udp_port, bp->geneve_port);
1678 if (--bp->geneve_port_cnt)
1682 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1683 port = bp->geneve_fw_dst_port_id;
1686 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1690 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1693 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1696 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1697 bp->geneve_port = 0;
1702 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1704 struct bnxt_filter_info *filter;
1705 struct bnxt_vnic_info *vnic;
1707 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1709 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1710 filter = STAILQ_FIRST(&vnic->filter);
1712 /* Search for this matching MAC+VLAN filter */
1713 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1714 /* Delete the filter */
1715 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1718 STAILQ_REMOVE(&vnic->filter, filter,
1719 bnxt_filter_info, next);
1720 bnxt_free_filter(bp, filter);
1722 "Deleted vlan filter for %d\n",
1726 filter = STAILQ_NEXT(filter, next);
1731 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1733 struct bnxt_filter_info *filter;
1734 struct bnxt_vnic_info *vnic;
1736 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1737 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1738 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1740 /* Implementation notes on the use of VNIC in this command:
1742 * By default, these filters belong to default vnic for the function.
1743 * Once these filters are set up, only destination VNIC can be modified.
1744 * If the destination VNIC is not specified in this command,
1745 * then the HWRM shall only create an l2 context id.
1748 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1749 filter = STAILQ_FIRST(&vnic->filter);
1750 /* Check if the VLAN has already been added */
1752 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
1755 filter = STAILQ_NEXT(filter, next);
1758 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1759 * command to create MAC+VLAN filter with the right flags, enables set.
1761 filter = bnxt_alloc_filter(bp);
1764 "MAC/VLAN filter alloc failed\n");
1767 /* MAC + VLAN ID filter */
1768 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1769 * untagged packets are received
1771 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1772 * packets and only the programmed vlan's packets are received
1774 filter->l2_ivlan = vlan_id;
1775 filter->l2_ivlan_mask = 0x0FFF;
1776 filter->enables |= en;
1777 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1779 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1781 /* Free the newly allocated filter as we were
1782 * not able to create the filter in hardware.
1784 filter->fw_l2_filter_id = UINT64_MAX;
1785 bnxt_free_filter(bp, filter);
1789 filter->mac_index = 0;
1790 /* Add this new filter to the list */
1792 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1794 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1797 "Added Vlan filter for %d\n", vlan_id);
1801 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1802 uint16_t vlan_id, int on)
1804 struct bnxt *bp = eth_dev->data->dev_private;
1807 rc = is_bnxt_in_error(bp);
1811 /* These operations apply to ALL existing MAC/VLAN filters */
1813 return bnxt_add_vlan_filter(bp, vlan_id);
1815 return bnxt_del_vlan_filter(bp, vlan_id);
1818 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1819 struct bnxt_vnic_info *vnic)
1821 struct bnxt_filter_info *filter;
1824 filter = STAILQ_FIRST(&vnic->filter);
1826 if (filter->mac_index == 0 &&
1827 !memcmp(filter->l2_addr, bp->mac_addr,
1828 RTE_ETHER_ADDR_LEN)) {
1829 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1831 STAILQ_REMOVE(&vnic->filter, filter,
1832 bnxt_filter_info, next);
1833 bnxt_free_filter(bp, filter);
1834 filter->fw_l2_filter_id = UINT64_MAX;
1838 filter = STAILQ_NEXT(filter, next);
1844 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1846 struct bnxt *bp = dev->data->dev_private;
1847 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1848 struct bnxt_vnic_info *vnic;
1852 rc = is_bnxt_in_error(bp);
1856 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1857 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1858 /* Remove any VLAN filters programmed */
1859 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1860 bnxt_del_vlan_filter(bp, i);
1862 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1866 /* Default filter will allow packets that match the
1867 * dest mac. So, it has to be deleted, otherwise, we
1868 * will endup receiving vlan packets for which the
1869 * filter is not programmed, when hw-vlan-filter
1870 * configuration is ON
1872 bnxt_del_dflt_mac_filter(bp, vnic);
1873 /* This filter will allow only untagged packets */
1874 bnxt_add_vlan_filter(bp, 0);
1876 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1877 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1879 if (mask & ETH_VLAN_STRIP_MASK) {
1880 /* Enable or disable VLAN stripping */
1881 for (i = 0; i < bp->nr_vnics; i++) {
1882 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1883 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1884 vnic->vlan_strip = true;
1886 vnic->vlan_strip = false;
1887 bnxt_hwrm_vnic_cfg(bp, vnic);
1889 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1890 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1893 if (mask & ETH_VLAN_EXTEND_MASK) {
1894 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1895 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1897 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1904 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1907 struct bnxt *bp = dev->data->dev_private;
1908 int qinq = dev->data->dev_conf.rxmode.offloads &
1909 DEV_RX_OFFLOAD_VLAN_EXTEND;
1911 if (vlan_type != ETH_VLAN_TYPE_INNER &&
1912 vlan_type != ETH_VLAN_TYPE_OUTER) {
1914 "Unsupported vlan type.");
1919 "QinQ not enabled. Needs to be ON as we can "
1920 "accelerate only outer vlan\n");
1924 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1926 case RTE_ETHER_TYPE_QINQ:
1928 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1930 case RTE_ETHER_TYPE_VLAN:
1932 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1936 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1940 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
1944 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
1947 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
1950 bp->outer_tpid_bd |= tpid;
1951 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
1952 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
1954 "Can accelerate only outer vlan in QinQ\n");
1962 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1963 struct rte_ether_addr *addr)
1965 struct bnxt *bp = dev->data->dev_private;
1966 /* Default Filter is tied to VNIC 0 */
1967 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1968 struct bnxt_filter_info *filter;
1971 rc = is_bnxt_in_error(bp);
1975 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1978 if (rte_is_zero_ether_addr(addr))
1981 STAILQ_FOREACH(filter, &vnic->filter, next) {
1982 /* Default Filter is at Index 0 */
1983 if (filter->mac_index != 0)
1986 memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN);
1987 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1988 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX |
1989 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1991 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1992 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1994 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1996 memcpy(filter->l2_addr, bp->mac_addr,
1997 RTE_ETHER_ADDR_LEN);
2001 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2002 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2010 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2011 struct rte_ether_addr *mc_addr_set,
2012 uint32_t nb_mc_addr)
2014 struct bnxt *bp = eth_dev->data->dev_private;
2015 char *mc_addr_list = (char *)mc_addr_set;
2016 struct bnxt_vnic_info *vnic;
2017 uint32_t off = 0, i = 0;
2020 rc = is_bnxt_in_error(bp);
2024 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2026 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2027 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2031 /* TODO Check for Duplicate mcast addresses */
2032 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2033 for (i = 0; i < nb_mc_addr; i++) {
2034 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2035 RTE_ETHER_ADDR_LEN);
2036 off += RTE_ETHER_ADDR_LEN;
2039 vnic->mc_addr_cnt = i;
2040 if (vnic->mc_addr_cnt)
2041 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2043 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2046 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2050 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2052 struct bnxt *bp = dev->data->dev_private;
2053 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2054 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2055 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2058 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2059 fw_major, fw_minor, fw_updt);
2061 ret += 1; /* add the size of '\0' */
2062 if (fw_size < (uint32_t)ret)
2069 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2070 struct rte_eth_rxq_info *qinfo)
2072 struct bnxt *bp = dev->data->dev_private;
2073 struct bnxt_rx_queue *rxq;
2075 if (is_bnxt_in_error(bp))
2078 rxq = dev->data->rx_queues[queue_id];
2080 qinfo->mp = rxq->mb_pool;
2081 qinfo->scattered_rx = dev->data->scattered_rx;
2082 qinfo->nb_desc = rxq->nb_rx_desc;
2084 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2085 qinfo->conf.rx_drop_en = 0;
2086 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2090 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2091 struct rte_eth_txq_info *qinfo)
2093 struct bnxt *bp = dev->data->dev_private;
2094 struct bnxt_tx_queue *txq;
2096 if (is_bnxt_in_error(bp))
2099 txq = dev->data->tx_queues[queue_id];
2101 qinfo->nb_desc = txq->nb_tx_desc;
2103 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2104 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2105 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2107 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2108 qinfo->conf.tx_rs_thresh = 0;
2109 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2112 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2114 struct bnxt *bp = eth_dev->data->dev_private;
2115 uint32_t new_pkt_size;
2119 rc = is_bnxt_in_error(bp);
2123 /* Exit if receive queues are not configured yet */
2124 if (!eth_dev->data->nb_rx_queues)
2127 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2128 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2132 * If vector-mode tx/rx is active, disallow any MTU change that would
2133 * require scattered receive support.
2135 if (eth_dev->data->dev_started &&
2136 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2137 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2139 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2141 "MTU change would require scattered rx support. ");
2142 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2147 if (new_mtu > RTE_ETHER_MTU) {
2148 bp->flags |= BNXT_FLAG_JUMBO;
2149 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2150 DEV_RX_OFFLOAD_JUMBO_FRAME;
2152 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2153 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2154 bp->flags &= ~BNXT_FLAG_JUMBO;
2157 /* Is there a change in mtu setting? */
2158 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2161 for (i = 0; i < bp->nr_vnics; i++) {
2162 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2165 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2166 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2170 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2171 size -= RTE_PKTMBUF_HEADROOM;
2173 if (size < new_mtu) {
2174 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2181 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2183 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2189 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2191 struct bnxt *bp = dev->data->dev_private;
2192 uint16_t vlan = bp->vlan;
2195 rc = is_bnxt_in_error(bp);
2199 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2201 "PVID cannot be modified for this function\n");
2204 bp->vlan = on ? pvid : 0;
2206 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2213 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2215 struct bnxt *bp = dev->data->dev_private;
2218 rc = is_bnxt_in_error(bp);
2222 return bnxt_hwrm_port_led_cfg(bp, true);
2226 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2228 struct bnxt *bp = dev->data->dev_private;
2231 rc = is_bnxt_in_error(bp);
2235 return bnxt_hwrm_port_led_cfg(bp, false);
2239 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2241 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2242 uint32_t desc = 0, raw_cons = 0, cons;
2243 struct bnxt_cp_ring_info *cpr;
2244 struct bnxt_rx_queue *rxq;
2245 struct rx_pkt_cmpl *rxcmp;
2248 rc = is_bnxt_in_error(bp);
2252 rxq = dev->data->rx_queues[rx_queue_id];
2254 raw_cons = cpr->cp_raw_cons;
2257 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2258 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2259 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2261 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2273 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2275 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2276 struct bnxt_rx_ring_info *rxr;
2277 struct bnxt_cp_ring_info *cpr;
2278 struct bnxt_sw_rx_bd *rx_buf;
2279 struct rx_pkt_cmpl *rxcmp;
2280 uint32_t cons, cp_cons;
2286 rc = is_bnxt_in_error(rxq->bp);
2293 if (offset >= rxq->nb_rx_desc)
2296 cons = RING_CMP(cpr->cp_ring_struct, offset);
2297 cp_cons = cpr->cp_raw_cons;
2298 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2300 if (cons > cp_cons) {
2301 if (CMPL_VALID(rxcmp, cpr->valid))
2302 return RTE_ETH_RX_DESC_DONE;
2304 if (CMPL_VALID(rxcmp, !cpr->valid))
2305 return RTE_ETH_RX_DESC_DONE;
2307 rx_buf = &rxr->rx_buf_ring[cons];
2308 if (rx_buf->mbuf == NULL)
2309 return RTE_ETH_RX_DESC_UNAVAIL;
2312 return RTE_ETH_RX_DESC_AVAIL;
2316 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2318 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2319 struct bnxt_tx_ring_info *txr;
2320 struct bnxt_cp_ring_info *cpr;
2321 struct bnxt_sw_tx_bd *tx_buf;
2322 struct tx_pkt_cmpl *txcmp;
2323 uint32_t cons, cp_cons;
2329 rc = is_bnxt_in_error(txq->bp);
2336 if (offset >= txq->nb_tx_desc)
2339 cons = RING_CMP(cpr->cp_ring_struct, offset);
2340 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2341 cp_cons = cpr->cp_raw_cons;
2343 if (cons > cp_cons) {
2344 if (CMPL_VALID(txcmp, cpr->valid))
2345 return RTE_ETH_TX_DESC_UNAVAIL;
2347 if (CMPL_VALID(txcmp, !cpr->valid))
2348 return RTE_ETH_TX_DESC_UNAVAIL;
2350 tx_buf = &txr->tx_buf_ring[cons];
2351 if (tx_buf->mbuf == NULL)
2352 return RTE_ETH_TX_DESC_DONE;
2354 return RTE_ETH_TX_DESC_FULL;
2357 static struct bnxt_filter_info *
2358 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2359 struct rte_eth_ethertype_filter *efilter,
2360 struct bnxt_vnic_info *vnic0,
2361 struct bnxt_vnic_info *vnic,
2364 struct bnxt_filter_info *mfilter = NULL;
2368 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2369 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2370 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2371 " ethertype filter.", efilter->ether_type);
2375 if (efilter->queue >= bp->rx_nr_rings) {
2376 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2381 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2382 vnic = &bp->vnic_info[efilter->queue];
2384 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2389 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2390 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2391 if ((!memcmp(efilter->mac_addr.addr_bytes,
2392 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2394 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2395 mfilter->ethertype == efilter->ether_type)) {
2401 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2402 if ((!memcmp(efilter->mac_addr.addr_bytes,
2403 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2404 mfilter->ethertype == efilter->ether_type &&
2406 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2420 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2421 enum rte_filter_op filter_op,
2424 struct bnxt *bp = dev->data->dev_private;
2425 struct rte_eth_ethertype_filter *efilter =
2426 (struct rte_eth_ethertype_filter *)arg;
2427 struct bnxt_filter_info *bfilter, *filter1;
2428 struct bnxt_vnic_info *vnic, *vnic0;
2431 if (filter_op == RTE_ETH_FILTER_NOP)
2435 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2440 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2441 vnic = &bp->vnic_info[efilter->queue];
2443 switch (filter_op) {
2444 case RTE_ETH_FILTER_ADD:
2445 bnxt_match_and_validate_ether_filter(bp, efilter,
2450 bfilter = bnxt_get_unused_filter(bp);
2451 if (bfilter == NULL) {
2453 "Not enough resources for a new filter.\n");
2456 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2457 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2458 RTE_ETHER_ADDR_LEN);
2459 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2460 RTE_ETHER_ADDR_LEN);
2461 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2462 bfilter->ethertype = efilter->ether_type;
2463 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2465 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2466 if (filter1 == NULL) {
2471 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2472 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2474 bfilter->dst_id = vnic->fw_vnic_id;
2476 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2478 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2481 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2484 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2486 case RTE_ETH_FILTER_DELETE:
2487 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2489 if (ret == -EEXIST) {
2490 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2492 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2494 bnxt_free_filter(bp, filter1);
2495 } else if (ret == 0) {
2496 PMD_DRV_LOG(ERR, "No matching filter found\n");
2500 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2506 bnxt_free_filter(bp, bfilter);
2512 parse_ntuple_filter(struct bnxt *bp,
2513 struct rte_eth_ntuple_filter *nfilter,
2514 struct bnxt_filter_info *bfilter)
2518 if (nfilter->queue >= bp->rx_nr_rings) {
2519 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2523 switch (nfilter->dst_port_mask) {
2525 bfilter->dst_port_mask = -1;
2526 bfilter->dst_port = nfilter->dst_port;
2527 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2528 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2531 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2535 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2536 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2538 switch (nfilter->proto_mask) {
2540 if (nfilter->proto == 17) /* IPPROTO_UDP */
2541 bfilter->ip_protocol = 17;
2542 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2543 bfilter->ip_protocol = 6;
2546 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2549 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2553 switch (nfilter->dst_ip_mask) {
2555 bfilter->dst_ipaddr_mask[0] = -1;
2556 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2557 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2558 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2561 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2565 switch (nfilter->src_ip_mask) {
2567 bfilter->src_ipaddr_mask[0] = -1;
2568 bfilter->src_ipaddr[0] = nfilter->src_ip;
2569 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2570 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2573 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2577 switch (nfilter->src_port_mask) {
2579 bfilter->src_port_mask = -1;
2580 bfilter->src_port = nfilter->src_port;
2581 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2582 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2585 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2589 bfilter->enables = en;
2593 static struct bnxt_filter_info*
2594 bnxt_match_ntuple_filter(struct bnxt *bp,
2595 struct bnxt_filter_info *bfilter,
2596 struct bnxt_vnic_info **mvnic)
2598 struct bnxt_filter_info *mfilter = NULL;
2601 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2602 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2603 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2604 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2605 bfilter->src_ipaddr_mask[0] ==
2606 mfilter->src_ipaddr_mask[0] &&
2607 bfilter->src_port == mfilter->src_port &&
2608 bfilter->src_port_mask == mfilter->src_port_mask &&
2609 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2610 bfilter->dst_ipaddr_mask[0] ==
2611 mfilter->dst_ipaddr_mask[0] &&
2612 bfilter->dst_port == mfilter->dst_port &&
2613 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2614 bfilter->flags == mfilter->flags &&
2615 bfilter->enables == mfilter->enables) {
2626 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2627 struct rte_eth_ntuple_filter *nfilter,
2628 enum rte_filter_op filter_op)
2630 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2631 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2634 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2635 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2639 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2640 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2644 bfilter = bnxt_get_unused_filter(bp);
2645 if (bfilter == NULL) {
2647 "Not enough resources for a new filter.\n");
2650 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2654 vnic = &bp->vnic_info[nfilter->queue];
2655 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2656 filter1 = STAILQ_FIRST(&vnic0->filter);
2657 if (filter1 == NULL) {
2662 bfilter->dst_id = vnic->fw_vnic_id;
2663 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2665 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2666 bfilter->ethertype = 0x800;
2667 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2669 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2671 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2672 bfilter->dst_id == mfilter->dst_id) {
2673 PMD_DRV_LOG(ERR, "filter exists.\n");
2676 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2677 bfilter->dst_id != mfilter->dst_id) {
2678 mfilter->dst_id = vnic->fw_vnic_id;
2679 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2680 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2681 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2682 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2683 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2686 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2687 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2692 if (filter_op == RTE_ETH_FILTER_ADD) {
2693 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2694 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2697 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2699 if (mfilter == NULL) {
2700 /* This should not happen. But for Coverity! */
2704 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2706 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2707 bnxt_free_filter(bp, mfilter);
2708 mfilter->fw_l2_filter_id = -1;
2709 bnxt_free_filter(bp, bfilter);
2710 bfilter->fw_l2_filter_id = -1;
2715 bfilter->fw_l2_filter_id = -1;
2716 bnxt_free_filter(bp, bfilter);
2721 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2722 enum rte_filter_op filter_op,
2725 struct bnxt *bp = dev->data->dev_private;
2728 if (filter_op == RTE_ETH_FILTER_NOP)
2732 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2737 switch (filter_op) {
2738 case RTE_ETH_FILTER_ADD:
2739 ret = bnxt_cfg_ntuple_filter(bp,
2740 (struct rte_eth_ntuple_filter *)arg,
2743 case RTE_ETH_FILTER_DELETE:
2744 ret = bnxt_cfg_ntuple_filter(bp,
2745 (struct rte_eth_ntuple_filter *)arg,
2749 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2757 bnxt_parse_fdir_filter(struct bnxt *bp,
2758 struct rte_eth_fdir_filter *fdir,
2759 struct bnxt_filter_info *filter)
2761 enum rte_fdir_mode fdir_mode =
2762 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2763 struct bnxt_vnic_info *vnic0, *vnic;
2764 struct bnxt_filter_info *filter1;
2768 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2771 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2772 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2774 switch (fdir->input.flow_type) {
2775 case RTE_ETH_FLOW_IPV4:
2776 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2778 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2779 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2780 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2781 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2782 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2783 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2784 filter->ip_addr_type =
2785 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2786 filter->src_ipaddr_mask[0] = 0xffffffff;
2787 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2788 filter->dst_ipaddr_mask[0] = 0xffffffff;
2789 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2790 filter->ethertype = 0x800;
2791 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2793 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2794 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2795 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2796 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2797 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2798 filter->dst_port_mask = 0xffff;
2799 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2800 filter->src_port_mask = 0xffff;
2801 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2802 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2803 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2804 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2805 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2806 filter->ip_protocol = 6;
2807 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2808 filter->ip_addr_type =
2809 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2810 filter->src_ipaddr_mask[0] = 0xffffffff;
2811 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2812 filter->dst_ipaddr_mask[0] = 0xffffffff;
2813 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2814 filter->ethertype = 0x800;
2815 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2817 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2818 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2819 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2820 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2821 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2822 filter->dst_port_mask = 0xffff;
2823 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2824 filter->src_port_mask = 0xffff;
2825 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2826 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2827 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2828 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2829 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2830 filter->ip_protocol = 17;
2831 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2832 filter->ip_addr_type =
2833 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2834 filter->src_ipaddr_mask[0] = 0xffffffff;
2835 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2836 filter->dst_ipaddr_mask[0] = 0xffffffff;
2837 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2838 filter->ethertype = 0x800;
2839 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2841 case RTE_ETH_FLOW_IPV6:
2842 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2844 filter->ip_addr_type =
2845 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2846 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2847 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2848 rte_memcpy(filter->src_ipaddr,
2849 fdir->input.flow.ipv6_flow.src_ip, 16);
2850 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2851 rte_memcpy(filter->dst_ipaddr,
2852 fdir->input.flow.ipv6_flow.dst_ip, 16);
2853 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2854 memset(filter->dst_ipaddr_mask, 0xff, 16);
2855 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2856 memset(filter->src_ipaddr_mask, 0xff, 16);
2857 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2858 filter->ethertype = 0x86dd;
2859 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2861 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2862 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2863 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2864 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2865 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2866 filter->dst_port_mask = 0xffff;
2867 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2868 filter->src_port_mask = 0xffff;
2869 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2870 filter->ip_addr_type =
2871 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2872 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2873 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2874 rte_memcpy(filter->src_ipaddr,
2875 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2876 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2877 rte_memcpy(filter->dst_ipaddr,
2878 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2879 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2880 memset(filter->dst_ipaddr_mask, 0xff, 16);
2881 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2882 memset(filter->src_ipaddr_mask, 0xff, 16);
2883 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2884 filter->ethertype = 0x86dd;
2885 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2887 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2888 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2889 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2890 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2891 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2892 filter->dst_port_mask = 0xffff;
2893 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2894 filter->src_port_mask = 0xffff;
2895 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2896 filter->ip_addr_type =
2897 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2898 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2899 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2900 rte_memcpy(filter->src_ipaddr,
2901 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2902 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2903 rte_memcpy(filter->dst_ipaddr,
2904 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2905 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2906 memset(filter->dst_ipaddr_mask, 0xff, 16);
2907 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2908 memset(filter->src_ipaddr_mask, 0xff, 16);
2909 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2910 filter->ethertype = 0x86dd;
2911 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2913 case RTE_ETH_FLOW_L2_PAYLOAD:
2914 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2915 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2917 case RTE_ETH_FLOW_VXLAN:
2918 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2920 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2921 filter->tunnel_type =
2922 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2923 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2925 case RTE_ETH_FLOW_NVGRE:
2926 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2928 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2929 filter->tunnel_type =
2930 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2931 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2933 case RTE_ETH_FLOW_UNKNOWN:
2934 case RTE_ETH_FLOW_RAW:
2935 case RTE_ETH_FLOW_FRAG_IPV4:
2936 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2937 case RTE_ETH_FLOW_FRAG_IPV6:
2938 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2939 case RTE_ETH_FLOW_IPV6_EX:
2940 case RTE_ETH_FLOW_IPV6_TCP_EX:
2941 case RTE_ETH_FLOW_IPV6_UDP_EX:
2942 case RTE_ETH_FLOW_GENEVE:
2948 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2949 vnic = &bp->vnic_info[fdir->action.rx_queue];
2951 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2955 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2956 rte_memcpy(filter->dst_macaddr,
2957 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2958 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2961 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2962 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2963 filter1 = STAILQ_FIRST(&vnic0->filter);
2964 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2966 filter->dst_id = vnic->fw_vnic_id;
2967 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2968 if (filter->dst_macaddr[i] == 0x00)
2969 filter1 = STAILQ_FIRST(&vnic0->filter);
2971 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2974 if (filter1 == NULL)
2977 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2978 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2980 filter->enables = en;
2985 static struct bnxt_filter_info *
2986 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2987 struct bnxt_vnic_info **mvnic)
2989 struct bnxt_filter_info *mf = NULL;
2992 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2993 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2995 STAILQ_FOREACH(mf, &vnic->filter, next) {
2996 if (mf->filter_type == nf->filter_type &&
2997 mf->flags == nf->flags &&
2998 mf->src_port == nf->src_port &&
2999 mf->src_port_mask == nf->src_port_mask &&
3000 mf->dst_port == nf->dst_port &&
3001 mf->dst_port_mask == nf->dst_port_mask &&
3002 mf->ip_protocol == nf->ip_protocol &&
3003 mf->ip_addr_type == nf->ip_addr_type &&
3004 mf->ethertype == nf->ethertype &&
3005 mf->vni == nf->vni &&
3006 mf->tunnel_type == nf->tunnel_type &&
3007 mf->l2_ovlan == nf->l2_ovlan &&
3008 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3009 mf->l2_ivlan == nf->l2_ivlan &&
3010 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3011 !memcmp(mf->l2_addr, nf->l2_addr,
3012 RTE_ETHER_ADDR_LEN) &&
3013 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3014 RTE_ETHER_ADDR_LEN) &&
3015 !memcmp(mf->src_macaddr, nf->src_macaddr,
3016 RTE_ETHER_ADDR_LEN) &&
3017 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3018 RTE_ETHER_ADDR_LEN) &&
3019 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3020 sizeof(nf->src_ipaddr)) &&
3021 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3022 sizeof(nf->src_ipaddr_mask)) &&
3023 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3024 sizeof(nf->dst_ipaddr)) &&
3025 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3026 sizeof(nf->dst_ipaddr_mask))) {
3037 bnxt_fdir_filter(struct rte_eth_dev *dev,
3038 enum rte_filter_op filter_op,
3041 struct bnxt *bp = dev->data->dev_private;
3042 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3043 struct bnxt_filter_info *filter, *match;
3044 struct bnxt_vnic_info *vnic, *mvnic;
3047 if (filter_op == RTE_ETH_FILTER_NOP)
3050 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3053 switch (filter_op) {
3054 case RTE_ETH_FILTER_ADD:
3055 case RTE_ETH_FILTER_DELETE:
3057 filter = bnxt_get_unused_filter(bp);
3058 if (filter == NULL) {
3060 "Not enough resources for a new flow.\n");
3064 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3067 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3069 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3070 vnic = &bp->vnic_info[0];
3072 vnic = &bp->vnic_info[fdir->action.rx_queue];
3074 match = bnxt_match_fdir(bp, filter, &mvnic);
3075 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3076 if (match->dst_id == vnic->fw_vnic_id) {
3077 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3081 match->dst_id = vnic->fw_vnic_id;
3082 ret = bnxt_hwrm_set_ntuple_filter(bp,
3085 STAILQ_REMOVE(&mvnic->filter, match,
3086 bnxt_filter_info, next);
3087 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3089 "Filter with matching pattern exist\n");
3091 "Updated it to new destination q\n");
3095 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3096 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3101 if (filter_op == RTE_ETH_FILTER_ADD) {
3102 ret = bnxt_hwrm_set_ntuple_filter(bp,
3107 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3109 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3110 STAILQ_REMOVE(&vnic->filter, match,
3111 bnxt_filter_info, next);
3112 bnxt_free_filter(bp, match);
3113 filter->fw_l2_filter_id = -1;
3114 bnxt_free_filter(bp, filter);
3117 case RTE_ETH_FILTER_FLUSH:
3118 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3119 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3121 STAILQ_FOREACH(filter, &vnic->filter, next) {
3122 if (filter->filter_type ==
3123 HWRM_CFA_NTUPLE_FILTER) {
3125 bnxt_hwrm_clear_ntuple_filter(bp,
3127 STAILQ_REMOVE(&vnic->filter, filter,
3128 bnxt_filter_info, next);
3133 case RTE_ETH_FILTER_UPDATE:
3134 case RTE_ETH_FILTER_STATS:
3135 case RTE_ETH_FILTER_INFO:
3136 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3139 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3146 filter->fw_l2_filter_id = -1;
3147 bnxt_free_filter(bp, filter);
3152 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3153 enum rte_filter_type filter_type,
3154 enum rte_filter_op filter_op, void *arg)
3158 ret = is_bnxt_in_error(dev->data->dev_private);
3162 switch (filter_type) {
3163 case RTE_ETH_FILTER_TUNNEL:
3165 "filter type: %d: To be implemented\n", filter_type);
3167 case RTE_ETH_FILTER_FDIR:
3168 ret = bnxt_fdir_filter(dev, filter_op, arg);
3170 case RTE_ETH_FILTER_NTUPLE:
3171 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3173 case RTE_ETH_FILTER_ETHERTYPE:
3174 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3176 case RTE_ETH_FILTER_GENERIC:
3177 if (filter_op != RTE_ETH_FILTER_GET)
3179 *(const void **)arg = &bnxt_flow_ops;
3183 "Filter type (%d) not supported", filter_type);
3190 static const uint32_t *
3191 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3193 static const uint32_t ptypes[] = {
3194 RTE_PTYPE_L2_ETHER_VLAN,
3195 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3196 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3200 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3201 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3202 RTE_PTYPE_INNER_L4_ICMP,
3203 RTE_PTYPE_INNER_L4_TCP,
3204 RTE_PTYPE_INNER_L4_UDP,
3208 if (!dev->rx_pkt_burst)
3214 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3217 uint32_t reg_base = *reg_arr & 0xfffff000;
3221 for (i = 0; i < count; i++) {
3222 if ((reg_arr[i] & 0xfffff000) != reg_base)
3225 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3226 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3230 static int bnxt_map_ptp_regs(struct bnxt *bp)
3232 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3236 reg_arr = ptp->rx_regs;
3237 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3241 reg_arr = ptp->tx_regs;
3242 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3246 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3247 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3249 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3250 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3255 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3257 rte_write32(0, (uint8_t *)bp->bar0 +
3258 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3259 rte_write32(0, (uint8_t *)bp->bar0 +
3260 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3263 static uint64_t bnxt_cc_read(struct bnxt *bp)
3267 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3268 BNXT_GRCPF_REG_SYNC_TIME));
3269 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3270 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3274 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3276 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3279 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3280 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3281 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3284 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3285 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3286 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3287 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3288 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3289 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3294 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3296 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3297 struct bnxt_pf_info *pf = &bp->pf;
3304 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3305 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3306 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3309 port_id = pf->port_id;
3310 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3311 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3313 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3314 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3315 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3316 /* bnxt_clr_rx_ts(bp); TBD */
3320 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3321 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3322 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3323 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3329 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3332 struct bnxt *bp = dev->data->dev_private;
3333 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3338 ns = rte_timespec_to_ns(ts);
3339 /* Set the timecounters to a new value. */
3346 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3348 struct bnxt *bp = dev->data->dev_private;
3349 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3350 uint64_t ns, systime_cycles = 0;
3356 if (BNXT_CHIP_THOR(bp))
3357 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3360 systime_cycles = bnxt_cc_read(bp);
3362 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3363 *ts = rte_ns_to_timespec(ns);
3368 bnxt_timesync_enable(struct rte_eth_dev *dev)
3370 struct bnxt *bp = dev->data->dev_private;
3371 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3379 ptp->tx_tstamp_en = 1;
3380 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3382 rc = bnxt_hwrm_ptp_cfg(bp);
3386 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3387 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3388 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3390 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3391 ptp->tc.cc_shift = shift;
3392 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3394 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3395 ptp->rx_tstamp_tc.cc_shift = shift;
3396 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3398 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3399 ptp->tx_tstamp_tc.cc_shift = shift;
3400 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3402 if (!BNXT_CHIP_THOR(bp))
3403 bnxt_map_ptp_regs(bp);
3409 bnxt_timesync_disable(struct rte_eth_dev *dev)
3411 struct bnxt *bp = dev->data->dev_private;
3412 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3418 ptp->tx_tstamp_en = 0;
3421 bnxt_hwrm_ptp_cfg(bp);
3423 if (!BNXT_CHIP_THOR(bp))
3424 bnxt_unmap_ptp_regs(bp);
3430 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3431 struct timespec *timestamp,
3432 uint32_t flags __rte_unused)
3434 struct bnxt *bp = dev->data->dev_private;
3435 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3436 uint64_t rx_tstamp_cycles = 0;
3442 if (BNXT_CHIP_THOR(bp))
3443 rx_tstamp_cycles = ptp->rx_timestamp;
3445 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3447 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3448 *timestamp = rte_ns_to_timespec(ns);
3453 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3454 struct timespec *timestamp)
3456 struct bnxt *bp = dev->data->dev_private;
3457 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3458 uint64_t tx_tstamp_cycles = 0;
3465 if (BNXT_CHIP_THOR(bp))
3466 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3469 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3471 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3472 *timestamp = rte_ns_to_timespec(ns);
3478 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3480 struct bnxt *bp = dev->data->dev_private;
3481 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3486 ptp->tc.nsec += delta;
3492 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3494 struct bnxt *bp = dev->data->dev_private;
3496 uint32_t dir_entries;
3497 uint32_t entry_length;
3499 rc = is_bnxt_in_error(bp);
3503 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3504 bp->pdev->addr.domain, bp->pdev->addr.bus,
3505 bp->pdev->addr.devid, bp->pdev->addr.function);
3507 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3511 return dir_entries * entry_length;
3515 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3516 struct rte_dev_eeprom_info *in_eeprom)
3518 struct bnxt *bp = dev->data->dev_private;
3523 rc = is_bnxt_in_error(bp);
3527 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3528 "len = %d\n", bp->pdev->addr.domain,
3529 bp->pdev->addr.bus, bp->pdev->addr.devid,
3530 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3532 if (in_eeprom->offset == 0) /* special offset value to get directory */
3533 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3536 index = in_eeprom->offset >> 24;
3537 offset = in_eeprom->offset & 0xffffff;
3540 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3541 in_eeprom->length, in_eeprom->data);
3546 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3549 case BNX_DIR_TYPE_CHIMP_PATCH:
3550 case BNX_DIR_TYPE_BOOTCODE:
3551 case BNX_DIR_TYPE_BOOTCODE_2:
3552 case BNX_DIR_TYPE_APE_FW:
3553 case BNX_DIR_TYPE_APE_PATCH:
3554 case BNX_DIR_TYPE_KONG_FW:
3555 case BNX_DIR_TYPE_KONG_PATCH:
3556 case BNX_DIR_TYPE_BONO_FW:
3557 case BNX_DIR_TYPE_BONO_PATCH:
3565 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3568 case BNX_DIR_TYPE_AVS:
3569 case BNX_DIR_TYPE_EXP_ROM_MBA:
3570 case BNX_DIR_TYPE_PCIE:
3571 case BNX_DIR_TYPE_TSCF_UCODE:
3572 case BNX_DIR_TYPE_EXT_PHY:
3573 case BNX_DIR_TYPE_CCM:
3574 case BNX_DIR_TYPE_ISCSI_BOOT:
3575 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3576 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3584 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3586 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3587 bnxt_dir_type_is_other_exec_format(dir_type);
3591 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3592 struct rte_dev_eeprom_info *in_eeprom)
3594 struct bnxt *bp = dev->data->dev_private;
3595 uint8_t index, dir_op;
3596 uint16_t type, ext, ordinal, attr;
3599 rc = is_bnxt_in_error(bp);
3603 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3604 "len = %d\n", bp->pdev->addr.domain,
3605 bp->pdev->addr.bus, bp->pdev->addr.devid,
3606 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3609 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3613 type = in_eeprom->magic >> 16;
3615 if (type == 0xffff) { /* special value for directory operations */
3616 index = in_eeprom->magic & 0xff;
3617 dir_op = in_eeprom->magic >> 8;
3621 case 0x0e: /* erase */
3622 if (in_eeprom->offset != ~in_eeprom->magic)
3624 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3630 /* Create or re-write an NVM item: */
3631 if (bnxt_dir_type_is_executable(type) == true)
3633 ext = in_eeprom->magic & 0xffff;
3634 ordinal = in_eeprom->offset >> 16;
3635 attr = in_eeprom->offset & 0xffff;
3637 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3638 in_eeprom->data, in_eeprom->length);
3645 static const struct eth_dev_ops bnxt_dev_ops = {
3646 .dev_infos_get = bnxt_dev_info_get_op,
3647 .dev_close = bnxt_dev_close_op,
3648 .dev_configure = bnxt_dev_configure_op,
3649 .dev_start = bnxt_dev_start_op,
3650 .dev_stop = bnxt_dev_stop_op,
3651 .dev_set_link_up = bnxt_dev_set_link_up_op,
3652 .dev_set_link_down = bnxt_dev_set_link_down_op,
3653 .stats_get = bnxt_stats_get_op,
3654 .stats_reset = bnxt_stats_reset_op,
3655 .rx_queue_setup = bnxt_rx_queue_setup_op,
3656 .rx_queue_release = bnxt_rx_queue_release_op,
3657 .tx_queue_setup = bnxt_tx_queue_setup_op,
3658 .tx_queue_release = bnxt_tx_queue_release_op,
3659 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3660 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3661 .reta_update = bnxt_reta_update_op,
3662 .reta_query = bnxt_reta_query_op,
3663 .rss_hash_update = bnxt_rss_hash_update_op,
3664 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3665 .link_update = bnxt_link_update_op,
3666 .promiscuous_enable = bnxt_promiscuous_enable_op,
3667 .promiscuous_disable = bnxt_promiscuous_disable_op,
3668 .allmulticast_enable = bnxt_allmulticast_enable_op,
3669 .allmulticast_disable = bnxt_allmulticast_disable_op,
3670 .mac_addr_add = bnxt_mac_addr_add_op,
3671 .mac_addr_remove = bnxt_mac_addr_remove_op,
3672 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3673 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3674 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3675 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3676 .vlan_filter_set = bnxt_vlan_filter_set_op,
3677 .vlan_offload_set = bnxt_vlan_offload_set_op,
3678 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3679 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3680 .mtu_set = bnxt_mtu_set_op,
3681 .mac_addr_set = bnxt_set_default_mac_addr_op,
3682 .xstats_get = bnxt_dev_xstats_get_op,
3683 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3684 .xstats_reset = bnxt_dev_xstats_reset_op,
3685 .fw_version_get = bnxt_fw_version_get,
3686 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3687 .rxq_info_get = bnxt_rxq_info_get_op,
3688 .txq_info_get = bnxt_txq_info_get_op,
3689 .dev_led_on = bnxt_dev_led_on_op,
3690 .dev_led_off = bnxt_dev_led_off_op,
3691 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3692 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3693 .rx_queue_count = bnxt_rx_queue_count_op,
3694 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3695 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3696 .rx_queue_start = bnxt_rx_queue_start,
3697 .rx_queue_stop = bnxt_rx_queue_stop,
3698 .tx_queue_start = bnxt_tx_queue_start,
3699 .tx_queue_stop = bnxt_tx_queue_stop,
3700 .filter_ctrl = bnxt_filter_ctrl_op,
3701 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3702 .get_eeprom_length = bnxt_get_eeprom_length_op,
3703 .get_eeprom = bnxt_get_eeprom_op,
3704 .set_eeprom = bnxt_set_eeprom_op,
3705 .timesync_enable = bnxt_timesync_enable,
3706 .timesync_disable = bnxt_timesync_disable,
3707 .timesync_read_time = bnxt_timesync_read_time,
3708 .timesync_write_time = bnxt_timesync_write_time,
3709 .timesync_adjust_time = bnxt_timesync_adjust_time,
3710 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3711 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3714 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3718 /* Only pre-map the reset GRC registers using window 3 */
3719 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3720 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3722 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3727 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3729 struct bnxt_error_recovery_info *info = bp->recovery_info;
3730 uint32_t reg_base = 0xffffffff;
3733 /* Only pre-map the monitoring GRC registers using window 2 */
3734 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3735 uint32_t reg = info->status_regs[i];
3737 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3740 if (reg_base == 0xffffffff)
3741 reg_base = reg & 0xfffff000;
3742 if ((reg & 0xfffff000) != reg_base)
3745 /* Use mask 0xffc as the Lower 2 bits indicates
3746 * address space location
3748 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3752 if (reg_base == 0xffffffff)
3755 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3756 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3761 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3763 struct bnxt_error_recovery_info *info = bp->recovery_info;
3764 uint32_t delay = info->delay_after_reset[index];
3765 uint32_t val = info->reset_reg_val[index];
3766 uint32_t reg = info->reset_reg[index];
3767 uint32_t type, offset;
3769 type = BNXT_FW_STATUS_REG_TYPE(reg);
3770 offset = BNXT_FW_STATUS_REG_OFF(reg);
3773 case BNXT_FW_STATUS_REG_TYPE_CFG:
3774 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3776 case BNXT_FW_STATUS_REG_TYPE_GRC:
3777 offset = bnxt_map_reset_regs(bp, offset);
3778 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3780 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3781 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3784 /* wait on a specific interval of time until core reset is complete */
3786 rte_delay_ms(delay);
3789 static void bnxt_dev_cleanup(struct bnxt *bp)
3791 bnxt_set_hwrm_link_config(bp, false);
3792 bp->link_info.link_up = 0;
3793 if (bp->dev_stopped == 0)
3794 bnxt_dev_stop_op(bp->eth_dev);
3796 bnxt_uninit_resources(bp, true);
3799 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3801 struct rte_eth_dev *dev = bp->eth_dev;
3802 struct rte_vlan_filter_conf *vfc;
3806 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3807 vfc = &dev->data->vlan_filter_conf;
3808 vidx = vlan_id / 64;
3809 vbit = vlan_id % 64;
3811 /* Each bit corresponds to a VLAN id */
3812 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3813 rc = bnxt_add_vlan_filter(bp, vlan_id);
3822 static int bnxt_restore_mac_filters(struct bnxt *bp)
3824 struct rte_eth_dev *dev = bp->eth_dev;
3825 struct rte_eth_dev_info dev_info;
3826 struct rte_ether_addr *addr;
3832 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
3835 rc = bnxt_dev_info_get_op(dev, &dev_info);
3839 /* replay MAC address configuration */
3840 for (i = 1; i < dev_info.max_mac_addrs; i++) {
3841 addr = &dev->data->mac_addrs[i];
3843 /* skip zero address */
3844 if (rte_is_zero_ether_addr(addr))
3848 pool_mask = dev->data->mac_pool_sel[i];
3851 if (pool_mask & 1ULL) {
3852 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3858 } while (pool_mask);
3864 static int bnxt_restore_filters(struct bnxt *bp)
3866 struct rte_eth_dev *dev = bp->eth_dev;
3869 if (dev->data->all_multicast)
3870 ret = bnxt_allmulticast_enable_op(dev);
3871 if (dev->data->promiscuous)
3872 ret = bnxt_promiscuous_enable_op(dev);
3874 ret = bnxt_restore_mac_filters(bp);
3878 ret = bnxt_restore_vlan_filters(bp);
3879 /* TODO restore other filters as well */
3883 static void bnxt_dev_recover(void *arg)
3885 struct bnxt *bp = arg;
3886 int timeout = bp->fw_reset_max_msecs;
3889 /* Clear Error flag so that device re-init should happen */
3890 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3893 rc = bnxt_hwrm_ver_get(bp);
3896 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3897 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3898 } while (rc && timeout);
3901 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3905 rc = bnxt_init_resources(bp, true);
3908 "Failed to initialize resources after reset\n");
3911 /* clear reset flag as the device is initialized now */
3912 bp->flags &= ~BNXT_FLAG_FW_RESET;
3914 rc = bnxt_dev_start_op(bp->eth_dev);
3916 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3920 rc = bnxt_restore_filters(bp);
3924 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3927 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3928 bnxt_uninit_resources(bp, false);
3929 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3932 void bnxt_dev_reset_and_resume(void *arg)
3934 struct bnxt *bp = arg;
3937 bnxt_dev_cleanup(bp);
3939 bnxt_wait_for_device_shutdown(bp);
3941 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3942 bnxt_dev_recover, (void *)bp);
3944 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3947 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3949 struct bnxt_error_recovery_info *info = bp->recovery_info;
3950 uint32_t reg = info->status_regs[index];
3951 uint32_t type, offset, val = 0;
3953 type = BNXT_FW_STATUS_REG_TYPE(reg);
3954 offset = BNXT_FW_STATUS_REG_OFF(reg);
3957 case BNXT_FW_STATUS_REG_TYPE_CFG:
3958 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3960 case BNXT_FW_STATUS_REG_TYPE_GRC:
3961 offset = info->mapped_status_regs[index];
3963 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3964 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3972 static int bnxt_fw_reset_all(struct bnxt *bp)
3974 struct bnxt_error_recovery_info *info = bp->recovery_info;
3978 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3979 /* Reset through master function driver */
3980 for (i = 0; i < info->reg_array_cnt; i++)
3981 bnxt_write_fw_reset_reg(bp, i);
3982 /* Wait for time specified by FW after triggering reset */
3983 rte_delay_ms(info->master_func_wait_period_after_reset);
3984 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3985 /* Reset with the help of Kong processor */
3986 rc = bnxt_hwrm_fw_reset(bp);
3988 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3994 static void bnxt_fw_reset_cb(void *arg)
3996 struct bnxt *bp = arg;
3997 struct bnxt_error_recovery_info *info = bp->recovery_info;
4000 /* Only Master function can do FW reset */
4001 if (bnxt_is_master_func(bp) &&
4002 bnxt_is_recovery_enabled(bp)) {
4003 rc = bnxt_fw_reset_all(bp);
4005 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4010 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4011 * EXCEPTION_FATAL_ASYNC event to all the functions
4012 * (including MASTER FUNC). After receiving this Async, all the active
4013 * drivers should treat this case as FW initiated recovery
4015 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4016 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4017 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4019 /* To recover from error */
4020 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4025 /* Driver should poll FW heartbeat, reset_counter with the frequency
4026 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4027 * When the driver detects heartbeat stop or change in reset_counter,
4028 * it has to trigger a reset to recover from the error condition.
4029 * A “master PF” is the function who will have the privilege to
4030 * initiate the chimp reset. The master PF will be elected by the
4031 * firmware and will be notified through async message.
4033 static void bnxt_check_fw_health(void *arg)
4035 struct bnxt *bp = arg;
4036 struct bnxt_error_recovery_info *info = bp->recovery_info;
4037 uint32_t val = 0, wait_msec;
4039 if (!info || !bnxt_is_recovery_enabled(bp) ||
4040 is_bnxt_in_error(bp))
4043 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4044 if (val == info->last_heart_beat)
4047 info->last_heart_beat = val;
4049 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4050 if (val != info->last_reset_counter)
4053 info->last_reset_counter = val;
4055 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4056 bnxt_check_fw_health, (void *)bp);
4060 /* Stop DMA to/from device */
4061 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4062 bp->flags |= BNXT_FLAG_FW_RESET;
4064 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4066 if (bnxt_is_master_func(bp))
4067 wait_msec = info->master_func_wait_period;
4069 wait_msec = info->normal_func_wait_period;
4071 rte_eal_alarm_set(US_PER_MS * wait_msec,
4072 bnxt_fw_reset_cb, (void *)bp);
4075 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4077 uint32_t polling_freq;
4079 if (!bnxt_is_recovery_enabled(bp))
4082 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4085 polling_freq = bp->recovery_info->driver_polling_freq;
4087 rte_eal_alarm_set(US_PER_MS * polling_freq,
4088 bnxt_check_fw_health, (void *)bp);
4089 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4092 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4094 if (!bnxt_is_recovery_enabled(bp))
4097 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4098 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4101 static bool bnxt_vf_pciid(uint16_t device_id)
4103 switch (device_id) {
4104 case BROADCOM_DEV_ID_57304_VF:
4105 case BROADCOM_DEV_ID_57406_VF:
4106 case BROADCOM_DEV_ID_5731X_VF:
4107 case BROADCOM_DEV_ID_5741X_VF:
4108 case BROADCOM_DEV_ID_57414_VF:
4109 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4110 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4111 case BROADCOM_DEV_ID_58802_VF:
4112 case BROADCOM_DEV_ID_57500_VF1:
4113 case BROADCOM_DEV_ID_57500_VF2:
4121 static bool bnxt_thor_device(uint16_t device_id)
4123 switch (device_id) {
4124 case BROADCOM_DEV_ID_57508:
4125 case BROADCOM_DEV_ID_57504:
4126 case BROADCOM_DEV_ID_57502:
4127 case BROADCOM_DEV_ID_57508_MF1:
4128 case BROADCOM_DEV_ID_57504_MF1:
4129 case BROADCOM_DEV_ID_57502_MF1:
4130 case BROADCOM_DEV_ID_57508_MF2:
4131 case BROADCOM_DEV_ID_57504_MF2:
4132 case BROADCOM_DEV_ID_57502_MF2:
4133 case BROADCOM_DEV_ID_57500_VF1:
4134 case BROADCOM_DEV_ID_57500_VF2:
4142 bool bnxt_stratus_device(struct bnxt *bp)
4144 uint16_t device_id = bp->pdev->id.device_id;
4146 switch (device_id) {
4147 case BROADCOM_DEV_ID_STRATUS_NIC:
4148 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4149 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4157 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4159 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4160 struct bnxt *bp = eth_dev->data->dev_private;
4162 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4163 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4164 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4165 if (!bp->bar0 || !bp->doorbell_base) {
4166 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4170 bp->eth_dev = eth_dev;
4176 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4177 struct bnxt_ctx_pg_info *ctx_pg,
4182 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4183 const struct rte_memzone *mz = NULL;
4184 char mz_name[RTE_MEMZONE_NAMESIZE];
4185 rte_iova_t mz_phys_addr;
4186 uint64_t valid_bits = 0;
4193 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4195 rmem->page_size = BNXT_PAGE_SIZE;
4196 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4197 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4198 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4200 valid_bits = PTU_PTE_VALID;
4202 if (rmem->nr_pages > 1) {
4203 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4204 "bnxt_ctx_pg_tbl%s_%x_%d",
4205 suffix, idx, bp->eth_dev->data->port_id);
4206 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4207 mz = rte_memzone_lookup(mz_name);
4209 mz = rte_memzone_reserve_aligned(mz_name,
4213 RTE_MEMZONE_SIZE_HINT_ONLY |
4214 RTE_MEMZONE_IOVA_CONTIG,
4220 memset(mz->addr, 0, mz->len);
4221 mz_phys_addr = mz->iova;
4222 if ((unsigned long)mz->addr == mz_phys_addr) {
4224 "physical address same as virtual\n");
4225 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4226 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4227 if (mz_phys_addr == RTE_BAD_IOVA) {
4229 "unable to map addr to phys memory\n");
4233 rte_mem_lock_page(((char *)mz->addr));
4235 rmem->pg_tbl = mz->addr;
4236 rmem->pg_tbl_map = mz_phys_addr;
4237 rmem->pg_tbl_mz = mz;
4240 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4241 suffix, idx, bp->eth_dev->data->port_id);
4242 mz = rte_memzone_lookup(mz_name);
4244 mz = rte_memzone_reserve_aligned(mz_name,
4248 RTE_MEMZONE_SIZE_HINT_ONLY |
4249 RTE_MEMZONE_IOVA_CONTIG,
4255 memset(mz->addr, 0, mz->len);
4256 mz_phys_addr = mz->iova;
4257 if ((unsigned long)mz->addr == mz_phys_addr) {
4259 "Memzone physical address same as virtual.\n");
4260 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4261 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4262 rte_mem_lock_page(((char *)mz->addr) + sz);
4263 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4264 if (mz_phys_addr == RTE_BAD_IOVA) {
4266 "unable to map addr to phys memory\n");
4271 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4272 rte_mem_lock_page(((char *)mz->addr) + sz);
4273 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4274 rmem->dma_arr[i] = mz_phys_addr + sz;
4276 if (rmem->nr_pages > 1) {
4277 if (i == rmem->nr_pages - 2 &&
4278 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4279 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4280 else if (i == rmem->nr_pages - 1 &&
4281 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4282 valid_bits |= PTU_PTE_LAST;
4284 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4290 if (rmem->vmem_size)
4291 rmem->vmem = (void **)mz->addr;
4292 rmem->dma_arr[0] = mz_phys_addr;
4296 static void bnxt_free_ctx_mem(struct bnxt *bp)
4300 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4303 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4304 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4305 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4306 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4307 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4308 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4309 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4310 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4311 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4312 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4313 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4315 for (i = 0; i < BNXT_MAX_Q; i++) {
4316 if (bp->ctx->tqm_mem[i])
4317 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4324 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4326 #define min_t(type, x, y) ({ \
4327 type __min1 = (x); \
4328 type __min2 = (y); \
4329 __min1 < __min2 ? __min1 : __min2; })
4331 #define max_t(type, x, y) ({ \
4332 type __max1 = (x); \
4333 type __max2 = (y); \
4334 __max1 > __max2 ? __max1 : __max2; })
4336 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4338 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4340 struct bnxt_ctx_pg_info *ctx_pg;
4341 struct bnxt_ctx_mem_info *ctx;
4342 uint32_t mem_size, ena, entries;
4345 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4347 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4351 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4354 ctx_pg = &ctx->qp_mem;
4355 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4356 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4357 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4361 ctx_pg = &ctx->srq_mem;
4362 ctx_pg->entries = ctx->srq_max_l2_entries;
4363 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4364 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4368 ctx_pg = &ctx->cq_mem;
4369 ctx_pg->entries = ctx->cq_max_l2_entries;
4370 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4371 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4375 ctx_pg = &ctx->vnic_mem;
4376 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4377 ctx->vnic_max_ring_table_entries;
4378 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4379 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4383 ctx_pg = &ctx->stat_mem;
4384 ctx_pg->entries = ctx->stat_max_entries;
4385 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4386 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4390 entries = ctx->qp_max_l2_entries +
4391 ctx->vnic_max_vnic_entries +
4392 ctx->tqm_min_entries_per_ring;
4393 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4394 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4395 ctx->tqm_max_entries_per_ring);
4396 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4397 ctx_pg = ctx->tqm_mem[i];
4398 /* use min tqm entries for now. */
4399 ctx_pg->entries = entries;
4400 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4401 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4404 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4407 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4408 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4411 "Failed to configure context mem: rc = %d\n", rc);
4413 ctx->flags |= BNXT_CTX_FLAG_INITED;
4418 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4420 struct rte_pci_device *pci_dev = bp->pdev;
4421 char mz_name[RTE_MEMZONE_NAMESIZE];
4422 const struct rte_memzone *mz = NULL;
4423 uint32_t total_alloc_len;
4424 rte_iova_t mz_phys_addr;
4426 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4429 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4430 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4431 pci_dev->addr.bus, pci_dev->addr.devid,
4432 pci_dev->addr.function, "rx_port_stats");
4433 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4434 mz = rte_memzone_lookup(mz_name);
4436 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4437 sizeof(struct rx_port_stats_ext) + 512);
4439 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4442 RTE_MEMZONE_SIZE_HINT_ONLY |
4443 RTE_MEMZONE_IOVA_CONTIG);
4447 memset(mz->addr, 0, mz->len);
4448 mz_phys_addr = mz->iova;
4449 if ((unsigned long)mz->addr == mz_phys_addr) {
4451 "Memzone physical address same as virtual.\n");
4453 "Using rte_mem_virt2iova()\n");
4454 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4455 if (mz_phys_addr == RTE_BAD_IOVA) {
4457 "Can't map address to physical memory\n");
4462 bp->rx_mem_zone = (const void *)mz;
4463 bp->hw_rx_port_stats = mz->addr;
4464 bp->hw_rx_port_stats_map = mz_phys_addr;
4466 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4467 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4468 pci_dev->addr.bus, pci_dev->addr.devid,
4469 pci_dev->addr.function, "tx_port_stats");
4470 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4471 mz = rte_memzone_lookup(mz_name);
4473 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4474 sizeof(struct tx_port_stats_ext) + 512);
4476 mz = rte_memzone_reserve(mz_name,
4480 RTE_MEMZONE_SIZE_HINT_ONLY |
4481 RTE_MEMZONE_IOVA_CONTIG);
4485 memset(mz->addr, 0, mz->len);
4486 mz_phys_addr = mz->iova;
4487 if ((unsigned long)mz->addr == mz_phys_addr) {
4489 "Memzone physical address same as virtual\n");
4490 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4491 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4492 if (mz_phys_addr == RTE_BAD_IOVA) {
4494 "Can't map address to physical memory\n");
4499 bp->tx_mem_zone = (const void *)mz;
4500 bp->hw_tx_port_stats = mz->addr;
4501 bp->hw_tx_port_stats_map = mz_phys_addr;
4502 bp->flags |= BNXT_FLAG_PORT_STATS;
4504 /* Display extended statistics if FW supports it */
4505 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4506 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4507 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4510 bp->hw_rx_port_stats_ext = (void *)
4511 ((uint8_t *)bp->hw_rx_port_stats +
4512 sizeof(struct rx_port_stats));
4513 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4514 sizeof(struct rx_port_stats);
4515 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4517 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4518 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4519 bp->hw_tx_port_stats_ext = (void *)
4520 ((uint8_t *)bp->hw_tx_port_stats +
4521 sizeof(struct tx_port_stats));
4522 bp->hw_tx_port_stats_ext_map =
4523 bp->hw_tx_port_stats_map +
4524 sizeof(struct tx_port_stats);
4525 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4531 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4533 struct bnxt *bp = eth_dev->data->dev_private;
4536 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4537 RTE_ETHER_ADDR_LEN *
4540 if (eth_dev->data->mac_addrs == NULL) {
4541 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4545 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4549 /* Generate a random MAC address, if none was assigned by PF */
4550 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4551 bnxt_eth_hw_addr_random(bp->mac_addr);
4553 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4554 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4555 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4557 rc = bnxt_hwrm_set_mac(bp);
4559 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4560 RTE_ETHER_ADDR_LEN);
4564 /* Copy the permanent MAC from the FUNC_QCAPS response */
4565 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4566 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4571 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4575 /* MAC is already configured in FW */
4576 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4579 /* Restore the old MAC configured */
4580 rc = bnxt_hwrm_set_mac(bp);
4582 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4587 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4592 #define ALLOW_FUNC(x) \
4594 uint32_t arg = (x); \
4595 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4596 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4599 /* Forward all requests if firmware is new enough */
4600 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4601 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4602 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4603 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4605 PMD_DRV_LOG(WARNING,
4606 "Firmware too old for VF mailbox functionality\n");
4607 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4611 * The following are used for driver cleanup. If we disallow these,
4612 * VF drivers can't clean up cleanly.
4614 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4615 ALLOW_FUNC(HWRM_VNIC_FREE);
4616 ALLOW_FUNC(HWRM_RING_FREE);
4617 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4618 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4619 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4620 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4621 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4622 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4625 static int bnxt_init_fw(struct bnxt *bp)
4630 rc = bnxt_hwrm_ver_get(bp);
4634 rc = bnxt_hwrm_func_reset(bp);
4638 rc = bnxt_hwrm_vnic_qcaps(bp);
4642 rc = bnxt_hwrm_queue_qportcfg(bp);
4646 /* Get the MAX capabilities for this function.
4647 * This function also allocates context memory for TQM rings and
4648 * informs the firmware about this allocated backing store memory.
4650 rc = bnxt_hwrm_func_qcaps(bp);
4654 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4658 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4662 /* Get the adapter error recovery support info */
4663 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4665 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4667 bnxt_hwrm_port_led_qcaps(bp);
4673 bnxt_init_locks(struct bnxt *bp)
4677 err = pthread_mutex_init(&bp->flow_lock, NULL);
4679 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4683 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4685 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4689 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4693 rc = bnxt_init_fw(bp);
4697 if (!reconfig_dev) {
4698 rc = bnxt_setup_mac_addr(bp->eth_dev);
4702 rc = bnxt_restore_dflt_mac(bp);
4707 bnxt_config_vf_req_fwd(bp);
4709 rc = bnxt_hwrm_func_driver_register(bp);
4711 PMD_DRV_LOG(ERR, "Failed to register driver");
4716 if (bp->pdev->max_vfs) {
4717 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4719 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4723 rc = bnxt_hwrm_allocate_pf_only(bp);
4726 "Failed to allocate PF resources");
4732 rc = bnxt_alloc_mem(bp, reconfig_dev);
4736 rc = bnxt_setup_int(bp);
4740 rc = bnxt_request_int(bp);
4744 rc = bnxt_init_locks(bp);
4752 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4754 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4755 static int version_printed;
4759 if (version_printed++ == 0)
4760 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4762 eth_dev->dev_ops = &bnxt_dev_ops;
4763 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4764 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4767 * For secondary processes, we don't initialise any further
4768 * as primary has already done this work.
4770 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4773 rte_eth_copy_pci_info(eth_dev, pci_dev);
4775 bp = eth_dev->data->dev_private;
4777 bp->dev_stopped = 1;
4779 if (bnxt_vf_pciid(pci_dev->id.device_id))
4780 bp->flags |= BNXT_FLAG_VF;
4782 if (bnxt_thor_device(pci_dev->id.device_id))
4783 bp->flags |= BNXT_FLAG_THOR_CHIP;
4785 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4786 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4787 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4788 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4789 bp->flags |= BNXT_FLAG_STINGRAY;
4791 rc = bnxt_init_board(eth_dev);
4794 "Failed to initialize board rc: %x\n", rc);
4798 rc = bnxt_alloc_hwrm_resources(bp);
4801 "Failed to allocate hwrm resource rc: %x\n", rc);
4804 rc = bnxt_init_resources(bp, false);
4808 rc = bnxt_alloc_stats_mem(bp);
4813 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4814 pci_dev->mem_resource[0].phys_addr,
4815 pci_dev->mem_resource[0].addr);
4820 bnxt_dev_uninit(eth_dev);
4825 bnxt_uninit_locks(struct bnxt *bp)
4827 pthread_mutex_destroy(&bp->flow_lock);
4828 pthread_mutex_destroy(&bp->def_cp_lock);
4832 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4837 bnxt_free_mem(bp, reconfig_dev);
4838 bnxt_hwrm_func_buf_unrgtr(bp);
4839 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4840 bp->flags &= ~BNXT_FLAG_REGISTERED;
4841 bnxt_free_ctx_mem(bp);
4842 if (!reconfig_dev) {
4843 bnxt_free_hwrm_resources(bp);
4845 if (bp->recovery_info != NULL) {
4846 rte_free(bp->recovery_info);
4847 bp->recovery_info = NULL;
4851 bnxt_uninit_locks(bp);
4852 rte_free(bp->ptp_cfg);
4858 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4860 struct bnxt *bp = eth_dev->data->dev_private;
4863 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4866 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4868 rc = bnxt_uninit_resources(bp, false);
4870 if (bp->tx_mem_zone) {
4871 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4872 bp->tx_mem_zone = NULL;
4875 if (bp->rx_mem_zone) {
4876 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4877 bp->rx_mem_zone = NULL;
4880 if (bp->dev_stopped == 0)
4881 bnxt_dev_close_op(eth_dev);
4883 rte_free(bp->pf.vf_info);
4884 eth_dev->dev_ops = NULL;
4885 eth_dev->rx_pkt_burst = NULL;
4886 eth_dev->tx_pkt_burst = NULL;
4891 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4892 struct rte_pci_device *pci_dev)
4894 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4898 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4900 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4901 return rte_eth_dev_pci_generic_remove(pci_dev,
4904 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4907 static struct rte_pci_driver bnxt_rte_pmd = {
4908 .id_table = bnxt_pci_id_map,
4909 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4910 .probe = bnxt_pci_probe,
4911 .remove = bnxt_pci_remove,
4915 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4917 if (strcmp(dev->device->driver->name, drv->driver.name))
4923 bool is_bnxt_supported(struct rte_eth_dev *dev)
4925 return is_device_supported(dev, &bnxt_rte_pmd);
4928 RTE_INIT(bnxt_init_log)
4930 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4931 if (bnxt_logtype_driver >= 0)
4932 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4935 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4936 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4937 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");