1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
30 #define DRV_MODULE_NAME "bnxt"
31 static const char bnxt_version[] =
32 "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
33 int bnxt_logtype_driver;
35 #define PCI_VENDOR_ID_BROADCOM 0x14E4
37 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
39 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
40 #define BROADCOM_DEV_ID_57414_VF 0x16c1
41 #define BROADCOM_DEV_ID_57301 0x16c8
42 #define BROADCOM_DEV_ID_57302 0x16c9
43 #define BROADCOM_DEV_ID_57304_PF 0x16ca
44 #define BROADCOM_DEV_ID_57304_VF 0x16cb
45 #define BROADCOM_DEV_ID_57417_MF 0x16cc
46 #define BROADCOM_DEV_ID_NS2 0x16cd
47 #define BROADCOM_DEV_ID_57311 0x16ce
48 #define BROADCOM_DEV_ID_57312 0x16cf
49 #define BROADCOM_DEV_ID_57402 0x16d0
50 #define BROADCOM_DEV_ID_57404 0x16d1
51 #define BROADCOM_DEV_ID_57406_PF 0x16d2
52 #define BROADCOM_DEV_ID_57406_VF 0x16d3
53 #define BROADCOM_DEV_ID_57402_MF 0x16d4
54 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
55 #define BROADCOM_DEV_ID_57412 0x16d6
56 #define BROADCOM_DEV_ID_57414 0x16d7
57 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
58 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
59 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
60 #define BROADCOM_DEV_ID_57412_MF 0x16de
61 #define BROADCOM_DEV_ID_57314 0x16df
62 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
63 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
64 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
65 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
66 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
67 #define BROADCOM_DEV_ID_57404_MF 0x16e7
68 #define BROADCOM_DEV_ID_57406_MF 0x16e8
69 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
70 #define BROADCOM_DEV_ID_57407_MF 0x16ea
71 #define BROADCOM_DEV_ID_57414_MF 0x16ec
72 #define BROADCOM_DEV_ID_57416_MF 0x16ee
73 #define BROADCOM_DEV_ID_58802 0xd802
74 #define BROADCOM_DEV_ID_58804 0xd804
75 #define BROADCOM_DEV_ID_58808 0x16f0
77 static const struct rte_pci_id bnxt_pci_id_map[] = {
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
79 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
81 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
119 { .vendor_id = 0, /* sentinel */ },
122 #define BNXT_ETH_RSS_SUPPORT ( \
124 ETH_RSS_NONFRAG_IPV4_TCP | \
125 ETH_RSS_NONFRAG_IPV4_UDP | \
127 ETH_RSS_NONFRAG_IPV6_TCP | \
128 ETH_RSS_NONFRAG_IPV6_UDP)
130 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
131 DEV_TX_OFFLOAD_IPV4_CKSUM | \
132 DEV_TX_OFFLOAD_TCP_CKSUM | \
133 DEV_TX_OFFLOAD_UDP_CKSUM | \
134 DEV_TX_OFFLOAD_TCP_TSO | \
135 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
136 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
137 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
138 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
139 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
140 DEV_TX_OFFLOAD_MULTI_SEGS)
142 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
143 DEV_RX_OFFLOAD_VLAN_STRIP | \
144 DEV_RX_OFFLOAD_IPV4_CKSUM | \
145 DEV_RX_OFFLOAD_UDP_CKSUM | \
146 DEV_RX_OFFLOAD_TCP_CKSUM | \
147 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
148 DEV_RX_OFFLOAD_JUMBO_FRAME | \
149 DEV_RX_OFFLOAD_CRC_STRIP | \
150 DEV_RX_OFFLOAD_TCP_LRO)
152 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
153 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
155 /***********************/
158 * High level utility functions
161 static void bnxt_free_mem(struct bnxt *bp)
163 bnxt_free_filter_mem(bp);
164 bnxt_free_vnic_attributes(bp);
165 bnxt_free_vnic_mem(bp);
168 bnxt_free_tx_rings(bp);
169 bnxt_free_rx_rings(bp);
170 bnxt_free_def_cp_ring(bp);
173 static int bnxt_alloc_mem(struct bnxt *bp)
177 /* Default completion ring */
178 rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
182 rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
183 bp->def_cp_ring, "def_cp");
187 rc = bnxt_alloc_vnic_mem(bp);
191 rc = bnxt_alloc_vnic_attributes(bp);
195 rc = bnxt_alloc_filter_mem(bp);
206 static int bnxt_init_chip(struct bnxt *bp)
209 struct rte_eth_link new;
210 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
211 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
212 uint32_t intr_vector = 0;
213 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
214 uint32_t vec = BNXT_MISC_VEC_ID;
217 /* disable uio/vfio intr/eventfd mapping */
218 rte_intr_disable(intr_handle);
220 if (bp->eth_dev->data->mtu > ETHER_MTU) {
221 bp->eth_dev->data->dev_conf.rxmode.offloads |=
222 DEV_RX_OFFLOAD_JUMBO_FRAME;
223 bp->flags |= BNXT_FLAG_JUMBO;
225 bp->eth_dev->data->dev_conf.rxmode.offloads &=
226 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
227 bp->flags &= ~BNXT_FLAG_JUMBO;
230 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
232 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
236 rc = bnxt_alloc_hwrm_rings(bp);
238 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
242 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
244 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
248 rc = bnxt_mq_rx_configure(bp);
250 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
254 /* VNIC configuration */
255 for (i = 0; i < bp->nr_vnics; i++) {
256 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
258 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
260 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
265 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
268 "HWRM vnic %d ctx alloc failure rc: %x\n",
273 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
275 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
280 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
283 "HWRM vnic %d filter failure rc: %x\n",
288 rc = bnxt_vnic_rss_configure(bp, vnic);
291 "HWRM vnic set RSS failure rc: %x\n", rc);
295 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
297 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
298 DEV_RX_OFFLOAD_TCP_LRO)
299 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
301 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
303 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
306 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
310 /* check and configure queue intr-vector mapping */
311 if ((rte_intr_cap_multiple(intr_handle) ||
312 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
313 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
314 intr_vector = bp->eth_dev->data->nb_rx_queues;
315 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
316 if (intr_vector > bp->rx_cp_nr_rings) {
317 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
321 if (rte_intr_efd_enable(intr_handle, intr_vector))
325 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
326 intr_handle->intr_vec =
327 rte_zmalloc("intr_vec",
328 bp->eth_dev->data->nb_rx_queues *
330 if (intr_handle->intr_vec == NULL) {
331 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
332 " intr_vec", bp->eth_dev->data->nb_rx_queues);
335 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
336 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
337 intr_handle->intr_vec, intr_handle->nb_efd,
338 intr_handle->max_intr);
341 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
343 intr_handle->intr_vec[queue_id] = vec;
344 if (vec < base + intr_handle->nb_efd - 1)
348 /* enable uio/vfio intr/eventfd mapping */
349 rte_intr_enable(intr_handle);
351 rc = bnxt_get_hwrm_link_config(bp, &new);
353 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
357 if (!bp->link_info.link_up) {
358 rc = bnxt_set_hwrm_link_config(bp, true);
361 "HWRM link config failure rc: %x\n", rc);
365 bnxt_print_link_info(bp->eth_dev);
370 bnxt_free_all_hwrm_resources(bp);
372 /* Some of the error status returned by FW may not be from errno.h */
379 static int bnxt_shutdown_nic(struct bnxt *bp)
381 bnxt_free_all_hwrm_resources(bp);
382 bnxt_free_all_filters(bp);
383 bnxt_free_all_vnics(bp);
387 static int bnxt_init_nic(struct bnxt *bp)
391 rc = bnxt_init_ring_grps(bp);
396 bnxt_init_filters(bp);
402 * Device configuration and status function
405 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
406 struct rte_eth_dev_info *dev_info)
408 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
409 uint16_t max_vnics, i, j, vpool, vrxq;
410 unsigned int max_rx_rings;
413 dev_info->max_mac_addrs = bp->max_l2_ctx;
414 dev_info->max_hash_mac_addrs = 0;
416 /* PF/VF specifics */
418 dev_info->max_vfs = bp->pdev->max_vfs;
419 max_rx_rings = RTE_MIN(bp->max_vnics, RTE_MIN(bp->max_l2_ctx,
420 RTE_MIN(bp->max_rsscos_ctx,
422 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
423 dev_info->max_rx_queues = max_rx_rings;
424 dev_info->max_tx_queues = max_rx_rings;
425 dev_info->reta_size = bp->max_rsscos_ctx;
426 dev_info->hash_key_size = 40;
427 max_vnics = bp->max_vnics;
429 /* Fast path specifics */
430 dev_info->min_rx_bufsize = 1;
431 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
434 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
435 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
436 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
437 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
438 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
441 dev_info->default_rxconf = (struct rte_eth_rxconf) {
447 .rx_free_thresh = 32,
448 /* If no descriptors available, pkts are dropped by default */
452 dev_info->default_txconf = (struct rte_eth_txconf) {
458 .tx_free_thresh = 32,
461 eth_dev->data->dev_conf.intr_conf.lsc = 1;
463 eth_dev->data->dev_conf.intr_conf.rxq = 1;
468 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
469 * need further investigation.
473 vpool = 64; /* ETH_64_POOLS */
474 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
475 for (i = 0; i < 4; vpool >>= 1, i++) {
476 if (max_vnics > vpool) {
477 for (j = 0; j < 5; vrxq >>= 1, j++) {
478 if (dev_info->max_rx_queues > vrxq) {
484 /* Not enough resources to support VMDq */
488 /* Not enough resources to support VMDq */
492 dev_info->max_vmdq_pools = vpool;
493 dev_info->vmdq_queue_num = vrxq;
495 dev_info->vmdq_pool_base = 0;
496 dev_info->vmdq_queue_base = 0;
499 /* Configure the device based on the configuration provided */
500 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
502 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
503 uint64_t tx_offloads = eth_dev->data->dev_conf.txmode.offloads;
504 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
506 if (tx_offloads != (tx_offloads & BNXT_DEV_TX_OFFLOAD_SUPPORT)) {
509 "Tx offloads requested 0x%" PRIx64 " supported 0x%x\n",
510 tx_offloads, BNXT_DEV_TX_OFFLOAD_SUPPORT);
514 if (rx_offloads != (rx_offloads & BNXT_DEV_RX_OFFLOAD_SUPPORT)) {
517 "Rx offloads requested 0x%" PRIx64 " supported 0x%x\n",
518 rx_offloads, BNXT_DEV_RX_OFFLOAD_SUPPORT);
522 bp->rx_queues = (void *)eth_dev->data->rx_queues;
523 bp->tx_queues = (void *)eth_dev->data->tx_queues;
525 /* Inherit new configurations */
526 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
527 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
528 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues + 1 >
530 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
532 (uint32_t)(eth_dev->data->nb_rx_queues + 1) > bp->max_ring_grps) {
534 "Insufficient resources to support requested config\n");
536 "Num Queues Requested: Tx %d, Rx %d\n",
537 eth_dev->data->nb_tx_queues,
538 eth_dev->data->nb_rx_queues);
540 "Res available: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d\n",
541 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
542 bp->max_stat_ctx, bp->max_ring_grps);
546 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
547 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
548 bp->rx_cp_nr_rings = bp->rx_nr_rings;
549 bp->tx_cp_nr_rings = bp->tx_nr_rings;
551 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
553 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
554 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
558 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
560 struct rte_eth_link *link = ð_dev->data->dev_link;
562 if (link->link_status)
563 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
564 eth_dev->data->port_id,
565 (uint32_t)link->link_speed,
566 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
567 ("full-duplex") : ("half-duplex\n"));
569 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
570 eth_dev->data->port_id);
573 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
575 bnxt_print_link_info(eth_dev);
579 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
581 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
582 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
586 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
588 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
589 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
593 rc = bnxt_init_chip(bp);
597 bnxt_link_update_op(eth_dev, 1);
599 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
600 vlan_mask |= ETH_VLAN_FILTER_MASK;
601 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
602 vlan_mask |= ETH_VLAN_STRIP_MASK;
603 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
607 bp->flags |= BNXT_FLAG_INIT_DONE;
611 bnxt_shutdown_nic(bp);
612 bnxt_free_tx_mbufs(bp);
613 bnxt_free_rx_mbufs(bp);
617 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
619 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
622 if (!bp->link_info.link_up)
623 rc = bnxt_set_hwrm_link_config(bp, true);
625 eth_dev->data->dev_link.link_status = 1;
627 bnxt_print_link_info(eth_dev);
631 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
633 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
635 eth_dev->data->dev_link.link_status = 0;
636 bnxt_set_hwrm_link_config(bp, false);
637 bp->link_info.link_up = 0;
642 /* Unload the driver, release resources */
643 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
645 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
647 if (bp->eth_dev->data->dev_started) {
648 /* TBD: STOP HW queues DMA */
649 eth_dev->data->dev_link.link_status = 0;
651 bnxt_set_hwrm_link_config(bp, false);
652 bnxt_hwrm_port_clr_stats(bp);
653 bp->flags &= ~BNXT_FLAG_INIT_DONE;
654 bnxt_shutdown_nic(bp);
658 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
660 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
662 if (bp->dev_stopped == 0)
663 bnxt_dev_stop_op(eth_dev);
665 bnxt_free_tx_mbufs(bp);
666 bnxt_free_rx_mbufs(bp);
668 if (eth_dev->data->mac_addrs != NULL) {
669 rte_free(eth_dev->data->mac_addrs);
670 eth_dev->data->mac_addrs = NULL;
672 if (bp->grp_info != NULL) {
673 rte_free(bp->grp_info);
678 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
681 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
682 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
683 struct bnxt_vnic_info *vnic;
684 struct bnxt_filter_info *filter, *temp_filter;
685 uint32_t pool = RTE_MIN(MAX_FF_POOLS, ETH_64_POOLS);
689 * Loop through all VNICs from the specified filter flow pools to
690 * remove the corresponding MAC addr filter
692 for (i = 0; i < pool; i++) {
693 if (!(pool_mask & (1ULL << i)))
696 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
697 filter = STAILQ_FIRST(&vnic->filter);
699 temp_filter = STAILQ_NEXT(filter, next);
700 if (filter->mac_index == index) {
701 STAILQ_REMOVE(&vnic->filter, filter,
702 bnxt_filter_info, next);
703 bnxt_hwrm_clear_l2_filter(bp, filter);
704 filter->mac_index = INVALID_MAC_INDEX;
705 memset(&filter->l2_addr, 0,
708 &bp->free_filter_list,
711 filter = temp_filter;
717 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
718 struct ether_addr *mac_addr,
719 uint32_t index, uint32_t pool)
721 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
722 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
723 struct bnxt_filter_info *filter;
726 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
731 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
734 /* Attach requested MAC address to the new l2_filter */
735 STAILQ_FOREACH(filter, &vnic->filter, next) {
736 if (filter->mac_index == index) {
738 "MAC addr already existed for pool %d\n", pool);
742 filter = bnxt_alloc_filter(bp);
744 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
747 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
748 filter->mac_index = index;
749 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
750 return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
753 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
756 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
757 struct rte_eth_link new;
758 unsigned int cnt = BNXT_LINK_WAIT_CNT;
760 memset(&new, 0, sizeof(new));
762 /* Retrieve link info from hardware */
763 rc = bnxt_get_hwrm_link_config(bp, &new);
765 new.link_speed = ETH_LINK_SPEED_100M;
766 new.link_duplex = ETH_LINK_FULL_DUPLEX;
768 "Failed to retrieve link rc = 0x%x!\n", rc);
771 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
773 if (!wait_to_complete)
775 } while (!new.link_status && cnt--);
778 /* Timed out or success */
779 if (new.link_status != eth_dev->data->dev_link.link_status ||
780 new.link_speed != eth_dev->data->dev_link.link_speed) {
781 memcpy(ð_dev->data->dev_link, &new,
782 sizeof(struct rte_eth_link));
783 bnxt_print_link_info(eth_dev);
789 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
791 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
792 struct bnxt_vnic_info *vnic;
794 if (bp->vnic_info == NULL)
797 vnic = &bp->vnic_info[0];
799 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
800 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
803 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
805 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
806 struct bnxt_vnic_info *vnic;
808 if (bp->vnic_info == NULL)
811 vnic = &bp->vnic_info[0];
813 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
814 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
817 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
819 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
820 struct bnxt_vnic_info *vnic;
822 if (bp->vnic_info == NULL)
825 vnic = &bp->vnic_info[0];
827 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
828 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
831 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
833 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
834 struct bnxt_vnic_info *vnic;
836 if (bp->vnic_info == NULL)
839 vnic = &bp->vnic_info[0];
841 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
842 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
845 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
846 struct rte_eth_rss_reta_entry64 *reta_conf,
849 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
850 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
851 struct bnxt_vnic_info *vnic;
854 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
857 if (reta_size != HW_HASH_INDEX_SIZE) {
858 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
859 "(%d) must equal the size supported by the hardware "
860 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
863 /* Update the RSS VNIC(s) */
864 for (i = 0; i < MAX_FF_POOLS; i++) {
865 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
866 memcpy(vnic->rss_table, reta_conf, reta_size);
868 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
874 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
875 struct rte_eth_rss_reta_entry64 *reta_conf,
878 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
879 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
880 struct rte_intr_handle *intr_handle
881 = &bp->pdev->intr_handle;
883 /* Retrieve from the default VNIC */
886 if (!vnic->rss_table)
889 if (reta_size != HW_HASH_INDEX_SIZE) {
890 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
891 "(%d) must equal the size supported by the hardware "
892 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
895 /* EW - need to revisit here copying from uint64_t to uint16_t */
896 memcpy(reta_conf, vnic->rss_table, reta_size);
898 if (rte_intr_allow_others(intr_handle)) {
899 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
900 bnxt_dev_lsc_intr_setup(eth_dev);
906 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
907 struct rte_eth_rss_conf *rss_conf)
909 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
910 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
911 struct bnxt_vnic_info *vnic;
912 uint16_t hash_type = 0;
916 * If RSS enablement were different than dev_configure,
917 * then return -EINVAL
919 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
920 if (!rss_conf->rss_hf)
921 PMD_DRV_LOG(ERR, "Hash type NONE\n");
923 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
927 bp->flags |= BNXT_FLAG_UPDATE_HASH;
928 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
930 if (rss_conf->rss_hf & ETH_RSS_IPV4)
931 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
932 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
933 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
934 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
935 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
936 if (rss_conf->rss_hf & ETH_RSS_IPV6)
937 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
938 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
939 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
940 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
941 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
943 /* Update the RSS VNIC(s) */
944 for (i = 0; i < MAX_FF_POOLS; i++) {
945 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
946 vnic->hash_type = hash_type;
949 * Use the supplied key if the key length is
950 * acceptable and the rss_key is not NULL
952 if (rss_conf->rss_key &&
953 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
954 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
955 rss_conf->rss_key_len);
957 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
963 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
964 struct rte_eth_rss_conf *rss_conf)
966 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
967 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
971 /* RSS configuration is the same for all VNICs */
972 if (vnic && vnic->rss_hash_key) {
973 if (rss_conf->rss_key) {
974 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
975 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
976 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
979 hash_types = vnic->hash_type;
980 rss_conf->rss_hf = 0;
981 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
982 rss_conf->rss_hf |= ETH_RSS_IPV4;
983 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
985 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
986 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
988 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
990 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
991 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
993 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
995 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
996 rss_conf->rss_hf |= ETH_RSS_IPV6;
997 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
999 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1000 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1002 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1004 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1005 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1007 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1011 "Unknwon RSS config from firmware (%08x), RSS disabled",
1016 rss_conf->rss_hf = 0;
1021 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1022 struct rte_eth_fc_conf *fc_conf)
1024 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1025 struct rte_eth_link link_info;
1028 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1032 memset(fc_conf, 0, sizeof(*fc_conf));
1033 if (bp->link_info.auto_pause)
1034 fc_conf->autoneg = 1;
1035 switch (bp->link_info.pause) {
1037 fc_conf->mode = RTE_FC_NONE;
1039 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1040 fc_conf->mode = RTE_FC_TX_PAUSE;
1042 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1043 fc_conf->mode = RTE_FC_RX_PAUSE;
1045 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1046 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1047 fc_conf->mode = RTE_FC_FULL;
1053 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1054 struct rte_eth_fc_conf *fc_conf)
1056 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1058 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1059 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1063 switch (fc_conf->mode) {
1065 bp->link_info.auto_pause = 0;
1066 bp->link_info.force_pause = 0;
1068 case RTE_FC_RX_PAUSE:
1069 if (fc_conf->autoneg) {
1070 bp->link_info.auto_pause =
1071 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1072 bp->link_info.force_pause = 0;
1074 bp->link_info.auto_pause = 0;
1075 bp->link_info.force_pause =
1076 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1079 case RTE_FC_TX_PAUSE:
1080 if (fc_conf->autoneg) {
1081 bp->link_info.auto_pause =
1082 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1083 bp->link_info.force_pause = 0;
1085 bp->link_info.auto_pause = 0;
1086 bp->link_info.force_pause =
1087 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1091 if (fc_conf->autoneg) {
1092 bp->link_info.auto_pause =
1093 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1094 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1095 bp->link_info.force_pause = 0;
1097 bp->link_info.auto_pause = 0;
1098 bp->link_info.force_pause =
1099 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1100 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1104 return bnxt_set_hwrm_link_config(bp, true);
1107 /* Add UDP tunneling port */
1109 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1110 struct rte_eth_udp_tunnel *udp_tunnel)
1112 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1113 uint16_t tunnel_type = 0;
1116 switch (udp_tunnel->prot_type) {
1117 case RTE_TUNNEL_TYPE_VXLAN:
1118 if (bp->vxlan_port_cnt) {
1119 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1120 udp_tunnel->udp_port);
1121 if (bp->vxlan_port != udp_tunnel->udp_port) {
1122 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1125 bp->vxlan_port_cnt++;
1129 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1130 bp->vxlan_port_cnt++;
1132 case RTE_TUNNEL_TYPE_GENEVE:
1133 if (bp->geneve_port_cnt) {
1134 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1135 udp_tunnel->udp_port);
1136 if (bp->geneve_port != udp_tunnel->udp_port) {
1137 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1140 bp->geneve_port_cnt++;
1144 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1145 bp->geneve_port_cnt++;
1148 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1151 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1157 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1158 struct rte_eth_udp_tunnel *udp_tunnel)
1160 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1161 uint16_t tunnel_type = 0;
1165 switch (udp_tunnel->prot_type) {
1166 case RTE_TUNNEL_TYPE_VXLAN:
1167 if (!bp->vxlan_port_cnt) {
1168 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1171 if (bp->vxlan_port != udp_tunnel->udp_port) {
1172 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1173 udp_tunnel->udp_port, bp->vxlan_port);
1176 if (--bp->vxlan_port_cnt)
1180 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1181 port = bp->vxlan_fw_dst_port_id;
1183 case RTE_TUNNEL_TYPE_GENEVE:
1184 if (!bp->geneve_port_cnt) {
1185 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1188 if (bp->geneve_port != udp_tunnel->udp_port) {
1189 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1190 udp_tunnel->udp_port, bp->geneve_port);
1193 if (--bp->geneve_port_cnt)
1197 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1198 port = bp->geneve_fw_dst_port_id;
1201 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1205 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1208 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1211 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1212 bp->geneve_port = 0;
1217 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1219 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1220 struct bnxt_vnic_info *vnic;
1223 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1225 /* Cycle through all VNICs */
1226 for (i = 0; i < bp->nr_vnics; i++) {
1228 * For each VNIC and each associated filter(s)
1229 * if VLAN exists && VLAN matches vlan_id
1230 * remove the MAC+VLAN filter
1231 * add a new MAC only filter
1233 * VLAN filter doesn't exist, just skip and continue
1235 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1236 filter = STAILQ_FIRST(&vnic->filter);
1238 temp_filter = STAILQ_NEXT(filter, next);
1240 if (filter->enables & chk &&
1241 filter->l2_ovlan == vlan_id) {
1242 /* Must delete the filter */
1243 STAILQ_REMOVE(&vnic->filter, filter,
1244 bnxt_filter_info, next);
1245 bnxt_hwrm_clear_l2_filter(bp, filter);
1247 &bp->free_filter_list,
1251 * Need to examine to see if the MAC
1252 * filter already existed or not before
1253 * allocating a new one
1256 new_filter = bnxt_alloc_filter(bp);
1259 "MAC/VLAN filter alloc failed\n");
1263 STAILQ_INSERT_TAIL(&vnic->filter,
1265 /* Inherit MAC from previous filter */
1266 new_filter->mac_index =
1268 memcpy(new_filter->l2_addr,
1269 filter->l2_addr, ETHER_ADDR_LEN);
1270 /* MAC only filter */
1271 rc = bnxt_hwrm_set_l2_filter(bp,
1277 "Del Vlan filter for %d\n",
1280 filter = temp_filter;
1288 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1290 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1291 struct bnxt_vnic_info *vnic;
1294 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN |
1295 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK;
1296 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1298 /* Cycle through all VNICs */
1299 for (i = 0; i < bp->nr_vnics; i++) {
1301 * For each VNIC and each associated filter(s)
1303 * if VLAN matches vlan_id
1304 * VLAN filter already exists, just skip and continue
1306 * add a new MAC+VLAN filter
1308 * Remove the old MAC only filter
1309 * Add a new MAC+VLAN filter
1311 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1312 filter = STAILQ_FIRST(&vnic->filter);
1314 temp_filter = STAILQ_NEXT(filter, next);
1316 if (filter->enables & chk) {
1317 if (filter->l2_ovlan == vlan_id)
1320 /* Must delete the MAC filter */
1321 STAILQ_REMOVE(&vnic->filter, filter,
1322 bnxt_filter_info, next);
1323 bnxt_hwrm_clear_l2_filter(bp, filter);
1324 filter->l2_ovlan = 0;
1326 &bp->free_filter_list,
1329 new_filter = bnxt_alloc_filter(bp);
1332 "MAC/VLAN filter alloc failed\n");
1336 STAILQ_INSERT_TAIL(&vnic->filter, new_filter,
1338 /* Inherit MAC from the previous filter */
1339 new_filter->mac_index = filter->mac_index;
1340 memcpy(new_filter->l2_addr, filter->l2_addr,
1342 /* MAC + VLAN ID filter */
1343 new_filter->l2_ovlan = vlan_id;
1344 new_filter->l2_ovlan_mask = 0xF000;
1345 new_filter->enables |= en;
1346 rc = bnxt_hwrm_set_l2_filter(bp,
1352 "Added Vlan filter for %d\n", vlan_id);
1354 filter = temp_filter;
1362 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1363 uint16_t vlan_id, int on)
1365 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1367 /* These operations apply to ALL existing MAC/VLAN filters */
1369 return bnxt_add_vlan_filter(bp, vlan_id);
1371 return bnxt_del_vlan_filter(bp, vlan_id);
1375 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1377 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1378 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1381 if (mask & ETH_VLAN_FILTER_MASK) {
1382 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1383 /* Remove any VLAN filters programmed */
1384 for (i = 0; i < 4095; i++)
1385 bnxt_del_vlan_filter(bp, i);
1387 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1388 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1391 if (mask & ETH_VLAN_STRIP_MASK) {
1392 /* Enable or disable VLAN stripping */
1393 for (i = 0; i < bp->nr_vnics; i++) {
1394 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1395 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1396 vnic->vlan_strip = true;
1398 vnic->vlan_strip = false;
1399 bnxt_hwrm_vnic_cfg(bp, vnic);
1401 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1402 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1405 if (mask & ETH_VLAN_EXTEND_MASK)
1406 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1412 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr)
1414 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1415 /* Default Filter is tied to VNIC 0 */
1416 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1417 struct bnxt_filter_info *filter;
1423 memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1425 STAILQ_FOREACH(filter, &vnic->filter, next) {
1426 /* Default Filter is at Index 0 */
1427 if (filter->mac_index != 0)
1429 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1432 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN);
1433 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN);
1434 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1436 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1437 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1438 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1441 filter->mac_index = 0;
1442 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1449 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1450 struct ether_addr *mc_addr_set,
1451 uint32_t nb_mc_addr)
1453 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1454 char *mc_addr_list = (char *)mc_addr_set;
1455 struct bnxt_vnic_info *vnic;
1456 uint32_t off = 0, i = 0;
1458 vnic = &bp->vnic_info[0];
1460 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1461 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1465 /* TODO Check for Duplicate mcast addresses */
1466 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1467 for (i = 0; i < nb_mc_addr; i++) {
1468 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN);
1469 off += ETHER_ADDR_LEN;
1472 vnic->mc_addr_cnt = i;
1475 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1479 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1481 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1482 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1483 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1484 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1487 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1488 fw_major, fw_minor, fw_updt);
1490 ret += 1; /* add the size of '\0' */
1491 if (fw_size < (uint32_t)ret)
1498 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1499 struct rte_eth_rxq_info *qinfo)
1501 struct bnxt_rx_queue *rxq;
1503 rxq = dev->data->rx_queues[queue_id];
1505 qinfo->mp = rxq->mb_pool;
1506 qinfo->scattered_rx = dev->data->scattered_rx;
1507 qinfo->nb_desc = rxq->nb_rx_desc;
1509 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1510 qinfo->conf.rx_drop_en = 0;
1511 qinfo->conf.rx_deferred_start = 0;
1515 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1516 struct rte_eth_txq_info *qinfo)
1518 struct bnxt_tx_queue *txq;
1520 txq = dev->data->tx_queues[queue_id];
1522 qinfo->nb_desc = txq->nb_tx_desc;
1524 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1525 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1526 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1528 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1529 qinfo->conf.tx_rs_thresh = 0;
1530 qinfo->conf.txq_flags = txq->txq_flags;
1531 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1534 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1536 struct bnxt *bp = eth_dev->data->dev_private;
1537 struct rte_eth_dev_info dev_info;
1538 uint32_t max_dev_mtu;
1542 bnxt_dev_info_get_op(eth_dev, &dev_info);
1543 max_dev_mtu = dev_info.max_rx_pktlen -
1544 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2;
1546 if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) {
1547 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1548 ETHER_MIN_MTU, max_dev_mtu);
1553 if (new_mtu > ETHER_MTU) {
1554 bp->flags |= BNXT_FLAG_JUMBO;
1555 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1556 DEV_RX_OFFLOAD_JUMBO_FRAME;
1558 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1559 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1560 bp->flags &= ~BNXT_FLAG_JUMBO;
1563 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
1564 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1566 eth_dev->data->mtu = new_mtu;
1567 PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1569 for (i = 0; i < bp->nr_vnics; i++) {
1570 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1572 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1573 ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1574 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1578 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1587 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1589 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1590 uint16_t vlan = bp->vlan;
1593 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1595 "PVID cannot be modified for this function\n");
1598 bp->vlan = on ? pvid : 0;
1600 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1607 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1609 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1611 return bnxt_hwrm_port_led_cfg(bp, true);
1615 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1617 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1619 return bnxt_hwrm_port_led_cfg(bp, false);
1623 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1625 uint32_t desc = 0, raw_cons = 0, cons;
1626 struct bnxt_cp_ring_info *cpr;
1627 struct bnxt_rx_queue *rxq;
1628 struct rx_pkt_cmpl *rxcmp;
1633 rxq = dev->data->rx_queues[rx_queue_id];
1637 while (raw_cons < rxq->nb_rx_desc) {
1638 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1639 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1641 if (!CMPL_VALID(rxcmp, valid))
1643 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1644 cmp_type = CMP_TYPE(rxcmp);
1645 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1646 cmp = (rte_le_to_cpu_32(
1647 ((struct rx_tpa_end_cmpl *)
1648 (rxcmp))->agg_bufs_v1) &
1649 RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1650 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1652 } else if (cmp_type == 0x11) {
1654 cmp = (rxcmp->agg_bufs_v1 &
1655 RX_PKT_CMPL_AGG_BUFS_MASK) >>
1656 RX_PKT_CMPL_AGG_BUFS_SFT;
1661 raw_cons += cmp ? cmp : 2;
1668 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1670 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1671 struct bnxt_rx_ring_info *rxr;
1672 struct bnxt_cp_ring_info *cpr;
1673 struct bnxt_sw_rx_bd *rx_buf;
1674 struct rx_pkt_cmpl *rxcmp;
1675 uint32_t cons, cp_cons;
1683 if (offset >= rxq->nb_rx_desc)
1686 cons = RING_CMP(cpr->cp_ring_struct, offset);
1687 cp_cons = cpr->cp_raw_cons;
1688 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1690 if (cons > cp_cons) {
1691 if (CMPL_VALID(rxcmp, cpr->valid))
1692 return RTE_ETH_RX_DESC_DONE;
1694 if (CMPL_VALID(rxcmp, !cpr->valid))
1695 return RTE_ETH_RX_DESC_DONE;
1697 rx_buf = &rxr->rx_buf_ring[cons];
1698 if (rx_buf->mbuf == NULL)
1699 return RTE_ETH_RX_DESC_UNAVAIL;
1702 return RTE_ETH_RX_DESC_AVAIL;
1706 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1708 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1709 struct bnxt_tx_ring_info *txr;
1710 struct bnxt_cp_ring_info *cpr;
1711 struct bnxt_sw_tx_bd *tx_buf;
1712 struct tx_pkt_cmpl *txcmp;
1713 uint32_t cons, cp_cons;
1721 if (offset >= txq->nb_tx_desc)
1724 cons = RING_CMP(cpr->cp_ring_struct, offset);
1725 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1726 cp_cons = cpr->cp_raw_cons;
1728 if (cons > cp_cons) {
1729 if (CMPL_VALID(txcmp, cpr->valid))
1730 return RTE_ETH_TX_DESC_UNAVAIL;
1732 if (CMPL_VALID(txcmp, !cpr->valid))
1733 return RTE_ETH_TX_DESC_UNAVAIL;
1735 tx_buf = &txr->tx_buf_ring[cons];
1736 if (tx_buf->mbuf == NULL)
1737 return RTE_ETH_TX_DESC_DONE;
1739 return RTE_ETH_TX_DESC_FULL;
1742 static struct bnxt_filter_info *
1743 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1744 struct rte_eth_ethertype_filter *efilter,
1745 struct bnxt_vnic_info *vnic0,
1746 struct bnxt_vnic_info *vnic,
1749 struct bnxt_filter_info *mfilter = NULL;
1753 if (efilter->ether_type == ETHER_TYPE_IPv4 ||
1754 efilter->ether_type == ETHER_TYPE_IPv6) {
1755 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
1756 " ethertype filter.", efilter->ether_type);
1760 if (efilter->queue >= bp->rx_nr_rings) {
1761 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1766 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1767 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1769 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1774 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1775 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1776 if ((!memcmp(efilter->mac_addr.addr_bytes,
1777 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1779 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1780 mfilter->ethertype == efilter->ether_type)) {
1786 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1787 if ((!memcmp(efilter->mac_addr.addr_bytes,
1788 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1789 mfilter->ethertype == efilter->ether_type &&
1791 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
1805 bnxt_ethertype_filter(struct rte_eth_dev *dev,
1806 enum rte_filter_op filter_op,
1809 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1810 struct rte_eth_ethertype_filter *efilter =
1811 (struct rte_eth_ethertype_filter *)arg;
1812 struct bnxt_filter_info *bfilter, *filter1;
1813 struct bnxt_vnic_info *vnic, *vnic0;
1816 if (filter_op == RTE_ETH_FILTER_NOP)
1820 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
1825 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1826 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1828 switch (filter_op) {
1829 case RTE_ETH_FILTER_ADD:
1830 bnxt_match_and_validate_ether_filter(bp, efilter,
1835 bfilter = bnxt_get_unused_filter(bp);
1836 if (bfilter == NULL) {
1838 "Not enough resources for a new filter.\n");
1841 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
1842 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
1844 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
1846 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
1847 bfilter->ethertype = efilter->ether_type;
1848 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
1850 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
1851 if (filter1 == NULL) {
1856 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
1857 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
1859 bfilter->dst_id = vnic->fw_vnic_id;
1861 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1863 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
1866 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
1869 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
1871 case RTE_ETH_FILTER_DELETE:
1872 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
1874 if (ret == -EEXIST) {
1875 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
1877 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
1879 bnxt_free_filter(bp, filter1);
1880 } else if (ret == 0) {
1881 PMD_DRV_LOG(ERR, "No matching filter found\n");
1885 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
1891 bnxt_free_filter(bp, bfilter);
1897 parse_ntuple_filter(struct bnxt *bp,
1898 struct rte_eth_ntuple_filter *nfilter,
1899 struct bnxt_filter_info *bfilter)
1903 if (nfilter->queue >= bp->rx_nr_rings) {
1904 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
1908 switch (nfilter->dst_port_mask) {
1910 bfilter->dst_port_mask = -1;
1911 bfilter->dst_port = nfilter->dst_port;
1912 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
1913 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
1916 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
1920 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
1921 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1923 switch (nfilter->proto_mask) {
1925 if (nfilter->proto == 17) /* IPPROTO_UDP */
1926 bfilter->ip_protocol = 17;
1927 else if (nfilter->proto == 6) /* IPPROTO_TCP */
1928 bfilter->ip_protocol = 6;
1931 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1934 PMD_DRV_LOG(ERR, "invalid protocol mask.");
1938 switch (nfilter->dst_ip_mask) {
1940 bfilter->dst_ipaddr_mask[0] = -1;
1941 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
1942 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
1943 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
1946 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
1950 switch (nfilter->src_ip_mask) {
1952 bfilter->src_ipaddr_mask[0] = -1;
1953 bfilter->src_ipaddr[0] = nfilter->src_ip;
1954 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
1955 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
1958 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
1962 switch (nfilter->src_port_mask) {
1964 bfilter->src_port_mask = -1;
1965 bfilter->src_port = nfilter->src_port;
1966 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
1967 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
1970 PMD_DRV_LOG(ERR, "invalid src_port mask.");
1975 //nfilter->priority = (uint8_t)filter->priority;
1977 bfilter->enables = en;
1981 static struct bnxt_filter_info*
1982 bnxt_match_ntuple_filter(struct bnxt *bp,
1983 struct bnxt_filter_info *bfilter,
1984 struct bnxt_vnic_info **mvnic)
1986 struct bnxt_filter_info *mfilter = NULL;
1989 for (i = bp->nr_vnics - 1; i >= 0; i--) {
1990 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1991 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
1992 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
1993 bfilter->src_ipaddr_mask[0] ==
1994 mfilter->src_ipaddr_mask[0] &&
1995 bfilter->src_port == mfilter->src_port &&
1996 bfilter->src_port_mask == mfilter->src_port_mask &&
1997 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
1998 bfilter->dst_ipaddr_mask[0] ==
1999 mfilter->dst_ipaddr_mask[0] &&
2000 bfilter->dst_port == mfilter->dst_port &&
2001 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2002 bfilter->flags == mfilter->flags &&
2003 bfilter->enables == mfilter->enables) {
2014 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2015 struct rte_eth_ntuple_filter *nfilter,
2016 enum rte_filter_op filter_op)
2018 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2019 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2022 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2023 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2027 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2028 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2032 bfilter = bnxt_get_unused_filter(bp);
2033 if (bfilter == NULL) {
2035 "Not enough resources for a new filter.\n");
2038 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2042 vnic = STAILQ_FIRST(&bp->ff_pool[nfilter->queue]);
2043 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2044 filter1 = STAILQ_FIRST(&vnic0->filter);
2045 if (filter1 == NULL) {
2050 bfilter->dst_id = vnic->fw_vnic_id;
2051 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2053 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2054 bfilter->ethertype = 0x800;
2055 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2057 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2059 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2060 bfilter->dst_id == mfilter->dst_id) {
2061 PMD_DRV_LOG(ERR, "filter exists.\n");
2064 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2065 bfilter->dst_id != mfilter->dst_id) {
2066 mfilter->dst_id = vnic->fw_vnic_id;
2067 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2068 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2069 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2070 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2071 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2074 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2075 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2080 if (filter_op == RTE_ETH_FILTER_ADD) {
2081 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2082 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2085 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2087 if (mfilter == NULL) {
2088 /* This should not happen. But for Coverity! */
2092 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2094 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2095 bnxt_free_filter(bp, mfilter);
2096 mfilter->fw_l2_filter_id = -1;
2097 bnxt_free_filter(bp, bfilter);
2098 bfilter->fw_l2_filter_id = -1;
2103 bfilter->fw_l2_filter_id = -1;
2104 bnxt_free_filter(bp, bfilter);
2109 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2110 enum rte_filter_op filter_op,
2113 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2116 if (filter_op == RTE_ETH_FILTER_NOP)
2120 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2125 switch (filter_op) {
2126 case RTE_ETH_FILTER_ADD:
2127 ret = bnxt_cfg_ntuple_filter(bp,
2128 (struct rte_eth_ntuple_filter *)arg,
2131 case RTE_ETH_FILTER_DELETE:
2132 ret = bnxt_cfg_ntuple_filter(bp,
2133 (struct rte_eth_ntuple_filter *)arg,
2137 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2145 bnxt_parse_fdir_filter(struct bnxt *bp,
2146 struct rte_eth_fdir_filter *fdir,
2147 struct bnxt_filter_info *filter)
2149 enum rte_fdir_mode fdir_mode =
2150 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2151 struct bnxt_vnic_info *vnic0, *vnic;
2152 struct bnxt_filter_info *filter1;
2156 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2159 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2160 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2162 switch (fdir->input.flow_type) {
2163 case RTE_ETH_FLOW_IPV4:
2164 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2166 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2167 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2168 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2169 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2170 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2171 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2172 filter->ip_addr_type =
2173 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2174 filter->src_ipaddr_mask[0] = 0xffffffff;
2175 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2176 filter->dst_ipaddr_mask[0] = 0xffffffff;
2177 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2178 filter->ethertype = 0x800;
2179 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2181 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2182 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2183 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2184 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2185 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2186 filter->dst_port_mask = 0xffff;
2187 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2188 filter->src_port_mask = 0xffff;
2189 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2190 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2191 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2192 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2193 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2194 filter->ip_protocol = 6;
2195 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2196 filter->ip_addr_type =
2197 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2198 filter->src_ipaddr_mask[0] = 0xffffffff;
2199 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2200 filter->dst_ipaddr_mask[0] = 0xffffffff;
2201 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2202 filter->ethertype = 0x800;
2203 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2205 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2206 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2207 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2208 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2209 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2210 filter->dst_port_mask = 0xffff;
2211 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2212 filter->src_port_mask = 0xffff;
2213 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2214 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2215 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2216 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2217 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2218 filter->ip_protocol = 17;
2219 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2220 filter->ip_addr_type =
2221 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2222 filter->src_ipaddr_mask[0] = 0xffffffff;
2223 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2224 filter->dst_ipaddr_mask[0] = 0xffffffff;
2225 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2226 filter->ethertype = 0x800;
2227 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2229 case RTE_ETH_FLOW_IPV6:
2230 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2232 filter->ip_addr_type =
2233 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2234 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2235 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2236 rte_memcpy(filter->src_ipaddr,
2237 fdir->input.flow.ipv6_flow.src_ip, 16);
2238 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2239 rte_memcpy(filter->dst_ipaddr,
2240 fdir->input.flow.ipv6_flow.dst_ip, 16);
2241 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2242 memset(filter->dst_ipaddr_mask, 0xff, 16);
2243 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2244 memset(filter->src_ipaddr_mask, 0xff, 16);
2245 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2246 filter->ethertype = 0x86dd;
2247 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2249 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2250 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2251 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2252 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2253 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2254 filter->dst_port_mask = 0xffff;
2255 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2256 filter->src_port_mask = 0xffff;
2257 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2258 filter->ip_addr_type =
2259 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2260 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2261 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2262 rte_memcpy(filter->src_ipaddr,
2263 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2264 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2265 rte_memcpy(filter->dst_ipaddr,
2266 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2267 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2268 memset(filter->dst_ipaddr_mask, 0xff, 16);
2269 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2270 memset(filter->src_ipaddr_mask, 0xff, 16);
2271 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2272 filter->ethertype = 0x86dd;
2273 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2275 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2276 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2277 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2278 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2279 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2280 filter->dst_port_mask = 0xffff;
2281 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2282 filter->src_port_mask = 0xffff;
2283 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2284 filter->ip_addr_type =
2285 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2286 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2287 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2288 rte_memcpy(filter->src_ipaddr,
2289 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2290 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2291 rte_memcpy(filter->dst_ipaddr,
2292 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2293 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2294 memset(filter->dst_ipaddr_mask, 0xff, 16);
2295 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2296 memset(filter->src_ipaddr_mask, 0xff, 16);
2297 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2298 filter->ethertype = 0x86dd;
2299 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2301 case RTE_ETH_FLOW_L2_PAYLOAD:
2302 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2303 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2305 case RTE_ETH_FLOW_VXLAN:
2306 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2308 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2309 filter->tunnel_type =
2310 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2311 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2313 case RTE_ETH_FLOW_NVGRE:
2314 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2316 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2317 filter->tunnel_type =
2318 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2319 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2321 case RTE_ETH_FLOW_UNKNOWN:
2322 case RTE_ETH_FLOW_RAW:
2323 case RTE_ETH_FLOW_FRAG_IPV4:
2324 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2325 case RTE_ETH_FLOW_FRAG_IPV6:
2326 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2327 case RTE_ETH_FLOW_IPV6_EX:
2328 case RTE_ETH_FLOW_IPV6_TCP_EX:
2329 case RTE_ETH_FLOW_IPV6_UDP_EX:
2330 case RTE_ETH_FLOW_GENEVE:
2336 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2337 vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2339 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2344 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2345 rte_memcpy(filter->dst_macaddr,
2346 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2347 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2350 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2351 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2352 filter1 = STAILQ_FIRST(&vnic0->filter);
2353 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2355 filter->dst_id = vnic->fw_vnic_id;
2356 for (i = 0; i < ETHER_ADDR_LEN; i++)
2357 if (filter->dst_macaddr[i] == 0x00)
2358 filter1 = STAILQ_FIRST(&vnic0->filter);
2360 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2363 if (filter1 == NULL)
2366 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2367 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2369 filter->enables = en;
2374 static struct bnxt_filter_info *
2375 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2376 struct bnxt_vnic_info **mvnic)
2378 struct bnxt_filter_info *mf = NULL;
2381 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2382 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2384 STAILQ_FOREACH(mf, &vnic->filter, next) {
2385 if (mf->filter_type == nf->filter_type &&
2386 mf->flags == nf->flags &&
2387 mf->src_port == nf->src_port &&
2388 mf->src_port_mask == nf->src_port_mask &&
2389 mf->dst_port == nf->dst_port &&
2390 mf->dst_port_mask == nf->dst_port_mask &&
2391 mf->ip_protocol == nf->ip_protocol &&
2392 mf->ip_addr_type == nf->ip_addr_type &&
2393 mf->ethertype == nf->ethertype &&
2394 mf->vni == nf->vni &&
2395 mf->tunnel_type == nf->tunnel_type &&
2396 mf->l2_ovlan == nf->l2_ovlan &&
2397 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2398 mf->l2_ivlan == nf->l2_ivlan &&
2399 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2400 !memcmp(mf->l2_addr, nf->l2_addr, ETHER_ADDR_LEN) &&
2401 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2403 !memcmp(mf->src_macaddr, nf->src_macaddr,
2405 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2407 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2408 sizeof(nf->src_ipaddr)) &&
2409 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2410 sizeof(nf->src_ipaddr_mask)) &&
2411 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2412 sizeof(nf->dst_ipaddr)) &&
2413 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2414 sizeof(nf->dst_ipaddr_mask))) {
2425 bnxt_fdir_filter(struct rte_eth_dev *dev,
2426 enum rte_filter_op filter_op,
2429 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2430 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2431 struct bnxt_filter_info *filter, *match;
2432 struct bnxt_vnic_info *vnic, *mvnic;
2435 if (filter_op == RTE_ETH_FILTER_NOP)
2438 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2441 switch (filter_op) {
2442 case RTE_ETH_FILTER_ADD:
2443 case RTE_ETH_FILTER_DELETE:
2444 filter = bnxt_get_unused_filter(bp);
2445 if (filter == NULL) {
2447 "Not enough resources for a new flow.\n");
2451 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2454 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2456 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2457 vnic = STAILQ_FIRST(&bp->ff_pool[0]);
2459 vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2461 match = bnxt_match_fdir(bp, filter, &mvnic);
2462 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2463 if (match->dst_id == vnic->fw_vnic_id) {
2464 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2468 match->dst_id = vnic->fw_vnic_id;
2469 ret = bnxt_hwrm_set_ntuple_filter(bp,
2472 STAILQ_REMOVE(&mvnic->filter, match,
2473 bnxt_filter_info, next);
2474 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2476 "Filter with matching pattern exist\n");
2478 "Updated it to new destination q\n");
2482 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2483 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2488 if (filter_op == RTE_ETH_FILTER_ADD) {
2489 ret = bnxt_hwrm_set_ntuple_filter(bp,
2494 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2496 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2497 STAILQ_REMOVE(&vnic->filter, match,
2498 bnxt_filter_info, next);
2499 bnxt_free_filter(bp, match);
2500 filter->fw_l2_filter_id = -1;
2501 bnxt_free_filter(bp, filter);
2504 case RTE_ETH_FILTER_FLUSH:
2505 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2506 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2508 STAILQ_FOREACH(filter, &vnic->filter, next) {
2509 if (filter->filter_type ==
2510 HWRM_CFA_NTUPLE_FILTER) {
2512 bnxt_hwrm_clear_ntuple_filter(bp,
2514 STAILQ_REMOVE(&vnic->filter, filter,
2515 bnxt_filter_info, next);
2520 case RTE_ETH_FILTER_UPDATE:
2521 case RTE_ETH_FILTER_STATS:
2522 case RTE_ETH_FILTER_INFO:
2523 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2526 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2533 filter->fw_l2_filter_id = -1;
2534 bnxt_free_filter(bp, filter);
2539 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2540 enum rte_filter_type filter_type,
2541 enum rte_filter_op filter_op, void *arg)
2545 switch (filter_type) {
2546 case RTE_ETH_FILTER_TUNNEL:
2548 "filter type: %d: To be implemented\n", filter_type);
2550 case RTE_ETH_FILTER_FDIR:
2551 ret = bnxt_fdir_filter(dev, filter_op, arg);
2553 case RTE_ETH_FILTER_NTUPLE:
2554 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2556 case RTE_ETH_FILTER_ETHERTYPE:
2557 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2559 case RTE_ETH_FILTER_GENERIC:
2560 if (filter_op != RTE_ETH_FILTER_GET)
2562 *(const void **)arg = &bnxt_flow_ops;
2566 "Filter type (%d) not supported", filter_type);
2573 static const uint32_t *
2574 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2576 static const uint32_t ptypes[] = {
2577 RTE_PTYPE_L2_ETHER_VLAN,
2578 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2579 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2583 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2584 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2585 RTE_PTYPE_INNER_L4_ICMP,
2586 RTE_PTYPE_INNER_L4_TCP,
2587 RTE_PTYPE_INNER_L4_UDP,
2591 if (dev->rx_pkt_burst == bnxt_recv_pkts)
2596 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2599 uint32_t reg_base = *reg_arr & 0xfffff000;
2603 for (i = 0; i < count; i++) {
2604 if ((reg_arr[i] & 0xfffff000) != reg_base)
2607 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2608 rte_cpu_to_le_32(rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off));
2612 static int bnxt_map_ptp_regs(struct bnxt *bp)
2614 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2618 reg_arr = ptp->rx_regs;
2619 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2623 reg_arr = ptp->tx_regs;
2624 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2628 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2629 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2631 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2632 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2637 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2639 rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2640 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16));
2641 rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2642 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20));
2645 static uint64_t bnxt_cc_read(struct bnxt *bp)
2649 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2650 BNXT_GRCPF_REG_SYNC_TIME));
2651 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2652 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2656 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2658 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2661 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2662 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2663 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2666 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2667 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2668 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2669 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2670 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2671 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2676 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2678 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2679 struct bnxt_pf_info *pf = &bp->pf;
2686 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2687 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2688 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2691 port_id = pf->port_id;
2692 rte_cpu_to_le_32(rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2693 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]));
2695 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2696 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2697 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2698 /* bnxt_clr_rx_ts(bp); TBD */
2702 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2703 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2704 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2705 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2711 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2714 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2715 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2720 ns = rte_timespec_to_ns(ts);
2721 /* Set the timecounters to a new value. */
2728 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2730 uint64_t ns, systime_cycles;
2731 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2732 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2737 systime_cycles = bnxt_cc_read(bp);
2738 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
2739 *ts = rte_ns_to_timespec(ns);
2744 bnxt_timesync_enable(struct rte_eth_dev *dev)
2746 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2747 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2754 ptp->tx_tstamp_en = 1;
2755 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
2757 if (!bnxt_hwrm_ptp_cfg(bp))
2758 bnxt_map_ptp_regs(bp);
2760 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
2761 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2762 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2764 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2765 ptp->tc.cc_shift = shift;
2766 ptp->tc.nsec_mask = (1ULL << shift) - 1;
2768 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2769 ptp->rx_tstamp_tc.cc_shift = shift;
2770 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2772 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2773 ptp->tx_tstamp_tc.cc_shift = shift;
2774 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2780 bnxt_timesync_disable(struct rte_eth_dev *dev)
2782 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2783 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2789 ptp->tx_tstamp_en = 0;
2792 bnxt_hwrm_ptp_cfg(bp);
2794 bnxt_unmap_ptp_regs(bp);
2800 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
2801 struct timespec *timestamp,
2802 uint32_t flags __rte_unused)
2804 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2805 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2806 uint64_t rx_tstamp_cycles = 0;
2812 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
2813 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
2814 *timestamp = rte_ns_to_timespec(ns);
2819 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
2820 struct timespec *timestamp)
2822 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2823 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2824 uint64_t tx_tstamp_cycles = 0;
2830 bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
2831 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
2832 *timestamp = rte_ns_to_timespec(ns);
2838 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
2840 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2841 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2846 ptp->tc.nsec += delta;
2852 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
2854 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2856 uint32_t dir_entries;
2857 uint32_t entry_length;
2859 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
2860 bp->pdev->addr.domain, bp->pdev->addr.bus,
2861 bp->pdev->addr.devid, bp->pdev->addr.function);
2863 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
2867 return dir_entries * entry_length;
2871 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
2872 struct rte_dev_eeprom_info *in_eeprom)
2874 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2878 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2879 "len = %d\n", bp->pdev->addr.domain,
2880 bp->pdev->addr.bus, bp->pdev->addr.devid,
2881 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2883 if (in_eeprom->offset == 0) /* special offset value to get directory */
2884 return bnxt_get_nvram_directory(bp, in_eeprom->length,
2887 index = in_eeprom->offset >> 24;
2888 offset = in_eeprom->offset & 0xffffff;
2891 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
2892 in_eeprom->length, in_eeprom->data);
2897 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
2900 case BNX_DIR_TYPE_CHIMP_PATCH:
2901 case BNX_DIR_TYPE_BOOTCODE:
2902 case BNX_DIR_TYPE_BOOTCODE_2:
2903 case BNX_DIR_TYPE_APE_FW:
2904 case BNX_DIR_TYPE_APE_PATCH:
2905 case BNX_DIR_TYPE_KONG_FW:
2906 case BNX_DIR_TYPE_KONG_PATCH:
2907 case BNX_DIR_TYPE_BONO_FW:
2908 case BNX_DIR_TYPE_BONO_PATCH:
2915 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
2918 case BNX_DIR_TYPE_AVS:
2919 case BNX_DIR_TYPE_EXP_ROM_MBA:
2920 case BNX_DIR_TYPE_PCIE:
2921 case BNX_DIR_TYPE_TSCF_UCODE:
2922 case BNX_DIR_TYPE_EXT_PHY:
2923 case BNX_DIR_TYPE_CCM:
2924 case BNX_DIR_TYPE_ISCSI_BOOT:
2925 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2926 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2933 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
2935 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2936 bnxt_dir_type_is_other_exec_format(dir_type);
2940 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
2941 struct rte_dev_eeprom_info *in_eeprom)
2943 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2944 uint8_t index, dir_op;
2945 uint16_t type, ext, ordinal, attr;
2947 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2948 "len = %d\n", bp->pdev->addr.domain,
2949 bp->pdev->addr.bus, bp->pdev->addr.devid,
2950 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2953 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
2957 type = in_eeprom->magic >> 16;
2959 if (type == 0xffff) { /* special value for directory operations */
2960 index = in_eeprom->magic & 0xff;
2961 dir_op = in_eeprom->magic >> 8;
2965 case 0x0e: /* erase */
2966 if (in_eeprom->offset != ~in_eeprom->magic)
2968 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
2974 /* Create or re-write an NVM item: */
2975 if (bnxt_dir_type_is_executable(type) == true)
2977 ext = in_eeprom->magic & 0xffff;
2978 ordinal = in_eeprom->offset >> 16;
2979 attr = in_eeprom->offset & 0xffff;
2981 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
2982 in_eeprom->data, in_eeprom->length);
2990 static const struct eth_dev_ops bnxt_dev_ops = {
2991 .dev_infos_get = bnxt_dev_info_get_op,
2992 .dev_close = bnxt_dev_close_op,
2993 .dev_configure = bnxt_dev_configure_op,
2994 .dev_start = bnxt_dev_start_op,
2995 .dev_stop = bnxt_dev_stop_op,
2996 .dev_set_link_up = bnxt_dev_set_link_up_op,
2997 .dev_set_link_down = bnxt_dev_set_link_down_op,
2998 .stats_get = bnxt_stats_get_op,
2999 .stats_reset = bnxt_stats_reset_op,
3000 .rx_queue_setup = bnxt_rx_queue_setup_op,
3001 .rx_queue_release = bnxt_rx_queue_release_op,
3002 .tx_queue_setup = bnxt_tx_queue_setup_op,
3003 .tx_queue_release = bnxt_tx_queue_release_op,
3004 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3005 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3006 .reta_update = bnxt_reta_update_op,
3007 .reta_query = bnxt_reta_query_op,
3008 .rss_hash_update = bnxt_rss_hash_update_op,
3009 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3010 .link_update = bnxt_link_update_op,
3011 .promiscuous_enable = bnxt_promiscuous_enable_op,
3012 .promiscuous_disable = bnxt_promiscuous_disable_op,
3013 .allmulticast_enable = bnxt_allmulticast_enable_op,
3014 .allmulticast_disable = bnxt_allmulticast_disable_op,
3015 .mac_addr_add = bnxt_mac_addr_add_op,
3016 .mac_addr_remove = bnxt_mac_addr_remove_op,
3017 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3018 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3019 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3020 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3021 .vlan_filter_set = bnxt_vlan_filter_set_op,
3022 .vlan_offload_set = bnxt_vlan_offload_set_op,
3023 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3024 .mtu_set = bnxt_mtu_set_op,
3025 .mac_addr_set = bnxt_set_default_mac_addr_op,
3026 .xstats_get = bnxt_dev_xstats_get_op,
3027 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3028 .xstats_reset = bnxt_dev_xstats_reset_op,
3029 .fw_version_get = bnxt_fw_version_get,
3030 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3031 .rxq_info_get = bnxt_rxq_info_get_op,
3032 .txq_info_get = bnxt_txq_info_get_op,
3033 .dev_led_on = bnxt_dev_led_on_op,
3034 .dev_led_off = bnxt_dev_led_off_op,
3035 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3036 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3037 .rx_queue_count = bnxt_rx_queue_count_op,
3038 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3039 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3040 .rx_queue_start = bnxt_rx_queue_start,
3041 .rx_queue_stop = bnxt_rx_queue_stop,
3042 .tx_queue_start = bnxt_tx_queue_start,
3043 .tx_queue_stop = bnxt_tx_queue_stop,
3044 .filter_ctrl = bnxt_filter_ctrl_op,
3045 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3046 .get_eeprom_length = bnxt_get_eeprom_length_op,
3047 .get_eeprom = bnxt_get_eeprom_op,
3048 .set_eeprom = bnxt_set_eeprom_op,
3049 .timesync_enable = bnxt_timesync_enable,
3050 .timesync_disable = bnxt_timesync_disable,
3051 .timesync_read_time = bnxt_timesync_read_time,
3052 .timesync_write_time = bnxt_timesync_write_time,
3053 .timesync_adjust_time = bnxt_timesync_adjust_time,
3054 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3055 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3058 static bool bnxt_vf_pciid(uint16_t id)
3060 if (id == BROADCOM_DEV_ID_57304_VF ||
3061 id == BROADCOM_DEV_ID_57406_VF ||
3062 id == BROADCOM_DEV_ID_5731X_VF ||
3063 id == BROADCOM_DEV_ID_5741X_VF ||
3064 id == BROADCOM_DEV_ID_57414_VF ||
3065 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3066 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3071 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3073 struct bnxt *bp = eth_dev->data->dev_private;
3074 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3077 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3078 if (!pci_dev->mem_resource[0].addr) {
3080 "Cannot find PCI device base address, aborting\n");
3082 goto init_err_disable;
3085 bp->eth_dev = eth_dev;
3088 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3090 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3092 goto init_err_release;
3095 if (!pci_dev->mem_resource[2].addr) {
3097 "Cannot find PCI device BAR 2 address, aborting\n");
3099 goto init_err_release;
3101 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3109 if (bp->doorbell_base)
3110 bp->doorbell_base = NULL;
3117 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
3119 #define ALLOW_FUNC(x) \
3121 typeof(x) arg = (x); \
3122 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3123 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3126 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3128 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3129 char mz_name[RTE_MEMZONE_NAMESIZE];
3130 const struct rte_memzone *mz = NULL;
3131 static int version_printed;
3132 uint32_t total_alloc_len;
3133 rte_iova_t mz_phys_addr;
3137 if (version_printed++ == 0)
3138 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3140 rte_eth_copy_pci_info(eth_dev, pci_dev);
3142 bp = eth_dev->data->dev_private;
3144 bp->dev_stopped = 1;
3146 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3149 if (bnxt_vf_pciid(pci_dev->id.device_id))
3150 bp->flags |= BNXT_FLAG_VF;
3152 rc = bnxt_init_board(eth_dev);
3155 "Board initialization failed rc: %x\n", rc);
3159 eth_dev->dev_ops = &bnxt_dev_ops;
3160 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3162 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3163 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3165 if (BNXT_PF(bp) && pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3166 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3167 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3168 pci_dev->addr.bus, pci_dev->addr.devid,
3169 pci_dev->addr.function, "rx_port_stats");
3170 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3171 mz = rte_memzone_lookup(mz_name);
3172 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3173 sizeof(struct rx_port_stats) + 512);
3175 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3178 RTE_MEMZONE_SIZE_HINT_ONLY |
3179 RTE_MEMZONE_IOVA_CONTIG);
3183 memset(mz->addr, 0, mz->len);
3184 mz_phys_addr = mz->iova;
3185 if ((unsigned long)mz->addr == mz_phys_addr) {
3186 PMD_DRV_LOG(WARNING,
3187 "Memzone physical address same as virtual.\n");
3188 PMD_DRV_LOG(WARNING,
3189 "Using rte_mem_virt2iova()\n");
3190 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3191 if (mz_phys_addr == 0) {
3193 "unable to map address to physical memory\n");
3198 bp->rx_mem_zone = (const void *)mz;
3199 bp->hw_rx_port_stats = mz->addr;
3200 bp->hw_rx_port_stats_map = mz_phys_addr;
3202 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3203 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3204 pci_dev->addr.bus, pci_dev->addr.devid,
3205 pci_dev->addr.function, "tx_port_stats");
3206 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3207 mz = rte_memzone_lookup(mz_name);
3208 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3209 sizeof(struct tx_port_stats) + 512);
3211 mz = rte_memzone_reserve(mz_name,
3215 RTE_MEMZONE_SIZE_HINT_ONLY |
3216 RTE_MEMZONE_IOVA_CONTIG);
3220 memset(mz->addr, 0, mz->len);
3221 mz_phys_addr = mz->iova;
3222 if ((unsigned long)mz->addr == mz_phys_addr) {
3223 PMD_DRV_LOG(WARNING,
3224 "Memzone physical address same as virtual.\n");
3225 PMD_DRV_LOG(WARNING,
3226 "Using rte_mem_virt2iova()\n");
3227 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3228 if (mz_phys_addr == 0) {
3230 "unable to map address to physical memory\n");
3235 bp->tx_mem_zone = (const void *)mz;
3236 bp->hw_tx_port_stats = mz->addr;
3237 bp->hw_tx_port_stats_map = mz_phys_addr;
3239 bp->flags |= BNXT_FLAG_PORT_STATS;
3242 rc = bnxt_alloc_hwrm_resources(bp);
3245 "hwrm resource allocation failure rc: %x\n", rc);
3248 rc = bnxt_hwrm_ver_get(bp);
3251 rc = bnxt_hwrm_queue_qportcfg(bp);
3253 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3257 rc = bnxt_hwrm_func_qcfg(bp);
3259 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3263 /* Get the MAX capabilities for this function */
3264 rc = bnxt_hwrm_func_qcaps(bp);
3266 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3269 if (bp->max_tx_rings == 0) {
3270 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3274 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3275 ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3276 if (eth_dev->data->mac_addrs == NULL) {
3278 "Failed to alloc %u bytes needed to store MAC addr tbl",
3279 ETHER_ADDR_LEN * bp->max_l2_ctx);
3284 if (check_zero_bytes(bp->dflt_mac_addr, ETHER_ADDR_LEN)) {
3286 "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
3287 bp->dflt_mac_addr[0], bp->dflt_mac_addr[1],
3288 bp->dflt_mac_addr[2], bp->dflt_mac_addr[3],
3289 bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]);
3293 /* Copy the permanent MAC from the qcap response address now. */
3294 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3295 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
3297 if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3298 /* 1 ring is for default completion ring */
3299 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3304 bp->grp_info = rte_zmalloc("bnxt_grp_info",
3305 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3306 if (!bp->grp_info) {
3308 "Failed to alloc %zu bytes to store group info table\n",
3309 sizeof(*bp->grp_info) * bp->max_ring_grps);
3314 /* Forward all requests if firmware is new enough */
3315 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3316 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3317 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3318 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3320 PMD_DRV_LOG(WARNING,
3321 "Firmware too old for VF mailbox functionality\n");
3322 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3326 * The following are used for driver cleanup. If we disallow these,
3327 * VF drivers can't clean up cleanly.
3329 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3330 ALLOW_FUNC(HWRM_VNIC_FREE);
3331 ALLOW_FUNC(HWRM_RING_FREE);
3332 ALLOW_FUNC(HWRM_RING_GRP_FREE);
3333 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3334 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3335 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3336 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3337 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3338 rc = bnxt_hwrm_func_driver_register(bp);
3341 "Failed to register driver");
3347 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3348 pci_dev->mem_resource[0].phys_addr,
3349 pci_dev->mem_resource[0].addr);
3351 rc = bnxt_hwrm_func_reset(bp);
3353 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3359 //if (bp->pf.active_vfs) {
3360 // TODO: Deallocate VF resources?
3362 if (bp->pdev->max_vfs) {
3363 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3365 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3369 rc = bnxt_hwrm_allocate_pf_only(bp);
3372 "Failed to allocate PF resources\n");
3378 bnxt_hwrm_port_led_qcaps(bp);
3380 rc = bnxt_setup_int(bp);
3384 rc = bnxt_alloc_mem(bp);
3386 goto error_free_int;
3388 rc = bnxt_request_int(bp);
3390 goto error_free_int;
3392 rc = bnxt_alloc_def_cp_ring(bp);
3394 goto error_free_int;
3396 bnxt_enable_int(bp);
3402 bnxt_disable_int(bp);
3403 bnxt_free_def_cp_ring(bp);
3404 bnxt_hwrm_func_buf_unrgtr(bp);
3408 bnxt_dev_uninit(eth_dev);
3414 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
3415 struct bnxt *bp = eth_dev->data->dev_private;
3418 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3421 bnxt_disable_int(bp);
3424 if (eth_dev->data->mac_addrs != NULL) {
3425 rte_free(eth_dev->data->mac_addrs);
3426 eth_dev->data->mac_addrs = NULL;
3428 if (bp->grp_info != NULL) {
3429 rte_free(bp->grp_info);
3430 bp->grp_info = NULL;
3432 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3433 bnxt_free_hwrm_resources(bp);
3434 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3435 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3436 if (bp->dev_stopped == 0)
3437 bnxt_dev_close_op(eth_dev);
3439 rte_free(bp->pf.vf_info);
3440 eth_dev->dev_ops = NULL;
3441 eth_dev->rx_pkt_burst = NULL;
3442 eth_dev->tx_pkt_burst = NULL;
3447 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3448 struct rte_pci_device *pci_dev)
3450 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
3454 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
3456 return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
3459 static struct rte_pci_driver bnxt_rte_pmd = {
3460 .id_table = bnxt_pci_id_map,
3461 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
3462 RTE_PCI_DRV_INTR_LSC,
3463 .probe = bnxt_pci_probe,
3464 .remove = bnxt_pci_remove,
3468 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
3470 if (strcmp(dev->device->driver->name, drv->driver.name))
3476 bool is_bnxt_supported(struct rte_eth_dev *dev)
3478 return is_device_supported(dev, &bnxt_rte_pmd);
3481 RTE_INIT(bnxt_init_log);
3485 bnxt_logtype_driver = rte_log_register("pmd.bnxt.driver");
3486 if (bnxt_logtype_driver >= 0)
3487 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_INFO);
3490 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
3491 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
3492 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");