1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
30 #define DRV_MODULE_NAME "bnxt"
31 static const char bnxt_version[] =
32 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
33 int bnxt_logtype_driver;
36 * The set of PCI devices this driver supports
38 static const struct rte_pci_id bnxt_pci_id_map[] = {
39 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
40 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
41 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
42 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
43 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
45 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
92 { .vendor_id = 0, /* sentinel */ },
95 #define BNXT_ETH_RSS_SUPPORT ( \
97 ETH_RSS_NONFRAG_IPV4_TCP | \
98 ETH_RSS_NONFRAG_IPV4_UDP | \
100 ETH_RSS_NONFRAG_IPV6_TCP | \
101 ETH_RSS_NONFRAG_IPV6_UDP)
103 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
104 DEV_TX_OFFLOAD_IPV4_CKSUM | \
105 DEV_TX_OFFLOAD_TCP_CKSUM | \
106 DEV_TX_OFFLOAD_UDP_CKSUM | \
107 DEV_TX_OFFLOAD_TCP_TSO | \
108 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
109 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
110 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
111 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
112 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
113 DEV_TX_OFFLOAD_QINQ_INSERT | \
114 DEV_TX_OFFLOAD_MULTI_SEGS)
116 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
117 DEV_RX_OFFLOAD_VLAN_STRIP | \
118 DEV_RX_OFFLOAD_IPV4_CKSUM | \
119 DEV_RX_OFFLOAD_UDP_CKSUM | \
120 DEV_RX_OFFLOAD_TCP_CKSUM | \
121 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
122 DEV_RX_OFFLOAD_JUMBO_FRAME | \
123 DEV_RX_OFFLOAD_KEEP_CRC | \
124 DEV_RX_OFFLOAD_VLAN_EXTEND | \
125 DEV_RX_OFFLOAD_TCP_LRO | \
126 DEV_RX_OFFLOAD_SCATTER | \
127 DEV_RX_OFFLOAD_RSS_HASH)
129 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
130 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
131 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
132 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
133 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
134 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
136 int is_bnxt_in_error(struct bnxt *bp)
138 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
140 if (bp->flags & BNXT_FLAG_FW_RESET)
146 /***********************/
149 * High level utility functions
152 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
154 if (!BNXT_CHIP_THOR(bp))
157 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
158 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
159 BNXT_RSS_ENTRIES_PER_CTX_THOR;
162 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
164 if (!BNXT_CHIP_THOR(bp))
165 return HW_HASH_INDEX_SIZE;
167 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
170 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
172 bnxt_free_filter_mem(bp);
173 bnxt_free_vnic_attributes(bp);
174 bnxt_free_vnic_mem(bp);
176 /* tx/rx rings are configured as part of *_queue_setup callbacks.
177 * If the number of rings change across fw update,
178 * we don't have much choice except to warn the user.
182 bnxt_free_tx_rings(bp);
183 bnxt_free_rx_rings(bp);
185 bnxt_free_async_cp_ring(bp);
186 bnxt_free_rxtx_nq_ring(bp);
188 rte_free(bp->grp_info);
192 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
196 rc = bnxt_alloc_ring_grps(bp);
200 rc = bnxt_alloc_async_ring_struct(bp);
204 rc = bnxt_alloc_vnic_mem(bp);
208 rc = bnxt_alloc_vnic_attributes(bp);
212 rc = bnxt_alloc_filter_mem(bp);
216 rc = bnxt_alloc_async_cp_ring(bp);
220 rc = bnxt_alloc_rxtx_nq_ring(bp);
227 bnxt_free_mem(bp, reconfig);
231 static int bnxt_init_chip(struct bnxt *bp)
233 struct bnxt_rx_queue *rxq;
234 struct rte_eth_link new;
235 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
236 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
237 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
238 uint64_t rx_offloads = dev_conf->rxmode.offloads;
239 uint32_t intr_vector = 0;
240 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
241 uint32_t vec = BNXT_MISC_VEC_ID;
245 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
246 bp->eth_dev->data->dev_conf.rxmode.offloads |=
247 DEV_RX_OFFLOAD_JUMBO_FRAME;
248 bp->flags |= BNXT_FLAG_JUMBO;
250 bp->eth_dev->data->dev_conf.rxmode.offloads &=
251 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
252 bp->flags &= ~BNXT_FLAG_JUMBO;
255 /* THOR does not support ring groups.
256 * But we will use the array to save RSS context IDs.
258 if (BNXT_CHIP_THOR(bp))
259 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
261 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
263 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
267 rc = bnxt_alloc_hwrm_rings(bp);
269 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
273 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
275 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
279 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
282 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
283 if (bp->rx_cos_queue[i].id != 0xff) {
284 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
288 "Num pools more than FW profile\n");
292 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
298 rc = bnxt_mq_rx_configure(bp);
300 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
304 /* VNIC configuration */
305 for (i = 0; i < bp->nr_vnics; i++) {
306 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
307 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
309 rc = bnxt_vnic_grp_alloc(bp, vnic);
313 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
314 i, vnic, vnic->fw_grp_ids);
316 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
318 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
323 /* Alloc RSS context only if RSS mode is enabled */
324 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
325 int j, nr_ctxs = bnxt_rss_ctxts(bp);
328 for (j = 0; j < nr_ctxs; j++) {
329 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
335 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
339 vnic->num_lb_ctxts = nr_ctxs;
343 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
344 * setting is not available at this time, it will not be
345 * configured correctly in the CFA.
347 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
348 vnic->vlan_strip = true;
350 vnic->vlan_strip = false;
352 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
354 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
359 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
362 "HWRM vnic %d filter failure rc: %x\n",
367 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
368 rxq = bp->eth_dev->data->rx_queues[j];
371 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
372 j, rxq->vnic, rxq->vnic->fw_grp_ids);
374 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
375 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
378 rc = bnxt_vnic_rss_configure(bp, vnic);
381 "HWRM vnic set RSS failure rc: %x\n", rc);
385 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
387 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
388 DEV_RX_OFFLOAD_TCP_LRO)
389 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
391 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
393 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
396 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
400 /* check and configure queue intr-vector mapping */
401 if ((rte_intr_cap_multiple(intr_handle) ||
402 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
403 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
404 intr_vector = bp->eth_dev->data->nb_rx_queues;
405 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
406 if (intr_vector > bp->rx_cp_nr_rings) {
407 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
411 rc = rte_intr_efd_enable(intr_handle, intr_vector);
416 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
417 intr_handle->intr_vec =
418 rte_zmalloc("intr_vec",
419 bp->eth_dev->data->nb_rx_queues *
421 if (intr_handle->intr_vec == NULL) {
422 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
423 " intr_vec", bp->eth_dev->data->nb_rx_queues);
427 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
428 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
429 intr_handle->intr_vec, intr_handle->nb_efd,
430 intr_handle->max_intr);
431 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
433 intr_handle->intr_vec[queue_id] =
434 vec + BNXT_RX_VEC_START;
435 if (vec < base + intr_handle->nb_efd - 1)
440 /* enable uio/vfio intr/eventfd mapping */
441 rc = rte_intr_enable(intr_handle);
445 rc = bnxt_get_hwrm_link_config(bp, &new);
447 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
451 if (!bp->link_info.link_up) {
452 rc = bnxt_set_hwrm_link_config(bp, true);
455 "HWRM link config failure rc: %x\n", rc);
459 bnxt_print_link_info(bp->eth_dev);
464 rte_free(intr_handle->intr_vec);
466 rte_intr_efd_disable(intr_handle);
468 /* Some of the error status returned by FW may not be from errno.h */
475 static int bnxt_shutdown_nic(struct bnxt *bp)
477 bnxt_free_all_hwrm_resources(bp);
478 bnxt_free_all_filters(bp);
479 bnxt_free_all_vnics(bp);
484 * Device configuration and status function
487 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
488 struct rte_eth_dev_info *dev_info)
490 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
491 struct bnxt *bp = eth_dev->data->dev_private;
492 uint16_t max_vnics, i, j, vpool, vrxq;
493 unsigned int max_rx_rings;
496 rc = is_bnxt_in_error(bp);
501 dev_info->max_mac_addrs = bp->max_l2_ctx;
502 dev_info->max_hash_mac_addrs = 0;
504 /* PF/VF specifics */
506 dev_info->max_vfs = pdev->max_vfs;
508 max_rx_rings = BNXT_MAX_RINGS(bp);
509 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
510 dev_info->max_rx_queues = max_rx_rings;
511 dev_info->max_tx_queues = max_rx_rings;
512 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
513 dev_info->hash_key_size = 40;
514 max_vnics = bp->max_vnics;
517 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
518 dev_info->max_mtu = BNXT_MAX_MTU;
520 /* Fast path specifics */
521 dev_info->min_rx_bufsize = 1;
522 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
524 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
525 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
526 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
527 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
528 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
531 dev_info->default_rxconf = (struct rte_eth_rxconf) {
537 .rx_free_thresh = 32,
538 /* If no descriptors available, pkts are dropped by default */
542 dev_info->default_txconf = (struct rte_eth_txconf) {
548 .tx_free_thresh = 32,
551 eth_dev->data->dev_conf.intr_conf.lsc = 1;
553 eth_dev->data->dev_conf.intr_conf.rxq = 1;
554 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
555 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
556 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
557 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
562 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
563 * need further investigation.
567 vpool = 64; /* ETH_64_POOLS */
568 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
569 for (i = 0; i < 4; vpool >>= 1, i++) {
570 if (max_vnics > vpool) {
571 for (j = 0; j < 5; vrxq >>= 1, j++) {
572 if (dev_info->max_rx_queues > vrxq) {
578 /* Not enough resources to support VMDq */
582 /* Not enough resources to support VMDq */
586 dev_info->max_vmdq_pools = vpool;
587 dev_info->vmdq_queue_num = vrxq;
589 dev_info->vmdq_pool_base = 0;
590 dev_info->vmdq_queue_base = 0;
595 /* Configure the device based on the configuration provided */
596 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
598 struct bnxt *bp = eth_dev->data->dev_private;
599 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
602 bp->rx_queues = (void *)eth_dev->data->rx_queues;
603 bp->tx_queues = (void *)eth_dev->data->tx_queues;
604 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
605 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
607 rc = is_bnxt_in_error(bp);
611 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
612 rc = bnxt_hwrm_check_vf_rings(bp);
614 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
618 /* If a resource has already been allocated - in this case
619 * it is the async completion ring, free it. Reallocate it after
620 * resource reservation. This will ensure the resource counts
621 * are calculated correctly.
624 pthread_mutex_lock(&bp->def_cp_lock);
626 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
627 bnxt_disable_int(bp);
628 bnxt_free_cp_ring(bp, bp->async_cp_ring);
631 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
633 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
634 pthread_mutex_unlock(&bp->def_cp_lock);
638 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
639 rc = bnxt_alloc_async_cp_ring(bp);
641 pthread_mutex_unlock(&bp->def_cp_lock);
647 pthread_mutex_unlock(&bp->def_cp_lock);
649 /* legacy driver needs to get updated values */
650 rc = bnxt_hwrm_func_qcaps(bp);
652 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
657 /* Inherit new configurations */
658 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
659 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
660 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
661 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
662 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
666 if (BNXT_HAS_RING_GRPS(bp) &&
667 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
670 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
671 bp->max_vnics < eth_dev->data->nb_rx_queues)
674 bp->rx_cp_nr_rings = bp->rx_nr_rings;
675 bp->tx_cp_nr_rings = bp->tx_nr_rings;
677 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
678 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
680 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
682 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
683 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
685 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
691 "Insufficient resources to support requested config\n");
693 "Num Queues Requested: Tx %d, Rx %d\n",
694 eth_dev->data->nb_tx_queues,
695 eth_dev->data->nb_rx_queues);
697 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
698 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
699 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
703 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
705 struct rte_eth_link *link = ð_dev->data->dev_link;
707 if (link->link_status)
708 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
709 eth_dev->data->port_id,
710 (uint32_t)link->link_speed,
711 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
712 ("full-duplex") : ("half-duplex\n"));
714 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
715 eth_dev->data->port_id);
719 * Determine whether the current configuration requires support for scattered
720 * receive; return 1 if scattered receive is required and 0 if not.
722 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
727 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
730 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
731 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
733 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
734 RTE_PKTMBUF_HEADROOM);
735 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
741 static eth_rx_burst_t
742 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
745 #ifndef RTE_LIBRTE_IEEE1588
747 * Vector mode receive can be enabled only if scatter rx is not
748 * in use and rx offloads are limited to VLAN stripping and
751 if (!eth_dev->data->scattered_rx &&
752 !(eth_dev->data->dev_conf.rxmode.offloads &
753 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
754 DEV_RX_OFFLOAD_KEEP_CRC |
755 DEV_RX_OFFLOAD_JUMBO_FRAME |
756 DEV_RX_OFFLOAD_IPV4_CKSUM |
757 DEV_RX_OFFLOAD_UDP_CKSUM |
758 DEV_RX_OFFLOAD_TCP_CKSUM |
759 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
760 DEV_RX_OFFLOAD_VLAN_FILTER))) {
761 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
762 eth_dev->data->port_id);
763 return bnxt_recv_pkts_vec;
765 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
766 eth_dev->data->port_id);
768 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
769 eth_dev->data->port_id,
770 eth_dev->data->scattered_rx,
771 eth_dev->data->dev_conf.rxmode.offloads);
774 return bnxt_recv_pkts;
777 static eth_tx_burst_t
778 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
781 #ifndef RTE_LIBRTE_IEEE1588
783 * Vector mode transmit can be enabled only if not using scatter rx
786 if (!eth_dev->data->scattered_rx &&
787 !eth_dev->data->dev_conf.txmode.offloads) {
788 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
789 eth_dev->data->port_id);
790 return bnxt_xmit_pkts_vec;
792 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
793 eth_dev->data->port_id);
795 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
796 eth_dev->data->port_id,
797 eth_dev->data->scattered_rx,
798 eth_dev->data->dev_conf.txmode.offloads);
801 return bnxt_xmit_pkts;
804 static int bnxt_handle_if_change_status(struct bnxt *bp)
808 /* Since fw has undergone a reset and lost all contexts,
809 * set fatal flag to not issue hwrm during cleanup
811 bp->flags |= BNXT_FLAG_FATAL_ERROR;
812 bnxt_uninit_resources(bp, true);
814 /* clear fatal flag so that re-init happens */
815 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
816 rc = bnxt_init_resources(bp, true);
818 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
823 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
825 struct bnxt *bp = eth_dev->data->dev_private;
826 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
830 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
831 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
835 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
837 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
838 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
841 rc = bnxt_hwrm_if_change(bp, 1);
843 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
844 rc = bnxt_handle_if_change_status(bp);
851 rc = bnxt_init_chip(bp);
855 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
857 bnxt_link_update_op(eth_dev, 1);
859 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
860 vlan_mask |= ETH_VLAN_FILTER_MASK;
861 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
862 vlan_mask |= ETH_VLAN_STRIP_MASK;
863 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
867 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
868 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
870 bp->flags |= BNXT_FLAG_INIT_DONE;
871 eth_dev->data->dev_started = 1;
873 pthread_mutex_lock(&bp->def_cp_lock);
874 bnxt_schedule_fw_health_check(bp);
875 pthread_mutex_unlock(&bp->def_cp_lock);
879 bnxt_hwrm_if_change(bp, 0);
880 bnxt_shutdown_nic(bp);
881 bnxt_free_tx_mbufs(bp);
882 bnxt_free_rx_mbufs(bp);
886 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
888 struct bnxt *bp = eth_dev->data->dev_private;
891 if (!bp->link_info.link_up)
892 rc = bnxt_set_hwrm_link_config(bp, true);
894 eth_dev->data->dev_link.link_status = 1;
896 bnxt_print_link_info(eth_dev);
900 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
902 struct bnxt *bp = eth_dev->data->dev_private;
904 eth_dev->data->dev_link.link_status = 0;
905 bnxt_set_hwrm_link_config(bp, false);
906 bp->link_info.link_up = 0;
911 /* Unload the driver, release resources */
912 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
914 struct bnxt *bp = eth_dev->data->dev_private;
915 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
916 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
918 eth_dev->data->dev_started = 0;
919 /* Prevent crashes when queues are still in use */
920 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
921 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
923 bnxt_disable_int(bp);
925 /* disable uio/vfio intr/eventfd mapping */
926 rte_intr_disable(intr_handle);
928 bnxt_cancel_fw_health_check(bp);
930 bp->flags &= ~BNXT_FLAG_INIT_DONE;
931 if (bp->eth_dev->data->dev_started) {
932 /* TBD: STOP HW queues DMA */
933 eth_dev->data->dev_link.link_status = 0;
935 bnxt_dev_set_link_down_op(eth_dev);
937 /* Wait for link to be reset and the async notification to process.
938 * During reset recovery, there is no need to wait
940 if (!is_bnxt_in_error(bp))
941 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
943 /* Clean queue intr-vector mapping */
944 rte_intr_efd_disable(intr_handle);
945 if (intr_handle->intr_vec != NULL) {
946 rte_free(intr_handle->intr_vec);
947 intr_handle->intr_vec = NULL;
950 bnxt_hwrm_port_clr_stats(bp);
951 bnxt_free_tx_mbufs(bp);
952 bnxt_free_rx_mbufs(bp);
953 /* Process any remaining notifications in default completion queue */
954 bnxt_int_handler(eth_dev);
955 bnxt_shutdown_nic(bp);
956 bnxt_hwrm_if_change(bp, 0);
961 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
963 struct bnxt *bp = eth_dev->data->dev_private;
965 if (bp->dev_stopped == 0)
966 bnxt_dev_stop_op(eth_dev);
968 if (eth_dev->data->mac_addrs != NULL) {
969 rte_free(eth_dev->data->mac_addrs);
970 eth_dev->data->mac_addrs = NULL;
972 if (bp->grp_info != NULL) {
973 rte_free(bp->grp_info);
977 bnxt_dev_uninit(eth_dev);
980 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
983 struct bnxt *bp = eth_dev->data->dev_private;
984 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
985 struct bnxt_vnic_info *vnic;
986 struct bnxt_filter_info *filter, *temp_filter;
989 if (is_bnxt_in_error(bp))
993 * Loop through all VNICs from the specified filter flow pools to
994 * remove the corresponding MAC addr filter
996 for (i = 0; i < bp->nr_vnics; i++) {
997 if (!(pool_mask & (1ULL << i)))
1000 vnic = &bp->vnic_info[i];
1001 filter = STAILQ_FIRST(&vnic->filter);
1003 temp_filter = STAILQ_NEXT(filter, next);
1004 if (filter->mac_index == index) {
1005 STAILQ_REMOVE(&vnic->filter, filter,
1006 bnxt_filter_info, next);
1007 bnxt_hwrm_clear_l2_filter(bp, filter);
1008 filter->mac_index = INVALID_MAC_INDEX;
1009 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1010 bnxt_free_filter(bp, filter);
1012 filter = temp_filter;
1017 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1018 struct rte_ether_addr *mac_addr, uint32_t index,
1021 struct bnxt_filter_info *filter;
1024 /* Attach requested MAC address to the new l2_filter */
1025 STAILQ_FOREACH(filter, &vnic->filter, next) {
1026 if (filter->mac_index == index) {
1028 "MAC addr already existed for pool %d\n",
1034 filter = bnxt_alloc_filter(bp);
1036 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1040 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1041 * if the MAC that's been programmed now is a different one, then,
1042 * copy that addr to filter->l2_addr
1045 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1046 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1048 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1050 filter->mac_index = index;
1051 if (filter->mac_index == 0)
1052 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1054 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1056 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1057 bnxt_free_filter(bp, filter);
1063 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1064 struct rte_ether_addr *mac_addr,
1065 uint32_t index, uint32_t pool)
1067 struct bnxt *bp = eth_dev->data->dev_private;
1068 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1071 rc = is_bnxt_in_error(bp);
1075 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1076 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1081 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1085 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1090 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1093 struct bnxt *bp = eth_dev->data->dev_private;
1094 struct rte_eth_link new;
1095 unsigned int cnt = BNXT_LINK_WAIT_CNT;
1097 rc = is_bnxt_in_error(bp);
1101 memset(&new, 0, sizeof(new));
1103 /* Retrieve link info from hardware */
1104 rc = bnxt_get_hwrm_link_config(bp, &new);
1106 new.link_speed = ETH_LINK_SPEED_100M;
1107 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1109 "Failed to retrieve link rc = 0x%x!\n", rc);
1113 if (!wait_to_complete || new.link_status)
1116 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1120 /* Timed out or success */
1121 if (new.link_status != eth_dev->data->dev_link.link_status ||
1122 new.link_speed != eth_dev->data->dev_link.link_speed) {
1123 rte_eth_linkstatus_set(eth_dev, &new);
1125 _rte_eth_dev_callback_process(eth_dev,
1126 RTE_ETH_EVENT_INTR_LSC,
1129 bnxt_print_link_info(eth_dev);
1135 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1137 struct bnxt *bp = eth_dev->data->dev_private;
1138 struct bnxt_vnic_info *vnic;
1142 rc = is_bnxt_in_error(bp);
1146 if (bp->vnic_info == NULL)
1149 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1151 old_flags = vnic->flags;
1152 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1153 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1155 vnic->flags = old_flags;
1160 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1162 struct bnxt *bp = eth_dev->data->dev_private;
1163 struct bnxt_vnic_info *vnic;
1167 rc = is_bnxt_in_error(bp);
1171 if (bp->vnic_info == NULL)
1174 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1176 old_flags = vnic->flags;
1177 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1178 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1180 vnic->flags = old_flags;
1185 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1187 struct bnxt *bp = eth_dev->data->dev_private;
1188 struct bnxt_vnic_info *vnic;
1192 rc = is_bnxt_in_error(bp);
1196 if (bp->vnic_info == NULL)
1199 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1201 old_flags = vnic->flags;
1202 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1203 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1205 vnic->flags = old_flags;
1210 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1212 struct bnxt *bp = eth_dev->data->dev_private;
1213 struct bnxt_vnic_info *vnic;
1217 rc = is_bnxt_in_error(bp);
1221 if (bp->vnic_info == NULL)
1224 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1226 old_flags = vnic->flags;
1227 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1228 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1230 vnic->flags = old_flags;
1235 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1236 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1238 if (qid >= bp->rx_nr_rings)
1241 return bp->eth_dev->data->rx_queues[qid];
1244 /* Return rxq corresponding to a given rss table ring/group ID. */
1245 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1247 struct bnxt_rx_queue *rxq;
1250 if (!BNXT_HAS_RING_GRPS(bp)) {
1251 for (i = 0; i < bp->rx_nr_rings; i++) {
1252 rxq = bp->eth_dev->data->rx_queues[i];
1253 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1257 for (i = 0; i < bp->rx_nr_rings; i++) {
1258 if (bp->grp_info[i].fw_grp_id == fwr)
1263 return INVALID_HW_RING_ID;
1266 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1267 struct rte_eth_rss_reta_entry64 *reta_conf,
1270 struct bnxt *bp = eth_dev->data->dev_private;
1271 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1272 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1273 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1277 rc = is_bnxt_in_error(bp);
1281 if (!vnic->rss_table)
1284 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1287 if (reta_size != tbl_size) {
1288 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1289 "(%d) must equal the size supported by the hardware "
1290 "(%d)\n", reta_size, tbl_size);
1294 for (i = 0; i < reta_size; i++) {
1295 struct bnxt_rx_queue *rxq;
1297 idx = i / RTE_RETA_GROUP_SIZE;
1298 sft = i % RTE_RETA_GROUP_SIZE;
1300 if (!(reta_conf[idx].mask & (1ULL << sft)))
1303 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1305 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1309 if (BNXT_CHIP_THOR(bp)) {
1310 vnic->rss_table[i * 2] =
1311 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1312 vnic->rss_table[i * 2 + 1] =
1313 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1315 vnic->rss_table[i] =
1316 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1320 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1324 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1325 struct rte_eth_rss_reta_entry64 *reta_conf,
1328 struct bnxt *bp = eth_dev->data->dev_private;
1329 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1330 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1331 uint16_t idx, sft, i;
1334 rc = is_bnxt_in_error(bp);
1338 /* Retrieve from the default VNIC */
1341 if (!vnic->rss_table)
1344 if (reta_size != tbl_size) {
1345 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1346 "(%d) must equal the size supported by the hardware "
1347 "(%d)\n", reta_size, tbl_size);
1351 for (idx = 0, i = 0; i < reta_size; i++) {
1352 idx = i / RTE_RETA_GROUP_SIZE;
1353 sft = i % RTE_RETA_GROUP_SIZE;
1355 if (reta_conf[idx].mask & (1ULL << sft)) {
1358 if (BNXT_CHIP_THOR(bp))
1359 qid = bnxt_rss_to_qid(bp,
1360 vnic->rss_table[i * 2]);
1362 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1364 if (qid == INVALID_HW_RING_ID) {
1365 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1368 reta_conf[idx].reta[sft] = qid;
1375 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1376 struct rte_eth_rss_conf *rss_conf)
1378 struct bnxt *bp = eth_dev->data->dev_private;
1379 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1380 struct bnxt_vnic_info *vnic;
1383 rc = is_bnxt_in_error(bp);
1388 * If RSS enablement were different than dev_configure,
1389 * then return -EINVAL
1391 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1392 if (!rss_conf->rss_hf)
1393 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1395 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1399 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1400 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1402 /* Update the default RSS VNIC(s) */
1403 vnic = &bp->vnic_info[0];
1404 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1407 * If hashkey is not specified, use the previously configured
1410 if (!rss_conf->rss_key)
1413 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1415 "Invalid hashkey length, should be 16 bytes\n");
1418 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1421 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1425 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1426 struct rte_eth_rss_conf *rss_conf)
1428 struct bnxt *bp = eth_dev->data->dev_private;
1429 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1431 uint32_t hash_types;
1433 rc = is_bnxt_in_error(bp);
1437 /* RSS configuration is the same for all VNICs */
1438 if (vnic && vnic->rss_hash_key) {
1439 if (rss_conf->rss_key) {
1440 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1441 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1442 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1445 hash_types = vnic->hash_type;
1446 rss_conf->rss_hf = 0;
1447 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1448 rss_conf->rss_hf |= ETH_RSS_IPV4;
1449 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1451 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1452 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1454 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1456 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1457 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1459 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1461 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1462 rss_conf->rss_hf |= ETH_RSS_IPV6;
1463 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1465 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1466 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1468 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1470 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1471 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1473 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1477 "Unknwon RSS config from firmware (%08x), RSS disabled",
1482 rss_conf->rss_hf = 0;
1487 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1488 struct rte_eth_fc_conf *fc_conf)
1490 struct bnxt *bp = dev->data->dev_private;
1491 struct rte_eth_link link_info;
1494 rc = is_bnxt_in_error(bp);
1498 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1502 memset(fc_conf, 0, sizeof(*fc_conf));
1503 if (bp->link_info.auto_pause)
1504 fc_conf->autoneg = 1;
1505 switch (bp->link_info.pause) {
1507 fc_conf->mode = RTE_FC_NONE;
1509 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1510 fc_conf->mode = RTE_FC_TX_PAUSE;
1512 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1513 fc_conf->mode = RTE_FC_RX_PAUSE;
1515 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1516 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1517 fc_conf->mode = RTE_FC_FULL;
1523 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1524 struct rte_eth_fc_conf *fc_conf)
1526 struct bnxt *bp = dev->data->dev_private;
1529 rc = is_bnxt_in_error(bp);
1533 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1534 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1538 switch (fc_conf->mode) {
1540 bp->link_info.auto_pause = 0;
1541 bp->link_info.force_pause = 0;
1543 case RTE_FC_RX_PAUSE:
1544 if (fc_conf->autoneg) {
1545 bp->link_info.auto_pause =
1546 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1547 bp->link_info.force_pause = 0;
1549 bp->link_info.auto_pause = 0;
1550 bp->link_info.force_pause =
1551 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1554 case RTE_FC_TX_PAUSE:
1555 if (fc_conf->autoneg) {
1556 bp->link_info.auto_pause =
1557 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1558 bp->link_info.force_pause = 0;
1560 bp->link_info.auto_pause = 0;
1561 bp->link_info.force_pause =
1562 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1566 if (fc_conf->autoneg) {
1567 bp->link_info.auto_pause =
1568 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1569 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1570 bp->link_info.force_pause = 0;
1572 bp->link_info.auto_pause = 0;
1573 bp->link_info.force_pause =
1574 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1575 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1579 return bnxt_set_hwrm_link_config(bp, true);
1582 /* Add UDP tunneling port */
1584 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1585 struct rte_eth_udp_tunnel *udp_tunnel)
1587 struct bnxt *bp = eth_dev->data->dev_private;
1588 uint16_t tunnel_type = 0;
1591 rc = is_bnxt_in_error(bp);
1595 switch (udp_tunnel->prot_type) {
1596 case RTE_TUNNEL_TYPE_VXLAN:
1597 if (bp->vxlan_port_cnt) {
1598 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1599 udp_tunnel->udp_port);
1600 if (bp->vxlan_port != udp_tunnel->udp_port) {
1601 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1604 bp->vxlan_port_cnt++;
1608 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1609 bp->vxlan_port_cnt++;
1611 case RTE_TUNNEL_TYPE_GENEVE:
1612 if (bp->geneve_port_cnt) {
1613 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1614 udp_tunnel->udp_port);
1615 if (bp->geneve_port != udp_tunnel->udp_port) {
1616 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1619 bp->geneve_port_cnt++;
1623 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1624 bp->geneve_port_cnt++;
1627 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1630 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1636 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1637 struct rte_eth_udp_tunnel *udp_tunnel)
1639 struct bnxt *bp = eth_dev->data->dev_private;
1640 uint16_t tunnel_type = 0;
1644 rc = is_bnxt_in_error(bp);
1648 switch (udp_tunnel->prot_type) {
1649 case RTE_TUNNEL_TYPE_VXLAN:
1650 if (!bp->vxlan_port_cnt) {
1651 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1654 if (bp->vxlan_port != udp_tunnel->udp_port) {
1655 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1656 udp_tunnel->udp_port, bp->vxlan_port);
1659 if (--bp->vxlan_port_cnt)
1663 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1664 port = bp->vxlan_fw_dst_port_id;
1666 case RTE_TUNNEL_TYPE_GENEVE:
1667 if (!bp->geneve_port_cnt) {
1668 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1671 if (bp->geneve_port != udp_tunnel->udp_port) {
1672 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1673 udp_tunnel->udp_port, bp->geneve_port);
1676 if (--bp->geneve_port_cnt)
1680 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1681 port = bp->geneve_fw_dst_port_id;
1684 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1688 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1691 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1694 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1695 bp->geneve_port = 0;
1700 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1702 struct bnxt_filter_info *filter;
1703 struct bnxt_vnic_info *vnic;
1705 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1707 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1708 filter = STAILQ_FIRST(&vnic->filter);
1710 /* Search for this matching MAC+VLAN filter */
1711 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1712 /* Delete the filter */
1713 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1716 STAILQ_REMOVE(&vnic->filter, filter,
1717 bnxt_filter_info, next);
1718 bnxt_free_filter(bp, filter);
1720 "Deleted vlan filter for %d\n",
1724 filter = STAILQ_NEXT(filter, next);
1729 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1731 struct bnxt_filter_info *filter;
1732 struct bnxt_vnic_info *vnic;
1734 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1735 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1736 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1738 /* Implementation notes on the use of VNIC in this command:
1740 * By default, these filters belong to default vnic for the function.
1741 * Once these filters are set up, only destination VNIC can be modified.
1742 * If the destination VNIC is not specified in this command,
1743 * then the HWRM shall only create an l2 context id.
1746 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1747 filter = STAILQ_FIRST(&vnic->filter);
1748 /* Check if the VLAN has already been added */
1750 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
1753 filter = STAILQ_NEXT(filter, next);
1756 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1757 * command to create MAC+VLAN filter with the right flags, enables set.
1759 filter = bnxt_alloc_filter(bp);
1762 "MAC/VLAN filter alloc failed\n");
1765 /* MAC + VLAN ID filter */
1766 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1767 * untagged packets are received
1769 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1770 * packets and only the programmed vlan's packets are received
1772 filter->l2_ivlan = vlan_id;
1773 filter->l2_ivlan_mask = 0x0FFF;
1774 filter->enables |= en;
1775 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1777 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1779 /* Free the newly allocated filter as we were
1780 * not able to create the filter in hardware.
1782 filter->fw_l2_filter_id = UINT64_MAX;
1783 bnxt_free_filter(bp, filter);
1787 filter->mac_index = 0;
1788 /* Add this new filter to the list */
1790 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1792 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1795 "Added Vlan filter for %d\n", vlan_id);
1799 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1800 uint16_t vlan_id, int on)
1802 struct bnxt *bp = eth_dev->data->dev_private;
1805 rc = is_bnxt_in_error(bp);
1809 /* These operations apply to ALL existing MAC/VLAN filters */
1811 return bnxt_add_vlan_filter(bp, vlan_id);
1813 return bnxt_del_vlan_filter(bp, vlan_id);
1816 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1817 struct bnxt_vnic_info *vnic)
1819 struct bnxt_filter_info *filter;
1822 filter = STAILQ_FIRST(&vnic->filter);
1824 if (filter->mac_index == 0 &&
1825 !memcmp(filter->l2_addr, bp->mac_addr,
1826 RTE_ETHER_ADDR_LEN)) {
1827 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1829 STAILQ_REMOVE(&vnic->filter, filter,
1830 bnxt_filter_info, next);
1831 bnxt_free_filter(bp, filter);
1832 filter->fw_l2_filter_id = UINT64_MAX;
1836 filter = STAILQ_NEXT(filter, next);
1842 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1844 struct bnxt *bp = dev->data->dev_private;
1845 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1846 struct bnxt_vnic_info *vnic;
1850 rc = is_bnxt_in_error(bp);
1854 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1855 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1856 /* Remove any VLAN filters programmed */
1857 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1858 bnxt_del_vlan_filter(bp, i);
1860 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1864 /* Default filter will allow packets that match the
1865 * dest mac. So, it has to be deleted, otherwise, we
1866 * will endup receiving vlan packets for which the
1867 * filter is not programmed, when hw-vlan-filter
1868 * configuration is ON
1870 bnxt_del_dflt_mac_filter(bp, vnic);
1871 /* This filter will allow only untagged packets */
1872 bnxt_add_vlan_filter(bp, 0);
1874 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1875 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1877 if (mask & ETH_VLAN_STRIP_MASK) {
1878 /* Enable or disable VLAN stripping */
1879 for (i = 0; i < bp->nr_vnics; i++) {
1880 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1881 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1882 vnic->vlan_strip = true;
1884 vnic->vlan_strip = false;
1885 bnxt_hwrm_vnic_cfg(bp, vnic);
1887 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1888 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1891 if (mask & ETH_VLAN_EXTEND_MASK) {
1892 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1893 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1895 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1902 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1905 struct bnxt *bp = dev->data->dev_private;
1906 int qinq = dev->data->dev_conf.rxmode.offloads &
1907 DEV_RX_OFFLOAD_VLAN_EXTEND;
1909 if (vlan_type != ETH_VLAN_TYPE_INNER &&
1910 vlan_type != ETH_VLAN_TYPE_OUTER) {
1912 "Unsupported vlan type.");
1917 "QinQ not enabled. Needs to be ON as we can "
1918 "accelerate only outer vlan\n");
1922 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1924 case RTE_ETHER_TYPE_QINQ:
1926 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1928 case RTE_ETHER_TYPE_VLAN:
1930 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1934 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1938 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
1942 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
1945 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
1948 bp->outer_tpid_bd |= tpid;
1949 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
1950 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
1952 "Can accelerate only outer vlan in QinQ\n");
1960 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1961 struct rte_ether_addr *addr)
1963 struct bnxt *bp = dev->data->dev_private;
1964 /* Default Filter is tied to VNIC 0 */
1965 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1966 struct bnxt_filter_info *filter;
1969 rc = is_bnxt_in_error(bp);
1973 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1976 if (rte_is_zero_ether_addr(addr))
1979 STAILQ_FOREACH(filter, &vnic->filter, next) {
1980 /* Default Filter is at Index 0 */
1981 if (filter->mac_index != 0)
1984 memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN);
1985 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1986 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX |
1987 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1989 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1990 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1992 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1994 memcpy(filter->l2_addr, bp->mac_addr,
1995 RTE_ETHER_ADDR_LEN);
1999 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2000 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2008 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2009 struct rte_ether_addr *mc_addr_set,
2010 uint32_t nb_mc_addr)
2012 struct bnxt *bp = eth_dev->data->dev_private;
2013 char *mc_addr_list = (char *)mc_addr_set;
2014 struct bnxt_vnic_info *vnic;
2015 uint32_t off = 0, i = 0;
2018 rc = is_bnxt_in_error(bp);
2022 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2024 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2025 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2029 /* TODO Check for Duplicate mcast addresses */
2030 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2031 for (i = 0; i < nb_mc_addr; i++) {
2032 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2033 RTE_ETHER_ADDR_LEN);
2034 off += RTE_ETHER_ADDR_LEN;
2037 vnic->mc_addr_cnt = i;
2038 if (vnic->mc_addr_cnt)
2039 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2041 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2044 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2048 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2050 struct bnxt *bp = dev->data->dev_private;
2051 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2052 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2053 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2056 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2057 fw_major, fw_minor, fw_updt);
2059 ret += 1; /* add the size of '\0' */
2060 if (fw_size < (uint32_t)ret)
2067 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2068 struct rte_eth_rxq_info *qinfo)
2070 struct bnxt *bp = dev->data->dev_private;
2071 struct bnxt_rx_queue *rxq;
2073 if (is_bnxt_in_error(bp))
2076 rxq = dev->data->rx_queues[queue_id];
2078 qinfo->mp = rxq->mb_pool;
2079 qinfo->scattered_rx = dev->data->scattered_rx;
2080 qinfo->nb_desc = rxq->nb_rx_desc;
2082 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2083 qinfo->conf.rx_drop_en = 0;
2084 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2088 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2089 struct rte_eth_txq_info *qinfo)
2091 struct bnxt *bp = dev->data->dev_private;
2092 struct bnxt_tx_queue *txq;
2094 if (is_bnxt_in_error(bp))
2097 txq = dev->data->tx_queues[queue_id];
2099 qinfo->nb_desc = txq->nb_tx_desc;
2101 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2102 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2103 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2105 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2106 qinfo->conf.tx_rs_thresh = 0;
2107 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2110 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2112 struct bnxt *bp = eth_dev->data->dev_private;
2113 uint32_t new_pkt_size;
2117 rc = is_bnxt_in_error(bp);
2121 /* Exit if receive queues are not configured yet */
2122 if (!eth_dev->data->nb_rx_queues)
2125 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2126 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2130 * If vector-mode tx/rx is active, disallow any MTU change that would
2131 * require scattered receive support.
2133 if (eth_dev->data->dev_started &&
2134 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2135 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2137 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2139 "MTU change would require scattered rx support. ");
2140 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2145 if (new_mtu > RTE_ETHER_MTU) {
2146 bp->flags |= BNXT_FLAG_JUMBO;
2147 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2148 DEV_RX_OFFLOAD_JUMBO_FRAME;
2150 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2151 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2152 bp->flags &= ~BNXT_FLAG_JUMBO;
2155 /* Is there a change in mtu setting? */
2156 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2159 for (i = 0; i < bp->nr_vnics; i++) {
2160 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2163 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2164 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2168 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2169 size -= RTE_PKTMBUF_HEADROOM;
2171 if (size < new_mtu) {
2172 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2179 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2181 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2187 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2189 struct bnxt *bp = dev->data->dev_private;
2190 uint16_t vlan = bp->vlan;
2193 rc = is_bnxt_in_error(bp);
2197 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2199 "PVID cannot be modified for this function\n");
2202 bp->vlan = on ? pvid : 0;
2204 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2211 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2213 struct bnxt *bp = dev->data->dev_private;
2216 rc = is_bnxt_in_error(bp);
2220 return bnxt_hwrm_port_led_cfg(bp, true);
2224 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2226 struct bnxt *bp = dev->data->dev_private;
2229 rc = is_bnxt_in_error(bp);
2233 return bnxt_hwrm_port_led_cfg(bp, false);
2237 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2239 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2240 uint32_t desc = 0, raw_cons = 0, cons;
2241 struct bnxt_cp_ring_info *cpr;
2242 struct bnxt_rx_queue *rxq;
2243 struct rx_pkt_cmpl *rxcmp;
2246 rc = is_bnxt_in_error(bp);
2250 rxq = dev->data->rx_queues[rx_queue_id];
2252 raw_cons = cpr->cp_raw_cons;
2255 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2256 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2257 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2259 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2271 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2273 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2274 struct bnxt_rx_ring_info *rxr;
2275 struct bnxt_cp_ring_info *cpr;
2276 struct bnxt_sw_rx_bd *rx_buf;
2277 struct rx_pkt_cmpl *rxcmp;
2278 uint32_t cons, cp_cons;
2284 rc = is_bnxt_in_error(rxq->bp);
2291 if (offset >= rxq->nb_rx_desc)
2294 cons = RING_CMP(cpr->cp_ring_struct, offset);
2295 cp_cons = cpr->cp_raw_cons;
2296 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2298 if (cons > cp_cons) {
2299 if (CMPL_VALID(rxcmp, cpr->valid))
2300 return RTE_ETH_RX_DESC_DONE;
2302 if (CMPL_VALID(rxcmp, !cpr->valid))
2303 return RTE_ETH_RX_DESC_DONE;
2305 rx_buf = &rxr->rx_buf_ring[cons];
2306 if (rx_buf->mbuf == NULL)
2307 return RTE_ETH_RX_DESC_UNAVAIL;
2310 return RTE_ETH_RX_DESC_AVAIL;
2314 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2316 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2317 struct bnxt_tx_ring_info *txr;
2318 struct bnxt_cp_ring_info *cpr;
2319 struct bnxt_sw_tx_bd *tx_buf;
2320 struct tx_pkt_cmpl *txcmp;
2321 uint32_t cons, cp_cons;
2327 rc = is_bnxt_in_error(txq->bp);
2334 if (offset >= txq->nb_tx_desc)
2337 cons = RING_CMP(cpr->cp_ring_struct, offset);
2338 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2339 cp_cons = cpr->cp_raw_cons;
2341 if (cons > cp_cons) {
2342 if (CMPL_VALID(txcmp, cpr->valid))
2343 return RTE_ETH_TX_DESC_UNAVAIL;
2345 if (CMPL_VALID(txcmp, !cpr->valid))
2346 return RTE_ETH_TX_DESC_UNAVAIL;
2348 tx_buf = &txr->tx_buf_ring[cons];
2349 if (tx_buf->mbuf == NULL)
2350 return RTE_ETH_TX_DESC_DONE;
2352 return RTE_ETH_TX_DESC_FULL;
2355 static struct bnxt_filter_info *
2356 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2357 struct rte_eth_ethertype_filter *efilter,
2358 struct bnxt_vnic_info *vnic0,
2359 struct bnxt_vnic_info *vnic,
2362 struct bnxt_filter_info *mfilter = NULL;
2366 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2367 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2368 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2369 " ethertype filter.", efilter->ether_type);
2373 if (efilter->queue >= bp->rx_nr_rings) {
2374 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2379 vnic0 = &bp->vnic_info[0];
2380 vnic = &bp->vnic_info[efilter->queue];
2382 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2387 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2388 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2389 if ((!memcmp(efilter->mac_addr.addr_bytes,
2390 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2392 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2393 mfilter->ethertype == efilter->ether_type)) {
2399 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2400 if ((!memcmp(efilter->mac_addr.addr_bytes,
2401 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2402 mfilter->ethertype == efilter->ether_type &&
2404 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2418 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2419 enum rte_filter_op filter_op,
2422 struct bnxt *bp = dev->data->dev_private;
2423 struct rte_eth_ethertype_filter *efilter =
2424 (struct rte_eth_ethertype_filter *)arg;
2425 struct bnxt_filter_info *bfilter, *filter1;
2426 struct bnxt_vnic_info *vnic, *vnic0;
2429 if (filter_op == RTE_ETH_FILTER_NOP)
2433 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2438 vnic0 = &bp->vnic_info[0];
2439 vnic = &bp->vnic_info[efilter->queue];
2441 switch (filter_op) {
2442 case RTE_ETH_FILTER_ADD:
2443 bnxt_match_and_validate_ether_filter(bp, efilter,
2448 bfilter = bnxt_get_unused_filter(bp);
2449 if (bfilter == NULL) {
2451 "Not enough resources for a new filter.\n");
2454 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2455 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2456 RTE_ETHER_ADDR_LEN);
2457 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2458 RTE_ETHER_ADDR_LEN);
2459 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2460 bfilter->ethertype = efilter->ether_type;
2461 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2463 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2464 if (filter1 == NULL) {
2469 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2470 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2472 bfilter->dst_id = vnic->fw_vnic_id;
2474 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2476 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2479 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2482 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2484 case RTE_ETH_FILTER_DELETE:
2485 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2487 if (ret == -EEXIST) {
2488 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2490 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2492 bnxt_free_filter(bp, filter1);
2493 } else if (ret == 0) {
2494 PMD_DRV_LOG(ERR, "No matching filter found\n");
2498 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2504 bnxt_free_filter(bp, bfilter);
2510 parse_ntuple_filter(struct bnxt *bp,
2511 struct rte_eth_ntuple_filter *nfilter,
2512 struct bnxt_filter_info *bfilter)
2516 if (nfilter->queue >= bp->rx_nr_rings) {
2517 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2521 switch (nfilter->dst_port_mask) {
2523 bfilter->dst_port_mask = -1;
2524 bfilter->dst_port = nfilter->dst_port;
2525 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2526 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2529 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2533 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2534 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2536 switch (nfilter->proto_mask) {
2538 if (nfilter->proto == 17) /* IPPROTO_UDP */
2539 bfilter->ip_protocol = 17;
2540 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2541 bfilter->ip_protocol = 6;
2544 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2547 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2551 switch (nfilter->dst_ip_mask) {
2553 bfilter->dst_ipaddr_mask[0] = -1;
2554 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2555 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2556 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2559 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2563 switch (nfilter->src_ip_mask) {
2565 bfilter->src_ipaddr_mask[0] = -1;
2566 bfilter->src_ipaddr[0] = nfilter->src_ip;
2567 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2568 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2571 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2575 switch (nfilter->src_port_mask) {
2577 bfilter->src_port_mask = -1;
2578 bfilter->src_port = nfilter->src_port;
2579 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2580 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2583 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2587 bfilter->enables = en;
2591 static struct bnxt_filter_info*
2592 bnxt_match_ntuple_filter(struct bnxt *bp,
2593 struct bnxt_filter_info *bfilter,
2594 struct bnxt_vnic_info **mvnic)
2596 struct bnxt_filter_info *mfilter = NULL;
2599 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2600 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2601 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2602 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2603 bfilter->src_ipaddr_mask[0] ==
2604 mfilter->src_ipaddr_mask[0] &&
2605 bfilter->src_port == mfilter->src_port &&
2606 bfilter->src_port_mask == mfilter->src_port_mask &&
2607 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2608 bfilter->dst_ipaddr_mask[0] ==
2609 mfilter->dst_ipaddr_mask[0] &&
2610 bfilter->dst_port == mfilter->dst_port &&
2611 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2612 bfilter->flags == mfilter->flags &&
2613 bfilter->enables == mfilter->enables) {
2624 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2625 struct rte_eth_ntuple_filter *nfilter,
2626 enum rte_filter_op filter_op)
2628 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2629 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2632 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2633 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2637 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2638 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2642 bfilter = bnxt_get_unused_filter(bp);
2643 if (bfilter == NULL) {
2645 "Not enough resources for a new filter.\n");
2648 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2652 vnic = &bp->vnic_info[nfilter->queue];
2653 vnic0 = &bp->vnic_info[0];
2654 filter1 = STAILQ_FIRST(&vnic0->filter);
2655 if (filter1 == NULL) {
2660 bfilter->dst_id = vnic->fw_vnic_id;
2661 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2663 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2664 bfilter->ethertype = 0x800;
2665 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2667 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2669 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2670 bfilter->dst_id == mfilter->dst_id) {
2671 PMD_DRV_LOG(ERR, "filter exists.\n");
2674 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2675 bfilter->dst_id != mfilter->dst_id) {
2676 mfilter->dst_id = vnic->fw_vnic_id;
2677 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2678 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2679 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2680 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2681 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2684 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2685 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2690 if (filter_op == RTE_ETH_FILTER_ADD) {
2691 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2692 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2695 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2697 if (mfilter == NULL) {
2698 /* This should not happen. But for Coverity! */
2702 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2704 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2705 bnxt_free_filter(bp, mfilter);
2706 mfilter->fw_l2_filter_id = -1;
2707 bnxt_free_filter(bp, bfilter);
2708 bfilter->fw_l2_filter_id = -1;
2713 bfilter->fw_l2_filter_id = -1;
2714 bnxt_free_filter(bp, bfilter);
2719 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2720 enum rte_filter_op filter_op,
2723 struct bnxt *bp = dev->data->dev_private;
2726 if (filter_op == RTE_ETH_FILTER_NOP)
2730 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2735 switch (filter_op) {
2736 case RTE_ETH_FILTER_ADD:
2737 ret = bnxt_cfg_ntuple_filter(bp,
2738 (struct rte_eth_ntuple_filter *)arg,
2741 case RTE_ETH_FILTER_DELETE:
2742 ret = bnxt_cfg_ntuple_filter(bp,
2743 (struct rte_eth_ntuple_filter *)arg,
2747 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2755 bnxt_parse_fdir_filter(struct bnxt *bp,
2756 struct rte_eth_fdir_filter *fdir,
2757 struct bnxt_filter_info *filter)
2759 enum rte_fdir_mode fdir_mode =
2760 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2761 struct bnxt_vnic_info *vnic0, *vnic;
2762 struct bnxt_filter_info *filter1;
2766 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2769 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2770 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2772 switch (fdir->input.flow_type) {
2773 case RTE_ETH_FLOW_IPV4:
2774 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2776 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2777 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2778 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2779 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2780 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2781 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2782 filter->ip_addr_type =
2783 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2784 filter->src_ipaddr_mask[0] = 0xffffffff;
2785 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2786 filter->dst_ipaddr_mask[0] = 0xffffffff;
2787 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2788 filter->ethertype = 0x800;
2789 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2791 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2792 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2793 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2794 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2795 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2796 filter->dst_port_mask = 0xffff;
2797 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2798 filter->src_port_mask = 0xffff;
2799 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2800 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2801 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2802 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2803 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2804 filter->ip_protocol = 6;
2805 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2806 filter->ip_addr_type =
2807 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2808 filter->src_ipaddr_mask[0] = 0xffffffff;
2809 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2810 filter->dst_ipaddr_mask[0] = 0xffffffff;
2811 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2812 filter->ethertype = 0x800;
2813 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2815 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2816 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2817 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2818 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2819 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2820 filter->dst_port_mask = 0xffff;
2821 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2822 filter->src_port_mask = 0xffff;
2823 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2824 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2825 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2826 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2827 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2828 filter->ip_protocol = 17;
2829 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2830 filter->ip_addr_type =
2831 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2832 filter->src_ipaddr_mask[0] = 0xffffffff;
2833 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2834 filter->dst_ipaddr_mask[0] = 0xffffffff;
2835 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2836 filter->ethertype = 0x800;
2837 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2839 case RTE_ETH_FLOW_IPV6:
2840 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2842 filter->ip_addr_type =
2843 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2844 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2845 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2846 rte_memcpy(filter->src_ipaddr,
2847 fdir->input.flow.ipv6_flow.src_ip, 16);
2848 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2849 rte_memcpy(filter->dst_ipaddr,
2850 fdir->input.flow.ipv6_flow.dst_ip, 16);
2851 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2852 memset(filter->dst_ipaddr_mask, 0xff, 16);
2853 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2854 memset(filter->src_ipaddr_mask, 0xff, 16);
2855 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2856 filter->ethertype = 0x86dd;
2857 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2859 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2860 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2861 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2862 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2863 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2864 filter->dst_port_mask = 0xffff;
2865 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2866 filter->src_port_mask = 0xffff;
2867 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2868 filter->ip_addr_type =
2869 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2870 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2871 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2872 rte_memcpy(filter->src_ipaddr,
2873 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2874 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2875 rte_memcpy(filter->dst_ipaddr,
2876 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2877 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2878 memset(filter->dst_ipaddr_mask, 0xff, 16);
2879 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2880 memset(filter->src_ipaddr_mask, 0xff, 16);
2881 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2882 filter->ethertype = 0x86dd;
2883 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2885 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2886 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2887 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2888 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2889 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2890 filter->dst_port_mask = 0xffff;
2891 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2892 filter->src_port_mask = 0xffff;
2893 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2894 filter->ip_addr_type =
2895 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2896 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2897 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2898 rte_memcpy(filter->src_ipaddr,
2899 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2900 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2901 rte_memcpy(filter->dst_ipaddr,
2902 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2903 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2904 memset(filter->dst_ipaddr_mask, 0xff, 16);
2905 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2906 memset(filter->src_ipaddr_mask, 0xff, 16);
2907 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2908 filter->ethertype = 0x86dd;
2909 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2911 case RTE_ETH_FLOW_L2_PAYLOAD:
2912 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2913 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2915 case RTE_ETH_FLOW_VXLAN:
2916 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2918 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2919 filter->tunnel_type =
2920 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2921 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2923 case RTE_ETH_FLOW_NVGRE:
2924 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2926 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2927 filter->tunnel_type =
2928 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2929 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2931 case RTE_ETH_FLOW_UNKNOWN:
2932 case RTE_ETH_FLOW_RAW:
2933 case RTE_ETH_FLOW_FRAG_IPV4:
2934 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2935 case RTE_ETH_FLOW_FRAG_IPV6:
2936 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2937 case RTE_ETH_FLOW_IPV6_EX:
2938 case RTE_ETH_FLOW_IPV6_TCP_EX:
2939 case RTE_ETH_FLOW_IPV6_UDP_EX:
2940 case RTE_ETH_FLOW_GENEVE:
2946 vnic0 = &bp->vnic_info[0];
2947 vnic = &bp->vnic_info[fdir->action.rx_queue];
2949 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2953 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2954 rte_memcpy(filter->dst_macaddr,
2955 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2956 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2959 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2960 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2961 filter1 = STAILQ_FIRST(&vnic0->filter);
2962 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2964 filter->dst_id = vnic->fw_vnic_id;
2965 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2966 if (filter->dst_macaddr[i] == 0x00)
2967 filter1 = STAILQ_FIRST(&vnic0->filter);
2969 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2972 if (filter1 == NULL)
2975 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2976 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2978 filter->enables = en;
2983 static struct bnxt_filter_info *
2984 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2985 struct bnxt_vnic_info **mvnic)
2987 struct bnxt_filter_info *mf = NULL;
2990 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2991 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2993 STAILQ_FOREACH(mf, &vnic->filter, next) {
2994 if (mf->filter_type == nf->filter_type &&
2995 mf->flags == nf->flags &&
2996 mf->src_port == nf->src_port &&
2997 mf->src_port_mask == nf->src_port_mask &&
2998 mf->dst_port == nf->dst_port &&
2999 mf->dst_port_mask == nf->dst_port_mask &&
3000 mf->ip_protocol == nf->ip_protocol &&
3001 mf->ip_addr_type == nf->ip_addr_type &&
3002 mf->ethertype == nf->ethertype &&
3003 mf->vni == nf->vni &&
3004 mf->tunnel_type == nf->tunnel_type &&
3005 mf->l2_ovlan == nf->l2_ovlan &&
3006 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3007 mf->l2_ivlan == nf->l2_ivlan &&
3008 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3009 !memcmp(mf->l2_addr, nf->l2_addr,
3010 RTE_ETHER_ADDR_LEN) &&
3011 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3012 RTE_ETHER_ADDR_LEN) &&
3013 !memcmp(mf->src_macaddr, nf->src_macaddr,
3014 RTE_ETHER_ADDR_LEN) &&
3015 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3016 RTE_ETHER_ADDR_LEN) &&
3017 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3018 sizeof(nf->src_ipaddr)) &&
3019 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3020 sizeof(nf->src_ipaddr_mask)) &&
3021 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3022 sizeof(nf->dst_ipaddr)) &&
3023 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3024 sizeof(nf->dst_ipaddr_mask))) {
3035 bnxt_fdir_filter(struct rte_eth_dev *dev,
3036 enum rte_filter_op filter_op,
3039 struct bnxt *bp = dev->data->dev_private;
3040 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3041 struct bnxt_filter_info *filter, *match;
3042 struct bnxt_vnic_info *vnic, *mvnic;
3045 if (filter_op == RTE_ETH_FILTER_NOP)
3048 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3051 switch (filter_op) {
3052 case RTE_ETH_FILTER_ADD:
3053 case RTE_ETH_FILTER_DELETE:
3055 filter = bnxt_get_unused_filter(bp);
3056 if (filter == NULL) {
3058 "Not enough resources for a new flow.\n");
3062 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3065 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3067 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3068 vnic = &bp->vnic_info[0];
3070 vnic = &bp->vnic_info[fdir->action.rx_queue];
3072 match = bnxt_match_fdir(bp, filter, &mvnic);
3073 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3074 if (match->dst_id == vnic->fw_vnic_id) {
3075 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3079 match->dst_id = vnic->fw_vnic_id;
3080 ret = bnxt_hwrm_set_ntuple_filter(bp,
3083 STAILQ_REMOVE(&mvnic->filter, match,
3084 bnxt_filter_info, next);
3085 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3087 "Filter with matching pattern exist\n");
3089 "Updated it to new destination q\n");
3093 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3094 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3099 if (filter_op == RTE_ETH_FILTER_ADD) {
3100 ret = bnxt_hwrm_set_ntuple_filter(bp,
3105 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3107 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3108 STAILQ_REMOVE(&vnic->filter, match,
3109 bnxt_filter_info, next);
3110 bnxt_free_filter(bp, match);
3111 filter->fw_l2_filter_id = -1;
3112 bnxt_free_filter(bp, filter);
3115 case RTE_ETH_FILTER_FLUSH:
3116 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3117 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3119 STAILQ_FOREACH(filter, &vnic->filter, next) {
3120 if (filter->filter_type ==
3121 HWRM_CFA_NTUPLE_FILTER) {
3123 bnxt_hwrm_clear_ntuple_filter(bp,
3125 STAILQ_REMOVE(&vnic->filter, filter,
3126 bnxt_filter_info, next);
3131 case RTE_ETH_FILTER_UPDATE:
3132 case RTE_ETH_FILTER_STATS:
3133 case RTE_ETH_FILTER_INFO:
3134 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3137 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3144 filter->fw_l2_filter_id = -1;
3145 bnxt_free_filter(bp, filter);
3150 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3151 enum rte_filter_type filter_type,
3152 enum rte_filter_op filter_op, void *arg)
3156 ret = is_bnxt_in_error(dev->data->dev_private);
3160 switch (filter_type) {
3161 case RTE_ETH_FILTER_TUNNEL:
3163 "filter type: %d: To be implemented\n", filter_type);
3165 case RTE_ETH_FILTER_FDIR:
3166 ret = bnxt_fdir_filter(dev, filter_op, arg);
3168 case RTE_ETH_FILTER_NTUPLE:
3169 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3171 case RTE_ETH_FILTER_ETHERTYPE:
3172 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3174 case RTE_ETH_FILTER_GENERIC:
3175 if (filter_op != RTE_ETH_FILTER_GET)
3177 *(const void **)arg = &bnxt_flow_ops;
3181 "Filter type (%d) not supported", filter_type);
3188 static const uint32_t *
3189 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3191 static const uint32_t ptypes[] = {
3192 RTE_PTYPE_L2_ETHER_VLAN,
3193 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3194 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3198 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3199 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3200 RTE_PTYPE_INNER_L4_ICMP,
3201 RTE_PTYPE_INNER_L4_TCP,
3202 RTE_PTYPE_INNER_L4_UDP,
3206 if (!dev->rx_pkt_burst)
3212 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3215 uint32_t reg_base = *reg_arr & 0xfffff000;
3219 for (i = 0; i < count; i++) {
3220 if ((reg_arr[i] & 0xfffff000) != reg_base)
3223 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3224 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3228 static int bnxt_map_ptp_regs(struct bnxt *bp)
3230 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3234 reg_arr = ptp->rx_regs;
3235 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3239 reg_arr = ptp->tx_regs;
3240 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3244 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3245 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3247 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3248 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3253 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3255 rte_write32(0, (uint8_t *)bp->bar0 +
3256 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3257 rte_write32(0, (uint8_t *)bp->bar0 +
3258 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3261 static uint64_t bnxt_cc_read(struct bnxt *bp)
3265 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3266 BNXT_GRCPF_REG_SYNC_TIME));
3267 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3268 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3272 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3274 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3277 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3278 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3279 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3282 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3283 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3284 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3285 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3286 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3287 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3292 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3294 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3295 struct bnxt_pf_info *pf = &bp->pf;
3302 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3303 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3304 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3307 port_id = pf->port_id;
3308 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3309 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3311 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3312 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3313 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3314 /* bnxt_clr_rx_ts(bp); TBD */
3318 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3319 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3320 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3321 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3327 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3330 struct bnxt *bp = dev->data->dev_private;
3331 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3336 ns = rte_timespec_to_ns(ts);
3337 /* Set the timecounters to a new value. */
3344 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3346 struct bnxt *bp = dev->data->dev_private;
3347 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3348 uint64_t ns, systime_cycles = 0;
3354 if (BNXT_CHIP_THOR(bp))
3355 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3358 systime_cycles = bnxt_cc_read(bp);
3360 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3361 *ts = rte_ns_to_timespec(ns);
3366 bnxt_timesync_enable(struct rte_eth_dev *dev)
3368 struct bnxt *bp = dev->data->dev_private;
3369 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3377 ptp->tx_tstamp_en = 1;
3378 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3380 rc = bnxt_hwrm_ptp_cfg(bp);
3384 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3385 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3386 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3388 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3389 ptp->tc.cc_shift = shift;
3390 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3392 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3393 ptp->rx_tstamp_tc.cc_shift = shift;
3394 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3396 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3397 ptp->tx_tstamp_tc.cc_shift = shift;
3398 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3400 if (!BNXT_CHIP_THOR(bp))
3401 bnxt_map_ptp_regs(bp);
3407 bnxt_timesync_disable(struct rte_eth_dev *dev)
3409 struct bnxt *bp = dev->data->dev_private;
3410 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3416 ptp->tx_tstamp_en = 0;
3419 bnxt_hwrm_ptp_cfg(bp);
3421 if (!BNXT_CHIP_THOR(bp))
3422 bnxt_unmap_ptp_regs(bp);
3428 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3429 struct timespec *timestamp,
3430 uint32_t flags __rte_unused)
3432 struct bnxt *bp = dev->data->dev_private;
3433 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3434 uint64_t rx_tstamp_cycles = 0;
3440 if (BNXT_CHIP_THOR(bp))
3441 rx_tstamp_cycles = ptp->rx_timestamp;
3443 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3445 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3446 *timestamp = rte_ns_to_timespec(ns);
3451 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3452 struct timespec *timestamp)
3454 struct bnxt *bp = dev->data->dev_private;
3455 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3456 uint64_t tx_tstamp_cycles = 0;
3463 if (BNXT_CHIP_THOR(bp))
3464 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3467 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3469 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3470 *timestamp = rte_ns_to_timespec(ns);
3476 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3478 struct bnxt *bp = dev->data->dev_private;
3479 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3484 ptp->tc.nsec += delta;
3490 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3492 struct bnxt *bp = dev->data->dev_private;
3494 uint32_t dir_entries;
3495 uint32_t entry_length;
3497 rc = is_bnxt_in_error(bp);
3501 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3502 bp->pdev->addr.domain, bp->pdev->addr.bus,
3503 bp->pdev->addr.devid, bp->pdev->addr.function);
3505 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3509 return dir_entries * entry_length;
3513 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3514 struct rte_dev_eeprom_info *in_eeprom)
3516 struct bnxt *bp = dev->data->dev_private;
3521 rc = is_bnxt_in_error(bp);
3525 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3526 "len = %d\n", bp->pdev->addr.domain,
3527 bp->pdev->addr.bus, bp->pdev->addr.devid,
3528 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3530 if (in_eeprom->offset == 0) /* special offset value to get directory */
3531 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3534 index = in_eeprom->offset >> 24;
3535 offset = in_eeprom->offset & 0xffffff;
3538 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3539 in_eeprom->length, in_eeprom->data);
3544 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3547 case BNX_DIR_TYPE_CHIMP_PATCH:
3548 case BNX_DIR_TYPE_BOOTCODE:
3549 case BNX_DIR_TYPE_BOOTCODE_2:
3550 case BNX_DIR_TYPE_APE_FW:
3551 case BNX_DIR_TYPE_APE_PATCH:
3552 case BNX_DIR_TYPE_KONG_FW:
3553 case BNX_DIR_TYPE_KONG_PATCH:
3554 case BNX_DIR_TYPE_BONO_FW:
3555 case BNX_DIR_TYPE_BONO_PATCH:
3563 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3566 case BNX_DIR_TYPE_AVS:
3567 case BNX_DIR_TYPE_EXP_ROM_MBA:
3568 case BNX_DIR_TYPE_PCIE:
3569 case BNX_DIR_TYPE_TSCF_UCODE:
3570 case BNX_DIR_TYPE_EXT_PHY:
3571 case BNX_DIR_TYPE_CCM:
3572 case BNX_DIR_TYPE_ISCSI_BOOT:
3573 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3574 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3582 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3584 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3585 bnxt_dir_type_is_other_exec_format(dir_type);
3589 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3590 struct rte_dev_eeprom_info *in_eeprom)
3592 struct bnxt *bp = dev->data->dev_private;
3593 uint8_t index, dir_op;
3594 uint16_t type, ext, ordinal, attr;
3597 rc = is_bnxt_in_error(bp);
3601 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3602 "len = %d\n", bp->pdev->addr.domain,
3603 bp->pdev->addr.bus, bp->pdev->addr.devid,
3604 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3607 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3611 type = in_eeprom->magic >> 16;
3613 if (type == 0xffff) { /* special value for directory operations */
3614 index = in_eeprom->magic & 0xff;
3615 dir_op = in_eeprom->magic >> 8;
3619 case 0x0e: /* erase */
3620 if (in_eeprom->offset != ~in_eeprom->magic)
3622 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3628 /* Create or re-write an NVM item: */
3629 if (bnxt_dir_type_is_executable(type) == true)
3631 ext = in_eeprom->magic & 0xffff;
3632 ordinal = in_eeprom->offset >> 16;
3633 attr = in_eeprom->offset & 0xffff;
3635 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3636 in_eeprom->data, in_eeprom->length);
3643 static const struct eth_dev_ops bnxt_dev_ops = {
3644 .dev_infos_get = bnxt_dev_info_get_op,
3645 .dev_close = bnxt_dev_close_op,
3646 .dev_configure = bnxt_dev_configure_op,
3647 .dev_start = bnxt_dev_start_op,
3648 .dev_stop = bnxt_dev_stop_op,
3649 .dev_set_link_up = bnxt_dev_set_link_up_op,
3650 .dev_set_link_down = bnxt_dev_set_link_down_op,
3651 .stats_get = bnxt_stats_get_op,
3652 .stats_reset = bnxt_stats_reset_op,
3653 .rx_queue_setup = bnxt_rx_queue_setup_op,
3654 .rx_queue_release = bnxt_rx_queue_release_op,
3655 .tx_queue_setup = bnxt_tx_queue_setup_op,
3656 .tx_queue_release = bnxt_tx_queue_release_op,
3657 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3658 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3659 .reta_update = bnxt_reta_update_op,
3660 .reta_query = bnxt_reta_query_op,
3661 .rss_hash_update = bnxt_rss_hash_update_op,
3662 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3663 .link_update = bnxt_link_update_op,
3664 .promiscuous_enable = bnxt_promiscuous_enable_op,
3665 .promiscuous_disable = bnxt_promiscuous_disable_op,
3666 .allmulticast_enable = bnxt_allmulticast_enable_op,
3667 .allmulticast_disable = bnxt_allmulticast_disable_op,
3668 .mac_addr_add = bnxt_mac_addr_add_op,
3669 .mac_addr_remove = bnxt_mac_addr_remove_op,
3670 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3671 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3672 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3673 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3674 .vlan_filter_set = bnxt_vlan_filter_set_op,
3675 .vlan_offload_set = bnxt_vlan_offload_set_op,
3676 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3677 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3678 .mtu_set = bnxt_mtu_set_op,
3679 .mac_addr_set = bnxt_set_default_mac_addr_op,
3680 .xstats_get = bnxt_dev_xstats_get_op,
3681 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3682 .xstats_reset = bnxt_dev_xstats_reset_op,
3683 .fw_version_get = bnxt_fw_version_get,
3684 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3685 .rxq_info_get = bnxt_rxq_info_get_op,
3686 .txq_info_get = bnxt_txq_info_get_op,
3687 .dev_led_on = bnxt_dev_led_on_op,
3688 .dev_led_off = bnxt_dev_led_off_op,
3689 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3690 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3691 .rx_queue_count = bnxt_rx_queue_count_op,
3692 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3693 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3694 .rx_queue_start = bnxt_rx_queue_start,
3695 .rx_queue_stop = bnxt_rx_queue_stop,
3696 .tx_queue_start = bnxt_tx_queue_start,
3697 .tx_queue_stop = bnxt_tx_queue_stop,
3698 .filter_ctrl = bnxt_filter_ctrl_op,
3699 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3700 .get_eeprom_length = bnxt_get_eeprom_length_op,
3701 .get_eeprom = bnxt_get_eeprom_op,
3702 .set_eeprom = bnxt_set_eeprom_op,
3703 .timesync_enable = bnxt_timesync_enable,
3704 .timesync_disable = bnxt_timesync_disable,
3705 .timesync_read_time = bnxt_timesync_read_time,
3706 .timesync_write_time = bnxt_timesync_write_time,
3707 .timesync_adjust_time = bnxt_timesync_adjust_time,
3708 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3709 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3712 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3716 /* Only pre-map the reset GRC registers using window 3 */
3717 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3718 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3720 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3725 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3727 struct bnxt_error_recovery_info *info = bp->recovery_info;
3728 uint32_t reg_base = 0xffffffff;
3731 /* Only pre-map the monitoring GRC registers using window 2 */
3732 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3733 uint32_t reg = info->status_regs[i];
3735 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3738 if (reg_base == 0xffffffff)
3739 reg_base = reg & 0xfffff000;
3740 if ((reg & 0xfffff000) != reg_base)
3743 /* Use mask 0xffc as the Lower 2 bits indicates
3744 * address space location
3746 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3750 if (reg_base == 0xffffffff)
3753 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3754 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3759 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3761 struct bnxt_error_recovery_info *info = bp->recovery_info;
3762 uint32_t delay = info->delay_after_reset[index];
3763 uint32_t val = info->reset_reg_val[index];
3764 uint32_t reg = info->reset_reg[index];
3765 uint32_t type, offset;
3767 type = BNXT_FW_STATUS_REG_TYPE(reg);
3768 offset = BNXT_FW_STATUS_REG_OFF(reg);
3771 case BNXT_FW_STATUS_REG_TYPE_CFG:
3772 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3774 case BNXT_FW_STATUS_REG_TYPE_GRC:
3775 offset = bnxt_map_reset_regs(bp, offset);
3776 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3778 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3779 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3782 /* wait on a specific interval of time until core reset is complete */
3784 rte_delay_ms(delay);
3787 static void bnxt_dev_cleanup(struct bnxt *bp)
3789 bnxt_set_hwrm_link_config(bp, false);
3790 bp->link_info.link_up = 0;
3791 if (bp->dev_stopped == 0)
3792 bnxt_dev_stop_op(bp->eth_dev);
3794 bnxt_uninit_resources(bp, true);
3797 static int bnxt_restore_filters(struct bnxt *bp)
3799 struct rte_eth_dev *dev = bp->eth_dev;
3802 if (dev->data->all_multicast)
3803 ret = bnxt_allmulticast_enable_op(dev);
3804 if (dev->data->promiscuous)
3805 ret = bnxt_promiscuous_enable_op(dev);
3807 /* TODO restore other filters as well */
3811 static void bnxt_dev_recover(void *arg)
3813 struct bnxt *bp = arg;
3814 int timeout = bp->fw_reset_max_msecs;
3817 /* Clear Error flag so that device re-init should happen */
3818 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3821 rc = bnxt_hwrm_ver_get(bp);
3824 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3825 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3826 } while (rc && timeout);
3829 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3833 rc = bnxt_init_resources(bp, true);
3836 "Failed to initialize resources after reset\n");
3839 /* clear reset flag as the device is initialized now */
3840 bp->flags &= ~BNXT_FLAG_FW_RESET;
3842 rc = bnxt_dev_start_op(bp->eth_dev);
3844 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3848 rc = bnxt_restore_filters(bp);
3852 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3855 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3856 bnxt_uninit_resources(bp, false);
3857 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3860 void bnxt_dev_reset_and_resume(void *arg)
3862 struct bnxt *bp = arg;
3865 bnxt_dev_cleanup(bp);
3867 bnxt_wait_for_device_shutdown(bp);
3869 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3870 bnxt_dev_recover, (void *)bp);
3872 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3875 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3877 struct bnxt_error_recovery_info *info = bp->recovery_info;
3878 uint32_t reg = info->status_regs[index];
3879 uint32_t type, offset, val = 0;
3881 type = BNXT_FW_STATUS_REG_TYPE(reg);
3882 offset = BNXT_FW_STATUS_REG_OFF(reg);
3885 case BNXT_FW_STATUS_REG_TYPE_CFG:
3886 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3888 case BNXT_FW_STATUS_REG_TYPE_GRC:
3889 offset = info->mapped_status_regs[index];
3891 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3892 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3900 static int bnxt_fw_reset_all(struct bnxt *bp)
3902 struct bnxt_error_recovery_info *info = bp->recovery_info;
3906 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3907 /* Reset through master function driver */
3908 for (i = 0; i < info->reg_array_cnt; i++)
3909 bnxt_write_fw_reset_reg(bp, i);
3910 /* Wait for time specified by FW after triggering reset */
3911 rte_delay_ms(info->master_func_wait_period_after_reset);
3912 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3913 /* Reset with the help of Kong processor */
3914 rc = bnxt_hwrm_fw_reset(bp);
3916 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3922 static void bnxt_fw_reset_cb(void *arg)
3924 struct bnxt *bp = arg;
3925 struct bnxt_error_recovery_info *info = bp->recovery_info;
3928 /* Only Master function can do FW reset */
3929 if (bnxt_is_master_func(bp) &&
3930 bnxt_is_recovery_enabled(bp)) {
3931 rc = bnxt_fw_reset_all(bp);
3933 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3938 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3939 * EXCEPTION_FATAL_ASYNC event to all the functions
3940 * (including MASTER FUNC). After receiving this Async, all the active
3941 * drivers should treat this case as FW initiated recovery
3943 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3944 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3945 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3947 /* To recover from error */
3948 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3953 /* Driver should poll FW heartbeat, reset_counter with the frequency
3954 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3955 * When the driver detects heartbeat stop or change in reset_counter,
3956 * it has to trigger a reset to recover from the error condition.
3957 * A “master PF” is the function who will have the privilege to
3958 * initiate the chimp reset. The master PF will be elected by the
3959 * firmware and will be notified through async message.
3961 static void bnxt_check_fw_health(void *arg)
3963 struct bnxt *bp = arg;
3964 struct bnxt_error_recovery_info *info = bp->recovery_info;
3965 uint32_t val = 0, wait_msec;
3967 if (!info || !bnxt_is_recovery_enabled(bp) ||
3968 is_bnxt_in_error(bp))
3971 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3972 if (val == info->last_heart_beat)
3975 info->last_heart_beat = val;
3977 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3978 if (val != info->last_reset_counter)
3981 info->last_reset_counter = val;
3983 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3984 bnxt_check_fw_health, (void *)bp);
3988 /* Stop DMA to/from device */
3989 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3990 bp->flags |= BNXT_FLAG_FW_RESET;
3992 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3994 if (bnxt_is_master_func(bp))
3995 wait_msec = info->master_func_wait_period;
3997 wait_msec = info->normal_func_wait_period;
3999 rte_eal_alarm_set(US_PER_MS * wait_msec,
4000 bnxt_fw_reset_cb, (void *)bp);
4003 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4005 uint32_t polling_freq;
4007 if (!bnxt_is_recovery_enabled(bp))
4010 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4013 polling_freq = bp->recovery_info->driver_polling_freq;
4015 rte_eal_alarm_set(US_PER_MS * polling_freq,
4016 bnxt_check_fw_health, (void *)bp);
4017 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4020 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4022 if (!bnxt_is_recovery_enabled(bp))
4025 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4026 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4029 static bool bnxt_vf_pciid(uint16_t id)
4031 if (id == BROADCOM_DEV_ID_57304_VF ||
4032 id == BROADCOM_DEV_ID_57406_VF ||
4033 id == BROADCOM_DEV_ID_5731X_VF ||
4034 id == BROADCOM_DEV_ID_5741X_VF ||
4035 id == BROADCOM_DEV_ID_57414_VF ||
4036 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4037 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
4038 id == BROADCOM_DEV_ID_58802_VF ||
4039 id == BROADCOM_DEV_ID_57500_VF1 ||
4040 id == BROADCOM_DEV_ID_57500_VF2)
4045 static bool bnxt_thor_device(uint16_t id)
4047 if (id == BROADCOM_DEV_ID_57508 ||
4048 id == BROADCOM_DEV_ID_57504 ||
4049 id == BROADCOM_DEV_ID_57502 ||
4050 id == BROADCOM_DEV_ID_57508_MF1 ||
4051 id == BROADCOM_DEV_ID_57504_MF1 ||
4052 id == BROADCOM_DEV_ID_57502_MF1 ||
4053 id == BROADCOM_DEV_ID_57508_MF2 ||
4054 id == BROADCOM_DEV_ID_57504_MF2 ||
4055 id == BROADCOM_DEV_ID_57502_MF2 ||
4056 id == BROADCOM_DEV_ID_57500_VF1 ||
4057 id == BROADCOM_DEV_ID_57500_VF2)
4063 bool bnxt_stratus_device(struct bnxt *bp)
4065 uint16_t id = bp->pdev->id.device_id;
4067 if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
4068 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4069 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
4074 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4076 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4077 struct bnxt *bp = eth_dev->data->dev_private;
4079 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4080 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4081 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4082 if (!bp->bar0 || !bp->doorbell_base) {
4083 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4087 bp->eth_dev = eth_dev;
4093 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
4094 struct bnxt_ctx_pg_info *ctx_pg,
4099 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4100 const struct rte_memzone *mz = NULL;
4101 char mz_name[RTE_MEMZONE_NAMESIZE];
4102 rte_iova_t mz_phys_addr;
4103 uint64_t valid_bits = 0;
4110 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4112 rmem->page_size = BNXT_PAGE_SIZE;
4113 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4114 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4115 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4117 valid_bits = PTU_PTE_VALID;
4119 if (rmem->nr_pages > 1) {
4120 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4121 "bnxt_ctx_pg_tbl%s_%x_%d",
4122 suffix, idx, bp->eth_dev->data->port_id);
4123 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4124 mz = rte_memzone_lookup(mz_name);
4126 mz = rte_memzone_reserve_aligned(mz_name,
4130 RTE_MEMZONE_SIZE_HINT_ONLY |
4131 RTE_MEMZONE_IOVA_CONTIG,
4137 memset(mz->addr, 0, mz->len);
4138 mz_phys_addr = mz->iova;
4139 if ((unsigned long)mz->addr == mz_phys_addr) {
4141 "physical address same as virtual\n");
4142 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4143 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4144 if (mz_phys_addr == RTE_BAD_IOVA) {
4146 "unable to map addr to phys memory\n");
4150 rte_mem_lock_page(((char *)mz->addr));
4152 rmem->pg_tbl = mz->addr;
4153 rmem->pg_tbl_map = mz_phys_addr;
4154 rmem->pg_tbl_mz = mz;
4157 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4158 suffix, idx, bp->eth_dev->data->port_id);
4159 mz = rte_memzone_lookup(mz_name);
4161 mz = rte_memzone_reserve_aligned(mz_name,
4165 RTE_MEMZONE_SIZE_HINT_ONLY |
4166 RTE_MEMZONE_IOVA_CONTIG,
4172 memset(mz->addr, 0, mz->len);
4173 mz_phys_addr = mz->iova;
4174 if ((unsigned long)mz->addr == mz_phys_addr) {
4176 "Memzone physical address same as virtual.\n");
4177 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4178 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4179 rte_mem_lock_page(((char *)mz->addr) + sz);
4180 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4181 if (mz_phys_addr == RTE_BAD_IOVA) {
4183 "unable to map addr to phys memory\n");
4188 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4189 rte_mem_lock_page(((char *)mz->addr) + sz);
4190 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4191 rmem->dma_arr[i] = mz_phys_addr + sz;
4193 if (rmem->nr_pages > 1) {
4194 if (i == rmem->nr_pages - 2 &&
4195 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4196 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4197 else if (i == rmem->nr_pages - 1 &&
4198 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4199 valid_bits |= PTU_PTE_LAST;
4201 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4207 if (rmem->vmem_size)
4208 rmem->vmem = (void **)mz->addr;
4209 rmem->dma_arr[0] = mz_phys_addr;
4213 static void bnxt_free_ctx_mem(struct bnxt *bp)
4217 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4220 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4221 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4222 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4223 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4224 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4225 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4226 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4227 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4228 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4229 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4230 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4232 for (i = 0; i < BNXT_MAX_Q; i++) {
4233 if (bp->ctx->tqm_mem[i])
4234 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4241 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4243 #define min_t(type, x, y) ({ \
4244 type __min1 = (x); \
4245 type __min2 = (y); \
4246 __min1 < __min2 ? __min1 : __min2; })
4248 #define max_t(type, x, y) ({ \
4249 type __max1 = (x); \
4250 type __max2 = (y); \
4251 __max1 > __max2 ? __max1 : __max2; })
4253 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4255 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4257 struct bnxt_ctx_pg_info *ctx_pg;
4258 struct bnxt_ctx_mem_info *ctx;
4259 uint32_t mem_size, ena, entries;
4262 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4264 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4268 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4271 ctx_pg = &ctx->qp_mem;
4272 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4273 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4274 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4278 ctx_pg = &ctx->srq_mem;
4279 ctx_pg->entries = ctx->srq_max_l2_entries;
4280 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4281 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4285 ctx_pg = &ctx->cq_mem;
4286 ctx_pg->entries = ctx->cq_max_l2_entries;
4287 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4288 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4292 ctx_pg = &ctx->vnic_mem;
4293 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4294 ctx->vnic_max_ring_table_entries;
4295 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4296 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4300 ctx_pg = &ctx->stat_mem;
4301 ctx_pg->entries = ctx->stat_max_entries;
4302 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4303 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4307 entries = ctx->qp_max_l2_entries +
4308 ctx->vnic_max_vnic_entries +
4309 ctx->tqm_min_entries_per_ring;
4310 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4311 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4312 ctx->tqm_max_entries_per_ring);
4313 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4314 ctx_pg = ctx->tqm_mem[i];
4315 /* use min tqm entries for now. */
4316 ctx_pg->entries = entries;
4317 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4318 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4321 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4324 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4325 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4328 "Failed to configure context mem: rc = %d\n", rc);
4330 ctx->flags |= BNXT_CTX_FLAG_INITED;
4335 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4337 struct rte_pci_device *pci_dev = bp->pdev;
4338 char mz_name[RTE_MEMZONE_NAMESIZE];
4339 const struct rte_memzone *mz = NULL;
4340 uint32_t total_alloc_len;
4341 rte_iova_t mz_phys_addr;
4343 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4346 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4347 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4348 pci_dev->addr.bus, pci_dev->addr.devid,
4349 pci_dev->addr.function, "rx_port_stats");
4350 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4351 mz = rte_memzone_lookup(mz_name);
4353 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4354 sizeof(struct rx_port_stats_ext) + 512);
4356 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4359 RTE_MEMZONE_SIZE_HINT_ONLY |
4360 RTE_MEMZONE_IOVA_CONTIG);
4364 memset(mz->addr, 0, mz->len);
4365 mz_phys_addr = mz->iova;
4366 if ((unsigned long)mz->addr == mz_phys_addr) {
4368 "Memzone physical address same as virtual.\n");
4370 "Using rte_mem_virt2iova()\n");
4371 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4372 if (mz_phys_addr == RTE_BAD_IOVA) {
4374 "Can't map address to physical memory\n");
4379 bp->rx_mem_zone = (const void *)mz;
4380 bp->hw_rx_port_stats = mz->addr;
4381 bp->hw_rx_port_stats_map = mz_phys_addr;
4383 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4384 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4385 pci_dev->addr.bus, pci_dev->addr.devid,
4386 pci_dev->addr.function, "tx_port_stats");
4387 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4388 mz = rte_memzone_lookup(mz_name);
4390 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4391 sizeof(struct tx_port_stats_ext) + 512);
4393 mz = rte_memzone_reserve(mz_name,
4397 RTE_MEMZONE_SIZE_HINT_ONLY |
4398 RTE_MEMZONE_IOVA_CONTIG);
4402 memset(mz->addr, 0, mz->len);
4403 mz_phys_addr = mz->iova;
4404 if ((unsigned long)mz->addr == mz_phys_addr) {
4406 "Memzone physical address same as virtual\n");
4407 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4408 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4409 if (mz_phys_addr == RTE_BAD_IOVA) {
4411 "Can't map address to physical memory\n");
4416 bp->tx_mem_zone = (const void *)mz;
4417 bp->hw_tx_port_stats = mz->addr;
4418 bp->hw_tx_port_stats_map = mz_phys_addr;
4419 bp->flags |= BNXT_FLAG_PORT_STATS;
4421 /* Display extended statistics if FW supports it */
4422 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4423 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4424 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4427 bp->hw_rx_port_stats_ext = (void *)
4428 ((uint8_t *)bp->hw_rx_port_stats +
4429 sizeof(struct rx_port_stats));
4430 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4431 sizeof(struct rx_port_stats);
4432 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4434 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4435 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4436 bp->hw_tx_port_stats_ext = (void *)
4437 ((uint8_t *)bp->hw_tx_port_stats +
4438 sizeof(struct tx_port_stats));
4439 bp->hw_tx_port_stats_ext_map =
4440 bp->hw_tx_port_stats_map +
4441 sizeof(struct tx_port_stats);
4442 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4448 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4450 struct bnxt *bp = eth_dev->data->dev_private;
4453 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4454 RTE_ETHER_ADDR_LEN *
4457 if (eth_dev->data->mac_addrs == NULL) {
4458 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4462 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4466 /* Generate a random MAC address, if none was assigned by PF */
4467 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4468 bnxt_eth_hw_addr_random(bp->mac_addr);
4470 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4471 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4472 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4474 rc = bnxt_hwrm_set_mac(bp);
4476 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4477 RTE_ETHER_ADDR_LEN);
4481 /* Copy the permanent MAC from the FUNC_QCAPS response */
4482 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4483 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4488 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4492 /* MAC is already configured in FW */
4493 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4496 /* Restore the old MAC configured */
4497 rc = bnxt_hwrm_set_mac(bp);
4499 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4504 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4509 #define ALLOW_FUNC(x) \
4511 uint32_t arg = (x); \
4512 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4513 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4516 /* Forward all requests if firmware is new enough */
4517 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4518 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4519 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4520 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4522 PMD_DRV_LOG(WARNING,
4523 "Firmware too old for VF mailbox functionality\n");
4524 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4528 * The following are used for driver cleanup. If we disallow these,
4529 * VF drivers can't clean up cleanly.
4531 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4532 ALLOW_FUNC(HWRM_VNIC_FREE);
4533 ALLOW_FUNC(HWRM_RING_FREE);
4534 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4535 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4536 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4537 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4538 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4539 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4542 static int bnxt_init_fw(struct bnxt *bp)
4547 rc = bnxt_hwrm_ver_get(bp);
4551 rc = bnxt_hwrm_func_reset(bp);
4555 rc = bnxt_hwrm_vnic_qcaps(bp);
4559 rc = bnxt_hwrm_queue_qportcfg(bp);
4563 /* Get the MAX capabilities for this function.
4564 * This function also allocates context memory for TQM rings and
4565 * informs the firmware about this allocated backing store memory.
4567 rc = bnxt_hwrm_func_qcaps(bp);
4571 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4575 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4579 /* Get the adapter error recovery support info */
4580 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4582 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4584 if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4585 mtu != bp->eth_dev->data->mtu)
4586 bp->eth_dev->data->mtu = mtu;
4588 bnxt_hwrm_port_led_qcaps(bp);
4594 bnxt_init_locks(struct bnxt *bp)
4598 err = pthread_mutex_init(&bp->flow_lock, NULL);
4600 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4604 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4606 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4610 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4614 rc = bnxt_init_fw(bp);
4618 if (!reconfig_dev) {
4619 rc = bnxt_setup_mac_addr(bp->eth_dev);
4623 rc = bnxt_restore_dflt_mac(bp);
4628 bnxt_config_vf_req_fwd(bp);
4630 rc = bnxt_hwrm_func_driver_register(bp);
4632 PMD_DRV_LOG(ERR, "Failed to register driver");
4637 if (bp->pdev->max_vfs) {
4638 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4640 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4644 rc = bnxt_hwrm_allocate_pf_only(bp);
4647 "Failed to allocate PF resources");
4653 rc = bnxt_alloc_mem(bp, reconfig_dev);
4657 rc = bnxt_setup_int(bp);
4661 rc = bnxt_request_int(bp);
4665 rc = bnxt_init_locks(bp);
4673 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4675 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4676 static int version_printed;
4680 if (version_printed++ == 0)
4681 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4683 eth_dev->dev_ops = &bnxt_dev_ops;
4684 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4685 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4688 * For secondary processes, we don't initialise any further
4689 * as primary has already done this work.
4691 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4694 rte_eth_copy_pci_info(eth_dev, pci_dev);
4696 bp = eth_dev->data->dev_private;
4698 bp->dev_stopped = 1;
4700 if (bnxt_vf_pciid(pci_dev->id.device_id))
4701 bp->flags |= BNXT_FLAG_VF;
4703 if (bnxt_thor_device(pci_dev->id.device_id))
4704 bp->flags |= BNXT_FLAG_THOR_CHIP;
4706 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4707 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4708 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4709 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4710 bp->flags |= BNXT_FLAG_STINGRAY;
4712 rc = bnxt_init_board(eth_dev);
4715 "Failed to initialize board rc: %x\n", rc);
4719 rc = bnxt_alloc_hwrm_resources(bp);
4722 "Failed to allocate hwrm resource rc: %x\n", rc);
4725 rc = bnxt_init_resources(bp, false);
4729 rc = bnxt_alloc_stats_mem(bp);
4734 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4735 pci_dev->mem_resource[0].phys_addr,
4736 pci_dev->mem_resource[0].addr);
4741 bnxt_dev_uninit(eth_dev);
4746 bnxt_uninit_locks(struct bnxt *bp)
4748 pthread_mutex_destroy(&bp->flow_lock);
4749 pthread_mutex_destroy(&bp->def_cp_lock);
4753 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4758 bnxt_free_mem(bp, reconfig_dev);
4759 bnxt_hwrm_func_buf_unrgtr(bp);
4760 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4761 bp->flags &= ~BNXT_FLAG_REGISTERED;
4762 bnxt_free_ctx_mem(bp);
4763 if (!reconfig_dev) {
4764 bnxt_free_hwrm_resources(bp);
4766 if (bp->recovery_info != NULL) {
4767 rte_free(bp->recovery_info);
4768 bp->recovery_info = NULL;
4772 bnxt_uninit_locks(bp);
4773 rte_free(bp->ptp_cfg);
4779 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4781 struct bnxt *bp = eth_dev->data->dev_private;
4784 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4787 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4789 rc = bnxt_uninit_resources(bp, false);
4791 if (bp->tx_mem_zone) {
4792 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4793 bp->tx_mem_zone = NULL;
4796 if (bp->rx_mem_zone) {
4797 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4798 bp->rx_mem_zone = NULL;
4801 if (bp->dev_stopped == 0)
4802 bnxt_dev_close_op(eth_dev);
4804 rte_free(bp->pf.vf_info);
4805 eth_dev->dev_ops = NULL;
4806 eth_dev->rx_pkt_burst = NULL;
4807 eth_dev->tx_pkt_burst = NULL;
4812 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4813 struct rte_pci_device *pci_dev)
4815 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4819 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4821 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4822 return rte_eth_dev_pci_generic_remove(pci_dev,
4825 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4828 static struct rte_pci_driver bnxt_rte_pmd = {
4829 .id_table = bnxt_pci_id_map,
4830 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4831 .probe = bnxt_pci_probe,
4832 .remove = bnxt_pci_remove,
4836 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4838 if (strcmp(dev->device->driver->name, drv->driver.name))
4844 bool is_bnxt_supported(struct rte_eth_dev *dev)
4846 return is_device_supported(dev, &bnxt_rte_pmd);
4849 RTE_INIT(bnxt_init_log)
4851 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4852 if (bnxt_logtype_driver >= 0)
4853 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4856 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4857 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4858 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");