4 * Copyright(c) Broadcom Limited.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include <rte_ethdev.h>
39 #include <rte_ethdev_pci.h>
40 #include <rte_malloc.h>
41 #include <rte_cycles.h>
45 #include "bnxt_filter.h"
46 #include "bnxt_hwrm.h"
48 #include "bnxt_ring.h"
51 #include "bnxt_stats.h"
54 #include "bnxt_vnic.h"
55 #include "hsi_struct_def_dpdk.h"
57 #define DRV_MODULE_NAME "bnxt"
58 static const char bnxt_version[] =
59 "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
61 #define PCI_VENDOR_ID_BROADCOM 0x14E4
63 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
64 #define BROADCOM_DEV_ID_57414_VF 0x16c1
65 #define BROADCOM_DEV_ID_57301 0x16c8
66 #define BROADCOM_DEV_ID_57302 0x16c9
67 #define BROADCOM_DEV_ID_57304_PF 0x16ca
68 #define BROADCOM_DEV_ID_57304_VF 0x16cb
69 #define BROADCOM_DEV_ID_57417_MF 0x16cc
70 #define BROADCOM_DEV_ID_NS2 0x16cd
71 #define BROADCOM_DEV_ID_57311 0x16ce
72 #define BROADCOM_DEV_ID_57312 0x16cf
73 #define BROADCOM_DEV_ID_57402 0x16d0
74 #define BROADCOM_DEV_ID_57404 0x16d1
75 #define BROADCOM_DEV_ID_57406_PF 0x16d2
76 #define BROADCOM_DEV_ID_57406_VF 0x16d3
77 #define BROADCOM_DEV_ID_57402_MF 0x16d4
78 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
79 #define BROADCOM_DEV_ID_57412 0x16d6
80 #define BROADCOM_DEV_ID_57414 0x16d7
81 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
82 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
83 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
84 #define BROADCOM_DEV_ID_57412_MF 0x16de
85 #define BROADCOM_DEV_ID_57314 0x16df
86 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
87 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
88 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
89 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
90 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
91 #define BROADCOM_DEV_ID_57404_MF 0x16e7
92 #define BROADCOM_DEV_ID_57406_MF 0x16e8
93 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
94 #define BROADCOM_DEV_ID_57407_MF 0x16ea
95 #define BROADCOM_DEV_ID_57414_MF 0x16ec
96 #define BROADCOM_DEV_ID_57416_MF 0x16ee
98 static const struct rte_pci_id bnxt_pci_id_map[] = {
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
130 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
131 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
132 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
133 { .vendor_id = 0, /* sentinel */ },
136 #define BNXT_ETH_RSS_SUPPORT ( \
138 ETH_RSS_NONFRAG_IPV4_TCP | \
139 ETH_RSS_NONFRAG_IPV4_UDP | \
141 ETH_RSS_NONFRAG_IPV6_TCP | \
142 ETH_RSS_NONFRAG_IPV6_UDP)
144 /***********************/
147 * High level utility functions
150 static void bnxt_free_mem(struct bnxt *bp)
152 bnxt_free_filter_mem(bp);
153 bnxt_free_vnic_attributes(bp);
154 bnxt_free_vnic_mem(bp);
157 bnxt_free_tx_rings(bp);
158 bnxt_free_rx_rings(bp);
159 bnxt_free_def_cp_ring(bp);
162 static int bnxt_alloc_mem(struct bnxt *bp)
166 /* Default completion ring */
167 rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
171 rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
172 bp->def_cp_ring, "def_cp");
176 rc = bnxt_alloc_vnic_mem(bp);
180 rc = bnxt_alloc_vnic_attributes(bp);
184 rc = bnxt_alloc_filter_mem(bp);
195 static int bnxt_init_chip(struct bnxt *bp)
197 unsigned int i, rss_idx, fw_idx;
198 struct rte_eth_link new;
201 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
203 RTE_LOG(ERR, PMD, "HWRM stat ctx alloc failure rc: %x\n", rc);
207 rc = bnxt_alloc_hwrm_rings(bp);
209 RTE_LOG(ERR, PMD, "HWRM ring alloc failure rc: %x\n", rc);
213 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
215 RTE_LOG(ERR, PMD, "HWRM ring grp alloc failure: %x\n", rc);
219 rc = bnxt_mq_rx_configure(bp);
221 RTE_LOG(ERR, PMD, "MQ mode configure failure rc: %x\n", rc);
225 /* VNIC configuration */
226 for (i = 0; i < bp->nr_vnics; i++) {
227 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
229 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
231 RTE_LOG(ERR, PMD, "HWRM vnic alloc failure rc: %x\n",
236 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
239 "HWRM vnic ctx alloc failure rc: %x\n", rc);
243 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
245 RTE_LOG(ERR, PMD, "HWRM vnic cfg failure rc: %x\n", rc);
249 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
251 RTE_LOG(ERR, PMD, "HWRM vnic filter failure rc: %x\n",
255 if (vnic->rss_table && vnic->hash_type) {
257 * Fill the RSS hash & redirection table with
258 * ring group ids for all VNICs
260 for (rss_idx = 0, fw_idx = 0;
261 rss_idx < HW_HASH_INDEX_SIZE;
262 rss_idx++, fw_idx++) {
263 if (vnic->fw_grp_ids[fw_idx] ==
266 vnic->rss_table[rss_idx] =
267 vnic->fw_grp_ids[fw_idx];
269 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
272 "HWRM vnic set RSS failure rc: %x\n",
278 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0]);
281 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
285 rc = bnxt_get_hwrm_link_config(bp, &new);
287 RTE_LOG(ERR, PMD, "HWRM Get link config failure rc: %x\n", rc);
291 if (!bp->link_info.link_up) {
292 rc = bnxt_set_hwrm_link_config(bp, true);
295 "HWRM link config failure rc: %x\n", rc);
303 bnxt_free_all_hwrm_resources(bp);
308 static int bnxt_shutdown_nic(struct bnxt *bp)
310 bnxt_free_all_hwrm_resources(bp);
311 bnxt_free_all_filters(bp);
312 bnxt_free_all_vnics(bp);
316 static int bnxt_init_nic(struct bnxt *bp)
320 bnxt_init_ring_grps(bp);
322 bnxt_init_filters(bp);
324 rc = bnxt_init_chip(bp);
332 * Device configuration and status function
335 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
336 struct rte_eth_dev_info *dev_info)
338 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
339 uint16_t max_vnics, i, j, vpool, vrxq;
341 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
344 dev_info->max_mac_addrs = MAX_NUM_MAC_ADDR;
345 dev_info->max_hash_mac_addrs = 0;
347 /* PF/VF specifics */
349 dev_info->max_vfs = bp->pdev->max_vfs;
350 dev_info->max_rx_queues = bp->max_rx_rings;
351 dev_info->max_tx_queues = bp->max_tx_rings;
352 dev_info->reta_size = bp->max_rsscos_ctx;
353 max_vnics = bp->max_vnics;
355 /* Fast path specifics */
356 dev_info->min_rx_bufsize = 1;
357 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
359 dev_info->rx_offload_capa = 0;
360 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
361 DEV_TX_OFFLOAD_TCP_CKSUM |
362 DEV_TX_OFFLOAD_UDP_CKSUM |
363 DEV_TX_OFFLOAD_TCP_TSO;
366 dev_info->default_rxconf = (struct rte_eth_rxconf) {
372 .rx_free_thresh = 32,
376 dev_info->default_txconf = (struct rte_eth_txconf) {
382 .tx_free_thresh = 32,
384 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
385 ETH_TXQ_FLAGS_NOOFFLOADS,
387 eth_dev->data->dev_conf.intr_conf.lsc = 1;
392 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
393 * need further investigation.
397 vpool = 64; /* ETH_64_POOLS */
398 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
399 for (i = 0; i < 4; vpool >>= 1, i++) {
400 if (max_vnics > vpool) {
401 for (j = 0; j < 5; vrxq >>= 1, j++) {
402 if (dev_info->max_rx_queues > vrxq) {
408 /* Not enough resources to support VMDq */
412 /* Not enough resources to support VMDq */
416 dev_info->max_vmdq_pools = vpool;
417 dev_info->vmdq_queue_num = vrxq;
419 dev_info->vmdq_pool_base = 0;
420 dev_info->vmdq_queue_base = 0;
423 /* Configure the device based on the configuration provided */
424 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
426 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
428 bp->rx_queues = (void *)eth_dev->data->rx_queues;
429 bp->tx_queues = (void *)eth_dev->data->tx_queues;
431 /* Inherit new configurations */
432 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
433 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
434 bp->rx_cp_nr_rings = bp->rx_nr_rings;
435 bp->tx_cp_nr_rings = bp->tx_nr_rings;
437 if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
439 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
440 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
445 rte_bnxt_atomic_write_link_status(struct rte_eth_dev *eth_dev,
446 struct rte_eth_link *link)
448 struct rte_eth_link *dst = ð_dev->data->dev_link;
449 struct rte_eth_link *src = link;
451 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
452 *(uint64_t *)src) == 0)
458 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
460 struct rte_eth_link *link = ð_dev->data->dev_link;
462 if (link->link_status)
463 RTE_LOG(INFO, PMD, "Port %d Link Up - speed %u Mbps - %s\n",
464 (uint8_t)(eth_dev->data->port_id),
465 (uint32_t)link->link_speed,
466 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
467 ("full-duplex") : ("half-duplex\n"));
469 RTE_LOG(INFO, PMD, "Port %d Link Down\n",
470 (uint8_t)(eth_dev->data->port_id));
473 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
475 bnxt_print_link_info(eth_dev);
479 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
481 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
486 rc = bnxt_init_nic(bp);
490 bnxt_link_update_op(eth_dev, 0);
494 bnxt_shutdown_nic(bp);
495 bnxt_free_tx_mbufs(bp);
496 bnxt_free_rx_mbufs(bp);
500 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
502 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
504 eth_dev->data->dev_link.link_status = 1;
505 bnxt_set_hwrm_link_config(bp, true);
509 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
511 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
513 eth_dev->data->dev_link.link_status = 0;
514 bnxt_set_hwrm_link_config(bp, false);
518 /* Unload the driver, release resources */
519 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
521 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
523 if (bp->eth_dev->data->dev_started) {
524 /* TBD: STOP HW queues DMA */
525 eth_dev->data->dev_link.link_status = 0;
527 bnxt_set_hwrm_link_config(bp, false);
528 bnxt_shutdown_nic(bp);
532 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
534 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
536 if (bp->dev_stopped == 0)
537 bnxt_dev_stop_op(eth_dev);
539 bnxt_free_tx_mbufs(bp);
540 bnxt_free_rx_mbufs(bp);
542 if (eth_dev->data->mac_addrs != NULL) {
543 rte_free(eth_dev->data->mac_addrs);
544 eth_dev->data->mac_addrs = NULL;
546 if (bp->grp_info != NULL) {
547 rte_free(bp->grp_info);
552 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
555 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
556 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
557 struct bnxt_vnic_info *vnic;
558 struct bnxt_filter_info *filter, *temp_filter;
562 * Loop through all VNICs from the specified filter flow pools to
563 * remove the corresponding MAC addr filter
565 for (i = 0; i < MAX_FF_POOLS; i++) {
566 if (!(pool_mask & (1ULL << i)))
569 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
570 filter = STAILQ_FIRST(&vnic->filter);
572 temp_filter = STAILQ_NEXT(filter, next);
573 if (filter->mac_index == index) {
574 STAILQ_REMOVE(&vnic->filter, filter,
575 bnxt_filter_info, next);
576 bnxt_hwrm_clear_filter(bp, filter);
577 filter->mac_index = INVALID_MAC_INDEX;
578 memset(&filter->l2_addr, 0,
581 &bp->free_filter_list,
584 filter = temp_filter;
590 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
591 struct ether_addr *mac_addr,
592 uint32_t index, uint32_t pool)
594 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
595 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
596 struct bnxt_filter_info *filter;
599 RTE_LOG(ERR, PMD, "Cannot add MAC address to a VF interface\n");
604 RTE_LOG(ERR, PMD, "VNIC not found for pool %d!\n", pool);
607 /* Attach requested MAC address to the new l2_filter */
608 STAILQ_FOREACH(filter, &vnic->filter, next) {
609 if (filter->mac_index == index) {
611 "MAC addr already existed for pool %d\n", pool);
615 filter = bnxt_alloc_filter(bp);
617 RTE_LOG(ERR, PMD, "L2 filter alloc failed\n");
620 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
621 filter->mac_index = index;
622 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
623 return bnxt_hwrm_set_filter(bp, vnic, filter);
626 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
629 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
630 struct rte_eth_link new;
631 unsigned int cnt = BNXT_LINK_WAIT_CNT;
633 memset(&new, 0, sizeof(new));
635 /* Retrieve link info from hardware */
636 rc = bnxt_get_hwrm_link_config(bp, &new);
638 new.link_speed = ETH_LINK_SPEED_100M;
639 new.link_duplex = ETH_LINK_FULL_DUPLEX;
641 "Failed to retrieve link rc = 0x%x!", rc);
644 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
646 if (!wait_to_complete)
648 } while (!new.link_status && cnt--);
651 /* Timed out or success */
652 if (new.link_status != eth_dev->data->dev_link.link_status ||
653 new.link_speed != eth_dev->data->dev_link.link_speed) {
654 rte_bnxt_atomic_write_link_status(eth_dev, &new);
655 bnxt_print_link_info(eth_dev);
661 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
663 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
664 struct bnxt_vnic_info *vnic;
666 if (bp->vnic_info == NULL)
669 vnic = &bp->vnic_info[0];
671 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
672 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
675 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
677 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
678 struct bnxt_vnic_info *vnic;
680 if (bp->vnic_info == NULL)
683 vnic = &bp->vnic_info[0];
685 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
686 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
689 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
691 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
692 struct bnxt_vnic_info *vnic;
694 if (bp->vnic_info == NULL)
697 vnic = &bp->vnic_info[0];
699 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
700 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
703 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
705 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
706 struct bnxt_vnic_info *vnic;
708 if (bp->vnic_info == NULL)
711 vnic = &bp->vnic_info[0];
713 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
714 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
717 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
718 struct rte_eth_rss_reta_entry64 *reta_conf,
721 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
722 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
723 struct bnxt_vnic_info *vnic;
726 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
729 if (reta_size != HW_HASH_INDEX_SIZE) {
730 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
731 "(%d) must equal the size supported by the hardware "
732 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
735 /* Update the RSS VNIC(s) */
736 for (i = 0; i < MAX_FF_POOLS; i++) {
737 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
738 memcpy(vnic->rss_table, reta_conf, reta_size);
740 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
746 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
747 struct rte_eth_rss_reta_entry64 *reta_conf,
750 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
751 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
752 struct rte_intr_handle *intr_handle
753 = &bp->pdev->intr_handle;
755 /* Retrieve from the default VNIC */
758 if (!vnic->rss_table)
761 if (reta_size != HW_HASH_INDEX_SIZE) {
762 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
763 "(%d) must equal the size supported by the hardware "
764 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
767 /* EW - need to revisit here copying from u64 to u16 */
768 memcpy(reta_conf, vnic->rss_table, reta_size);
770 if (rte_intr_allow_others(intr_handle)) {
771 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
772 bnxt_dev_lsc_intr_setup(eth_dev);
778 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
779 struct rte_eth_rss_conf *rss_conf)
781 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
782 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
783 struct bnxt_vnic_info *vnic;
784 uint16_t hash_type = 0;
788 * If RSS enablement were different than dev_configure,
789 * then return -EINVAL
791 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
792 if (!rss_conf->rss_hf)
795 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
798 if (rss_conf->rss_hf & ETH_RSS_IPV4)
799 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
800 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
801 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
802 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
803 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
804 if (rss_conf->rss_hf & ETH_RSS_IPV6)
805 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
806 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
807 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
808 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
809 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
811 /* Update the RSS VNIC(s) */
812 for (i = 0; i < MAX_FF_POOLS; i++) {
813 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
814 vnic->hash_type = hash_type;
817 * Use the supplied key if the key length is
818 * acceptable and the rss_key is not NULL
820 if (rss_conf->rss_key &&
821 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
822 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
823 rss_conf->rss_key_len);
825 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
831 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
832 struct rte_eth_rss_conf *rss_conf)
834 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
835 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
839 /* RSS configuration is the same for all VNICs */
840 if (vnic && vnic->rss_hash_key) {
841 if (rss_conf->rss_key) {
842 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
843 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
844 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
847 hash_types = vnic->hash_type;
848 rss_conf->rss_hf = 0;
849 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
850 rss_conf->rss_hf |= ETH_RSS_IPV4;
851 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
853 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
854 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
856 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
858 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
859 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
861 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
863 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
864 rss_conf->rss_hf |= ETH_RSS_IPV6;
865 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
867 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
868 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
870 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
872 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
873 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
875 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
879 "Unknwon RSS config from firmware (%08x), RSS disabled",
884 rss_conf->rss_hf = 0;
889 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
890 struct rte_eth_fc_conf *fc_conf)
892 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
893 struct rte_eth_link link_info;
896 rc = bnxt_get_hwrm_link_config(bp, &link_info);
900 memset(fc_conf, 0, sizeof(*fc_conf));
901 if (bp->link_info.auto_pause)
902 fc_conf->autoneg = 1;
903 switch (bp->link_info.pause) {
905 fc_conf->mode = RTE_FC_NONE;
907 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
908 fc_conf->mode = RTE_FC_TX_PAUSE;
910 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
911 fc_conf->mode = RTE_FC_RX_PAUSE;
913 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
914 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
915 fc_conf->mode = RTE_FC_FULL;
921 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
922 struct rte_eth_fc_conf *fc_conf)
924 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
926 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp)) {
927 RTE_LOG(ERR, PMD, "Flow Control Settings cannot be modified\n");
931 switch (fc_conf->mode) {
933 bp->link_info.auto_pause = 0;
934 bp->link_info.force_pause = 0;
936 case RTE_FC_RX_PAUSE:
937 if (fc_conf->autoneg) {
938 bp->link_info.auto_pause =
939 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
940 bp->link_info.force_pause = 0;
942 bp->link_info.auto_pause = 0;
943 bp->link_info.force_pause =
944 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
947 case RTE_FC_TX_PAUSE:
948 if (fc_conf->autoneg) {
949 bp->link_info.auto_pause =
950 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
951 bp->link_info.force_pause = 0;
953 bp->link_info.auto_pause = 0;
954 bp->link_info.force_pause =
955 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
959 if (fc_conf->autoneg) {
960 bp->link_info.auto_pause =
961 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
962 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
963 bp->link_info.force_pause = 0;
965 bp->link_info.auto_pause = 0;
966 bp->link_info.force_pause =
967 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
968 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
972 return bnxt_set_hwrm_link_config(bp, true);
979 static const struct eth_dev_ops bnxt_dev_ops = {
980 .dev_infos_get = bnxt_dev_info_get_op,
981 .dev_close = bnxt_dev_close_op,
982 .dev_configure = bnxt_dev_configure_op,
983 .dev_start = bnxt_dev_start_op,
984 .dev_stop = bnxt_dev_stop_op,
985 .dev_set_link_up = bnxt_dev_set_link_up_op,
986 .dev_set_link_down = bnxt_dev_set_link_down_op,
987 .stats_get = bnxt_stats_get_op,
988 .stats_reset = bnxt_stats_reset_op,
989 .rx_queue_setup = bnxt_rx_queue_setup_op,
990 .rx_queue_release = bnxt_rx_queue_release_op,
991 .tx_queue_setup = bnxt_tx_queue_setup_op,
992 .tx_queue_release = bnxt_tx_queue_release_op,
993 .reta_update = bnxt_reta_update_op,
994 .reta_query = bnxt_reta_query_op,
995 .rss_hash_update = bnxt_rss_hash_update_op,
996 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
997 .link_update = bnxt_link_update_op,
998 .promiscuous_enable = bnxt_promiscuous_enable_op,
999 .promiscuous_disable = bnxt_promiscuous_disable_op,
1000 .allmulticast_enable = bnxt_allmulticast_enable_op,
1001 .allmulticast_disable = bnxt_allmulticast_disable_op,
1002 .mac_addr_add = bnxt_mac_addr_add_op,
1003 .mac_addr_remove = bnxt_mac_addr_remove_op,
1004 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
1005 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
1008 static bool bnxt_vf_pciid(uint16_t id)
1010 if (id == BROADCOM_DEV_ID_57304_VF ||
1011 id == BROADCOM_DEV_ID_57406_VF ||
1012 id == BROADCOM_DEV_ID_5731X_VF ||
1013 id == BROADCOM_DEV_ID_5741X_VF)
1018 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
1020 struct bnxt *bp = eth_dev->data->dev_private;
1021 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1024 /* enable device (incl. PCI PM wakeup), and bus-mastering */
1025 if (!pci_dev->mem_resource[0].addr) {
1027 "Cannot find PCI device base address, aborting\n");
1029 goto init_err_disable;
1032 bp->eth_dev = eth_dev;
1035 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
1037 RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n");
1039 goto init_err_release;
1052 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
1054 #define ALLOW_FUNC(x) \
1056 typeof(x) arg = (x); \
1057 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
1058 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
1061 bnxt_dev_init(struct rte_eth_dev *eth_dev)
1063 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1064 static int version_printed;
1068 if (version_printed++ == 0)
1069 RTE_LOG(INFO, PMD, "%s", bnxt_version);
1071 rte_eth_copy_pci_info(eth_dev, pci_dev);
1072 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1074 bp = eth_dev->data->dev_private;
1075 bp->dev_stopped = 1;
1077 if (bnxt_vf_pciid(pci_dev->id.device_id))
1078 bp->flags |= BNXT_FLAG_VF;
1080 rc = bnxt_init_board(eth_dev);
1083 "Board initialization failed rc: %x\n", rc);
1086 eth_dev->dev_ops = &bnxt_dev_ops;
1087 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
1088 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
1090 rc = bnxt_alloc_hwrm_resources(bp);
1093 "hwrm resource allocation failure rc: %x\n", rc);
1096 rc = bnxt_hwrm_ver_get(bp);
1099 bnxt_hwrm_queue_qportcfg(bp);
1101 bnxt_hwrm_func_qcfg(bp);
1103 /* Get the MAX capabilities for this function */
1104 rc = bnxt_hwrm_func_qcaps(bp);
1106 RTE_LOG(ERR, PMD, "hwrm query capability failure rc: %x\n", rc);
1109 if (bp->max_tx_rings == 0) {
1110 RTE_LOG(ERR, PMD, "No TX rings available!\n");
1114 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
1115 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR, 0);
1116 if (eth_dev->data->mac_addrs == NULL) {
1118 "Failed to alloc %u bytes needed to store MAC addr tbl",
1119 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR);
1123 /* Copy the permanent MAC from the qcap response address now. */
1124 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
1125 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
1126 bp->grp_info = rte_zmalloc("bnxt_grp_info",
1127 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
1128 if (!bp->grp_info) {
1130 "Failed to alloc %zu bytes needed to store group info table\n",
1131 sizeof(*bp->grp_info) * bp->max_ring_grps);
1136 /* Forward all requests if firmware is new enough */
1137 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
1138 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
1139 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
1140 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
1142 RTE_LOG(WARNING, PMD,
1143 "Firmware too old for VF mailbox functionality\n");
1144 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
1148 * The following are used for driver cleanup. If we disallow these,
1149 * VF drivers can't clean up cleanly.
1151 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
1152 ALLOW_FUNC(HWRM_VNIC_FREE);
1153 ALLOW_FUNC(HWRM_RING_FREE);
1154 ALLOW_FUNC(HWRM_RING_GRP_FREE);
1155 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
1156 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
1157 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
1158 rc = bnxt_hwrm_func_driver_register(bp);
1161 "Failed to register driver");
1167 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
1168 pci_dev->mem_resource[0].phys_addr,
1169 pci_dev->mem_resource[0].addr);
1171 rc = bnxt_hwrm_func_reset(bp);
1173 RTE_LOG(ERR, PMD, "hwrm chip reset failure rc: %x\n", rc);
1179 //if (bp->pf.active_vfs) {
1180 // TODO: Deallocate VF resources?
1182 if (bp->pdev->max_vfs) {
1183 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
1185 RTE_LOG(ERR, PMD, "Failed to allocate VFs\n");
1189 rc = bnxt_hwrm_allocate_pf_only(bp);
1192 "Failed to allocate PF resources\n");
1198 rc = bnxt_setup_int(bp);
1202 rc = bnxt_alloc_mem(bp);
1204 goto error_free_int;
1206 rc = bnxt_request_int(bp);
1208 goto error_free_int;
1210 bnxt_enable_int(bp);
1215 bnxt_disable_int(bp);
1216 bnxt_free_def_cp_ring(bp);
1217 bnxt_hwrm_func_buf_unrgtr(bp);
1221 bnxt_dev_uninit(eth_dev);
1227 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
1228 struct bnxt *bp = eth_dev->data->dev_private;
1231 bnxt_disable_int(bp);
1234 if (eth_dev->data->mac_addrs != NULL) {
1235 rte_free(eth_dev->data->mac_addrs);
1236 eth_dev->data->mac_addrs = NULL;
1238 if (bp->grp_info != NULL) {
1239 rte_free(bp->grp_info);
1240 bp->grp_info = NULL;
1242 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
1243 bnxt_free_hwrm_resources(bp);
1244 if (bp->dev_stopped == 0)
1245 bnxt_dev_close_op(eth_dev);
1247 rte_free(bp->pf.vf_info);
1248 eth_dev->dev_ops = NULL;
1249 eth_dev->rx_pkt_burst = NULL;
1250 eth_dev->tx_pkt_burst = NULL;
1255 int bnxt_rcv_msg_from_vf(struct bnxt *bp, uint16_t vf_id, void *msg)
1257 struct rte_pmd_bnxt_mb_event_param cb_param;
1259 cb_param.retval = RTE_PMD_BNXT_MB_EVENT_PROCEED;
1260 cb_param.vf_id = vf_id;
1263 _rte_eth_dev_callback_process(bp->eth_dev, RTE_ETH_EVENT_VF_MBOX,
1266 /* Default to approve */
1267 if (cb_param.retval == RTE_PMD_BNXT_MB_EVENT_PROCEED)
1268 cb_param.retval = RTE_PMD_BNXT_MB_EVENT_NOOP_ACK;
1270 return cb_param.retval == RTE_PMD_BNXT_MB_EVENT_NOOP_ACK ? true : false;
1273 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1274 struct rte_pci_device *pci_dev)
1276 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
1280 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
1282 return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
1285 static struct rte_pci_driver bnxt_rte_pmd = {
1286 .id_table = bnxt_pci_id_map,
1287 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
1288 RTE_PCI_DRV_INTR_LSC,
1289 .probe = bnxt_pci_probe,
1290 .remove = bnxt_pci_remove,
1293 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
1294 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
1295 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");