drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14
  15 #include "bnxt.h"
  16 #include "bnxt_cpr.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29 #include "bnxt_util.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  34 int bnxt_logtype_driver;
  35
  36 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  37
  38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  41 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  42 #define BROADCOM_DEV_ID_57301 0x16c8
  43 #define BROADCOM_DEV_ID_57302 0x16c9
  44 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  45 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  46 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  47 #define BROADCOM_DEV_ID_NS2 0x16cd
  48 #define BROADCOM_DEV_ID_57311 0x16ce
  49 #define BROADCOM_DEV_ID_57312 0x16cf
  50 #define BROADCOM_DEV_ID_57402 0x16d0
  51 #define BROADCOM_DEV_ID_57404 0x16d1
  52 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  53 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  54 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  56 #define BROADCOM_DEV_ID_57412 0x16d6
  57 #define BROADCOM_DEV_ID_57414 0x16d7
  58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  61 #define BROADCOM_DEV_ID_57412_MF 0x16de
  62 #define BROADCOM_DEV_ID_57314 0x16df
  63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  68 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  69 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  71 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  72 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  73 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  74 #define BROADCOM_DEV_ID_58802 0xd802
  75 #define BROADCOM_DEV_ID_58804 0xd804
  76 #define BROADCOM_DEV_ID_58808 0x16f0
  77 #define BROADCOM_DEV_ID_58802_VF 0xd800
  78
  79 static const struct rte_pci_id bnxt_pci_id_map[] = {
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  81                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  83                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 122         { .vendor_id = 0, /* sentinel */ },
 123 };
 124
 125 #define BNXT_ETH_RSS_SUPPORT (  \
 126         ETH_RSS_IPV4 |          \
 127         ETH_RSS_NONFRAG_IPV4_TCP |      \
 128         ETH_RSS_NONFRAG_IPV4_UDP |      \
 129         ETH_RSS_IPV6 |          \
 130         ETH_RSS_NONFRAG_IPV6_TCP |      \
 131         ETH_RSS_NONFRAG_IPV6_UDP)
 132
 133 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 134                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 135                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 136                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 137                                      DEV_TX_OFFLOAD_TCP_TSO | \
 138                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 139                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 140                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 141                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 142                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 143                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 144
 145 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 146                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 147                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 148                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 149                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 150                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 151                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 152                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 153                                      DEV_RX_OFFLOAD_TCP_LRO)
 154
 155 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 156 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 157 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 158 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 159
 160 /***********************/
 161
 162 /*
 163  * High level utility functions
 164  */
 165
 166 static void bnxt_free_mem(struct bnxt *bp)
 167 {
 168         bnxt_free_filter_mem(bp);
 169         bnxt_free_vnic_attributes(bp);
 170         bnxt_free_vnic_mem(bp);
 171
 172         bnxt_free_stats(bp);
 173         bnxt_free_tx_rings(bp);
 174         bnxt_free_rx_rings(bp);
 175 }
 176
 177 static int bnxt_alloc_mem(struct bnxt *bp)
 178 {
 179         int rc;
 180
 181         rc = bnxt_alloc_vnic_mem(bp);
 182         if (rc)
 183                 goto alloc_mem_err;
 184
 185         rc = bnxt_alloc_vnic_attributes(bp);
 186         if (rc)
 187                 goto alloc_mem_err;
 188
 189         rc = bnxt_alloc_filter_mem(bp);
 190         if (rc)
 191                 goto alloc_mem_err;
 192
 193         return 0;
 194
 195 alloc_mem_err:
 196         bnxt_free_mem(bp);
 197         return rc;
 198 }
 199
 200 static int bnxt_init_chip(struct bnxt *bp)
 201 {
 202         struct bnxt_rx_queue *rxq;
 203         struct rte_eth_link new;
 204         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 205         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 206         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 207         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 208         uint32_t intr_vector = 0;
 209         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 210         uint32_t vec = BNXT_MISC_VEC_ID;
 211         unsigned int i, j;
 212         int rc;
 213
 214         /* disable uio/vfio intr/eventfd mapping */
 215         rte_intr_disable(intr_handle);
 216
 217         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 218                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 219                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 220                 bp->flags |= BNXT_FLAG_JUMBO;
 221         } else {
 222                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 223                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 224                 bp->flags &= ~BNXT_FLAG_JUMBO;
 225         }
 226
 227         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 228         if (rc) {
 229                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 230                 goto err_out;
 231         }
 232
 233         rc = bnxt_alloc_hwrm_rings(bp);
 234         if (rc) {
 235                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 236                 goto err_out;
 237         }
 238
 239         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 240         if (rc) {
 241                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 242                 goto err_out;
 243         }
 244
 245         rc = bnxt_mq_rx_configure(bp);
 246         if (rc) {
 247                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 248                 goto err_out;
 249         }
 250
 251         /* VNIC configuration */
 252         for (i = 0; i < bp->nr_vnics; i++) {
 253                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 254                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 255                 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
 256
 257                 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
 258                 if (!vnic->fw_grp_ids) {
 259                         PMD_DRV_LOG(ERR,
 260                                     "Failed to alloc %d bytes for group ids\n",
 261                                     size);
 262                         rc = -ENOMEM;
 263                         goto err_out;
 264                 }
 265                 memset(vnic->fw_grp_ids, -1, size);
 266
 267                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 268                             i, vnic, vnic->fw_grp_ids);
 269
 270                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 271                 if (rc) {
 272                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 273                                 i, rc);
 274                         goto err_out;
 275                 }
 276
 277                 /* Alloc RSS context only if RSS mode is enabled */
 278                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 279                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
 280                         if (rc) {
 281                                 PMD_DRV_LOG(ERR,
 282                                         "HWRM vnic %d ctx alloc failure rc: %x\n",
 283                                         i, rc);
 284                                 goto err_out;
 285                         }
 286                 }
 287
 288                 /*
 289                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 290                  * setting is not available at this time, it will not be
 291                  * configured correctly in the CFA.
 292                  */
 293                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 294                         vnic->vlan_strip = true;
 295                 else
 296                         vnic->vlan_strip = false;
 297
 298                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 299                 if (rc) {
 300                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 301                                 i, rc);
 302                         goto err_out;
 303                 }
 304
 305                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 306                 if (rc) {
 307                         PMD_DRV_LOG(ERR,
 308                                 "HWRM vnic %d filter failure rc: %x\n",
 309                                 i, rc);
 310                         goto err_out;
 311                 }
 312
 313                 for (j = 0; j < bp->rx_nr_rings; j++) {
 314                         rxq = bp->eth_dev->data->rx_queues[j];
 315
 316                         PMD_DRV_LOG(DEBUG,
 317                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 318                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 319
 320                         if (rxq->rx_deferred_start)
 321                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 322                 }
 323
 324                 rc = bnxt_vnic_rss_configure(bp, vnic);
 325                 if (rc) {
 326                         PMD_DRV_LOG(ERR,
 327                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 328                         goto err_out;
 329                 }
 330
 331                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 332
 333                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 334                     DEV_RX_OFFLOAD_TCP_LRO)
 335                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 336                 else
 337                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 338         }
 339         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 340         if (rc) {
 341                 PMD_DRV_LOG(ERR,
 342                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 343                 goto err_out;
 344         }
 345
 346         /* check and configure queue intr-vector mapping */
 347         if ((rte_intr_cap_multiple(intr_handle) ||
 348              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 349             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 350                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 351                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 352                 if (intr_vector > bp->rx_cp_nr_rings) {
 353                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 354                                         bp->rx_cp_nr_rings);
 355                         return -ENOTSUP;
 356                 }
 357                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 358                         return -1;
 359         }
 360
 361         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 362                 intr_handle->intr_vec =
 363                         rte_zmalloc("intr_vec",
 364                                     bp->eth_dev->data->nb_rx_queues *
 365                                     sizeof(int), 0);
 366                 if (intr_handle->intr_vec == NULL) {
 367                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 368                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 369                         return -ENOMEM;
 370                 }
 371                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 372                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 373                          intr_handle->intr_vec, intr_handle->nb_efd,
 374                         intr_handle->max_intr);
 375         }
 376
 377         for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 378              queue_id++) {
 379                 intr_handle->intr_vec[queue_id] = vec;
 380                 if (vec < base + intr_handle->nb_efd - 1)
 381                         vec++;
 382         }
 383
 384         /* enable uio/vfio intr/eventfd mapping */
 385         rte_intr_enable(intr_handle);
 386
 387         rc = bnxt_get_hwrm_link_config(bp, &new);
 388         if (rc) {
 389                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 390                 goto err_out;
 391         }
 392
 393         if (!bp->link_info.link_up) {
 394                 rc = bnxt_set_hwrm_link_config(bp, true);
 395                 if (rc) {
 396                         PMD_DRV_LOG(ERR,
 397                                 "HWRM link config failure rc: %x\n", rc);
 398                         goto err_out;
 399                 }
 400         }
 401         bnxt_print_link_info(bp->eth_dev);
 402
 403         return 0;
 404
 405 err_out:
 406         bnxt_free_all_hwrm_resources(bp);
 407
 408         /* Some of the error status returned by FW may not be from errno.h */
 409         if (rc > 0)
 410                 rc = -EIO;
 411
 412         return rc;
 413 }
 414
 415 static int bnxt_shutdown_nic(struct bnxt *bp)
 416 {
 417         bnxt_free_all_hwrm_resources(bp);
 418         bnxt_free_all_filters(bp);
 419         bnxt_free_all_vnics(bp);
 420         return 0;
 421 }
 422
 423 static int bnxt_init_nic(struct bnxt *bp)
 424 {
 425         int rc;
 426
 427         rc = bnxt_init_ring_grps(bp);
 428         if (rc)
 429                 return rc;
 430
 431         bnxt_init_vnics(bp);
 432         bnxt_init_filters(bp);
 433
 434         return 0;
 435 }
 436
 437 /*
 438  * Device configuration and status function
 439  */
 440
 441 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 442                                   struct rte_eth_dev_info *dev_info)
 443 {
 444         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 445         uint16_t max_vnics, i, j, vpool, vrxq;
 446         unsigned int max_rx_rings;
 447
 448         /* MAC Specifics */
 449         dev_info->max_mac_addrs = bp->max_l2_ctx;
 450         dev_info->max_hash_mac_addrs = 0;
 451
 452         /* PF/VF specifics */
 453         if (BNXT_PF(bp))
 454                 dev_info->max_vfs = bp->pdev->max_vfs;
 455         max_rx_rings = RTE_MIN(bp->max_vnics, bp->max_stat_ctx);
 456         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 457         dev_info->max_rx_queues = max_rx_rings;
 458         dev_info->max_tx_queues = max_rx_rings;
 459         dev_info->reta_size = HW_HASH_INDEX_SIZE;
 460         dev_info->hash_key_size = 40;
 461         max_vnics = bp->max_vnics;
 462
 463         /* Fast path specifics */
 464         dev_info->min_rx_bufsize = 1;
 465         dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
 466                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
 467
 468         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 469         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 470                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 471         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 472         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 473
 474         /* *INDENT-OFF* */
 475         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 476                 .rx_thresh = {
 477                         .pthresh = 8,
 478                         .hthresh = 8,
 479                         .wthresh = 0,
 480                 },
 481                 .rx_free_thresh = 32,
 482                 /* If no descriptors available, pkts are dropped by default */
 483                 .rx_drop_en = 1,
 484         };
 485
 486         dev_info->default_txconf = (struct rte_eth_txconf) {
 487                 .tx_thresh = {
 488                         .pthresh = 32,
 489                         .hthresh = 0,
 490                         .wthresh = 0,
 491                 },
 492                 .tx_free_thresh = 32,
 493                 .tx_rs_thresh = 32,
 494         };
 495         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 496
 497         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 498         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 499         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 500         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 501         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 502
 503         /* *INDENT-ON* */
 504
 505         /*
 506          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 507          *       need further investigation.
 508          */
 509
 510         /* VMDq resources */
 511         vpool = 64; /* ETH_64_POOLS */
 512         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 513         for (i = 0; i < 4; vpool >>= 1, i++) {
 514                 if (max_vnics > vpool) {
 515                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 516                                 if (dev_info->max_rx_queues > vrxq) {
 517                                         if (vpool > vrxq)
 518                                                 vpool = vrxq;
 519                                         goto found;
 520                                 }
 521                         }
 522                         /* Not enough resources to support VMDq */
 523                         break;
 524                 }
 525         }
 526         /* Not enough resources to support VMDq */
 527         vpool = 0;
 528         vrxq = 0;
 529 found:
 530         dev_info->max_vmdq_pools = vpool;
 531         dev_info->vmdq_queue_num = vrxq;
 532
 533         dev_info->vmdq_pool_base = 0;
 534         dev_info->vmdq_queue_base = 0;
 535 }
 536
 537 /* Configure the device based on the configuration provided */
 538 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 539 {
 540         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 541         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 542         int rc;
 543
 544         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 545         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 546         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 547         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 548
 549         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 550                 rc = bnxt_hwrm_check_vf_rings(bp);
 551                 if (rc) {
 552                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 553                         return -ENOSPC;
 554                 }
 555
 556                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 557                 if (rc) {
 558                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 559                         return -ENOSPC;
 560                 }
 561         } else {
 562                 /* legacy driver needs to get updated values */
 563                 rc = bnxt_hwrm_func_qcaps(bp);
 564                 if (rc) {
 565                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 566                         return rc;
 567                 }
 568         }
 569
 570         /* Inherit new configurations */
 571         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 572             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 573             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 574             bp->max_cp_rings ||
 575             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 576             bp->max_stat_ctx ||
 577             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps ||
 578             (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 579              bp->max_vnics < eth_dev->data->nb_rx_queues)) {
 580                 PMD_DRV_LOG(ERR,
 581                         "Insufficient resources to support requested config\n");
 582                 PMD_DRV_LOG(ERR,
 583                         "Num Queues Requested: Tx %d, Rx %d\n",
 584                         eth_dev->data->nb_tx_queues,
 585                         eth_dev->data->nb_rx_queues);
 586                 PMD_DRV_LOG(ERR,
 587                         "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 588                         bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 589                         bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 590                 return -ENOSPC;
 591         }
 592
 593         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 594         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 595
 596         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 597                 eth_dev->data->mtu =
 598                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 599                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 600                         BNXT_NUM_VLANS;
 601                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 602         }
 603         return 0;
 604 }
 605
 606 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 607 {
 608         struct rte_eth_link *link = &eth_dev->data->dev_link;
 609
 610         if (link->link_status)
 611                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 612                         eth_dev->data->port_id,
 613                         (uint32_t)link->link_speed,
 614                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 615                         ("full-duplex") : ("half-duplex\n"));
 616         else
 617                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 618                         eth_dev->data->port_id);
 619 }
 620
 621 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
 622 {
 623         bnxt_print_link_info(eth_dev);
 624         return 0;
 625 }
 626
 627 /*
 628  * Determine whether the current configuration requires support for scattered
 629  * receive; return 1 if scattered receive is required and 0 if not.
 630  */
 631 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 632 {
 633         uint16_t buf_size;
 634         int i;
 635
 636         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 637                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 638
 639                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 640                                       RTE_PKTMBUF_HEADROOM);
 641                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 642                         return 1;
 643         }
 644         return 0;
 645 }
 646
 647 static eth_rx_burst_t
 648 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 649 {
 650 #ifdef RTE_ARCH_X86
 651         /*
 652          * Vector mode receive can be enabled only if scatter rx is not
 653          * in use and rx offloads are limited to VLAN stripping and
 654          * CRC stripping.
 655          */
 656         if (!eth_dev->data->scattered_rx &&
 657             !(eth_dev->data->dev_conf.rxmode.offloads &
 658               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 659                 DEV_RX_OFFLOAD_KEEP_CRC |
 660                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 661                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 662                 DEV_RX_OFFLOAD_UDP_CKSUM |
 663                 DEV_RX_OFFLOAD_TCP_CKSUM |
 664                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 665                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 666                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 667                             eth_dev->data->port_id);
 668                 return bnxt_recv_pkts_vec;
 669         }
 670         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 671                     eth_dev->data->port_id);
 672         PMD_DRV_LOG(INFO,
 673                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 674                     eth_dev->data->port_id,
 675                     eth_dev->data->scattered_rx,
 676                     eth_dev->data->dev_conf.rxmode.offloads);
 677 #endif
 678         return bnxt_recv_pkts;
 679 }
 680
 681 static eth_tx_burst_t
 682 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 683 {
 684 #ifdef RTE_ARCH_X86
 685         /*
 686          * Vector mode receive can be enabled only if scatter tx is not
 687          * in use and tx offloads other than VLAN insertion are not
 688          * in use.
 689          */
 690         if (!eth_dev->data->scattered_rx &&
 691             !(eth_dev->data->dev_conf.txmode.offloads &
 692               ~DEV_TX_OFFLOAD_VLAN_INSERT)) {
 693                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 694                             eth_dev->data->port_id);
 695                 return bnxt_xmit_pkts_vec;
 696         }
 697         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 698                     eth_dev->data->port_id);
 699         PMD_DRV_LOG(INFO,
 700                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 701                     eth_dev->data->port_id,
 702                     eth_dev->data->scattered_rx,
 703                     eth_dev->data->dev_conf.txmode.offloads);
 704 #endif
 705         return bnxt_xmit_pkts;
 706 }
 707
 708 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 709 {
 710         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 711         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 712         int vlan_mask = 0;
 713         int rc;
 714
 715         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 716                 PMD_DRV_LOG(ERR,
 717                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 718                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 719         }
 720         bp->dev_stopped = 0;
 721
 722         rc = bnxt_init_chip(bp);
 723         if (rc)
 724                 goto error;
 725
 726         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 727
 728         bnxt_link_update_op(eth_dev, 1);
 729
 730         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 731                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 732         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 733                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 734         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 735         if (rc)
 736                 goto error;
 737
 738         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 739         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 740         bp->flags |= BNXT_FLAG_INIT_DONE;
 741         return 0;
 742
 743 error:
 744         bnxt_shutdown_nic(bp);
 745         bnxt_free_tx_mbufs(bp);
 746         bnxt_free_rx_mbufs(bp);
 747         return rc;
 748 }
 749
 750 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 751 {
 752         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 753         int rc = 0;
 754
 755         if (!bp->link_info.link_up)
 756                 rc = bnxt_set_hwrm_link_config(bp, true);
 757         if (!rc)
 758                 eth_dev->data->dev_link.link_status = 1;
 759
 760         bnxt_print_link_info(eth_dev);
 761         return 0;
 762 }
 763
 764 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 765 {
 766         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 767
 768         eth_dev->data->dev_link.link_status = 0;
 769         bnxt_set_hwrm_link_config(bp, false);
 770         bp->link_info.link_up = 0;
 771
 772         return 0;
 773 }
 774
 775 /* Unload the driver, release resources */
 776 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 777 {
 778         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 779
 780         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 781         if (bp->eth_dev->data->dev_started) {
 782                 /* TBD: STOP HW queues DMA */
 783                 eth_dev->data->dev_link.link_status = 0;
 784         }
 785         bnxt_set_hwrm_link_config(bp, false);
 786         bnxt_hwrm_port_clr_stats(bp);
 787         bnxt_free_tx_mbufs(bp);
 788         bnxt_free_rx_mbufs(bp);
 789         bnxt_shutdown_nic(bp);
 790         bp->dev_stopped = 1;
 791 }
 792
 793 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 794 {
 795         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 796
 797         if (bp->dev_stopped == 0)
 798                 bnxt_dev_stop_op(eth_dev);
 799
 800         if (eth_dev->data->mac_addrs != NULL) {
 801                 rte_free(eth_dev->data->mac_addrs);
 802                 eth_dev->data->mac_addrs = NULL;
 803         }
 804         if (bp->grp_info != NULL) {
 805                 rte_free(bp->grp_info);
 806                 bp->grp_info = NULL;
 807         }
 808
 809         bnxt_dev_uninit(eth_dev);
 810 }
 811
 812 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 813                                     uint32_t index)
 814 {
 815         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 816         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 817         struct bnxt_vnic_info *vnic;
 818         struct bnxt_filter_info *filter, *temp_filter;
 819         uint32_t i;
 820
 821         /*
 822          * Loop through all VNICs from the specified filter flow pools to
 823          * remove the corresponding MAC addr filter
 824          */
 825         for (i = 0; i < bp->nr_vnics; i++) {
 826                 if (!(pool_mask & (1ULL << i)))
 827                         continue;
 828
 829                 vnic = &bp->vnic_info[i];
 830                 filter = STAILQ_FIRST(&vnic->filter);
 831                 while (filter) {
 832                         temp_filter = STAILQ_NEXT(filter, next);
 833                         if (filter->mac_index == index) {
 834                                 STAILQ_REMOVE(&vnic->filter, filter,
 835                                                 bnxt_filter_info, next);
 836                                 bnxt_hwrm_clear_l2_filter(bp, filter);
 837                                 filter->mac_index = INVALID_MAC_INDEX;
 838                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
 839                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
 840                                                    filter, next);
 841                         }
 842                         filter = temp_filter;
 843                 }
 844         }
 845 }
 846
 847 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 848                                 struct rte_ether_addr *mac_addr,
 849                                 uint32_t index, uint32_t pool)
 850 {
 851         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 852         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
 853         struct bnxt_filter_info *filter;
 854
 855         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
 856                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
 857                 return -ENOTSUP;
 858         }
 859
 860         if (!vnic) {
 861                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
 862                 return -EINVAL;
 863         }
 864         /* Attach requested MAC address to the new l2_filter */
 865         STAILQ_FOREACH(filter, &vnic->filter, next) {
 866                 if (filter->mac_index == index) {
 867                         PMD_DRV_LOG(ERR,
 868                                 "MAC addr already existed for pool %d\n", pool);
 869                         return 0;
 870                 }
 871         }
 872         filter = bnxt_alloc_filter(bp);
 873         if (!filter) {
 874                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
 875                 return -ENODEV;
 876         }
 877         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
 878         filter->mac_index = index;
 879         memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
 880         return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
 881 }
 882
 883 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
 884 {
 885         int rc = 0;
 886         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 887         struct rte_eth_link new;
 888         unsigned int cnt = BNXT_LINK_WAIT_CNT;
 889
 890         memset(&new, 0, sizeof(new));
 891         do {
 892                 /* Retrieve link info from hardware */
 893                 rc = bnxt_get_hwrm_link_config(bp, &new);
 894                 if (rc) {
 895                         new.link_speed = ETH_LINK_SPEED_100M;
 896                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 897                         PMD_DRV_LOG(ERR,
 898                                 "Failed to retrieve link rc = 0x%x!\n", rc);
 899                         goto out;
 900                 }
 901                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
 902
 903                 if (!wait_to_complete)
 904                         break;
 905         } while (!new.link_status && cnt--);
 906
 907 out:
 908         /* Timed out or success */
 909         if (new.link_status != eth_dev->data->dev_link.link_status ||
 910         new.link_speed != eth_dev->data->dev_link.link_speed) {
 911                 memcpy(&eth_dev->data->dev_link, &new,
 912                         sizeof(struct rte_eth_link));
 913
 914                 _rte_eth_dev_callback_process(eth_dev,
 915                                               RTE_ETH_EVENT_INTR_LSC,
 916                                               NULL);
 917
 918                 bnxt_print_link_info(eth_dev);
 919         }
 920
 921         return rc;
 922 }
 923
 924 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
 925 {
 926         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 927         struct bnxt_vnic_info *vnic;
 928
 929         if (bp->vnic_info == NULL)
 930                 return;
 931
 932         vnic = &bp->vnic_info[0];
 933
 934         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
 935         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 936 }
 937
 938 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
 939 {
 940         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 941         struct bnxt_vnic_info *vnic;
 942
 943         if (bp->vnic_info == NULL)
 944                 return;
 945
 946         vnic = &bp->vnic_info[0];
 947
 948         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
 949         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 950 }
 951
 952 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
 953 {
 954         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 955         struct bnxt_vnic_info *vnic;
 956
 957         if (bp->vnic_info == NULL)
 958                 return;
 959
 960         vnic = &bp->vnic_info[0];
 961
 962         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
 963         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 964 }
 965
 966 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
 967 {
 968         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 969         struct bnxt_vnic_info *vnic;
 970
 971         if (bp->vnic_info == NULL)
 972                 return;
 973
 974         vnic = &bp->vnic_info[0];
 975
 976         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
 977         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
 978 }
 979
 980 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
 981                             struct rte_eth_rss_reta_entry64 *reta_conf,
 982                             uint16_t reta_size)
 983 {
 984         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 985         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 986         struct bnxt_vnic_info *vnic;
 987         int i;
 988
 989         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
 990                 return -EINVAL;
 991
 992         if (reta_size != HW_HASH_INDEX_SIZE) {
 993                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
 994                         "(%d) must equal the size supported by the hardware "
 995                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 996                 return -EINVAL;
 997         }
 998         /* Update the RSS VNIC(s) */
 999         for (i = 0; i < bp->max_vnics; i++) {
1000                 vnic = &bp->vnic_info[i];
1001                 memcpy(vnic->rss_table, reta_conf, reta_size);
1002                 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1003         }
1004         return 0;
1005 }
1006
1007 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1008                               struct rte_eth_rss_reta_entry64 *reta_conf,
1009                               uint16_t reta_size)
1010 {
1011         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1012         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1013         struct rte_intr_handle *intr_handle
1014                 = &bp->pdev->intr_handle;
1015
1016         /* Retrieve from the default VNIC */
1017         if (!vnic)
1018                 return -EINVAL;
1019         if (!vnic->rss_table)
1020                 return -EINVAL;
1021
1022         if (reta_size != HW_HASH_INDEX_SIZE) {
1023                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1024                         "(%d) must equal the size supported by the hardware "
1025                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
1026                 return -EINVAL;
1027         }
1028         /* EW - need to revisit here copying from uint64_t to uint16_t */
1029         memcpy(reta_conf, vnic->rss_table, reta_size);
1030
1031         if (rte_intr_allow_others(intr_handle)) {
1032                 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
1033                         bnxt_dev_lsc_intr_setup(eth_dev);
1034         }
1035
1036         return 0;
1037 }
1038
1039 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1040                                    struct rte_eth_rss_conf *rss_conf)
1041 {
1042         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1043         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1044         struct bnxt_vnic_info *vnic;
1045         uint16_t hash_type = 0;
1046         unsigned int i;
1047
1048         /*
1049          * If RSS enablement were different than dev_configure,
1050          * then return -EINVAL
1051          */
1052         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1053                 if (!rss_conf->rss_hf)
1054                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1055         } else {
1056                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1057                         return -EINVAL;
1058         }
1059
1060         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1061         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1062
1063         if (rss_conf->rss_hf & ETH_RSS_IPV4)
1064                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1065         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1066                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1067         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1068                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1069         if (rss_conf->rss_hf & ETH_RSS_IPV6)
1070                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1071         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1072                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1073         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1074                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1075
1076         /* Update the RSS VNIC(s) */
1077         for (i = 0; i < bp->nr_vnics; i++) {
1078                 vnic = &bp->vnic_info[i];
1079                 vnic->hash_type = hash_type;
1080
1081                 /*
1082                  * Use the supplied key if the key length is
1083                  * acceptable and the rss_key is not NULL
1084                  */
1085                 if (rss_conf->rss_key &&
1086                     rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1087                         memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1088                                rss_conf->rss_key_len);
1089
1090                 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1091         }
1092         return 0;
1093 }
1094
1095 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1096                                      struct rte_eth_rss_conf *rss_conf)
1097 {
1098         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1099         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1100         int len;
1101         uint32_t hash_types;
1102
1103         /* RSS configuration is the same for all VNICs */
1104         if (vnic && vnic->rss_hash_key) {
1105                 if (rss_conf->rss_key) {
1106                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1107                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1108                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1109                 }
1110
1111                 hash_types = vnic->hash_type;
1112                 rss_conf->rss_hf = 0;
1113                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1114                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1115                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1116                 }
1117                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1118                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1119                         hash_types &=
1120                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1121                 }
1122                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1123                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1124                         hash_types &=
1125                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1126                 }
1127                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1128                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1129                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1130                 }
1131                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1132                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1133                         hash_types &=
1134                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1135                 }
1136                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1137                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1138                         hash_types &=
1139                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1140                 }
1141                 if (hash_types) {
1142                         PMD_DRV_LOG(ERR,
1143                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1144                                 vnic->hash_type);
1145                         return -ENOTSUP;
1146                 }
1147         } else {
1148                 rss_conf->rss_hf = 0;
1149         }
1150         return 0;
1151 }
1152
1153 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1154                                struct rte_eth_fc_conf *fc_conf)
1155 {
1156         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1157         struct rte_eth_link link_info;
1158         int rc;
1159
1160         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1161         if (rc)
1162                 return rc;
1163
1164         memset(fc_conf, 0, sizeof(*fc_conf));
1165         if (bp->link_info.auto_pause)
1166                 fc_conf->autoneg = 1;
1167         switch (bp->link_info.pause) {
1168         case 0:
1169                 fc_conf->mode = RTE_FC_NONE;
1170                 break;
1171         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1172                 fc_conf->mode = RTE_FC_TX_PAUSE;
1173                 break;
1174         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1175                 fc_conf->mode = RTE_FC_RX_PAUSE;
1176                 break;
1177         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1178                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1179                 fc_conf->mode = RTE_FC_FULL;
1180                 break;
1181         }
1182         return 0;
1183 }
1184
1185 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1186                                struct rte_eth_fc_conf *fc_conf)
1187 {
1188         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1189
1190         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1191                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1192                 return -ENOTSUP;
1193         }
1194
1195         switch (fc_conf->mode) {
1196         case RTE_FC_NONE:
1197                 bp->link_info.auto_pause = 0;
1198                 bp->link_info.force_pause = 0;
1199                 break;
1200         case RTE_FC_RX_PAUSE:
1201                 if (fc_conf->autoneg) {
1202                         bp->link_info.auto_pause =
1203                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1204                         bp->link_info.force_pause = 0;
1205                 } else {
1206                         bp->link_info.auto_pause = 0;
1207                         bp->link_info.force_pause =
1208                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1209                 }
1210                 break;
1211         case RTE_FC_TX_PAUSE:
1212                 if (fc_conf->autoneg) {
1213                         bp->link_info.auto_pause =
1214                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1215                         bp->link_info.force_pause = 0;
1216                 } else {
1217                         bp->link_info.auto_pause = 0;
1218                         bp->link_info.force_pause =
1219                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1220                 }
1221                 break;
1222         case RTE_FC_FULL:
1223                 if (fc_conf->autoneg) {
1224                         bp->link_info.auto_pause =
1225                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1226                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1227                         bp->link_info.force_pause = 0;
1228                 } else {
1229                         bp->link_info.auto_pause = 0;
1230                         bp->link_info.force_pause =
1231                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1232                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1233                 }
1234                 break;
1235         }
1236         return bnxt_set_hwrm_link_config(bp, true);
1237 }
1238
1239 /* Add UDP tunneling port */
1240 static int
1241 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1242                          struct rte_eth_udp_tunnel *udp_tunnel)
1243 {
1244         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1245         uint16_t tunnel_type = 0;
1246         int rc = 0;
1247
1248         switch (udp_tunnel->prot_type) {
1249         case RTE_TUNNEL_TYPE_VXLAN:
1250                 if (bp->vxlan_port_cnt) {
1251                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1252                                 udp_tunnel->udp_port);
1253                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1254                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1255                                 return -ENOSPC;
1256                         }
1257                         bp->vxlan_port_cnt++;
1258                         return 0;
1259                 }
1260                 tunnel_type =
1261                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1262                 bp->vxlan_port_cnt++;
1263                 break;
1264         case RTE_TUNNEL_TYPE_GENEVE:
1265                 if (bp->geneve_port_cnt) {
1266                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1267                                 udp_tunnel->udp_port);
1268                         if (bp->geneve_port != udp_tunnel->udp_port) {
1269                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1270                                 return -ENOSPC;
1271                         }
1272                         bp->geneve_port_cnt++;
1273                         return 0;
1274                 }
1275                 tunnel_type =
1276                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1277                 bp->geneve_port_cnt++;
1278                 break;
1279         default:
1280                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1281                 return -ENOTSUP;
1282         }
1283         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1284                                              tunnel_type);
1285         return rc;
1286 }
1287
1288 static int
1289 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1290                          struct rte_eth_udp_tunnel *udp_tunnel)
1291 {
1292         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1293         uint16_t tunnel_type = 0;
1294         uint16_t port = 0;
1295         int rc = 0;
1296
1297         switch (udp_tunnel->prot_type) {
1298         case RTE_TUNNEL_TYPE_VXLAN:
1299                 if (!bp->vxlan_port_cnt) {
1300                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1301                         return -EINVAL;
1302                 }
1303                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1304                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1305                                 udp_tunnel->udp_port, bp->vxlan_port);
1306                         return -EINVAL;
1307                 }
1308                 if (--bp->vxlan_port_cnt)
1309                         return 0;
1310
1311                 tunnel_type =
1312                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1313                 port = bp->vxlan_fw_dst_port_id;
1314                 break;
1315         case RTE_TUNNEL_TYPE_GENEVE:
1316                 if (!bp->geneve_port_cnt) {
1317                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1318                         return -EINVAL;
1319                 }
1320                 if (bp->geneve_port != udp_tunnel->udp_port) {
1321                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1322                                 udp_tunnel->udp_port, bp->geneve_port);
1323                         return -EINVAL;
1324                 }
1325                 if (--bp->geneve_port_cnt)
1326                         return 0;
1327
1328                 tunnel_type =
1329                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1330                 port = bp->geneve_fw_dst_port_id;
1331                 break;
1332         default:
1333                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1334                 return -ENOTSUP;
1335         }
1336
1337         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1338         if (!rc) {
1339                 if (tunnel_type ==
1340                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1341                         bp->vxlan_port = 0;
1342                 if (tunnel_type ==
1343                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1344                         bp->geneve_port = 0;
1345         }
1346         return rc;
1347 }
1348
1349 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1350 {
1351         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1352         struct bnxt_vnic_info *vnic;
1353         unsigned int i;
1354         int rc = 0;
1355         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1356
1357         /* Cycle through all VNICs */
1358         for (i = 0; i < bp->nr_vnics; i++) {
1359                 /*
1360                  * For each VNIC and each associated filter(s)
1361                  * if VLAN exists && VLAN matches vlan_id
1362                  *      remove the MAC+VLAN filter
1363                  *      add a new MAC only filter
1364                  * else
1365                  *      VLAN filter doesn't exist, just skip and continue
1366                  */
1367                 vnic = &bp->vnic_info[i];
1368                 filter = STAILQ_FIRST(&vnic->filter);
1369                 while (filter) {
1370                         temp_filter = STAILQ_NEXT(filter, next);
1371
1372                         if (filter->enables & chk &&
1373                             filter->l2_ovlan == vlan_id) {
1374                                 /* Must delete the filter */
1375                                 STAILQ_REMOVE(&vnic->filter, filter,
1376                                               bnxt_filter_info, next);
1377                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1378                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1379                                                    filter, next);
1380
1381                                 /*
1382                                  * Need to examine to see if the MAC
1383                                  * filter already existed or not before
1384                                  * allocating a new one
1385                                  */
1386
1387                                 new_filter = bnxt_alloc_filter(bp);
1388                                 if (!new_filter) {
1389                                         PMD_DRV_LOG(ERR,
1390                                                         "MAC/VLAN filter alloc failed\n");
1391                                         rc = -ENOMEM;
1392                                         goto exit;
1393                                 }
1394                                 STAILQ_INSERT_TAIL(&vnic->filter,
1395                                                 new_filter, next);
1396                                 /* Inherit MAC from previous filter */
1397                                 new_filter->mac_index =
1398                                         filter->mac_index;
1399                                 memcpy(new_filter->l2_addr, filter->l2_addr,
1400                                        RTE_ETHER_ADDR_LEN);
1401                                 /* MAC only filter */
1402                                 rc = bnxt_hwrm_set_l2_filter(bp,
1403                                                              vnic->fw_vnic_id,
1404                                                              new_filter);
1405                                 if (rc)
1406                                         goto exit;
1407                                 PMD_DRV_LOG(INFO,
1408                                             "Del Vlan filter for %d\n",
1409                                             vlan_id);
1410                         }
1411                         filter = temp_filter;
1412                 }
1413         }
1414 exit:
1415         return rc;
1416 }
1417
1418 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1419 {
1420         struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1421         struct bnxt_vnic_info *vnic;
1422         unsigned int i;
1423         int rc = 0;
1424         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1425                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1426         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1427
1428         /* Cycle through all VNICs */
1429         for (i = 0; i < bp->nr_vnics; i++) {
1430                 /*
1431                  * For each VNIC and each associated filter(s)
1432                  * if VLAN exists:
1433                  *   if VLAN matches vlan_id
1434                  *      VLAN filter already exists, just skip and continue
1435                  *   else
1436                  *      add a new MAC+VLAN filter
1437                  * else
1438                  *   Remove the old MAC only filter
1439                  *    Add a new MAC+VLAN filter
1440                  */
1441                 vnic = &bp->vnic_info[i];
1442                 filter = STAILQ_FIRST(&vnic->filter);
1443                 while (filter) {
1444                         temp_filter = STAILQ_NEXT(filter, next);
1445
1446                         if (filter->enables & chk) {
1447                                 if (filter->l2_ivlan == vlan_id)
1448                                         goto cont;
1449                         } else {
1450                                 /* Must delete the MAC filter */
1451                                 STAILQ_REMOVE(&vnic->filter, filter,
1452                                                 bnxt_filter_info, next);
1453                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1454                                 filter->l2_ovlan = 0;
1455                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1456                                                    filter, next);
1457                         }
1458                         new_filter = bnxt_alloc_filter(bp);
1459                         if (!new_filter) {
1460                                 PMD_DRV_LOG(ERR,
1461                                                 "MAC/VLAN filter alloc failed\n");
1462                                 rc = -ENOMEM;
1463                                 goto exit;
1464                         }
1465                         STAILQ_INSERT_TAIL(&vnic->filter, new_filter, next);
1466                         /* Inherit MAC from the previous filter */
1467                         new_filter->mac_index = filter->mac_index;
1468                         memcpy(new_filter->l2_addr, filter->l2_addr,
1469                                RTE_ETHER_ADDR_LEN);
1470                         /* MAC + VLAN ID filter */
1471                         new_filter->l2_ivlan = vlan_id;
1472                         new_filter->l2_ivlan_mask = 0xF000;
1473                         new_filter->enables |= en;
1474                         rc = bnxt_hwrm_set_l2_filter(bp,
1475                                         vnic->fw_vnic_id,
1476                                         new_filter);
1477                         if (rc)
1478                                 goto exit;
1479                         PMD_DRV_LOG(INFO,
1480                                     "Added Vlan filter for %d\n", vlan_id);
1481 cont:
1482                         filter = temp_filter;
1483                 }
1484         }
1485 exit:
1486         return rc;
1487 }
1488
1489 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1490                 uint16_t vlan_id, int on)
1491 {
1492         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1493
1494         /* These operations apply to ALL existing MAC/VLAN filters */
1495         if (on)
1496                 return bnxt_add_vlan_filter(bp, vlan_id);
1497         else
1498                 return bnxt_del_vlan_filter(bp, vlan_id);
1499 }
1500
1501 static int
1502 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1503 {
1504         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1505         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1506         unsigned int i;
1507
1508         if (mask & ETH_VLAN_FILTER_MASK) {
1509                 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1510                         /* Remove any VLAN filters programmed */
1511                         for (i = 0; i < 4095; i++)
1512                                 bnxt_del_vlan_filter(bp, i);
1513                 }
1514                 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1515                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1516         }
1517
1518         if (mask & ETH_VLAN_STRIP_MASK) {
1519                 /* Enable or disable VLAN stripping */
1520                 for (i = 0; i < bp->nr_vnics; i++) {
1521                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1522                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1523                                 vnic->vlan_strip = true;
1524                         else
1525                                 vnic->vlan_strip = false;
1526                         bnxt_hwrm_vnic_cfg(bp, vnic);
1527                 }
1528                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1529                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1530         }
1531
1532         if (mask & ETH_VLAN_EXTEND_MASK)
1533                 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1534
1535         return 0;
1536 }
1537
1538 static int
1539 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1540                         struct rte_ether_addr *addr)
1541 {
1542         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1543         /* Default Filter is tied to VNIC 0 */
1544         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1545         struct bnxt_filter_info *filter;
1546         int rc;
1547
1548         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1549                 return -EPERM;
1550
1551         memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1552
1553         STAILQ_FOREACH(filter, &vnic->filter, next) {
1554                 /* Default Filter is at Index 0 */
1555                 if (filter->mac_index != 0)
1556                         continue;
1557                 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1558                 if (rc)
1559                         return rc;
1560                 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1561                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1562                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1563                 filter->enables |=
1564                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1565                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1566                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1567                 if (rc)
1568                         return rc;
1569                 filter->mac_index = 0;
1570                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1571         }
1572
1573         return 0;
1574 }
1575
1576 static int
1577 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1578                           struct rte_ether_addr *mc_addr_set,
1579                           uint32_t nb_mc_addr)
1580 {
1581         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1582         char *mc_addr_list = (char *)mc_addr_set;
1583         struct bnxt_vnic_info *vnic;
1584         uint32_t off = 0, i = 0;
1585
1586         vnic = &bp->vnic_info[0];
1587
1588         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1589                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1590                 goto allmulti;
1591         }
1592
1593         /* TODO Check for Duplicate mcast addresses */
1594         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1595         for (i = 0; i < nb_mc_addr; i++) {
1596                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1597                         RTE_ETHER_ADDR_LEN);
1598                 off += RTE_ETHER_ADDR_LEN;
1599         }
1600
1601         vnic->mc_addr_cnt = i;
1602
1603 allmulti:
1604         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1605 }
1606
1607 static int
1608 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1609 {
1610         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1611         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1612         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1613         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1614         int ret;
1615
1616         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1617                         fw_major, fw_minor, fw_updt);
1618
1619         ret += 1; /* add the size of '\0' */
1620         if (fw_size < (uint32_t)ret)
1621                 return ret;
1622         else
1623                 return 0;
1624 }
1625
1626 static void
1627 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1628         struct rte_eth_rxq_info *qinfo)
1629 {
1630         struct bnxt_rx_queue *rxq;
1631
1632         rxq = dev->data->rx_queues[queue_id];
1633
1634         qinfo->mp = rxq->mb_pool;
1635         qinfo->scattered_rx = dev->data->scattered_rx;
1636         qinfo->nb_desc = rxq->nb_rx_desc;
1637
1638         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1639         qinfo->conf.rx_drop_en = 0;
1640         qinfo->conf.rx_deferred_start = 0;
1641 }
1642
1643 static void
1644 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1645         struct rte_eth_txq_info *qinfo)
1646 {
1647         struct bnxt_tx_queue *txq;
1648
1649         txq = dev->data->tx_queues[queue_id];
1650
1651         qinfo->nb_desc = txq->nb_tx_desc;
1652
1653         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1654         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1655         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1656
1657         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1658         qinfo->conf.tx_rs_thresh = 0;
1659         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1660 }
1661
1662 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1663 {
1664         struct bnxt *bp = eth_dev->data->dev_private;
1665         struct rte_eth_dev_info dev_info;
1666         uint32_t new_pkt_size;
1667         uint32_t rc = 0;
1668         uint32_t i;
1669
1670         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1671                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1672
1673         bnxt_dev_info_get_op(eth_dev, &dev_info);
1674
1675         if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1676                 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1677                         RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1678                 return -EINVAL;
1679         }
1680
1681 #ifdef RTE_ARCH_X86
1682         /*
1683          * If vector-mode tx/rx is active, disallow any MTU change that would
1684          * require scattered receive support.
1685          */
1686         if (eth_dev->data->dev_started &&
1687             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1688              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1689             (new_pkt_size >
1690              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1691                 PMD_DRV_LOG(ERR,
1692                             "MTU change would require scattered rx support. ");
1693                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
1694                 return -EINVAL;
1695         }
1696 #endif
1697
1698         if (new_mtu > RTE_ETHER_MTU) {
1699                 bp->flags |= BNXT_FLAG_JUMBO;
1700                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1701                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1702         } else {
1703                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1704                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1705                 bp->flags &= ~BNXT_FLAG_JUMBO;
1706         }
1707
1708         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
1709
1710         eth_dev->data->mtu = new_mtu;
1711         PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1712
1713         for (i = 0; i < bp->nr_vnics; i++) {
1714                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1715                 uint16_t size = 0;
1716
1717                 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1718                                         RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1719                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1720                 if (rc)
1721                         break;
1722
1723                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1724                 size -= RTE_PKTMBUF_HEADROOM;
1725
1726                 if (size < new_mtu) {
1727                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1728                         if (rc)
1729                                 return rc;
1730                 }
1731         }
1732
1733         return rc;
1734 }
1735
1736 static int
1737 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1738 {
1739         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1740         uint16_t vlan = bp->vlan;
1741         int rc;
1742
1743         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1744                 PMD_DRV_LOG(ERR,
1745                         "PVID cannot be modified for this function\n");
1746                 return -ENOTSUP;
1747         }
1748         bp->vlan = on ? pvid : 0;
1749
1750         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1751         if (rc)
1752                 bp->vlan = vlan;
1753         return rc;
1754 }
1755
1756 static int
1757 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1758 {
1759         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1760
1761         return bnxt_hwrm_port_led_cfg(bp, true);
1762 }
1763
1764 static int
1765 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1766 {
1767         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1768
1769         return bnxt_hwrm_port_led_cfg(bp, false);
1770 }
1771
1772 static uint32_t
1773 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1774 {
1775         uint32_t desc = 0, raw_cons = 0, cons;
1776         struct bnxt_cp_ring_info *cpr;
1777         struct bnxt_rx_queue *rxq;
1778         struct rx_pkt_cmpl *rxcmp;
1779         uint16_t cmp_type;
1780         uint8_t cmp = 1;
1781         bool valid;
1782
1783         rxq = dev->data->rx_queues[rx_queue_id];
1784         cpr = rxq->cp_ring;
1785         valid = cpr->valid;
1786
1787         while (raw_cons < rxq->nb_rx_desc) {
1788                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1789                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1790
1791                 if (!CMPL_VALID(rxcmp, valid))
1792                         goto nothing_to_do;
1793                 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1794                 cmp_type = CMP_TYPE(rxcmp);
1795                 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1796                         cmp = (rte_le_to_cpu_32(
1797                                         ((struct rx_tpa_end_cmpl *)
1798                                          (rxcmp))->agg_bufs_v1) &
1799                                RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1800                                 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1801                         desc++;
1802                 } else if (cmp_type == 0x11) {
1803                         desc++;
1804                         cmp = (rxcmp->agg_bufs_v1 &
1805                                    RX_PKT_CMPL_AGG_BUFS_MASK) >>
1806                                 RX_PKT_CMPL_AGG_BUFS_SFT;
1807                 } else {
1808                         cmp = 1;
1809                 }
1810 nothing_to_do:
1811                 raw_cons += cmp ? cmp : 2;
1812         }
1813
1814         return desc;
1815 }
1816
1817 static int
1818 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1819 {
1820         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1821         struct bnxt_rx_ring_info *rxr;
1822         struct bnxt_cp_ring_info *cpr;
1823         struct bnxt_sw_rx_bd *rx_buf;
1824         struct rx_pkt_cmpl *rxcmp;
1825         uint32_t cons, cp_cons;
1826
1827         if (!rxq)
1828                 return -EINVAL;
1829
1830         cpr = rxq->cp_ring;
1831         rxr = rxq->rx_ring;
1832
1833         if (offset >= rxq->nb_rx_desc)
1834                 return -EINVAL;
1835
1836         cons = RING_CMP(cpr->cp_ring_struct, offset);
1837         cp_cons = cpr->cp_raw_cons;
1838         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1839
1840         if (cons > cp_cons) {
1841                 if (CMPL_VALID(rxcmp, cpr->valid))
1842                         return RTE_ETH_RX_DESC_DONE;
1843         } else {
1844                 if (CMPL_VALID(rxcmp, !cpr->valid))
1845                         return RTE_ETH_RX_DESC_DONE;
1846         }
1847         rx_buf = &rxr->rx_buf_ring[cons];
1848         if (rx_buf->mbuf == NULL)
1849                 return RTE_ETH_RX_DESC_UNAVAIL;
1850
1851
1852         return RTE_ETH_RX_DESC_AVAIL;
1853 }
1854
1855 static int
1856 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1857 {
1858         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1859         struct bnxt_tx_ring_info *txr;
1860         struct bnxt_cp_ring_info *cpr;
1861         struct bnxt_sw_tx_bd *tx_buf;
1862         struct tx_pkt_cmpl *txcmp;
1863         uint32_t cons, cp_cons;
1864
1865         if (!txq)
1866                 return -EINVAL;
1867
1868         cpr = txq->cp_ring;
1869         txr = txq->tx_ring;
1870
1871         if (offset >= txq->nb_tx_desc)
1872                 return -EINVAL;
1873
1874         cons = RING_CMP(cpr->cp_ring_struct, offset);
1875         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1876         cp_cons = cpr->cp_raw_cons;
1877
1878         if (cons > cp_cons) {
1879                 if (CMPL_VALID(txcmp, cpr->valid))
1880                         return RTE_ETH_TX_DESC_UNAVAIL;
1881         } else {
1882                 if (CMPL_VALID(txcmp, !cpr->valid))
1883                         return RTE_ETH_TX_DESC_UNAVAIL;
1884         }
1885         tx_buf = &txr->tx_buf_ring[cons];
1886         if (tx_buf->mbuf == NULL)
1887                 return RTE_ETH_TX_DESC_DONE;
1888
1889         return RTE_ETH_TX_DESC_FULL;
1890 }
1891
1892 static struct bnxt_filter_info *
1893 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1894                                 struct rte_eth_ethertype_filter *efilter,
1895                                 struct bnxt_vnic_info *vnic0,
1896                                 struct bnxt_vnic_info *vnic,
1897                                 int *ret)
1898 {
1899         struct bnxt_filter_info *mfilter = NULL;
1900         int match = 0;
1901         *ret = 0;
1902
1903         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
1904                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
1905                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
1906                         " ethertype filter.", efilter->ether_type);
1907                 *ret = -EINVAL;
1908                 goto exit;
1909         }
1910         if (efilter->queue >= bp->rx_nr_rings) {
1911                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1912                 *ret = -EINVAL;
1913                 goto exit;
1914         }
1915
1916         vnic0 = &bp->vnic_info[0];
1917         vnic = &bp->vnic_info[efilter->queue];
1918         if (vnic == NULL) {
1919                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1920                 *ret = -EINVAL;
1921                 goto exit;
1922         }
1923
1924         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1925                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1926                         if ((!memcmp(efilter->mac_addr.addr_bytes,
1927                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
1928                              mfilter->flags ==
1929                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1930                              mfilter->ethertype == efilter->ether_type)) {
1931                                 match = 1;
1932                                 break;
1933                         }
1934                 }
1935         } else {
1936                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1937                         if ((!memcmp(efilter->mac_addr.addr_bytes,
1938                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
1939                              mfilter->ethertype == efilter->ether_type &&
1940                              mfilter->flags ==
1941                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
1942                                 match = 1;
1943                                 break;
1944                         }
1945         }
1946
1947         if (match)
1948                 *ret = -EEXIST;
1949
1950 exit:
1951         return mfilter;
1952 }
1953
1954 static int
1955 bnxt_ethertype_filter(struct rte_eth_dev *dev,
1956                         enum rte_filter_op filter_op,
1957                         void *arg)
1958 {
1959         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1960         struct rte_eth_ethertype_filter *efilter =
1961                         (struct rte_eth_ethertype_filter *)arg;
1962         struct bnxt_filter_info *bfilter, *filter1;
1963         struct bnxt_vnic_info *vnic, *vnic0;
1964         int ret;
1965
1966         if (filter_op == RTE_ETH_FILTER_NOP)
1967                 return 0;
1968
1969         if (arg == NULL) {
1970                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
1971                             filter_op);
1972                 return -EINVAL;
1973         }
1974
1975         vnic0 = &bp->vnic_info[0];
1976         vnic = &bp->vnic_info[efilter->queue];
1977
1978         switch (filter_op) {
1979         case RTE_ETH_FILTER_ADD:
1980                 bnxt_match_and_validate_ether_filter(bp, efilter,
1981                                                         vnic0, vnic, &ret);
1982                 if (ret < 0)
1983                         return ret;
1984
1985                 bfilter = bnxt_get_unused_filter(bp);
1986                 if (bfilter == NULL) {
1987                         PMD_DRV_LOG(ERR,
1988                                 "Not enough resources for a new filter.\n");
1989                         return -ENOMEM;
1990                 }
1991                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
1992                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
1993                        RTE_ETHER_ADDR_LEN);
1994                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
1995                        RTE_ETHER_ADDR_LEN);
1996                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
1997                 bfilter->ethertype = efilter->ether_type;
1998                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
1999
2000                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2001                 if (filter1 == NULL) {
2002                         ret = -1;
2003                         goto cleanup;
2004                 }
2005                 bfilter->enables |=
2006                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2007                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2008
2009                 bfilter->dst_id = vnic->fw_vnic_id;
2010
2011                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2012                         bfilter->flags =
2013                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2014                 }
2015
2016                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2017                 if (ret)
2018                         goto cleanup;
2019                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2020                 break;
2021         case RTE_ETH_FILTER_DELETE:
2022                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2023                                                         vnic0, vnic, &ret);
2024                 if (ret == -EEXIST) {
2025                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2026
2027                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2028                                       next);
2029                         bnxt_free_filter(bp, filter1);
2030                 } else if (ret == 0) {
2031                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2032                 }
2033                 break;
2034         default:
2035                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2036                 ret = -EINVAL;
2037                 goto error;
2038         }
2039         return ret;
2040 cleanup:
2041         bnxt_free_filter(bp, bfilter);
2042 error:
2043         return ret;
2044 }
2045
2046 static inline int
2047 parse_ntuple_filter(struct bnxt *bp,
2048                     struct rte_eth_ntuple_filter *nfilter,
2049                     struct bnxt_filter_info *bfilter)
2050 {
2051         uint32_t en = 0;
2052
2053         if (nfilter->queue >= bp->rx_nr_rings) {
2054                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2055                 return -EINVAL;
2056         }
2057
2058         switch (nfilter->dst_port_mask) {
2059         case UINT16_MAX:
2060                 bfilter->dst_port_mask = -1;
2061                 bfilter->dst_port = nfilter->dst_port;
2062                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2063                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2064                 break;
2065         default:
2066                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2067                 return -EINVAL;
2068         }
2069
2070         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2071         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2072
2073         switch (nfilter->proto_mask) {
2074         case UINT8_MAX:
2075                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2076                         bfilter->ip_protocol = 17;
2077                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2078                         bfilter->ip_protocol = 6;
2079                 else
2080                         return -EINVAL;
2081                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2082                 break;
2083         default:
2084                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2085                 return -EINVAL;
2086         }
2087
2088         switch (nfilter->dst_ip_mask) {
2089         case UINT32_MAX:
2090                 bfilter->dst_ipaddr_mask[0] = -1;
2091                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2092                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2093                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2094                 break;
2095         default:
2096                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2097                 return -EINVAL;
2098         }
2099
2100         switch (nfilter->src_ip_mask) {
2101         case UINT32_MAX:
2102                 bfilter->src_ipaddr_mask[0] = -1;
2103                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2104                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2105                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2106                 break;
2107         default:
2108                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2109                 return -EINVAL;
2110         }
2111
2112         switch (nfilter->src_port_mask) {
2113         case UINT16_MAX:
2114                 bfilter->src_port_mask = -1;
2115                 bfilter->src_port = nfilter->src_port;
2116                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2117                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2118                 break;
2119         default:
2120                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2121                 return -EINVAL;
2122         }
2123
2124         //TODO Priority
2125         //nfilter->priority = (uint8_t)filter->priority;
2126
2127         bfilter->enables = en;
2128         return 0;
2129 }
2130
2131 static struct bnxt_filter_info*
2132 bnxt_match_ntuple_filter(struct bnxt *bp,
2133                          struct bnxt_filter_info *bfilter,
2134                          struct bnxt_vnic_info **mvnic)
2135 {
2136         struct bnxt_filter_info *mfilter = NULL;
2137         int i;
2138
2139         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2140                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2141                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2142                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2143                             bfilter->src_ipaddr_mask[0] ==
2144                             mfilter->src_ipaddr_mask[0] &&
2145                             bfilter->src_port == mfilter->src_port &&
2146                             bfilter->src_port_mask == mfilter->src_port_mask &&
2147                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2148                             bfilter->dst_ipaddr_mask[0] ==
2149                             mfilter->dst_ipaddr_mask[0] &&
2150                             bfilter->dst_port == mfilter->dst_port &&
2151                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2152                             bfilter->flags == mfilter->flags &&
2153                             bfilter->enables == mfilter->enables) {
2154                                 if (mvnic)
2155                                         *mvnic = vnic;
2156                                 return mfilter;
2157                         }
2158                 }
2159         }
2160         return NULL;
2161 }
2162
2163 static int
2164 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2165                        struct rte_eth_ntuple_filter *nfilter,
2166                        enum rte_filter_op filter_op)
2167 {
2168         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2169         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2170         int ret;
2171
2172         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2173                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2174                 return -EINVAL;
2175         }
2176
2177         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2178                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2179                 return -EINVAL;
2180         }
2181
2182         bfilter = bnxt_get_unused_filter(bp);
2183         if (bfilter == NULL) {
2184                 PMD_DRV_LOG(ERR,
2185                         "Not enough resources for a new filter.\n");
2186                 return -ENOMEM;
2187         }
2188         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2189         if (ret < 0)
2190                 goto free_filter;
2191
2192         vnic = &bp->vnic_info[nfilter->queue];
2193         vnic0 = &bp->vnic_info[0];
2194         filter1 = STAILQ_FIRST(&vnic0->filter);
2195         if (filter1 == NULL) {
2196                 ret = -1;
2197                 goto free_filter;
2198         }
2199
2200         bfilter->dst_id = vnic->fw_vnic_id;
2201         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2202         bfilter->enables |=
2203                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2204         bfilter->ethertype = 0x800;
2205         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2206
2207         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2208
2209         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2210             bfilter->dst_id == mfilter->dst_id) {
2211                 PMD_DRV_LOG(ERR, "filter exists.\n");
2212                 ret = -EEXIST;
2213                 goto free_filter;
2214         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2215                    bfilter->dst_id != mfilter->dst_id) {
2216                 mfilter->dst_id = vnic->fw_vnic_id;
2217                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2218                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2219                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2220                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2221                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2222                 goto free_filter;
2223         }
2224         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2225                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2226                 ret = -ENOENT;
2227                 goto free_filter;
2228         }
2229
2230         if (filter_op == RTE_ETH_FILTER_ADD) {
2231                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2232                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2233                 if (ret)
2234                         goto free_filter;
2235                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2236         } else {
2237                 if (mfilter == NULL) {
2238                         /* This should not happen. But for Coverity! */
2239                         ret = -ENOENT;
2240                         goto free_filter;
2241                 }
2242                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2243
2244                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2245                 bnxt_free_filter(bp, mfilter);
2246                 mfilter->fw_l2_filter_id = -1;
2247                 bnxt_free_filter(bp, bfilter);
2248                 bfilter->fw_l2_filter_id = -1;
2249         }
2250
2251         return 0;
2252 free_filter:
2253         bfilter->fw_l2_filter_id = -1;
2254         bnxt_free_filter(bp, bfilter);
2255         return ret;
2256 }
2257
2258 static int
2259 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2260                         enum rte_filter_op filter_op,
2261                         void *arg)
2262 {
2263         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2264         int ret;
2265
2266         if (filter_op == RTE_ETH_FILTER_NOP)
2267                 return 0;
2268
2269         if (arg == NULL) {
2270                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2271                             filter_op);
2272                 return -EINVAL;
2273         }
2274
2275         switch (filter_op) {
2276         case RTE_ETH_FILTER_ADD:
2277                 ret = bnxt_cfg_ntuple_filter(bp,
2278                         (struct rte_eth_ntuple_filter *)arg,
2279                         filter_op);
2280                 break;
2281         case RTE_ETH_FILTER_DELETE:
2282                 ret = bnxt_cfg_ntuple_filter(bp,
2283                         (struct rte_eth_ntuple_filter *)arg,
2284                         filter_op);
2285                 break;
2286         default:
2287                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2288                 ret = -EINVAL;
2289                 break;
2290         }
2291         return ret;
2292 }
2293
2294 static int
2295 bnxt_parse_fdir_filter(struct bnxt *bp,
2296                        struct rte_eth_fdir_filter *fdir,
2297                        struct bnxt_filter_info *filter)
2298 {
2299         enum rte_fdir_mode fdir_mode =
2300                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2301         struct bnxt_vnic_info *vnic0, *vnic;
2302         struct bnxt_filter_info *filter1;
2303         uint32_t en = 0;
2304         int i;
2305
2306         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2307                 return -EINVAL;
2308
2309         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2310         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2311
2312         switch (fdir->input.flow_type) {
2313         case RTE_ETH_FLOW_IPV4:
2314         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2315                 /* FALLTHROUGH */
2316                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2317                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2318                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2319                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2320                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2321                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2322                 filter->ip_addr_type =
2323                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2324                 filter->src_ipaddr_mask[0] = 0xffffffff;
2325                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2326                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2327                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2328                 filter->ethertype = 0x800;
2329                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2330                 break;
2331         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2332                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2333                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2334                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2335                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2336                 filter->dst_port_mask = 0xffff;
2337                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2338                 filter->src_port_mask = 0xffff;
2339                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2340                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2341                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2342                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2343                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2344                 filter->ip_protocol = 6;
2345                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2346                 filter->ip_addr_type =
2347                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2348                 filter->src_ipaddr_mask[0] = 0xffffffff;
2349                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2350                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2351                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2352                 filter->ethertype = 0x800;
2353                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2354                 break;
2355         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2356                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2357                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2358                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2359                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2360                 filter->dst_port_mask = 0xffff;
2361                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2362                 filter->src_port_mask = 0xffff;
2363                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2364                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2365                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2366                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2367                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2368                 filter->ip_protocol = 17;
2369                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2370                 filter->ip_addr_type =
2371                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2372                 filter->src_ipaddr_mask[0] = 0xffffffff;
2373                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2374                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2375                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2376                 filter->ethertype = 0x800;
2377                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2378                 break;
2379         case RTE_ETH_FLOW_IPV6:
2380         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2381                 /* FALLTHROUGH */
2382                 filter->ip_addr_type =
2383                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2384                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2385                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2386                 rte_memcpy(filter->src_ipaddr,
2387                            fdir->input.flow.ipv6_flow.src_ip, 16);
2388                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2389                 rte_memcpy(filter->dst_ipaddr,
2390                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2391                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2392                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2393                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2394                 memset(filter->src_ipaddr_mask, 0xff, 16);
2395                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2396                 filter->ethertype = 0x86dd;
2397                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2398                 break;
2399         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2400                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2401                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2402                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2403                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2404                 filter->dst_port_mask = 0xffff;
2405                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2406                 filter->src_port_mask = 0xffff;
2407                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2408                 filter->ip_addr_type =
2409                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2410                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2411                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2412                 rte_memcpy(filter->src_ipaddr,
2413                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2414                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2415                 rte_memcpy(filter->dst_ipaddr,
2416                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2417                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2418                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2419                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2420                 memset(filter->src_ipaddr_mask, 0xff, 16);
2421                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2422                 filter->ethertype = 0x86dd;
2423                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2424                 break;
2425         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2426                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2427                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2428                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2429                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2430                 filter->dst_port_mask = 0xffff;
2431                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2432                 filter->src_port_mask = 0xffff;
2433                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2434                 filter->ip_addr_type =
2435                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2436                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2437                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2438                 rte_memcpy(filter->src_ipaddr,
2439                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2440                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2441                 rte_memcpy(filter->dst_ipaddr,
2442                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2443                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2444                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2445                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2446                 memset(filter->src_ipaddr_mask, 0xff, 16);
2447                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2448                 filter->ethertype = 0x86dd;
2449                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2450                 break;
2451         case RTE_ETH_FLOW_L2_PAYLOAD:
2452                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2453                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2454                 break;
2455         case RTE_ETH_FLOW_VXLAN:
2456                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2457                         return -EINVAL;
2458                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2459                 filter->tunnel_type =
2460                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2461                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2462                 break;
2463         case RTE_ETH_FLOW_NVGRE:
2464                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2465                         return -EINVAL;
2466                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2467                 filter->tunnel_type =
2468                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2469                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2470                 break;
2471         case RTE_ETH_FLOW_UNKNOWN:
2472         case RTE_ETH_FLOW_RAW:
2473         case RTE_ETH_FLOW_FRAG_IPV4:
2474         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2475         case RTE_ETH_FLOW_FRAG_IPV6:
2476         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2477         case RTE_ETH_FLOW_IPV6_EX:
2478         case RTE_ETH_FLOW_IPV6_TCP_EX:
2479         case RTE_ETH_FLOW_IPV6_UDP_EX:
2480         case RTE_ETH_FLOW_GENEVE:
2481                 /* FALLTHROUGH */
2482         default:
2483                 return -EINVAL;
2484         }
2485
2486         vnic0 = &bp->vnic_info[0];
2487         vnic = &bp->vnic_info[fdir->action.rx_queue];
2488         if (vnic == NULL) {
2489                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2490                 return -EINVAL;
2491         }
2492
2493
2494         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2495                 rte_memcpy(filter->dst_macaddr,
2496                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2497                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2498         }
2499
2500         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2501                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2502                 filter1 = STAILQ_FIRST(&vnic0->filter);
2503                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2504         } else {
2505                 filter->dst_id = vnic->fw_vnic_id;
2506                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2507                         if (filter->dst_macaddr[i] == 0x00)
2508                                 filter1 = STAILQ_FIRST(&vnic0->filter);
2509                         else
2510                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2511         }
2512
2513         if (filter1 == NULL)
2514                 return -EINVAL;
2515
2516         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2517         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2518
2519         filter->enables = en;
2520
2521         return 0;
2522 }
2523
2524 static struct bnxt_filter_info *
2525 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2526                 struct bnxt_vnic_info **mvnic)
2527 {
2528         struct bnxt_filter_info *mf = NULL;
2529         int i;
2530
2531         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2532                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2533
2534                 STAILQ_FOREACH(mf, &vnic->filter, next) {
2535                         if (mf->filter_type == nf->filter_type &&
2536                             mf->flags == nf->flags &&
2537                             mf->src_port == nf->src_port &&
2538                             mf->src_port_mask == nf->src_port_mask &&
2539                             mf->dst_port == nf->dst_port &&
2540                             mf->dst_port_mask == nf->dst_port_mask &&
2541                             mf->ip_protocol == nf->ip_protocol &&
2542                             mf->ip_addr_type == nf->ip_addr_type &&
2543                             mf->ethertype == nf->ethertype &&
2544                             mf->vni == nf->vni &&
2545                             mf->tunnel_type == nf->tunnel_type &&
2546                             mf->l2_ovlan == nf->l2_ovlan &&
2547                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2548                             mf->l2_ivlan == nf->l2_ivlan &&
2549                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2550                             !memcmp(mf->l2_addr, nf->l2_addr,
2551                                     RTE_ETHER_ADDR_LEN) &&
2552                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2553                                     RTE_ETHER_ADDR_LEN) &&
2554                             !memcmp(mf->src_macaddr, nf->src_macaddr,
2555                                     RTE_ETHER_ADDR_LEN) &&
2556                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2557                                     RTE_ETHER_ADDR_LEN) &&
2558                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2559                                     sizeof(nf->src_ipaddr)) &&
2560                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2561                                     sizeof(nf->src_ipaddr_mask)) &&
2562                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2563                                     sizeof(nf->dst_ipaddr)) &&
2564                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2565                                     sizeof(nf->dst_ipaddr_mask))) {
2566                                 if (mvnic)
2567                                         *mvnic = vnic;
2568                                 return mf;
2569                         }
2570                 }
2571         }
2572         return NULL;
2573 }
2574
2575 static int
2576 bnxt_fdir_filter(struct rte_eth_dev *dev,
2577                  enum rte_filter_op filter_op,
2578                  void *arg)
2579 {
2580         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2581         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
2582         struct bnxt_filter_info *filter, *match;
2583         struct bnxt_vnic_info *vnic, *mvnic;
2584         int ret = 0, i;
2585
2586         if (filter_op == RTE_ETH_FILTER_NOP)
2587                 return 0;
2588
2589         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2590                 return -EINVAL;
2591
2592         switch (filter_op) {
2593         case RTE_ETH_FILTER_ADD:
2594         case RTE_ETH_FILTER_DELETE:
2595                 /* FALLTHROUGH */
2596                 filter = bnxt_get_unused_filter(bp);
2597                 if (filter == NULL) {
2598                         PMD_DRV_LOG(ERR,
2599                                 "Not enough resources for a new flow.\n");
2600                         return -ENOMEM;
2601                 }
2602
2603                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2604                 if (ret != 0)
2605                         goto free_filter;
2606                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2607
2608                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2609                         vnic = &bp->vnic_info[0];
2610                 else
2611                         vnic = &bp->vnic_info[fdir->action.rx_queue];
2612
2613                 match = bnxt_match_fdir(bp, filter, &mvnic);
2614                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2615                         if (match->dst_id == vnic->fw_vnic_id) {
2616                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2617                                 ret = -EEXIST;
2618                                 goto free_filter;
2619                         } else {
2620                                 match->dst_id = vnic->fw_vnic_id;
2621                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
2622                                                                   match->dst_id,
2623                                                                   match);
2624                                 STAILQ_REMOVE(&mvnic->filter, match,
2625                                               bnxt_filter_info, next);
2626                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2627                                 PMD_DRV_LOG(ERR,
2628                                         "Filter with matching pattern exist\n");
2629                                 PMD_DRV_LOG(ERR,
2630                                         "Updated it to new destination q\n");
2631                                 goto free_filter;
2632                         }
2633                 }
2634                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2635                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2636                         ret = -ENOENT;
2637                         goto free_filter;
2638                 }
2639
2640                 if (filter_op == RTE_ETH_FILTER_ADD) {
2641                         ret = bnxt_hwrm_set_ntuple_filter(bp,
2642                                                           filter->dst_id,
2643                                                           filter);
2644                         if (ret)
2645                                 goto free_filter;
2646                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2647                 } else {
2648                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2649                         STAILQ_REMOVE(&vnic->filter, match,
2650                                       bnxt_filter_info, next);
2651                         bnxt_free_filter(bp, match);
2652                         filter->fw_l2_filter_id = -1;
2653                         bnxt_free_filter(bp, filter);
2654                 }
2655                 break;
2656         case RTE_ETH_FILTER_FLUSH:
2657                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2658                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2659
2660                         STAILQ_FOREACH(filter, &vnic->filter, next) {
2661                                 if (filter->filter_type ==
2662                                     HWRM_CFA_NTUPLE_FILTER) {
2663                                         ret =
2664                                         bnxt_hwrm_clear_ntuple_filter(bp,
2665                                                                       filter);
2666                                         STAILQ_REMOVE(&vnic->filter, filter,
2667                                                       bnxt_filter_info, next);
2668                                 }
2669                         }
2670                 }
2671                 return ret;
2672         case RTE_ETH_FILTER_UPDATE:
2673         case RTE_ETH_FILTER_STATS:
2674         case RTE_ETH_FILTER_INFO:
2675                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2676                 break;
2677         default:
2678                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2679                 ret = -EINVAL;
2680                 break;
2681         }
2682         return ret;
2683
2684 free_filter:
2685         filter->fw_l2_filter_id = -1;
2686         bnxt_free_filter(bp, filter);
2687         return ret;
2688 }
2689
2690 static int
2691 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2692                     enum rte_filter_type filter_type,
2693                     enum rte_filter_op filter_op, void *arg)
2694 {
2695         int ret = 0;
2696
2697         switch (filter_type) {
2698         case RTE_ETH_FILTER_TUNNEL:
2699                 PMD_DRV_LOG(ERR,
2700                         "filter type: %d: To be implemented\n", filter_type);
2701                 break;
2702         case RTE_ETH_FILTER_FDIR:
2703                 ret = bnxt_fdir_filter(dev, filter_op, arg);
2704                 break;
2705         case RTE_ETH_FILTER_NTUPLE:
2706                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2707                 break;
2708         case RTE_ETH_FILTER_ETHERTYPE:
2709                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2710                 break;
2711         case RTE_ETH_FILTER_GENERIC:
2712                 if (filter_op != RTE_ETH_FILTER_GET)
2713                         return -EINVAL;
2714                 *(const void **)arg = &bnxt_flow_ops;
2715                 break;
2716         default:
2717                 PMD_DRV_LOG(ERR,
2718                         "Filter type (%d) not supported", filter_type);
2719                 ret = -EINVAL;
2720                 break;
2721         }
2722         return ret;
2723 }
2724
2725 static const uint32_t *
2726 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2727 {
2728         static const uint32_t ptypes[] = {
2729                 RTE_PTYPE_L2_ETHER_VLAN,
2730                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2731                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2732                 RTE_PTYPE_L4_ICMP,
2733                 RTE_PTYPE_L4_TCP,
2734                 RTE_PTYPE_L4_UDP,
2735                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2736                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2737                 RTE_PTYPE_INNER_L4_ICMP,
2738                 RTE_PTYPE_INNER_L4_TCP,
2739                 RTE_PTYPE_INNER_L4_UDP,
2740                 RTE_PTYPE_UNKNOWN
2741         };
2742
2743         if (!dev->rx_pkt_burst)
2744                 return NULL;
2745
2746         return ptypes;
2747 }
2748
2749 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2750                          int reg_win)
2751 {
2752         uint32_t reg_base = *reg_arr & 0xfffff000;
2753         uint32_t win_off;
2754         int i;
2755
2756         for (i = 0; i < count; i++) {
2757                 if ((reg_arr[i] & 0xfffff000) != reg_base)
2758                         return -ERANGE;
2759         }
2760         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2761         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
2762         return 0;
2763 }
2764
2765 static int bnxt_map_ptp_regs(struct bnxt *bp)
2766 {
2767         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2768         uint32_t *reg_arr;
2769         int rc, i;
2770
2771         reg_arr = ptp->rx_regs;
2772         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2773         if (rc)
2774                 return rc;
2775
2776         reg_arr = ptp->tx_regs;
2777         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2778         if (rc)
2779                 return rc;
2780
2781         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2782                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2783
2784         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2785                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2786
2787         return 0;
2788 }
2789
2790 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2791 {
2792         rte_write32(0, (uint8_t *)bp->bar0 +
2793                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
2794         rte_write32(0, (uint8_t *)bp->bar0 +
2795                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
2796 }
2797
2798 static uint64_t bnxt_cc_read(struct bnxt *bp)
2799 {
2800         uint64_t ns;
2801
2802         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2803                               BNXT_GRCPF_REG_SYNC_TIME));
2804         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2805                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2806         return ns;
2807 }
2808
2809 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2810 {
2811         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2812         uint32_t fifo;
2813
2814         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2815                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2816         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2817                 return -EAGAIN;
2818
2819         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2820                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2821         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2822                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2823         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2824                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2825
2826         return 0;
2827 }
2828
2829 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2830 {
2831         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2832         struct bnxt_pf_info *pf = &bp->pf;
2833         uint16_t port_id;
2834         uint32_t fifo;
2835
2836         if (!ptp)
2837                 return -ENODEV;
2838
2839         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2840                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2841         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2842                 return -EAGAIN;
2843
2844         port_id = pf->port_id;
2845         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2846                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
2847
2848         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2849                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2850         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2851 /*              bnxt_clr_rx_ts(bp);       TBD  */
2852                 return -EBUSY;
2853         }
2854
2855         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2856                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2857         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2858                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2859
2860         return 0;
2861 }
2862
2863 static int
2864 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2865 {
2866         uint64_t ns;
2867         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2868         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2869
2870         if (!ptp)
2871                 return 0;
2872
2873         ns = rte_timespec_to_ns(ts);
2874         /* Set the timecounters to a new value. */
2875         ptp->tc.nsec = ns;
2876
2877         return 0;
2878 }
2879
2880 static int
2881 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2882 {
2883         uint64_t ns, systime_cycles;
2884         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2885         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2886
2887         if (!ptp)
2888                 return 0;
2889
2890         systime_cycles = bnxt_cc_read(bp);
2891         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
2892         *ts = rte_ns_to_timespec(ns);
2893
2894         return 0;
2895 }
2896 static int
2897 bnxt_timesync_enable(struct rte_eth_dev *dev)
2898 {
2899         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2900         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2901         uint32_t shift = 0;
2902
2903         if (!ptp)
2904                 return 0;
2905
2906         ptp->rx_filter = 1;
2907         ptp->tx_tstamp_en = 1;
2908         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
2909
2910         if (!bnxt_hwrm_ptp_cfg(bp))
2911                 bnxt_map_ptp_regs(bp);
2912
2913         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
2914         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2915         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2916
2917         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2918         ptp->tc.cc_shift = shift;
2919         ptp->tc.nsec_mask = (1ULL << shift) - 1;
2920
2921         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2922         ptp->rx_tstamp_tc.cc_shift = shift;
2923         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2924
2925         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2926         ptp->tx_tstamp_tc.cc_shift = shift;
2927         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2928
2929         return 0;
2930 }
2931
2932 static int
2933 bnxt_timesync_disable(struct rte_eth_dev *dev)
2934 {
2935         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2936         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2937
2938         if (!ptp)
2939                 return 0;
2940
2941         ptp->rx_filter = 0;
2942         ptp->tx_tstamp_en = 0;
2943         ptp->rxctl = 0;
2944
2945         bnxt_hwrm_ptp_cfg(bp);
2946
2947         bnxt_unmap_ptp_regs(bp);
2948
2949         return 0;
2950 }
2951
2952 static int
2953 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
2954                                  struct timespec *timestamp,
2955                                  uint32_t flags __rte_unused)
2956 {
2957         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2958         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2959         uint64_t rx_tstamp_cycles = 0;
2960         uint64_t ns;
2961
2962         if (!ptp)
2963                 return 0;
2964
2965         bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
2966         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
2967         *timestamp = rte_ns_to_timespec(ns);
2968         return  0;
2969 }
2970
2971 static int
2972 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
2973                                  struct timespec *timestamp)
2974 {
2975         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2976         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2977         uint64_t tx_tstamp_cycles = 0;
2978         uint64_t ns;
2979
2980         if (!ptp)
2981                 return 0;
2982
2983         bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
2984         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
2985         *timestamp = rte_ns_to_timespec(ns);
2986
2987         return 0;
2988 }
2989
2990 static int
2991 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
2992 {
2993         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2994         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2995
2996         if (!ptp)
2997                 return 0;
2998
2999         ptp->tc.nsec += delta;
3000
3001         return 0;
3002 }
3003
3004 static int
3005 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3006 {
3007         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3008         int rc;
3009         uint32_t dir_entries;
3010         uint32_t entry_length;
3011
3012         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3013                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3014                 bp->pdev->addr.devid, bp->pdev->addr.function);
3015
3016         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3017         if (rc != 0)
3018                 return rc;
3019
3020         return dir_entries * entry_length;
3021 }
3022
3023 static int
3024 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3025                 struct rte_dev_eeprom_info *in_eeprom)
3026 {
3027         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3028         uint32_t index;
3029         uint32_t offset;
3030
3031         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3032                 "len = %d\n", bp->pdev->addr.domain,
3033                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3034                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3035
3036         if (in_eeprom->offset == 0) /* special offset value to get directory */
3037                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3038                                                 in_eeprom->data);
3039
3040         index = in_eeprom->offset >> 24;
3041         offset = in_eeprom->offset & 0xffffff;
3042
3043         if (index != 0)
3044                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3045                                            in_eeprom->length, in_eeprom->data);
3046
3047         return 0;
3048 }
3049
3050 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3051 {
3052         switch (dir_type) {
3053         case BNX_DIR_TYPE_CHIMP_PATCH:
3054         case BNX_DIR_TYPE_BOOTCODE:
3055         case BNX_DIR_TYPE_BOOTCODE_2:
3056         case BNX_DIR_TYPE_APE_FW:
3057         case BNX_DIR_TYPE_APE_PATCH:
3058         case BNX_DIR_TYPE_KONG_FW:
3059         case BNX_DIR_TYPE_KONG_PATCH:
3060         case BNX_DIR_TYPE_BONO_FW:
3061         case BNX_DIR_TYPE_BONO_PATCH:
3062                 /* FALLTHROUGH */
3063                 return true;
3064         }
3065
3066         return false;
3067 }
3068
3069 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3070 {
3071         switch (dir_type) {
3072         case BNX_DIR_TYPE_AVS:
3073         case BNX_DIR_TYPE_EXP_ROM_MBA:
3074         case BNX_DIR_TYPE_PCIE:
3075         case BNX_DIR_TYPE_TSCF_UCODE:
3076         case BNX_DIR_TYPE_EXT_PHY:
3077         case BNX_DIR_TYPE_CCM:
3078         case BNX_DIR_TYPE_ISCSI_BOOT:
3079         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3080         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3081                 /* FALLTHROUGH */
3082                 return true;
3083         }
3084
3085         return false;
3086 }
3087
3088 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3089 {
3090         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3091                 bnxt_dir_type_is_other_exec_format(dir_type);
3092 }
3093
3094 static int
3095 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3096                 struct rte_dev_eeprom_info *in_eeprom)
3097 {
3098         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3099         uint8_t index, dir_op;
3100         uint16_t type, ext, ordinal, attr;
3101
3102         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3103                 "len = %d\n", bp->pdev->addr.domain,
3104                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3105                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3106
3107         if (!BNXT_PF(bp)) {
3108                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3109                 return -EINVAL;
3110         }
3111
3112         type = in_eeprom->magic >> 16;
3113
3114         if (type == 0xffff) { /* special value for directory operations */
3115                 index = in_eeprom->magic & 0xff;
3116                 dir_op = in_eeprom->magic >> 8;
3117                 if (index == 0)
3118                         return -EINVAL;
3119                 switch (dir_op) {
3120                 case 0x0e: /* erase */
3121                         if (in_eeprom->offset != ~in_eeprom->magic)
3122                                 return -EINVAL;
3123                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3124                 default:
3125                         return -EINVAL;
3126                 }
3127         }
3128
3129         /* Create or re-write an NVM item: */
3130         if (bnxt_dir_type_is_executable(type) == true)
3131                 return -EOPNOTSUPP;
3132         ext = in_eeprom->magic & 0xffff;
3133         ordinal = in_eeprom->offset >> 16;
3134         attr = in_eeprom->offset & 0xffff;
3135
3136         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3137                                      in_eeprom->data, in_eeprom->length);
3138         return 0;
3139 }
3140
3141 /*
3142  * Initialization
3143  */
3144
3145 static const struct eth_dev_ops bnxt_dev_ops = {
3146         .dev_infos_get = bnxt_dev_info_get_op,
3147         .dev_close = bnxt_dev_close_op,
3148         .dev_configure = bnxt_dev_configure_op,
3149         .dev_start = bnxt_dev_start_op,
3150         .dev_stop = bnxt_dev_stop_op,
3151         .dev_set_link_up = bnxt_dev_set_link_up_op,
3152         .dev_set_link_down = bnxt_dev_set_link_down_op,
3153         .stats_get = bnxt_stats_get_op,
3154         .stats_reset = bnxt_stats_reset_op,
3155         .rx_queue_setup = bnxt_rx_queue_setup_op,
3156         .rx_queue_release = bnxt_rx_queue_release_op,
3157         .tx_queue_setup = bnxt_tx_queue_setup_op,
3158         .tx_queue_release = bnxt_tx_queue_release_op,
3159         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3160         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3161         .reta_update = bnxt_reta_update_op,
3162         .reta_query = bnxt_reta_query_op,
3163         .rss_hash_update = bnxt_rss_hash_update_op,
3164         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3165         .link_update = bnxt_link_update_op,
3166         .promiscuous_enable = bnxt_promiscuous_enable_op,
3167         .promiscuous_disable = bnxt_promiscuous_disable_op,
3168         .allmulticast_enable = bnxt_allmulticast_enable_op,
3169         .allmulticast_disable = bnxt_allmulticast_disable_op,
3170         .mac_addr_add = bnxt_mac_addr_add_op,
3171         .mac_addr_remove = bnxt_mac_addr_remove_op,
3172         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3173         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3174         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3175         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3176         .vlan_filter_set = bnxt_vlan_filter_set_op,
3177         .vlan_offload_set = bnxt_vlan_offload_set_op,
3178         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3179         .mtu_set = bnxt_mtu_set_op,
3180         .mac_addr_set = bnxt_set_default_mac_addr_op,
3181         .xstats_get = bnxt_dev_xstats_get_op,
3182         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3183         .xstats_reset = bnxt_dev_xstats_reset_op,
3184         .fw_version_get = bnxt_fw_version_get,
3185         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3186         .rxq_info_get = bnxt_rxq_info_get_op,
3187         .txq_info_get = bnxt_txq_info_get_op,
3188         .dev_led_on = bnxt_dev_led_on_op,
3189         .dev_led_off = bnxt_dev_led_off_op,
3190         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3191         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3192         .rx_queue_count = bnxt_rx_queue_count_op,
3193         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3194         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3195         .rx_queue_start = bnxt_rx_queue_start,
3196         .rx_queue_stop = bnxt_rx_queue_stop,
3197         .tx_queue_start = bnxt_tx_queue_start,
3198         .tx_queue_stop = bnxt_tx_queue_stop,
3199         .filter_ctrl = bnxt_filter_ctrl_op,
3200         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3201         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3202         .get_eeprom           = bnxt_get_eeprom_op,
3203         .set_eeprom           = bnxt_set_eeprom_op,
3204         .timesync_enable      = bnxt_timesync_enable,
3205         .timesync_disable     = bnxt_timesync_disable,
3206         .timesync_read_time   = bnxt_timesync_read_time,
3207         .timesync_write_time   = bnxt_timesync_write_time,
3208         .timesync_adjust_time = bnxt_timesync_adjust_time,
3209         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3210         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3211 };
3212
3213 static bool bnxt_vf_pciid(uint16_t id)
3214 {
3215         if (id == BROADCOM_DEV_ID_57304_VF ||
3216             id == BROADCOM_DEV_ID_57406_VF ||
3217             id == BROADCOM_DEV_ID_5731X_VF ||
3218             id == BROADCOM_DEV_ID_5741X_VF ||
3219             id == BROADCOM_DEV_ID_57414_VF ||
3220             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3221             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3222             id == BROADCOM_DEV_ID_58802_VF)
3223                 return true;
3224         return false;
3225 }
3226
3227 bool bnxt_stratus_device(struct bnxt *bp)
3228 {
3229         uint16_t id = bp->pdev->id.device_id;
3230
3231         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3232             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3233             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3234                 return true;
3235         return false;
3236 }
3237
3238 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3239 {
3240         struct bnxt *bp = eth_dev->data->dev_private;
3241         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3242         int rc;
3243
3244         /* enable device (incl. PCI PM wakeup), and bus-mastering */
3245         if (!pci_dev->mem_resource[0].addr) {
3246                 PMD_DRV_LOG(ERR,
3247                         "Cannot find PCI device base address, aborting\n");
3248                 rc = -ENODEV;
3249                 goto init_err_disable;
3250         }
3251
3252         bp->eth_dev = eth_dev;
3253         bp->pdev = pci_dev;
3254
3255         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3256         if (!bp->bar0) {
3257                 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3258                 rc = -ENOMEM;
3259                 goto init_err_release;
3260         }
3261
3262         if (!pci_dev->mem_resource[2].addr) {
3263                 PMD_DRV_LOG(ERR,
3264                             "Cannot find PCI device BAR 2 address, aborting\n");
3265                 rc = -ENODEV;
3266                 goto init_err_release;
3267         } else {
3268                 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3269         }
3270
3271         return 0;
3272
3273 init_err_release:
3274         if (bp->bar0)
3275                 bp->bar0 = NULL;
3276         if (bp->doorbell_base)
3277                 bp->doorbell_base = NULL;
3278
3279 init_err_disable:
3280
3281         return rc;
3282 }
3283
3284
3285 #define ALLOW_FUNC(x)   \
3286         { \
3287                 typeof(x) arg = (x); \
3288                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3289                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3290         }
3291 static int
3292 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3293 {
3294         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3295         char mz_name[RTE_MEMZONE_NAMESIZE];
3296         const struct rte_memzone *mz = NULL;
3297         static int version_printed;
3298         uint32_t total_alloc_len;
3299         rte_iova_t mz_phys_addr;
3300         struct bnxt *bp;
3301         int rc;
3302
3303         if (version_printed++ == 0)
3304                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3305
3306         rte_eth_copy_pci_info(eth_dev, pci_dev);
3307
3308         bp = eth_dev->data->dev_private;
3309
3310         bp->dev_stopped = 1;
3311
3312         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3313                 goto skip_init;
3314
3315         if (bnxt_vf_pciid(pci_dev->id.device_id))
3316                 bp->flags |= BNXT_FLAG_VF;
3317
3318         rc = bnxt_init_board(eth_dev);
3319         if (rc) {
3320                 PMD_DRV_LOG(ERR,
3321                         "Board initialization failed rc: %x\n", rc);
3322                 goto error;
3323         }
3324 skip_init:
3325         eth_dev->dev_ops = &bnxt_dev_ops;
3326         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3327         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3328         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3329                 return 0;
3330
3331         if (pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3332                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3333                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3334                          pci_dev->addr.bus, pci_dev->addr.devid,
3335                          pci_dev->addr.function, "rx_port_stats");
3336                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3337                 mz = rte_memzone_lookup(mz_name);
3338                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3339                                         sizeof(struct rx_port_stats) +
3340                                         sizeof(struct rx_port_stats_ext) +
3341                                         512);
3342                 if (!mz) {
3343                         mz = rte_memzone_reserve(mz_name, total_alloc_len,
3344                                         SOCKET_ID_ANY,
3345                                         RTE_MEMZONE_2MB |
3346                                         RTE_MEMZONE_SIZE_HINT_ONLY |
3347                                         RTE_MEMZONE_IOVA_CONTIG);
3348                         if (mz == NULL)
3349                                 return -ENOMEM;
3350                 }
3351                 memset(mz->addr, 0, mz->len);
3352                 mz_phys_addr = mz->iova;
3353                 if ((unsigned long)mz->addr == mz_phys_addr) {
3354                         PMD_DRV_LOG(INFO,
3355                                 "Memzone physical address same as virtual using rte_mem_virt2iova()\n");
3356                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3357                         if (mz_phys_addr == 0) {
3358                                 PMD_DRV_LOG(ERR,
3359                                 "unable to map address to physical memory\n");
3360                                 return -ENOMEM;
3361                         }
3362                 }
3363
3364                 bp->rx_mem_zone = (const void *)mz;
3365                 bp->hw_rx_port_stats = mz->addr;
3366                 bp->hw_rx_port_stats_map = mz_phys_addr;
3367
3368                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3369                          "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3370                          pci_dev->addr.bus, pci_dev->addr.devid,
3371                          pci_dev->addr.function, "tx_port_stats");
3372                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3373                 mz = rte_memzone_lookup(mz_name);
3374                 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3375                                         sizeof(struct tx_port_stats) +
3376                                         sizeof(struct tx_port_stats_ext) +
3377                                         512);
3378                 if (!mz) {
3379                         mz = rte_memzone_reserve(mz_name,
3380                                         total_alloc_len,
3381                                         SOCKET_ID_ANY,
3382                                         RTE_MEMZONE_2MB |
3383                                         RTE_MEMZONE_SIZE_HINT_ONLY |
3384                                         RTE_MEMZONE_IOVA_CONTIG);
3385                         if (mz == NULL)
3386                                 return -ENOMEM;
3387                 }
3388                 memset(mz->addr, 0, mz->len);
3389                 mz_phys_addr = mz->iova;
3390                 if ((unsigned long)mz->addr == mz_phys_addr) {
3391                         PMD_DRV_LOG(WARNING,
3392                                 "Memzone physical address same as virtual.\n");
3393                         PMD_DRV_LOG(WARNING,
3394                                 "Using rte_mem_virt2iova()\n");
3395                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
3396                         if (mz_phys_addr == 0) {
3397                                 PMD_DRV_LOG(ERR,
3398                                 "unable to map address to physical memory\n");
3399                                 return -ENOMEM;
3400                         }
3401                 }
3402
3403                 bp->tx_mem_zone = (const void *)mz;
3404                 bp->hw_tx_port_stats = mz->addr;
3405                 bp->hw_tx_port_stats_map = mz_phys_addr;
3406
3407                 bp->flags |= BNXT_FLAG_PORT_STATS;
3408
3409                 /* Display extended statistics if FW supports it */
3410                 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
3411                     bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0)
3412                         goto skip_ext_stats;
3413
3414                 bp->hw_rx_port_stats_ext = (void *)
3415                         (bp->hw_rx_port_stats + sizeof(struct rx_port_stats));
3416                 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
3417                         sizeof(struct rx_port_stats);
3418                 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
3419
3420
3421                 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2) {
3422                         bp->hw_tx_port_stats_ext = (void *)
3423                         (bp->hw_tx_port_stats + sizeof(struct tx_port_stats));
3424                         bp->hw_tx_port_stats_ext_map =
3425                                 bp->hw_tx_port_stats_map +
3426                                 sizeof(struct tx_port_stats);
3427                         bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
3428                 }
3429         }
3430
3431 skip_ext_stats:
3432         rc = bnxt_alloc_hwrm_resources(bp);
3433         if (rc) {
3434                 PMD_DRV_LOG(ERR,
3435                         "hwrm resource allocation failure rc: %x\n", rc);
3436                 goto error_free;
3437         }
3438         rc = bnxt_hwrm_ver_get(bp);
3439         if (rc)
3440                 goto error_free;
3441         rc = bnxt_hwrm_queue_qportcfg(bp);
3442         if (rc) {
3443                 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3444                 goto error_free;
3445         }
3446
3447         rc = bnxt_hwrm_func_qcfg(bp);
3448         if (rc) {
3449                 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3450                 goto error_free;
3451         }
3452
3453         /* Get the MAX capabilities for this function */
3454         rc = bnxt_hwrm_func_qcaps(bp);
3455         if (rc) {
3456                 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3457                 goto error_free;
3458         }
3459         if (bp->max_tx_rings == 0) {
3460                 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3461                 rc = -EBUSY;
3462                 goto error_free;
3463         }
3464         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3465                                         RTE_ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3466         if (eth_dev->data->mac_addrs == NULL) {
3467                 PMD_DRV_LOG(ERR,
3468                         "Failed to alloc %u bytes needed to store MAC addr tbl",
3469                         RTE_ETHER_ADDR_LEN * bp->max_l2_ctx);
3470                 rc = -ENOMEM;
3471                 goto error_free;
3472         }
3473
3474         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
3475                 PMD_DRV_LOG(ERR,
3476                             "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
3477                             bp->dflt_mac_addr[0], bp->dflt_mac_addr[1],
3478                             bp->dflt_mac_addr[2], bp->dflt_mac_addr[3],
3479                             bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]);
3480                 rc = -EINVAL;
3481                 goto error_free;
3482         }
3483         /* Copy the permanent MAC from the qcap response address now. */
3484         memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3485         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
3486
3487         if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3488                 /* 1 ring is for default completion ring */
3489                 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3490                 rc = -ENOSPC;
3491                 goto error_free;
3492         }
3493
3494         bp->grp_info = rte_zmalloc("bnxt_grp_info",
3495                                 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3496         if (!bp->grp_info) {
3497                 PMD_DRV_LOG(ERR,
3498                         "Failed to alloc %zu bytes to store group info table\n",
3499                         sizeof(*bp->grp_info) * bp->max_ring_grps);
3500                 rc = -ENOMEM;
3501                 goto error_free;
3502         }
3503
3504         /* Forward all requests if firmware is new enough */
3505         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3506             (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3507             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3508                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3509         } else {
3510                 PMD_DRV_LOG(WARNING,
3511                         "Firmware too old for VF mailbox functionality\n");
3512                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3513         }
3514
3515         /*
3516          * The following are used for driver cleanup.  If we disallow these,
3517          * VF drivers can't clean up cleanly.
3518          */
3519         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3520         ALLOW_FUNC(HWRM_VNIC_FREE);
3521         ALLOW_FUNC(HWRM_RING_FREE);
3522         ALLOW_FUNC(HWRM_RING_GRP_FREE);
3523         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3524         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3525         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3526         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3527         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3528         rc = bnxt_hwrm_func_driver_register(bp);
3529         if (rc) {
3530                 PMD_DRV_LOG(ERR,
3531                         "Failed to register driver");
3532                 rc = -EBUSY;
3533                 goto error_free;
3534         }
3535
3536         PMD_DRV_LOG(INFO,
3537                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3538                 pci_dev->mem_resource[0].phys_addr,
3539                 pci_dev->mem_resource[0].addr);
3540
3541         rc = bnxt_hwrm_func_reset(bp);
3542         if (rc) {
3543                 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3544                 rc = -EIO;
3545                 goto error_free;
3546         }
3547
3548         if (BNXT_PF(bp)) {
3549                 //if (bp->pf.active_vfs) {
3550                         // TODO: Deallocate VF resources?
3551                 //}
3552                 if (bp->pdev->max_vfs) {
3553                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3554                         if (rc) {
3555                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3556                                 goto error_free;
3557                         }
3558                 } else {
3559                         rc = bnxt_hwrm_allocate_pf_only(bp);
3560                         if (rc) {
3561                                 PMD_DRV_LOG(ERR,
3562                                         "Failed to allocate PF resources\n");
3563                                 goto error_free;
3564                         }
3565                 }
3566         }
3567
3568         bnxt_hwrm_port_led_qcaps(bp);
3569
3570         rc = bnxt_setup_int(bp);
3571         if (rc)
3572                 goto error_free;
3573
3574         rc = bnxt_alloc_mem(bp);
3575         if (rc)
3576                 goto error_free_int;
3577
3578         rc = bnxt_request_int(bp);
3579         if (rc)
3580                 goto error_free_int;
3581
3582         bnxt_enable_int(bp);
3583         bnxt_init_nic(bp);
3584
3585         return 0;
3586
3587 error_free_int:
3588         bnxt_disable_int(bp);
3589         bnxt_hwrm_func_buf_unrgtr(bp);
3590         bnxt_free_int(bp);
3591         bnxt_free_mem(bp);
3592 error_free:
3593         bnxt_dev_uninit(eth_dev);
3594 error:
3595         return rc;
3596 }
3597
3598 static int
3599 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
3600 {
3601         struct bnxt *bp = eth_dev->data->dev_private;
3602         int rc;
3603
3604         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3605                 return -EPERM;
3606
3607         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
3608         bnxt_disable_int(bp);
3609         bnxt_free_int(bp);
3610         bnxt_free_mem(bp);
3611         if (bp->grp_info != NULL) {
3612                 rte_free(bp->grp_info);
3613                 bp->grp_info = NULL;
3614         }
3615         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3616         bnxt_free_hwrm_resources(bp);
3617
3618         if (bp->tx_mem_zone) {
3619                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3620                 bp->tx_mem_zone = NULL;
3621         }
3622
3623         if (bp->rx_mem_zone) {
3624                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3625                 bp->rx_mem_zone = NULL;
3626         }
3627
3628         if (bp->dev_stopped == 0)
3629                 bnxt_dev_close_op(eth_dev);
3630         if (bp->pf.vf_info)
3631                 rte_free(bp->pf.vf_info);
3632         eth_dev->dev_ops = NULL;
3633         eth_dev->rx_pkt_burst = NULL;
3634         eth_dev->tx_pkt_burst = NULL;
3635
3636         return rc;
3637 }
3638
3639 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3640         struct rte_pci_device *pci_dev)
3641 {
3642         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
3643                 bnxt_dev_init);
3644 }
3645
3646 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
3647 {
3648         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3649                 return rte_eth_dev_pci_generic_remove(pci_dev,
3650                                 bnxt_dev_uninit);
3651         else
3652                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3653 }
3654
3655 static struct rte_pci_driver bnxt_rte_pmd = {
3656         .id_table = bnxt_pci_id_map,
3657         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
3658                 RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_IOVA_AS_VA,
3659         .probe = bnxt_pci_probe,
3660         .remove = bnxt_pci_remove,
3661 };
3662
3663 static bool
3664 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
3665 {
3666         if (strcmp(dev->device->driver->name, drv->driver.name))
3667                 return false;
3668
3669         return true;
3670 }
3671
3672 bool is_bnxt_supported(struct rte_eth_dev *dev)
3673 {
3674         return is_device_supported(dev, &bnxt_rte_pmd);
3675 }
3676
3677 RTE_INIT(bnxt_init_log)
3678 {
3679         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
3680         if (bnxt_logtype_driver >= 0)
3681                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
3682 }
3683
3684 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
3685 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
3686 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");