1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
29 #include "bnxt_util.h"
31 #define DRV_MODULE_NAME "bnxt"
32 static const char bnxt_version[] =
33 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
34 int bnxt_logtype_driver;
36 #define PCI_VENDOR_ID_BROADCOM 0x14E4
38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
41 #define BROADCOM_DEV_ID_57414_VF 0x16c1
42 #define BROADCOM_DEV_ID_57301 0x16c8
43 #define BROADCOM_DEV_ID_57302 0x16c9
44 #define BROADCOM_DEV_ID_57304_PF 0x16ca
45 #define BROADCOM_DEV_ID_57304_VF 0x16cb
46 #define BROADCOM_DEV_ID_57417_MF 0x16cc
47 #define BROADCOM_DEV_ID_NS2 0x16cd
48 #define BROADCOM_DEV_ID_57311 0x16ce
49 #define BROADCOM_DEV_ID_57312 0x16cf
50 #define BROADCOM_DEV_ID_57402 0x16d0
51 #define BROADCOM_DEV_ID_57404 0x16d1
52 #define BROADCOM_DEV_ID_57406_PF 0x16d2
53 #define BROADCOM_DEV_ID_57406_VF 0x16d3
54 #define BROADCOM_DEV_ID_57402_MF 0x16d4
55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
56 #define BROADCOM_DEV_ID_57412 0x16d6
57 #define BROADCOM_DEV_ID_57414 0x16d7
58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
61 #define BROADCOM_DEV_ID_57412_MF 0x16de
62 #define BROADCOM_DEV_ID_57314 0x16df
63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
68 #define BROADCOM_DEV_ID_57404_MF 0x16e7
69 #define BROADCOM_DEV_ID_57406_MF 0x16e8
70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
71 #define BROADCOM_DEV_ID_57407_MF 0x16ea
72 #define BROADCOM_DEV_ID_57414_MF 0x16ec
73 #define BROADCOM_DEV_ID_57416_MF 0x16ee
74 #define BROADCOM_DEV_ID_58802 0xd802
75 #define BROADCOM_DEV_ID_58804 0xd804
76 #define BROADCOM_DEV_ID_58808 0x16f0
77 #define BROADCOM_DEV_ID_58802_VF 0xd800
79 static const struct rte_pci_id bnxt_pci_id_map[] = {
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
81 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
83 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
122 { .vendor_id = 0, /* sentinel */ },
125 #define BNXT_ETH_RSS_SUPPORT ( \
127 ETH_RSS_NONFRAG_IPV4_TCP | \
128 ETH_RSS_NONFRAG_IPV4_UDP | \
130 ETH_RSS_NONFRAG_IPV6_TCP | \
131 ETH_RSS_NONFRAG_IPV6_UDP)
133 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
134 DEV_TX_OFFLOAD_IPV4_CKSUM | \
135 DEV_TX_OFFLOAD_TCP_CKSUM | \
136 DEV_TX_OFFLOAD_UDP_CKSUM | \
137 DEV_TX_OFFLOAD_TCP_TSO | \
138 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
139 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
140 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
141 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
142 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
143 DEV_TX_OFFLOAD_MULTI_SEGS)
145 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
146 DEV_RX_OFFLOAD_VLAN_STRIP | \
147 DEV_RX_OFFLOAD_IPV4_CKSUM | \
148 DEV_RX_OFFLOAD_UDP_CKSUM | \
149 DEV_RX_OFFLOAD_TCP_CKSUM | \
150 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
151 DEV_RX_OFFLOAD_JUMBO_FRAME | \
152 DEV_RX_OFFLOAD_KEEP_CRC | \
153 DEV_RX_OFFLOAD_TCP_LRO)
155 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
156 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
157 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
158 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
160 /***********************/
163 * High level utility functions
166 static void bnxt_free_mem(struct bnxt *bp)
168 bnxt_free_filter_mem(bp);
169 bnxt_free_vnic_attributes(bp);
170 bnxt_free_vnic_mem(bp);
173 bnxt_free_tx_rings(bp);
174 bnxt_free_rx_rings(bp);
177 static int bnxt_alloc_mem(struct bnxt *bp)
181 rc = bnxt_alloc_vnic_mem(bp);
185 rc = bnxt_alloc_vnic_attributes(bp);
189 rc = bnxt_alloc_filter_mem(bp);
200 static int bnxt_init_chip(struct bnxt *bp)
202 struct bnxt_rx_queue *rxq;
203 struct rte_eth_link new;
204 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
205 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
206 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
207 uint64_t rx_offloads = dev_conf->rxmode.offloads;
208 uint32_t intr_vector = 0;
209 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
210 uint32_t vec = BNXT_MISC_VEC_ID;
214 /* disable uio/vfio intr/eventfd mapping */
215 rte_intr_disable(intr_handle);
217 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
218 bp->eth_dev->data->dev_conf.rxmode.offloads |=
219 DEV_RX_OFFLOAD_JUMBO_FRAME;
220 bp->flags |= BNXT_FLAG_JUMBO;
222 bp->eth_dev->data->dev_conf.rxmode.offloads &=
223 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
224 bp->flags &= ~BNXT_FLAG_JUMBO;
227 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
229 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
233 rc = bnxt_alloc_hwrm_rings(bp);
235 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
239 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
241 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
245 rc = bnxt_mq_rx_configure(bp);
247 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
251 /* VNIC configuration */
252 for (i = 0; i < bp->nr_vnics; i++) {
253 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
254 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
255 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
257 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
258 if (!vnic->fw_grp_ids) {
260 "Failed to alloc %d bytes for group ids\n",
265 memset(vnic->fw_grp_ids, -1, size);
267 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
268 i, vnic, vnic->fw_grp_ids);
270 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
272 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
277 /* Alloc RSS context only if RSS mode is enabled */
278 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
279 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
282 "HWRM vnic %d ctx alloc failure rc: %x\n",
289 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
290 * setting is not available at this time, it will not be
291 * configured correctly in the CFA.
293 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
294 vnic->vlan_strip = true;
296 vnic->vlan_strip = false;
298 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
300 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
305 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
308 "HWRM vnic %d filter failure rc: %x\n",
313 for (j = 0; j < bp->rx_nr_rings; j++) {
314 rxq = bp->eth_dev->data->rx_queues[j];
317 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
318 j, rxq->vnic, rxq->vnic->fw_grp_ids);
320 if (rxq->rx_deferred_start)
321 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
324 rc = bnxt_vnic_rss_configure(bp, vnic);
327 "HWRM vnic set RSS failure rc: %x\n", rc);
331 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
333 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
334 DEV_RX_OFFLOAD_TCP_LRO)
335 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
337 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
339 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
342 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
346 /* check and configure queue intr-vector mapping */
347 if ((rte_intr_cap_multiple(intr_handle) ||
348 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
349 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
350 intr_vector = bp->eth_dev->data->nb_rx_queues;
351 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
352 if (intr_vector > bp->rx_cp_nr_rings) {
353 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
357 if (rte_intr_efd_enable(intr_handle, intr_vector))
361 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
362 intr_handle->intr_vec =
363 rte_zmalloc("intr_vec",
364 bp->eth_dev->data->nb_rx_queues *
366 if (intr_handle->intr_vec == NULL) {
367 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
368 " intr_vec", bp->eth_dev->data->nb_rx_queues);
371 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
372 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
373 intr_handle->intr_vec, intr_handle->nb_efd,
374 intr_handle->max_intr);
377 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
379 intr_handle->intr_vec[queue_id] = vec;
380 if (vec < base + intr_handle->nb_efd - 1)
384 /* enable uio/vfio intr/eventfd mapping */
385 rte_intr_enable(intr_handle);
387 rc = bnxt_get_hwrm_link_config(bp, &new);
389 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
393 if (!bp->link_info.link_up) {
394 rc = bnxt_set_hwrm_link_config(bp, true);
397 "HWRM link config failure rc: %x\n", rc);
401 bnxt_print_link_info(bp->eth_dev);
406 bnxt_free_all_hwrm_resources(bp);
408 /* Some of the error status returned by FW may not be from errno.h */
415 static int bnxt_shutdown_nic(struct bnxt *bp)
417 bnxt_free_all_hwrm_resources(bp);
418 bnxt_free_all_filters(bp);
419 bnxt_free_all_vnics(bp);
423 static int bnxt_init_nic(struct bnxt *bp)
427 rc = bnxt_init_ring_grps(bp);
432 bnxt_init_filters(bp);
438 * Device configuration and status function
441 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
442 struct rte_eth_dev_info *dev_info)
444 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
445 uint16_t max_vnics, i, j, vpool, vrxq;
446 unsigned int max_rx_rings;
449 dev_info->max_mac_addrs = bp->max_l2_ctx;
450 dev_info->max_hash_mac_addrs = 0;
452 /* PF/VF specifics */
454 dev_info->max_vfs = bp->pdev->max_vfs;
455 max_rx_rings = RTE_MIN(bp->max_vnics, bp->max_stat_ctx);
456 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
457 dev_info->max_rx_queues = max_rx_rings;
458 dev_info->max_tx_queues = max_rx_rings;
459 dev_info->reta_size = HW_HASH_INDEX_SIZE;
460 dev_info->hash_key_size = 40;
461 max_vnics = bp->max_vnics;
463 /* Fast path specifics */
464 dev_info->min_rx_bufsize = 1;
465 dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
466 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
468 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
469 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
470 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
471 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
472 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
475 dev_info->default_rxconf = (struct rte_eth_rxconf) {
481 .rx_free_thresh = 32,
482 /* If no descriptors available, pkts are dropped by default */
486 dev_info->default_txconf = (struct rte_eth_txconf) {
492 .tx_free_thresh = 32,
495 eth_dev->data->dev_conf.intr_conf.lsc = 1;
497 eth_dev->data->dev_conf.intr_conf.rxq = 1;
498 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
499 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
500 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
501 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
506 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
507 * need further investigation.
511 vpool = 64; /* ETH_64_POOLS */
512 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
513 for (i = 0; i < 4; vpool >>= 1, i++) {
514 if (max_vnics > vpool) {
515 for (j = 0; j < 5; vrxq >>= 1, j++) {
516 if (dev_info->max_rx_queues > vrxq) {
522 /* Not enough resources to support VMDq */
526 /* Not enough resources to support VMDq */
530 dev_info->max_vmdq_pools = vpool;
531 dev_info->vmdq_queue_num = vrxq;
533 dev_info->vmdq_pool_base = 0;
534 dev_info->vmdq_queue_base = 0;
537 /* Configure the device based on the configuration provided */
538 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
540 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
541 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
544 bp->rx_queues = (void *)eth_dev->data->rx_queues;
545 bp->tx_queues = (void *)eth_dev->data->tx_queues;
546 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
547 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
549 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
550 rc = bnxt_hwrm_check_vf_rings(bp);
552 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
556 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
558 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
562 /* legacy driver needs to get updated values */
563 rc = bnxt_hwrm_func_qcaps(bp);
565 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
570 /* Inherit new configurations */
571 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
572 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
573 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
575 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
577 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps ||
578 (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
579 bp->max_vnics < eth_dev->data->nb_rx_queues)) {
581 "Insufficient resources to support requested config\n");
583 "Num Queues Requested: Tx %d, Rx %d\n",
584 eth_dev->data->nb_tx_queues,
585 eth_dev->data->nb_rx_queues);
587 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
588 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
589 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
593 bp->rx_cp_nr_rings = bp->rx_nr_rings;
594 bp->tx_cp_nr_rings = bp->tx_nr_rings;
596 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
598 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
599 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
601 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
606 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
608 struct rte_eth_link *link = ð_dev->data->dev_link;
610 if (link->link_status)
611 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
612 eth_dev->data->port_id,
613 (uint32_t)link->link_speed,
614 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
615 ("full-duplex") : ("half-duplex\n"));
617 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
618 eth_dev->data->port_id);
621 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
623 bnxt_print_link_info(eth_dev);
628 * Determine whether the current configuration requires support for scattered
629 * receive; return 1 if scattered receive is required and 0 if not.
631 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
636 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
637 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
639 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
640 RTE_PKTMBUF_HEADROOM);
641 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
647 static eth_rx_burst_t
648 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
652 * Vector mode receive can be enabled only if scatter rx is not
653 * in use and rx offloads are limited to VLAN stripping and
656 if (!eth_dev->data->scattered_rx &&
657 !(eth_dev->data->dev_conf.rxmode.offloads &
658 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
659 DEV_RX_OFFLOAD_KEEP_CRC |
660 DEV_RX_OFFLOAD_JUMBO_FRAME |
661 DEV_RX_OFFLOAD_IPV4_CKSUM |
662 DEV_RX_OFFLOAD_UDP_CKSUM |
663 DEV_RX_OFFLOAD_TCP_CKSUM |
664 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
665 DEV_RX_OFFLOAD_VLAN_FILTER))) {
666 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
667 eth_dev->data->port_id);
668 return bnxt_recv_pkts_vec;
670 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
671 eth_dev->data->port_id);
673 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
674 eth_dev->data->port_id,
675 eth_dev->data->scattered_rx,
676 eth_dev->data->dev_conf.rxmode.offloads);
678 return bnxt_recv_pkts;
681 static eth_tx_burst_t
682 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
686 * Vector mode receive can be enabled only if scatter tx is not
687 * in use and tx offloads other than VLAN insertion are not
690 if (!eth_dev->data->scattered_rx &&
691 !(eth_dev->data->dev_conf.txmode.offloads &
692 ~DEV_TX_OFFLOAD_VLAN_INSERT)) {
693 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
694 eth_dev->data->port_id);
695 return bnxt_xmit_pkts_vec;
697 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
698 eth_dev->data->port_id);
700 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
701 eth_dev->data->port_id,
702 eth_dev->data->scattered_rx,
703 eth_dev->data->dev_conf.txmode.offloads);
705 return bnxt_xmit_pkts;
708 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
710 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
711 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
715 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
717 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
718 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
722 rc = bnxt_init_chip(bp);
726 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
728 bnxt_link_update_op(eth_dev, 1);
730 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
731 vlan_mask |= ETH_VLAN_FILTER_MASK;
732 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
733 vlan_mask |= ETH_VLAN_STRIP_MASK;
734 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
738 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
739 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
740 bp->flags |= BNXT_FLAG_INIT_DONE;
744 bnxt_shutdown_nic(bp);
745 bnxt_free_tx_mbufs(bp);
746 bnxt_free_rx_mbufs(bp);
750 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
752 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
755 if (!bp->link_info.link_up)
756 rc = bnxt_set_hwrm_link_config(bp, true);
758 eth_dev->data->dev_link.link_status = 1;
760 bnxt_print_link_info(eth_dev);
764 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
766 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
768 eth_dev->data->dev_link.link_status = 0;
769 bnxt_set_hwrm_link_config(bp, false);
770 bp->link_info.link_up = 0;
775 /* Unload the driver, release resources */
776 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
778 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
780 bp->flags &= ~BNXT_FLAG_INIT_DONE;
781 if (bp->eth_dev->data->dev_started) {
782 /* TBD: STOP HW queues DMA */
783 eth_dev->data->dev_link.link_status = 0;
785 bnxt_set_hwrm_link_config(bp, false);
786 bnxt_hwrm_port_clr_stats(bp);
787 bnxt_free_tx_mbufs(bp);
788 bnxt_free_rx_mbufs(bp);
789 bnxt_shutdown_nic(bp);
793 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
795 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
797 if (bp->dev_stopped == 0)
798 bnxt_dev_stop_op(eth_dev);
800 if (eth_dev->data->mac_addrs != NULL) {
801 rte_free(eth_dev->data->mac_addrs);
802 eth_dev->data->mac_addrs = NULL;
804 if (bp->grp_info != NULL) {
805 rte_free(bp->grp_info);
809 bnxt_dev_uninit(eth_dev);
812 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
815 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
816 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
817 struct bnxt_vnic_info *vnic;
818 struct bnxt_filter_info *filter, *temp_filter;
822 * Loop through all VNICs from the specified filter flow pools to
823 * remove the corresponding MAC addr filter
825 for (i = 0; i < bp->nr_vnics; i++) {
826 if (!(pool_mask & (1ULL << i)))
829 vnic = &bp->vnic_info[i];
830 filter = STAILQ_FIRST(&vnic->filter);
832 temp_filter = STAILQ_NEXT(filter, next);
833 if (filter->mac_index == index) {
834 STAILQ_REMOVE(&vnic->filter, filter,
835 bnxt_filter_info, next);
836 bnxt_hwrm_clear_l2_filter(bp, filter);
837 filter->mac_index = INVALID_MAC_INDEX;
838 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
839 STAILQ_INSERT_TAIL(&bp->free_filter_list,
842 filter = temp_filter;
847 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
848 struct rte_ether_addr *mac_addr,
849 uint32_t index, uint32_t pool)
851 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
852 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
853 struct bnxt_filter_info *filter;
855 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
856 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
861 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
864 /* Attach requested MAC address to the new l2_filter */
865 STAILQ_FOREACH(filter, &vnic->filter, next) {
866 if (filter->mac_index == index) {
868 "MAC addr already existed for pool %d\n", pool);
872 filter = bnxt_alloc_filter(bp);
874 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
877 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
878 filter->mac_index = index;
879 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
880 return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
883 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
886 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
887 struct rte_eth_link new;
888 unsigned int cnt = BNXT_LINK_WAIT_CNT;
890 memset(&new, 0, sizeof(new));
892 /* Retrieve link info from hardware */
893 rc = bnxt_get_hwrm_link_config(bp, &new);
895 new.link_speed = ETH_LINK_SPEED_100M;
896 new.link_duplex = ETH_LINK_FULL_DUPLEX;
898 "Failed to retrieve link rc = 0x%x!\n", rc);
901 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
903 if (!wait_to_complete)
905 } while (!new.link_status && cnt--);
908 /* Timed out or success */
909 if (new.link_status != eth_dev->data->dev_link.link_status ||
910 new.link_speed != eth_dev->data->dev_link.link_speed) {
911 memcpy(ð_dev->data->dev_link, &new,
912 sizeof(struct rte_eth_link));
914 _rte_eth_dev_callback_process(eth_dev,
915 RTE_ETH_EVENT_INTR_LSC,
918 bnxt_print_link_info(eth_dev);
924 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
926 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
927 struct bnxt_vnic_info *vnic;
929 if (bp->vnic_info == NULL)
932 vnic = &bp->vnic_info[0];
934 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
935 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
938 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
940 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
941 struct bnxt_vnic_info *vnic;
943 if (bp->vnic_info == NULL)
946 vnic = &bp->vnic_info[0];
948 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
949 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
952 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
954 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
955 struct bnxt_vnic_info *vnic;
957 if (bp->vnic_info == NULL)
960 vnic = &bp->vnic_info[0];
962 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
963 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
966 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
968 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
969 struct bnxt_vnic_info *vnic;
971 if (bp->vnic_info == NULL)
974 vnic = &bp->vnic_info[0];
976 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
977 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
980 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
981 struct rte_eth_rss_reta_entry64 *reta_conf,
984 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
985 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
986 struct bnxt_vnic_info *vnic;
989 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
992 if (reta_size != HW_HASH_INDEX_SIZE) {
993 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
994 "(%d) must equal the size supported by the hardware "
995 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
998 /* Update the RSS VNIC(s) */
999 for (i = 0; i < bp->max_vnics; i++) {
1000 vnic = &bp->vnic_info[i];
1001 memcpy(vnic->rss_table, reta_conf, reta_size);
1002 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1007 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1008 struct rte_eth_rss_reta_entry64 *reta_conf,
1011 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1012 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1013 struct rte_intr_handle *intr_handle
1014 = &bp->pdev->intr_handle;
1016 /* Retrieve from the default VNIC */
1019 if (!vnic->rss_table)
1022 if (reta_size != HW_HASH_INDEX_SIZE) {
1023 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1024 "(%d) must equal the size supported by the hardware "
1025 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
1028 /* EW - need to revisit here copying from uint64_t to uint16_t */
1029 memcpy(reta_conf, vnic->rss_table, reta_size);
1031 if (rte_intr_allow_others(intr_handle)) {
1032 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
1033 bnxt_dev_lsc_intr_setup(eth_dev);
1039 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1040 struct rte_eth_rss_conf *rss_conf)
1042 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1043 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1044 struct bnxt_vnic_info *vnic;
1045 uint16_t hash_type = 0;
1049 * If RSS enablement were different than dev_configure,
1050 * then return -EINVAL
1052 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1053 if (!rss_conf->rss_hf)
1054 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1056 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1060 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1061 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1063 if (rss_conf->rss_hf & ETH_RSS_IPV4)
1064 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1065 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1066 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1067 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1068 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1069 if (rss_conf->rss_hf & ETH_RSS_IPV6)
1070 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1071 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1072 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1073 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1074 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1076 /* Update the RSS VNIC(s) */
1077 for (i = 0; i < bp->nr_vnics; i++) {
1078 vnic = &bp->vnic_info[i];
1079 vnic->hash_type = hash_type;
1082 * Use the supplied key if the key length is
1083 * acceptable and the rss_key is not NULL
1085 if (rss_conf->rss_key &&
1086 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1087 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1088 rss_conf->rss_key_len);
1090 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1095 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1096 struct rte_eth_rss_conf *rss_conf)
1098 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1099 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1101 uint32_t hash_types;
1103 /* RSS configuration is the same for all VNICs */
1104 if (vnic && vnic->rss_hash_key) {
1105 if (rss_conf->rss_key) {
1106 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1107 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1108 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1111 hash_types = vnic->hash_type;
1112 rss_conf->rss_hf = 0;
1113 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1114 rss_conf->rss_hf |= ETH_RSS_IPV4;
1115 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1117 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1118 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1120 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1122 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1123 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1125 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1127 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1128 rss_conf->rss_hf |= ETH_RSS_IPV6;
1129 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1131 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1132 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1134 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1136 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1137 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1139 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1143 "Unknwon RSS config from firmware (%08x), RSS disabled",
1148 rss_conf->rss_hf = 0;
1153 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1154 struct rte_eth_fc_conf *fc_conf)
1156 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1157 struct rte_eth_link link_info;
1160 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1164 memset(fc_conf, 0, sizeof(*fc_conf));
1165 if (bp->link_info.auto_pause)
1166 fc_conf->autoneg = 1;
1167 switch (bp->link_info.pause) {
1169 fc_conf->mode = RTE_FC_NONE;
1171 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1172 fc_conf->mode = RTE_FC_TX_PAUSE;
1174 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1175 fc_conf->mode = RTE_FC_RX_PAUSE;
1177 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1178 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1179 fc_conf->mode = RTE_FC_FULL;
1185 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1186 struct rte_eth_fc_conf *fc_conf)
1188 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1190 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1191 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1195 switch (fc_conf->mode) {
1197 bp->link_info.auto_pause = 0;
1198 bp->link_info.force_pause = 0;
1200 case RTE_FC_RX_PAUSE:
1201 if (fc_conf->autoneg) {
1202 bp->link_info.auto_pause =
1203 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1204 bp->link_info.force_pause = 0;
1206 bp->link_info.auto_pause = 0;
1207 bp->link_info.force_pause =
1208 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1211 case RTE_FC_TX_PAUSE:
1212 if (fc_conf->autoneg) {
1213 bp->link_info.auto_pause =
1214 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1215 bp->link_info.force_pause = 0;
1217 bp->link_info.auto_pause = 0;
1218 bp->link_info.force_pause =
1219 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1223 if (fc_conf->autoneg) {
1224 bp->link_info.auto_pause =
1225 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1226 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1227 bp->link_info.force_pause = 0;
1229 bp->link_info.auto_pause = 0;
1230 bp->link_info.force_pause =
1231 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1232 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1236 return bnxt_set_hwrm_link_config(bp, true);
1239 /* Add UDP tunneling port */
1241 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1242 struct rte_eth_udp_tunnel *udp_tunnel)
1244 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1245 uint16_t tunnel_type = 0;
1248 switch (udp_tunnel->prot_type) {
1249 case RTE_TUNNEL_TYPE_VXLAN:
1250 if (bp->vxlan_port_cnt) {
1251 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1252 udp_tunnel->udp_port);
1253 if (bp->vxlan_port != udp_tunnel->udp_port) {
1254 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1257 bp->vxlan_port_cnt++;
1261 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1262 bp->vxlan_port_cnt++;
1264 case RTE_TUNNEL_TYPE_GENEVE:
1265 if (bp->geneve_port_cnt) {
1266 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1267 udp_tunnel->udp_port);
1268 if (bp->geneve_port != udp_tunnel->udp_port) {
1269 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1272 bp->geneve_port_cnt++;
1276 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1277 bp->geneve_port_cnt++;
1280 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1283 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1289 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1290 struct rte_eth_udp_tunnel *udp_tunnel)
1292 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1293 uint16_t tunnel_type = 0;
1297 switch (udp_tunnel->prot_type) {
1298 case RTE_TUNNEL_TYPE_VXLAN:
1299 if (!bp->vxlan_port_cnt) {
1300 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1303 if (bp->vxlan_port != udp_tunnel->udp_port) {
1304 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1305 udp_tunnel->udp_port, bp->vxlan_port);
1308 if (--bp->vxlan_port_cnt)
1312 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1313 port = bp->vxlan_fw_dst_port_id;
1315 case RTE_TUNNEL_TYPE_GENEVE:
1316 if (!bp->geneve_port_cnt) {
1317 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1320 if (bp->geneve_port != udp_tunnel->udp_port) {
1321 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1322 udp_tunnel->udp_port, bp->geneve_port);
1325 if (--bp->geneve_port_cnt)
1329 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1330 port = bp->geneve_fw_dst_port_id;
1333 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1337 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1340 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1343 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1344 bp->geneve_port = 0;
1349 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1351 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1352 struct bnxt_vnic_info *vnic;
1355 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1357 /* Cycle through all VNICs */
1358 for (i = 0; i < bp->nr_vnics; i++) {
1360 * For each VNIC and each associated filter(s)
1361 * if VLAN exists && VLAN matches vlan_id
1362 * remove the MAC+VLAN filter
1363 * add a new MAC only filter
1365 * VLAN filter doesn't exist, just skip and continue
1367 vnic = &bp->vnic_info[i];
1368 filter = STAILQ_FIRST(&vnic->filter);
1370 temp_filter = STAILQ_NEXT(filter, next);
1372 if (filter->enables & chk &&
1373 filter->l2_ovlan == vlan_id) {
1374 /* Must delete the filter */
1375 STAILQ_REMOVE(&vnic->filter, filter,
1376 bnxt_filter_info, next);
1377 bnxt_hwrm_clear_l2_filter(bp, filter);
1378 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1382 * Need to examine to see if the MAC
1383 * filter already existed or not before
1384 * allocating a new one
1387 new_filter = bnxt_alloc_filter(bp);
1390 "MAC/VLAN filter alloc failed\n");
1394 STAILQ_INSERT_TAIL(&vnic->filter,
1396 /* Inherit MAC from previous filter */
1397 new_filter->mac_index =
1399 memcpy(new_filter->l2_addr, filter->l2_addr,
1400 RTE_ETHER_ADDR_LEN);
1401 /* MAC only filter */
1402 rc = bnxt_hwrm_set_l2_filter(bp,
1408 "Del Vlan filter for %d\n",
1411 filter = temp_filter;
1418 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1420 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1421 struct bnxt_vnic_info *vnic;
1424 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1425 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1426 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1428 /* Cycle through all VNICs */
1429 for (i = 0; i < bp->nr_vnics; i++) {
1431 * For each VNIC and each associated filter(s)
1433 * if VLAN matches vlan_id
1434 * VLAN filter already exists, just skip and continue
1436 * add a new MAC+VLAN filter
1438 * Remove the old MAC only filter
1439 * Add a new MAC+VLAN filter
1441 vnic = &bp->vnic_info[i];
1442 filter = STAILQ_FIRST(&vnic->filter);
1444 temp_filter = STAILQ_NEXT(filter, next);
1446 if (filter->enables & chk) {
1447 if (filter->l2_ivlan == vlan_id)
1450 /* Must delete the MAC filter */
1451 STAILQ_REMOVE(&vnic->filter, filter,
1452 bnxt_filter_info, next);
1453 bnxt_hwrm_clear_l2_filter(bp, filter);
1454 filter->l2_ovlan = 0;
1455 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1458 new_filter = bnxt_alloc_filter(bp);
1461 "MAC/VLAN filter alloc failed\n");
1465 STAILQ_INSERT_TAIL(&vnic->filter, new_filter, next);
1466 /* Inherit MAC from the previous filter */
1467 new_filter->mac_index = filter->mac_index;
1468 memcpy(new_filter->l2_addr, filter->l2_addr,
1469 RTE_ETHER_ADDR_LEN);
1470 /* MAC + VLAN ID filter */
1471 new_filter->l2_ivlan = vlan_id;
1472 new_filter->l2_ivlan_mask = 0xF000;
1473 new_filter->enables |= en;
1474 rc = bnxt_hwrm_set_l2_filter(bp,
1480 "Added Vlan filter for %d\n", vlan_id);
1482 filter = temp_filter;
1489 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1490 uint16_t vlan_id, int on)
1492 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1494 /* These operations apply to ALL existing MAC/VLAN filters */
1496 return bnxt_add_vlan_filter(bp, vlan_id);
1498 return bnxt_del_vlan_filter(bp, vlan_id);
1502 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1504 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1505 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1508 if (mask & ETH_VLAN_FILTER_MASK) {
1509 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1510 /* Remove any VLAN filters programmed */
1511 for (i = 0; i < 4095; i++)
1512 bnxt_del_vlan_filter(bp, i);
1514 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1515 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1518 if (mask & ETH_VLAN_STRIP_MASK) {
1519 /* Enable or disable VLAN stripping */
1520 for (i = 0; i < bp->nr_vnics; i++) {
1521 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1522 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1523 vnic->vlan_strip = true;
1525 vnic->vlan_strip = false;
1526 bnxt_hwrm_vnic_cfg(bp, vnic);
1528 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1529 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1532 if (mask & ETH_VLAN_EXTEND_MASK)
1533 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1539 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1540 struct rte_ether_addr *addr)
1542 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1543 /* Default Filter is tied to VNIC 0 */
1544 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1545 struct bnxt_filter_info *filter;
1548 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1551 memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1553 STAILQ_FOREACH(filter, &vnic->filter, next) {
1554 /* Default Filter is at Index 0 */
1555 if (filter->mac_index != 0)
1557 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1560 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1561 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1562 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1564 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1565 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1566 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1569 filter->mac_index = 0;
1570 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1577 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1578 struct rte_ether_addr *mc_addr_set,
1579 uint32_t nb_mc_addr)
1581 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1582 char *mc_addr_list = (char *)mc_addr_set;
1583 struct bnxt_vnic_info *vnic;
1584 uint32_t off = 0, i = 0;
1586 vnic = &bp->vnic_info[0];
1588 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1589 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1593 /* TODO Check for Duplicate mcast addresses */
1594 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1595 for (i = 0; i < nb_mc_addr; i++) {
1596 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1597 RTE_ETHER_ADDR_LEN);
1598 off += RTE_ETHER_ADDR_LEN;
1601 vnic->mc_addr_cnt = i;
1604 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1608 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1610 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1611 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1612 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1613 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1616 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1617 fw_major, fw_minor, fw_updt);
1619 ret += 1; /* add the size of '\0' */
1620 if (fw_size < (uint32_t)ret)
1627 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1628 struct rte_eth_rxq_info *qinfo)
1630 struct bnxt_rx_queue *rxq;
1632 rxq = dev->data->rx_queues[queue_id];
1634 qinfo->mp = rxq->mb_pool;
1635 qinfo->scattered_rx = dev->data->scattered_rx;
1636 qinfo->nb_desc = rxq->nb_rx_desc;
1638 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1639 qinfo->conf.rx_drop_en = 0;
1640 qinfo->conf.rx_deferred_start = 0;
1644 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1645 struct rte_eth_txq_info *qinfo)
1647 struct bnxt_tx_queue *txq;
1649 txq = dev->data->tx_queues[queue_id];
1651 qinfo->nb_desc = txq->nb_tx_desc;
1653 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1654 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1655 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1657 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1658 qinfo->conf.tx_rs_thresh = 0;
1659 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1662 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1664 struct bnxt *bp = eth_dev->data->dev_private;
1665 struct rte_eth_dev_info dev_info;
1666 uint32_t new_pkt_size;
1670 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1671 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1673 bnxt_dev_info_get_op(eth_dev, &dev_info);
1675 if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1676 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1677 RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1683 * If vector-mode tx/rx is active, disallow any MTU change that would
1684 * require scattered receive support.
1686 if (eth_dev->data->dev_started &&
1687 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1688 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1690 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1692 "MTU change would require scattered rx support. ");
1693 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
1698 if (new_mtu > RTE_ETHER_MTU) {
1699 bp->flags |= BNXT_FLAG_JUMBO;
1700 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1701 DEV_RX_OFFLOAD_JUMBO_FRAME;
1703 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1704 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1705 bp->flags &= ~BNXT_FLAG_JUMBO;
1708 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
1710 eth_dev->data->mtu = new_mtu;
1711 PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1713 for (i = 0; i < bp->nr_vnics; i++) {
1714 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1717 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1718 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1719 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1723 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1724 size -= RTE_PKTMBUF_HEADROOM;
1726 if (size < new_mtu) {
1727 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1737 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1739 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1740 uint16_t vlan = bp->vlan;
1743 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1745 "PVID cannot be modified for this function\n");
1748 bp->vlan = on ? pvid : 0;
1750 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1757 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1759 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1761 return bnxt_hwrm_port_led_cfg(bp, true);
1765 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1767 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1769 return bnxt_hwrm_port_led_cfg(bp, false);
1773 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1775 uint32_t desc = 0, raw_cons = 0, cons;
1776 struct bnxt_cp_ring_info *cpr;
1777 struct bnxt_rx_queue *rxq;
1778 struct rx_pkt_cmpl *rxcmp;
1783 rxq = dev->data->rx_queues[rx_queue_id];
1787 while (raw_cons < rxq->nb_rx_desc) {
1788 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1789 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1791 if (!CMPL_VALID(rxcmp, valid))
1793 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1794 cmp_type = CMP_TYPE(rxcmp);
1795 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1796 cmp = (rte_le_to_cpu_32(
1797 ((struct rx_tpa_end_cmpl *)
1798 (rxcmp))->agg_bufs_v1) &
1799 RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1800 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1802 } else if (cmp_type == 0x11) {
1804 cmp = (rxcmp->agg_bufs_v1 &
1805 RX_PKT_CMPL_AGG_BUFS_MASK) >>
1806 RX_PKT_CMPL_AGG_BUFS_SFT;
1811 raw_cons += cmp ? cmp : 2;
1818 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1820 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1821 struct bnxt_rx_ring_info *rxr;
1822 struct bnxt_cp_ring_info *cpr;
1823 struct bnxt_sw_rx_bd *rx_buf;
1824 struct rx_pkt_cmpl *rxcmp;
1825 uint32_t cons, cp_cons;
1833 if (offset >= rxq->nb_rx_desc)
1836 cons = RING_CMP(cpr->cp_ring_struct, offset);
1837 cp_cons = cpr->cp_raw_cons;
1838 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1840 if (cons > cp_cons) {
1841 if (CMPL_VALID(rxcmp, cpr->valid))
1842 return RTE_ETH_RX_DESC_DONE;
1844 if (CMPL_VALID(rxcmp, !cpr->valid))
1845 return RTE_ETH_RX_DESC_DONE;
1847 rx_buf = &rxr->rx_buf_ring[cons];
1848 if (rx_buf->mbuf == NULL)
1849 return RTE_ETH_RX_DESC_UNAVAIL;
1852 return RTE_ETH_RX_DESC_AVAIL;
1856 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1858 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1859 struct bnxt_tx_ring_info *txr;
1860 struct bnxt_cp_ring_info *cpr;
1861 struct bnxt_sw_tx_bd *tx_buf;
1862 struct tx_pkt_cmpl *txcmp;
1863 uint32_t cons, cp_cons;
1871 if (offset >= txq->nb_tx_desc)
1874 cons = RING_CMP(cpr->cp_ring_struct, offset);
1875 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1876 cp_cons = cpr->cp_raw_cons;
1878 if (cons > cp_cons) {
1879 if (CMPL_VALID(txcmp, cpr->valid))
1880 return RTE_ETH_TX_DESC_UNAVAIL;
1882 if (CMPL_VALID(txcmp, !cpr->valid))
1883 return RTE_ETH_TX_DESC_UNAVAIL;
1885 tx_buf = &txr->tx_buf_ring[cons];
1886 if (tx_buf->mbuf == NULL)
1887 return RTE_ETH_TX_DESC_DONE;
1889 return RTE_ETH_TX_DESC_FULL;
1892 static struct bnxt_filter_info *
1893 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1894 struct rte_eth_ethertype_filter *efilter,
1895 struct bnxt_vnic_info *vnic0,
1896 struct bnxt_vnic_info *vnic,
1899 struct bnxt_filter_info *mfilter = NULL;
1903 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
1904 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
1905 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
1906 " ethertype filter.", efilter->ether_type);
1910 if (efilter->queue >= bp->rx_nr_rings) {
1911 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1916 vnic0 = &bp->vnic_info[0];
1917 vnic = &bp->vnic_info[efilter->queue];
1919 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1924 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1925 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1926 if ((!memcmp(efilter->mac_addr.addr_bytes,
1927 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
1929 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1930 mfilter->ethertype == efilter->ether_type)) {
1936 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1937 if ((!memcmp(efilter->mac_addr.addr_bytes,
1938 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
1939 mfilter->ethertype == efilter->ether_type &&
1941 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
1955 bnxt_ethertype_filter(struct rte_eth_dev *dev,
1956 enum rte_filter_op filter_op,
1959 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1960 struct rte_eth_ethertype_filter *efilter =
1961 (struct rte_eth_ethertype_filter *)arg;
1962 struct bnxt_filter_info *bfilter, *filter1;
1963 struct bnxt_vnic_info *vnic, *vnic0;
1966 if (filter_op == RTE_ETH_FILTER_NOP)
1970 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
1975 vnic0 = &bp->vnic_info[0];
1976 vnic = &bp->vnic_info[efilter->queue];
1978 switch (filter_op) {
1979 case RTE_ETH_FILTER_ADD:
1980 bnxt_match_and_validate_ether_filter(bp, efilter,
1985 bfilter = bnxt_get_unused_filter(bp);
1986 if (bfilter == NULL) {
1988 "Not enough resources for a new filter.\n");
1991 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
1992 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
1993 RTE_ETHER_ADDR_LEN);
1994 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
1995 RTE_ETHER_ADDR_LEN);
1996 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
1997 bfilter->ethertype = efilter->ether_type;
1998 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2000 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2001 if (filter1 == NULL) {
2006 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2007 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2009 bfilter->dst_id = vnic->fw_vnic_id;
2011 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2013 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2016 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2019 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2021 case RTE_ETH_FILTER_DELETE:
2022 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2024 if (ret == -EEXIST) {
2025 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2027 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2029 bnxt_free_filter(bp, filter1);
2030 } else if (ret == 0) {
2031 PMD_DRV_LOG(ERR, "No matching filter found\n");
2035 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2041 bnxt_free_filter(bp, bfilter);
2047 parse_ntuple_filter(struct bnxt *bp,
2048 struct rte_eth_ntuple_filter *nfilter,
2049 struct bnxt_filter_info *bfilter)
2053 if (nfilter->queue >= bp->rx_nr_rings) {
2054 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2058 switch (nfilter->dst_port_mask) {
2060 bfilter->dst_port_mask = -1;
2061 bfilter->dst_port = nfilter->dst_port;
2062 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2063 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2066 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2070 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2071 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2073 switch (nfilter->proto_mask) {
2075 if (nfilter->proto == 17) /* IPPROTO_UDP */
2076 bfilter->ip_protocol = 17;
2077 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2078 bfilter->ip_protocol = 6;
2081 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2084 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2088 switch (nfilter->dst_ip_mask) {
2090 bfilter->dst_ipaddr_mask[0] = -1;
2091 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2092 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2093 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2096 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2100 switch (nfilter->src_ip_mask) {
2102 bfilter->src_ipaddr_mask[0] = -1;
2103 bfilter->src_ipaddr[0] = nfilter->src_ip;
2104 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2105 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2108 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2112 switch (nfilter->src_port_mask) {
2114 bfilter->src_port_mask = -1;
2115 bfilter->src_port = nfilter->src_port;
2116 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2117 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2120 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2125 //nfilter->priority = (uint8_t)filter->priority;
2127 bfilter->enables = en;
2131 static struct bnxt_filter_info*
2132 bnxt_match_ntuple_filter(struct bnxt *bp,
2133 struct bnxt_filter_info *bfilter,
2134 struct bnxt_vnic_info **mvnic)
2136 struct bnxt_filter_info *mfilter = NULL;
2139 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2140 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2141 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2142 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2143 bfilter->src_ipaddr_mask[0] ==
2144 mfilter->src_ipaddr_mask[0] &&
2145 bfilter->src_port == mfilter->src_port &&
2146 bfilter->src_port_mask == mfilter->src_port_mask &&
2147 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2148 bfilter->dst_ipaddr_mask[0] ==
2149 mfilter->dst_ipaddr_mask[0] &&
2150 bfilter->dst_port == mfilter->dst_port &&
2151 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2152 bfilter->flags == mfilter->flags &&
2153 bfilter->enables == mfilter->enables) {
2164 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2165 struct rte_eth_ntuple_filter *nfilter,
2166 enum rte_filter_op filter_op)
2168 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2169 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2172 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2173 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2177 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2178 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2182 bfilter = bnxt_get_unused_filter(bp);
2183 if (bfilter == NULL) {
2185 "Not enough resources for a new filter.\n");
2188 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2192 vnic = &bp->vnic_info[nfilter->queue];
2193 vnic0 = &bp->vnic_info[0];
2194 filter1 = STAILQ_FIRST(&vnic0->filter);
2195 if (filter1 == NULL) {
2200 bfilter->dst_id = vnic->fw_vnic_id;
2201 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2203 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2204 bfilter->ethertype = 0x800;
2205 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2207 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2209 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2210 bfilter->dst_id == mfilter->dst_id) {
2211 PMD_DRV_LOG(ERR, "filter exists.\n");
2214 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2215 bfilter->dst_id != mfilter->dst_id) {
2216 mfilter->dst_id = vnic->fw_vnic_id;
2217 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2218 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2219 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2220 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2221 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2224 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2225 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2230 if (filter_op == RTE_ETH_FILTER_ADD) {
2231 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2232 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2235 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2237 if (mfilter == NULL) {
2238 /* This should not happen. But for Coverity! */
2242 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2244 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2245 bnxt_free_filter(bp, mfilter);
2246 mfilter->fw_l2_filter_id = -1;
2247 bnxt_free_filter(bp, bfilter);
2248 bfilter->fw_l2_filter_id = -1;
2253 bfilter->fw_l2_filter_id = -1;
2254 bnxt_free_filter(bp, bfilter);
2259 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2260 enum rte_filter_op filter_op,
2263 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2266 if (filter_op == RTE_ETH_FILTER_NOP)
2270 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2275 switch (filter_op) {
2276 case RTE_ETH_FILTER_ADD:
2277 ret = bnxt_cfg_ntuple_filter(bp,
2278 (struct rte_eth_ntuple_filter *)arg,
2281 case RTE_ETH_FILTER_DELETE:
2282 ret = bnxt_cfg_ntuple_filter(bp,
2283 (struct rte_eth_ntuple_filter *)arg,
2287 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2295 bnxt_parse_fdir_filter(struct bnxt *bp,
2296 struct rte_eth_fdir_filter *fdir,
2297 struct bnxt_filter_info *filter)
2299 enum rte_fdir_mode fdir_mode =
2300 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2301 struct bnxt_vnic_info *vnic0, *vnic;
2302 struct bnxt_filter_info *filter1;
2306 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2309 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2310 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2312 switch (fdir->input.flow_type) {
2313 case RTE_ETH_FLOW_IPV4:
2314 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2316 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2317 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2318 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2319 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2320 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2321 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2322 filter->ip_addr_type =
2323 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2324 filter->src_ipaddr_mask[0] = 0xffffffff;
2325 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2326 filter->dst_ipaddr_mask[0] = 0xffffffff;
2327 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2328 filter->ethertype = 0x800;
2329 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2331 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2332 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2333 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2334 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2335 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2336 filter->dst_port_mask = 0xffff;
2337 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2338 filter->src_port_mask = 0xffff;
2339 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2340 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2341 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2342 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2343 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2344 filter->ip_protocol = 6;
2345 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2346 filter->ip_addr_type =
2347 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2348 filter->src_ipaddr_mask[0] = 0xffffffff;
2349 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2350 filter->dst_ipaddr_mask[0] = 0xffffffff;
2351 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2352 filter->ethertype = 0x800;
2353 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2355 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2356 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2357 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2358 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2359 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2360 filter->dst_port_mask = 0xffff;
2361 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2362 filter->src_port_mask = 0xffff;
2363 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2364 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2365 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2366 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2367 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2368 filter->ip_protocol = 17;
2369 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2370 filter->ip_addr_type =
2371 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2372 filter->src_ipaddr_mask[0] = 0xffffffff;
2373 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2374 filter->dst_ipaddr_mask[0] = 0xffffffff;
2375 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2376 filter->ethertype = 0x800;
2377 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2379 case RTE_ETH_FLOW_IPV6:
2380 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2382 filter->ip_addr_type =
2383 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2384 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2385 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2386 rte_memcpy(filter->src_ipaddr,
2387 fdir->input.flow.ipv6_flow.src_ip, 16);
2388 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2389 rte_memcpy(filter->dst_ipaddr,
2390 fdir->input.flow.ipv6_flow.dst_ip, 16);
2391 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2392 memset(filter->dst_ipaddr_mask, 0xff, 16);
2393 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2394 memset(filter->src_ipaddr_mask, 0xff, 16);
2395 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2396 filter->ethertype = 0x86dd;
2397 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2399 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2400 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2401 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2402 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2403 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2404 filter->dst_port_mask = 0xffff;
2405 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2406 filter->src_port_mask = 0xffff;
2407 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2408 filter->ip_addr_type =
2409 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2410 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2411 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2412 rte_memcpy(filter->src_ipaddr,
2413 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2414 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2415 rte_memcpy(filter->dst_ipaddr,
2416 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2417 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2418 memset(filter->dst_ipaddr_mask, 0xff, 16);
2419 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2420 memset(filter->src_ipaddr_mask, 0xff, 16);
2421 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2422 filter->ethertype = 0x86dd;
2423 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2425 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2426 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2427 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2428 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2429 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2430 filter->dst_port_mask = 0xffff;
2431 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2432 filter->src_port_mask = 0xffff;
2433 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2434 filter->ip_addr_type =
2435 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2436 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2437 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2438 rte_memcpy(filter->src_ipaddr,
2439 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2440 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2441 rte_memcpy(filter->dst_ipaddr,
2442 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2443 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2444 memset(filter->dst_ipaddr_mask, 0xff, 16);
2445 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2446 memset(filter->src_ipaddr_mask, 0xff, 16);
2447 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2448 filter->ethertype = 0x86dd;
2449 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2451 case RTE_ETH_FLOW_L2_PAYLOAD:
2452 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2453 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2455 case RTE_ETH_FLOW_VXLAN:
2456 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2458 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2459 filter->tunnel_type =
2460 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2461 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2463 case RTE_ETH_FLOW_NVGRE:
2464 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2466 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2467 filter->tunnel_type =
2468 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2469 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2471 case RTE_ETH_FLOW_UNKNOWN:
2472 case RTE_ETH_FLOW_RAW:
2473 case RTE_ETH_FLOW_FRAG_IPV4:
2474 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2475 case RTE_ETH_FLOW_FRAG_IPV6:
2476 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2477 case RTE_ETH_FLOW_IPV6_EX:
2478 case RTE_ETH_FLOW_IPV6_TCP_EX:
2479 case RTE_ETH_FLOW_IPV6_UDP_EX:
2480 case RTE_ETH_FLOW_GENEVE:
2486 vnic0 = &bp->vnic_info[0];
2487 vnic = &bp->vnic_info[fdir->action.rx_queue];
2489 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2494 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2495 rte_memcpy(filter->dst_macaddr,
2496 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2497 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2500 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2501 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2502 filter1 = STAILQ_FIRST(&vnic0->filter);
2503 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2505 filter->dst_id = vnic->fw_vnic_id;
2506 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2507 if (filter->dst_macaddr[i] == 0x00)
2508 filter1 = STAILQ_FIRST(&vnic0->filter);
2510 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2513 if (filter1 == NULL)
2516 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2517 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2519 filter->enables = en;
2524 static struct bnxt_filter_info *
2525 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2526 struct bnxt_vnic_info **mvnic)
2528 struct bnxt_filter_info *mf = NULL;
2531 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2532 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2534 STAILQ_FOREACH(mf, &vnic->filter, next) {
2535 if (mf->filter_type == nf->filter_type &&
2536 mf->flags == nf->flags &&
2537 mf->src_port == nf->src_port &&
2538 mf->src_port_mask == nf->src_port_mask &&
2539 mf->dst_port == nf->dst_port &&
2540 mf->dst_port_mask == nf->dst_port_mask &&
2541 mf->ip_protocol == nf->ip_protocol &&
2542 mf->ip_addr_type == nf->ip_addr_type &&
2543 mf->ethertype == nf->ethertype &&
2544 mf->vni == nf->vni &&
2545 mf->tunnel_type == nf->tunnel_type &&
2546 mf->l2_ovlan == nf->l2_ovlan &&
2547 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2548 mf->l2_ivlan == nf->l2_ivlan &&
2549 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2550 !memcmp(mf->l2_addr, nf->l2_addr,
2551 RTE_ETHER_ADDR_LEN) &&
2552 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2553 RTE_ETHER_ADDR_LEN) &&
2554 !memcmp(mf->src_macaddr, nf->src_macaddr,
2555 RTE_ETHER_ADDR_LEN) &&
2556 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2557 RTE_ETHER_ADDR_LEN) &&
2558 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2559 sizeof(nf->src_ipaddr)) &&
2560 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2561 sizeof(nf->src_ipaddr_mask)) &&
2562 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2563 sizeof(nf->dst_ipaddr)) &&
2564 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2565 sizeof(nf->dst_ipaddr_mask))) {
2576 bnxt_fdir_filter(struct rte_eth_dev *dev,
2577 enum rte_filter_op filter_op,
2580 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2581 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2582 struct bnxt_filter_info *filter, *match;
2583 struct bnxt_vnic_info *vnic, *mvnic;
2586 if (filter_op == RTE_ETH_FILTER_NOP)
2589 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2592 switch (filter_op) {
2593 case RTE_ETH_FILTER_ADD:
2594 case RTE_ETH_FILTER_DELETE:
2596 filter = bnxt_get_unused_filter(bp);
2597 if (filter == NULL) {
2599 "Not enough resources for a new flow.\n");
2603 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2606 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2608 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2609 vnic = &bp->vnic_info[0];
2611 vnic = &bp->vnic_info[fdir->action.rx_queue];
2613 match = bnxt_match_fdir(bp, filter, &mvnic);
2614 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2615 if (match->dst_id == vnic->fw_vnic_id) {
2616 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2620 match->dst_id = vnic->fw_vnic_id;
2621 ret = bnxt_hwrm_set_ntuple_filter(bp,
2624 STAILQ_REMOVE(&mvnic->filter, match,
2625 bnxt_filter_info, next);
2626 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2628 "Filter with matching pattern exist\n");
2630 "Updated it to new destination q\n");
2634 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2635 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2640 if (filter_op == RTE_ETH_FILTER_ADD) {
2641 ret = bnxt_hwrm_set_ntuple_filter(bp,
2646 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2648 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2649 STAILQ_REMOVE(&vnic->filter, match,
2650 bnxt_filter_info, next);
2651 bnxt_free_filter(bp, match);
2652 filter->fw_l2_filter_id = -1;
2653 bnxt_free_filter(bp, filter);
2656 case RTE_ETH_FILTER_FLUSH:
2657 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2658 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2660 STAILQ_FOREACH(filter, &vnic->filter, next) {
2661 if (filter->filter_type ==
2662 HWRM_CFA_NTUPLE_FILTER) {
2664 bnxt_hwrm_clear_ntuple_filter(bp,
2666 STAILQ_REMOVE(&vnic->filter, filter,
2667 bnxt_filter_info, next);
2672 case RTE_ETH_FILTER_UPDATE:
2673 case RTE_ETH_FILTER_STATS:
2674 case RTE_ETH_FILTER_INFO:
2675 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2678 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2685 filter->fw_l2_filter_id = -1;
2686 bnxt_free_filter(bp, filter);
2691 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2692 enum rte_filter_type filter_type,
2693 enum rte_filter_op filter_op, void *arg)
2697 switch (filter_type) {
2698 case RTE_ETH_FILTER_TUNNEL:
2700 "filter type: %d: To be implemented\n", filter_type);
2702 case RTE_ETH_FILTER_FDIR:
2703 ret = bnxt_fdir_filter(dev, filter_op, arg);
2705 case RTE_ETH_FILTER_NTUPLE:
2706 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2708 case RTE_ETH_FILTER_ETHERTYPE:
2709 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2711 case RTE_ETH_FILTER_GENERIC:
2712 if (filter_op != RTE_ETH_FILTER_GET)
2714 *(const void **)arg = &bnxt_flow_ops;
2718 "Filter type (%d) not supported", filter_type);
2725 static const uint32_t *
2726 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2728 static const uint32_t ptypes[] = {
2729 RTE_PTYPE_L2_ETHER_VLAN,
2730 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2731 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2735 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2736 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2737 RTE_PTYPE_INNER_L4_ICMP,
2738 RTE_PTYPE_INNER_L4_TCP,
2739 RTE_PTYPE_INNER_L4_UDP,
2743 if (!dev->rx_pkt_burst)
2749 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2752 uint32_t reg_base = *reg_arr & 0xfffff000;
2756 for (i = 0; i < count; i++) {
2757 if ((reg_arr[i] & 0xfffff000) != reg_base)
2760 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2761 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
2765 static int bnxt_map_ptp_regs(struct bnxt *bp)
2767 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2771 reg_arr = ptp->rx_regs;
2772 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2776 reg_arr = ptp->tx_regs;
2777 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2781 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2782 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2784 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2785 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2790 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2792 rte_write32(0, (uint8_t *)bp->bar0 +
2793 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
2794 rte_write32(0, (uint8_t *)bp->bar0 +
2795 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
2798 static uint64_t bnxt_cc_read(struct bnxt *bp)
2802 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2803 BNXT_GRCPF_REG_SYNC_TIME));
2804 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2805 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2809 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2811 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2814 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2815 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2816 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2819 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2820 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2821 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2822 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2823 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2824 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2829 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2831 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2832 struct bnxt_pf_info *pf = &bp->pf;
2839 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2840 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2841 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2844 port_id = pf->port_id;
2845 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2846 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
2848 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2849 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2850 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2851 /* bnxt_clr_rx_ts(bp); TBD */
2855 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2856 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2857 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2858 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2864 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2867 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2868 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2873 ns = rte_timespec_to_ns(ts);
2874 /* Set the timecounters to a new value. */
2881 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2883 uint64_t ns, systime_cycles;
2884 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2885 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2890 systime_cycles = bnxt_cc_read(bp);
2891 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
2892 *ts = rte_ns_to_timespec(ns);
2897 bnxt_timesync_enable(struct rte_eth_dev *dev)
2899 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2900 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2907 ptp->tx_tstamp_en = 1;
2908 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
2910 if (!bnxt_hwrm_ptp_cfg(bp))
2911 bnxt_map_ptp_regs(bp);
2913 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
2914 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2915 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2917 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2918 ptp->tc.cc_shift = shift;
2919 ptp->tc.nsec_mask = (1ULL << shift) - 1;
2921 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2922 ptp->rx_tstamp_tc.cc_shift = shift;
2923 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2925 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2926 ptp->tx_tstamp_tc.cc_shift = shift;
2927 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2933 bnxt_timesync_disable(struct rte_eth_dev *dev)
2935 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2936 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2942 ptp->tx_tstamp_en = 0;
2945 bnxt_hwrm_ptp_cfg(bp);
2947 bnxt_unmap_ptp_regs(bp);
2953 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
2954 struct timespec *timestamp,
2955 uint32_t flags __rte_unused)
2957 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2958 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2959 uint64_t rx_tstamp_cycles = 0;
2965 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
2966 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
2967 *timestamp = rte_ns_to_timespec(ns);
2972 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
2973 struct timespec *timestamp)
2975 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2976 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2977 uint64_t tx_tstamp_cycles = 0;
2983 bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
2984 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
2985 *timestamp = rte_ns_to_timespec(ns);
2991 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
2993 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2994 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2999 ptp->tc.nsec += delta;
3005 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3007 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3009 uint32_t dir_entries;
3010 uint32_t entry_length;
3012 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3013 bp->pdev->addr.domain, bp->pdev->addr.bus,
3014 bp->pdev->addr.devid, bp->pdev->addr.function);
3016 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3020 return dir_entries * entry_length;
3024 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3025 struct rte_dev_eeprom_info *in_eeprom)
3027 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3031 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3032 "len = %d\n", bp->pdev->addr.domain,
3033 bp->pdev->addr.bus, bp->pdev->addr.devid,
3034 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3036 if (in_eeprom->offset == 0) /* special offset value to get directory */
3037 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3040 index = in_eeprom->offset >> 24;
3041 offset = in_eeprom->offset & 0xffffff;
3044 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3045 in_eeprom->length, in_eeprom->data);
3050 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3053 case BNX_DIR_TYPE_CHIMP_PATCH:
3054 case BNX_DIR_TYPE_BOOTCODE:
3055 case BNX_DIR_TYPE_BOOTCODE_2:
3056 case BNX_DIR_TYPE_APE_FW:
3057 case BNX_DIR_TYPE_APE_PATCH:
3058 case BNX_DIR_TYPE_KONG_FW:
3059 case BNX_DIR_TYPE_KONG_PATCH:
3060 case BNX_DIR_TYPE_BONO_FW:
3061 case BNX_DIR_TYPE_BONO_PATCH:
3069 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3072 case BNX_DIR_TYPE_AVS:
3073 case BNX_DIR_TYPE_EXP_ROM_MBA:
3074 case BNX_DIR_TYPE_PCIE:
3075 case BNX_DIR_TYPE_TSCF_UCODE:
3076 case BNX_DIR_TYPE_EXT_PHY:
3077 case BNX_DIR_TYPE_CCM:
3078 case BNX_DIR_TYPE_ISCSI_BOOT:
3079 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3080 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3088 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3090 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3091 bnxt_dir_type_is_other_exec_format(dir_type);
3095 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3096 struct rte_dev_eeprom_info *in_eeprom)
3098 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3099 uint8_t index, dir_op;
3100 uint16_t type, ext, ordinal, attr;
3102 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3103 "len = %d\n", bp->pdev->addr.domain,
3104 bp->pdev->addr.bus, bp->pdev->addr.devid,
3105 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3108 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3112 type = in_eeprom->magic >> 16;
3114 if (type == 0xffff) { /* special value for directory operations */
3115 index = in_eeprom->magic & 0xff;
3116 dir_op = in_eeprom->magic >> 8;
3120 case 0x0e: /* erase */
3121 if (in_eeprom->offset != ~in_eeprom->magic)
3123 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3129 /* Create or re-write an NVM item: */
3130 if (bnxt_dir_type_is_executable(type) == true)
3132 ext = in_eeprom->magic & 0xffff;
3133 ordinal = in_eeprom->offset >> 16;
3134 attr = in_eeprom->offset & 0xffff;
3136 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3137 in_eeprom->data, in_eeprom->length);
3145 static const struct eth_dev_ops bnxt_dev_ops = {
3146 .dev_infos_get = bnxt_dev_info_get_op,
3147 .dev_close = bnxt_dev_close_op,
3148 .dev_configure = bnxt_dev_configure_op,
3149 .dev_start = bnxt_dev_start_op,
3150 .dev_stop = bnxt_dev_stop_op,
3151 .dev_set_link_up = bnxt_dev_set_link_up_op,
3152 .dev_set_link_down = bnxt_dev_set_link_down_op,
3153 .stats_get = bnxt_stats_get_op,
3154 .stats_reset = bnxt_stats_reset_op,
3155 .rx_queue_setup = bnxt_rx_queue_setup_op,
3156 .rx_queue_release = bnxt_rx_queue_release_op,
3157 .tx_queue_setup = bnxt_tx_queue_setup_op,
3158 .tx_queue_release = bnxt_tx_queue_release_op,
3159 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3160 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3161 .reta_update = bnxt_reta_update_op,
3162 .reta_query = bnxt_reta_query_op,
3163 .rss_hash_update = bnxt_rss_hash_update_op,
3164 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3165 .link_update = bnxt_link_update_op,
3166 .promiscuous_enable = bnxt_promiscuous_enable_op,
3167 .promiscuous_disable = bnxt_promiscuous_disable_op,
3168 .allmulticast_enable = bnxt_allmulticast_enable_op,
3169 .allmulticast_disable = bnxt_allmulticast_disable_op,
3170 .mac_addr_add = bnxt_mac_addr_add_op,
3171 .mac_addr_remove = bnxt_mac_addr_remove_op,
3172 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3173 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3174 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3175 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3176 .vlan_filter_set = bnxt_vlan_filter_set_op,
3177 .vlan_offload_set = bnxt_vlan_offload_set_op,
3178 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3179 .mtu_set = bnxt_mtu_set_op,
3180 .mac_addr_set = bnxt_set_default_mac_addr_op,
3181 .xstats_get = bnxt_dev_xstats_get_op,
3182 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3183 .xstats_reset = bnxt_dev_xstats_reset_op,
3184 .fw_version_get = bnxt_fw_version_get,
3185 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3186 .rxq_info_get = bnxt_rxq_info_get_op,
3187 .txq_info_get = bnxt_txq_info_get_op,
3188 .dev_led_on = bnxt_dev_led_on_op,
3189 .dev_led_off = bnxt_dev_led_off_op,
3190 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3191 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3192 .rx_queue_count = bnxt_rx_queue_count_op,
3193 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3194 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3195 .rx_queue_start = bnxt_rx_queue_start,
3196 .rx_queue_stop = bnxt_rx_queue_stop,
3197 .tx_queue_start = bnxt_tx_queue_start,
3198 .tx_queue_stop = bnxt_tx_queue_stop,
3199 .filter_ctrl = bnxt_filter_ctrl_op,
3200 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3201 .get_eeprom_length = bnxt_get_eeprom_length_op,
3202 .get_eeprom = bnxt_get_eeprom_op,
3203 .set_eeprom = bnxt_set_eeprom_op,
3204 .timesync_enable = bnxt_timesync_enable,
3205 .timesync_disable = bnxt_timesync_disable,
3206 .timesync_read_time = bnxt_timesync_read_time,
3207 .timesync_write_time = bnxt_timesync_write_time,
3208 .timesync_adjust_time = bnxt_timesync_adjust_time,
3209 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3210 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3213 static bool bnxt_vf_pciid(uint16_t id)
3215 if (id == BROADCOM_DEV_ID_57304_VF ||
3216 id == BROADCOM_DEV_ID_57406_VF ||
3217 id == BROADCOM_DEV_ID_5731X_VF ||
3218 id == BROADCOM_DEV_ID_5741X_VF ||
3219 id == BROADCOM_DEV_ID_57414_VF ||
3220 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3221 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3222 id == BROADCOM_DEV_ID_58802_VF)
3227 bool bnxt_stratus_device(struct bnxt *bp)
3229 uint16_t id = bp->pdev->id.device_id;
3231 if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3232 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3233 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3238 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3240 struct bnxt *bp = eth_dev->data->dev_private;
3241 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3244 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3245 if (!pci_dev->mem_resource[0].addr) {
3247 "Cannot find PCI device base address, aborting\n");
3249 goto init_err_disable;
3252 bp->eth_dev = eth_dev;
3255 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3257 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3259 goto init_err_release;
3262 if (!pci_dev->mem_resource[2].addr) {
3264 "Cannot find PCI device BAR 2 address, aborting\n");
3266 goto init_err_release;
3268 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3276 if (bp->doorbell_base)
3277 bp->doorbell_base = NULL;
3285 #define ALLOW_FUNC(x) \
3287 typeof(x) arg = (x); \
3288 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3289 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3292 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3294 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3295 char mz_name[RTE_MEMZONE_NAMESIZE];
3296 const struct rte_memzone *mz = NULL;
3297 static int version_printed;
3298 uint32_t total_alloc_len;
3299 rte_iova_t mz_phys_addr;
3303 if (version_printed++ == 0)
3304 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3306 rte_eth_copy_pci_info(eth_dev, pci_dev);
3308 bp = eth_dev->data->dev_private;
3310 bp->dev_stopped = 1;
3312 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3315 if (bnxt_vf_pciid(pci_dev->id.device_id))
3316 bp->flags |= BNXT_FLAG_VF;
3318 rc = bnxt_init_board(eth_dev);
3321 "Board initialization failed rc: %x\n", rc);
3325 eth_dev->dev_ops = &bnxt_dev_ops;
3326 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3327 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3328 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3331 if (pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3332 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3333 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3334 pci_dev->addr.bus, pci_dev->addr.devid,
3335 pci_dev->addr.function, "rx_port_stats");
3336 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3337 mz = rte_memzone_lookup(mz_name);
3338 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3339 sizeof(struct rx_port_stats) +
3340 sizeof(struct rx_port_stats_ext) +
3343 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3346 RTE_MEMZONE_SIZE_HINT_ONLY |
3347 RTE_MEMZONE_IOVA_CONTIG);
3351 memset(mz->addr, 0, mz->len);
3352 mz_phys_addr = mz->iova;
3353 if ((unsigned long)mz->addr == mz_phys_addr) {
3355 "Memzone physical address same as virtual using rte_mem_virt2iova()\n");
3356 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3357 if (mz_phys_addr == 0) {
3359 "unable to map address to physical memory\n");
3364 bp->rx_mem_zone = (const void *)mz;
3365 bp->hw_rx_port_stats = mz->addr;
3366 bp->hw_rx_port_stats_map = mz_phys_addr;
3368 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3369 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3370 pci_dev->addr.bus, pci_dev->addr.devid,
3371 pci_dev->addr.function, "tx_port_stats");
3372 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3373 mz = rte_memzone_lookup(mz_name);
3374 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3375 sizeof(struct tx_port_stats) +
3376 sizeof(struct tx_port_stats_ext) +
3379 mz = rte_memzone_reserve(mz_name,
3383 RTE_MEMZONE_SIZE_HINT_ONLY |
3384 RTE_MEMZONE_IOVA_CONTIG);
3388 memset(mz->addr, 0, mz->len);
3389 mz_phys_addr = mz->iova;
3390 if ((unsigned long)mz->addr == mz_phys_addr) {
3391 PMD_DRV_LOG(WARNING,
3392 "Memzone physical address same as virtual.\n");
3393 PMD_DRV_LOG(WARNING,
3394 "Using rte_mem_virt2iova()\n");
3395 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3396 if (mz_phys_addr == 0) {
3398 "unable to map address to physical memory\n");
3403 bp->tx_mem_zone = (const void *)mz;
3404 bp->hw_tx_port_stats = mz->addr;
3405 bp->hw_tx_port_stats_map = mz_phys_addr;
3407 bp->flags |= BNXT_FLAG_PORT_STATS;
3409 /* Display extended statistics if FW supports it */
3410 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
3411 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0)
3412 goto skip_ext_stats;
3414 bp->hw_rx_port_stats_ext = (void *)
3415 (bp->hw_rx_port_stats + sizeof(struct rx_port_stats));
3416 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
3417 sizeof(struct rx_port_stats);
3418 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
3421 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2) {
3422 bp->hw_tx_port_stats_ext = (void *)
3423 (bp->hw_tx_port_stats + sizeof(struct tx_port_stats));
3424 bp->hw_tx_port_stats_ext_map =
3425 bp->hw_tx_port_stats_map +
3426 sizeof(struct tx_port_stats);
3427 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
3432 rc = bnxt_alloc_hwrm_resources(bp);
3435 "hwrm resource allocation failure rc: %x\n", rc);
3438 rc = bnxt_hwrm_ver_get(bp);
3441 rc = bnxt_hwrm_queue_qportcfg(bp);
3443 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3447 rc = bnxt_hwrm_func_qcfg(bp);
3449 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3453 /* Get the MAX capabilities for this function */
3454 rc = bnxt_hwrm_func_qcaps(bp);
3456 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3459 if (bp->max_tx_rings == 0) {
3460 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3464 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3465 RTE_ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3466 if (eth_dev->data->mac_addrs == NULL) {
3468 "Failed to alloc %u bytes needed to store MAC addr tbl",
3469 RTE_ETHER_ADDR_LEN * bp->max_l2_ctx);
3474 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
3476 "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
3477 bp->dflt_mac_addr[0], bp->dflt_mac_addr[1],
3478 bp->dflt_mac_addr[2], bp->dflt_mac_addr[3],
3479 bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]);
3483 /* Copy the permanent MAC from the qcap response address now. */
3484 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3485 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
3487 if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3488 /* 1 ring is for default completion ring */
3489 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3494 bp->grp_info = rte_zmalloc("bnxt_grp_info",
3495 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3496 if (!bp->grp_info) {
3498 "Failed to alloc %zu bytes to store group info table\n",
3499 sizeof(*bp->grp_info) * bp->max_ring_grps);
3504 /* Forward all requests if firmware is new enough */
3505 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3506 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3507 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3508 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3510 PMD_DRV_LOG(WARNING,
3511 "Firmware too old for VF mailbox functionality\n");
3512 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3516 * The following are used for driver cleanup. If we disallow these,
3517 * VF drivers can't clean up cleanly.
3519 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3520 ALLOW_FUNC(HWRM_VNIC_FREE);
3521 ALLOW_FUNC(HWRM_RING_FREE);
3522 ALLOW_FUNC(HWRM_RING_GRP_FREE);
3523 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3524 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3525 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3526 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3527 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3528 rc = bnxt_hwrm_func_driver_register(bp);
3531 "Failed to register driver");
3537 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3538 pci_dev->mem_resource[0].phys_addr,
3539 pci_dev->mem_resource[0].addr);
3541 rc = bnxt_hwrm_func_reset(bp);
3543 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3549 //if (bp->pf.active_vfs) {
3550 // TODO: Deallocate VF resources?
3552 if (bp->pdev->max_vfs) {
3553 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3555 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3559 rc = bnxt_hwrm_allocate_pf_only(bp);
3562 "Failed to allocate PF resources\n");
3568 bnxt_hwrm_port_led_qcaps(bp);
3570 rc = bnxt_setup_int(bp);
3574 rc = bnxt_alloc_mem(bp);
3576 goto error_free_int;
3578 rc = bnxt_request_int(bp);
3580 goto error_free_int;
3582 bnxt_enable_int(bp);
3588 bnxt_disable_int(bp);
3589 bnxt_hwrm_func_buf_unrgtr(bp);
3593 bnxt_dev_uninit(eth_dev);
3599 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
3601 struct bnxt *bp = eth_dev->data->dev_private;
3604 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3607 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
3608 bnxt_disable_int(bp);
3611 if (bp->grp_info != NULL) {
3612 rte_free(bp->grp_info);
3613 bp->grp_info = NULL;
3615 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3616 bnxt_free_hwrm_resources(bp);
3618 if (bp->tx_mem_zone) {
3619 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3620 bp->tx_mem_zone = NULL;
3623 if (bp->rx_mem_zone) {
3624 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3625 bp->rx_mem_zone = NULL;
3628 if (bp->dev_stopped == 0)
3629 bnxt_dev_close_op(eth_dev);
3631 rte_free(bp->pf.vf_info);
3632 eth_dev->dev_ops = NULL;
3633 eth_dev->rx_pkt_burst = NULL;
3634 eth_dev->tx_pkt_burst = NULL;
3639 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3640 struct rte_pci_device *pci_dev)
3642 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
3646 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
3648 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3649 return rte_eth_dev_pci_generic_remove(pci_dev,
3652 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3655 static struct rte_pci_driver bnxt_rte_pmd = {
3656 .id_table = bnxt_pci_id_map,
3657 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
3658 RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_IOVA_AS_VA,
3659 .probe = bnxt_pci_probe,
3660 .remove = bnxt_pci_remove,
3664 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
3666 if (strcmp(dev->device->driver->name, drv->driver.name))
3672 bool is_bnxt_supported(struct rte_eth_dev *dev)
3674 return is_device_supported(dev, &bnxt_rte_pmd);
3677 RTE_INIT(bnxt_init_log)
3679 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
3680 if (bnxt_logtype_driver >= 0)
3681 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
3684 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
3685 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
3686 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");