4 * Copyright(c) Broadcom Limited.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Broadcom Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include <rte_ethdev.h>
39 #include <rte_ethdev_pci.h>
40 #include <rte_malloc.h>
41 #include <rte_cycles.h>
45 #include "bnxt_filter.h"
46 #include "bnxt_hwrm.h"
48 #include "bnxt_ring.h"
51 #include "bnxt_stats.h"
54 #include "bnxt_vnic.h"
55 #include "hsi_struct_def_dpdk.h"
56 #include "bnxt_nvm_defs.h"
58 #define DRV_MODULE_NAME "bnxt"
59 static const char bnxt_version[] =
60 "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
62 #define PCI_VENDOR_ID_BROADCOM 0x14E4
64 #define BROADCOM_DEV_ID_STRATUS_NIC_VF 0x1609
65 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
66 #define BROADCOM_DEV_ID_57414_VF 0x16c1
67 #define BROADCOM_DEV_ID_57301 0x16c8
68 #define BROADCOM_DEV_ID_57302 0x16c9
69 #define BROADCOM_DEV_ID_57304_PF 0x16ca
70 #define BROADCOM_DEV_ID_57304_VF 0x16cb
71 #define BROADCOM_DEV_ID_57417_MF 0x16cc
72 #define BROADCOM_DEV_ID_NS2 0x16cd
73 #define BROADCOM_DEV_ID_57311 0x16ce
74 #define BROADCOM_DEV_ID_57312 0x16cf
75 #define BROADCOM_DEV_ID_57402 0x16d0
76 #define BROADCOM_DEV_ID_57404 0x16d1
77 #define BROADCOM_DEV_ID_57406_PF 0x16d2
78 #define BROADCOM_DEV_ID_57406_VF 0x16d3
79 #define BROADCOM_DEV_ID_57402_MF 0x16d4
80 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
81 #define BROADCOM_DEV_ID_57412 0x16d6
82 #define BROADCOM_DEV_ID_57414 0x16d7
83 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
84 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
85 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
86 #define BROADCOM_DEV_ID_57412_MF 0x16de
87 #define BROADCOM_DEV_ID_57314 0x16df
88 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
89 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
90 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
91 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
92 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
93 #define BROADCOM_DEV_ID_57404_MF 0x16e7
94 #define BROADCOM_DEV_ID_57406_MF 0x16e8
95 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
96 #define BROADCOM_DEV_ID_57407_MF 0x16ea
97 #define BROADCOM_DEV_ID_57414_MF 0x16ec
98 #define BROADCOM_DEV_ID_57416_MF 0x16ee
100 static const struct rte_pci_id bnxt_pci_id_map[] = {
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
102 BROADCOM_DEV_ID_STRATUS_NIC_VF) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
130 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
131 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
132 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
133 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
134 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
135 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
136 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
137 { .vendor_id = 0, /* sentinel */ },
140 #define BNXT_ETH_RSS_SUPPORT ( \
142 ETH_RSS_NONFRAG_IPV4_TCP | \
143 ETH_RSS_NONFRAG_IPV4_UDP | \
145 ETH_RSS_NONFRAG_IPV6_TCP | \
146 ETH_RSS_NONFRAG_IPV6_UDP)
148 static void bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
150 /***********************/
153 * High level utility functions
156 static void bnxt_free_mem(struct bnxt *bp)
158 bnxt_free_filter_mem(bp);
159 bnxt_free_vnic_attributes(bp);
160 bnxt_free_vnic_mem(bp);
163 bnxt_free_tx_rings(bp);
164 bnxt_free_rx_rings(bp);
165 bnxt_free_def_cp_ring(bp);
168 static int bnxt_alloc_mem(struct bnxt *bp)
172 /* Default completion ring */
173 rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
177 rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
178 bp->def_cp_ring, "def_cp");
182 rc = bnxt_alloc_vnic_mem(bp);
186 rc = bnxt_alloc_vnic_attributes(bp);
190 rc = bnxt_alloc_filter_mem(bp);
201 static int bnxt_init_chip(struct bnxt *bp)
203 unsigned int i, rss_idx, fw_idx;
204 struct rte_eth_link new;
207 if (bp->eth_dev->data->mtu > ETHER_MTU) {
208 bp->eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
209 bp->flags |= BNXT_FLAG_JUMBO;
211 bp->eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
212 bp->flags &= ~BNXT_FLAG_JUMBO;
215 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
217 RTE_LOG(ERR, PMD, "HWRM stat ctx alloc failure rc: %x\n", rc);
221 rc = bnxt_alloc_hwrm_rings(bp);
223 RTE_LOG(ERR, PMD, "HWRM ring alloc failure rc: %x\n", rc);
227 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
229 RTE_LOG(ERR, PMD, "HWRM ring grp alloc failure: %x\n", rc);
233 rc = bnxt_mq_rx_configure(bp);
235 RTE_LOG(ERR, PMD, "MQ mode configure failure rc: %x\n", rc);
239 /* VNIC configuration */
240 for (i = 0; i < bp->nr_vnics; i++) {
241 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
243 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
245 RTE_LOG(ERR, PMD, "HWRM vnic %d alloc failure rc: %x\n",
250 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
253 "HWRM vnic %d ctx alloc failure rc: %x\n",
258 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
260 RTE_LOG(ERR, PMD, "HWRM vnic %d cfg failure rc: %x\n",
265 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
268 "HWRM vnic %d filter failure rc: %x\n",
272 if (vnic->rss_table && vnic->hash_type) {
274 * Fill the RSS hash & redirection table with
275 * ring group ids for all VNICs
277 for (rss_idx = 0, fw_idx = 0;
278 rss_idx < HW_HASH_INDEX_SIZE;
279 rss_idx++, fw_idx++) {
280 if (vnic->fw_grp_ids[fw_idx] ==
283 vnic->rss_table[rss_idx] =
284 vnic->fw_grp_ids[fw_idx];
286 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
289 "HWRM vnic %d set RSS failure rc: %x\n",
295 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
297 if (bp->eth_dev->data->dev_conf.rxmode.enable_lro)
298 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
300 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
302 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
305 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
309 rc = bnxt_get_hwrm_link_config(bp, &new);
311 RTE_LOG(ERR, PMD, "HWRM Get link config failure rc: %x\n", rc);
315 if (!bp->link_info.link_up) {
316 rc = bnxt_set_hwrm_link_config(bp, true);
319 "HWRM link config failure rc: %x\n", rc);
327 bnxt_free_all_hwrm_resources(bp);
332 static int bnxt_shutdown_nic(struct bnxt *bp)
334 bnxt_free_all_hwrm_resources(bp);
335 bnxt_free_all_filters(bp);
336 bnxt_free_all_vnics(bp);
340 static int bnxt_init_nic(struct bnxt *bp)
344 bnxt_init_ring_grps(bp);
346 bnxt_init_filters(bp);
348 rc = bnxt_init_chip(bp);
356 * Device configuration and status function
359 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
360 struct rte_eth_dev_info *dev_info)
362 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
363 uint16_t max_vnics, i, j, vpool, vrxq;
364 unsigned int max_rx_rings;
366 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
369 dev_info->max_mac_addrs = MAX_NUM_MAC_ADDR;
370 dev_info->max_hash_mac_addrs = 0;
372 /* PF/VF specifics */
374 dev_info->max_vfs = bp->pdev->max_vfs;
375 max_rx_rings = RTE_MIN(bp->max_vnics, RTE_MIN(bp->max_l2_ctx,
376 RTE_MIN(bp->max_rsscos_ctx,
378 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
379 dev_info->max_rx_queues = max_rx_rings;
380 dev_info->max_tx_queues = max_rx_rings;
381 dev_info->reta_size = bp->max_rsscos_ctx;
382 dev_info->hash_key_size = 40;
383 max_vnics = bp->max_vnics;
385 /* Fast path specifics */
386 dev_info->min_rx_bufsize = 1;
387 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
389 dev_info->rx_offload_capa = 0;
390 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
391 DEV_TX_OFFLOAD_TCP_CKSUM |
392 DEV_TX_OFFLOAD_UDP_CKSUM |
393 DEV_TX_OFFLOAD_TCP_TSO |
394 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
395 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
396 DEV_TX_OFFLOAD_GRE_TNL_TSO |
397 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
398 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
401 dev_info->default_rxconf = (struct rte_eth_rxconf) {
407 .rx_free_thresh = 32,
411 dev_info->default_txconf = (struct rte_eth_txconf) {
417 .tx_free_thresh = 32,
419 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
420 ETH_TXQ_FLAGS_NOOFFLOADS,
422 eth_dev->data->dev_conf.intr_conf.lsc = 1;
427 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
428 * need further investigation.
432 vpool = 64; /* ETH_64_POOLS */
433 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
434 for (i = 0; i < 4; vpool >>= 1, i++) {
435 if (max_vnics > vpool) {
436 for (j = 0; j < 5; vrxq >>= 1, j++) {
437 if (dev_info->max_rx_queues > vrxq) {
443 /* Not enough resources to support VMDq */
447 /* Not enough resources to support VMDq */
451 dev_info->max_vmdq_pools = vpool;
452 dev_info->vmdq_queue_num = vrxq;
454 dev_info->vmdq_pool_base = 0;
455 dev_info->vmdq_queue_base = 0;
458 /* Configure the device based on the configuration provided */
459 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
461 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
463 bp->rx_queues = (void *)eth_dev->data->rx_queues;
464 bp->tx_queues = (void *)eth_dev->data->tx_queues;
466 /* Inherit new configurations */
467 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
468 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
469 bp->rx_cp_nr_rings = bp->rx_nr_rings;
470 bp->tx_cp_nr_rings = bp->tx_nr_rings;
472 if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
474 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
475 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
480 rte_bnxt_atomic_write_link_status(struct rte_eth_dev *eth_dev,
481 struct rte_eth_link *link)
483 struct rte_eth_link *dst = ð_dev->data->dev_link;
484 struct rte_eth_link *src = link;
486 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
487 *(uint64_t *)src) == 0)
493 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
495 struct rte_eth_link *link = ð_dev->data->dev_link;
497 if (link->link_status)
498 RTE_LOG(INFO, PMD, "Port %d Link Up - speed %u Mbps - %s\n",
499 (uint8_t)(eth_dev->data->port_id),
500 (uint32_t)link->link_speed,
501 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
502 ("full-duplex") : ("half-duplex\n"));
504 RTE_LOG(INFO, PMD, "Port %d Link Down\n",
505 (uint8_t)(eth_dev->data->port_id));
508 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
510 bnxt_print_link_info(eth_dev);
514 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
516 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
522 rc = bnxt_init_nic(bp);
526 bnxt_link_update_op(eth_dev, 0);
528 if (eth_dev->data->dev_conf.rxmode.hw_vlan_filter)
529 vlan_mask |= ETH_VLAN_FILTER_MASK;
530 if (eth_dev->data->dev_conf.rxmode.hw_vlan_strip)
531 vlan_mask |= ETH_VLAN_STRIP_MASK;
532 bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
537 bnxt_shutdown_nic(bp);
538 bnxt_free_tx_mbufs(bp);
539 bnxt_free_rx_mbufs(bp);
543 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
545 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
547 eth_dev->data->dev_link.link_status = 1;
548 bnxt_set_hwrm_link_config(bp, true);
552 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
554 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
556 eth_dev->data->dev_link.link_status = 0;
557 bnxt_set_hwrm_link_config(bp, false);
561 /* Unload the driver, release resources */
562 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
564 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
566 if (bp->eth_dev->data->dev_started) {
567 /* TBD: STOP HW queues DMA */
568 eth_dev->data->dev_link.link_status = 0;
570 bnxt_set_hwrm_link_config(bp, false);
571 bnxt_hwrm_port_clr_stats(bp);
572 bnxt_shutdown_nic(bp);
576 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
578 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
580 if (bp->dev_stopped == 0)
581 bnxt_dev_stop_op(eth_dev);
583 bnxt_free_tx_mbufs(bp);
584 bnxt_free_rx_mbufs(bp);
586 if (eth_dev->data->mac_addrs != NULL) {
587 rte_free(eth_dev->data->mac_addrs);
588 eth_dev->data->mac_addrs = NULL;
590 if (bp->grp_info != NULL) {
591 rte_free(bp->grp_info);
596 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
599 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
600 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
601 struct bnxt_vnic_info *vnic;
602 struct bnxt_filter_info *filter, *temp_filter;
606 * Loop through all VNICs from the specified filter flow pools to
607 * remove the corresponding MAC addr filter
609 for (i = 0; i < MAX_FF_POOLS; i++) {
610 if (!(pool_mask & (1ULL << i)))
613 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
614 filter = STAILQ_FIRST(&vnic->filter);
616 temp_filter = STAILQ_NEXT(filter, next);
617 if (filter->mac_index == index) {
618 STAILQ_REMOVE(&vnic->filter, filter,
619 bnxt_filter_info, next);
620 bnxt_hwrm_clear_l2_filter(bp, filter);
621 filter->mac_index = INVALID_MAC_INDEX;
622 memset(&filter->l2_addr, 0,
625 &bp->free_filter_list,
628 filter = temp_filter;
634 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
635 struct ether_addr *mac_addr,
636 uint32_t index, uint32_t pool)
638 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
639 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
640 struct bnxt_filter_info *filter;
643 RTE_LOG(ERR, PMD, "Cannot add MAC address to a VF interface\n");
648 RTE_LOG(ERR, PMD, "VNIC not found for pool %d!\n", pool);
651 /* Attach requested MAC address to the new l2_filter */
652 STAILQ_FOREACH(filter, &vnic->filter, next) {
653 if (filter->mac_index == index) {
655 "MAC addr already existed for pool %d\n", pool);
659 filter = bnxt_alloc_filter(bp);
661 RTE_LOG(ERR, PMD, "L2 filter alloc failed\n");
664 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
665 filter->mac_index = index;
666 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
667 return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
670 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
673 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
674 struct rte_eth_link new;
675 unsigned int cnt = BNXT_LINK_WAIT_CNT;
677 memset(&new, 0, sizeof(new));
679 /* Retrieve link info from hardware */
680 rc = bnxt_get_hwrm_link_config(bp, &new);
682 new.link_speed = ETH_LINK_SPEED_100M;
683 new.link_duplex = ETH_LINK_FULL_DUPLEX;
685 "Failed to retrieve link rc = 0x%x!\n", rc);
688 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
690 if (!wait_to_complete)
692 } while (!new.link_status && cnt--);
695 /* Timed out or success */
696 if (new.link_status != eth_dev->data->dev_link.link_status ||
697 new.link_speed != eth_dev->data->dev_link.link_speed) {
698 rte_bnxt_atomic_write_link_status(eth_dev, &new);
699 bnxt_print_link_info(eth_dev);
705 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
707 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
708 struct bnxt_vnic_info *vnic;
710 if (bp->vnic_info == NULL)
713 vnic = &bp->vnic_info[0];
715 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
716 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
719 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
721 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
722 struct bnxt_vnic_info *vnic;
724 if (bp->vnic_info == NULL)
727 vnic = &bp->vnic_info[0];
729 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
730 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
733 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
735 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
736 struct bnxt_vnic_info *vnic;
738 if (bp->vnic_info == NULL)
741 vnic = &bp->vnic_info[0];
743 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
744 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
747 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
749 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
750 struct bnxt_vnic_info *vnic;
752 if (bp->vnic_info == NULL)
755 vnic = &bp->vnic_info[0];
757 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
758 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
761 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
762 struct rte_eth_rss_reta_entry64 *reta_conf,
765 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
766 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
767 struct bnxt_vnic_info *vnic;
770 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
773 if (reta_size != HW_HASH_INDEX_SIZE) {
774 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
775 "(%d) must equal the size supported by the hardware "
776 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
779 /* Update the RSS VNIC(s) */
780 for (i = 0; i < MAX_FF_POOLS; i++) {
781 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
782 memcpy(vnic->rss_table, reta_conf, reta_size);
784 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
790 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
791 struct rte_eth_rss_reta_entry64 *reta_conf,
794 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
795 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
796 struct rte_intr_handle *intr_handle
797 = &bp->pdev->intr_handle;
799 /* Retrieve from the default VNIC */
802 if (!vnic->rss_table)
805 if (reta_size != HW_HASH_INDEX_SIZE) {
806 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
807 "(%d) must equal the size supported by the hardware "
808 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
811 /* EW - need to revisit here copying from u64 to u16 */
812 memcpy(reta_conf, vnic->rss_table, reta_size);
814 if (rte_intr_allow_others(intr_handle)) {
815 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
816 bnxt_dev_lsc_intr_setup(eth_dev);
822 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
823 struct rte_eth_rss_conf *rss_conf)
825 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
826 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
827 struct bnxt_vnic_info *vnic;
828 uint16_t hash_type = 0;
832 * If RSS enablement were different than dev_configure,
833 * then return -EINVAL
835 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
836 if (!rss_conf->rss_hf)
837 RTE_LOG(ERR, PMD, "Hash type NONE\n");
839 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
843 bp->flags |= BNXT_FLAG_UPDATE_HASH;
844 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
846 if (rss_conf->rss_hf & ETH_RSS_IPV4)
847 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
848 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
849 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
850 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
851 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
852 if (rss_conf->rss_hf & ETH_RSS_IPV6)
853 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
854 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
855 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
856 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
857 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
859 /* Update the RSS VNIC(s) */
860 for (i = 0; i < MAX_FF_POOLS; i++) {
861 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
862 vnic->hash_type = hash_type;
865 * Use the supplied key if the key length is
866 * acceptable and the rss_key is not NULL
868 if (rss_conf->rss_key &&
869 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
870 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
871 rss_conf->rss_key_len);
873 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
879 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
880 struct rte_eth_rss_conf *rss_conf)
882 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
883 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
887 /* RSS configuration is the same for all VNICs */
888 if (vnic && vnic->rss_hash_key) {
889 if (rss_conf->rss_key) {
890 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
891 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
892 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
895 hash_types = vnic->hash_type;
896 rss_conf->rss_hf = 0;
897 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
898 rss_conf->rss_hf |= ETH_RSS_IPV4;
899 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
901 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
902 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
904 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
906 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
907 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
909 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
911 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
912 rss_conf->rss_hf |= ETH_RSS_IPV6;
913 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
915 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
916 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
918 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
920 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
921 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
923 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
927 "Unknwon RSS config from firmware (%08x), RSS disabled",
932 rss_conf->rss_hf = 0;
937 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
938 struct rte_eth_fc_conf *fc_conf)
940 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
941 struct rte_eth_link link_info;
944 rc = bnxt_get_hwrm_link_config(bp, &link_info);
948 memset(fc_conf, 0, sizeof(*fc_conf));
949 if (bp->link_info.auto_pause)
950 fc_conf->autoneg = 1;
951 switch (bp->link_info.pause) {
953 fc_conf->mode = RTE_FC_NONE;
955 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
956 fc_conf->mode = RTE_FC_TX_PAUSE;
958 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
959 fc_conf->mode = RTE_FC_RX_PAUSE;
961 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
962 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
963 fc_conf->mode = RTE_FC_FULL;
969 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
970 struct rte_eth_fc_conf *fc_conf)
972 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
974 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp)) {
975 RTE_LOG(ERR, PMD, "Flow Control Settings cannot be modified\n");
979 switch (fc_conf->mode) {
981 bp->link_info.auto_pause = 0;
982 bp->link_info.force_pause = 0;
984 case RTE_FC_RX_PAUSE:
985 if (fc_conf->autoneg) {
986 bp->link_info.auto_pause =
987 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
988 bp->link_info.force_pause = 0;
990 bp->link_info.auto_pause = 0;
991 bp->link_info.force_pause =
992 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
995 case RTE_FC_TX_PAUSE:
996 if (fc_conf->autoneg) {
997 bp->link_info.auto_pause =
998 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
999 bp->link_info.force_pause = 0;
1001 bp->link_info.auto_pause = 0;
1002 bp->link_info.force_pause =
1003 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1007 if (fc_conf->autoneg) {
1008 bp->link_info.auto_pause =
1009 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1010 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1011 bp->link_info.force_pause = 0;
1013 bp->link_info.auto_pause = 0;
1014 bp->link_info.force_pause =
1015 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1016 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1020 return bnxt_set_hwrm_link_config(bp, true);
1023 /* Add UDP tunneling port */
1025 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1026 struct rte_eth_udp_tunnel *udp_tunnel)
1028 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1029 uint16_t tunnel_type = 0;
1032 switch (udp_tunnel->prot_type) {
1033 case RTE_TUNNEL_TYPE_VXLAN:
1034 if (bp->vxlan_port_cnt) {
1035 RTE_LOG(ERR, PMD, "Tunnel Port %d already programmed\n",
1036 udp_tunnel->udp_port);
1037 if (bp->vxlan_port != udp_tunnel->udp_port) {
1038 RTE_LOG(ERR, PMD, "Only one port allowed\n");
1041 bp->vxlan_port_cnt++;
1045 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1046 bp->vxlan_port_cnt++;
1048 case RTE_TUNNEL_TYPE_GENEVE:
1049 if (bp->geneve_port_cnt) {
1050 RTE_LOG(ERR, PMD, "Tunnel Port %d already programmed\n",
1051 udp_tunnel->udp_port);
1052 if (bp->geneve_port != udp_tunnel->udp_port) {
1053 RTE_LOG(ERR, PMD, "Only one port allowed\n");
1056 bp->geneve_port_cnt++;
1060 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1061 bp->geneve_port_cnt++;
1064 RTE_LOG(ERR, PMD, "Tunnel type is not supported\n");
1067 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1073 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1074 struct rte_eth_udp_tunnel *udp_tunnel)
1076 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1077 uint16_t tunnel_type = 0;
1081 switch (udp_tunnel->prot_type) {
1082 case RTE_TUNNEL_TYPE_VXLAN:
1083 if (!bp->vxlan_port_cnt) {
1084 RTE_LOG(ERR, PMD, "No Tunnel port configured yet\n");
1087 if (bp->vxlan_port != udp_tunnel->udp_port) {
1088 RTE_LOG(ERR, PMD, "Req Port: %d. Configured port: %d\n",
1089 udp_tunnel->udp_port, bp->vxlan_port);
1092 if (--bp->vxlan_port_cnt)
1096 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1097 port = bp->vxlan_fw_dst_port_id;
1099 case RTE_TUNNEL_TYPE_GENEVE:
1100 if (!bp->geneve_port_cnt) {
1101 RTE_LOG(ERR, PMD, "No Tunnel port configured yet\n");
1104 if (bp->geneve_port != udp_tunnel->udp_port) {
1105 RTE_LOG(ERR, PMD, "Req Port: %d. Configured port: %d\n",
1106 udp_tunnel->udp_port, bp->geneve_port);
1109 if (--bp->geneve_port_cnt)
1113 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1114 port = bp->geneve_fw_dst_port_id;
1117 RTE_LOG(ERR, PMD, "Tunnel type is not supported\n");
1121 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1124 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1127 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1128 bp->geneve_port = 0;
1133 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1135 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1136 struct bnxt_vnic_info *vnic;
1139 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1141 /* Cycle through all VNICs */
1142 for (i = 0; i < bp->nr_vnics; i++) {
1144 * For each VNIC and each associated filter(s)
1145 * if VLAN exists && VLAN matches vlan_id
1146 * remove the MAC+VLAN filter
1147 * add a new MAC only filter
1149 * VLAN filter doesn't exist, just skip and continue
1151 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1152 filter = STAILQ_FIRST(&vnic->filter);
1154 temp_filter = STAILQ_NEXT(filter, next);
1156 if (filter->enables & chk &&
1157 filter->l2_ovlan == vlan_id) {
1158 /* Must delete the filter */
1159 STAILQ_REMOVE(&vnic->filter, filter,
1160 bnxt_filter_info, next);
1161 bnxt_hwrm_clear_l2_filter(bp, filter);
1163 &bp->free_filter_list,
1167 * Need to examine to see if the MAC
1168 * filter already existed or not before
1169 * allocating a new one
1172 new_filter = bnxt_alloc_filter(bp);
1175 "MAC/VLAN filter alloc failed\n");
1179 STAILQ_INSERT_TAIL(&vnic->filter,
1181 /* Inherit MAC from previous filter */
1182 new_filter->mac_index =
1184 memcpy(new_filter->l2_addr,
1185 filter->l2_addr, ETHER_ADDR_LEN);
1186 /* MAC only filter */
1187 rc = bnxt_hwrm_set_l2_filter(bp,
1193 "Del Vlan filter for %d\n",
1196 filter = temp_filter;
1204 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1206 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1207 struct bnxt_vnic_info *vnic;
1210 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN |
1211 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK;
1212 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1214 /* Cycle through all VNICs */
1215 for (i = 0; i < bp->nr_vnics; i++) {
1217 * For each VNIC and each associated filter(s)
1219 * if VLAN matches vlan_id
1220 * VLAN filter already exists, just skip and continue
1222 * add a new MAC+VLAN filter
1224 * Remove the old MAC only filter
1225 * Add a new MAC+VLAN filter
1227 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1228 filter = STAILQ_FIRST(&vnic->filter);
1230 temp_filter = STAILQ_NEXT(filter, next);
1232 if (filter->enables & chk) {
1233 if (filter->l2_ovlan == vlan_id)
1236 /* Must delete the MAC filter */
1237 STAILQ_REMOVE(&vnic->filter, filter,
1238 bnxt_filter_info, next);
1239 bnxt_hwrm_clear_l2_filter(bp, filter);
1240 filter->l2_ovlan = 0;
1242 &bp->free_filter_list,
1245 new_filter = bnxt_alloc_filter(bp);
1248 "MAC/VLAN filter alloc failed\n");
1252 STAILQ_INSERT_TAIL(&vnic->filter, new_filter,
1254 /* Inherit MAC from the previous filter */
1255 new_filter->mac_index = filter->mac_index;
1256 memcpy(new_filter->l2_addr, filter->l2_addr,
1258 /* MAC + VLAN ID filter */
1259 new_filter->l2_ovlan = vlan_id;
1260 new_filter->l2_ovlan_mask = 0xF000;
1261 new_filter->enables |= en;
1262 rc = bnxt_hwrm_set_l2_filter(bp,
1268 "Added Vlan filter for %d\n", vlan_id);
1270 filter = temp_filter;
1278 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1279 uint16_t vlan_id, int on)
1281 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1283 /* These operations apply to ALL existing MAC/VLAN filters */
1285 return bnxt_add_vlan_filter(bp, vlan_id);
1287 return bnxt_del_vlan_filter(bp, vlan_id);
1291 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1293 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1296 if (mask & ETH_VLAN_FILTER_MASK) {
1297 if (!dev->data->dev_conf.rxmode.hw_vlan_filter) {
1298 /* Remove any VLAN filters programmed */
1299 for (i = 0; i < 4095; i++)
1300 bnxt_del_vlan_filter(bp, i);
1302 RTE_LOG(INFO, PMD, "VLAN Filtering: %d\n",
1303 dev->data->dev_conf.rxmode.hw_vlan_filter);
1306 if (mask & ETH_VLAN_STRIP_MASK) {
1307 /* Enable or disable VLAN stripping */
1308 for (i = 0; i < bp->nr_vnics; i++) {
1309 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1310 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1311 vnic->vlan_strip = true;
1313 vnic->vlan_strip = false;
1314 bnxt_hwrm_vnic_cfg(bp, vnic);
1316 RTE_LOG(INFO, PMD, "VLAN Strip Offload: %d\n",
1317 dev->data->dev_conf.rxmode.hw_vlan_strip);
1320 if (mask & ETH_VLAN_EXTEND_MASK)
1321 RTE_LOG(ERR, PMD, "Extend VLAN Not supported\n");
1325 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr)
1327 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1328 /* Default Filter is tied to VNIC 0 */
1329 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1330 struct bnxt_filter_info *filter;
1336 memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1337 memcpy(&dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
1339 STAILQ_FOREACH(filter, &vnic->filter, next) {
1340 /* Default Filter is at Index 0 */
1341 if (filter->mac_index != 0)
1343 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1346 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN);
1347 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN);
1348 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1350 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1351 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1352 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1355 filter->mac_index = 0;
1356 RTE_LOG(DEBUG, PMD, "Set MAC addr\n");
1361 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1362 struct ether_addr *mc_addr_set,
1363 uint32_t nb_mc_addr)
1365 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1366 char *mc_addr_list = (char *)mc_addr_set;
1367 struct bnxt_vnic_info *vnic;
1368 uint32_t off = 0, i = 0;
1370 vnic = &bp->vnic_info[0];
1372 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1373 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1377 /* TODO Check for Duplicate mcast addresses */
1378 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1379 for (i = 0; i < nb_mc_addr; i++) {
1380 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN);
1381 off += ETHER_ADDR_LEN;
1384 vnic->mc_addr_cnt = i;
1387 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1391 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1393 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1394 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1395 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1396 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1399 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1400 fw_major, fw_minor, fw_updt);
1402 ret += 1; /* add the size of '\0' */
1403 if (fw_size < (uint32_t)ret)
1410 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1411 struct rte_eth_rxq_info *qinfo)
1413 struct bnxt_rx_queue *rxq;
1415 rxq = dev->data->rx_queues[queue_id];
1417 qinfo->mp = rxq->mb_pool;
1418 qinfo->scattered_rx = dev->data->scattered_rx;
1419 qinfo->nb_desc = rxq->nb_rx_desc;
1421 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1422 qinfo->conf.rx_drop_en = 0;
1423 qinfo->conf.rx_deferred_start = 0;
1427 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1428 struct rte_eth_txq_info *qinfo)
1430 struct bnxt_tx_queue *txq;
1432 txq = dev->data->tx_queues[queue_id];
1434 qinfo->nb_desc = txq->nb_tx_desc;
1436 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1437 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1438 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1440 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1441 qinfo->conf.tx_rs_thresh = 0;
1442 qinfo->conf.txq_flags = txq->txq_flags;
1443 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1446 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1448 struct bnxt *bp = eth_dev->data->dev_private;
1449 struct rte_eth_dev_info dev_info;
1450 uint32_t max_dev_mtu;
1454 bnxt_dev_info_get_op(eth_dev, &dev_info);
1455 max_dev_mtu = dev_info.max_rx_pktlen -
1456 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2;
1458 if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) {
1459 RTE_LOG(ERR, PMD, "MTU requested must be within (%d, %d)\n",
1460 ETHER_MIN_MTU, max_dev_mtu);
1465 if (new_mtu > ETHER_MTU) {
1466 bp->flags |= BNXT_FLAG_JUMBO;
1467 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1;
1469 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0;
1470 bp->flags &= ~BNXT_FLAG_JUMBO;
1473 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
1474 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1476 eth_dev->data->mtu = new_mtu;
1477 RTE_LOG(INFO, PMD, "New MTU is %d\n", eth_dev->data->mtu);
1479 for (i = 0; i < bp->nr_vnics; i++) {
1480 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1482 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1483 ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1484 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1488 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1497 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1499 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1500 uint16_t vlan = bp->vlan;
1503 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp)) {
1505 "PVID cannot be modified for this function\n");
1508 bp->vlan = on ? pvid : 0;
1510 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1517 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1519 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1521 return bnxt_hwrm_port_led_cfg(bp, true);
1525 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1527 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1529 return bnxt_hwrm_port_led_cfg(bp, false);
1533 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1535 uint32_t desc = 0, raw_cons = 0, cons;
1536 struct bnxt_cp_ring_info *cpr;
1537 struct bnxt_rx_queue *rxq;
1538 struct rx_pkt_cmpl *rxcmp;
1543 rxq = dev->data->rx_queues[rx_queue_id];
1547 while (raw_cons < rxq->nb_rx_desc) {
1548 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1549 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1551 if (!CMPL_VALID(rxcmp, valid))
1553 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1554 cmp_type = CMP_TYPE(rxcmp);
1555 if (cmp_type == RX_PKT_CMPL_TYPE_RX_L2_TPA_END) {
1556 cmp = (rte_le_to_cpu_32(
1557 ((struct rx_tpa_end_cmpl *)
1558 (rxcmp))->agg_bufs_v1) &
1559 RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1560 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1562 } else if (cmp_type == 0x11) {
1564 cmp = (rxcmp->agg_bufs_v1 &
1565 RX_PKT_CMPL_AGG_BUFS_MASK) >>
1566 RX_PKT_CMPL_AGG_BUFS_SFT;
1571 raw_cons += cmp ? cmp : 2;
1578 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1580 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1581 struct bnxt_rx_ring_info *rxr;
1582 struct bnxt_cp_ring_info *cpr;
1583 struct bnxt_sw_rx_bd *rx_buf;
1584 struct rx_pkt_cmpl *rxcmp;
1585 uint32_t cons, cp_cons;
1593 if (offset >= rxq->nb_rx_desc)
1596 cons = RING_CMP(cpr->cp_ring_struct, offset);
1597 cp_cons = cpr->cp_raw_cons;
1598 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1600 if (cons > cp_cons) {
1601 if (CMPL_VALID(rxcmp, cpr->valid))
1602 return RTE_ETH_RX_DESC_DONE;
1604 if (CMPL_VALID(rxcmp, !cpr->valid))
1605 return RTE_ETH_RX_DESC_DONE;
1607 rx_buf = &rxr->rx_buf_ring[cons];
1608 if (rx_buf->mbuf == NULL)
1609 return RTE_ETH_RX_DESC_UNAVAIL;
1612 return RTE_ETH_RX_DESC_AVAIL;
1616 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1618 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1619 struct bnxt_tx_ring_info *txr;
1620 struct bnxt_cp_ring_info *cpr;
1621 struct bnxt_sw_tx_bd *tx_buf;
1622 struct tx_pkt_cmpl *txcmp;
1623 uint32_t cons, cp_cons;
1631 if (offset >= txq->nb_tx_desc)
1634 cons = RING_CMP(cpr->cp_ring_struct, offset);
1635 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1636 cp_cons = cpr->cp_raw_cons;
1638 if (cons > cp_cons) {
1639 if (CMPL_VALID(txcmp, cpr->valid))
1640 return RTE_ETH_TX_DESC_UNAVAIL;
1642 if (CMPL_VALID(txcmp, !cpr->valid))
1643 return RTE_ETH_TX_DESC_UNAVAIL;
1645 tx_buf = &txr->tx_buf_ring[cons];
1646 if (tx_buf->mbuf == NULL)
1647 return RTE_ETH_TX_DESC_DONE;
1649 return RTE_ETH_TX_DESC_FULL;
1652 static struct bnxt_filter_info *
1653 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1654 struct rte_eth_ethertype_filter *efilter,
1655 struct bnxt_vnic_info *vnic0,
1656 struct bnxt_vnic_info *vnic,
1659 struct bnxt_filter_info *mfilter = NULL;
1663 if (efilter->ether_type != ETHER_TYPE_IPv4 &&
1664 efilter->ether_type != ETHER_TYPE_IPv6) {
1665 RTE_LOG(ERR, PMD, "unsupported ether_type(0x%04x) in"
1666 " ethertype filter.", efilter->ether_type);
1669 if (efilter->queue >= bp->rx_nr_rings) {
1670 RTE_LOG(ERR, PMD, "Invalid queue %d\n", efilter->queue);
1674 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1675 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1677 RTE_LOG(ERR, PMD, "Invalid queue %d\n", efilter->queue);
1681 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1682 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1683 if ((!memcmp(efilter->mac_addr.addr_bytes,
1684 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1686 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1687 mfilter->ethertype == efilter->ether_type)) {
1693 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1694 if ((!memcmp(efilter->mac_addr.addr_bytes,
1695 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1696 mfilter->ethertype == efilter->ether_type &&
1698 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
1711 bnxt_ethertype_filter(struct rte_eth_dev *dev,
1712 enum rte_filter_op filter_op,
1715 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1716 struct rte_eth_ethertype_filter *efilter =
1717 (struct rte_eth_ethertype_filter *)arg;
1718 struct bnxt_filter_info *bfilter, *filter1;
1719 struct bnxt_vnic_info *vnic, *vnic0;
1722 if (filter_op == RTE_ETH_FILTER_NOP)
1726 RTE_LOG(ERR, PMD, "arg shouldn't be NULL for operation %u.",
1731 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1732 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1734 switch (filter_op) {
1735 case RTE_ETH_FILTER_ADD:
1736 bnxt_match_and_validate_ether_filter(bp, efilter,
1741 bfilter = bnxt_get_unused_filter(bp);
1742 if (bfilter == NULL) {
1744 "Not enough resources for a new filter.\n");
1747 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
1748 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
1750 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
1752 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
1753 bfilter->ethertype = efilter->ether_type;
1754 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
1756 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
1757 if (filter1 == NULL) {
1762 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
1763 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
1765 bfilter->dst_id = vnic->fw_vnic_id;
1767 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1769 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
1772 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
1775 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
1777 case RTE_ETH_FILTER_DELETE:
1778 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
1780 if (ret == -EEXIST) {
1781 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
1783 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
1785 bnxt_free_filter(bp, filter1);
1786 } else if (ret == 0) {
1787 RTE_LOG(ERR, PMD, "No matching filter found\n");
1791 RTE_LOG(ERR, PMD, "unsupported operation %u.", filter_op);
1797 bnxt_free_filter(bp, bfilter);
1803 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
1804 enum rte_filter_type filter_type,
1805 enum rte_filter_op filter_op, void *arg)
1809 switch (filter_type) {
1810 case RTE_ETH_FILTER_NTUPLE:
1811 case RTE_ETH_FILTER_FDIR:
1812 case RTE_ETH_FILTER_TUNNEL:
1815 "filter type: %d: To be implemented\n", filter_type);
1817 case RTE_ETH_FILTER_ETHERTYPE:
1818 ret = bnxt_ethertype_filter(dev, filter_op, arg);
1820 case RTE_ETH_FILTER_GENERIC:
1821 if (filter_op != RTE_ETH_FILTER_GET)
1823 *(const void **)arg = &bnxt_flow_ops;
1827 "Filter type (%d) not supported", filter_type);
1834 static const uint32_t *
1835 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
1837 static const uint32_t ptypes[] = {
1838 RTE_PTYPE_L2_ETHER_VLAN,
1839 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1840 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1844 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1845 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1846 RTE_PTYPE_INNER_L4_ICMP,
1847 RTE_PTYPE_INNER_L4_TCP,
1848 RTE_PTYPE_INNER_L4_UDP,
1852 if (dev->rx_pkt_burst == bnxt_recv_pkts)
1860 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
1862 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1864 uint32_t dir_entries;
1865 uint32_t entry_length;
1867 RTE_LOG(INFO, PMD, "%s(): %04x:%02x:%02x:%02x\n",
1868 __func__, bp->pdev->addr.domain, bp->pdev->addr.bus,
1869 bp->pdev->addr.devid, bp->pdev->addr.function);
1871 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
1875 return dir_entries * entry_length;
1879 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
1880 struct rte_dev_eeprom_info *in_eeprom)
1882 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1886 RTE_LOG(INFO, PMD, "%s(): %04x:%02x:%02x:%02x in_eeprom->offset = %d "
1887 "len = %d\n", __func__, bp->pdev->addr.domain,
1888 bp->pdev->addr.bus, bp->pdev->addr.devid,
1889 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
1891 if (in_eeprom->offset == 0) /* special offset value to get directory */
1892 return bnxt_get_nvram_directory(bp, in_eeprom->length,
1895 index = in_eeprom->offset >> 24;
1896 offset = in_eeprom->offset & 0xffffff;
1899 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
1900 in_eeprom->length, in_eeprom->data);
1905 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
1908 case BNX_DIR_TYPE_CHIMP_PATCH:
1909 case BNX_DIR_TYPE_BOOTCODE:
1910 case BNX_DIR_TYPE_BOOTCODE_2:
1911 case BNX_DIR_TYPE_APE_FW:
1912 case BNX_DIR_TYPE_APE_PATCH:
1913 case BNX_DIR_TYPE_KONG_FW:
1914 case BNX_DIR_TYPE_KONG_PATCH:
1915 case BNX_DIR_TYPE_BONO_FW:
1916 case BNX_DIR_TYPE_BONO_PATCH:
1923 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
1926 case BNX_DIR_TYPE_AVS:
1927 case BNX_DIR_TYPE_EXP_ROM_MBA:
1928 case BNX_DIR_TYPE_PCIE:
1929 case BNX_DIR_TYPE_TSCF_UCODE:
1930 case BNX_DIR_TYPE_EXT_PHY:
1931 case BNX_DIR_TYPE_CCM:
1932 case BNX_DIR_TYPE_ISCSI_BOOT:
1933 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
1934 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
1941 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
1943 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
1944 bnxt_dir_type_is_other_exec_format(dir_type);
1948 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
1949 struct rte_dev_eeprom_info *in_eeprom)
1951 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1952 uint8_t index, dir_op;
1953 uint16_t type, ext, ordinal, attr;
1955 RTE_LOG(INFO, PMD, "%s(): %04x:%02x:%02x:%02x in_eeprom->offset = %d "
1956 "len = %d\n", __func__, bp->pdev->addr.domain,
1957 bp->pdev->addr.bus, bp->pdev->addr.devid,
1958 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
1961 RTE_LOG(ERR, PMD, "NVM write not supported from a VF\n");
1965 type = in_eeprom->magic >> 16;
1967 if (type == 0xffff) { /* special value for directory operations */
1968 index = in_eeprom->magic & 0xff;
1969 dir_op = in_eeprom->magic >> 8;
1973 case 0x0e: /* erase */
1974 if (in_eeprom->offset != ~in_eeprom->magic)
1976 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
1982 /* Create or re-write an NVM item: */
1983 if (bnxt_dir_type_is_executable(type) == true)
1985 ext = in_eeprom->magic & 0xffff;
1986 ordinal = in_eeprom->offset >> 16;
1987 attr = in_eeprom->offset & 0xffff;
1989 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
1990 in_eeprom->data, in_eeprom->length);
1998 static const struct eth_dev_ops bnxt_dev_ops = {
1999 .dev_infos_get = bnxt_dev_info_get_op,
2000 .dev_close = bnxt_dev_close_op,
2001 .dev_configure = bnxt_dev_configure_op,
2002 .dev_start = bnxt_dev_start_op,
2003 .dev_stop = bnxt_dev_stop_op,
2004 .dev_set_link_up = bnxt_dev_set_link_up_op,
2005 .dev_set_link_down = bnxt_dev_set_link_down_op,
2006 .stats_get = bnxt_stats_get_op,
2007 .stats_reset = bnxt_stats_reset_op,
2008 .rx_queue_setup = bnxt_rx_queue_setup_op,
2009 .rx_queue_release = bnxt_rx_queue_release_op,
2010 .tx_queue_setup = bnxt_tx_queue_setup_op,
2011 .tx_queue_release = bnxt_tx_queue_release_op,
2012 .reta_update = bnxt_reta_update_op,
2013 .reta_query = bnxt_reta_query_op,
2014 .rss_hash_update = bnxt_rss_hash_update_op,
2015 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
2016 .link_update = bnxt_link_update_op,
2017 .promiscuous_enable = bnxt_promiscuous_enable_op,
2018 .promiscuous_disable = bnxt_promiscuous_disable_op,
2019 .allmulticast_enable = bnxt_allmulticast_enable_op,
2020 .allmulticast_disable = bnxt_allmulticast_disable_op,
2021 .mac_addr_add = bnxt_mac_addr_add_op,
2022 .mac_addr_remove = bnxt_mac_addr_remove_op,
2023 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
2024 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
2025 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
2026 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
2027 .vlan_filter_set = bnxt_vlan_filter_set_op,
2028 .vlan_offload_set = bnxt_vlan_offload_set_op,
2029 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
2030 .mtu_set = bnxt_mtu_set_op,
2031 .mac_addr_set = bnxt_set_default_mac_addr_op,
2032 .xstats_get = bnxt_dev_xstats_get_op,
2033 .xstats_get_names = bnxt_dev_xstats_get_names_op,
2034 .xstats_reset = bnxt_dev_xstats_reset_op,
2035 .fw_version_get = bnxt_fw_version_get,
2036 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
2037 .rxq_info_get = bnxt_rxq_info_get_op,
2038 .txq_info_get = bnxt_txq_info_get_op,
2039 .dev_led_on = bnxt_dev_led_on_op,
2040 .dev_led_off = bnxt_dev_led_off_op,
2041 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
2042 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
2043 .rx_queue_count = bnxt_rx_queue_count_op,
2044 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
2045 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
2046 .filter_ctrl = bnxt_filter_ctrl_op,
2047 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
2048 .get_eeprom_length = bnxt_get_eeprom_length_op,
2049 .get_eeprom = bnxt_get_eeprom_op,
2050 .set_eeprom = bnxt_set_eeprom_op,
2053 static bool bnxt_vf_pciid(uint16_t id)
2055 if (id == BROADCOM_DEV_ID_57304_VF ||
2056 id == BROADCOM_DEV_ID_57406_VF ||
2057 id == BROADCOM_DEV_ID_5731X_VF ||
2058 id == BROADCOM_DEV_ID_5741X_VF ||
2059 id == BROADCOM_DEV_ID_57414_VF ||
2060 id == BROADCOM_DEV_ID_STRATUS_NIC_VF)
2065 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
2067 struct bnxt *bp = eth_dev->data->dev_private;
2068 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2071 /* enable device (incl. PCI PM wakeup), and bus-mastering */
2072 if (!pci_dev->mem_resource[0].addr) {
2074 "Cannot find PCI device base address, aborting\n");
2076 goto init_err_disable;
2079 bp->eth_dev = eth_dev;
2082 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
2084 RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n");
2086 goto init_err_release;
2099 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
2101 #define ALLOW_FUNC(x) \
2103 typeof(x) arg = (x); \
2104 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
2105 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
2108 bnxt_dev_init(struct rte_eth_dev *eth_dev)
2110 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2111 char mz_name[RTE_MEMZONE_NAMESIZE];
2112 const struct rte_memzone *mz = NULL;
2113 static int version_printed;
2114 uint32_t total_alloc_len;
2115 phys_addr_t mz_phys_addr;
2119 if (version_printed++ == 0)
2120 RTE_LOG(INFO, PMD, "%s\n", bnxt_version);
2122 rte_eth_copy_pci_info(eth_dev, pci_dev);
2123 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
2125 bp = eth_dev->data->dev_private;
2127 rte_atomic64_init(&bp->rx_mbuf_alloc_fail);
2128 bp->dev_stopped = 1;
2130 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2133 if (bnxt_vf_pciid(pci_dev->id.device_id))
2134 bp->flags |= BNXT_FLAG_VF;
2136 rc = bnxt_init_board(eth_dev);
2139 "Board initialization failed rc: %x\n", rc);
2143 eth_dev->dev_ops = &bnxt_dev_ops;
2144 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2146 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
2147 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
2149 if (BNXT_PF(bp) && pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
2150 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
2151 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
2152 pci_dev->addr.bus, pci_dev->addr.devid,
2153 pci_dev->addr.function, "rx_port_stats");
2154 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
2155 mz = rte_memzone_lookup(mz_name);
2156 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
2157 sizeof(struct rx_port_stats) + 512);
2159 mz = rte_memzone_reserve(mz_name, total_alloc_len,
2162 RTE_MEMZONE_SIZE_HINT_ONLY);
2166 memset(mz->addr, 0, mz->len);
2167 mz_phys_addr = mz->phys_addr;
2168 if ((unsigned long)mz->addr == mz_phys_addr) {
2169 RTE_LOG(WARNING, PMD,
2170 "Memzone physical address same as virtual.\n");
2171 RTE_LOG(WARNING, PMD,
2172 "Using rte_mem_virt2phy()\n");
2173 mz_phys_addr = rte_mem_virt2phy(mz->addr);
2174 if (mz_phys_addr == 0) {
2176 "unable to map address to physical memory\n");
2181 bp->rx_mem_zone = (const void *)mz;
2182 bp->hw_rx_port_stats = mz->addr;
2183 bp->hw_rx_port_stats_map = mz_phys_addr;
2185 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
2186 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
2187 pci_dev->addr.bus, pci_dev->addr.devid,
2188 pci_dev->addr.function, "tx_port_stats");
2189 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
2190 mz = rte_memzone_lookup(mz_name);
2191 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
2192 sizeof(struct tx_port_stats) + 512);
2194 mz = rte_memzone_reserve(mz_name, total_alloc_len,
2197 RTE_MEMZONE_SIZE_HINT_ONLY);
2201 memset(mz->addr, 0, mz->len);
2202 mz_phys_addr = mz->phys_addr;
2203 if ((unsigned long)mz->addr == mz_phys_addr) {
2204 RTE_LOG(WARNING, PMD,
2205 "Memzone physical address same as virtual.\n");
2206 RTE_LOG(WARNING, PMD,
2207 "Using rte_mem_virt2phy()\n");
2208 mz_phys_addr = rte_mem_virt2phy(mz->addr);
2209 if (mz_phys_addr == 0) {
2211 "unable to map address to physical memory\n");
2216 bp->tx_mem_zone = (const void *)mz;
2217 bp->hw_tx_port_stats = mz->addr;
2218 bp->hw_tx_port_stats_map = mz_phys_addr;
2220 bp->flags |= BNXT_FLAG_PORT_STATS;
2223 rc = bnxt_alloc_hwrm_resources(bp);
2226 "hwrm resource allocation failure rc: %x\n", rc);
2229 rc = bnxt_hwrm_ver_get(bp);
2232 bnxt_hwrm_queue_qportcfg(bp);
2234 bnxt_hwrm_func_qcfg(bp);
2236 /* Get the MAX capabilities for this function */
2237 rc = bnxt_hwrm_func_qcaps(bp);
2239 RTE_LOG(ERR, PMD, "hwrm query capability failure rc: %x\n", rc);
2242 if (bp->max_tx_rings == 0) {
2243 RTE_LOG(ERR, PMD, "No TX rings available!\n");
2247 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
2248 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR, 0);
2249 if (eth_dev->data->mac_addrs == NULL) {
2251 "Failed to alloc %u bytes needed to store MAC addr tbl",
2252 ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR);
2256 /* Copy the permanent MAC from the qcap response address now. */
2257 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
2258 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
2259 bp->grp_info = rte_zmalloc("bnxt_grp_info",
2260 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
2261 if (!bp->grp_info) {
2263 "Failed to alloc %zu bytes needed to store group info table\n",
2264 sizeof(*bp->grp_info) * bp->max_ring_grps);
2269 /* Forward all requests if firmware is new enough */
2270 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
2271 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
2272 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
2273 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
2275 RTE_LOG(WARNING, PMD,
2276 "Firmware too old for VF mailbox functionality\n");
2277 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
2281 * The following are used for driver cleanup. If we disallow these,
2282 * VF drivers can't clean up cleanly.
2284 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
2285 ALLOW_FUNC(HWRM_VNIC_FREE);
2286 ALLOW_FUNC(HWRM_RING_FREE);
2287 ALLOW_FUNC(HWRM_RING_GRP_FREE);
2288 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
2289 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
2290 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
2291 rc = bnxt_hwrm_func_driver_register(bp);
2294 "Failed to register driver");
2300 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
2301 pci_dev->mem_resource[0].phys_addr,
2302 pci_dev->mem_resource[0].addr);
2304 rc = bnxt_hwrm_func_reset(bp);
2306 RTE_LOG(ERR, PMD, "hwrm chip reset failure rc: %x\n", rc);
2312 //if (bp->pf.active_vfs) {
2313 // TODO: Deallocate VF resources?
2315 if (bp->pdev->max_vfs) {
2316 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
2318 RTE_LOG(ERR, PMD, "Failed to allocate VFs\n");
2322 rc = bnxt_hwrm_allocate_pf_only(bp);
2325 "Failed to allocate PF resources\n");
2331 bnxt_hwrm_port_led_qcaps(bp);
2333 rc = bnxt_setup_int(bp);
2337 rc = bnxt_alloc_mem(bp);
2339 goto error_free_int;
2341 rc = bnxt_request_int(bp);
2343 goto error_free_int;
2345 rc = bnxt_alloc_def_cp_ring(bp);
2347 goto error_free_int;
2349 bnxt_enable_int(bp);
2354 bnxt_disable_int(bp);
2355 bnxt_free_def_cp_ring(bp);
2356 bnxt_hwrm_func_buf_unrgtr(bp);
2360 bnxt_dev_uninit(eth_dev);
2366 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
2367 struct bnxt *bp = eth_dev->data->dev_private;
2370 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2373 bnxt_disable_int(bp);
2376 if (eth_dev->data->mac_addrs != NULL) {
2377 rte_free(eth_dev->data->mac_addrs);
2378 eth_dev->data->mac_addrs = NULL;
2380 if (bp->grp_info != NULL) {
2381 rte_free(bp->grp_info);
2382 bp->grp_info = NULL;
2384 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
2385 bnxt_free_hwrm_resources(bp);
2386 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
2387 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
2388 if (bp->dev_stopped == 0)
2389 bnxt_dev_close_op(eth_dev);
2391 rte_free(bp->pf.vf_info);
2392 eth_dev->dev_ops = NULL;
2393 eth_dev->rx_pkt_burst = NULL;
2394 eth_dev->tx_pkt_burst = NULL;
2399 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2400 struct rte_pci_device *pci_dev)
2402 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
2406 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
2408 return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
2411 static struct rte_pci_driver bnxt_rte_pmd = {
2412 .id_table = bnxt_pci_id_map,
2413 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
2414 RTE_PCI_DRV_INTR_LSC,
2415 .probe = bnxt_pci_probe,
2416 .remove = bnxt_pci_remove,
2420 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
2422 if (strcmp(dev->device->driver->name, drv->driver.name))
2428 bool is_bnxt_supported(struct rte_eth_dev *dev)
2430 return is_device_supported(dev, &bnxt_rte_pmd);
2433 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
2434 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
2435 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");