drivers/net/bnxt/bnxt_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) Broadcom Limited.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Broadcom Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <inttypes.h>
  35 #include <stdbool.h>
  36
  37 #include <rte_dev.h>
  38 #include <rte_ethdev.h>
  39 #include <rte_malloc.h>
  40 #include <rte_cycles.h>
  41
  42 #include "bnxt.h"
  43 #include "bnxt_cpr.h"
  44 #include "bnxt_filter.h"
  45 #include "bnxt_hwrm.h"
  46 #include "bnxt_ring.h"
  47 #include "bnxt_rxq.h"
  48 #include "bnxt_rxr.h"
  49 #include "bnxt_stats.h"
  50 #include "bnxt_txq.h"
  51 #include "bnxt_txr.h"
  52 #include "bnxt_vnic.h"
  53 #include "hsi_struct_def_dpdk.h"
  54
  55 #define DRV_MODULE_NAME         "bnxt"
  56 static const char bnxt_version[] =
  57         "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
  58
  59 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  60
  61 #define BROADCOM_DEV_ID_57301 0x16c8
  62 #define BROADCOM_DEV_ID_57302 0x16c9
  63 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  64 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  65 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  66 #define BROADCOM_DEV_ID_NS2 0x16cd
  67 #define BROADCOM_DEV_ID_57311 0x16ce
  68 #define BROADCOM_DEV_ID_57312 0x16cf
  69 #define BROADCOM_DEV_ID_57402 0x16d0
  70 #define BROADCOM_DEV_ID_57404 0x16d1
  71 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  72 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  73 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  74 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  75 #define BROADCOM_DEV_ID_57412 0x16d6
  76 #define BROADCOM_DEV_ID_57414 0x16d7
  77 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  78 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  79 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  80 #define BROADCOM_DEV_ID_57412_MF 0x16de
  81 #define BROADCOM_DEV_ID_57314 0x16df
  82 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  83 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  84 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  85 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  86 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  87 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  88 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  89 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  90 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  91 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  92 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  93
  94 static struct rte_pci_id bnxt_pci_id_map[] = {
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 127         { .vendor_id = 0, /* sentinel */ },
 128 };
 129
 130 #define BNXT_ETH_RSS_SUPPORT (  \
 131         ETH_RSS_IPV4 |          \
 132         ETH_RSS_NONFRAG_IPV4_TCP |      \
 133         ETH_RSS_NONFRAG_IPV4_UDP |      \
 134         ETH_RSS_IPV6 |          \
 135         ETH_RSS_NONFRAG_IPV6_TCP |      \
 136         ETH_RSS_NONFRAG_IPV6_UDP)
 137
 138 /***********************/
 139
 140 /*
 141  * High level utility functions
 142  */
 143
 144 static void bnxt_free_mem(struct bnxt *bp)
 145 {
 146         bnxt_free_filter_mem(bp);
 147         bnxt_free_vnic_attributes(bp);
 148         bnxt_free_vnic_mem(bp);
 149
 150         bnxt_free_stats(bp);
 151         bnxt_free_tx_rings(bp);
 152         bnxt_free_rx_rings(bp);
 153         bnxt_free_def_cp_ring(bp);
 154 }
 155
 156 static int bnxt_alloc_mem(struct bnxt *bp)
 157 {
 158         int rc;
 159
 160         /* Default completion ring */
 161         rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
 162         if (rc)
 163                 goto alloc_mem_err;
 164
 165         rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
 166                               bp->def_cp_ring, "def_cp");
 167         if (rc)
 168                 goto alloc_mem_err;
 169
 170         rc = bnxt_alloc_vnic_mem(bp);
 171         if (rc)
 172                 goto alloc_mem_err;
 173
 174         rc = bnxt_alloc_vnic_attributes(bp);
 175         if (rc)
 176                 goto alloc_mem_err;
 177
 178         rc = bnxt_alloc_filter_mem(bp);
 179         if (rc)
 180                 goto alloc_mem_err;
 181
 182         return 0;
 183
 184 alloc_mem_err:
 185         bnxt_free_mem(bp);
 186         return rc;
 187 }
 188
 189 static int bnxt_init_chip(struct bnxt *bp)
 190 {
 191         unsigned int i, rss_idx, fw_idx;
 192         int rc;
 193
 194         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 195         if (rc) {
 196                 RTE_LOG(ERR, PMD, "HWRM stat ctx alloc failure rc: %x\n", rc);
 197                 goto err_out;
 198         }
 199
 200         rc = bnxt_alloc_hwrm_rings(bp);
 201         if (rc) {
 202                 RTE_LOG(ERR, PMD, "HWRM ring alloc failure rc: %x\n", rc);
 203                 goto err_out;
 204         }
 205
 206         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 207         if (rc) {
 208                 RTE_LOG(ERR, PMD, "HWRM ring grp alloc failure: %x\n", rc);
 209                 goto err_out;
 210         }
 211
 212         rc = bnxt_mq_rx_configure(bp);
 213         if (rc) {
 214                 RTE_LOG(ERR, PMD, "MQ mode configure failure rc: %x\n", rc);
 215                 goto err_out;
 216         }
 217
 218         /* VNIC configuration */
 219         for (i = 0; i < bp->nr_vnics; i++) {
 220                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 221
 222                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 223                 if (rc) {
 224                         RTE_LOG(ERR, PMD, "HWRM vnic alloc failure rc: %x\n",
 225                                 rc);
 226                         goto err_out;
 227                 }
 228
 229                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
 230                 if (rc) {
 231                         RTE_LOG(ERR, PMD,
 232                                 "HWRM vnic ctx alloc failure rc: %x\n", rc);
 233                         goto err_out;
 234                 }
 235
 236                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 237                 if (rc) {
 238                         RTE_LOG(ERR, PMD, "HWRM vnic cfg failure rc: %x\n", rc);
 239                         goto err_out;
 240                 }
 241
 242                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 243                 if (rc) {
 244                         RTE_LOG(ERR, PMD, "HWRM vnic filter failure rc: %x\n",
 245                                 rc);
 246                         goto err_out;
 247                 }
 248                 if (vnic->rss_table && vnic->hash_type) {
 249                         /*
 250                          * Fill the RSS hash & redirection table with
 251                          * ring group ids for all VNICs
 252                          */
 253                         for (rss_idx = 0, fw_idx = 0;
 254                              rss_idx < HW_HASH_INDEX_SIZE;
 255                              rss_idx++, fw_idx++) {
 256                                 if (vnic->fw_grp_ids[fw_idx] ==
 257                                     INVALID_HW_RING_ID)
 258                                         fw_idx = 0;
 259                                 vnic->rss_table[rss_idx] =
 260                                                 vnic->fw_grp_ids[fw_idx];
 261                         }
 262                         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 263                         if (rc) {
 264                                 RTE_LOG(ERR, PMD,
 265                                         "HWRM vnic set RSS failure rc: %x\n",
 266                                         rc);
 267                                 goto err_out;
 268                         }
 269                 }
 270         }
 271         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0]);
 272         if (rc) {
 273                 RTE_LOG(ERR, PMD,
 274                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 275                 goto err_out;
 276         }
 277
 278         return 0;
 279
 280 err_out:
 281         bnxt_free_all_hwrm_resources(bp);
 282
 283         return rc;
 284 }
 285
 286 static int bnxt_shutdown_nic(struct bnxt *bp)
 287 {
 288         bnxt_free_all_hwrm_resources(bp);
 289         bnxt_free_all_filters(bp);
 290         bnxt_free_all_vnics(bp);
 291         return 0;
 292 }
 293
 294 static int bnxt_init_nic(struct bnxt *bp)
 295 {
 296         int rc;
 297
 298         bnxt_init_ring_grps(bp);
 299         bnxt_init_vnics(bp);
 300         bnxt_init_filters(bp);
 301
 302         rc = bnxt_init_chip(bp);
 303         if (rc)
 304                 return rc;
 305
 306         return 0;
 307 }
 308
 309 /*
 310  * Device configuration and status function
 311  */
 312
 313 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 314                                   struct rte_eth_dev_info *dev_info)
 315 {
 316         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 317         uint16_t max_vnics, i, j, vpool, vrxq;
 318
 319         /* MAC Specifics */
 320         dev_info->max_mac_addrs = MAX_NUM_MAC_ADDR;
 321         dev_info->max_hash_mac_addrs = 0;
 322
 323         /* PF/VF specifics */
 324         if (BNXT_PF(bp)) {
 325                 dev_info->max_rx_queues = bp->pf.max_rx_rings;
 326                 dev_info->max_tx_queues = bp->pf.max_tx_rings;
 327                 dev_info->max_vfs = bp->pf.active_vfs;
 328                 dev_info->reta_size = bp->pf.max_rsscos_ctx;
 329                 max_vnics = bp->pf.max_vnics;
 330         } else {
 331                 dev_info->max_rx_queues = bp->vf.max_rx_rings;
 332                 dev_info->max_tx_queues = bp->vf.max_tx_rings;
 333                 dev_info->reta_size = bp->vf.max_rsscos_ctx;
 334                 max_vnics = bp->vf.max_vnics;
 335         }
 336
 337         /* Fast path specifics */
 338         dev_info->min_rx_bufsize = 1;
 339         dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
 340                                   + VLAN_TAG_SIZE;
 341         dev_info->rx_offload_capa = 0;
 342         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
 343                                         DEV_TX_OFFLOAD_TCP_CKSUM |
 344                                         DEV_TX_OFFLOAD_UDP_CKSUM |
 345                                         DEV_TX_OFFLOAD_TCP_TSO;
 346
 347         /* *INDENT-OFF* */
 348         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 349                 .rx_thresh = {
 350                         .pthresh = 8,
 351                         .hthresh = 8,
 352                         .wthresh = 0,
 353                 },
 354                 .rx_free_thresh = 32,
 355                 .rx_drop_en = 0,
 356         };
 357
 358         dev_info->default_txconf = (struct rte_eth_txconf) {
 359                 .tx_thresh = {
 360                         .pthresh = 32,
 361                         .hthresh = 0,
 362                         .wthresh = 0,
 363                 },
 364                 .tx_free_thresh = 32,
 365                 .tx_rs_thresh = 32,
 366                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
 367                              ETH_TXQ_FLAGS_NOOFFLOADS,
 368         };
 369         /* *INDENT-ON* */
 370
 371         /*
 372          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 373          *       need further investigation.
 374          */
 375
 376         /* VMDq resources */
 377         vpool = 64; /* ETH_64_POOLS */
 378         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 379         for (i = 0; i < 4; vpool >>= 1, i++) {
 380                 if (max_vnics > vpool) {
 381                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 382                                 if (dev_info->max_rx_queues > vrxq) {
 383                                         if (vpool > vrxq)
 384                                                 vpool = vrxq;
 385                                         goto found;
 386                                 }
 387                         }
 388                         /* Not enough resources to support VMDq */
 389                         break;
 390                 }
 391         }
 392         /* Not enough resources to support VMDq */
 393         vpool = 0;
 394         vrxq = 0;
 395 found:
 396         dev_info->max_vmdq_pools = vpool;
 397         dev_info->vmdq_queue_num = vrxq;
 398
 399         dev_info->vmdq_pool_base = 0;
 400         dev_info->vmdq_queue_base = 0;
 401 }
 402
 403 /* Configure the device based on the configuration provided */
 404 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 405 {
 406         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 407         int rc;
 408
 409         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 410         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 411
 412         /* Inherit new configurations */
 413         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 414         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 415         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 416         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 417
 418         if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
 419                 eth_dev->data->mtu =
 420                                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 421                                 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
 422         rc = bnxt_set_hwrm_link_config(bp, true);
 423         return rc;
 424 }
 425
 426 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 427 {
 428         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 429         int rc;
 430
 431         bp->dev_stopped = 0;
 432         rc = bnxt_hwrm_func_reset(bp);
 433         if (rc) {
 434                 RTE_LOG(ERR, PMD, "hwrm chip reset failure rc: %x\n", rc);
 435                 rc = -1;
 436                 goto error;
 437         }
 438
 439         rc = bnxt_alloc_mem(bp);
 440         if (rc)
 441                 goto error;
 442
 443         rc = bnxt_init_nic(bp);
 444         if (rc)
 445                 goto error;
 446
 447         return 0;
 448
 449 error:
 450         bnxt_shutdown_nic(bp);
 451         bnxt_free_tx_mbufs(bp);
 452         bnxt_free_rx_mbufs(bp);
 453         bnxt_free_mem(bp);
 454         return rc;
 455 }
 456
 457 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 458 {
 459         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 460
 461         eth_dev->data->dev_link.link_status = 1;
 462         bnxt_set_hwrm_link_config(bp, true);
 463         return 0;
 464 }
 465
 466 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 467 {
 468         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 469
 470         eth_dev->data->dev_link.link_status = 0;
 471         bnxt_set_hwrm_link_config(bp, false);
 472         return 0;
 473 }
 474
 475 /* Unload the driver, release resources */
 476 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 477 {
 478         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 479
 480         if (bp->eth_dev->data->dev_started) {
 481                 /* TBD: STOP HW queues DMA */
 482                 eth_dev->data->dev_link.link_status = 0;
 483         }
 484         bnxt_set_hwrm_link_config(bp, false);
 485         bnxt_shutdown_nic(bp);
 486         bp->dev_stopped = 1;
 487 }
 488
 489 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 490 {
 491         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 492
 493         if (bp->dev_stopped == 0)
 494                 bnxt_dev_stop_op(eth_dev);
 495
 496         bnxt_free_tx_mbufs(bp);
 497         bnxt_free_rx_mbufs(bp);
 498         bnxt_free_mem(bp);
 499         if (eth_dev->data->mac_addrs != NULL) {
 500                 rte_free(eth_dev->data->mac_addrs);
 501                 eth_dev->data->mac_addrs = NULL;
 502         }
 503         if (bp->grp_info != NULL) {
 504                 rte_free(bp->grp_info);
 505                 bp->grp_info = NULL;
 506         }
 507 }
 508
 509 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
 510                                     uint32_t index)
 511 {
 512         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 513         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
 514         struct bnxt_vnic_info *vnic;
 515         struct bnxt_filter_info *filter, *temp_filter;
 516         int i;
 517
 518         /*
 519          * Loop through all VNICs from the specified filter flow pools to
 520          * remove the corresponding MAC addr filter
 521          */
 522         for (i = 0; i < MAX_FF_POOLS; i++) {
 523                 if (!(pool_mask & (1ULL << i)))
 524                         continue;
 525
 526                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 527                         filter = STAILQ_FIRST(&vnic->filter);
 528                         while (filter) {
 529                                 temp_filter = STAILQ_NEXT(filter, next);
 530                                 if (filter->mac_index == index) {
 531                                         STAILQ_REMOVE(&vnic->filter, filter,
 532                                                       bnxt_filter_info, next);
 533                                         bnxt_hwrm_clear_filter(bp, filter);
 534                                         filter->mac_index = INVALID_MAC_INDEX;
 535                                         memset(&filter->l2_addr, 0,
 536                                                ETHER_ADDR_LEN);
 537                                         STAILQ_INSERT_TAIL(
 538                                                         &bp->free_filter_list,
 539                                                         filter, next);
 540                                 }
 541                                 filter = temp_filter;
 542                         }
 543                 }
 544         }
 545 }
 546
 547 static void bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
 548                                  struct ether_addr *mac_addr,
 549                                  uint32_t index, uint32_t pool)
 550 {
 551         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 552         struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
 553         struct bnxt_filter_info *filter;
 554
 555         if (BNXT_VF(bp)) {
 556                 RTE_LOG(ERR, PMD, "Cannot add MAC address to a VF interface\n");
 557                 return;
 558         }
 559
 560         if (!vnic) {
 561                 RTE_LOG(ERR, PMD, "VNIC not found for pool %d!\n", pool);
 562                 return;
 563         }
 564         /* Attach requested MAC address to the new l2_filter */
 565         STAILQ_FOREACH(filter, &vnic->filter, next) {
 566                 if (filter->mac_index == index) {
 567                         RTE_LOG(ERR, PMD,
 568                                 "MAC addr already existed for pool %d\n", pool);
 569                         return;
 570                 }
 571         }
 572         filter = bnxt_alloc_filter(bp);
 573         if (!filter) {
 574                 RTE_LOG(ERR, PMD, "L2 filter alloc failed\n");
 575                 return;
 576         }
 577         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
 578         filter->mac_index = index;
 579         memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
 580         bnxt_hwrm_set_filter(bp, vnic, filter);
 581 }
 582
 583 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
 584                                int wait_to_complete)
 585 {
 586         int rc = 0;
 587         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 588         struct rte_eth_link new;
 589         unsigned int cnt = BNXT_LINK_WAIT_CNT;
 590
 591         memset(&new, 0, sizeof(new));
 592         do {
 593                 /* Retrieve link info from hardware */
 594                 rc = bnxt_get_hwrm_link_config(bp, &new);
 595                 if (rc) {
 596                         new.link_speed = ETH_LINK_SPEED_100M;
 597                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
 598                         RTE_LOG(ERR, PMD,
 599                                 "Failed to retrieve link rc = 0x%x!", rc);
 600                         goto out;
 601                 }
 602                 if (!wait_to_complete)
 603                         break;
 604
 605                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
 606
 607         } while (!new.link_status && cnt--);
 608
 609         /* Timed out or success */
 610         if (new.link_status) {
 611                 /* Update only if success */
 612                 eth_dev->data->dev_link.link_duplex = new.link_duplex;
 613                 eth_dev->data->dev_link.link_speed = new.link_speed;
 614         }
 615         eth_dev->data->dev_link.link_status = new.link_status;
 616 out:
 617         return rc;
 618 }
 619
 620 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
 621 {
 622         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 623         struct bnxt_vnic_info *vnic;
 624
 625         if (bp->vnic_info == NULL)
 626                 return;
 627
 628         vnic = &bp->vnic_info[0];
 629
 630         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
 631         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
 632 }
 633
 634 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
 635 {
 636         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 637         struct bnxt_vnic_info *vnic;
 638
 639         if (bp->vnic_info == NULL)
 640                 return;
 641
 642         vnic = &bp->vnic_info[0];
 643
 644         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
 645         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
 646 }
 647
 648 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
 649 {
 650         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 651         struct bnxt_vnic_info *vnic;
 652
 653         if (bp->vnic_info == NULL)
 654                 return;
 655
 656         vnic = &bp->vnic_info[0];
 657
 658         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
 659         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
 660 }
 661
 662 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
 663 {
 664         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 665         struct bnxt_vnic_info *vnic;
 666
 667         if (bp->vnic_info == NULL)
 668                 return;
 669
 670         vnic = &bp->vnic_info[0];
 671
 672         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
 673         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
 674 }
 675
 676 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
 677                             struct rte_eth_rss_reta_entry64 *reta_conf,
 678                             uint16_t reta_size)
 679 {
 680         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 681         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 682         struct bnxt_vnic_info *vnic;
 683         int i;
 684
 685         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
 686                 return -EINVAL;
 687
 688         if (reta_size != HW_HASH_INDEX_SIZE) {
 689                 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
 690                         "(%d) must equal the size supported by the hardware "
 691                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 692                 return -EINVAL;
 693         }
 694         /* Update the RSS VNIC(s) */
 695         for (i = 0; i < MAX_FF_POOLS; i++) {
 696                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 697                         memcpy(vnic->rss_table, reta_conf, reta_size);
 698
 699                         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 700                 }
 701         }
 702         return 0;
 703 }
 704
 705 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
 706                               struct rte_eth_rss_reta_entry64 *reta_conf,
 707                               uint16_t reta_size)
 708 {
 709         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 710         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
 711
 712         /* Retrieve from the default VNIC */
 713         if (!vnic)
 714                 return -EINVAL;
 715         if (!vnic->rss_table)
 716                 return -EINVAL;
 717
 718         if (reta_size != HW_HASH_INDEX_SIZE) {
 719                 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
 720                         "(%d) must equal the size supported by the hardware "
 721                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
 722                 return -EINVAL;
 723         }
 724         /* EW - need to revisit here copying from u64 to u16 */
 725         memcpy(reta_conf, vnic->rss_table, reta_size);
 726
 727         return 0;
 728 }
 729
 730 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
 731                                    struct rte_eth_rss_conf *rss_conf)
 732 {
 733         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 734         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 735         struct bnxt_vnic_info *vnic;
 736         uint16_t hash_type = 0;
 737         int i;
 738
 739         /*
 740          * If RSS enablement were different than dev_configure,
 741          * then return -EINVAL
 742          */
 743         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
 744                 if (!rss_conf->rss_hf)
 745                         return -EINVAL;
 746         } else {
 747                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
 748                         return -EINVAL;
 749         }
 750         if (rss_conf->rss_hf & ETH_RSS_IPV4)
 751                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
 752         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
 753                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
 754         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
 755                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
 756         if (rss_conf->rss_hf & ETH_RSS_IPV6)
 757                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
 758         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
 759                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
 760         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
 761                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
 762
 763         /* Update the RSS VNIC(s) */
 764         for (i = 0; i < MAX_FF_POOLS; i++) {
 765                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
 766                         vnic->hash_type = hash_type;
 767
 768                         /*
 769                          * Use the supplied key if the key length is
 770                          * acceptable and the rss_key is not NULL
 771                          */
 772                         if (rss_conf->rss_key &&
 773                             rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
 774                                 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
 775                                        rss_conf->rss_key_len);
 776
 777                         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
 778                 }
 779         }
 780         return 0;
 781 }
 782
 783 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
 784                                      struct rte_eth_rss_conf *rss_conf)
 785 {
 786         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
 787         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
 788         int len;
 789         uint32_t hash_types;
 790
 791         /* RSS configuration is the same for all VNICs */
 792         if (vnic && vnic->rss_hash_key) {
 793                 if (rss_conf->rss_key) {
 794                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
 795                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
 796                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
 797                 }
 798
 799                 hash_types = vnic->hash_type;
 800                 rss_conf->rss_hf = 0;
 801                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
 802                         rss_conf->rss_hf |= ETH_RSS_IPV4;
 803                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
 804                 }
 805                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
 806                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
 807                         hash_types &=
 808                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
 809                 }
 810                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
 811                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
 812                         hash_types &=
 813                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
 814                 }
 815                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
 816                         rss_conf->rss_hf |= ETH_RSS_IPV6;
 817                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
 818                 }
 819                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
 820                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
 821                         hash_types &=
 822                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
 823                 }
 824                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
 825                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
 826                         hash_types &=
 827                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
 828                 }
 829                 if (hash_types) {
 830                         RTE_LOG(ERR, PMD,
 831                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
 832                                 vnic->hash_type);
 833                         return -ENOTSUP;
 834                 }
 835         } else {
 836                 rss_conf->rss_hf = 0;
 837         }
 838         return 0;
 839 }
 840
 841 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
 842                                struct rte_eth_fc_conf *fc_conf __rte_unused)
 843 {
 844         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
 845         struct rte_eth_link link_info;
 846         int rc;
 847
 848         rc = bnxt_get_hwrm_link_config(bp, &link_info);
 849         if (rc)
 850                 return rc;
 851
 852         memset(fc_conf, 0, sizeof(*fc_conf));
 853         if (bp->link_info.auto_pause)
 854                 fc_conf->autoneg = 1;
 855         switch (bp->link_info.pause) {
 856         case 0:
 857                 fc_conf->mode = RTE_FC_NONE;
 858                 break;
 859         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
 860                 fc_conf->mode = RTE_FC_TX_PAUSE;
 861                 break;
 862         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
 863                 fc_conf->mode = RTE_FC_RX_PAUSE;
 864                 break;
 865         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
 866                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
 867                 fc_conf->mode = RTE_FC_FULL;
 868                 break;
 869         }
 870         return 0;
 871 }
 872
 873 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
 874                                struct rte_eth_fc_conf *fc_conf)
 875 {
 876         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
 877
 878         if (BNXT_NPAR_PF(bp) || BNXT_VF(bp)) {
 879                 RTE_LOG(ERR, PMD, "Flow Control Settings cannot be modified\n");
 880                 return -ENOTSUP;
 881         }
 882
 883         switch (fc_conf->mode) {
 884         case RTE_FC_NONE:
 885                 bp->link_info.auto_pause = 0;
 886                 bp->link_info.force_pause = 0;
 887                 break;
 888         case RTE_FC_RX_PAUSE:
 889                 if (fc_conf->autoneg) {
 890                         bp->link_info.auto_pause =
 891                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
 892                         bp->link_info.force_pause = 0;
 893                 } else {
 894                         bp->link_info.auto_pause = 0;
 895                         bp->link_info.force_pause =
 896                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
 897                 }
 898                 break;
 899         case RTE_FC_TX_PAUSE:
 900                 if (fc_conf->autoneg) {
 901                         bp->link_info.auto_pause =
 902                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
 903                         bp->link_info.force_pause = 0;
 904                 } else {
 905                         bp->link_info.auto_pause = 0;
 906                         bp->link_info.force_pause =
 907                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
 908                 }
 909                 break;
 910         case RTE_FC_FULL:
 911                 if (fc_conf->autoneg) {
 912                         bp->link_info.auto_pause =
 913                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
 914                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
 915                         bp->link_info.force_pause = 0;
 916                 } else {
 917                         bp->link_info.auto_pause = 0;
 918                         bp->link_info.force_pause =
 919                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
 920                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
 921                 }
 922                 break;
 923         }
 924         return bnxt_set_hwrm_link_config(bp, true);
 925 }
 926
 927 /*
 928  * Initialization
 929  */
 930
 931 static struct eth_dev_ops bnxt_dev_ops = {
 932         .dev_infos_get = bnxt_dev_info_get_op,
 933         .dev_close = bnxt_dev_close_op,
 934         .dev_configure = bnxt_dev_configure_op,
 935         .dev_start = bnxt_dev_start_op,
 936         .dev_stop = bnxt_dev_stop_op,
 937         .dev_set_link_up = bnxt_dev_set_link_up_op,
 938         .dev_set_link_down = bnxt_dev_set_link_down_op,
 939         .stats_get = bnxt_stats_get_op,
 940         .stats_reset = bnxt_stats_reset_op,
 941         .rx_queue_setup = bnxt_rx_queue_setup_op,
 942         .rx_queue_release = bnxt_rx_queue_release_op,
 943         .tx_queue_setup = bnxt_tx_queue_setup_op,
 944         .tx_queue_release = bnxt_tx_queue_release_op,
 945         .reta_update = bnxt_reta_update_op,
 946         .reta_query = bnxt_reta_query_op,
 947         .rss_hash_update = bnxt_rss_hash_update_op,
 948         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
 949         .link_update = bnxt_link_update_op,
 950         .promiscuous_enable = bnxt_promiscuous_enable_op,
 951         .promiscuous_disable = bnxt_promiscuous_disable_op,
 952         .allmulticast_enable = bnxt_allmulticast_enable_op,
 953         .allmulticast_disable = bnxt_allmulticast_disable_op,
 954         .mac_addr_add = bnxt_mac_addr_add_op,
 955         .mac_addr_remove = bnxt_mac_addr_remove_op,
 956         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
 957         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
 958 };
 959
 960 static bool bnxt_vf_pciid(uint16_t id)
 961 {
 962         if (id == BROADCOM_DEV_ID_57304_VF ||
 963             id == BROADCOM_DEV_ID_57406_VF ||
 964             id == BROADCOM_DEV_ID_5731X_VF ||
 965             id == BROADCOM_DEV_ID_5741X_VF)
 966                 return true;
 967         return false;
 968 }
 969
 970 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
 971 {
 972         int rc;
 973         struct bnxt *bp = eth_dev->data->dev_private;
 974
 975         /* enable device (incl. PCI PM wakeup), and bus-mastering */
 976         if (!eth_dev->pci_dev->mem_resource[0].addr) {
 977                 RTE_LOG(ERR, PMD,
 978                         "Cannot find PCI device base address, aborting\n");
 979                 rc = -ENODEV;
 980                 goto init_err_disable;
 981         }
 982
 983         bp->eth_dev = eth_dev;
 984         bp->pdev = eth_dev->pci_dev;
 985
 986         bp->bar0 = (void *)eth_dev->pci_dev->mem_resource[0].addr;
 987         if (!bp->bar0) {
 988                 RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n");
 989                 rc = -ENOMEM;
 990                 goto init_err_release;
 991         }
 992         return 0;
 993
 994 init_err_release:
 995         if (bp->bar0)
 996                 bp->bar0 = NULL;
 997
 998 init_err_disable:
 999
1000         return rc;
1001 }
1002
1003 static int
1004 bnxt_dev_init(struct rte_eth_dev *eth_dev)
1005 {
1006         static int version_printed;
1007         struct bnxt *bp;
1008         int rc;
1009
1010         if (version_printed++ == 0)
1011                 RTE_LOG(INFO, PMD, "%s", bnxt_version);
1012
1013         rte_eth_copy_pci_info(eth_dev, eth_dev->pci_dev);
1014         bp = eth_dev->data->dev_private;
1015
1016         if (bnxt_vf_pciid(eth_dev->pci_dev->id.device_id))
1017                 bp->flags |= BNXT_FLAG_VF;
1018
1019         rc = bnxt_init_board(eth_dev);
1020         if (rc) {
1021                 RTE_LOG(ERR, PMD,
1022                         "Board initialization failed rc: %x\n", rc);
1023                 goto error;
1024         }
1025         eth_dev->dev_ops = &bnxt_dev_ops;
1026         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
1027         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
1028
1029         rc = bnxt_alloc_hwrm_resources(bp);
1030         if (rc) {
1031                 RTE_LOG(ERR, PMD,
1032                         "hwrm resource allocation failure rc: %x\n", rc);
1033                 goto error_free;
1034         }
1035         rc = bnxt_hwrm_ver_get(bp);
1036         if (rc)
1037                 goto error_free;
1038         bnxt_hwrm_queue_qportcfg(bp);
1039
1040         bnxt_hwrm_func_qcfg(bp);
1041
1042         /* Get the MAX capabilities for this function */
1043         rc = bnxt_hwrm_func_qcaps(bp);
1044         if (rc) {
1045                 RTE_LOG(ERR, PMD, "hwrm query capability failure rc: %x\n", rc);
1046                 goto error_free;
1047         }
1048         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
1049                                         ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR, 0);
1050         if (eth_dev->data->mac_addrs == NULL) {
1051                 RTE_LOG(ERR, PMD,
1052                         "Failed to alloc %u bytes needed to store MAC addr tbl",
1053                         ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR);
1054                 rc = -ENOMEM;
1055                 goto error_free;
1056         }
1057         /* Copy the permanent MAC from the qcap response address now. */
1058         if (BNXT_PF(bp))
1059                 memcpy(bp->mac_addr, bp->pf.mac_addr, sizeof(bp->mac_addr));
1060         else
1061                 memcpy(bp->mac_addr, bp->vf.mac_addr, sizeof(bp->mac_addr));
1062         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
1063         bp->grp_info = rte_zmalloc("bnxt_grp_info",
1064                                 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
1065         if (!bp->grp_info) {
1066                 RTE_LOG(ERR, PMD,
1067                         "Failed to alloc %zu bytes needed to store group info table\n",
1068                         sizeof(*bp->grp_info) * bp->max_ring_grps);
1069                 rc = -ENOMEM;
1070                 goto error_free;
1071         }
1072
1073         rc = bnxt_hwrm_func_driver_register(bp, 0,
1074                                             bp->pf.vf_req_fwd);
1075         if (rc) {
1076                 RTE_LOG(ERR, PMD,
1077                         "Failed to register driver");
1078                 rc = -EBUSY;
1079                 goto error_free;
1080         }
1081
1082         RTE_LOG(INFO, PMD,
1083                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
1084                 eth_dev->pci_dev->mem_resource[0].phys_addr,
1085                 eth_dev->pci_dev->mem_resource[0].addr);
1086
1087         bp->dev_stopped = 0;
1088
1089         return 0;
1090
1091 error_free:
1092         eth_dev->driver->eth_dev_uninit(eth_dev);
1093 error:
1094         return rc;
1095 }
1096
1097 static int
1098 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
1099         struct bnxt *bp = eth_dev->data->dev_private;
1100         int rc;
1101
1102         if (eth_dev->data->mac_addrs != NULL) {
1103                 rte_free(eth_dev->data->mac_addrs);
1104                 eth_dev->data->mac_addrs = NULL;
1105         }
1106         if (bp->grp_info != NULL) {
1107                 rte_free(bp->grp_info);
1108                 bp->grp_info = NULL;
1109         }
1110         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
1111         bnxt_free_hwrm_resources(bp);
1112         if (bp->dev_stopped == 0)
1113                 bnxt_dev_close_op(eth_dev);
1114         eth_dev->dev_ops = NULL;
1115         eth_dev->rx_pkt_burst = NULL;
1116         eth_dev->tx_pkt_burst = NULL;
1117
1118         return rc;
1119 }
1120
1121 static struct eth_driver bnxt_rte_pmd = {
1122         .pci_drv = {
1123                     .id_table = bnxt_pci_id_map,
1124                     .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
1125                             RTE_PCI_DRV_DETACHABLE,
1126                     .probe = rte_eth_dev_pci_probe,
1127                     .remove = rte_eth_dev_pci_remove
1128                     },
1129         .eth_dev_init = bnxt_dev_init,
1130         .eth_dev_uninit = bnxt_dev_uninit,
1131         .dev_private_size = sizeof(struct bnxt),
1132 };
1133
1134 DRIVER_REGISTER_PCI(net_bnxt, bnxt_rte_pmd.pci_drv);
1135 DRIVER_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);