1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
18 #include "bnxt_filter.h"
19 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_stats.h"
27 #include "bnxt_vnic.h"
28 #include "hsi_struct_def_dpdk.h"
29 #include "bnxt_nvm_defs.h"
30 #include "bnxt_util.h"
32 #define DRV_MODULE_NAME "bnxt"
33 static const char bnxt_version[] =
34 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
35 int bnxt_logtype_driver;
37 #define PCI_VENDOR_ID_BROADCOM 0x14E4
39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
40 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
41 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
42 #define BROADCOM_DEV_ID_57414_VF 0x16c1
43 #define BROADCOM_DEV_ID_57301 0x16c8
44 #define BROADCOM_DEV_ID_57302 0x16c9
45 #define BROADCOM_DEV_ID_57304_PF 0x16ca
46 #define BROADCOM_DEV_ID_57304_VF 0x16cb
47 #define BROADCOM_DEV_ID_57417_MF 0x16cc
48 #define BROADCOM_DEV_ID_NS2 0x16cd
49 #define BROADCOM_DEV_ID_57311 0x16ce
50 #define BROADCOM_DEV_ID_57312 0x16cf
51 #define BROADCOM_DEV_ID_57402 0x16d0
52 #define BROADCOM_DEV_ID_57404 0x16d1
53 #define BROADCOM_DEV_ID_57406_PF 0x16d2
54 #define BROADCOM_DEV_ID_57406_VF 0x16d3
55 #define BROADCOM_DEV_ID_57402_MF 0x16d4
56 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
57 #define BROADCOM_DEV_ID_57412 0x16d6
58 #define BROADCOM_DEV_ID_57414 0x16d7
59 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
60 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
61 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
62 #define BROADCOM_DEV_ID_57412_MF 0x16de
63 #define BROADCOM_DEV_ID_57314 0x16df
64 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
65 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
66 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
67 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
68 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
69 #define BROADCOM_DEV_ID_57404_MF 0x16e7
70 #define BROADCOM_DEV_ID_57406_MF 0x16e8
71 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
72 #define BROADCOM_DEV_ID_57407_MF 0x16ea
73 #define BROADCOM_DEV_ID_57414_MF 0x16ec
74 #define BROADCOM_DEV_ID_57416_MF 0x16ee
75 #define BROADCOM_DEV_ID_57508 0x1750
76 #define BROADCOM_DEV_ID_57504 0x1751
77 #define BROADCOM_DEV_ID_57502 0x1752
78 #define BROADCOM_DEV_ID_57500_VF1 0x1806
79 #define BROADCOM_DEV_ID_57500_VF2 0x1807
80 #define BROADCOM_DEV_ID_58802 0xd802
81 #define BROADCOM_DEV_ID_58804 0xd804
82 #define BROADCOM_DEV_ID_58808 0x16f0
83 #define BROADCOM_DEV_ID_58802_VF 0xd800
85 static const struct rte_pci_id bnxt_pci_id_map[] = {
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
87 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
89 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
130 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
131 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
132 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
133 { .vendor_id = 0, /* sentinel */ },
136 #define BNXT_ETH_RSS_SUPPORT ( \
138 ETH_RSS_NONFRAG_IPV4_TCP | \
139 ETH_RSS_NONFRAG_IPV4_UDP | \
141 ETH_RSS_NONFRAG_IPV6_TCP | \
142 ETH_RSS_NONFRAG_IPV6_UDP)
144 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
145 DEV_TX_OFFLOAD_IPV4_CKSUM | \
146 DEV_TX_OFFLOAD_TCP_CKSUM | \
147 DEV_TX_OFFLOAD_UDP_CKSUM | \
148 DEV_TX_OFFLOAD_TCP_TSO | \
149 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
150 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
151 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
152 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
153 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
154 DEV_TX_OFFLOAD_QINQ_INSERT | \
155 DEV_TX_OFFLOAD_MULTI_SEGS)
157 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
158 DEV_RX_OFFLOAD_VLAN_STRIP | \
159 DEV_RX_OFFLOAD_IPV4_CKSUM | \
160 DEV_RX_OFFLOAD_UDP_CKSUM | \
161 DEV_RX_OFFLOAD_TCP_CKSUM | \
162 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
163 DEV_RX_OFFLOAD_JUMBO_FRAME | \
164 DEV_RX_OFFLOAD_KEEP_CRC | \
165 DEV_RX_OFFLOAD_VLAN_EXTEND | \
166 DEV_RX_OFFLOAD_TCP_LRO)
168 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
169 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
170 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
171 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
172 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
173 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
174 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
176 int is_bnxt_in_error(struct bnxt *bp)
178 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
180 if (bp->flags & BNXT_FLAG_FW_RESET)
186 /***********************/
189 * High level utility functions
192 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
194 if (!BNXT_CHIP_THOR(bp))
197 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
198 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
199 BNXT_RSS_ENTRIES_PER_CTX_THOR;
202 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
204 if (!BNXT_CHIP_THOR(bp))
205 return HW_HASH_INDEX_SIZE;
207 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
210 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
212 bnxt_free_filter_mem(bp);
213 bnxt_free_vnic_attributes(bp);
214 bnxt_free_vnic_mem(bp);
216 /* tx/rx rings are configured as part of *_queue_setup callbacks.
217 * If the number of rings change across fw update,
218 * we don't have much choice except to warn the user.
222 bnxt_free_tx_rings(bp);
223 bnxt_free_rx_rings(bp);
225 bnxt_free_async_cp_ring(bp);
228 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
232 rc = bnxt_alloc_ring_grps(bp);
236 rc = bnxt_alloc_async_ring_struct(bp);
240 rc = bnxt_alloc_vnic_mem(bp);
244 rc = bnxt_alloc_vnic_attributes(bp);
248 rc = bnxt_alloc_filter_mem(bp);
252 rc = bnxt_alloc_async_cp_ring(bp);
259 bnxt_free_mem(bp, reconfig);
263 static int bnxt_init_chip(struct bnxt *bp)
265 struct bnxt_rx_queue *rxq;
266 struct rte_eth_link new;
267 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
268 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
269 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
270 uint64_t rx_offloads = dev_conf->rxmode.offloads;
271 uint32_t intr_vector = 0;
272 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
273 uint32_t vec = BNXT_MISC_VEC_ID;
277 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
278 bp->eth_dev->data->dev_conf.rxmode.offloads |=
279 DEV_RX_OFFLOAD_JUMBO_FRAME;
280 bp->flags |= BNXT_FLAG_JUMBO;
282 bp->eth_dev->data->dev_conf.rxmode.offloads &=
283 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
284 bp->flags &= ~BNXT_FLAG_JUMBO;
287 /* THOR does not support ring groups.
288 * But we will use the array to save RSS context IDs.
290 if (BNXT_CHIP_THOR(bp))
291 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
293 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
295 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
299 rc = bnxt_alloc_hwrm_rings(bp);
301 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
305 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
307 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
311 rc = bnxt_mq_rx_configure(bp);
313 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
317 /* VNIC configuration */
318 for (i = 0; i < bp->nr_vnics; i++) {
319 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
320 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
322 rc = bnxt_vnic_grp_alloc(bp, vnic);
326 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
327 i, vnic, vnic->fw_grp_ids);
329 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
331 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
336 /* Alloc RSS context only if RSS mode is enabled */
337 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
338 int j, nr_ctxs = bnxt_rss_ctxts(bp);
341 for (j = 0; j < nr_ctxs; j++) {
342 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
348 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
352 vnic->num_lb_ctxts = nr_ctxs;
356 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
357 * setting is not available at this time, it will not be
358 * configured correctly in the CFA.
360 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
361 vnic->vlan_strip = true;
363 vnic->vlan_strip = false;
365 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
367 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
372 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
375 "HWRM vnic %d filter failure rc: %x\n",
380 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
381 rxq = bp->eth_dev->data->rx_queues[j];
384 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
385 j, rxq->vnic, rxq->vnic->fw_grp_ids);
387 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
388 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
391 rc = bnxt_vnic_rss_configure(bp, vnic);
394 "HWRM vnic set RSS failure rc: %x\n", rc);
398 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
400 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
401 DEV_RX_OFFLOAD_TCP_LRO)
402 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
404 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
406 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
409 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
413 /* check and configure queue intr-vector mapping */
414 if ((rte_intr_cap_multiple(intr_handle) ||
415 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
416 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
417 intr_vector = bp->eth_dev->data->nb_rx_queues;
418 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
419 if (intr_vector > bp->rx_cp_nr_rings) {
420 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
424 rc = rte_intr_efd_enable(intr_handle, intr_vector);
429 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
430 intr_handle->intr_vec =
431 rte_zmalloc("intr_vec",
432 bp->eth_dev->data->nb_rx_queues *
434 if (intr_handle->intr_vec == NULL) {
435 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
436 " intr_vec", bp->eth_dev->data->nb_rx_queues);
440 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
441 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
442 intr_handle->intr_vec, intr_handle->nb_efd,
443 intr_handle->max_intr);
444 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
446 intr_handle->intr_vec[queue_id] =
447 vec + BNXT_RX_VEC_START;
448 if (vec < base + intr_handle->nb_efd - 1)
453 /* enable uio/vfio intr/eventfd mapping */
454 rc = rte_intr_enable(intr_handle);
458 rc = bnxt_get_hwrm_link_config(bp, &new);
460 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
464 if (!bp->link_info.link_up) {
465 rc = bnxt_set_hwrm_link_config(bp, true);
468 "HWRM link config failure rc: %x\n", rc);
472 bnxt_print_link_info(bp->eth_dev);
477 rte_free(intr_handle->intr_vec);
479 rte_intr_efd_disable(intr_handle);
481 /* Some of the error status returned by FW may not be from errno.h */
488 static int bnxt_shutdown_nic(struct bnxt *bp)
490 bnxt_free_all_hwrm_resources(bp);
491 bnxt_free_all_filters(bp);
492 bnxt_free_all_vnics(bp);
496 static int bnxt_init_nic(struct bnxt *bp)
500 if (BNXT_HAS_RING_GRPS(bp)) {
501 rc = bnxt_init_ring_grps(bp);
507 bnxt_init_filters(bp);
513 * Device configuration and status function
516 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
517 struct rte_eth_dev_info *dev_info)
519 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
520 struct bnxt *bp = eth_dev->data->dev_private;
521 uint16_t max_vnics, i, j, vpool, vrxq;
522 unsigned int max_rx_rings;
525 rc = is_bnxt_in_error(bp);
530 dev_info->max_mac_addrs = bp->max_l2_ctx;
531 dev_info->max_hash_mac_addrs = 0;
533 /* PF/VF specifics */
535 dev_info->max_vfs = pdev->max_vfs;
537 max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
538 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
539 dev_info->max_rx_queues = max_rx_rings;
540 dev_info->max_tx_queues = max_rx_rings;
541 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
542 dev_info->hash_key_size = 40;
543 max_vnics = bp->max_vnics;
546 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
547 dev_info->max_mtu = BNXT_MAX_MTU;
549 /* Fast path specifics */
550 dev_info->min_rx_bufsize = 1;
551 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
553 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
554 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
555 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
556 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
557 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
560 dev_info->default_rxconf = (struct rte_eth_rxconf) {
566 .rx_free_thresh = 32,
567 /* If no descriptors available, pkts are dropped by default */
571 dev_info->default_txconf = (struct rte_eth_txconf) {
577 .tx_free_thresh = 32,
580 eth_dev->data->dev_conf.intr_conf.lsc = 1;
582 eth_dev->data->dev_conf.intr_conf.rxq = 1;
583 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
584 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
585 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
586 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
591 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
592 * need further investigation.
596 vpool = 64; /* ETH_64_POOLS */
597 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
598 for (i = 0; i < 4; vpool >>= 1, i++) {
599 if (max_vnics > vpool) {
600 for (j = 0; j < 5; vrxq >>= 1, j++) {
601 if (dev_info->max_rx_queues > vrxq) {
607 /* Not enough resources to support VMDq */
611 /* Not enough resources to support VMDq */
615 dev_info->max_vmdq_pools = vpool;
616 dev_info->vmdq_queue_num = vrxq;
618 dev_info->vmdq_pool_base = 0;
619 dev_info->vmdq_queue_base = 0;
624 /* Configure the device based on the configuration provided */
625 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
627 struct bnxt *bp = eth_dev->data->dev_private;
628 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
631 bp->rx_queues = (void *)eth_dev->data->rx_queues;
632 bp->tx_queues = (void *)eth_dev->data->tx_queues;
633 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
634 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
636 rc = is_bnxt_in_error(bp);
640 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
641 rc = bnxt_hwrm_check_vf_rings(bp);
643 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
647 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
649 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
653 /* legacy driver needs to get updated values */
654 rc = bnxt_hwrm_func_qcaps(bp);
656 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
661 /* Inherit new configurations */
662 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
663 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
664 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
665 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
666 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
670 if (BNXT_HAS_RING_GRPS(bp) &&
671 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
674 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
675 bp->max_vnics < eth_dev->data->nb_rx_queues)
678 bp->rx_cp_nr_rings = bp->rx_nr_rings;
679 bp->tx_cp_nr_rings = bp->tx_nr_rings;
681 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
683 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
684 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
686 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
692 "Insufficient resources to support requested config\n");
694 "Num Queues Requested: Tx %d, Rx %d\n",
695 eth_dev->data->nb_tx_queues,
696 eth_dev->data->nb_rx_queues);
698 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
699 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
700 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
704 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
706 struct rte_eth_link *link = ð_dev->data->dev_link;
708 if (link->link_status)
709 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
710 eth_dev->data->port_id,
711 (uint32_t)link->link_speed,
712 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
713 ("full-duplex") : ("half-duplex\n"));
715 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
716 eth_dev->data->port_id);
720 * Determine whether the current configuration requires support for scattered
721 * receive; return 1 if scattered receive is required and 0 if not.
723 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
728 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
729 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
731 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
732 RTE_PKTMBUF_HEADROOM);
733 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
739 static eth_rx_burst_t
740 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
743 #ifndef RTE_LIBRTE_IEEE1588
745 * Vector mode receive can be enabled only if scatter rx is not
746 * in use and rx offloads are limited to VLAN stripping and
749 if (!eth_dev->data->scattered_rx &&
750 !(eth_dev->data->dev_conf.rxmode.offloads &
751 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
752 DEV_RX_OFFLOAD_KEEP_CRC |
753 DEV_RX_OFFLOAD_JUMBO_FRAME |
754 DEV_RX_OFFLOAD_IPV4_CKSUM |
755 DEV_RX_OFFLOAD_UDP_CKSUM |
756 DEV_RX_OFFLOAD_TCP_CKSUM |
757 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
758 DEV_RX_OFFLOAD_VLAN_FILTER))) {
759 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
760 eth_dev->data->port_id);
761 return bnxt_recv_pkts_vec;
763 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
764 eth_dev->data->port_id);
766 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
767 eth_dev->data->port_id,
768 eth_dev->data->scattered_rx,
769 eth_dev->data->dev_conf.rxmode.offloads);
772 return bnxt_recv_pkts;
775 static eth_tx_burst_t
776 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
779 #ifndef RTE_LIBRTE_IEEE1588
781 * Vector mode transmit can be enabled only if not using scatter rx
784 if (!eth_dev->data->scattered_rx &&
785 !eth_dev->data->dev_conf.txmode.offloads) {
786 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
787 eth_dev->data->port_id);
788 return bnxt_xmit_pkts_vec;
790 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
791 eth_dev->data->port_id);
793 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
794 eth_dev->data->port_id,
795 eth_dev->data->scattered_rx,
796 eth_dev->data->dev_conf.txmode.offloads);
799 return bnxt_xmit_pkts;
802 static int bnxt_handle_if_change_status(struct bnxt *bp)
806 /* Since fw has undergone a reset and lost all contexts,
807 * set fatal flag to not issue hwrm during cleanup
809 bp->flags |= BNXT_FLAG_FATAL_ERROR;
810 bnxt_uninit_resources(bp, true);
812 /* clear fatal flag so that re-init happens */
813 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
814 rc = bnxt_init_resources(bp, true);
816 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
821 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
823 struct bnxt *bp = eth_dev->data->dev_private;
824 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
828 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
830 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
831 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
835 rc = bnxt_hwrm_if_change(bp, 1);
837 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
838 rc = bnxt_handle_if_change_status(bp);
844 rc = bnxt_init_chip(bp);
848 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
850 bnxt_link_update_op(eth_dev, 1);
852 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
853 vlan_mask |= ETH_VLAN_FILTER_MASK;
854 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
855 vlan_mask |= ETH_VLAN_STRIP_MASK;
856 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
860 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
861 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
863 bp->flags |= BNXT_FLAG_INIT_DONE;
864 eth_dev->data->dev_started = 1;
866 bnxt_schedule_fw_health_check(bp);
870 bnxt_hwrm_if_change(bp, 0);
871 bnxt_shutdown_nic(bp);
872 bnxt_free_tx_mbufs(bp);
873 bnxt_free_rx_mbufs(bp);
877 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
879 struct bnxt *bp = eth_dev->data->dev_private;
882 if (!bp->link_info.link_up)
883 rc = bnxt_set_hwrm_link_config(bp, true);
885 eth_dev->data->dev_link.link_status = 1;
887 bnxt_print_link_info(eth_dev);
891 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
893 struct bnxt *bp = eth_dev->data->dev_private;
895 eth_dev->data->dev_link.link_status = 0;
896 bnxt_set_hwrm_link_config(bp, false);
897 bp->link_info.link_up = 0;
902 /* Unload the driver, release resources */
903 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
905 struct bnxt *bp = eth_dev->data->dev_private;
906 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
907 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
909 eth_dev->data->dev_started = 0;
910 /* Prevent crashes when queues are still in use */
911 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
912 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
914 bnxt_disable_int(bp);
916 /* disable uio/vfio intr/eventfd mapping */
917 rte_intr_disable(intr_handle);
919 bnxt_cancel_fw_health_check(bp);
921 bp->flags &= ~BNXT_FLAG_INIT_DONE;
922 if (bp->eth_dev->data->dev_started) {
923 /* TBD: STOP HW queues DMA */
924 eth_dev->data->dev_link.link_status = 0;
926 bnxt_dev_set_link_down_op(eth_dev);
927 /* Wait for link to be reset and the async notification to process. */
928 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
930 /* Clean queue intr-vector mapping */
931 rte_intr_efd_disable(intr_handle);
932 if (intr_handle->intr_vec != NULL) {
933 rte_free(intr_handle->intr_vec);
934 intr_handle->intr_vec = NULL;
937 bnxt_hwrm_port_clr_stats(bp);
938 bnxt_free_tx_mbufs(bp);
939 bnxt_free_rx_mbufs(bp);
940 /* Process any remaining notifications in default completion queue */
941 bnxt_int_handler(eth_dev);
942 bnxt_shutdown_nic(bp);
943 bnxt_hwrm_if_change(bp, 0);
947 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
949 struct bnxt *bp = eth_dev->data->dev_private;
951 if (bp->dev_stopped == 0)
952 bnxt_dev_stop_op(eth_dev);
954 if (eth_dev->data->mac_addrs != NULL) {
955 rte_free(eth_dev->data->mac_addrs);
956 eth_dev->data->mac_addrs = NULL;
958 if (bp->grp_info != NULL) {
959 rte_free(bp->grp_info);
963 bnxt_dev_uninit(eth_dev);
966 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
969 struct bnxt *bp = eth_dev->data->dev_private;
970 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
971 struct bnxt_vnic_info *vnic;
972 struct bnxt_filter_info *filter, *temp_filter;
975 if (is_bnxt_in_error(bp))
979 * Loop through all VNICs from the specified filter flow pools to
980 * remove the corresponding MAC addr filter
982 for (i = 0; i < bp->nr_vnics; i++) {
983 if (!(pool_mask & (1ULL << i)))
986 vnic = &bp->vnic_info[i];
987 filter = STAILQ_FIRST(&vnic->filter);
989 temp_filter = STAILQ_NEXT(filter, next);
990 if (filter->mac_index == index) {
991 STAILQ_REMOVE(&vnic->filter, filter,
992 bnxt_filter_info, next);
993 bnxt_hwrm_clear_l2_filter(bp, filter);
994 filter->mac_index = INVALID_MAC_INDEX;
995 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
996 STAILQ_INSERT_TAIL(&bp->free_filter_list,
999 filter = temp_filter;
1004 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1005 struct rte_ether_addr *mac_addr, uint32_t index)
1007 struct bnxt_filter_info *filter;
1010 filter = STAILQ_FIRST(&vnic->filter);
1011 /* During bnxt_mac_addr_add_op, default MAC is
1012 * already programmed, so skip it. But, when
1013 * hw-vlan-filter is turned OFF from ON, default
1014 * MAC filter should be restored
1019 filter = bnxt_alloc_filter(bp);
1021 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1025 filter->mac_index = index;
1026 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1027 * if the MAC that's been programmed now is a different one, then,
1028 * copy that addr to filter->l2_addr
1031 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1032 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1034 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1036 if (filter->mac_index == 0) {
1037 filter->dflt = true;
1038 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1040 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1043 filter->mac_index = INVALID_MAC_INDEX;
1044 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1045 bnxt_free_filter(bp, filter);
1051 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1052 struct rte_ether_addr *mac_addr,
1053 uint32_t index, uint32_t pool)
1055 struct bnxt *bp = eth_dev->data->dev_private;
1056 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1057 struct bnxt_filter_info *filter;
1060 rc = is_bnxt_in_error(bp);
1064 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1065 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1070 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1073 /* Attach requested MAC address to the new l2_filter */
1074 STAILQ_FOREACH(filter, &vnic->filter, next) {
1075 if (filter->mac_index == index) {
1077 "MAC addr already existed for pool %d\n", pool);
1082 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index);
1087 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1090 struct bnxt *bp = eth_dev->data->dev_private;
1091 struct rte_eth_link new;
1092 unsigned int cnt = BNXT_LINK_WAIT_CNT;
1094 rc = is_bnxt_in_error(bp);
1098 memset(&new, 0, sizeof(new));
1100 /* Retrieve link info from hardware */
1101 rc = bnxt_get_hwrm_link_config(bp, &new);
1103 new.link_speed = ETH_LINK_SPEED_100M;
1104 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1106 "Failed to retrieve link rc = 0x%x!\n", rc);
1110 if (!wait_to_complete || new.link_status)
1113 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1117 /* Timed out or success */
1118 if (new.link_status != eth_dev->data->dev_link.link_status ||
1119 new.link_speed != eth_dev->data->dev_link.link_speed) {
1120 rte_eth_linkstatus_set(eth_dev, &new);
1122 _rte_eth_dev_callback_process(eth_dev,
1123 RTE_ETH_EVENT_INTR_LSC,
1126 bnxt_print_link_info(eth_dev);
1132 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1134 struct bnxt *bp = eth_dev->data->dev_private;
1135 struct bnxt_vnic_info *vnic;
1139 rc = is_bnxt_in_error(bp);
1143 if (bp->vnic_info == NULL)
1146 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1148 old_flags = vnic->flags;
1149 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1150 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1152 vnic->flags = old_flags;
1157 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1159 struct bnxt *bp = eth_dev->data->dev_private;
1160 struct bnxt_vnic_info *vnic;
1164 rc = is_bnxt_in_error(bp);
1168 if (bp->vnic_info == NULL)
1171 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1173 old_flags = vnic->flags;
1174 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1175 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1177 vnic->flags = old_flags;
1182 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1184 struct bnxt *bp = eth_dev->data->dev_private;
1185 struct bnxt_vnic_info *vnic;
1189 rc = is_bnxt_in_error(bp);
1193 if (bp->vnic_info == NULL)
1196 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1198 old_flags = vnic->flags;
1199 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1200 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1202 vnic->flags = old_flags;
1207 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1209 struct bnxt *bp = eth_dev->data->dev_private;
1210 struct bnxt_vnic_info *vnic;
1214 rc = is_bnxt_in_error(bp);
1218 if (bp->vnic_info == NULL)
1221 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1223 old_flags = vnic->flags;
1224 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1225 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1227 vnic->flags = old_flags;
1232 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1233 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1235 if (qid >= bp->rx_nr_rings)
1238 return bp->eth_dev->data->rx_queues[qid];
1241 /* Return rxq corresponding to a given rss table ring/group ID. */
1242 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1244 struct bnxt_rx_queue *rxq;
1247 if (!BNXT_HAS_RING_GRPS(bp)) {
1248 for (i = 0; i < bp->rx_nr_rings; i++) {
1249 rxq = bp->eth_dev->data->rx_queues[i];
1250 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1254 for (i = 0; i < bp->rx_nr_rings; i++) {
1255 if (bp->grp_info[i].fw_grp_id == fwr)
1260 return INVALID_HW_RING_ID;
1263 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1264 struct rte_eth_rss_reta_entry64 *reta_conf,
1267 struct bnxt *bp = eth_dev->data->dev_private;
1268 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1269 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1270 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1274 rc = is_bnxt_in_error(bp);
1278 if (!vnic->rss_table)
1281 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1284 if (reta_size != tbl_size) {
1285 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1286 "(%d) must equal the size supported by the hardware "
1287 "(%d)\n", reta_size, tbl_size);
1291 for (i = 0; i < reta_size; i++) {
1292 struct bnxt_rx_queue *rxq;
1294 idx = i / RTE_RETA_GROUP_SIZE;
1295 sft = i % RTE_RETA_GROUP_SIZE;
1297 if (!(reta_conf[idx].mask & (1ULL << sft)))
1300 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1302 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1306 if (BNXT_CHIP_THOR(bp)) {
1307 vnic->rss_table[i * 2] =
1308 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1309 vnic->rss_table[i * 2 + 1] =
1310 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1312 vnic->rss_table[i] =
1313 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1316 vnic->rss_table[i] =
1317 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1320 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1324 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1325 struct rte_eth_rss_reta_entry64 *reta_conf,
1328 struct bnxt *bp = eth_dev->data->dev_private;
1329 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1330 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1331 uint16_t idx, sft, i;
1334 rc = is_bnxt_in_error(bp);
1338 /* Retrieve from the default VNIC */
1341 if (!vnic->rss_table)
1344 if (reta_size != tbl_size) {
1345 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1346 "(%d) must equal the size supported by the hardware "
1347 "(%d)\n", reta_size, tbl_size);
1351 for (idx = 0, i = 0; i < reta_size; i++) {
1352 idx = i / RTE_RETA_GROUP_SIZE;
1353 sft = i % RTE_RETA_GROUP_SIZE;
1355 if (reta_conf[idx].mask & (1ULL << sft)) {
1358 if (BNXT_CHIP_THOR(bp))
1359 qid = bnxt_rss_to_qid(bp,
1360 vnic->rss_table[i * 2]);
1362 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1364 if (qid == INVALID_HW_RING_ID) {
1365 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1368 reta_conf[idx].reta[sft] = qid;
1375 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1376 struct rte_eth_rss_conf *rss_conf)
1378 struct bnxt *bp = eth_dev->data->dev_private;
1379 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1380 struct bnxt_vnic_info *vnic;
1383 rc = is_bnxt_in_error(bp);
1388 * If RSS enablement were different than dev_configure,
1389 * then return -EINVAL
1391 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1392 if (!rss_conf->rss_hf)
1393 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1395 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1399 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1400 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1402 /* Update the default RSS VNIC(s) */
1403 vnic = &bp->vnic_info[0];
1404 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1407 * If hashkey is not specified, use the previously configured
1410 if (!rss_conf->rss_key)
1413 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1415 "Invalid hashkey length, should be 16 bytes\n");
1418 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1421 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1425 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1426 struct rte_eth_rss_conf *rss_conf)
1428 struct bnxt *bp = eth_dev->data->dev_private;
1429 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1431 uint32_t hash_types;
1433 rc = is_bnxt_in_error(bp);
1437 /* RSS configuration is the same for all VNICs */
1438 if (vnic && vnic->rss_hash_key) {
1439 if (rss_conf->rss_key) {
1440 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1441 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1442 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1445 hash_types = vnic->hash_type;
1446 rss_conf->rss_hf = 0;
1447 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1448 rss_conf->rss_hf |= ETH_RSS_IPV4;
1449 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1451 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1452 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1454 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1456 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1457 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1459 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1461 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1462 rss_conf->rss_hf |= ETH_RSS_IPV6;
1463 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1465 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1466 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1468 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1470 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1471 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1473 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1477 "Unknwon RSS config from firmware (%08x), RSS disabled",
1482 rss_conf->rss_hf = 0;
1487 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1488 struct rte_eth_fc_conf *fc_conf)
1490 struct bnxt *bp = dev->data->dev_private;
1491 struct rte_eth_link link_info;
1494 rc = is_bnxt_in_error(bp);
1498 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1502 memset(fc_conf, 0, sizeof(*fc_conf));
1503 if (bp->link_info.auto_pause)
1504 fc_conf->autoneg = 1;
1505 switch (bp->link_info.pause) {
1507 fc_conf->mode = RTE_FC_NONE;
1509 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1510 fc_conf->mode = RTE_FC_TX_PAUSE;
1512 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1513 fc_conf->mode = RTE_FC_RX_PAUSE;
1515 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1516 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1517 fc_conf->mode = RTE_FC_FULL;
1523 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1524 struct rte_eth_fc_conf *fc_conf)
1526 struct bnxt *bp = dev->data->dev_private;
1529 rc = is_bnxt_in_error(bp);
1533 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1534 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1538 switch (fc_conf->mode) {
1540 bp->link_info.auto_pause = 0;
1541 bp->link_info.force_pause = 0;
1543 case RTE_FC_RX_PAUSE:
1544 if (fc_conf->autoneg) {
1545 bp->link_info.auto_pause =
1546 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1547 bp->link_info.force_pause = 0;
1549 bp->link_info.auto_pause = 0;
1550 bp->link_info.force_pause =
1551 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1554 case RTE_FC_TX_PAUSE:
1555 if (fc_conf->autoneg) {
1556 bp->link_info.auto_pause =
1557 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1558 bp->link_info.force_pause = 0;
1560 bp->link_info.auto_pause = 0;
1561 bp->link_info.force_pause =
1562 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1566 if (fc_conf->autoneg) {
1567 bp->link_info.auto_pause =
1568 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1569 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1570 bp->link_info.force_pause = 0;
1572 bp->link_info.auto_pause = 0;
1573 bp->link_info.force_pause =
1574 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1575 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1579 return bnxt_set_hwrm_link_config(bp, true);
1582 /* Add UDP tunneling port */
1584 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1585 struct rte_eth_udp_tunnel *udp_tunnel)
1587 struct bnxt *bp = eth_dev->data->dev_private;
1588 uint16_t tunnel_type = 0;
1591 rc = is_bnxt_in_error(bp);
1595 switch (udp_tunnel->prot_type) {
1596 case RTE_TUNNEL_TYPE_VXLAN:
1597 if (bp->vxlan_port_cnt) {
1598 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1599 udp_tunnel->udp_port);
1600 if (bp->vxlan_port != udp_tunnel->udp_port) {
1601 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1604 bp->vxlan_port_cnt++;
1608 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1609 bp->vxlan_port_cnt++;
1611 case RTE_TUNNEL_TYPE_GENEVE:
1612 if (bp->geneve_port_cnt) {
1613 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1614 udp_tunnel->udp_port);
1615 if (bp->geneve_port != udp_tunnel->udp_port) {
1616 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1619 bp->geneve_port_cnt++;
1623 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1624 bp->geneve_port_cnt++;
1627 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1630 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1636 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1637 struct rte_eth_udp_tunnel *udp_tunnel)
1639 struct bnxt *bp = eth_dev->data->dev_private;
1640 uint16_t tunnel_type = 0;
1644 rc = is_bnxt_in_error(bp);
1648 switch (udp_tunnel->prot_type) {
1649 case RTE_TUNNEL_TYPE_VXLAN:
1650 if (!bp->vxlan_port_cnt) {
1651 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1654 if (bp->vxlan_port != udp_tunnel->udp_port) {
1655 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1656 udp_tunnel->udp_port, bp->vxlan_port);
1659 if (--bp->vxlan_port_cnt)
1663 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1664 port = bp->vxlan_fw_dst_port_id;
1666 case RTE_TUNNEL_TYPE_GENEVE:
1667 if (!bp->geneve_port_cnt) {
1668 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1671 if (bp->geneve_port != udp_tunnel->udp_port) {
1672 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1673 udp_tunnel->udp_port, bp->geneve_port);
1676 if (--bp->geneve_port_cnt)
1680 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1681 port = bp->geneve_fw_dst_port_id;
1684 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1688 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1691 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1694 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1695 bp->geneve_port = 0;
1700 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1702 struct bnxt_filter_info *filter;
1703 struct bnxt_vnic_info *vnic;
1705 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1707 /* if VLAN exists && VLAN matches vlan_id
1708 * remove the MAC+VLAN filter
1709 * add a new MAC only filter
1711 * VLAN filter doesn't exist, just skip and continue
1713 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1714 filter = STAILQ_FIRST(&vnic->filter);
1716 /* Search for this matching MAC+VLAN filter */
1717 if ((filter->enables & chk) &&
1718 (filter->l2_ivlan == vlan_id &&
1719 filter->l2_ivlan_mask != 0) &&
1720 !memcmp(filter->l2_addr, bp->mac_addr,
1721 RTE_ETHER_ADDR_LEN)) {
1722 /* Delete the filter */
1723 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1726 STAILQ_REMOVE(&vnic->filter, filter,
1727 bnxt_filter_info, next);
1728 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1731 "Del Vlan filter for %d\n",
1735 filter = STAILQ_NEXT(filter, next);
1740 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1742 struct bnxt_filter_info *filter;
1743 struct bnxt_vnic_info *vnic;
1745 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1746 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1747 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1749 /* Implementation notes on the use of VNIC in this command:
1751 * By default, these filters belong to default vnic for the function.
1752 * Once these filters are set up, only destination VNIC can be modified.
1753 * If the destination VNIC is not specified in this command,
1754 * then the HWRM shall only create an l2 context id.
1757 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1758 filter = STAILQ_FIRST(&vnic->filter);
1759 /* Check if the VLAN has already been added */
1761 if ((filter->enables & chk) &&
1762 (filter->l2_ivlan == vlan_id &&
1763 filter->l2_ivlan_mask == 0x0FFF) &&
1764 !memcmp(filter->l2_addr, bp->mac_addr,
1765 RTE_ETHER_ADDR_LEN))
1768 filter = STAILQ_NEXT(filter, next);
1771 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1772 * command to create MAC+VLAN filter with the right flags, enables set.
1774 filter = bnxt_alloc_filter(bp);
1777 "MAC/VLAN filter alloc failed\n");
1780 /* MAC + VLAN ID filter */
1781 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1782 * untagged packets are received
1784 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1785 * packets and only the programmed vlan's packets are received
1787 filter->l2_ivlan = vlan_id;
1788 filter->l2_ivlan_mask = 0x0FFF;
1789 filter->enables |= en;
1790 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1792 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1794 /* Free the newly allocated filter as we were
1795 * not able to create the filter in hardware.
1797 filter->fw_l2_filter_id = UINT64_MAX;
1798 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1801 /* Add this new filter to the list */
1803 filter->dflt = true;
1804 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1806 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1811 "Added Vlan filter for %d\n", vlan_id);
1815 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1816 uint16_t vlan_id, int on)
1818 struct bnxt *bp = eth_dev->data->dev_private;
1821 rc = is_bnxt_in_error(bp);
1825 /* These operations apply to ALL existing MAC/VLAN filters */
1827 return bnxt_add_vlan_filter(bp, vlan_id);
1829 return bnxt_del_vlan_filter(bp, vlan_id);
1832 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1833 struct bnxt_vnic_info *vnic)
1835 struct bnxt_filter_info *filter;
1838 filter = STAILQ_FIRST(&vnic->filter);
1841 !memcmp(filter->l2_addr, bp->mac_addr,
1842 RTE_ETHER_ADDR_LEN)) {
1843 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1846 filter->dflt = false;
1847 STAILQ_REMOVE(&vnic->filter, filter,
1848 bnxt_filter_info, next);
1849 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1851 filter->fw_l2_filter_id = -1;
1854 filter = STAILQ_NEXT(filter, next);
1860 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1862 struct bnxt *bp = dev->data->dev_private;
1863 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1864 struct bnxt_vnic_info *vnic;
1868 rc = is_bnxt_in_error(bp);
1872 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1873 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1874 /* Remove any VLAN filters programmed */
1875 for (i = 0; i < 4095; i++)
1876 bnxt_del_vlan_filter(bp, i);
1878 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0);
1882 /* Default filter will allow packets that match the
1883 * dest mac. So, it has to be deleted, otherwise, we
1884 * will endup receiving vlan packets for which the
1885 * filter is not programmed, when hw-vlan-filter
1886 * configuration is ON
1888 bnxt_del_dflt_mac_filter(bp, vnic);
1889 /* This filter will allow only untagged packets */
1890 bnxt_add_vlan_filter(bp, 0);
1892 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1893 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1895 if (mask & ETH_VLAN_STRIP_MASK) {
1896 /* Enable or disable VLAN stripping */
1897 for (i = 0; i < bp->nr_vnics; i++) {
1898 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1899 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1900 vnic->vlan_strip = true;
1902 vnic->vlan_strip = false;
1903 bnxt_hwrm_vnic_cfg(bp, vnic);
1905 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1906 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1909 if (mask & ETH_VLAN_EXTEND_MASK) {
1910 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1911 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1913 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1920 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1923 struct bnxt *bp = dev->data->dev_private;
1924 int qinq = dev->data->dev_conf.rxmode.offloads &
1925 DEV_RX_OFFLOAD_VLAN_EXTEND;
1927 if (vlan_type != ETH_VLAN_TYPE_INNER &&
1928 vlan_type != ETH_VLAN_TYPE_OUTER) {
1930 "Unsupported vlan type.");
1935 "QinQ not enabled. Needs to be ON as we can "
1936 "accelerate only outer vlan\n");
1940 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1942 case RTE_ETHER_TYPE_QINQ:
1944 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1946 case RTE_ETHER_TYPE_VLAN:
1948 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1952 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1956 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
1960 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
1963 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
1966 bp->outer_tpid_bd |= tpid;
1967 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
1968 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
1970 "Can accelerate only outer vlan in QinQ\n");
1978 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1979 struct rte_ether_addr *addr)
1981 struct bnxt *bp = dev->data->dev_private;
1982 /* Default Filter is tied to VNIC 0 */
1983 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1984 struct bnxt_filter_info *filter;
1987 rc = is_bnxt_in_error(bp);
1991 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1994 if (rte_is_zero_ether_addr(addr))
1997 STAILQ_FOREACH(filter, &vnic->filter, next) {
1998 /* Default Filter is at Index 0 */
1999 if (filter->mac_index != 0)
2002 memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN);
2003 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
2004 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX |
2005 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2007 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
2008 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
2010 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2012 memcpy(filter->l2_addr, bp->mac_addr,
2013 RTE_ETHER_ADDR_LEN);
2017 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2018 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2026 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2027 struct rte_ether_addr *mc_addr_set,
2028 uint32_t nb_mc_addr)
2030 struct bnxt *bp = eth_dev->data->dev_private;
2031 char *mc_addr_list = (char *)mc_addr_set;
2032 struct bnxt_vnic_info *vnic;
2033 uint32_t off = 0, i = 0;
2036 rc = is_bnxt_in_error(bp);
2040 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2042 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2043 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2047 /* TODO Check for Duplicate mcast addresses */
2048 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2049 for (i = 0; i < nb_mc_addr; i++) {
2050 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2051 RTE_ETHER_ADDR_LEN);
2052 off += RTE_ETHER_ADDR_LEN;
2055 vnic->mc_addr_cnt = i;
2056 if (vnic->mc_addr_cnt)
2057 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2059 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2062 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2066 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2068 struct bnxt *bp = dev->data->dev_private;
2069 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2070 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2071 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2074 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2075 fw_major, fw_minor, fw_updt);
2077 ret += 1; /* add the size of '\0' */
2078 if (fw_size < (uint32_t)ret)
2085 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2086 struct rte_eth_rxq_info *qinfo)
2088 struct bnxt_rx_queue *rxq;
2090 rxq = dev->data->rx_queues[queue_id];
2092 qinfo->mp = rxq->mb_pool;
2093 qinfo->scattered_rx = dev->data->scattered_rx;
2094 qinfo->nb_desc = rxq->nb_rx_desc;
2096 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2097 qinfo->conf.rx_drop_en = 0;
2098 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2102 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2103 struct rte_eth_txq_info *qinfo)
2105 struct bnxt_tx_queue *txq;
2107 txq = dev->data->tx_queues[queue_id];
2109 qinfo->nb_desc = txq->nb_tx_desc;
2111 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2112 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2113 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2115 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2116 qinfo->conf.tx_rs_thresh = 0;
2117 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2120 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2122 struct bnxt *bp = eth_dev->data->dev_private;
2123 uint32_t new_pkt_size;
2127 rc = is_bnxt_in_error(bp);
2131 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2132 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2136 * If vector-mode tx/rx is active, disallow any MTU change that would
2137 * require scattered receive support.
2139 if (eth_dev->data->dev_started &&
2140 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2141 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2143 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2145 "MTU change would require scattered rx support. ");
2146 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2151 if (new_mtu > RTE_ETHER_MTU) {
2152 bp->flags |= BNXT_FLAG_JUMBO;
2153 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2154 DEV_RX_OFFLOAD_JUMBO_FRAME;
2156 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2157 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2158 bp->flags &= ~BNXT_FLAG_JUMBO;
2161 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2163 for (i = 0; i < bp->nr_vnics; i++) {
2164 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2167 vnic->mru = new_mtu + RTE_ETHER_HDR_LEN +
2168 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
2169 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2173 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2174 size -= RTE_PKTMBUF_HEADROOM;
2176 if (size < new_mtu) {
2177 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2183 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2189 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2191 struct bnxt *bp = dev->data->dev_private;
2192 uint16_t vlan = bp->vlan;
2195 rc = is_bnxt_in_error(bp);
2199 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2201 "PVID cannot be modified for this function\n");
2204 bp->vlan = on ? pvid : 0;
2206 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2213 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2215 struct bnxt *bp = dev->data->dev_private;
2218 rc = is_bnxt_in_error(bp);
2222 return bnxt_hwrm_port_led_cfg(bp, true);
2226 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2228 struct bnxt *bp = dev->data->dev_private;
2231 rc = is_bnxt_in_error(bp);
2235 return bnxt_hwrm_port_led_cfg(bp, false);
2239 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2241 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2242 uint32_t desc = 0, raw_cons = 0, cons;
2243 struct bnxt_cp_ring_info *cpr;
2244 struct bnxt_rx_queue *rxq;
2245 struct rx_pkt_cmpl *rxcmp;
2248 rc = is_bnxt_in_error(bp);
2252 rxq = dev->data->rx_queues[rx_queue_id];
2254 raw_cons = cpr->cp_raw_cons;
2257 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2258 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2259 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2261 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2273 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2275 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2276 struct bnxt_rx_ring_info *rxr;
2277 struct bnxt_cp_ring_info *cpr;
2278 struct bnxt_sw_rx_bd *rx_buf;
2279 struct rx_pkt_cmpl *rxcmp;
2280 uint32_t cons, cp_cons;
2286 rc = is_bnxt_in_error(rxq->bp);
2293 if (offset >= rxq->nb_rx_desc)
2296 cons = RING_CMP(cpr->cp_ring_struct, offset);
2297 cp_cons = cpr->cp_raw_cons;
2298 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2300 if (cons > cp_cons) {
2301 if (CMPL_VALID(rxcmp, cpr->valid))
2302 return RTE_ETH_RX_DESC_DONE;
2304 if (CMPL_VALID(rxcmp, !cpr->valid))
2305 return RTE_ETH_RX_DESC_DONE;
2307 rx_buf = &rxr->rx_buf_ring[cons];
2308 if (rx_buf->mbuf == NULL)
2309 return RTE_ETH_RX_DESC_UNAVAIL;
2312 return RTE_ETH_RX_DESC_AVAIL;
2316 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2318 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2319 struct bnxt_tx_ring_info *txr;
2320 struct bnxt_cp_ring_info *cpr;
2321 struct bnxt_sw_tx_bd *tx_buf;
2322 struct tx_pkt_cmpl *txcmp;
2323 uint32_t cons, cp_cons;
2329 rc = is_bnxt_in_error(txq->bp);
2336 if (offset >= txq->nb_tx_desc)
2339 cons = RING_CMP(cpr->cp_ring_struct, offset);
2340 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2341 cp_cons = cpr->cp_raw_cons;
2343 if (cons > cp_cons) {
2344 if (CMPL_VALID(txcmp, cpr->valid))
2345 return RTE_ETH_TX_DESC_UNAVAIL;
2347 if (CMPL_VALID(txcmp, !cpr->valid))
2348 return RTE_ETH_TX_DESC_UNAVAIL;
2350 tx_buf = &txr->tx_buf_ring[cons];
2351 if (tx_buf->mbuf == NULL)
2352 return RTE_ETH_TX_DESC_DONE;
2354 return RTE_ETH_TX_DESC_FULL;
2357 static struct bnxt_filter_info *
2358 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2359 struct rte_eth_ethertype_filter *efilter,
2360 struct bnxt_vnic_info *vnic0,
2361 struct bnxt_vnic_info *vnic,
2364 struct bnxt_filter_info *mfilter = NULL;
2368 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2369 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2370 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2371 " ethertype filter.", efilter->ether_type);
2375 if (efilter->queue >= bp->rx_nr_rings) {
2376 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2381 vnic0 = &bp->vnic_info[0];
2382 vnic = &bp->vnic_info[efilter->queue];
2384 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2389 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2390 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2391 if ((!memcmp(efilter->mac_addr.addr_bytes,
2392 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2394 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2395 mfilter->ethertype == efilter->ether_type)) {
2401 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2402 if ((!memcmp(efilter->mac_addr.addr_bytes,
2403 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2404 mfilter->ethertype == efilter->ether_type &&
2406 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2420 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2421 enum rte_filter_op filter_op,
2424 struct bnxt *bp = dev->data->dev_private;
2425 struct rte_eth_ethertype_filter *efilter =
2426 (struct rte_eth_ethertype_filter *)arg;
2427 struct bnxt_filter_info *bfilter, *filter1;
2428 struct bnxt_vnic_info *vnic, *vnic0;
2431 if (filter_op == RTE_ETH_FILTER_NOP)
2435 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2440 vnic0 = &bp->vnic_info[0];
2441 vnic = &bp->vnic_info[efilter->queue];
2443 switch (filter_op) {
2444 case RTE_ETH_FILTER_ADD:
2445 bnxt_match_and_validate_ether_filter(bp, efilter,
2450 bfilter = bnxt_get_unused_filter(bp);
2451 if (bfilter == NULL) {
2453 "Not enough resources for a new filter.\n");
2456 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2457 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2458 RTE_ETHER_ADDR_LEN);
2459 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2460 RTE_ETHER_ADDR_LEN);
2461 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2462 bfilter->ethertype = efilter->ether_type;
2463 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2465 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2466 if (filter1 == NULL) {
2471 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2472 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2474 bfilter->dst_id = vnic->fw_vnic_id;
2476 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2478 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2481 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2484 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2486 case RTE_ETH_FILTER_DELETE:
2487 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2489 if (ret == -EEXIST) {
2490 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2492 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2494 bnxt_free_filter(bp, filter1);
2495 } else if (ret == 0) {
2496 PMD_DRV_LOG(ERR, "No matching filter found\n");
2500 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2506 bnxt_free_filter(bp, bfilter);
2512 parse_ntuple_filter(struct bnxt *bp,
2513 struct rte_eth_ntuple_filter *nfilter,
2514 struct bnxt_filter_info *bfilter)
2518 if (nfilter->queue >= bp->rx_nr_rings) {
2519 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2523 switch (nfilter->dst_port_mask) {
2525 bfilter->dst_port_mask = -1;
2526 bfilter->dst_port = nfilter->dst_port;
2527 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2528 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2531 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2535 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2536 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2538 switch (nfilter->proto_mask) {
2540 if (nfilter->proto == 17) /* IPPROTO_UDP */
2541 bfilter->ip_protocol = 17;
2542 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2543 bfilter->ip_protocol = 6;
2546 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2549 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2553 switch (nfilter->dst_ip_mask) {
2555 bfilter->dst_ipaddr_mask[0] = -1;
2556 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2557 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2558 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2561 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2565 switch (nfilter->src_ip_mask) {
2567 bfilter->src_ipaddr_mask[0] = -1;
2568 bfilter->src_ipaddr[0] = nfilter->src_ip;
2569 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2570 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2573 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2577 switch (nfilter->src_port_mask) {
2579 bfilter->src_port_mask = -1;
2580 bfilter->src_port = nfilter->src_port;
2581 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2582 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2585 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2590 //nfilter->priority = (uint8_t)filter->priority;
2592 bfilter->enables = en;
2596 static struct bnxt_filter_info*
2597 bnxt_match_ntuple_filter(struct bnxt *bp,
2598 struct bnxt_filter_info *bfilter,
2599 struct bnxt_vnic_info **mvnic)
2601 struct bnxt_filter_info *mfilter = NULL;
2604 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2605 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2606 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2607 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2608 bfilter->src_ipaddr_mask[0] ==
2609 mfilter->src_ipaddr_mask[0] &&
2610 bfilter->src_port == mfilter->src_port &&
2611 bfilter->src_port_mask == mfilter->src_port_mask &&
2612 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2613 bfilter->dst_ipaddr_mask[0] ==
2614 mfilter->dst_ipaddr_mask[0] &&
2615 bfilter->dst_port == mfilter->dst_port &&
2616 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2617 bfilter->flags == mfilter->flags &&
2618 bfilter->enables == mfilter->enables) {
2629 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2630 struct rte_eth_ntuple_filter *nfilter,
2631 enum rte_filter_op filter_op)
2633 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2634 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2637 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2638 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2642 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2643 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2647 bfilter = bnxt_get_unused_filter(bp);
2648 if (bfilter == NULL) {
2650 "Not enough resources for a new filter.\n");
2653 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2657 vnic = &bp->vnic_info[nfilter->queue];
2658 vnic0 = &bp->vnic_info[0];
2659 filter1 = STAILQ_FIRST(&vnic0->filter);
2660 if (filter1 == NULL) {
2665 bfilter->dst_id = vnic->fw_vnic_id;
2666 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2668 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2669 bfilter->ethertype = 0x800;
2670 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2672 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2674 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2675 bfilter->dst_id == mfilter->dst_id) {
2676 PMD_DRV_LOG(ERR, "filter exists.\n");
2679 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2680 bfilter->dst_id != mfilter->dst_id) {
2681 mfilter->dst_id = vnic->fw_vnic_id;
2682 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2683 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2684 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2685 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2686 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2689 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2690 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2695 if (filter_op == RTE_ETH_FILTER_ADD) {
2696 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2697 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2700 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2702 if (mfilter == NULL) {
2703 /* This should not happen. But for Coverity! */
2707 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2709 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2710 bnxt_free_filter(bp, mfilter);
2711 mfilter->fw_l2_filter_id = -1;
2712 bnxt_free_filter(bp, bfilter);
2713 bfilter->fw_l2_filter_id = -1;
2718 bfilter->fw_l2_filter_id = -1;
2719 bnxt_free_filter(bp, bfilter);
2724 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2725 enum rte_filter_op filter_op,
2728 struct bnxt *bp = dev->data->dev_private;
2731 if (filter_op == RTE_ETH_FILTER_NOP)
2735 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2740 switch (filter_op) {
2741 case RTE_ETH_FILTER_ADD:
2742 ret = bnxt_cfg_ntuple_filter(bp,
2743 (struct rte_eth_ntuple_filter *)arg,
2746 case RTE_ETH_FILTER_DELETE:
2747 ret = bnxt_cfg_ntuple_filter(bp,
2748 (struct rte_eth_ntuple_filter *)arg,
2752 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2760 bnxt_parse_fdir_filter(struct bnxt *bp,
2761 struct rte_eth_fdir_filter *fdir,
2762 struct bnxt_filter_info *filter)
2764 enum rte_fdir_mode fdir_mode =
2765 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2766 struct bnxt_vnic_info *vnic0, *vnic;
2767 struct bnxt_filter_info *filter1;
2771 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2774 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2775 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2777 switch (fdir->input.flow_type) {
2778 case RTE_ETH_FLOW_IPV4:
2779 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2781 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2782 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2783 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2784 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2785 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2786 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2787 filter->ip_addr_type =
2788 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2789 filter->src_ipaddr_mask[0] = 0xffffffff;
2790 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2791 filter->dst_ipaddr_mask[0] = 0xffffffff;
2792 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2793 filter->ethertype = 0x800;
2794 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2796 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2797 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2798 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2799 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2800 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2801 filter->dst_port_mask = 0xffff;
2802 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2803 filter->src_port_mask = 0xffff;
2804 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2805 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2806 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2807 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2808 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2809 filter->ip_protocol = 6;
2810 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2811 filter->ip_addr_type =
2812 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2813 filter->src_ipaddr_mask[0] = 0xffffffff;
2814 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2815 filter->dst_ipaddr_mask[0] = 0xffffffff;
2816 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2817 filter->ethertype = 0x800;
2818 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2820 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2821 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2822 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2823 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2824 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2825 filter->dst_port_mask = 0xffff;
2826 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2827 filter->src_port_mask = 0xffff;
2828 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2829 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2830 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2831 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2832 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2833 filter->ip_protocol = 17;
2834 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2835 filter->ip_addr_type =
2836 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2837 filter->src_ipaddr_mask[0] = 0xffffffff;
2838 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2839 filter->dst_ipaddr_mask[0] = 0xffffffff;
2840 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2841 filter->ethertype = 0x800;
2842 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2844 case RTE_ETH_FLOW_IPV6:
2845 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2847 filter->ip_addr_type =
2848 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2849 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2850 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2851 rte_memcpy(filter->src_ipaddr,
2852 fdir->input.flow.ipv6_flow.src_ip, 16);
2853 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2854 rte_memcpy(filter->dst_ipaddr,
2855 fdir->input.flow.ipv6_flow.dst_ip, 16);
2856 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2857 memset(filter->dst_ipaddr_mask, 0xff, 16);
2858 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2859 memset(filter->src_ipaddr_mask, 0xff, 16);
2860 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2861 filter->ethertype = 0x86dd;
2862 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2864 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2865 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2866 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2867 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2868 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2869 filter->dst_port_mask = 0xffff;
2870 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2871 filter->src_port_mask = 0xffff;
2872 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2873 filter->ip_addr_type =
2874 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2875 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2876 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2877 rte_memcpy(filter->src_ipaddr,
2878 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2879 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2880 rte_memcpy(filter->dst_ipaddr,
2881 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2882 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2883 memset(filter->dst_ipaddr_mask, 0xff, 16);
2884 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2885 memset(filter->src_ipaddr_mask, 0xff, 16);
2886 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2887 filter->ethertype = 0x86dd;
2888 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2890 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2891 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2892 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2893 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2894 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2895 filter->dst_port_mask = 0xffff;
2896 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2897 filter->src_port_mask = 0xffff;
2898 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2899 filter->ip_addr_type =
2900 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2901 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2902 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2903 rte_memcpy(filter->src_ipaddr,
2904 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2905 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2906 rte_memcpy(filter->dst_ipaddr,
2907 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2908 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2909 memset(filter->dst_ipaddr_mask, 0xff, 16);
2910 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2911 memset(filter->src_ipaddr_mask, 0xff, 16);
2912 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2913 filter->ethertype = 0x86dd;
2914 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2916 case RTE_ETH_FLOW_L2_PAYLOAD:
2917 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2918 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2920 case RTE_ETH_FLOW_VXLAN:
2921 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2923 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2924 filter->tunnel_type =
2925 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2926 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2928 case RTE_ETH_FLOW_NVGRE:
2929 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2931 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2932 filter->tunnel_type =
2933 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2934 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2936 case RTE_ETH_FLOW_UNKNOWN:
2937 case RTE_ETH_FLOW_RAW:
2938 case RTE_ETH_FLOW_FRAG_IPV4:
2939 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2940 case RTE_ETH_FLOW_FRAG_IPV6:
2941 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2942 case RTE_ETH_FLOW_IPV6_EX:
2943 case RTE_ETH_FLOW_IPV6_TCP_EX:
2944 case RTE_ETH_FLOW_IPV6_UDP_EX:
2945 case RTE_ETH_FLOW_GENEVE:
2951 vnic0 = &bp->vnic_info[0];
2952 vnic = &bp->vnic_info[fdir->action.rx_queue];
2954 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2959 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2960 rte_memcpy(filter->dst_macaddr,
2961 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2962 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2965 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2966 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2967 filter1 = STAILQ_FIRST(&vnic0->filter);
2968 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2970 filter->dst_id = vnic->fw_vnic_id;
2971 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2972 if (filter->dst_macaddr[i] == 0x00)
2973 filter1 = STAILQ_FIRST(&vnic0->filter);
2975 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2978 if (filter1 == NULL)
2981 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2982 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2984 filter->enables = en;
2989 static struct bnxt_filter_info *
2990 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2991 struct bnxt_vnic_info **mvnic)
2993 struct bnxt_filter_info *mf = NULL;
2996 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2997 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2999 STAILQ_FOREACH(mf, &vnic->filter, next) {
3000 if (mf->filter_type == nf->filter_type &&
3001 mf->flags == nf->flags &&
3002 mf->src_port == nf->src_port &&
3003 mf->src_port_mask == nf->src_port_mask &&
3004 mf->dst_port == nf->dst_port &&
3005 mf->dst_port_mask == nf->dst_port_mask &&
3006 mf->ip_protocol == nf->ip_protocol &&
3007 mf->ip_addr_type == nf->ip_addr_type &&
3008 mf->ethertype == nf->ethertype &&
3009 mf->vni == nf->vni &&
3010 mf->tunnel_type == nf->tunnel_type &&
3011 mf->l2_ovlan == nf->l2_ovlan &&
3012 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3013 mf->l2_ivlan == nf->l2_ivlan &&
3014 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3015 !memcmp(mf->l2_addr, nf->l2_addr,
3016 RTE_ETHER_ADDR_LEN) &&
3017 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3018 RTE_ETHER_ADDR_LEN) &&
3019 !memcmp(mf->src_macaddr, nf->src_macaddr,
3020 RTE_ETHER_ADDR_LEN) &&
3021 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3022 RTE_ETHER_ADDR_LEN) &&
3023 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3024 sizeof(nf->src_ipaddr)) &&
3025 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3026 sizeof(nf->src_ipaddr_mask)) &&
3027 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3028 sizeof(nf->dst_ipaddr)) &&
3029 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3030 sizeof(nf->dst_ipaddr_mask))) {
3041 bnxt_fdir_filter(struct rte_eth_dev *dev,
3042 enum rte_filter_op filter_op,
3045 struct bnxt *bp = dev->data->dev_private;
3046 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3047 struct bnxt_filter_info *filter, *match;
3048 struct bnxt_vnic_info *vnic, *mvnic;
3051 if (filter_op == RTE_ETH_FILTER_NOP)
3054 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3057 switch (filter_op) {
3058 case RTE_ETH_FILTER_ADD:
3059 case RTE_ETH_FILTER_DELETE:
3061 filter = bnxt_get_unused_filter(bp);
3062 if (filter == NULL) {
3064 "Not enough resources for a new flow.\n");
3068 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3071 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3073 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3074 vnic = &bp->vnic_info[0];
3076 vnic = &bp->vnic_info[fdir->action.rx_queue];
3078 match = bnxt_match_fdir(bp, filter, &mvnic);
3079 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3080 if (match->dst_id == vnic->fw_vnic_id) {
3081 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3085 match->dst_id = vnic->fw_vnic_id;
3086 ret = bnxt_hwrm_set_ntuple_filter(bp,
3089 STAILQ_REMOVE(&mvnic->filter, match,
3090 bnxt_filter_info, next);
3091 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3093 "Filter with matching pattern exist\n");
3095 "Updated it to new destination q\n");
3099 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3100 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3105 if (filter_op == RTE_ETH_FILTER_ADD) {
3106 ret = bnxt_hwrm_set_ntuple_filter(bp,
3111 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3113 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3114 STAILQ_REMOVE(&vnic->filter, match,
3115 bnxt_filter_info, next);
3116 bnxt_free_filter(bp, match);
3117 filter->fw_l2_filter_id = -1;
3118 bnxt_free_filter(bp, filter);
3121 case RTE_ETH_FILTER_FLUSH:
3122 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3123 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3125 STAILQ_FOREACH(filter, &vnic->filter, next) {
3126 if (filter->filter_type ==
3127 HWRM_CFA_NTUPLE_FILTER) {
3129 bnxt_hwrm_clear_ntuple_filter(bp,
3131 STAILQ_REMOVE(&vnic->filter, filter,
3132 bnxt_filter_info, next);
3137 case RTE_ETH_FILTER_UPDATE:
3138 case RTE_ETH_FILTER_STATS:
3139 case RTE_ETH_FILTER_INFO:
3140 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3143 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3150 filter->fw_l2_filter_id = -1;
3151 bnxt_free_filter(bp, filter);
3156 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3157 enum rte_filter_type filter_type,
3158 enum rte_filter_op filter_op, void *arg)
3162 ret = is_bnxt_in_error(dev->data->dev_private);
3166 switch (filter_type) {
3167 case RTE_ETH_FILTER_TUNNEL:
3169 "filter type: %d: To be implemented\n", filter_type);
3171 case RTE_ETH_FILTER_FDIR:
3172 ret = bnxt_fdir_filter(dev, filter_op, arg);
3174 case RTE_ETH_FILTER_NTUPLE:
3175 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3177 case RTE_ETH_FILTER_ETHERTYPE:
3178 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3180 case RTE_ETH_FILTER_GENERIC:
3181 if (filter_op != RTE_ETH_FILTER_GET)
3183 *(const void **)arg = &bnxt_flow_ops;
3187 "Filter type (%d) not supported", filter_type);
3194 static const uint32_t *
3195 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3197 static const uint32_t ptypes[] = {
3198 RTE_PTYPE_L2_ETHER_VLAN,
3199 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3200 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3204 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3205 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3206 RTE_PTYPE_INNER_L4_ICMP,
3207 RTE_PTYPE_INNER_L4_TCP,
3208 RTE_PTYPE_INNER_L4_UDP,
3212 if (!dev->rx_pkt_burst)
3218 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3221 uint32_t reg_base = *reg_arr & 0xfffff000;
3225 for (i = 0; i < count; i++) {
3226 if ((reg_arr[i] & 0xfffff000) != reg_base)
3229 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3230 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3234 static int bnxt_map_ptp_regs(struct bnxt *bp)
3236 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3240 reg_arr = ptp->rx_regs;
3241 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3245 reg_arr = ptp->tx_regs;
3246 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3250 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3251 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3253 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3254 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3259 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3261 rte_write32(0, (uint8_t *)bp->bar0 +
3262 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3263 rte_write32(0, (uint8_t *)bp->bar0 +
3264 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3267 static uint64_t bnxt_cc_read(struct bnxt *bp)
3271 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3272 BNXT_GRCPF_REG_SYNC_TIME));
3273 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3274 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3278 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3280 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3283 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3284 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3285 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3288 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3289 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3290 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3291 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3292 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3293 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3298 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3300 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3301 struct bnxt_pf_info *pf = &bp->pf;
3308 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3309 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3310 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3313 port_id = pf->port_id;
3314 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3315 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3317 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3318 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3319 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3320 /* bnxt_clr_rx_ts(bp); TBD */
3324 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3325 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3326 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3327 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3333 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3336 struct bnxt *bp = dev->data->dev_private;
3337 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3342 ns = rte_timespec_to_ns(ts);
3343 /* Set the timecounters to a new value. */
3350 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3352 struct bnxt *bp = dev->data->dev_private;
3353 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3354 uint64_t ns, systime_cycles = 0;
3360 if (BNXT_CHIP_THOR(bp))
3361 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3364 systime_cycles = bnxt_cc_read(bp);
3366 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3367 *ts = rte_ns_to_timespec(ns);
3372 bnxt_timesync_enable(struct rte_eth_dev *dev)
3374 struct bnxt *bp = dev->data->dev_private;
3375 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3383 ptp->tx_tstamp_en = 1;
3384 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3386 rc = bnxt_hwrm_ptp_cfg(bp);
3390 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3391 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3392 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3394 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3395 ptp->tc.cc_shift = shift;
3396 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3398 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3399 ptp->rx_tstamp_tc.cc_shift = shift;
3400 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3402 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3403 ptp->tx_tstamp_tc.cc_shift = shift;
3404 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3406 if (!BNXT_CHIP_THOR(bp))
3407 bnxt_map_ptp_regs(bp);
3413 bnxt_timesync_disable(struct rte_eth_dev *dev)
3415 struct bnxt *bp = dev->data->dev_private;
3416 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3422 ptp->tx_tstamp_en = 0;
3425 bnxt_hwrm_ptp_cfg(bp);
3427 if (!BNXT_CHIP_THOR(bp))
3428 bnxt_unmap_ptp_regs(bp);
3434 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3435 struct timespec *timestamp,
3436 uint32_t flags __rte_unused)
3438 struct bnxt *bp = dev->data->dev_private;
3439 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3440 uint64_t rx_tstamp_cycles = 0;
3446 if (BNXT_CHIP_THOR(bp))
3447 rx_tstamp_cycles = ptp->rx_timestamp;
3449 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3451 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3452 *timestamp = rte_ns_to_timespec(ns);
3457 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3458 struct timespec *timestamp)
3460 struct bnxt *bp = dev->data->dev_private;
3461 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3462 uint64_t tx_tstamp_cycles = 0;
3469 if (BNXT_CHIP_THOR(bp))
3470 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3473 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3475 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3476 *timestamp = rte_ns_to_timespec(ns);
3482 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3484 struct bnxt *bp = dev->data->dev_private;
3485 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3490 ptp->tc.nsec += delta;
3496 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3498 struct bnxt *bp = dev->data->dev_private;
3500 uint32_t dir_entries;
3501 uint32_t entry_length;
3503 rc = is_bnxt_in_error(bp);
3507 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3508 bp->pdev->addr.domain, bp->pdev->addr.bus,
3509 bp->pdev->addr.devid, bp->pdev->addr.function);
3511 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3515 return dir_entries * entry_length;
3519 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3520 struct rte_dev_eeprom_info *in_eeprom)
3522 struct bnxt *bp = dev->data->dev_private;
3527 rc = is_bnxt_in_error(bp);
3531 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3532 "len = %d\n", bp->pdev->addr.domain,
3533 bp->pdev->addr.bus, bp->pdev->addr.devid,
3534 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3536 if (in_eeprom->offset == 0) /* special offset value to get directory */
3537 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3540 index = in_eeprom->offset >> 24;
3541 offset = in_eeprom->offset & 0xffffff;
3544 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3545 in_eeprom->length, in_eeprom->data);
3550 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3553 case BNX_DIR_TYPE_CHIMP_PATCH:
3554 case BNX_DIR_TYPE_BOOTCODE:
3555 case BNX_DIR_TYPE_BOOTCODE_2:
3556 case BNX_DIR_TYPE_APE_FW:
3557 case BNX_DIR_TYPE_APE_PATCH:
3558 case BNX_DIR_TYPE_KONG_FW:
3559 case BNX_DIR_TYPE_KONG_PATCH:
3560 case BNX_DIR_TYPE_BONO_FW:
3561 case BNX_DIR_TYPE_BONO_PATCH:
3569 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3572 case BNX_DIR_TYPE_AVS:
3573 case BNX_DIR_TYPE_EXP_ROM_MBA:
3574 case BNX_DIR_TYPE_PCIE:
3575 case BNX_DIR_TYPE_TSCF_UCODE:
3576 case BNX_DIR_TYPE_EXT_PHY:
3577 case BNX_DIR_TYPE_CCM:
3578 case BNX_DIR_TYPE_ISCSI_BOOT:
3579 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3580 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3588 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3590 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3591 bnxt_dir_type_is_other_exec_format(dir_type);
3595 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3596 struct rte_dev_eeprom_info *in_eeprom)
3598 struct bnxt *bp = dev->data->dev_private;
3599 uint8_t index, dir_op;
3600 uint16_t type, ext, ordinal, attr;
3603 rc = is_bnxt_in_error(bp);
3607 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3608 "len = %d\n", bp->pdev->addr.domain,
3609 bp->pdev->addr.bus, bp->pdev->addr.devid,
3610 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3613 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3617 type = in_eeprom->magic >> 16;
3619 if (type == 0xffff) { /* special value for directory operations */
3620 index = in_eeprom->magic & 0xff;
3621 dir_op = in_eeprom->magic >> 8;
3625 case 0x0e: /* erase */
3626 if (in_eeprom->offset != ~in_eeprom->magic)
3628 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3634 /* Create or re-write an NVM item: */
3635 if (bnxt_dir_type_is_executable(type) == true)
3637 ext = in_eeprom->magic & 0xffff;
3638 ordinal = in_eeprom->offset >> 16;
3639 attr = in_eeprom->offset & 0xffff;
3641 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3642 in_eeprom->data, in_eeprom->length);
3649 static const struct eth_dev_ops bnxt_dev_ops = {
3650 .dev_infos_get = bnxt_dev_info_get_op,
3651 .dev_close = bnxt_dev_close_op,
3652 .dev_configure = bnxt_dev_configure_op,
3653 .dev_start = bnxt_dev_start_op,
3654 .dev_stop = bnxt_dev_stop_op,
3655 .dev_set_link_up = bnxt_dev_set_link_up_op,
3656 .dev_set_link_down = bnxt_dev_set_link_down_op,
3657 .stats_get = bnxt_stats_get_op,
3658 .stats_reset = bnxt_stats_reset_op,
3659 .rx_queue_setup = bnxt_rx_queue_setup_op,
3660 .rx_queue_release = bnxt_rx_queue_release_op,
3661 .tx_queue_setup = bnxt_tx_queue_setup_op,
3662 .tx_queue_release = bnxt_tx_queue_release_op,
3663 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3664 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3665 .reta_update = bnxt_reta_update_op,
3666 .reta_query = bnxt_reta_query_op,
3667 .rss_hash_update = bnxt_rss_hash_update_op,
3668 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3669 .link_update = bnxt_link_update_op,
3670 .promiscuous_enable = bnxt_promiscuous_enable_op,
3671 .promiscuous_disable = bnxt_promiscuous_disable_op,
3672 .allmulticast_enable = bnxt_allmulticast_enable_op,
3673 .allmulticast_disable = bnxt_allmulticast_disable_op,
3674 .mac_addr_add = bnxt_mac_addr_add_op,
3675 .mac_addr_remove = bnxt_mac_addr_remove_op,
3676 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3677 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3678 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3679 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3680 .vlan_filter_set = bnxt_vlan_filter_set_op,
3681 .vlan_offload_set = bnxt_vlan_offload_set_op,
3682 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3683 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3684 .mtu_set = bnxt_mtu_set_op,
3685 .mac_addr_set = bnxt_set_default_mac_addr_op,
3686 .xstats_get = bnxt_dev_xstats_get_op,
3687 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3688 .xstats_reset = bnxt_dev_xstats_reset_op,
3689 .fw_version_get = bnxt_fw_version_get,
3690 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3691 .rxq_info_get = bnxt_rxq_info_get_op,
3692 .txq_info_get = bnxt_txq_info_get_op,
3693 .dev_led_on = bnxt_dev_led_on_op,
3694 .dev_led_off = bnxt_dev_led_off_op,
3695 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3696 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3697 .rx_queue_count = bnxt_rx_queue_count_op,
3698 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3699 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3700 .rx_queue_start = bnxt_rx_queue_start,
3701 .rx_queue_stop = bnxt_rx_queue_stop,
3702 .tx_queue_start = bnxt_tx_queue_start,
3703 .tx_queue_stop = bnxt_tx_queue_stop,
3704 .filter_ctrl = bnxt_filter_ctrl_op,
3705 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3706 .get_eeprom_length = bnxt_get_eeprom_length_op,
3707 .get_eeprom = bnxt_get_eeprom_op,
3708 .set_eeprom = bnxt_set_eeprom_op,
3709 .timesync_enable = bnxt_timesync_enable,
3710 .timesync_disable = bnxt_timesync_disable,
3711 .timesync_read_time = bnxt_timesync_read_time,
3712 .timesync_write_time = bnxt_timesync_write_time,
3713 .timesync_adjust_time = bnxt_timesync_adjust_time,
3714 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3715 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3718 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3722 /* Only pre-map the reset GRC registers using window 3 */
3723 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3724 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3726 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3731 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3733 struct bnxt_error_recovery_info *info = bp->recovery_info;
3734 uint32_t reg_base = 0xffffffff;
3737 /* Only pre-map the monitoring GRC registers using window 2 */
3738 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3739 uint32_t reg = info->status_regs[i];
3741 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3744 if (reg_base == 0xffffffff)
3745 reg_base = reg & 0xfffff000;
3746 if ((reg & 0xfffff000) != reg_base)
3749 /* Use mask 0xffc as the Lower 2 bits indicates
3750 * address space location
3752 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3756 if (reg_base == 0xffffffff)
3759 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3760 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3765 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3767 struct bnxt_error_recovery_info *info = bp->recovery_info;
3768 uint32_t delay = info->delay_after_reset[index];
3769 uint32_t val = info->reset_reg_val[index];
3770 uint32_t reg = info->reset_reg[index];
3771 uint32_t type, offset;
3773 type = BNXT_FW_STATUS_REG_TYPE(reg);
3774 offset = BNXT_FW_STATUS_REG_OFF(reg);
3777 case BNXT_FW_STATUS_REG_TYPE_CFG:
3778 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3780 case BNXT_FW_STATUS_REG_TYPE_GRC:
3781 offset = bnxt_map_reset_regs(bp, offset);
3782 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3784 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3785 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3788 /* wait on a specific interval of time until core reset is complete */
3790 rte_delay_ms(delay);
3793 static void bnxt_dev_cleanup(struct bnxt *bp)
3795 bnxt_set_hwrm_link_config(bp, false);
3796 bp->link_info.link_up = 0;
3797 if (bp->dev_stopped == 0)
3798 bnxt_dev_stop_op(bp->eth_dev);
3800 bnxt_uninit_resources(bp, true);
3803 static int bnxt_restore_filters(struct bnxt *bp)
3805 struct rte_eth_dev *dev = bp->eth_dev;
3808 if (dev->data->all_multicast)
3809 ret = bnxt_allmulticast_enable_op(dev);
3810 if (dev->data->promiscuous)
3811 ret = bnxt_promiscuous_enable_op(dev);
3813 /* TODO restore other filters as well */
3817 static void bnxt_dev_recover(void *arg)
3819 struct bnxt *bp = arg;
3820 int timeout = bp->fw_reset_max_msecs;
3823 /* Clear Error flag so that device re-init should happen */
3824 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3827 rc = bnxt_hwrm_ver_get(bp);
3830 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3831 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3832 } while (rc && timeout);
3835 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3839 rc = bnxt_init_resources(bp, true);
3842 "Failed to initialize resources after reset\n");
3845 /* clear reset flag as the device is initialized now */
3846 bp->flags &= ~BNXT_FLAG_FW_RESET;
3848 rc = bnxt_dev_start_op(bp->eth_dev);
3850 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3854 rc = bnxt_restore_filters(bp);
3858 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3861 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3862 bnxt_uninit_resources(bp, false);
3863 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3866 void bnxt_dev_reset_and_resume(void *arg)
3868 struct bnxt *bp = arg;
3871 bnxt_dev_cleanup(bp);
3873 bnxt_wait_for_device_shutdown(bp);
3875 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3876 bnxt_dev_recover, (void *)bp);
3878 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3881 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3883 struct bnxt_error_recovery_info *info = bp->recovery_info;
3884 uint32_t reg = info->status_regs[index];
3885 uint32_t type, offset, val = 0;
3887 type = BNXT_FW_STATUS_REG_TYPE(reg);
3888 offset = BNXT_FW_STATUS_REG_OFF(reg);
3891 case BNXT_FW_STATUS_REG_TYPE_CFG:
3892 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3894 case BNXT_FW_STATUS_REG_TYPE_GRC:
3895 offset = info->mapped_status_regs[index];
3897 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3898 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3906 static int bnxt_fw_reset_all(struct bnxt *bp)
3908 struct bnxt_error_recovery_info *info = bp->recovery_info;
3912 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3913 /* Reset through master function driver */
3914 for (i = 0; i < info->reg_array_cnt; i++)
3915 bnxt_write_fw_reset_reg(bp, i);
3916 /* Wait for time specified by FW after triggering reset */
3917 rte_delay_ms(info->master_func_wait_period_after_reset);
3918 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3919 /* Reset with the help of Kong processor */
3920 rc = bnxt_hwrm_fw_reset(bp);
3922 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3928 static void bnxt_fw_reset_cb(void *arg)
3930 struct bnxt *bp = arg;
3931 struct bnxt_error_recovery_info *info = bp->recovery_info;
3934 /* Only Master function can do FW reset */
3935 if (bnxt_is_master_func(bp) &&
3936 bnxt_is_recovery_enabled(bp)) {
3937 rc = bnxt_fw_reset_all(bp);
3939 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3944 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3945 * EXCEPTION_FATAL_ASYNC event to all the functions
3946 * (including MASTER FUNC). After receiving this Async, all the active
3947 * drivers should treat this case as FW initiated recovery
3949 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3950 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3951 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3953 /* To recover from error */
3954 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3959 /* Driver should poll FW heartbeat, reset_counter with the frequency
3960 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3961 * When the driver detects heartbeat stop or change in reset_counter,
3962 * it has to trigger a reset to recover from the error condition.
3963 * A “master PF” is the function who will have the privilege to
3964 * initiate the chimp reset. The master PF will be elected by the
3965 * firmware and will be notified through async message.
3967 static void bnxt_check_fw_health(void *arg)
3969 struct bnxt *bp = arg;
3970 struct bnxt_error_recovery_info *info = bp->recovery_info;
3971 uint32_t val = 0, wait_msec;
3973 if (!info || !bnxt_is_recovery_enabled(bp) ||
3974 is_bnxt_in_error(bp))
3977 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3978 if (val == info->last_heart_beat)
3981 info->last_heart_beat = val;
3983 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3984 if (val != info->last_reset_counter)
3987 info->last_reset_counter = val;
3989 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3990 bnxt_check_fw_health, (void *)bp);
3994 /* Stop DMA to/from device */
3995 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3996 bp->flags |= BNXT_FLAG_FW_RESET;
3998 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4000 if (bnxt_is_master_func(bp))
4001 wait_msec = info->master_func_wait_period;
4003 wait_msec = info->normal_func_wait_period;
4005 rte_eal_alarm_set(US_PER_MS * wait_msec,
4006 bnxt_fw_reset_cb, (void *)bp);
4009 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4011 uint32_t polling_freq;
4013 if (!bnxt_is_recovery_enabled(bp))
4016 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4019 polling_freq = bp->recovery_info->driver_polling_freq;
4021 rte_eal_alarm_set(US_PER_MS * polling_freq,
4022 bnxt_check_fw_health, (void *)bp);
4023 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4026 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4028 if (!bnxt_is_recovery_enabled(bp))
4031 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4032 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4035 static bool bnxt_vf_pciid(uint16_t id)
4037 if (id == BROADCOM_DEV_ID_57304_VF ||
4038 id == BROADCOM_DEV_ID_57406_VF ||
4039 id == BROADCOM_DEV_ID_5731X_VF ||
4040 id == BROADCOM_DEV_ID_5741X_VF ||
4041 id == BROADCOM_DEV_ID_57414_VF ||
4042 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4043 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
4044 id == BROADCOM_DEV_ID_58802_VF ||
4045 id == BROADCOM_DEV_ID_57500_VF1 ||
4046 id == BROADCOM_DEV_ID_57500_VF2)
4051 bool bnxt_stratus_device(struct bnxt *bp)
4053 uint16_t id = bp->pdev->id.device_id;
4055 if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
4056 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4057 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
4062 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4064 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4065 struct bnxt *bp = eth_dev->data->dev_private;
4067 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4068 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4069 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4070 if (!bp->bar0 || !bp->doorbell_base) {
4071 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4075 bp->eth_dev = eth_dev;
4081 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
4082 struct bnxt_ctx_pg_info *ctx_pg,
4087 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4088 const struct rte_memzone *mz = NULL;
4089 char mz_name[RTE_MEMZONE_NAMESIZE];
4090 rte_iova_t mz_phys_addr;
4091 uint64_t valid_bits = 0;
4098 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4100 rmem->page_size = BNXT_PAGE_SIZE;
4101 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4102 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4103 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4105 valid_bits = PTU_PTE_VALID;
4107 if (rmem->nr_pages > 1) {
4108 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4109 "bnxt_ctx_pg_tbl%s_%x_%d",
4110 suffix, idx, bp->eth_dev->data->port_id);
4111 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4112 mz = rte_memzone_lookup(mz_name);
4114 mz = rte_memzone_reserve_aligned(mz_name,
4118 RTE_MEMZONE_SIZE_HINT_ONLY |
4119 RTE_MEMZONE_IOVA_CONTIG,
4125 memset(mz->addr, 0, mz->len);
4126 mz_phys_addr = mz->iova;
4127 if ((unsigned long)mz->addr == mz_phys_addr) {
4129 "physical address same as virtual\n");
4130 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4131 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4132 if (mz_phys_addr == RTE_BAD_IOVA) {
4134 "unable to map addr to phys memory\n");
4138 rte_mem_lock_page(((char *)mz->addr));
4140 rmem->pg_tbl = mz->addr;
4141 rmem->pg_tbl_map = mz_phys_addr;
4142 rmem->pg_tbl_mz = mz;
4145 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4146 suffix, idx, bp->eth_dev->data->port_id);
4147 mz = rte_memzone_lookup(mz_name);
4149 mz = rte_memzone_reserve_aligned(mz_name,
4153 RTE_MEMZONE_SIZE_HINT_ONLY |
4154 RTE_MEMZONE_IOVA_CONTIG,
4160 memset(mz->addr, 0, mz->len);
4161 mz_phys_addr = mz->iova;
4162 if ((unsigned long)mz->addr == mz_phys_addr) {
4164 "Memzone physical address same as virtual.\n");
4165 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4166 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4167 rte_mem_lock_page(((char *)mz->addr) + sz);
4168 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4169 if (mz_phys_addr == RTE_BAD_IOVA) {
4171 "unable to map addr to phys memory\n");
4176 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4177 rte_mem_lock_page(((char *)mz->addr) + sz);
4178 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4179 rmem->dma_arr[i] = mz_phys_addr + sz;
4181 if (rmem->nr_pages > 1) {
4182 if (i == rmem->nr_pages - 2 &&
4183 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4184 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4185 else if (i == rmem->nr_pages - 1 &&
4186 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4187 valid_bits |= PTU_PTE_LAST;
4189 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4195 if (rmem->vmem_size)
4196 rmem->vmem = (void **)mz->addr;
4197 rmem->dma_arr[0] = mz_phys_addr;
4201 static void bnxt_free_ctx_mem(struct bnxt *bp)
4205 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4208 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4209 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4210 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4211 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4212 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4213 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4214 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4215 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4216 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4217 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4218 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4220 for (i = 0; i < BNXT_MAX_Q; i++) {
4221 if (bp->ctx->tqm_mem[i])
4222 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4229 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4231 #define min_t(type, x, y) ({ \
4232 type __min1 = (x); \
4233 type __min2 = (y); \
4234 __min1 < __min2 ? __min1 : __min2; })
4236 #define max_t(type, x, y) ({ \
4237 type __max1 = (x); \
4238 type __max2 = (y); \
4239 __max1 > __max2 ? __max1 : __max2; })
4241 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4243 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4245 struct bnxt_ctx_pg_info *ctx_pg;
4246 struct bnxt_ctx_mem_info *ctx;
4247 uint32_t mem_size, ena, entries;
4250 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4252 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4256 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4259 ctx_pg = &ctx->qp_mem;
4260 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4261 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4262 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4266 ctx_pg = &ctx->srq_mem;
4267 ctx_pg->entries = ctx->srq_max_l2_entries;
4268 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4269 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4273 ctx_pg = &ctx->cq_mem;
4274 ctx_pg->entries = ctx->cq_max_l2_entries;
4275 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4276 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4280 ctx_pg = &ctx->vnic_mem;
4281 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4282 ctx->vnic_max_ring_table_entries;
4283 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4284 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4288 ctx_pg = &ctx->stat_mem;
4289 ctx_pg->entries = ctx->stat_max_entries;
4290 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4291 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4295 entries = ctx->qp_max_l2_entries +
4296 ctx->vnic_max_vnic_entries +
4297 ctx->tqm_min_entries_per_ring;
4298 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4299 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4300 ctx->tqm_max_entries_per_ring);
4301 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4302 ctx_pg = ctx->tqm_mem[i];
4303 /* use min tqm entries for now. */
4304 ctx_pg->entries = entries;
4305 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4306 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4309 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4312 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4313 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4316 "Failed to configure context mem: rc = %d\n", rc);
4318 ctx->flags |= BNXT_CTX_FLAG_INITED;
4323 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4325 struct rte_pci_device *pci_dev = bp->pdev;
4326 char mz_name[RTE_MEMZONE_NAMESIZE];
4327 const struct rte_memzone *mz = NULL;
4328 uint32_t total_alloc_len;
4329 rte_iova_t mz_phys_addr;
4331 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4334 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4335 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4336 pci_dev->addr.bus, pci_dev->addr.devid,
4337 pci_dev->addr.function, "rx_port_stats");
4338 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4339 mz = rte_memzone_lookup(mz_name);
4341 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4342 sizeof(struct rx_port_stats_ext) + 512);
4344 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4347 RTE_MEMZONE_SIZE_HINT_ONLY |
4348 RTE_MEMZONE_IOVA_CONTIG);
4352 memset(mz->addr, 0, mz->len);
4353 mz_phys_addr = mz->iova;
4354 if ((unsigned long)mz->addr == mz_phys_addr) {
4356 "Memzone physical address same as virtual.\n");
4358 "Using rte_mem_virt2iova()\n");
4359 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4360 if (mz_phys_addr == RTE_BAD_IOVA) {
4362 "Can't map address to physical memory\n");
4367 bp->rx_mem_zone = (const void *)mz;
4368 bp->hw_rx_port_stats = mz->addr;
4369 bp->hw_rx_port_stats_map = mz_phys_addr;
4371 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4372 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4373 pci_dev->addr.bus, pci_dev->addr.devid,
4374 pci_dev->addr.function, "tx_port_stats");
4375 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4376 mz = rte_memzone_lookup(mz_name);
4378 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4379 sizeof(struct tx_port_stats_ext) + 512);
4381 mz = rte_memzone_reserve(mz_name,
4385 RTE_MEMZONE_SIZE_HINT_ONLY |
4386 RTE_MEMZONE_IOVA_CONTIG);
4390 memset(mz->addr, 0, mz->len);
4391 mz_phys_addr = mz->iova;
4392 if ((unsigned long)mz->addr == mz_phys_addr) {
4394 "Memzone physical address same as virtual\n");
4395 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4396 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4397 if (mz_phys_addr == RTE_BAD_IOVA) {
4399 "Can't map address to physical memory\n");
4404 bp->tx_mem_zone = (const void *)mz;
4405 bp->hw_tx_port_stats = mz->addr;
4406 bp->hw_tx_port_stats_map = mz_phys_addr;
4407 bp->flags |= BNXT_FLAG_PORT_STATS;
4409 /* Display extended statistics if FW supports it */
4410 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4411 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4412 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4415 bp->hw_rx_port_stats_ext = (void *)
4416 ((uint8_t *)bp->hw_rx_port_stats +
4417 sizeof(struct rx_port_stats));
4418 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4419 sizeof(struct rx_port_stats);
4420 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4422 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4423 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4424 bp->hw_tx_port_stats_ext = (void *)
4425 ((uint8_t *)bp->hw_tx_port_stats +
4426 sizeof(struct tx_port_stats));
4427 bp->hw_tx_port_stats_ext_map =
4428 bp->hw_tx_port_stats_map +
4429 sizeof(struct tx_port_stats);
4430 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4436 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4438 struct bnxt *bp = eth_dev->data->dev_private;
4441 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4442 RTE_ETHER_ADDR_LEN *
4445 if (eth_dev->data->mac_addrs == NULL) {
4446 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4450 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4454 /* Generate a random MAC address, if none was assigned by PF */
4455 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4456 bnxt_eth_hw_addr_random(bp->mac_addr);
4458 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4459 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4460 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4462 rc = bnxt_hwrm_set_mac(bp);
4464 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4465 RTE_ETHER_ADDR_LEN);
4469 /* Copy the permanent MAC from the FUNC_QCAPS response */
4470 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4471 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4476 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4480 /* MAC is already configured in FW */
4481 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4484 /* Restore the old MAC configured */
4485 rc = bnxt_hwrm_set_mac(bp);
4487 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4492 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4497 #define ALLOW_FUNC(x) \
4499 uint32_t arg = (x); \
4500 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4501 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4504 /* Forward all requests if firmware is new enough */
4505 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4506 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4507 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4508 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4510 PMD_DRV_LOG(WARNING,
4511 "Firmware too old for VF mailbox functionality\n");
4512 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4516 * The following are used for driver cleanup. If we disallow these,
4517 * VF drivers can't clean up cleanly.
4519 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4520 ALLOW_FUNC(HWRM_VNIC_FREE);
4521 ALLOW_FUNC(HWRM_RING_FREE);
4522 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4523 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4524 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4525 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4526 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4527 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4530 static int bnxt_init_fw(struct bnxt *bp)
4535 rc = bnxt_hwrm_ver_get(bp);
4539 rc = bnxt_hwrm_func_reset(bp);
4543 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4547 rc = bnxt_hwrm_queue_qportcfg(bp);
4551 /* Get the MAX capabilities for this function */
4552 rc = bnxt_hwrm_func_qcaps(bp);
4556 rc = bnxt_hwrm_vnic_qcaps(bp);
4560 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4564 /* Get the adapter error recovery support info */
4565 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4567 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4569 if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4570 mtu != bp->eth_dev->data->mtu)
4571 bp->eth_dev->data->mtu = mtu;
4573 bnxt_hwrm_port_led_qcaps(bp);
4579 bnxt_init_locks(struct bnxt *bp)
4583 err = pthread_mutex_init(&bp->flow_lock, NULL);
4585 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4589 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4593 rc = bnxt_init_fw(bp);
4597 if (!reconfig_dev) {
4598 rc = bnxt_setup_mac_addr(bp->eth_dev);
4602 rc = bnxt_restore_dflt_mac(bp);
4607 bnxt_config_vf_req_fwd(bp);
4609 rc = bnxt_hwrm_func_driver_register(bp);
4611 PMD_DRV_LOG(ERR, "Failed to register driver");
4616 if (bp->pdev->max_vfs) {
4617 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4619 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4623 rc = bnxt_hwrm_allocate_pf_only(bp);
4626 "Failed to allocate PF resources");
4632 rc = bnxt_alloc_mem(bp, reconfig_dev);
4636 rc = bnxt_setup_int(bp);
4642 rc = bnxt_request_int(bp);
4646 rc = bnxt_init_locks(bp);
4654 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4656 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4657 static int version_printed;
4661 if (version_printed++ == 0)
4662 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4664 eth_dev->dev_ops = &bnxt_dev_ops;
4665 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4666 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4669 * For secondary processes, we don't initialise any further
4670 * as primary has already done this work.
4672 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4675 rte_eth_copy_pci_info(eth_dev, pci_dev);
4677 bp = eth_dev->data->dev_private;
4679 bp->dev_stopped = 1;
4681 if (bnxt_vf_pciid(pci_dev->id.device_id))
4682 bp->flags |= BNXT_FLAG_VF;
4684 if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4685 pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4686 pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4687 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4688 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4689 bp->flags |= BNXT_FLAG_THOR_CHIP;
4691 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4692 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4693 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4694 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4695 bp->flags |= BNXT_FLAG_STINGRAY;
4697 rc = bnxt_init_board(eth_dev);
4700 "Failed to initialize board rc: %x\n", rc);
4704 rc = bnxt_alloc_hwrm_resources(bp);
4707 "Failed to allocate hwrm resource rc: %x\n", rc);
4710 rc = bnxt_init_resources(bp, false);
4714 rc = bnxt_alloc_stats_mem(bp);
4719 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4720 pci_dev->mem_resource[0].phys_addr,
4721 pci_dev->mem_resource[0].addr);
4726 bnxt_dev_uninit(eth_dev);
4731 bnxt_uninit_locks(struct bnxt *bp)
4733 pthread_mutex_destroy(&bp->flow_lock);
4737 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4742 bnxt_free_mem(bp, reconfig_dev);
4743 bnxt_hwrm_func_buf_unrgtr(bp);
4744 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4745 bp->flags &= ~BNXT_FLAG_REGISTERED;
4746 bnxt_free_ctx_mem(bp);
4747 if (!reconfig_dev) {
4748 bnxt_free_hwrm_resources(bp);
4750 if (bp->recovery_info != NULL) {
4751 rte_free(bp->recovery_info);
4752 bp->recovery_info = NULL;
4756 rte_free(bp->ptp_cfg);
4762 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4764 struct bnxt *bp = eth_dev->data->dev_private;
4767 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4770 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4772 rc = bnxt_uninit_resources(bp, false);
4774 if (bp->grp_info != NULL) {
4775 rte_free(bp->grp_info);
4776 bp->grp_info = NULL;
4779 if (bp->tx_mem_zone) {
4780 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4781 bp->tx_mem_zone = NULL;
4784 if (bp->rx_mem_zone) {
4785 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4786 bp->rx_mem_zone = NULL;
4789 if (bp->dev_stopped == 0)
4790 bnxt_dev_close_op(eth_dev);
4792 rte_free(bp->pf.vf_info);
4793 eth_dev->dev_ops = NULL;
4794 eth_dev->rx_pkt_burst = NULL;
4795 eth_dev->tx_pkt_burst = NULL;
4797 bnxt_uninit_locks(bp);
4802 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4803 struct rte_pci_device *pci_dev)
4805 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4809 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4811 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4812 return rte_eth_dev_pci_generic_remove(pci_dev,
4815 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4818 static struct rte_pci_driver bnxt_rte_pmd = {
4819 .id_table = bnxt_pci_id_map,
4820 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4821 .probe = bnxt_pci_probe,
4822 .remove = bnxt_pci_remove,
4826 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4828 if (strcmp(dev->device->driver->name, drv->driver.name))
4834 bool is_bnxt_supported(struct rte_eth_dev *dev)
4836 return is_device_supported(dev, &bnxt_rte_pmd);
4839 RTE_INIT(bnxt_init_log)
4841 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4842 if (bnxt_logtype_driver >= 0)
4843 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4846 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4847 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4848 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");