1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
29 #include "bnxt_util.h"
31 #define DRV_MODULE_NAME "bnxt"
32 static const char bnxt_version[] =
33 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
34 int bnxt_logtype_driver;
36 #define PCI_VENDOR_ID_BROADCOM 0x14E4
38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
41 #define BROADCOM_DEV_ID_57414_VF 0x16c1
42 #define BROADCOM_DEV_ID_57301 0x16c8
43 #define BROADCOM_DEV_ID_57302 0x16c9
44 #define BROADCOM_DEV_ID_57304_PF 0x16ca
45 #define BROADCOM_DEV_ID_57304_VF 0x16cb
46 #define BROADCOM_DEV_ID_57417_MF 0x16cc
47 #define BROADCOM_DEV_ID_NS2 0x16cd
48 #define BROADCOM_DEV_ID_57311 0x16ce
49 #define BROADCOM_DEV_ID_57312 0x16cf
50 #define BROADCOM_DEV_ID_57402 0x16d0
51 #define BROADCOM_DEV_ID_57404 0x16d1
52 #define BROADCOM_DEV_ID_57406_PF 0x16d2
53 #define BROADCOM_DEV_ID_57406_VF 0x16d3
54 #define BROADCOM_DEV_ID_57402_MF 0x16d4
55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
56 #define BROADCOM_DEV_ID_57412 0x16d6
57 #define BROADCOM_DEV_ID_57414 0x16d7
58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
61 #define BROADCOM_DEV_ID_57412_MF 0x16de
62 #define BROADCOM_DEV_ID_57314 0x16df
63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
68 #define BROADCOM_DEV_ID_57404_MF 0x16e7
69 #define BROADCOM_DEV_ID_57406_MF 0x16e8
70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
71 #define BROADCOM_DEV_ID_57407_MF 0x16ea
72 #define BROADCOM_DEV_ID_57414_MF 0x16ec
73 #define BROADCOM_DEV_ID_57416_MF 0x16ee
74 #define BROADCOM_DEV_ID_57508 0x1750
75 #define BROADCOM_DEV_ID_57504 0x1751
76 #define BROADCOM_DEV_ID_57502 0x1752
77 #define BROADCOM_DEV_ID_57500_VF 0x1807
78 #define BROADCOM_DEV_ID_58802 0xd802
79 #define BROADCOM_DEV_ID_58804 0xd804
80 #define BROADCOM_DEV_ID_58808 0x16f0
81 #define BROADCOM_DEV_ID_58802_VF 0xd800
83 static const struct rte_pci_id bnxt_pci_id_map[] = {
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
85 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
87 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF) },
130 { .vendor_id = 0, /* sentinel */ },
133 #define BNXT_ETH_RSS_SUPPORT ( \
135 ETH_RSS_NONFRAG_IPV4_TCP | \
136 ETH_RSS_NONFRAG_IPV4_UDP | \
138 ETH_RSS_NONFRAG_IPV6_TCP | \
139 ETH_RSS_NONFRAG_IPV6_UDP)
141 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
142 DEV_TX_OFFLOAD_IPV4_CKSUM | \
143 DEV_TX_OFFLOAD_TCP_CKSUM | \
144 DEV_TX_OFFLOAD_UDP_CKSUM | \
145 DEV_TX_OFFLOAD_TCP_TSO | \
146 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
147 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
148 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
149 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
150 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
151 DEV_TX_OFFLOAD_MULTI_SEGS)
153 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
154 DEV_RX_OFFLOAD_VLAN_STRIP | \
155 DEV_RX_OFFLOAD_IPV4_CKSUM | \
156 DEV_RX_OFFLOAD_UDP_CKSUM | \
157 DEV_RX_OFFLOAD_TCP_CKSUM | \
158 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
159 DEV_RX_OFFLOAD_JUMBO_FRAME | \
160 DEV_RX_OFFLOAD_KEEP_CRC | \
161 DEV_RX_OFFLOAD_TCP_LRO)
163 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
164 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
165 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
166 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
168 /***********************/
171 * High level utility functions
174 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
176 if (!BNXT_CHIP_THOR(bp))
179 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
180 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
181 BNXT_RSS_ENTRIES_PER_CTX_THOR;
184 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
186 if (!BNXT_CHIP_THOR(bp))
187 return HW_HASH_INDEX_SIZE;
189 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
192 static void bnxt_free_mem(struct bnxt *bp)
194 bnxt_free_filter_mem(bp);
195 bnxt_free_vnic_attributes(bp);
196 bnxt_free_vnic_mem(bp);
199 bnxt_free_tx_rings(bp);
200 bnxt_free_rx_rings(bp);
203 static int bnxt_alloc_mem(struct bnxt *bp)
207 rc = bnxt_alloc_vnic_mem(bp);
211 rc = bnxt_alloc_vnic_attributes(bp);
215 rc = bnxt_alloc_filter_mem(bp);
226 static int bnxt_init_chip(struct bnxt *bp)
228 struct bnxt_rx_queue *rxq;
229 struct rte_eth_link new;
230 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
231 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
232 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
233 uint64_t rx_offloads = dev_conf->rxmode.offloads;
234 uint32_t intr_vector = 0;
235 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
236 uint32_t vec = BNXT_MISC_VEC_ID;
240 /* disable uio/vfio intr/eventfd mapping */
241 rte_intr_disable(intr_handle);
243 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
244 bp->eth_dev->data->dev_conf.rxmode.offloads |=
245 DEV_RX_OFFLOAD_JUMBO_FRAME;
246 bp->flags |= BNXT_FLAG_JUMBO;
248 bp->eth_dev->data->dev_conf.rxmode.offloads &=
249 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
250 bp->flags &= ~BNXT_FLAG_JUMBO;
253 /* THOR does not support ring groups.
254 * But we will use the array to save RSS context IDs.
256 if (BNXT_CHIP_THOR(bp))
257 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
259 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
261 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
265 rc = bnxt_alloc_hwrm_rings(bp);
267 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
271 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
273 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
277 rc = bnxt_mq_rx_configure(bp);
279 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
283 /* VNIC configuration */
284 for (i = 0; i < bp->nr_vnics; i++) {
285 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
286 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
287 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
289 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
290 if (!vnic->fw_grp_ids) {
292 "Failed to alloc %d bytes for group ids\n",
297 memset(vnic->fw_grp_ids, -1, size);
299 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
300 i, vnic, vnic->fw_grp_ids);
302 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
304 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
309 /* Alloc RSS context only if RSS mode is enabled */
310 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
311 int j, nr_ctxs = bnxt_rss_ctxts(bp);
314 for (j = 0; j < nr_ctxs; j++) {
315 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
321 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
325 vnic->num_lb_ctxts = nr_ctxs;
329 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
330 * setting is not available at this time, it will not be
331 * configured correctly in the CFA.
333 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
334 vnic->vlan_strip = true;
336 vnic->vlan_strip = false;
338 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
340 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
345 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
348 "HWRM vnic %d filter failure rc: %x\n",
353 for (j = 0; j < bp->rx_nr_rings; j++) {
354 rxq = bp->eth_dev->data->rx_queues[j];
357 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
358 j, rxq->vnic, rxq->vnic->fw_grp_ids);
360 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
361 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
364 rc = bnxt_vnic_rss_configure(bp, vnic);
367 "HWRM vnic set RSS failure rc: %x\n", rc);
371 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
373 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
374 DEV_RX_OFFLOAD_TCP_LRO)
375 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
377 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
379 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
382 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
386 /* check and configure queue intr-vector mapping */
387 if ((rte_intr_cap_multiple(intr_handle) ||
388 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
389 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
390 intr_vector = bp->eth_dev->data->nb_rx_queues;
391 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
392 if (intr_vector > bp->rx_cp_nr_rings) {
393 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
397 rc = rte_intr_efd_enable(intr_handle, intr_vector);
402 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
403 intr_handle->intr_vec =
404 rte_zmalloc("intr_vec",
405 bp->eth_dev->data->nb_rx_queues *
407 if (intr_handle->intr_vec == NULL) {
408 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
409 " intr_vec", bp->eth_dev->data->nb_rx_queues);
413 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
414 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
415 intr_handle->intr_vec, intr_handle->nb_efd,
416 intr_handle->max_intr);
417 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
419 intr_handle->intr_vec[queue_id] = vec;
420 if (vec < base + intr_handle->nb_efd - 1)
425 /* enable uio/vfio intr/eventfd mapping */
426 rc = rte_intr_enable(intr_handle);
430 rc = bnxt_get_hwrm_link_config(bp, &new);
432 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
436 if (!bp->link_info.link_up) {
437 rc = bnxt_set_hwrm_link_config(bp, true);
440 "HWRM link config failure rc: %x\n", rc);
444 bnxt_print_link_info(bp->eth_dev);
449 rte_free(intr_handle->intr_vec);
451 rte_intr_efd_disable(intr_handle);
453 /* Some of the error status returned by FW may not be from errno.h */
460 static int bnxt_shutdown_nic(struct bnxt *bp)
462 bnxt_free_all_hwrm_resources(bp);
463 bnxt_free_all_filters(bp);
464 bnxt_free_all_vnics(bp);
468 static int bnxt_init_nic(struct bnxt *bp)
472 if (BNXT_HAS_RING_GRPS(bp)) {
473 rc = bnxt_init_ring_grps(bp);
479 bnxt_init_filters(bp);
485 * Device configuration and status function
488 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
489 struct rte_eth_dev_info *dev_info)
491 struct bnxt *bp = eth_dev->data->dev_private;
492 uint16_t max_vnics, i, j, vpool, vrxq;
493 unsigned int max_rx_rings;
496 dev_info->max_mac_addrs = bp->max_l2_ctx;
497 dev_info->max_hash_mac_addrs = 0;
499 /* PF/VF specifics */
501 dev_info->max_vfs = bp->pdev->max_vfs;
502 max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
503 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
504 dev_info->max_rx_queues = max_rx_rings;
505 dev_info->max_tx_queues = max_rx_rings;
506 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
507 dev_info->hash_key_size = 40;
508 max_vnics = bp->max_vnics;
510 /* Fast path specifics */
511 dev_info->min_rx_bufsize = 1;
512 dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
513 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
515 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
516 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
517 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
518 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
519 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
522 dev_info->default_rxconf = (struct rte_eth_rxconf) {
528 .rx_free_thresh = 32,
529 /* If no descriptors available, pkts are dropped by default */
533 dev_info->default_txconf = (struct rte_eth_txconf) {
539 .tx_free_thresh = 32,
542 eth_dev->data->dev_conf.intr_conf.lsc = 1;
544 eth_dev->data->dev_conf.intr_conf.rxq = 1;
545 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
546 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
547 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
548 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
553 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
554 * need further investigation.
558 vpool = 64; /* ETH_64_POOLS */
559 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
560 for (i = 0; i < 4; vpool >>= 1, i++) {
561 if (max_vnics > vpool) {
562 for (j = 0; j < 5; vrxq >>= 1, j++) {
563 if (dev_info->max_rx_queues > vrxq) {
569 /* Not enough resources to support VMDq */
573 /* Not enough resources to support VMDq */
577 dev_info->max_vmdq_pools = vpool;
578 dev_info->vmdq_queue_num = vrxq;
580 dev_info->vmdq_pool_base = 0;
581 dev_info->vmdq_queue_base = 0;
584 /* Configure the device based on the configuration provided */
585 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
587 struct bnxt *bp = eth_dev->data->dev_private;
588 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
591 bp->rx_queues = (void *)eth_dev->data->rx_queues;
592 bp->tx_queues = (void *)eth_dev->data->tx_queues;
593 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
594 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
596 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
597 rc = bnxt_hwrm_check_vf_rings(bp);
599 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
603 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
605 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
609 /* legacy driver needs to get updated values */
610 rc = bnxt_hwrm_func_qcaps(bp);
612 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
617 /* Inherit new configurations */
618 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
619 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
620 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
622 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
626 if (BNXT_HAS_RING_GRPS(bp) &&
627 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
630 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
631 bp->max_vnics < eth_dev->data->nb_rx_queues)
634 bp->rx_cp_nr_rings = bp->rx_nr_rings;
635 bp->tx_cp_nr_rings = bp->tx_nr_rings;
637 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
639 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
640 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
642 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
648 "Insufficient resources to support requested config\n");
650 "Num Queues Requested: Tx %d, Rx %d\n",
651 eth_dev->data->nb_tx_queues,
652 eth_dev->data->nb_rx_queues);
654 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
655 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
656 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
660 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
662 struct rte_eth_link *link = ð_dev->data->dev_link;
664 if (link->link_status)
665 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
666 eth_dev->data->port_id,
667 (uint32_t)link->link_speed,
668 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
669 ("full-duplex") : ("half-duplex\n"));
671 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
672 eth_dev->data->port_id);
676 * Determine whether the current configuration requires support for scattered
677 * receive; return 1 if scattered receive is required and 0 if not.
679 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
684 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
685 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
687 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
688 RTE_PKTMBUF_HEADROOM);
689 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
695 static eth_rx_burst_t
696 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
700 * Vector mode receive can be enabled only if scatter rx is not
701 * in use and rx offloads are limited to VLAN stripping and
704 if (!eth_dev->data->scattered_rx &&
705 !(eth_dev->data->dev_conf.rxmode.offloads &
706 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
707 DEV_RX_OFFLOAD_KEEP_CRC |
708 DEV_RX_OFFLOAD_JUMBO_FRAME |
709 DEV_RX_OFFLOAD_IPV4_CKSUM |
710 DEV_RX_OFFLOAD_UDP_CKSUM |
711 DEV_RX_OFFLOAD_TCP_CKSUM |
712 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
713 DEV_RX_OFFLOAD_VLAN_FILTER))) {
714 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
715 eth_dev->data->port_id);
716 return bnxt_recv_pkts_vec;
718 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
719 eth_dev->data->port_id);
721 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
722 eth_dev->data->port_id,
723 eth_dev->data->scattered_rx,
724 eth_dev->data->dev_conf.rxmode.offloads);
726 return bnxt_recv_pkts;
729 static eth_tx_burst_t
730 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
734 * Vector mode receive can be enabled only if scatter tx is not
735 * in use and tx offloads other than VLAN insertion are not
738 if (!eth_dev->data->scattered_rx &&
739 !(eth_dev->data->dev_conf.txmode.offloads &
740 ~DEV_TX_OFFLOAD_VLAN_INSERT)) {
741 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
742 eth_dev->data->port_id);
743 return bnxt_xmit_pkts_vec;
745 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
746 eth_dev->data->port_id);
748 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
749 eth_dev->data->port_id,
750 eth_dev->data->scattered_rx,
751 eth_dev->data->dev_conf.txmode.offloads);
753 return bnxt_xmit_pkts;
756 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
758 struct bnxt *bp = eth_dev->data->dev_private;
759 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
763 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
765 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
766 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
769 rc = bnxt_init_chip(bp);
773 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
775 bnxt_link_update_op(eth_dev, 1);
777 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
778 vlan_mask |= ETH_VLAN_FILTER_MASK;
779 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
780 vlan_mask |= ETH_VLAN_STRIP_MASK;
781 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
785 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
786 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
788 bp->flags |= BNXT_FLAG_INIT_DONE;
793 bnxt_shutdown_nic(bp);
794 bnxt_free_tx_mbufs(bp);
795 bnxt_free_rx_mbufs(bp);
799 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
801 struct bnxt *bp = eth_dev->data->dev_private;
804 if (!bp->link_info.link_up)
805 rc = bnxt_set_hwrm_link_config(bp, true);
807 eth_dev->data->dev_link.link_status = 1;
809 bnxt_print_link_info(eth_dev);
813 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
815 struct bnxt *bp = eth_dev->data->dev_private;
817 eth_dev->data->dev_link.link_status = 0;
818 bnxt_set_hwrm_link_config(bp, false);
819 bp->link_info.link_up = 0;
824 /* Unload the driver, release resources */
825 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
827 struct bnxt *bp = eth_dev->data->dev_private;
828 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
829 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
831 bnxt_disable_int(bp);
833 /* disable uio/vfio intr/eventfd mapping */
834 rte_intr_disable(intr_handle);
836 bp->flags &= ~BNXT_FLAG_INIT_DONE;
837 if (bp->eth_dev->data->dev_started) {
838 /* TBD: STOP HW queues DMA */
839 eth_dev->data->dev_link.link_status = 0;
841 bnxt_set_hwrm_link_config(bp, false);
843 /* Clean queue intr-vector mapping */
844 rte_intr_efd_disable(intr_handle);
845 if (intr_handle->intr_vec != NULL) {
846 rte_free(intr_handle->intr_vec);
847 intr_handle->intr_vec = NULL;
850 bnxt_hwrm_port_clr_stats(bp);
851 bnxt_free_tx_mbufs(bp);
852 bnxt_free_rx_mbufs(bp);
853 bnxt_shutdown_nic(bp);
857 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
859 struct bnxt *bp = eth_dev->data->dev_private;
861 if (bp->dev_stopped == 0)
862 bnxt_dev_stop_op(eth_dev);
864 if (eth_dev->data->mac_addrs != NULL) {
865 rte_free(eth_dev->data->mac_addrs);
866 eth_dev->data->mac_addrs = NULL;
868 if (bp->grp_info != NULL) {
869 rte_free(bp->grp_info);
873 bnxt_dev_uninit(eth_dev);
876 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
879 struct bnxt *bp = eth_dev->data->dev_private;
880 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
881 struct bnxt_vnic_info *vnic;
882 struct bnxt_filter_info *filter, *temp_filter;
886 * Loop through all VNICs from the specified filter flow pools to
887 * remove the corresponding MAC addr filter
889 for (i = 0; i < bp->nr_vnics; i++) {
890 if (!(pool_mask & (1ULL << i)))
893 vnic = &bp->vnic_info[i];
894 filter = STAILQ_FIRST(&vnic->filter);
896 temp_filter = STAILQ_NEXT(filter, next);
897 if (filter->mac_index == index) {
898 STAILQ_REMOVE(&vnic->filter, filter,
899 bnxt_filter_info, next);
900 bnxt_hwrm_clear_l2_filter(bp, filter);
901 filter->mac_index = INVALID_MAC_INDEX;
902 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
903 STAILQ_INSERT_TAIL(&bp->free_filter_list,
906 filter = temp_filter;
911 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
912 struct rte_ether_addr *mac_addr,
913 uint32_t index, uint32_t pool)
915 struct bnxt *bp = eth_dev->data->dev_private;
916 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
917 struct bnxt_filter_info *filter;
920 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
921 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
926 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
929 /* Attach requested MAC address to the new l2_filter */
930 STAILQ_FOREACH(filter, &vnic->filter, next) {
931 if (filter->mac_index == index) {
933 "MAC addr already existed for pool %d\n", pool);
937 filter = bnxt_alloc_filter(bp);
939 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
943 filter->mac_index = index;
944 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
946 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
948 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
950 filter->mac_index = INVALID_MAC_INDEX;
951 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
952 bnxt_free_filter(bp, filter);
958 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
961 struct bnxt *bp = eth_dev->data->dev_private;
962 struct rte_eth_link new;
963 unsigned int cnt = BNXT_LINK_WAIT_CNT;
965 memset(&new, 0, sizeof(new));
967 /* Retrieve link info from hardware */
968 rc = bnxt_get_hwrm_link_config(bp, &new);
970 new.link_speed = ETH_LINK_SPEED_100M;
971 new.link_duplex = ETH_LINK_FULL_DUPLEX;
973 "Failed to retrieve link rc = 0x%x!\n", rc);
977 if (!wait_to_complete || new.link_status)
980 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
984 /* Timed out or success */
985 if (new.link_status != eth_dev->data->dev_link.link_status ||
986 new.link_speed != eth_dev->data->dev_link.link_speed) {
987 memcpy(ð_dev->data->dev_link, &new,
988 sizeof(struct rte_eth_link));
990 _rte_eth_dev_callback_process(eth_dev,
991 RTE_ETH_EVENT_INTR_LSC,
994 bnxt_print_link_info(eth_dev);
1000 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1002 struct bnxt *bp = eth_dev->data->dev_private;
1003 struct bnxt_vnic_info *vnic;
1005 if (bp->vnic_info == NULL)
1008 vnic = &bp->vnic_info[0];
1010 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1011 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1014 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1016 struct bnxt *bp = eth_dev->data->dev_private;
1017 struct bnxt_vnic_info *vnic;
1019 if (bp->vnic_info == NULL)
1022 vnic = &bp->vnic_info[0];
1024 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1025 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1028 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1030 struct bnxt *bp = eth_dev->data->dev_private;
1031 struct bnxt_vnic_info *vnic;
1033 if (bp->vnic_info == NULL)
1036 vnic = &bp->vnic_info[0];
1038 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1039 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1042 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1044 struct bnxt *bp = eth_dev->data->dev_private;
1045 struct bnxt_vnic_info *vnic;
1047 if (bp->vnic_info == NULL)
1050 vnic = &bp->vnic_info[0];
1052 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1053 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1056 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1057 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1059 if (qid >= bp->rx_nr_rings)
1062 return bp->eth_dev->data->rx_queues[qid];
1065 /* Return rxq corresponding to a given rss table ring/group ID. */
1066 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1068 struct bnxt_rx_queue *rxq;
1071 if (!BNXT_HAS_RING_GRPS(bp)) {
1072 for (i = 0; i < bp->rx_nr_rings; i++) {
1073 rxq = bp->eth_dev->data->rx_queues[i];
1074 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1078 for (i = 0; i < bp->rx_nr_rings; i++) {
1079 if (bp->grp_info[i].fw_grp_id == fwr)
1084 return INVALID_HW_RING_ID;
1087 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1088 struct rte_eth_rss_reta_entry64 *reta_conf,
1091 struct bnxt *bp = eth_dev->data->dev_private;
1092 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1093 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1094 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1098 if (!vnic->rss_table)
1101 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1104 if (reta_size != tbl_size) {
1105 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1106 "(%d) must equal the size supported by the hardware "
1107 "(%d)\n", reta_size, tbl_size);
1111 for (i = 0; i < reta_size; i++) {
1112 struct bnxt_rx_queue *rxq;
1114 idx = i / RTE_RETA_GROUP_SIZE;
1115 sft = i % RTE_RETA_GROUP_SIZE;
1117 if (!(reta_conf[idx].mask & (1ULL << sft)))
1120 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1122 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1126 if (BNXT_CHIP_THOR(bp)) {
1127 vnic->rss_table[i * 2] =
1128 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1129 vnic->rss_table[i * 2 + 1] =
1130 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1132 vnic->rss_table[i] =
1133 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1136 vnic->rss_table[i] =
1137 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1140 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1144 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1145 struct rte_eth_rss_reta_entry64 *reta_conf,
1148 struct bnxt *bp = eth_dev->data->dev_private;
1149 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1150 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1151 uint16_t idx, sft, i;
1153 /* Retrieve from the default VNIC */
1156 if (!vnic->rss_table)
1159 if (reta_size != tbl_size) {
1160 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1161 "(%d) must equal the size supported by the hardware "
1162 "(%d)\n", reta_size, tbl_size);
1166 for (idx = 0, i = 0; i < reta_size; i++) {
1167 idx = i / RTE_RETA_GROUP_SIZE;
1168 sft = i % RTE_RETA_GROUP_SIZE;
1170 if (reta_conf[idx].mask & (1ULL << sft)) {
1173 if (BNXT_CHIP_THOR(bp))
1174 qid = bnxt_rss_to_qid(bp,
1175 vnic->rss_table[i * 2]);
1177 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1179 if (qid == INVALID_HW_RING_ID) {
1180 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1183 reta_conf[idx].reta[sft] = qid;
1190 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1191 struct rte_eth_rss_conf *rss_conf)
1193 struct bnxt *bp = eth_dev->data->dev_private;
1194 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1195 struct bnxt_vnic_info *vnic;
1196 uint16_t hash_type = 0;
1200 * If RSS enablement were different than dev_configure,
1201 * then return -EINVAL
1203 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1204 if (!rss_conf->rss_hf)
1205 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1207 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1211 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1212 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1214 if (rss_conf->rss_hf & ETH_RSS_IPV4)
1215 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1216 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1217 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1218 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1219 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1220 if (rss_conf->rss_hf & ETH_RSS_IPV6)
1221 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1222 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1223 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1224 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1225 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1227 /* Update the RSS VNIC(s) */
1228 for (i = 0; i < bp->nr_vnics; i++) {
1229 vnic = &bp->vnic_info[i];
1230 vnic->hash_type = hash_type;
1233 * Use the supplied key if the key length is
1234 * acceptable and the rss_key is not NULL
1236 if (rss_conf->rss_key &&
1237 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1238 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1239 rss_conf->rss_key_len);
1241 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1246 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1247 struct rte_eth_rss_conf *rss_conf)
1249 struct bnxt *bp = eth_dev->data->dev_private;
1250 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1252 uint32_t hash_types;
1254 /* RSS configuration is the same for all VNICs */
1255 if (vnic && vnic->rss_hash_key) {
1256 if (rss_conf->rss_key) {
1257 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1258 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1259 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1262 hash_types = vnic->hash_type;
1263 rss_conf->rss_hf = 0;
1264 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1265 rss_conf->rss_hf |= ETH_RSS_IPV4;
1266 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1268 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1269 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1271 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1273 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1274 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1276 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1278 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1279 rss_conf->rss_hf |= ETH_RSS_IPV6;
1280 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1282 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1283 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1285 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1287 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1288 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1290 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1294 "Unknwon RSS config from firmware (%08x), RSS disabled",
1299 rss_conf->rss_hf = 0;
1304 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1305 struct rte_eth_fc_conf *fc_conf)
1307 struct bnxt *bp = dev->data->dev_private;
1308 struct rte_eth_link link_info;
1311 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1315 memset(fc_conf, 0, sizeof(*fc_conf));
1316 if (bp->link_info.auto_pause)
1317 fc_conf->autoneg = 1;
1318 switch (bp->link_info.pause) {
1320 fc_conf->mode = RTE_FC_NONE;
1322 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1323 fc_conf->mode = RTE_FC_TX_PAUSE;
1325 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1326 fc_conf->mode = RTE_FC_RX_PAUSE;
1328 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1329 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1330 fc_conf->mode = RTE_FC_FULL;
1336 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1337 struct rte_eth_fc_conf *fc_conf)
1339 struct bnxt *bp = dev->data->dev_private;
1341 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1342 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1346 switch (fc_conf->mode) {
1348 bp->link_info.auto_pause = 0;
1349 bp->link_info.force_pause = 0;
1351 case RTE_FC_RX_PAUSE:
1352 if (fc_conf->autoneg) {
1353 bp->link_info.auto_pause =
1354 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1355 bp->link_info.force_pause = 0;
1357 bp->link_info.auto_pause = 0;
1358 bp->link_info.force_pause =
1359 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1362 case RTE_FC_TX_PAUSE:
1363 if (fc_conf->autoneg) {
1364 bp->link_info.auto_pause =
1365 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1366 bp->link_info.force_pause = 0;
1368 bp->link_info.auto_pause = 0;
1369 bp->link_info.force_pause =
1370 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1374 if (fc_conf->autoneg) {
1375 bp->link_info.auto_pause =
1376 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1377 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1378 bp->link_info.force_pause = 0;
1380 bp->link_info.auto_pause = 0;
1381 bp->link_info.force_pause =
1382 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1383 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1387 return bnxt_set_hwrm_link_config(bp, true);
1390 /* Add UDP tunneling port */
1392 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1393 struct rte_eth_udp_tunnel *udp_tunnel)
1395 struct bnxt *bp = eth_dev->data->dev_private;
1396 uint16_t tunnel_type = 0;
1399 switch (udp_tunnel->prot_type) {
1400 case RTE_TUNNEL_TYPE_VXLAN:
1401 if (bp->vxlan_port_cnt) {
1402 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1403 udp_tunnel->udp_port);
1404 if (bp->vxlan_port != udp_tunnel->udp_port) {
1405 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1408 bp->vxlan_port_cnt++;
1412 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1413 bp->vxlan_port_cnt++;
1415 case RTE_TUNNEL_TYPE_GENEVE:
1416 if (bp->geneve_port_cnt) {
1417 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1418 udp_tunnel->udp_port);
1419 if (bp->geneve_port != udp_tunnel->udp_port) {
1420 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1423 bp->geneve_port_cnt++;
1427 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1428 bp->geneve_port_cnt++;
1431 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1434 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1440 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1441 struct rte_eth_udp_tunnel *udp_tunnel)
1443 struct bnxt *bp = eth_dev->data->dev_private;
1444 uint16_t tunnel_type = 0;
1448 switch (udp_tunnel->prot_type) {
1449 case RTE_TUNNEL_TYPE_VXLAN:
1450 if (!bp->vxlan_port_cnt) {
1451 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1454 if (bp->vxlan_port != udp_tunnel->udp_port) {
1455 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1456 udp_tunnel->udp_port, bp->vxlan_port);
1459 if (--bp->vxlan_port_cnt)
1463 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1464 port = bp->vxlan_fw_dst_port_id;
1466 case RTE_TUNNEL_TYPE_GENEVE:
1467 if (!bp->geneve_port_cnt) {
1468 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1471 if (bp->geneve_port != udp_tunnel->udp_port) {
1472 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1473 udp_tunnel->udp_port, bp->geneve_port);
1476 if (--bp->geneve_port_cnt)
1480 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1481 port = bp->geneve_fw_dst_port_id;
1484 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1488 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1491 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1494 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1495 bp->geneve_port = 0;
1500 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1502 struct bnxt_filter_info *filter;
1503 struct bnxt_vnic_info *vnic;
1505 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1507 /* if VLAN exists && VLAN matches vlan_id
1508 * remove the MAC+VLAN filter
1509 * add a new MAC only filter
1511 * VLAN filter doesn't exist, just skip and continue
1513 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1514 filter = STAILQ_FIRST(&vnic->filter);
1516 /* Search for this matching MAC+VLAN filter */
1517 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1518 !memcmp(filter->l2_addr,
1520 RTE_ETHER_ADDR_LEN)) {
1521 /* Delete the filter */
1522 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1525 STAILQ_REMOVE(&vnic->filter, filter,
1526 bnxt_filter_info, next);
1527 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1530 "Del Vlan filter for %d\n",
1534 filter = STAILQ_NEXT(filter, next);
1539 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1541 struct bnxt_filter_info *filter;
1542 struct bnxt_vnic_info *vnic;
1544 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1545 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1546 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1548 /* Implementation notes on the use of VNIC in this command:
1550 * By default, these filters belong to default vnic for the function.
1551 * Once these filters are set up, only destination VNIC can be modified.
1552 * If the destination VNIC is not specified in this command,
1553 * then the HWRM shall only create an l2 context id.
1556 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1557 filter = STAILQ_FIRST(&vnic->filter);
1558 /* Check if the VLAN has already been added */
1560 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1561 !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN))
1564 filter = STAILQ_NEXT(filter, next);
1567 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1568 * command to create MAC+VLAN filter with the right flags, enables set.
1570 filter = bnxt_alloc_filter(bp);
1573 "MAC/VLAN filter alloc failed\n");
1576 /* MAC + VLAN ID filter */
1577 filter->l2_ivlan = vlan_id;
1578 filter->l2_ivlan_mask = 0x0FFF;
1579 filter->enables |= en;
1580 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1582 /* Free the newly allocated filter as we were
1583 * not able to create the filter in hardware.
1585 filter->fw_l2_filter_id = UINT64_MAX;
1586 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1590 /* Add this new filter to the list */
1591 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1593 "Added Vlan filter for %d\n", vlan_id);
1597 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1598 uint16_t vlan_id, int on)
1600 struct bnxt *bp = eth_dev->data->dev_private;
1602 /* These operations apply to ALL existing MAC/VLAN filters */
1604 return bnxt_add_vlan_filter(bp, vlan_id);
1606 return bnxt_del_vlan_filter(bp, vlan_id);
1610 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1612 struct bnxt *bp = dev->data->dev_private;
1613 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1616 if (mask & ETH_VLAN_FILTER_MASK) {
1617 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1618 /* Remove any VLAN filters programmed */
1619 for (i = 0; i < 4095; i++)
1620 bnxt_del_vlan_filter(bp, i);
1622 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1623 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1626 if (mask & ETH_VLAN_STRIP_MASK) {
1627 /* Enable or disable VLAN stripping */
1628 for (i = 0; i < bp->nr_vnics; i++) {
1629 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1630 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1631 vnic->vlan_strip = true;
1633 vnic->vlan_strip = false;
1634 bnxt_hwrm_vnic_cfg(bp, vnic);
1636 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1637 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1640 if (mask & ETH_VLAN_EXTEND_MASK)
1641 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1647 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1648 struct rte_ether_addr *addr)
1650 struct bnxt *bp = dev->data->dev_private;
1651 /* Default Filter is tied to VNIC 0 */
1652 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1653 struct bnxt_filter_info *filter;
1656 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1659 if (rte_is_zero_ether_addr(addr))
1662 STAILQ_FOREACH(filter, &vnic->filter, next) {
1663 /* Default Filter is at Index 0 */
1664 if (filter->mac_index != 0)
1667 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1668 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1669 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1671 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1672 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1674 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1678 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1679 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1687 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1688 struct rte_ether_addr *mc_addr_set,
1689 uint32_t nb_mc_addr)
1691 struct bnxt *bp = eth_dev->data->dev_private;
1692 char *mc_addr_list = (char *)mc_addr_set;
1693 struct bnxt_vnic_info *vnic;
1694 uint32_t off = 0, i = 0;
1696 vnic = &bp->vnic_info[0];
1698 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1699 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1703 /* TODO Check for Duplicate mcast addresses */
1704 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1705 for (i = 0; i < nb_mc_addr; i++) {
1706 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1707 RTE_ETHER_ADDR_LEN);
1708 off += RTE_ETHER_ADDR_LEN;
1711 vnic->mc_addr_cnt = i;
1714 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1718 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1720 struct bnxt *bp = dev->data->dev_private;
1721 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1722 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1723 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1726 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1727 fw_major, fw_minor, fw_updt);
1729 ret += 1; /* add the size of '\0' */
1730 if (fw_size < (uint32_t)ret)
1737 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1738 struct rte_eth_rxq_info *qinfo)
1740 struct bnxt_rx_queue *rxq;
1742 rxq = dev->data->rx_queues[queue_id];
1744 qinfo->mp = rxq->mb_pool;
1745 qinfo->scattered_rx = dev->data->scattered_rx;
1746 qinfo->nb_desc = rxq->nb_rx_desc;
1748 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1749 qinfo->conf.rx_drop_en = 0;
1750 qinfo->conf.rx_deferred_start = 0;
1754 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1755 struct rte_eth_txq_info *qinfo)
1757 struct bnxt_tx_queue *txq;
1759 txq = dev->data->tx_queues[queue_id];
1761 qinfo->nb_desc = txq->nb_tx_desc;
1763 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1764 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1765 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1767 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1768 qinfo->conf.tx_rs_thresh = 0;
1769 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1772 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1774 struct bnxt *bp = eth_dev->data->dev_private;
1775 struct rte_eth_dev_info dev_info;
1776 uint32_t new_pkt_size;
1780 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1781 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1783 bnxt_dev_info_get_op(eth_dev, &dev_info);
1785 if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1786 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1787 RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1793 * If vector-mode tx/rx is active, disallow any MTU change that would
1794 * require scattered receive support.
1796 if (eth_dev->data->dev_started &&
1797 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1798 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1800 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1802 "MTU change would require scattered rx support. ");
1803 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
1808 if (new_mtu > RTE_ETHER_MTU) {
1809 bp->flags |= BNXT_FLAG_JUMBO;
1810 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1811 DEV_RX_OFFLOAD_JUMBO_FRAME;
1813 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1814 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1815 bp->flags &= ~BNXT_FLAG_JUMBO;
1818 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
1820 eth_dev->data->mtu = new_mtu;
1821 PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1823 for (i = 0; i < bp->nr_vnics; i++) {
1824 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1827 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1828 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1829 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1833 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1834 size -= RTE_PKTMBUF_HEADROOM;
1836 if (size < new_mtu) {
1837 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1847 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1849 struct bnxt *bp = dev->data->dev_private;
1850 uint16_t vlan = bp->vlan;
1853 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1855 "PVID cannot be modified for this function\n");
1858 bp->vlan = on ? pvid : 0;
1860 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1867 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1869 struct bnxt *bp = dev->data->dev_private;
1871 return bnxt_hwrm_port_led_cfg(bp, true);
1875 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1877 struct bnxt *bp = dev->data->dev_private;
1879 return bnxt_hwrm_port_led_cfg(bp, false);
1883 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1885 uint32_t desc = 0, raw_cons = 0, cons;
1886 struct bnxt_cp_ring_info *cpr;
1887 struct bnxt_rx_queue *rxq;
1888 struct rx_pkt_cmpl *rxcmp;
1893 rxq = dev->data->rx_queues[rx_queue_id];
1897 while (raw_cons < rxq->nb_rx_desc) {
1898 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1899 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1901 if (!CMPL_VALID(rxcmp, valid))
1903 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1904 cmp_type = CMP_TYPE(rxcmp);
1905 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1906 cmp = (rte_le_to_cpu_32(
1907 ((struct rx_tpa_end_cmpl *)
1908 (rxcmp))->agg_bufs_v1) &
1909 RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1910 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1912 } else if (cmp_type == 0x11) {
1914 cmp = (rxcmp->agg_bufs_v1 &
1915 RX_PKT_CMPL_AGG_BUFS_MASK) >>
1916 RX_PKT_CMPL_AGG_BUFS_SFT;
1921 raw_cons += cmp ? cmp : 2;
1928 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1930 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1931 struct bnxt_rx_ring_info *rxr;
1932 struct bnxt_cp_ring_info *cpr;
1933 struct bnxt_sw_rx_bd *rx_buf;
1934 struct rx_pkt_cmpl *rxcmp;
1935 uint32_t cons, cp_cons;
1943 if (offset >= rxq->nb_rx_desc)
1946 cons = RING_CMP(cpr->cp_ring_struct, offset);
1947 cp_cons = cpr->cp_raw_cons;
1948 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1950 if (cons > cp_cons) {
1951 if (CMPL_VALID(rxcmp, cpr->valid))
1952 return RTE_ETH_RX_DESC_DONE;
1954 if (CMPL_VALID(rxcmp, !cpr->valid))
1955 return RTE_ETH_RX_DESC_DONE;
1957 rx_buf = &rxr->rx_buf_ring[cons];
1958 if (rx_buf->mbuf == NULL)
1959 return RTE_ETH_RX_DESC_UNAVAIL;
1962 return RTE_ETH_RX_DESC_AVAIL;
1966 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1968 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1969 struct bnxt_tx_ring_info *txr;
1970 struct bnxt_cp_ring_info *cpr;
1971 struct bnxt_sw_tx_bd *tx_buf;
1972 struct tx_pkt_cmpl *txcmp;
1973 uint32_t cons, cp_cons;
1981 if (offset >= txq->nb_tx_desc)
1984 cons = RING_CMP(cpr->cp_ring_struct, offset);
1985 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1986 cp_cons = cpr->cp_raw_cons;
1988 if (cons > cp_cons) {
1989 if (CMPL_VALID(txcmp, cpr->valid))
1990 return RTE_ETH_TX_DESC_UNAVAIL;
1992 if (CMPL_VALID(txcmp, !cpr->valid))
1993 return RTE_ETH_TX_DESC_UNAVAIL;
1995 tx_buf = &txr->tx_buf_ring[cons];
1996 if (tx_buf->mbuf == NULL)
1997 return RTE_ETH_TX_DESC_DONE;
1999 return RTE_ETH_TX_DESC_FULL;
2002 static struct bnxt_filter_info *
2003 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2004 struct rte_eth_ethertype_filter *efilter,
2005 struct bnxt_vnic_info *vnic0,
2006 struct bnxt_vnic_info *vnic,
2009 struct bnxt_filter_info *mfilter = NULL;
2013 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2014 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2015 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2016 " ethertype filter.", efilter->ether_type);
2020 if (efilter->queue >= bp->rx_nr_rings) {
2021 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2026 vnic0 = &bp->vnic_info[0];
2027 vnic = &bp->vnic_info[efilter->queue];
2029 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2034 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2035 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2036 if ((!memcmp(efilter->mac_addr.addr_bytes,
2037 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2039 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2040 mfilter->ethertype == efilter->ether_type)) {
2046 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2047 if ((!memcmp(efilter->mac_addr.addr_bytes,
2048 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2049 mfilter->ethertype == efilter->ether_type &&
2051 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2065 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2066 enum rte_filter_op filter_op,
2069 struct bnxt *bp = dev->data->dev_private;
2070 struct rte_eth_ethertype_filter *efilter =
2071 (struct rte_eth_ethertype_filter *)arg;
2072 struct bnxt_filter_info *bfilter, *filter1;
2073 struct bnxt_vnic_info *vnic, *vnic0;
2076 if (filter_op == RTE_ETH_FILTER_NOP)
2080 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2085 vnic0 = &bp->vnic_info[0];
2086 vnic = &bp->vnic_info[efilter->queue];
2088 switch (filter_op) {
2089 case RTE_ETH_FILTER_ADD:
2090 bnxt_match_and_validate_ether_filter(bp, efilter,
2095 bfilter = bnxt_get_unused_filter(bp);
2096 if (bfilter == NULL) {
2098 "Not enough resources for a new filter.\n");
2101 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2102 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2103 RTE_ETHER_ADDR_LEN);
2104 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2105 RTE_ETHER_ADDR_LEN);
2106 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2107 bfilter->ethertype = efilter->ether_type;
2108 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2110 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2111 if (filter1 == NULL) {
2116 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2117 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2119 bfilter->dst_id = vnic->fw_vnic_id;
2121 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2123 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2126 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2129 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2131 case RTE_ETH_FILTER_DELETE:
2132 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2134 if (ret == -EEXIST) {
2135 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2137 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2139 bnxt_free_filter(bp, filter1);
2140 } else if (ret == 0) {
2141 PMD_DRV_LOG(ERR, "No matching filter found\n");
2145 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2151 bnxt_free_filter(bp, bfilter);
2157 parse_ntuple_filter(struct bnxt *bp,
2158 struct rte_eth_ntuple_filter *nfilter,
2159 struct bnxt_filter_info *bfilter)
2163 if (nfilter->queue >= bp->rx_nr_rings) {
2164 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2168 switch (nfilter->dst_port_mask) {
2170 bfilter->dst_port_mask = -1;
2171 bfilter->dst_port = nfilter->dst_port;
2172 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2173 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2176 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2180 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2181 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2183 switch (nfilter->proto_mask) {
2185 if (nfilter->proto == 17) /* IPPROTO_UDP */
2186 bfilter->ip_protocol = 17;
2187 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2188 bfilter->ip_protocol = 6;
2191 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2194 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2198 switch (nfilter->dst_ip_mask) {
2200 bfilter->dst_ipaddr_mask[0] = -1;
2201 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2202 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2203 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2206 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2210 switch (nfilter->src_ip_mask) {
2212 bfilter->src_ipaddr_mask[0] = -1;
2213 bfilter->src_ipaddr[0] = nfilter->src_ip;
2214 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2215 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2218 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2222 switch (nfilter->src_port_mask) {
2224 bfilter->src_port_mask = -1;
2225 bfilter->src_port = nfilter->src_port;
2226 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2227 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2230 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2235 //nfilter->priority = (uint8_t)filter->priority;
2237 bfilter->enables = en;
2241 static struct bnxt_filter_info*
2242 bnxt_match_ntuple_filter(struct bnxt *bp,
2243 struct bnxt_filter_info *bfilter,
2244 struct bnxt_vnic_info **mvnic)
2246 struct bnxt_filter_info *mfilter = NULL;
2249 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2250 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2251 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2252 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2253 bfilter->src_ipaddr_mask[0] ==
2254 mfilter->src_ipaddr_mask[0] &&
2255 bfilter->src_port == mfilter->src_port &&
2256 bfilter->src_port_mask == mfilter->src_port_mask &&
2257 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2258 bfilter->dst_ipaddr_mask[0] ==
2259 mfilter->dst_ipaddr_mask[0] &&
2260 bfilter->dst_port == mfilter->dst_port &&
2261 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2262 bfilter->flags == mfilter->flags &&
2263 bfilter->enables == mfilter->enables) {
2274 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2275 struct rte_eth_ntuple_filter *nfilter,
2276 enum rte_filter_op filter_op)
2278 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2279 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2282 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2283 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2287 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2288 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2292 bfilter = bnxt_get_unused_filter(bp);
2293 if (bfilter == NULL) {
2295 "Not enough resources for a new filter.\n");
2298 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2302 vnic = &bp->vnic_info[nfilter->queue];
2303 vnic0 = &bp->vnic_info[0];
2304 filter1 = STAILQ_FIRST(&vnic0->filter);
2305 if (filter1 == NULL) {
2310 bfilter->dst_id = vnic->fw_vnic_id;
2311 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2313 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2314 bfilter->ethertype = 0x800;
2315 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2317 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2319 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2320 bfilter->dst_id == mfilter->dst_id) {
2321 PMD_DRV_LOG(ERR, "filter exists.\n");
2324 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2325 bfilter->dst_id != mfilter->dst_id) {
2326 mfilter->dst_id = vnic->fw_vnic_id;
2327 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2328 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2329 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2330 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2331 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2334 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2335 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2340 if (filter_op == RTE_ETH_FILTER_ADD) {
2341 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2342 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2345 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2347 if (mfilter == NULL) {
2348 /* This should not happen. But for Coverity! */
2352 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2354 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2355 bnxt_free_filter(bp, mfilter);
2356 mfilter->fw_l2_filter_id = -1;
2357 bnxt_free_filter(bp, bfilter);
2358 bfilter->fw_l2_filter_id = -1;
2363 bfilter->fw_l2_filter_id = -1;
2364 bnxt_free_filter(bp, bfilter);
2369 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2370 enum rte_filter_op filter_op,
2373 struct bnxt *bp = dev->data->dev_private;
2376 if (filter_op == RTE_ETH_FILTER_NOP)
2380 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2385 switch (filter_op) {
2386 case RTE_ETH_FILTER_ADD:
2387 ret = bnxt_cfg_ntuple_filter(bp,
2388 (struct rte_eth_ntuple_filter *)arg,
2391 case RTE_ETH_FILTER_DELETE:
2392 ret = bnxt_cfg_ntuple_filter(bp,
2393 (struct rte_eth_ntuple_filter *)arg,
2397 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2405 bnxt_parse_fdir_filter(struct bnxt *bp,
2406 struct rte_eth_fdir_filter *fdir,
2407 struct bnxt_filter_info *filter)
2409 enum rte_fdir_mode fdir_mode =
2410 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2411 struct bnxt_vnic_info *vnic0, *vnic;
2412 struct bnxt_filter_info *filter1;
2416 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2419 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2420 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2422 switch (fdir->input.flow_type) {
2423 case RTE_ETH_FLOW_IPV4:
2424 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2426 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2427 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2428 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2429 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2430 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2431 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2432 filter->ip_addr_type =
2433 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2434 filter->src_ipaddr_mask[0] = 0xffffffff;
2435 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2436 filter->dst_ipaddr_mask[0] = 0xffffffff;
2437 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2438 filter->ethertype = 0x800;
2439 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2441 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2442 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2443 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2444 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2445 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2446 filter->dst_port_mask = 0xffff;
2447 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2448 filter->src_port_mask = 0xffff;
2449 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2450 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2451 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2452 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2453 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2454 filter->ip_protocol = 6;
2455 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2456 filter->ip_addr_type =
2457 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2458 filter->src_ipaddr_mask[0] = 0xffffffff;
2459 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2460 filter->dst_ipaddr_mask[0] = 0xffffffff;
2461 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2462 filter->ethertype = 0x800;
2463 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2465 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2466 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2467 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2468 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2469 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2470 filter->dst_port_mask = 0xffff;
2471 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2472 filter->src_port_mask = 0xffff;
2473 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2474 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2475 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2476 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2477 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2478 filter->ip_protocol = 17;
2479 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2480 filter->ip_addr_type =
2481 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2482 filter->src_ipaddr_mask[0] = 0xffffffff;
2483 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2484 filter->dst_ipaddr_mask[0] = 0xffffffff;
2485 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2486 filter->ethertype = 0x800;
2487 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2489 case RTE_ETH_FLOW_IPV6:
2490 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2492 filter->ip_addr_type =
2493 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2494 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2495 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2496 rte_memcpy(filter->src_ipaddr,
2497 fdir->input.flow.ipv6_flow.src_ip, 16);
2498 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2499 rte_memcpy(filter->dst_ipaddr,
2500 fdir->input.flow.ipv6_flow.dst_ip, 16);
2501 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2502 memset(filter->dst_ipaddr_mask, 0xff, 16);
2503 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2504 memset(filter->src_ipaddr_mask, 0xff, 16);
2505 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2506 filter->ethertype = 0x86dd;
2507 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2509 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2510 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2511 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2512 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2513 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2514 filter->dst_port_mask = 0xffff;
2515 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2516 filter->src_port_mask = 0xffff;
2517 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2518 filter->ip_addr_type =
2519 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2520 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2521 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2522 rte_memcpy(filter->src_ipaddr,
2523 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2524 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2525 rte_memcpy(filter->dst_ipaddr,
2526 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2527 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2528 memset(filter->dst_ipaddr_mask, 0xff, 16);
2529 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2530 memset(filter->src_ipaddr_mask, 0xff, 16);
2531 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2532 filter->ethertype = 0x86dd;
2533 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2535 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2536 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2537 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2538 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2539 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2540 filter->dst_port_mask = 0xffff;
2541 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2542 filter->src_port_mask = 0xffff;
2543 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2544 filter->ip_addr_type =
2545 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2546 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2547 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2548 rte_memcpy(filter->src_ipaddr,
2549 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2550 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2551 rte_memcpy(filter->dst_ipaddr,
2552 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2553 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2554 memset(filter->dst_ipaddr_mask, 0xff, 16);
2555 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2556 memset(filter->src_ipaddr_mask, 0xff, 16);
2557 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2558 filter->ethertype = 0x86dd;
2559 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2561 case RTE_ETH_FLOW_L2_PAYLOAD:
2562 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2563 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2565 case RTE_ETH_FLOW_VXLAN:
2566 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2568 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2569 filter->tunnel_type =
2570 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2571 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2573 case RTE_ETH_FLOW_NVGRE:
2574 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2576 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2577 filter->tunnel_type =
2578 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2579 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2581 case RTE_ETH_FLOW_UNKNOWN:
2582 case RTE_ETH_FLOW_RAW:
2583 case RTE_ETH_FLOW_FRAG_IPV4:
2584 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2585 case RTE_ETH_FLOW_FRAG_IPV6:
2586 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2587 case RTE_ETH_FLOW_IPV6_EX:
2588 case RTE_ETH_FLOW_IPV6_TCP_EX:
2589 case RTE_ETH_FLOW_IPV6_UDP_EX:
2590 case RTE_ETH_FLOW_GENEVE:
2596 vnic0 = &bp->vnic_info[0];
2597 vnic = &bp->vnic_info[fdir->action.rx_queue];
2599 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2604 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2605 rte_memcpy(filter->dst_macaddr,
2606 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2607 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2610 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2611 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2612 filter1 = STAILQ_FIRST(&vnic0->filter);
2613 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2615 filter->dst_id = vnic->fw_vnic_id;
2616 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2617 if (filter->dst_macaddr[i] == 0x00)
2618 filter1 = STAILQ_FIRST(&vnic0->filter);
2620 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2623 if (filter1 == NULL)
2626 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2627 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2629 filter->enables = en;
2634 static struct bnxt_filter_info *
2635 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2636 struct bnxt_vnic_info **mvnic)
2638 struct bnxt_filter_info *mf = NULL;
2641 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2642 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2644 STAILQ_FOREACH(mf, &vnic->filter, next) {
2645 if (mf->filter_type == nf->filter_type &&
2646 mf->flags == nf->flags &&
2647 mf->src_port == nf->src_port &&
2648 mf->src_port_mask == nf->src_port_mask &&
2649 mf->dst_port == nf->dst_port &&
2650 mf->dst_port_mask == nf->dst_port_mask &&
2651 mf->ip_protocol == nf->ip_protocol &&
2652 mf->ip_addr_type == nf->ip_addr_type &&
2653 mf->ethertype == nf->ethertype &&
2654 mf->vni == nf->vni &&
2655 mf->tunnel_type == nf->tunnel_type &&
2656 mf->l2_ovlan == nf->l2_ovlan &&
2657 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2658 mf->l2_ivlan == nf->l2_ivlan &&
2659 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2660 !memcmp(mf->l2_addr, nf->l2_addr,
2661 RTE_ETHER_ADDR_LEN) &&
2662 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2663 RTE_ETHER_ADDR_LEN) &&
2664 !memcmp(mf->src_macaddr, nf->src_macaddr,
2665 RTE_ETHER_ADDR_LEN) &&
2666 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2667 RTE_ETHER_ADDR_LEN) &&
2668 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2669 sizeof(nf->src_ipaddr)) &&
2670 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2671 sizeof(nf->src_ipaddr_mask)) &&
2672 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2673 sizeof(nf->dst_ipaddr)) &&
2674 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2675 sizeof(nf->dst_ipaddr_mask))) {
2686 bnxt_fdir_filter(struct rte_eth_dev *dev,
2687 enum rte_filter_op filter_op,
2690 struct bnxt *bp = dev->data->dev_private;
2691 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2692 struct bnxt_filter_info *filter, *match;
2693 struct bnxt_vnic_info *vnic, *mvnic;
2696 if (filter_op == RTE_ETH_FILTER_NOP)
2699 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2702 switch (filter_op) {
2703 case RTE_ETH_FILTER_ADD:
2704 case RTE_ETH_FILTER_DELETE:
2706 filter = bnxt_get_unused_filter(bp);
2707 if (filter == NULL) {
2709 "Not enough resources for a new flow.\n");
2713 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2716 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2718 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2719 vnic = &bp->vnic_info[0];
2721 vnic = &bp->vnic_info[fdir->action.rx_queue];
2723 match = bnxt_match_fdir(bp, filter, &mvnic);
2724 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2725 if (match->dst_id == vnic->fw_vnic_id) {
2726 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2730 match->dst_id = vnic->fw_vnic_id;
2731 ret = bnxt_hwrm_set_ntuple_filter(bp,
2734 STAILQ_REMOVE(&mvnic->filter, match,
2735 bnxt_filter_info, next);
2736 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2738 "Filter with matching pattern exist\n");
2740 "Updated it to new destination q\n");
2744 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2745 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2750 if (filter_op == RTE_ETH_FILTER_ADD) {
2751 ret = bnxt_hwrm_set_ntuple_filter(bp,
2756 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2758 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2759 STAILQ_REMOVE(&vnic->filter, match,
2760 bnxt_filter_info, next);
2761 bnxt_free_filter(bp, match);
2762 filter->fw_l2_filter_id = -1;
2763 bnxt_free_filter(bp, filter);
2766 case RTE_ETH_FILTER_FLUSH:
2767 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2768 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2770 STAILQ_FOREACH(filter, &vnic->filter, next) {
2771 if (filter->filter_type ==
2772 HWRM_CFA_NTUPLE_FILTER) {
2774 bnxt_hwrm_clear_ntuple_filter(bp,
2776 STAILQ_REMOVE(&vnic->filter, filter,
2777 bnxt_filter_info, next);
2782 case RTE_ETH_FILTER_UPDATE:
2783 case RTE_ETH_FILTER_STATS:
2784 case RTE_ETH_FILTER_INFO:
2785 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2788 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2795 filter->fw_l2_filter_id = -1;
2796 bnxt_free_filter(bp, filter);
2801 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2802 enum rte_filter_type filter_type,
2803 enum rte_filter_op filter_op, void *arg)
2807 switch (filter_type) {
2808 case RTE_ETH_FILTER_TUNNEL:
2810 "filter type: %d: To be implemented\n", filter_type);
2812 case RTE_ETH_FILTER_FDIR:
2813 ret = bnxt_fdir_filter(dev, filter_op, arg);
2815 case RTE_ETH_FILTER_NTUPLE:
2816 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2818 case RTE_ETH_FILTER_ETHERTYPE:
2819 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2821 case RTE_ETH_FILTER_GENERIC:
2822 if (filter_op != RTE_ETH_FILTER_GET)
2824 *(const void **)arg = &bnxt_flow_ops;
2828 "Filter type (%d) not supported", filter_type);
2835 static const uint32_t *
2836 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2838 static const uint32_t ptypes[] = {
2839 RTE_PTYPE_L2_ETHER_VLAN,
2840 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2841 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2845 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2846 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2847 RTE_PTYPE_INNER_L4_ICMP,
2848 RTE_PTYPE_INNER_L4_TCP,
2849 RTE_PTYPE_INNER_L4_UDP,
2853 if (!dev->rx_pkt_burst)
2859 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2862 uint32_t reg_base = *reg_arr & 0xfffff000;
2866 for (i = 0; i < count; i++) {
2867 if ((reg_arr[i] & 0xfffff000) != reg_base)
2870 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2871 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
2875 static int bnxt_map_ptp_regs(struct bnxt *bp)
2877 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2881 reg_arr = ptp->rx_regs;
2882 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2886 reg_arr = ptp->tx_regs;
2887 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2891 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2892 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2894 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2895 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2900 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2902 rte_write32(0, (uint8_t *)bp->bar0 +
2903 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
2904 rte_write32(0, (uint8_t *)bp->bar0 +
2905 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
2908 static uint64_t bnxt_cc_read(struct bnxt *bp)
2912 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2913 BNXT_GRCPF_REG_SYNC_TIME));
2914 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2915 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2919 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2921 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2924 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2925 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2926 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2929 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2930 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2931 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2932 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2933 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2934 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2939 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2941 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2942 struct bnxt_pf_info *pf = &bp->pf;
2949 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2950 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2951 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2954 port_id = pf->port_id;
2955 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2956 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
2958 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2959 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2960 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2961 /* bnxt_clr_rx_ts(bp); TBD */
2965 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2966 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2967 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2968 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2974 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2977 struct bnxt *bp = dev->data->dev_private;
2978 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2983 ns = rte_timespec_to_ns(ts);
2984 /* Set the timecounters to a new value. */
2991 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2993 uint64_t ns, systime_cycles;
2994 struct bnxt *bp = dev->data->dev_private;
2995 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3000 systime_cycles = bnxt_cc_read(bp);
3001 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3002 *ts = rte_ns_to_timespec(ns);
3007 bnxt_timesync_enable(struct rte_eth_dev *dev)
3009 struct bnxt *bp = dev->data->dev_private;
3010 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3017 ptp->tx_tstamp_en = 1;
3018 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3020 if (!bnxt_hwrm_ptp_cfg(bp))
3021 bnxt_map_ptp_regs(bp);
3023 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3024 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3025 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3027 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3028 ptp->tc.cc_shift = shift;
3029 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3031 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3032 ptp->rx_tstamp_tc.cc_shift = shift;
3033 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3035 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3036 ptp->tx_tstamp_tc.cc_shift = shift;
3037 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3043 bnxt_timesync_disable(struct rte_eth_dev *dev)
3045 struct bnxt *bp = dev->data->dev_private;
3046 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3052 ptp->tx_tstamp_en = 0;
3055 bnxt_hwrm_ptp_cfg(bp);
3057 bnxt_unmap_ptp_regs(bp);
3063 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3064 struct timespec *timestamp,
3065 uint32_t flags __rte_unused)
3067 struct bnxt *bp = dev->data->dev_private;
3068 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3069 uint64_t rx_tstamp_cycles = 0;
3075 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3076 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3077 *timestamp = rte_ns_to_timespec(ns);
3082 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3083 struct timespec *timestamp)
3085 struct bnxt *bp = dev->data->dev_private;
3086 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3087 uint64_t tx_tstamp_cycles = 0;
3093 bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3094 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3095 *timestamp = rte_ns_to_timespec(ns);
3101 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3103 struct bnxt *bp = dev->data->dev_private;
3104 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3109 ptp->tc.nsec += delta;
3115 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3117 struct bnxt *bp = dev->data->dev_private;
3119 uint32_t dir_entries;
3120 uint32_t entry_length;
3122 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3123 bp->pdev->addr.domain, bp->pdev->addr.bus,
3124 bp->pdev->addr.devid, bp->pdev->addr.function);
3126 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3130 return dir_entries * entry_length;
3134 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3135 struct rte_dev_eeprom_info *in_eeprom)
3137 struct bnxt *bp = dev->data->dev_private;
3141 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3142 "len = %d\n", bp->pdev->addr.domain,
3143 bp->pdev->addr.bus, bp->pdev->addr.devid,
3144 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3146 if (in_eeprom->offset == 0) /* special offset value to get directory */
3147 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3150 index = in_eeprom->offset >> 24;
3151 offset = in_eeprom->offset & 0xffffff;
3154 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3155 in_eeprom->length, in_eeprom->data);
3160 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3163 case BNX_DIR_TYPE_CHIMP_PATCH:
3164 case BNX_DIR_TYPE_BOOTCODE:
3165 case BNX_DIR_TYPE_BOOTCODE_2:
3166 case BNX_DIR_TYPE_APE_FW:
3167 case BNX_DIR_TYPE_APE_PATCH:
3168 case BNX_DIR_TYPE_KONG_FW:
3169 case BNX_DIR_TYPE_KONG_PATCH:
3170 case BNX_DIR_TYPE_BONO_FW:
3171 case BNX_DIR_TYPE_BONO_PATCH:
3179 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3182 case BNX_DIR_TYPE_AVS:
3183 case BNX_DIR_TYPE_EXP_ROM_MBA:
3184 case BNX_DIR_TYPE_PCIE:
3185 case BNX_DIR_TYPE_TSCF_UCODE:
3186 case BNX_DIR_TYPE_EXT_PHY:
3187 case BNX_DIR_TYPE_CCM:
3188 case BNX_DIR_TYPE_ISCSI_BOOT:
3189 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3190 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3198 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3200 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3201 bnxt_dir_type_is_other_exec_format(dir_type);
3205 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3206 struct rte_dev_eeprom_info *in_eeprom)
3208 struct bnxt *bp = dev->data->dev_private;
3209 uint8_t index, dir_op;
3210 uint16_t type, ext, ordinal, attr;
3212 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3213 "len = %d\n", bp->pdev->addr.domain,
3214 bp->pdev->addr.bus, bp->pdev->addr.devid,
3215 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3218 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3222 type = in_eeprom->magic >> 16;
3224 if (type == 0xffff) { /* special value for directory operations */
3225 index = in_eeprom->magic & 0xff;
3226 dir_op = in_eeprom->magic >> 8;
3230 case 0x0e: /* erase */
3231 if (in_eeprom->offset != ~in_eeprom->magic)
3233 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3239 /* Create or re-write an NVM item: */
3240 if (bnxt_dir_type_is_executable(type) == true)
3242 ext = in_eeprom->magic & 0xffff;
3243 ordinal = in_eeprom->offset >> 16;
3244 attr = in_eeprom->offset & 0xffff;
3246 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3247 in_eeprom->data, in_eeprom->length);
3254 static const struct eth_dev_ops bnxt_dev_ops = {
3255 .dev_infos_get = bnxt_dev_info_get_op,
3256 .dev_close = bnxt_dev_close_op,
3257 .dev_configure = bnxt_dev_configure_op,
3258 .dev_start = bnxt_dev_start_op,
3259 .dev_stop = bnxt_dev_stop_op,
3260 .dev_set_link_up = bnxt_dev_set_link_up_op,
3261 .dev_set_link_down = bnxt_dev_set_link_down_op,
3262 .stats_get = bnxt_stats_get_op,
3263 .stats_reset = bnxt_stats_reset_op,
3264 .rx_queue_setup = bnxt_rx_queue_setup_op,
3265 .rx_queue_release = bnxt_rx_queue_release_op,
3266 .tx_queue_setup = bnxt_tx_queue_setup_op,
3267 .tx_queue_release = bnxt_tx_queue_release_op,
3268 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3269 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3270 .reta_update = bnxt_reta_update_op,
3271 .reta_query = bnxt_reta_query_op,
3272 .rss_hash_update = bnxt_rss_hash_update_op,
3273 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3274 .link_update = bnxt_link_update_op,
3275 .promiscuous_enable = bnxt_promiscuous_enable_op,
3276 .promiscuous_disable = bnxt_promiscuous_disable_op,
3277 .allmulticast_enable = bnxt_allmulticast_enable_op,
3278 .allmulticast_disable = bnxt_allmulticast_disable_op,
3279 .mac_addr_add = bnxt_mac_addr_add_op,
3280 .mac_addr_remove = bnxt_mac_addr_remove_op,
3281 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3282 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3283 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3284 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3285 .vlan_filter_set = bnxt_vlan_filter_set_op,
3286 .vlan_offload_set = bnxt_vlan_offload_set_op,
3287 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3288 .mtu_set = bnxt_mtu_set_op,
3289 .mac_addr_set = bnxt_set_default_mac_addr_op,
3290 .xstats_get = bnxt_dev_xstats_get_op,
3291 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3292 .xstats_reset = bnxt_dev_xstats_reset_op,
3293 .fw_version_get = bnxt_fw_version_get,
3294 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3295 .rxq_info_get = bnxt_rxq_info_get_op,
3296 .txq_info_get = bnxt_txq_info_get_op,
3297 .dev_led_on = bnxt_dev_led_on_op,
3298 .dev_led_off = bnxt_dev_led_off_op,
3299 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3300 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3301 .rx_queue_count = bnxt_rx_queue_count_op,
3302 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3303 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3304 .rx_queue_start = bnxt_rx_queue_start,
3305 .rx_queue_stop = bnxt_rx_queue_stop,
3306 .tx_queue_start = bnxt_tx_queue_start,
3307 .tx_queue_stop = bnxt_tx_queue_stop,
3308 .filter_ctrl = bnxt_filter_ctrl_op,
3309 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3310 .get_eeprom_length = bnxt_get_eeprom_length_op,
3311 .get_eeprom = bnxt_get_eeprom_op,
3312 .set_eeprom = bnxt_set_eeprom_op,
3313 .timesync_enable = bnxt_timesync_enable,
3314 .timesync_disable = bnxt_timesync_disable,
3315 .timesync_read_time = bnxt_timesync_read_time,
3316 .timesync_write_time = bnxt_timesync_write_time,
3317 .timesync_adjust_time = bnxt_timesync_adjust_time,
3318 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3319 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3322 static bool bnxt_vf_pciid(uint16_t id)
3324 if (id == BROADCOM_DEV_ID_57304_VF ||
3325 id == BROADCOM_DEV_ID_57406_VF ||
3326 id == BROADCOM_DEV_ID_5731X_VF ||
3327 id == BROADCOM_DEV_ID_5741X_VF ||
3328 id == BROADCOM_DEV_ID_57414_VF ||
3329 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3330 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3331 id == BROADCOM_DEV_ID_58802_VF ||
3332 id == BROADCOM_DEV_ID_57500_VF)
3337 bool bnxt_stratus_device(struct bnxt *bp)
3339 uint16_t id = bp->pdev->id.device_id;
3341 if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3342 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3343 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3348 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3350 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3351 struct bnxt *bp = eth_dev->data->dev_private;
3353 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3354 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3355 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3356 if (!bp->bar0 || !bp->doorbell_base) {
3357 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
3361 bp->eth_dev = eth_dev;
3367 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3368 struct bnxt_ctx_pg_info *ctx_pg,
3373 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3374 const struct rte_memzone *mz = NULL;
3375 char mz_name[RTE_MEMZONE_NAMESIZE];
3376 rte_iova_t mz_phys_addr;
3377 uint64_t valid_bits = 0;
3384 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3386 rmem->page_size = BNXT_PAGE_SIZE;
3387 rmem->pg_arr = ctx_pg->ctx_pg_arr;
3388 rmem->dma_arr = ctx_pg->ctx_dma_arr;
3389 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3391 valid_bits = PTU_PTE_VALID;
3393 if (rmem->nr_pages > 1) {
3394 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_pg_tbl%s_%x",
3396 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3397 mz = rte_memzone_lookup(mz_name);
3399 mz = rte_memzone_reserve_aligned(mz_name,
3403 RTE_MEMZONE_SIZE_HINT_ONLY |
3404 RTE_MEMZONE_IOVA_CONTIG,
3410 memset(mz->addr, 0, mz->len);
3411 mz_phys_addr = mz->iova;
3412 if ((unsigned long)mz->addr == mz_phys_addr) {
3413 PMD_DRV_LOG(WARNING,
3414 "Memzone physical address same as virtual.\n");
3415 PMD_DRV_LOG(WARNING,
3416 "Using rte_mem_virt2iova()\n");
3417 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3418 if (mz_phys_addr == RTE_BAD_IOVA) {
3420 "unable to map addr to phys memory\n");
3424 rte_mem_lock_page(((char *)mz->addr));
3426 rmem->pg_tbl = mz->addr;
3427 rmem->pg_tbl_map = mz_phys_addr;
3428 rmem->pg_tbl_mz = mz;
3431 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x", suffix, idx);
3432 mz = rte_memzone_lookup(mz_name);
3434 mz = rte_memzone_reserve_aligned(mz_name,
3438 RTE_MEMZONE_SIZE_HINT_ONLY |
3439 RTE_MEMZONE_IOVA_CONTIG,
3445 memset(mz->addr, 0, mz->len);
3446 mz_phys_addr = mz->iova;
3447 if ((unsigned long)mz->addr == mz_phys_addr) {
3448 PMD_DRV_LOG(WARNING,
3449 "Memzone physical address same as virtual.\n");
3450 PMD_DRV_LOG(WARNING,
3451 "Using rte_mem_virt2iova()\n");
3452 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
3453 rte_mem_lock_page(((char *)mz->addr) + sz);
3454 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3455 if (mz_phys_addr == RTE_BAD_IOVA) {
3457 "unable to map addr to phys memory\n");
3462 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
3463 rte_mem_lock_page(((char *)mz->addr) + sz);
3464 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
3465 rmem->dma_arr[i] = mz_phys_addr + sz;
3467 if (rmem->nr_pages > 1) {
3468 if (i == rmem->nr_pages - 2 &&
3469 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3470 valid_bits |= PTU_PTE_NEXT_TO_LAST;
3471 else if (i == rmem->nr_pages - 1 &&
3472 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3473 valid_bits |= PTU_PTE_LAST;
3475 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
3481 if (rmem->vmem_size)
3482 rmem->vmem = (void **)mz->addr;
3483 rmem->dma_arr[0] = mz_phys_addr;
3487 static void bnxt_free_ctx_mem(struct bnxt *bp)
3491 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
3494 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
3495 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
3496 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
3497 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
3498 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
3499 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
3500 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
3501 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
3502 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
3503 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
3504 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
3506 for (i = 0; i < BNXT_MAX_Q; i++) {
3507 if (bp->ctx->tqm_mem[i])
3508 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
3515 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
3517 #define min_t(type, x, y) ({ \
3518 type __min1 = (x); \
3519 type __min2 = (y); \
3520 __min1 < __min2 ? __min1 : __min2; })
3522 #define max_t(type, x, y) ({ \
3523 type __max1 = (x); \
3524 type __max2 = (y); \
3525 __max1 > __max2 ? __max1 : __max2; })
3527 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
3529 int bnxt_alloc_ctx_mem(struct bnxt *bp)
3531 struct bnxt_ctx_pg_info *ctx_pg;
3532 struct bnxt_ctx_mem_info *ctx;
3533 uint32_t mem_size, ena, entries;
3536 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
3538 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
3542 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
3545 ctx_pg = &ctx->qp_mem;
3546 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
3547 mem_size = ctx->qp_entry_size * ctx_pg->entries;
3548 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
3552 ctx_pg = &ctx->srq_mem;
3553 ctx_pg->entries = ctx->srq_max_l2_entries;
3554 mem_size = ctx->srq_entry_size * ctx_pg->entries;
3555 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
3559 ctx_pg = &ctx->cq_mem;
3560 ctx_pg->entries = ctx->cq_max_l2_entries;
3561 mem_size = ctx->cq_entry_size * ctx_pg->entries;
3562 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
3566 ctx_pg = &ctx->vnic_mem;
3567 ctx_pg->entries = ctx->vnic_max_vnic_entries +
3568 ctx->vnic_max_ring_table_entries;
3569 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
3570 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
3574 ctx_pg = &ctx->stat_mem;
3575 ctx_pg->entries = ctx->stat_max_entries;
3576 mem_size = ctx->stat_entry_size * ctx_pg->entries;
3577 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
3581 entries = ctx->qp_max_l2_entries;
3582 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
3583 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
3584 ctx->tqm_max_entries_per_ring);
3585 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
3586 ctx_pg = ctx->tqm_mem[i];
3587 /* use min tqm entries for now. */
3588 ctx_pg->entries = entries;
3589 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
3590 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
3593 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
3596 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
3597 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
3600 "Failed to configure context mem: rc = %d\n", rc);
3602 ctx->flags |= BNXT_CTX_FLAG_INITED;
3607 static int bnxt_alloc_stats_mem(struct bnxt *bp)
3609 struct rte_pci_device *pci_dev = bp->pdev;
3610 char mz_name[RTE_MEMZONE_NAMESIZE];
3611 const struct rte_memzone *mz = NULL;
3612 uint32_t total_alloc_len;
3613 rte_iova_t mz_phys_addr;
3615 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
3618 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3619 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3620 pci_dev->addr.bus, pci_dev->addr.devid,
3621 pci_dev->addr.function, "rx_port_stats");
3622 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3623 mz = rte_memzone_lookup(mz_name);
3625 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
3626 sizeof(struct rx_port_stats_ext) + 512);
3628 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3631 RTE_MEMZONE_SIZE_HINT_ONLY |
3632 RTE_MEMZONE_IOVA_CONTIG);
3636 memset(mz->addr, 0, mz->len);
3637 mz_phys_addr = mz->iova;
3638 if ((unsigned long)mz->addr == mz_phys_addr) {
3639 PMD_DRV_LOG(WARNING,
3640 "Memzone physical address same as virtual.\n");
3641 PMD_DRV_LOG(WARNING,
3642 "Using rte_mem_virt2iova()\n");
3643 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3644 if (mz_phys_addr == RTE_BAD_IOVA) {
3646 "Can't map address to physical memory\n");
3651 bp->rx_mem_zone = (const void *)mz;
3652 bp->hw_rx_port_stats = mz->addr;
3653 bp->hw_rx_port_stats_map = mz_phys_addr;
3655 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3656 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3657 pci_dev->addr.bus, pci_dev->addr.devid,
3658 pci_dev->addr.function, "tx_port_stats");
3659 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3660 mz = rte_memzone_lookup(mz_name);
3662 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
3663 sizeof(struct tx_port_stats_ext) + 512);
3665 mz = rte_memzone_reserve(mz_name,
3669 RTE_MEMZONE_SIZE_HINT_ONLY |
3670 RTE_MEMZONE_IOVA_CONTIG);
3674 memset(mz->addr, 0, mz->len);
3675 mz_phys_addr = mz->iova;
3676 if ((unsigned long)mz->addr == mz_phys_addr) {
3677 PMD_DRV_LOG(WARNING,
3678 "Memzone physical address same as virtual\n");
3679 PMD_DRV_LOG(WARNING,
3680 "Using rte_mem_virt2iova()\n");
3681 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3682 if (mz_phys_addr == RTE_BAD_IOVA) {
3684 "Can't map address to physical memory\n");
3689 bp->tx_mem_zone = (const void *)mz;
3690 bp->hw_tx_port_stats = mz->addr;
3691 bp->hw_tx_port_stats_map = mz_phys_addr;
3692 bp->flags |= BNXT_FLAG_PORT_STATS;
3694 /* Display extended statistics if FW supports it */
3695 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
3696 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
3697 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
3700 bp->hw_rx_port_stats_ext = (void *)
3701 ((uint8_t *)bp->hw_rx_port_stats +
3702 sizeof(struct rx_port_stats));
3703 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
3704 sizeof(struct rx_port_stats);
3705 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
3707 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
3708 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
3709 bp->hw_tx_port_stats_ext = (void *)
3710 ((uint8_t *)bp->hw_tx_port_stats +
3711 sizeof(struct tx_port_stats));
3712 bp->hw_tx_port_stats_ext_map =
3713 bp->hw_tx_port_stats_map +
3714 sizeof(struct tx_port_stats);
3715 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
3721 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
3723 struct bnxt *bp = eth_dev->data->dev_private;
3726 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3727 RTE_ETHER_ADDR_LEN *
3730 if (eth_dev->data->mac_addrs == NULL) {
3731 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
3735 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
3739 /* Generate a random MAC address, if none was assigned by PF */
3740 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
3741 bnxt_eth_hw_addr_random(bp->mac_addr);
3743 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
3744 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
3745 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
3747 rc = bnxt_hwrm_set_mac(bp);
3749 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
3750 RTE_ETHER_ADDR_LEN);
3754 /* Copy the permanent MAC from the FUNC_QCAPS response */
3755 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
3756 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
3761 #define ALLOW_FUNC(x) \
3763 uint32_t arg = (x); \
3764 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3765 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3768 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3770 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3771 static int version_printed;
3776 if (version_printed++ == 0)
3777 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3779 rte_eth_copy_pci_info(eth_dev, pci_dev);
3781 bp = eth_dev->data->dev_private;
3783 bp->dev_stopped = 1;
3785 eth_dev->dev_ops = &bnxt_dev_ops;
3786 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3787 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3790 * For secondary processes, we don't initialise any further
3791 * as primary has already done this work.
3793 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3796 if (bnxt_vf_pciid(pci_dev->id.device_id))
3797 bp->flags |= BNXT_FLAG_VF;
3799 if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
3800 pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
3801 pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
3802 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF)
3803 bp->flags |= BNXT_FLAG_THOR_CHIP;
3805 rc = bnxt_init_board(eth_dev);
3808 "Board initialization failed rc: %x\n", rc);
3812 rc = bnxt_alloc_hwrm_resources(bp);
3815 "hwrm resource allocation failure rc: %x\n", rc);
3818 rc = bnxt_hwrm_ver_get(bp);
3822 rc = bnxt_hwrm_func_reset(bp);
3824 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3829 rc = bnxt_hwrm_queue_qportcfg(bp);
3831 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3834 /* Get the MAX capabilities for this function */
3835 rc = bnxt_hwrm_func_qcaps(bp);
3837 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3841 rc = bnxt_alloc_stats_mem(bp);
3845 if (bp->max_tx_rings == 0) {
3846 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3851 rc = bnxt_setup_mac_addr(eth_dev);
3855 /* THOR does not support ring groups.
3856 * But we will use the array to save RSS context IDs.
3858 if (BNXT_CHIP_THOR(bp)) {
3859 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
3860 } else if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3861 /* 1 ring is for default completion ring */
3862 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3867 if (BNXT_HAS_RING_GRPS(bp)) {
3868 bp->grp_info = rte_zmalloc("bnxt_grp_info",
3869 sizeof(*bp->grp_info) *
3870 bp->max_ring_grps, 0);
3871 if (!bp->grp_info) {
3873 "Failed to alloc %zu bytes for grp info tbl.\n",
3874 sizeof(*bp->grp_info) * bp->max_ring_grps);
3880 /* Forward all requests if firmware is new enough */
3881 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3882 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3883 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3884 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3886 PMD_DRV_LOG(WARNING,
3887 "Firmware too old for VF mailbox functionality\n");
3888 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3892 * The following are used for driver cleanup. If we disallow these,
3893 * VF drivers can't clean up cleanly.
3895 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3896 ALLOW_FUNC(HWRM_VNIC_FREE);
3897 ALLOW_FUNC(HWRM_RING_FREE);
3898 ALLOW_FUNC(HWRM_RING_GRP_FREE);
3899 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3900 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3901 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3902 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3903 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3904 rc = bnxt_hwrm_func_driver_register(bp);
3907 "Failed to register driver");
3913 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3914 pci_dev->mem_resource[0].phys_addr,
3915 pci_dev->mem_resource[0].addr);
3917 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
3919 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3923 if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
3924 mtu != eth_dev->data->mtu)
3925 eth_dev->data->mtu = mtu;
3928 //if (bp->pf.active_vfs) {
3929 // TODO: Deallocate VF resources?
3931 if (bp->pdev->max_vfs) {
3932 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3934 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3938 rc = bnxt_hwrm_allocate_pf_only(bp);
3941 "Failed to allocate PF resources\n");
3947 bnxt_hwrm_port_led_qcaps(bp);
3949 rc = bnxt_setup_int(bp);
3953 rc = bnxt_alloc_mem(bp);
3959 rc = bnxt_request_int(bp);
3966 bnxt_dev_uninit(eth_dev);
3972 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
3974 struct bnxt *bp = eth_dev->data->dev_private;
3977 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3980 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
3981 bnxt_disable_int(bp);
3985 bnxt_hwrm_func_buf_unrgtr(bp);
3987 if (bp->grp_info != NULL) {
3988 rte_free(bp->grp_info);
3989 bp->grp_info = NULL;
3991 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3992 bnxt_free_hwrm_resources(bp);
3994 if (bp->tx_mem_zone) {
3995 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3996 bp->tx_mem_zone = NULL;
3999 if (bp->rx_mem_zone) {
4000 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4001 bp->rx_mem_zone = NULL;
4004 if (bp->dev_stopped == 0)
4005 bnxt_dev_close_op(eth_dev);
4007 rte_free(bp->pf.vf_info);
4008 bnxt_free_ctx_mem(bp);
4009 eth_dev->dev_ops = NULL;
4010 eth_dev->rx_pkt_burst = NULL;
4011 eth_dev->tx_pkt_burst = NULL;
4016 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4017 struct rte_pci_device *pci_dev)
4019 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4023 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4025 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4026 return rte_eth_dev_pci_generic_remove(pci_dev,
4029 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4032 static struct rte_pci_driver bnxt_rte_pmd = {
4033 .id_table = bnxt_pci_id_map,
4034 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4035 .probe = bnxt_pci_probe,
4036 .remove = bnxt_pci_remove,
4040 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4042 if (strcmp(dev->device->driver->name, drv->driver.name))
4048 bool is_bnxt_supported(struct rte_eth_dev *dev)
4050 return is_device_supported(dev, &bnxt_rte_pmd);
4053 RTE_INIT(bnxt_init_log)
4055 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4056 if (bnxt_logtype_driver >= 0)
4057 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4060 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4061 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4062 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");