1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
29 #include "bnxt_util.h"
31 #define DRV_MODULE_NAME "bnxt"
32 static const char bnxt_version[] =
33 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
34 int bnxt_logtype_driver;
36 #define PCI_VENDOR_ID_BROADCOM 0x14E4
38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
41 #define BROADCOM_DEV_ID_57414_VF 0x16c1
42 #define BROADCOM_DEV_ID_57301 0x16c8
43 #define BROADCOM_DEV_ID_57302 0x16c9
44 #define BROADCOM_DEV_ID_57304_PF 0x16ca
45 #define BROADCOM_DEV_ID_57304_VF 0x16cb
46 #define BROADCOM_DEV_ID_57417_MF 0x16cc
47 #define BROADCOM_DEV_ID_NS2 0x16cd
48 #define BROADCOM_DEV_ID_57311 0x16ce
49 #define BROADCOM_DEV_ID_57312 0x16cf
50 #define BROADCOM_DEV_ID_57402 0x16d0
51 #define BROADCOM_DEV_ID_57404 0x16d1
52 #define BROADCOM_DEV_ID_57406_PF 0x16d2
53 #define BROADCOM_DEV_ID_57406_VF 0x16d3
54 #define BROADCOM_DEV_ID_57402_MF 0x16d4
55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
56 #define BROADCOM_DEV_ID_57412 0x16d6
57 #define BROADCOM_DEV_ID_57414 0x16d7
58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
61 #define BROADCOM_DEV_ID_57412_MF 0x16de
62 #define BROADCOM_DEV_ID_57314 0x16df
63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
68 #define BROADCOM_DEV_ID_57404_MF 0x16e7
69 #define BROADCOM_DEV_ID_57406_MF 0x16e8
70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
71 #define BROADCOM_DEV_ID_57407_MF 0x16ea
72 #define BROADCOM_DEV_ID_57414_MF 0x16ec
73 #define BROADCOM_DEV_ID_57416_MF 0x16ee
74 #define BROADCOM_DEV_ID_58802 0xd802
75 #define BROADCOM_DEV_ID_58804 0xd804
76 #define BROADCOM_DEV_ID_58808 0x16f0
77 #define BROADCOM_DEV_ID_58802_VF 0xd800
79 static const struct rte_pci_id bnxt_pci_id_map[] = {
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
81 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
83 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
122 { .vendor_id = 0, /* sentinel */ },
125 #define BNXT_ETH_RSS_SUPPORT ( \
127 ETH_RSS_NONFRAG_IPV4_TCP | \
128 ETH_RSS_NONFRAG_IPV4_UDP | \
130 ETH_RSS_NONFRAG_IPV6_TCP | \
131 ETH_RSS_NONFRAG_IPV6_UDP)
133 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
134 DEV_TX_OFFLOAD_IPV4_CKSUM | \
135 DEV_TX_OFFLOAD_TCP_CKSUM | \
136 DEV_TX_OFFLOAD_UDP_CKSUM | \
137 DEV_TX_OFFLOAD_TCP_TSO | \
138 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
139 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
140 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
141 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
142 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
143 DEV_TX_OFFLOAD_MULTI_SEGS)
145 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
146 DEV_RX_OFFLOAD_VLAN_STRIP | \
147 DEV_RX_OFFLOAD_IPV4_CKSUM | \
148 DEV_RX_OFFLOAD_UDP_CKSUM | \
149 DEV_RX_OFFLOAD_TCP_CKSUM | \
150 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
151 DEV_RX_OFFLOAD_JUMBO_FRAME | \
152 DEV_RX_OFFLOAD_KEEP_CRC | \
153 DEV_RX_OFFLOAD_TCP_LRO)
155 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
156 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
157 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
158 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
160 /***********************/
163 * High level utility functions
166 static void bnxt_free_mem(struct bnxt *bp)
168 bnxt_free_filter_mem(bp);
169 bnxt_free_vnic_attributes(bp);
170 bnxt_free_vnic_mem(bp);
173 bnxt_free_tx_rings(bp);
174 bnxt_free_rx_rings(bp);
177 static int bnxt_alloc_mem(struct bnxt *bp)
181 rc = bnxt_alloc_vnic_mem(bp);
185 rc = bnxt_alloc_vnic_attributes(bp);
189 rc = bnxt_alloc_filter_mem(bp);
200 static int bnxt_init_chip(struct bnxt *bp)
202 struct bnxt_rx_queue *rxq;
203 struct rte_eth_link new;
204 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
205 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
206 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
207 uint64_t rx_offloads = dev_conf->rxmode.offloads;
208 uint32_t intr_vector = 0;
209 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
210 uint32_t vec = BNXT_MISC_VEC_ID;
214 /* disable uio/vfio intr/eventfd mapping */
215 rte_intr_disable(intr_handle);
217 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
218 bp->eth_dev->data->dev_conf.rxmode.offloads |=
219 DEV_RX_OFFLOAD_JUMBO_FRAME;
220 bp->flags |= BNXT_FLAG_JUMBO;
222 bp->eth_dev->data->dev_conf.rxmode.offloads &=
223 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
224 bp->flags &= ~BNXT_FLAG_JUMBO;
227 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
229 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
233 rc = bnxt_alloc_hwrm_rings(bp);
235 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
239 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
241 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
245 rc = bnxt_mq_rx_configure(bp);
247 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
251 /* VNIC configuration */
252 for (i = 0; i < bp->nr_vnics; i++) {
253 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
254 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
255 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
257 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
258 if (!vnic->fw_grp_ids) {
260 "Failed to alloc %d bytes for group ids\n",
265 memset(vnic->fw_grp_ids, -1, size);
267 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
268 i, vnic, vnic->fw_grp_ids);
270 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
272 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
277 /* Alloc RSS context only if RSS mode is enabled */
278 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
279 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
282 "HWRM vnic %d ctx alloc failure rc: %x\n",
289 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
290 * setting is not available at this time, it will not be
291 * configured correctly in the CFA.
293 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
294 vnic->vlan_strip = true;
296 vnic->vlan_strip = false;
298 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
300 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
305 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
308 "HWRM vnic %d filter failure rc: %x\n",
313 for (j = 0; j < bp->rx_nr_rings; j++) {
314 rxq = bp->eth_dev->data->rx_queues[j];
317 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
318 j, rxq->vnic, rxq->vnic->fw_grp_ids);
320 if (rxq->rx_deferred_start)
321 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
324 rc = bnxt_vnic_rss_configure(bp, vnic);
327 "HWRM vnic set RSS failure rc: %x\n", rc);
331 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
333 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
334 DEV_RX_OFFLOAD_TCP_LRO)
335 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
337 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
339 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
342 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
346 /* check and configure queue intr-vector mapping */
347 if ((rte_intr_cap_multiple(intr_handle) ||
348 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
349 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
350 intr_vector = bp->eth_dev->data->nb_rx_queues;
351 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
352 if (intr_vector > bp->rx_cp_nr_rings) {
353 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
357 if (rte_intr_efd_enable(intr_handle, intr_vector))
361 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
362 intr_handle->intr_vec =
363 rte_zmalloc("intr_vec",
364 bp->eth_dev->data->nb_rx_queues *
366 if (intr_handle->intr_vec == NULL) {
367 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
368 " intr_vec", bp->eth_dev->data->nb_rx_queues);
371 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
372 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
373 intr_handle->intr_vec, intr_handle->nb_efd,
374 intr_handle->max_intr);
377 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
379 intr_handle->intr_vec[queue_id] = vec;
380 if (vec < base + intr_handle->nb_efd - 1)
384 /* enable uio/vfio intr/eventfd mapping */
385 rte_intr_enable(intr_handle);
387 rc = bnxt_get_hwrm_link_config(bp, &new);
389 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
393 if (!bp->link_info.link_up) {
394 rc = bnxt_set_hwrm_link_config(bp, true);
397 "HWRM link config failure rc: %x\n", rc);
401 bnxt_print_link_info(bp->eth_dev);
406 bnxt_free_all_hwrm_resources(bp);
408 /* Some of the error status returned by FW may not be from errno.h */
415 static int bnxt_shutdown_nic(struct bnxt *bp)
417 bnxt_free_all_hwrm_resources(bp);
418 bnxt_free_all_filters(bp);
419 bnxt_free_all_vnics(bp);
423 static int bnxt_init_nic(struct bnxt *bp)
427 rc = bnxt_init_ring_grps(bp);
432 bnxt_init_filters(bp);
438 * Device configuration and status function
441 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
442 struct rte_eth_dev_info *dev_info)
444 struct bnxt *bp = eth_dev->data->dev_private;
445 uint16_t max_vnics, i, j, vpool, vrxq;
446 unsigned int max_rx_rings;
449 dev_info->max_mac_addrs = bp->max_l2_ctx;
450 dev_info->max_hash_mac_addrs = 0;
452 /* PF/VF specifics */
454 dev_info->max_vfs = bp->pdev->max_vfs;
455 max_rx_rings = RTE_MIN(bp->max_vnics, bp->max_stat_ctx);
456 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
457 dev_info->max_rx_queues = max_rx_rings;
458 dev_info->max_tx_queues = max_rx_rings;
459 dev_info->reta_size = HW_HASH_INDEX_SIZE;
460 dev_info->hash_key_size = 40;
461 max_vnics = bp->max_vnics;
463 /* Fast path specifics */
464 dev_info->min_rx_bufsize = 1;
465 dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
466 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
468 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
469 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
470 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
471 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
472 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
475 dev_info->default_rxconf = (struct rte_eth_rxconf) {
481 .rx_free_thresh = 32,
482 /* If no descriptors available, pkts are dropped by default */
486 dev_info->default_txconf = (struct rte_eth_txconf) {
492 .tx_free_thresh = 32,
495 eth_dev->data->dev_conf.intr_conf.lsc = 1;
497 eth_dev->data->dev_conf.intr_conf.rxq = 1;
498 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
499 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
500 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
501 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
506 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
507 * need further investigation.
511 vpool = 64; /* ETH_64_POOLS */
512 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
513 for (i = 0; i < 4; vpool >>= 1, i++) {
514 if (max_vnics > vpool) {
515 for (j = 0; j < 5; vrxq >>= 1, j++) {
516 if (dev_info->max_rx_queues > vrxq) {
522 /* Not enough resources to support VMDq */
526 /* Not enough resources to support VMDq */
530 dev_info->max_vmdq_pools = vpool;
531 dev_info->vmdq_queue_num = vrxq;
533 dev_info->vmdq_pool_base = 0;
534 dev_info->vmdq_queue_base = 0;
537 /* Configure the device based on the configuration provided */
538 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
540 struct bnxt *bp = eth_dev->data->dev_private;
541 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
544 bp->rx_queues = (void *)eth_dev->data->rx_queues;
545 bp->tx_queues = (void *)eth_dev->data->tx_queues;
546 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
547 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
549 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
550 rc = bnxt_hwrm_check_vf_rings(bp);
552 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
556 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
558 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
562 /* legacy driver needs to get updated values */
563 rc = bnxt_hwrm_func_qcaps(bp);
565 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
570 /* Inherit new configurations */
571 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
572 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
573 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
575 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
577 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps ||
578 (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
579 bp->max_vnics < eth_dev->data->nb_rx_queues)) {
581 "Insufficient resources to support requested config\n");
583 "Num Queues Requested: Tx %d, Rx %d\n",
584 eth_dev->data->nb_tx_queues,
585 eth_dev->data->nb_rx_queues);
587 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
588 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
589 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
593 bp->rx_cp_nr_rings = bp->rx_nr_rings;
594 bp->tx_cp_nr_rings = bp->tx_nr_rings;
596 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
598 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
599 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
601 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
606 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
608 struct rte_eth_link *link = ð_dev->data->dev_link;
610 if (link->link_status)
611 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
612 eth_dev->data->port_id,
613 (uint32_t)link->link_speed,
614 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
615 ("full-duplex") : ("half-duplex\n"));
617 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
618 eth_dev->data->port_id);
622 * Determine whether the current configuration requires support for scattered
623 * receive; return 1 if scattered receive is required and 0 if not.
625 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
630 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
631 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
633 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
634 RTE_PKTMBUF_HEADROOM);
635 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
641 static eth_rx_burst_t
642 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
646 * Vector mode receive can be enabled only if scatter rx is not
647 * in use and rx offloads are limited to VLAN stripping and
650 if (!eth_dev->data->scattered_rx &&
651 !(eth_dev->data->dev_conf.rxmode.offloads &
652 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
653 DEV_RX_OFFLOAD_KEEP_CRC |
654 DEV_RX_OFFLOAD_JUMBO_FRAME |
655 DEV_RX_OFFLOAD_IPV4_CKSUM |
656 DEV_RX_OFFLOAD_UDP_CKSUM |
657 DEV_RX_OFFLOAD_TCP_CKSUM |
658 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
659 DEV_RX_OFFLOAD_VLAN_FILTER))) {
660 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
661 eth_dev->data->port_id);
662 return bnxt_recv_pkts_vec;
664 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
665 eth_dev->data->port_id);
667 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
668 eth_dev->data->port_id,
669 eth_dev->data->scattered_rx,
670 eth_dev->data->dev_conf.rxmode.offloads);
672 return bnxt_recv_pkts;
675 static eth_tx_burst_t
676 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
680 * Vector mode receive can be enabled only if scatter tx is not
681 * in use and tx offloads other than VLAN insertion are not
684 if (!eth_dev->data->scattered_rx &&
685 !(eth_dev->data->dev_conf.txmode.offloads &
686 ~DEV_TX_OFFLOAD_VLAN_INSERT)) {
687 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
688 eth_dev->data->port_id);
689 return bnxt_xmit_pkts_vec;
691 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
692 eth_dev->data->port_id);
694 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
695 eth_dev->data->port_id,
696 eth_dev->data->scattered_rx,
697 eth_dev->data->dev_conf.txmode.offloads);
699 return bnxt_xmit_pkts;
702 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
704 struct bnxt *bp = eth_dev->data->dev_private;
705 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
709 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
711 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
712 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
716 rc = bnxt_init_chip(bp);
720 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
722 bnxt_link_update_op(eth_dev, 1);
724 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
725 vlan_mask |= ETH_VLAN_FILTER_MASK;
726 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
727 vlan_mask |= ETH_VLAN_STRIP_MASK;
728 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
732 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
733 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
734 bp->flags |= BNXT_FLAG_INIT_DONE;
738 bnxt_shutdown_nic(bp);
739 bnxt_free_tx_mbufs(bp);
740 bnxt_free_rx_mbufs(bp);
744 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
746 struct bnxt *bp = eth_dev->data->dev_private;
749 if (!bp->link_info.link_up)
750 rc = bnxt_set_hwrm_link_config(bp, true);
752 eth_dev->data->dev_link.link_status = 1;
754 bnxt_print_link_info(eth_dev);
758 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
760 struct bnxt *bp = eth_dev->data->dev_private;
762 eth_dev->data->dev_link.link_status = 0;
763 bnxt_set_hwrm_link_config(bp, false);
764 bp->link_info.link_up = 0;
769 /* Unload the driver, release resources */
770 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
772 struct bnxt *bp = eth_dev->data->dev_private;
774 bp->flags &= ~BNXT_FLAG_INIT_DONE;
775 if (bp->eth_dev->data->dev_started) {
776 /* TBD: STOP HW queues DMA */
777 eth_dev->data->dev_link.link_status = 0;
779 bnxt_set_hwrm_link_config(bp, false);
780 bnxt_hwrm_port_clr_stats(bp);
781 bnxt_free_tx_mbufs(bp);
782 bnxt_free_rx_mbufs(bp);
783 bnxt_shutdown_nic(bp);
787 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
789 struct bnxt *bp = eth_dev->data->dev_private;
791 if (bp->dev_stopped == 0)
792 bnxt_dev_stop_op(eth_dev);
794 if (eth_dev->data->mac_addrs != NULL) {
795 rte_free(eth_dev->data->mac_addrs);
796 eth_dev->data->mac_addrs = NULL;
798 if (bp->grp_info != NULL) {
799 rte_free(bp->grp_info);
803 bnxt_dev_uninit(eth_dev);
806 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
809 struct bnxt *bp = eth_dev->data->dev_private;
810 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
811 struct bnxt_vnic_info *vnic;
812 struct bnxt_filter_info *filter, *temp_filter;
816 * Loop through all VNICs from the specified filter flow pools to
817 * remove the corresponding MAC addr filter
819 for (i = 0; i < bp->nr_vnics; i++) {
820 if (!(pool_mask & (1ULL << i)))
823 vnic = &bp->vnic_info[i];
824 filter = STAILQ_FIRST(&vnic->filter);
826 temp_filter = STAILQ_NEXT(filter, next);
827 if (filter->mac_index == index) {
828 STAILQ_REMOVE(&vnic->filter, filter,
829 bnxt_filter_info, next);
830 bnxt_hwrm_clear_l2_filter(bp, filter);
831 filter->mac_index = INVALID_MAC_INDEX;
832 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
833 STAILQ_INSERT_TAIL(&bp->free_filter_list,
836 filter = temp_filter;
841 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
842 struct rte_ether_addr *mac_addr,
843 uint32_t index, uint32_t pool)
845 struct bnxt *bp = eth_dev->data->dev_private;
846 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
847 struct bnxt_filter_info *filter;
849 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
850 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
855 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
858 /* Attach requested MAC address to the new l2_filter */
859 STAILQ_FOREACH(filter, &vnic->filter, next) {
860 if (filter->mac_index == index) {
862 "MAC addr already existed for pool %d\n", pool);
866 filter = bnxt_alloc_filter(bp);
868 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
871 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
872 filter->mac_index = index;
873 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
874 return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
877 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
880 struct bnxt *bp = eth_dev->data->dev_private;
881 struct rte_eth_link new;
882 unsigned int cnt = BNXT_LINK_WAIT_CNT;
884 memset(&new, 0, sizeof(new));
886 /* Retrieve link info from hardware */
887 rc = bnxt_get_hwrm_link_config(bp, &new);
889 new.link_speed = ETH_LINK_SPEED_100M;
890 new.link_duplex = ETH_LINK_FULL_DUPLEX;
892 "Failed to retrieve link rc = 0x%x!\n", rc);
895 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
897 if (!wait_to_complete)
899 } while (!new.link_status && cnt--);
902 /* Timed out or success */
903 if (new.link_status != eth_dev->data->dev_link.link_status ||
904 new.link_speed != eth_dev->data->dev_link.link_speed) {
905 memcpy(ð_dev->data->dev_link, &new,
906 sizeof(struct rte_eth_link));
908 _rte_eth_dev_callback_process(eth_dev,
909 RTE_ETH_EVENT_INTR_LSC,
912 bnxt_print_link_info(eth_dev);
918 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
920 struct bnxt *bp = eth_dev->data->dev_private;
921 struct bnxt_vnic_info *vnic;
923 if (bp->vnic_info == NULL)
926 vnic = &bp->vnic_info[0];
928 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
929 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
932 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
934 struct bnxt *bp = eth_dev->data->dev_private;
935 struct bnxt_vnic_info *vnic;
937 if (bp->vnic_info == NULL)
940 vnic = &bp->vnic_info[0];
942 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
943 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
946 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
948 struct bnxt *bp = eth_dev->data->dev_private;
949 struct bnxt_vnic_info *vnic;
951 if (bp->vnic_info == NULL)
954 vnic = &bp->vnic_info[0];
956 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
957 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
960 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
962 struct bnxt *bp = eth_dev->data->dev_private;
963 struct bnxt_vnic_info *vnic;
965 if (bp->vnic_info == NULL)
968 vnic = &bp->vnic_info[0];
970 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
971 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
974 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
975 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
977 if (qid >= bp->rx_nr_rings)
980 return bp->eth_dev->data->rx_queues[qid];
983 /* Return rxq corresponding to a given rss table ring/group ID. */
984 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
988 for (i = 0; i < bp->rx_nr_rings; i++) {
989 if (bp->grp_info[i].fw_grp_id == fwr)
993 return INVALID_HW_RING_ID;
996 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
997 struct rte_eth_rss_reta_entry64 *reta_conf,
1000 struct bnxt *bp = eth_dev->data->dev_private;
1001 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1002 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1003 uint16_t tbl_size = HW_HASH_INDEX_SIZE;
1007 if (!vnic->rss_table)
1010 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1013 if (reta_size != tbl_size) {
1014 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1015 "(%d) must equal the size supported by the hardware "
1016 "(%d)\n", reta_size, tbl_size);
1020 for (i = 0; i < reta_size; i++) {
1021 struct bnxt_rx_queue *rxq;
1023 idx = i / RTE_RETA_GROUP_SIZE;
1024 sft = i % RTE_RETA_GROUP_SIZE;
1026 if (!(reta_conf[idx].mask & (1ULL << sft)))
1029 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1031 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1035 vnic->rss_table[i] =
1036 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1039 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1043 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1044 struct rte_eth_rss_reta_entry64 *reta_conf,
1047 struct bnxt *bp = eth_dev->data->dev_private;
1048 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1049 uint16_t tbl_size = HW_HASH_INDEX_SIZE;
1050 uint16_t idx, sft, i;
1052 /* Retrieve from the default VNIC */
1055 if (!vnic->rss_table)
1058 if (reta_size != tbl_size) {
1059 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1060 "(%d) must equal the size supported by the hardware "
1061 "(%d)\n", reta_size, tbl_size);
1065 for (idx = 0, i = 0; i < reta_size; i++) {
1066 idx = i / RTE_RETA_GROUP_SIZE;
1067 sft = i % RTE_RETA_GROUP_SIZE;
1069 if (reta_conf[idx].mask & (1ULL << sft)) {
1072 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1074 if (qid == INVALID_HW_RING_ID) {
1075 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1078 reta_conf[idx].reta[sft] = qid;
1085 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1086 struct rte_eth_rss_conf *rss_conf)
1088 struct bnxt *bp = eth_dev->data->dev_private;
1089 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1090 struct bnxt_vnic_info *vnic;
1091 uint16_t hash_type = 0;
1095 * If RSS enablement were different than dev_configure,
1096 * then return -EINVAL
1098 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1099 if (!rss_conf->rss_hf)
1100 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1102 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1106 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1107 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1109 if (rss_conf->rss_hf & ETH_RSS_IPV4)
1110 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1111 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1112 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1113 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1114 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1115 if (rss_conf->rss_hf & ETH_RSS_IPV6)
1116 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1117 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1118 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1119 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1120 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1122 /* Update the RSS VNIC(s) */
1123 for (i = 0; i < bp->nr_vnics; i++) {
1124 vnic = &bp->vnic_info[i];
1125 vnic->hash_type = hash_type;
1128 * Use the supplied key if the key length is
1129 * acceptable and the rss_key is not NULL
1131 if (rss_conf->rss_key &&
1132 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1133 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1134 rss_conf->rss_key_len);
1136 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1141 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1142 struct rte_eth_rss_conf *rss_conf)
1144 struct bnxt *bp = eth_dev->data->dev_private;
1145 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1147 uint32_t hash_types;
1149 /* RSS configuration is the same for all VNICs */
1150 if (vnic && vnic->rss_hash_key) {
1151 if (rss_conf->rss_key) {
1152 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1153 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1154 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1157 hash_types = vnic->hash_type;
1158 rss_conf->rss_hf = 0;
1159 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1160 rss_conf->rss_hf |= ETH_RSS_IPV4;
1161 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1163 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1164 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1166 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1168 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1169 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1171 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1173 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1174 rss_conf->rss_hf |= ETH_RSS_IPV6;
1175 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1177 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1178 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1180 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1182 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1183 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1185 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1189 "Unknwon RSS config from firmware (%08x), RSS disabled",
1194 rss_conf->rss_hf = 0;
1199 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1200 struct rte_eth_fc_conf *fc_conf)
1202 struct bnxt *bp = dev->data->dev_private;
1203 struct rte_eth_link link_info;
1206 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1210 memset(fc_conf, 0, sizeof(*fc_conf));
1211 if (bp->link_info.auto_pause)
1212 fc_conf->autoneg = 1;
1213 switch (bp->link_info.pause) {
1215 fc_conf->mode = RTE_FC_NONE;
1217 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1218 fc_conf->mode = RTE_FC_TX_PAUSE;
1220 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1221 fc_conf->mode = RTE_FC_RX_PAUSE;
1223 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1224 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1225 fc_conf->mode = RTE_FC_FULL;
1231 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1232 struct rte_eth_fc_conf *fc_conf)
1234 struct bnxt *bp = dev->data->dev_private;
1236 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1237 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1241 switch (fc_conf->mode) {
1243 bp->link_info.auto_pause = 0;
1244 bp->link_info.force_pause = 0;
1246 case RTE_FC_RX_PAUSE:
1247 if (fc_conf->autoneg) {
1248 bp->link_info.auto_pause =
1249 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1250 bp->link_info.force_pause = 0;
1252 bp->link_info.auto_pause = 0;
1253 bp->link_info.force_pause =
1254 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1257 case RTE_FC_TX_PAUSE:
1258 if (fc_conf->autoneg) {
1259 bp->link_info.auto_pause =
1260 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1261 bp->link_info.force_pause = 0;
1263 bp->link_info.auto_pause = 0;
1264 bp->link_info.force_pause =
1265 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1269 if (fc_conf->autoneg) {
1270 bp->link_info.auto_pause =
1271 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1272 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1273 bp->link_info.force_pause = 0;
1275 bp->link_info.auto_pause = 0;
1276 bp->link_info.force_pause =
1277 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1278 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1282 return bnxt_set_hwrm_link_config(bp, true);
1285 /* Add UDP tunneling port */
1287 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1288 struct rte_eth_udp_tunnel *udp_tunnel)
1290 struct bnxt *bp = eth_dev->data->dev_private;
1291 uint16_t tunnel_type = 0;
1294 switch (udp_tunnel->prot_type) {
1295 case RTE_TUNNEL_TYPE_VXLAN:
1296 if (bp->vxlan_port_cnt) {
1297 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1298 udp_tunnel->udp_port);
1299 if (bp->vxlan_port != udp_tunnel->udp_port) {
1300 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1303 bp->vxlan_port_cnt++;
1307 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1308 bp->vxlan_port_cnt++;
1310 case RTE_TUNNEL_TYPE_GENEVE:
1311 if (bp->geneve_port_cnt) {
1312 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1313 udp_tunnel->udp_port);
1314 if (bp->geneve_port != udp_tunnel->udp_port) {
1315 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1318 bp->geneve_port_cnt++;
1322 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1323 bp->geneve_port_cnt++;
1326 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1329 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1335 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1336 struct rte_eth_udp_tunnel *udp_tunnel)
1338 struct bnxt *bp = eth_dev->data->dev_private;
1339 uint16_t tunnel_type = 0;
1343 switch (udp_tunnel->prot_type) {
1344 case RTE_TUNNEL_TYPE_VXLAN:
1345 if (!bp->vxlan_port_cnt) {
1346 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1349 if (bp->vxlan_port != udp_tunnel->udp_port) {
1350 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1351 udp_tunnel->udp_port, bp->vxlan_port);
1354 if (--bp->vxlan_port_cnt)
1358 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1359 port = bp->vxlan_fw_dst_port_id;
1361 case RTE_TUNNEL_TYPE_GENEVE:
1362 if (!bp->geneve_port_cnt) {
1363 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1366 if (bp->geneve_port != udp_tunnel->udp_port) {
1367 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1368 udp_tunnel->udp_port, bp->geneve_port);
1371 if (--bp->geneve_port_cnt)
1375 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1376 port = bp->geneve_fw_dst_port_id;
1379 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1383 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1386 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1389 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1390 bp->geneve_port = 0;
1395 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1397 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1398 struct bnxt_vnic_info *vnic;
1401 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1403 /* Cycle through all VNICs */
1404 for (i = 0; i < bp->nr_vnics; i++) {
1406 * For each VNIC and each associated filter(s)
1407 * if VLAN exists && VLAN matches vlan_id
1408 * remove the MAC+VLAN filter
1409 * add a new MAC only filter
1411 * VLAN filter doesn't exist, just skip and continue
1413 vnic = &bp->vnic_info[i];
1414 filter = STAILQ_FIRST(&vnic->filter);
1416 temp_filter = STAILQ_NEXT(filter, next);
1418 if (filter->enables & chk &&
1419 filter->l2_ovlan == vlan_id) {
1420 /* Must delete the filter */
1421 STAILQ_REMOVE(&vnic->filter, filter,
1422 bnxt_filter_info, next);
1423 bnxt_hwrm_clear_l2_filter(bp, filter);
1424 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1428 * Need to examine to see if the MAC
1429 * filter already existed or not before
1430 * allocating a new one
1433 new_filter = bnxt_alloc_filter(bp);
1436 "MAC/VLAN filter alloc failed\n");
1440 STAILQ_INSERT_TAIL(&vnic->filter,
1442 /* Inherit MAC from previous filter */
1443 new_filter->mac_index =
1445 memcpy(new_filter->l2_addr, filter->l2_addr,
1446 RTE_ETHER_ADDR_LEN);
1447 /* MAC only filter */
1448 rc = bnxt_hwrm_set_l2_filter(bp,
1454 "Del Vlan filter for %d\n",
1457 filter = temp_filter;
1464 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1466 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1467 struct bnxt_vnic_info *vnic;
1470 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1471 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1472 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1474 /* Cycle through all VNICs */
1475 for (i = 0; i < bp->nr_vnics; i++) {
1477 * For each VNIC and each associated filter(s)
1479 * if VLAN matches vlan_id
1480 * VLAN filter already exists, just skip and continue
1482 * add a new MAC+VLAN filter
1484 * Remove the old MAC only filter
1485 * Add a new MAC+VLAN filter
1487 vnic = &bp->vnic_info[i];
1488 filter = STAILQ_FIRST(&vnic->filter);
1490 temp_filter = STAILQ_NEXT(filter, next);
1492 if (filter->enables & chk) {
1493 if (filter->l2_ivlan == vlan_id)
1496 /* Must delete the MAC filter */
1497 STAILQ_REMOVE(&vnic->filter, filter,
1498 bnxt_filter_info, next);
1499 bnxt_hwrm_clear_l2_filter(bp, filter);
1500 filter->l2_ovlan = 0;
1501 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1504 new_filter = bnxt_alloc_filter(bp);
1507 "MAC/VLAN filter alloc failed\n");
1511 STAILQ_INSERT_TAIL(&vnic->filter, new_filter, next);
1512 /* Inherit MAC from the previous filter */
1513 new_filter->mac_index = filter->mac_index;
1514 memcpy(new_filter->l2_addr, filter->l2_addr,
1515 RTE_ETHER_ADDR_LEN);
1516 /* MAC + VLAN ID filter */
1517 new_filter->l2_ivlan = vlan_id;
1518 new_filter->l2_ivlan_mask = 0xF000;
1519 new_filter->enables |= en;
1520 rc = bnxt_hwrm_set_l2_filter(bp,
1526 "Added Vlan filter for %d\n", vlan_id);
1528 filter = temp_filter;
1535 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1536 uint16_t vlan_id, int on)
1538 struct bnxt *bp = eth_dev->data->dev_private;
1540 /* These operations apply to ALL existing MAC/VLAN filters */
1542 return bnxt_add_vlan_filter(bp, vlan_id);
1544 return bnxt_del_vlan_filter(bp, vlan_id);
1548 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1550 struct bnxt *bp = dev->data->dev_private;
1551 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1554 if (mask & ETH_VLAN_FILTER_MASK) {
1555 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1556 /* Remove any VLAN filters programmed */
1557 for (i = 0; i < 4095; i++)
1558 bnxt_del_vlan_filter(bp, i);
1560 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1561 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1564 if (mask & ETH_VLAN_STRIP_MASK) {
1565 /* Enable or disable VLAN stripping */
1566 for (i = 0; i < bp->nr_vnics; i++) {
1567 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1568 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1569 vnic->vlan_strip = true;
1571 vnic->vlan_strip = false;
1572 bnxt_hwrm_vnic_cfg(bp, vnic);
1574 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1575 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1578 if (mask & ETH_VLAN_EXTEND_MASK)
1579 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1585 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1586 struct rte_ether_addr *addr)
1588 struct bnxt *bp = dev->data->dev_private;
1589 /* Default Filter is tied to VNIC 0 */
1590 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1591 struct bnxt_filter_info *filter;
1594 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1597 memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1599 STAILQ_FOREACH(filter, &vnic->filter, next) {
1600 /* Default Filter is at Index 0 */
1601 if (filter->mac_index != 0)
1603 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1606 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1607 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1608 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1610 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1611 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1612 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1615 filter->mac_index = 0;
1616 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1623 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1624 struct rte_ether_addr *mc_addr_set,
1625 uint32_t nb_mc_addr)
1627 struct bnxt *bp = eth_dev->data->dev_private;
1628 char *mc_addr_list = (char *)mc_addr_set;
1629 struct bnxt_vnic_info *vnic;
1630 uint32_t off = 0, i = 0;
1632 vnic = &bp->vnic_info[0];
1634 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1635 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1639 /* TODO Check for Duplicate mcast addresses */
1640 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1641 for (i = 0; i < nb_mc_addr; i++) {
1642 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1643 RTE_ETHER_ADDR_LEN);
1644 off += RTE_ETHER_ADDR_LEN;
1647 vnic->mc_addr_cnt = i;
1650 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1654 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1656 struct bnxt *bp = dev->data->dev_private;
1657 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1658 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1659 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1662 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1663 fw_major, fw_minor, fw_updt);
1665 ret += 1; /* add the size of '\0' */
1666 if (fw_size < (uint32_t)ret)
1673 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1674 struct rte_eth_rxq_info *qinfo)
1676 struct bnxt_rx_queue *rxq;
1678 rxq = dev->data->rx_queues[queue_id];
1680 qinfo->mp = rxq->mb_pool;
1681 qinfo->scattered_rx = dev->data->scattered_rx;
1682 qinfo->nb_desc = rxq->nb_rx_desc;
1684 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1685 qinfo->conf.rx_drop_en = 0;
1686 qinfo->conf.rx_deferred_start = 0;
1690 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1691 struct rte_eth_txq_info *qinfo)
1693 struct bnxt_tx_queue *txq;
1695 txq = dev->data->tx_queues[queue_id];
1697 qinfo->nb_desc = txq->nb_tx_desc;
1699 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1700 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1701 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1703 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1704 qinfo->conf.tx_rs_thresh = 0;
1705 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1708 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1710 struct bnxt *bp = eth_dev->data->dev_private;
1711 struct rte_eth_dev_info dev_info;
1712 uint32_t new_pkt_size;
1716 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1717 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1719 bnxt_dev_info_get_op(eth_dev, &dev_info);
1721 if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1722 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1723 RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1729 * If vector-mode tx/rx is active, disallow any MTU change that would
1730 * require scattered receive support.
1732 if (eth_dev->data->dev_started &&
1733 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1734 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1736 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1738 "MTU change would require scattered rx support. ");
1739 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
1744 if (new_mtu > RTE_ETHER_MTU) {
1745 bp->flags |= BNXT_FLAG_JUMBO;
1746 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1747 DEV_RX_OFFLOAD_JUMBO_FRAME;
1749 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1750 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1751 bp->flags &= ~BNXT_FLAG_JUMBO;
1754 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
1756 eth_dev->data->mtu = new_mtu;
1757 PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1759 for (i = 0; i < bp->nr_vnics; i++) {
1760 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1763 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1764 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1765 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1769 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1770 size -= RTE_PKTMBUF_HEADROOM;
1772 if (size < new_mtu) {
1773 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1783 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1785 struct bnxt *bp = dev->data->dev_private;
1786 uint16_t vlan = bp->vlan;
1789 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1791 "PVID cannot be modified for this function\n");
1794 bp->vlan = on ? pvid : 0;
1796 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1803 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1805 struct bnxt *bp = dev->data->dev_private;
1807 return bnxt_hwrm_port_led_cfg(bp, true);
1811 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1813 struct bnxt *bp = dev->data->dev_private;
1815 return bnxt_hwrm_port_led_cfg(bp, false);
1819 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1821 uint32_t desc = 0, raw_cons = 0, cons;
1822 struct bnxt_cp_ring_info *cpr;
1823 struct bnxt_rx_queue *rxq;
1824 struct rx_pkt_cmpl *rxcmp;
1829 rxq = dev->data->rx_queues[rx_queue_id];
1833 while (raw_cons < rxq->nb_rx_desc) {
1834 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1835 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1837 if (!CMPL_VALID(rxcmp, valid))
1839 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1840 cmp_type = CMP_TYPE(rxcmp);
1841 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1842 cmp = (rte_le_to_cpu_32(
1843 ((struct rx_tpa_end_cmpl *)
1844 (rxcmp))->agg_bufs_v1) &
1845 RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1846 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1848 } else if (cmp_type == 0x11) {
1850 cmp = (rxcmp->agg_bufs_v1 &
1851 RX_PKT_CMPL_AGG_BUFS_MASK) >>
1852 RX_PKT_CMPL_AGG_BUFS_SFT;
1857 raw_cons += cmp ? cmp : 2;
1864 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1866 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1867 struct bnxt_rx_ring_info *rxr;
1868 struct bnxt_cp_ring_info *cpr;
1869 struct bnxt_sw_rx_bd *rx_buf;
1870 struct rx_pkt_cmpl *rxcmp;
1871 uint32_t cons, cp_cons;
1879 if (offset >= rxq->nb_rx_desc)
1882 cons = RING_CMP(cpr->cp_ring_struct, offset);
1883 cp_cons = cpr->cp_raw_cons;
1884 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1886 if (cons > cp_cons) {
1887 if (CMPL_VALID(rxcmp, cpr->valid))
1888 return RTE_ETH_RX_DESC_DONE;
1890 if (CMPL_VALID(rxcmp, !cpr->valid))
1891 return RTE_ETH_RX_DESC_DONE;
1893 rx_buf = &rxr->rx_buf_ring[cons];
1894 if (rx_buf->mbuf == NULL)
1895 return RTE_ETH_RX_DESC_UNAVAIL;
1898 return RTE_ETH_RX_DESC_AVAIL;
1902 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1904 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1905 struct bnxt_tx_ring_info *txr;
1906 struct bnxt_cp_ring_info *cpr;
1907 struct bnxt_sw_tx_bd *tx_buf;
1908 struct tx_pkt_cmpl *txcmp;
1909 uint32_t cons, cp_cons;
1917 if (offset >= txq->nb_tx_desc)
1920 cons = RING_CMP(cpr->cp_ring_struct, offset);
1921 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1922 cp_cons = cpr->cp_raw_cons;
1924 if (cons > cp_cons) {
1925 if (CMPL_VALID(txcmp, cpr->valid))
1926 return RTE_ETH_TX_DESC_UNAVAIL;
1928 if (CMPL_VALID(txcmp, !cpr->valid))
1929 return RTE_ETH_TX_DESC_UNAVAIL;
1931 tx_buf = &txr->tx_buf_ring[cons];
1932 if (tx_buf->mbuf == NULL)
1933 return RTE_ETH_TX_DESC_DONE;
1935 return RTE_ETH_TX_DESC_FULL;
1938 static struct bnxt_filter_info *
1939 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1940 struct rte_eth_ethertype_filter *efilter,
1941 struct bnxt_vnic_info *vnic0,
1942 struct bnxt_vnic_info *vnic,
1945 struct bnxt_filter_info *mfilter = NULL;
1949 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
1950 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
1951 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
1952 " ethertype filter.", efilter->ether_type);
1956 if (efilter->queue >= bp->rx_nr_rings) {
1957 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1962 vnic0 = &bp->vnic_info[0];
1963 vnic = &bp->vnic_info[efilter->queue];
1965 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1970 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1971 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1972 if ((!memcmp(efilter->mac_addr.addr_bytes,
1973 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
1975 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1976 mfilter->ethertype == efilter->ether_type)) {
1982 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1983 if ((!memcmp(efilter->mac_addr.addr_bytes,
1984 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
1985 mfilter->ethertype == efilter->ether_type &&
1987 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2001 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2002 enum rte_filter_op filter_op,
2005 struct bnxt *bp = dev->data->dev_private;
2006 struct rte_eth_ethertype_filter *efilter =
2007 (struct rte_eth_ethertype_filter *)arg;
2008 struct bnxt_filter_info *bfilter, *filter1;
2009 struct bnxt_vnic_info *vnic, *vnic0;
2012 if (filter_op == RTE_ETH_FILTER_NOP)
2016 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2021 vnic0 = &bp->vnic_info[0];
2022 vnic = &bp->vnic_info[efilter->queue];
2024 switch (filter_op) {
2025 case RTE_ETH_FILTER_ADD:
2026 bnxt_match_and_validate_ether_filter(bp, efilter,
2031 bfilter = bnxt_get_unused_filter(bp);
2032 if (bfilter == NULL) {
2034 "Not enough resources for a new filter.\n");
2037 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2038 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2039 RTE_ETHER_ADDR_LEN);
2040 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2041 RTE_ETHER_ADDR_LEN);
2042 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2043 bfilter->ethertype = efilter->ether_type;
2044 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2046 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2047 if (filter1 == NULL) {
2052 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2053 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2055 bfilter->dst_id = vnic->fw_vnic_id;
2057 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2059 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2062 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2065 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2067 case RTE_ETH_FILTER_DELETE:
2068 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2070 if (ret == -EEXIST) {
2071 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2073 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2075 bnxt_free_filter(bp, filter1);
2076 } else if (ret == 0) {
2077 PMD_DRV_LOG(ERR, "No matching filter found\n");
2081 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2087 bnxt_free_filter(bp, bfilter);
2093 parse_ntuple_filter(struct bnxt *bp,
2094 struct rte_eth_ntuple_filter *nfilter,
2095 struct bnxt_filter_info *bfilter)
2099 if (nfilter->queue >= bp->rx_nr_rings) {
2100 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2104 switch (nfilter->dst_port_mask) {
2106 bfilter->dst_port_mask = -1;
2107 bfilter->dst_port = nfilter->dst_port;
2108 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2109 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2112 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2116 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2117 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2119 switch (nfilter->proto_mask) {
2121 if (nfilter->proto == 17) /* IPPROTO_UDP */
2122 bfilter->ip_protocol = 17;
2123 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2124 bfilter->ip_protocol = 6;
2127 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2130 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2134 switch (nfilter->dst_ip_mask) {
2136 bfilter->dst_ipaddr_mask[0] = -1;
2137 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2138 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2139 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2142 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2146 switch (nfilter->src_ip_mask) {
2148 bfilter->src_ipaddr_mask[0] = -1;
2149 bfilter->src_ipaddr[0] = nfilter->src_ip;
2150 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2151 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2154 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2158 switch (nfilter->src_port_mask) {
2160 bfilter->src_port_mask = -1;
2161 bfilter->src_port = nfilter->src_port;
2162 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2163 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2166 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2171 //nfilter->priority = (uint8_t)filter->priority;
2173 bfilter->enables = en;
2177 static struct bnxt_filter_info*
2178 bnxt_match_ntuple_filter(struct bnxt *bp,
2179 struct bnxt_filter_info *bfilter,
2180 struct bnxt_vnic_info **mvnic)
2182 struct bnxt_filter_info *mfilter = NULL;
2185 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2186 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2187 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2188 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2189 bfilter->src_ipaddr_mask[0] ==
2190 mfilter->src_ipaddr_mask[0] &&
2191 bfilter->src_port == mfilter->src_port &&
2192 bfilter->src_port_mask == mfilter->src_port_mask &&
2193 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2194 bfilter->dst_ipaddr_mask[0] ==
2195 mfilter->dst_ipaddr_mask[0] &&
2196 bfilter->dst_port == mfilter->dst_port &&
2197 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2198 bfilter->flags == mfilter->flags &&
2199 bfilter->enables == mfilter->enables) {
2210 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2211 struct rte_eth_ntuple_filter *nfilter,
2212 enum rte_filter_op filter_op)
2214 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2215 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2218 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2219 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2223 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2224 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2228 bfilter = bnxt_get_unused_filter(bp);
2229 if (bfilter == NULL) {
2231 "Not enough resources for a new filter.\n");
2234 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2238 vnic = &bp->vnic_info[nfilter->queue];
2239 vnic0 = &bp->vnic_info[0];
2240 filter1 = STAILQ_FIRST(&vnic0->filter);
2241 if (filter1 == NULL) {
2246 bfilter->dst_id = vnic->fw_vnic_id;
2247 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2249 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2250 bfilter->ethertype = 0x800;
2251 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2253 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2255 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2256 bfilter->dst_id == mfilter->dst_id) {
2257 PMD_DRV_LOG(ERR, "filter exists.\n");
2260 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2261 bfilter->dst_id != mfilter->dst_id) {
2262 mfilter->dst_id = vnic->fw_vnic_id;
2263 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2264 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2265 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2266 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2267 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2270 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2271 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2276 if (filter_op == RTE_ETH_FILTER_ADD) {
2277 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2278 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2281 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2283 if (mfilter == NULL) {
2284 /* This should not happen. But for Coverity! */
2288 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2290 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2291 bnxt_free_filter(bp, mfilter);
2292 mfilter->fw_l2_filter_id = -1;
2293 bnxt_free_filter(bp, bfilter);
2294 bfilter->fw_l2_filter_id = -1;
2299 bfilter->fw_l2_filter_id = -1;
2300 bnxt_free_filter(bp, bfilter);
2305 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2306 enum rte_filter_op filter_op,
2309 struct bnxt *bp = dev->data->dev_private;
2312 if (filter_op == RTE_ETH_FILTER_NOP)
2316 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2321 switch (filter_op) {
2322 case RTE_ETH_FILTER_ADD:
2323 ret = bnxt_cfg_ntuple_filter(bp,
2324 (struct rte_eth_ntuple_filter *)arg,
2327 case RTE_ETH_FILTER_DELETE:
2328 ret = bnxt_cfg_ntuple_filter(bp,
2329 (struct rte_eth_ntuple_filter *)arg,
2333 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2341 bnxt_parse_fdir_filter(struct bnxt *bp,
2342 struct rte_eth_fdir_filter *fdir,
2343 struct bnxt_filter_info *filter)
2345 enum rte_fdir_mode fdir_mode =
2346 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2347 struct bnxt_vnic_info *vnic0, *vnic;
2348 struct bnxt_filter_info *filter1;
2352 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2355 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2356 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2358 switch (fdir->input.flow_type) {
2359 case RTE_ETH_FLOW_IPV4:
2360 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2362 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2363 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2364 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2365 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2366 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2367 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2368 filter->ip_addr_type =
2369 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2370 filter->src_ipaddr_mask[0] = 0xffffffff;
2371 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2372 filter->dst_ipaddr_mask[0] = 0xffffffff;
2373 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2374 filter->ethertype = 0x800;
2375 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2377 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2378 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2379 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2380 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2381 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2382 filter->dst_port_mask = 0xffff;
2383 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2384 filter->src_port_mask = 0xffff;
2385 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2386 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2387 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2388 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2389 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2390 filter->ip_protocol = 6;
2391 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2392 filter->ip_addr_type =
2393 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2394 filter->src_ipaddr_mask[0] = 0xffffffff;
2395 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2396 filter->dst_ipaddr_mask[0] = 0xffffffff;
2397 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2398 filter->ethertype = 0x800;
2399 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2401 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2402 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2403 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2404 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2405 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2406 filter->dst_port_mask = 0xffff;
2407 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2408 filter->src_port_mask = 0xffff;
2409 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2410 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2411 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2412 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2413 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2414 filter->ip_protocol = 17;
2415 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2416 filter->ip_addr_type =
2417 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2418 filter->src_ipaddr_mask[0] = 0xffffffff;
2419 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2420 filter->dst_ipaddr_mask[0] = 0xffffffff;
2421 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2422 filter->ethertype = 0x800;
2423 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2425 case RTE_ETH_FLOW_IPV6:
2426 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2428 filter->ip_addr_type =
2429 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2430 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2431 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2432 rte_memcpy(filter->src_ipaddr,
2433 fdir->input.flow.ipv6_flow.src_ip, 16);
2434 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2435 rte_memcpy(filter->dst_ipaddr,
2436 fdir->input.flow.ipv6_flow.dst_ip, 16);
2437 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2438 memset(filter->dst_ipaddr_mask, 0xff, 16);
2439 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2440 memset(filter->src_ipaddr_mask, 0xff, 16);
2441 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2442 filter->ethertype = 0x86dd;
2443 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2445 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2446 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2447 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2448 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2449 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2450 filter->dst_port_mask = 0xffff;
2451 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2452 filter->src_port_mask = 0xffff;
2453 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2454 filter->ip_addr_type =
2455 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2456 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2457 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2458 rte_memcpy(filter->src_ipaddr,
2459 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2460 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2461 rte_memcpy(filter->dst_ipaddr,
2462 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2463 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2464 memset(filter->dst_ipaddr_mask, 0xff, 16);
2465 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2466 memset(filter->src_ipaddr_mask, 0xff, 16);
2467 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2468 filter->ethertype = 0x86dd;
2469 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2471 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2472 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2473 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2474 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2475 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2476 filter->dst_port_mask = 0xffff;
2477 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2478 filter->src_port_mask = 0xffff;
2479 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2480 filter->ip_addr_type =
2481 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2482 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2483 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2484 rte_memcpy(filter->src_ipaddr,
2485 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2486 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2487 rte_memcpy(filter->dst_ipaddr,
2488 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2489 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2490 memset(filter->dst_ipaddr_mask, 0xff, 16);
2491 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2492 memset(filter->src_ipaddr_mask, 0xff, 16);
2493 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2494 filter->ethertype = 0x86dd;
2495 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2497 case RTE_ETH_FLOW_L2_PAYLOAD:
2498 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2499 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2501 case RTE_ETH_FLOW_VXLAN:
2502 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2504 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2505 filter->tunnel_type =
2506 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2507 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2509 case RTE_ETH_FLOW_NVGRE:
2510 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2512 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2513 filter->tunnel_type =
2514 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2515 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2517 case RTE_ETH_FLOW_UNKNOWN:
2518 case RTE_ETH_FLOW_RAW:
2519 case RTE_ETH_FLOW_FRAG_IPV4:
2520 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2521 case RTE_ETH_FLOW_FRAG_IPV6:
2522 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2523 case RTE_ETH_FLOW_IPV6_EX:
2524 case RTE_ETH_FLOW_IPV6_TCP_EX:
2525 case RTE_ETH_FLOW_IPV6_UDP_EX:
2526 case RTE_ETH_FLOW_GENEVE:
2532 vnic0 = &bp->vnic_info[0];
2533 vnic = &bp->vnic_info[fdir->action.rx_queue];
2535 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2540 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2541 rte_memcpy(filter->dst_macaddr,
2542 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2543 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2546 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2547 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2548 filter1 = STAILQ_FIRST(&vnic0->filter);
2549 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2551 filter->dst_id = vnic->fw_vnic_id;
2552 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2553 if (filter->dst_macaddr[i] == 0x00)
2554 filter1 = STAILQ_FIRST(&vnic0->filter);
2556 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2559 if (filter1 == NULL)
2562 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2563 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2565 filter->enables = en;
2570 static struct bnxt_filter_info *
2571 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2572 struct bnxt_vnic_info **mvnic)
2574 struct bnxt_filter_info *mf = NULL;
2577 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2578 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2580 STAILQ_FOREACH(mf, &vnic->filter, next) {
2581 if (mf->filter_type == nf->filter_type &&
2582 mf->flags == nf->flags &&
2583 mf->src_port == nf->src_port &&
2584 mf->src_port_mask == nf->src_port_mask &&
2585 mf->dst_port == nf->dst_port &&
2586 mf->dst_port_mask == nf->dst_port_mask &&
2587 mf->ip_protocol == nf->ip_protocol &&
2588 mf->ip_addr_type == nf->ip_addr_type &&
2589 mf->ethertype == nf->ethertype &&
2590 mf->vni == nf->vni &&
2591 mf->tunnel_type == nf->tunnel_type &&
2592 mf->l2_ovlan == nf->l2_ovlan &&
2593 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2594 mf->l2_ivlan == nf->l2_ivlan &&
2595 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2596 !memcmp(mf->l2_addr, nf->l2_addr,
2597 RTE_ETHER_ADDR_LEN) &&
2598 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2599 RTE_ETHER_ADDR_LEN) &&
2600 !memcmp(mf->src_macaddr, nf->src_macaddr,
2601 RTE_ETHER_ADDR_LEN) &&
2602 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2603 RTE_ETHER_ADDR_LEN) &&
2604 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2605 sizeof(nf->src_ipaddr)) &&
2606 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2607 sizeof(nf->src_ipaddr_mask)) &&
2608 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2609 sizeof(nf->dst_ipaddr)) &&
2610 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2611 sizeof(nf->dst_ipaddr_mask))) {
2622 bnxt_fdir_filter(struct rte_eth_dev *dev,
2623 enum rte_filter_op filter_op,
2626 struct bnxt *bp = dev->data->dev_private;
2627 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2628 struct bnxt_filter_info *filter, *match;
2629 struct bnxt_vnic_info *vnic, *mvnic;
2632 if (filter_op == RTE_ETH_FILTER_NOP)
2635 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2638 switch (filter_op) {
2639 case RTE_ETH_FILTER_ADD:
2640 case RTE_ETH_FILTER_DELETE:
2642 filter = bnxt_get_unused_filter(bp);
2643 if (filter == NULL) {
2645 "Not enough resources for a new flow.\n");
2649 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2652 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2654 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2655 vnic = &bp->vnic_info[0];
2657 vnic = &bp->vnic_info[fdir->action.rx_queue];
2659 match = bnxt_match_fdir(bp, filter, &mvnic);
2660 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2661 if (match->dst_id == vnic->fw_vnic_id) {
2662 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2666 match->dst_id = vnic->fw_vnic_id;
2667 ret = bnxt_hwrm_set_ntuple_filter(bp,
2670 STAILQ_REMOVE(&mvnic->filter, match,
2671 bnxt_filter_info, next);
2672 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2674 "Filter with matching pattern exist\n");
2676 "Updated it to new destination q\n");
2680 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2681 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2686 if (filter_op == RTE_ETH_FILTER_ADD) {
2687 ret = bnxt_hwrm_set_ntuple_filter(bp,
2692 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2694 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2695 STAILQ_REMOVE(&vnic->filter, match,
2696 bnxt_filter_info, next);
2697 bnxt_free_filter(bp, match);
2698 filter->fw_l2_filter_id = -1;
2699 bnxt_free_filter(bp, filter);
2702 case RTE_ETH_FILTER_FLUSH:
2703 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2704 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2706 STAILQ_FOREACH(filter, &vnic->filter, next) {
2707 if (filter->filter_type ==
2708 HWRM_CFA_NTUPLE_FILTER) {
2710 bnxt_hwrm_clear_ntuple_filter(bp,
2712 STAILQ_REMOVE(&vnic->filter, filter,
2713 bnxt_filter_info, next);
2718 case RTE_ETH_FILTER_UPDATE:
2719 case RTE_ETH_FILTER_STATS:
2720 case RTE_ETH_FILTER_INFO:
2721 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2724 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2731 filter->fw_l2_filter_id = -1;
2732 bnxt_free_filter(bp, filter);
2737 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2738 enum rte_filter_type filter_type,
2739 enum rte_filter_op filter_op, void *arg)
2743 switch (filter_type) {
2744 case RTE_ETH_FILTER_TUNNEL:
2746 "filter type: %d: To be implemented\n", filter_type);
2748 case RTE_ETH_FILTER_FDIR:
2749 ret = bnxt_fdir_filter(dev, filter_op, arg);
2751 case RTE_ETH_FILTER_NTUPLE:
2752 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2754 case RTE_ETH_FILTER_ETHERTYPE:
2755 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2757 case RTE_ETH_FILTER_GENERIC:
2758 if (filter_op != RTE_ETH_FILTER_GET)
2760 *(const void **)arg = &bnxt_flow_ops;
2764 "Filter type (%d) not supported", filter_type);
2771 static const uint32_t *
2772 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2774 static const uint32_t ptypes[] = {
2775 RTE_PTYPE_L2_ETHER_VLAN,
2776 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2777 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2781 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2782 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2783 RTE_PTYPE_INNER_L4_ICMP,
2784 RTE_PTYPE_INNER_L4_TCP,
2785 RTE_PTYPE_INNER_L4_UDP,
2789 if (!dev->rx_pkt_burst)
2795 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2798 uint32_t reg_base = *reg_arr & 0xfffff000;
2802 for (i = 0; i < count; i++) {
2803 if ((reg_arr[i] & 0xfffff000) != reg_base)
2806 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2807 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
2811 static int bnxt_map_ptp_regs(struct bnxt *bp)
2813 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2817 reg_arr = ptp->rx_regs;
2818 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2822 reg_arr = ptp->tx_regs;
2823 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2827 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2828 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2830 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2831 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2836 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2838 rte_write32(0, (uint8_t *)bp->bar0 +
2839 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
2840 rte_write32(0, (uint8_t *)bp->bar0 +
2841 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
2844 static uint64_t bnxt_cc_read(struct bnxt *bp)
2848 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2849 BNXT_GRCPF_REG_SYNC_TIME));
2850 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2851 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2855 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2857 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2860 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2861 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2862 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2865 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2866 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2867 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2868 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2869 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2870 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2875 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2877 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2878 struct bnxt_pf_info *pf = &bp->pf;
2885 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2886 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2887 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2890 port_id = pf->port_id;
2891 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2892 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
2894 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2895 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2896 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2897 /* bnxt_clr_rx_ts(bp); TBD */
2901 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2902 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2903 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2904 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2910 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2913 struct bnxt *bp = dev->data->dev_private;
2914 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2919 ns = rte_timespec_to_ns(ts);
2920 /* Set the timecounters to a new value. */
2927 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2929 uint64_t ns, systime_cycles;
2930 struct bnxt *bp = dev->data->dev_private;
2931 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2936 systime_cycles = bnxt_cc_read(bp);
2937 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
2938 *ts = rte_ns_to_timespec(ns);
2943 bnxt_timesync_enable(struct rte_eth_dev *dev)
2945 struct bnxt *bp = dev->data->dev_private;
2946 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2953 ptp->tx_tstamp_en = 1;
2954 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
2956 if (!bnxt_hwrm_ptp_cfg(bp))
2957 bnxt_map_ptp_regs(bp);
2959 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
2960 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2961 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2963 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2964 ptp->tc.cc_shift = shift;
2965 ptp->tc.nsec_mask = (1ULL << shift) - 1;
2967 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2968 ptp->rx_tstamp_tc.cc_shift = shift;
2969 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2971 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2972 ptp->tx_tstamp_tc.cc_shift = shift;
2973 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2979 bnxt_timesync_disable(struct rte_eth_dev *dev)
2981 struct bnxt *bp = dev->data->dev_private;
2982 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2988 ptp->tx_tstamp_en = 0;
2991 bnxt_hwrm_ptp_cfg(bp);
2993 bnxt_unmap_ptp_regs(bp);
2999 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3000 struct timespec *timestamp,
3001 uint32_t flags __rte_unused)
3003 struct bnxt *bp = dev->data->dev_private;
3004 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3005 uint64_t rx_tstamp_cycles = 0;
3011 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3012 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3013 *timestamp = rte_ns_to_timespec(ns);
3018 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3019 struct timespec *timestamp)
3021 struct bnxt *bp = dev->data->dev_private;
3022 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3023 uint64_t tx_tstamp_cycles = 0;
3029 bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3030 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3031 *timestamp = rte_ns_to_timespec(ns);
3037 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3039 struct bnxt *bp = dev->data->dev_private;
3040 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3045 ptp->tc.nsec += delta;
3051 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3053 struct bnxt *bp = dev->data->dev_private;
3055 uint32_t dir_entries;
3056 uint32_t entry_length;
3058 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3059 bp->pdev->addr.domain, bp->pdev->addr.bus,
3060 bp->pdev->addr.devid, bp->pdev->addr.function);
3062 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3066 return dir_entries * entry_length;
3070 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3071 struct rte_dev_eeprom_info *in_eeprom)
3073 struct bnxt *bp = dev->data->dev_private;
3077 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3078 "len = %d\n", bp->pdev->addr.domain,
3079 bp->pdev->addr.bus, bp->pdev->addr.devid,
3080 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3082 if (in_eeprom->offset == 0) /* special offset value to get directory */
3083 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3086 index = in_eeprom->offset >> 24;
3087 offset = in_eeprom->offset & 0xffffff;
3090 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3091 in_eeprom->length, in_eeprom->data);
3096 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3099 case BNX_DIR_TYPE_CHIMP_PATCH:
3100 case BNX_DIR_TYPE_BOOTCODE:
3101 case BNX_DIR_TYPE_BOOTCODE_2:
3102 case BNX_DIR_TYPE_APE_FW:
3103 case BNX_DIR_TYPE_APE_PATCH:
3104 case BNX_DIR_TYPE_KONG_FW:
3105 case BNX_DIR_TYPE_KONG_PATCH:
3106 case BNX_DIR_TYPE_BONO_FW:
3107 case BNX_DIR_TYPE_BONO_PATCH:
3115 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3118 case BNX_DIR_TYPE_AVS:
3119 case BNX_DIR_TYPE_EXP_ROM_MBA:
3120 case BNX_DIR_TYPE_PCIE:
3121 case BNX_DIR_TYPE_TSCF_UCODE:
3122 case BNX_DIR_TYPE_EXT_PHY:
3123 case BNX_DIR_TYPE_CCM:
3124 case BNX_DIR_TYPE_ISCSI_BOOT:
3125 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3126 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3134 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3136 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3137 bnxt_dir_type_is_other_exec_format(dir_type);
3141 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3142 struct rte_dev_eeprom_info *in_eeprom)
3144 struct bnxt *bp = dev->data->dev_private;
3145 uint8_t index, dir_op;
3146 uint16_t type, ext, ordinal, attr;
3148 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3149 "len = %d\n", bp->pdev->addr.domain,
3150 bp->pdev->addr.bus, bp->pdev->addr.devid,
3151 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3154 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3158 type = in_eeprom->magic >> 16;
3160 if (type == 0xffff) { /* special value for directory operations */
3161 index = in_eeprom->magic & 0xff;
3162 dir_op = in_eeprom->magic >> 8;
3166 case 0x0e: /* erase */
3167 if (in_eeprom->offset != ~in_eeprom->magic)
3169 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3175 /* Create or re-write an NVM item: */
3176 if (bnxt_dir_type_is_executable(type) == true)
3178 ext = in_eeprom->magic & 0xffff;
3179 ordinal = in_eeprom->offset >> 16;
3180 attr = in_eeprom->offset & 0xffff;
3182 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3183 in_eeprom->data, in_eeprom->length);
3191 static const struct eth_dev_ops bnxt_dev_ops = {
3192 .dev_infos_get = bnxt_dev_info_get_op,
3193 .dev_close = bnxt_dev_close_op,
3194 .dev_configure = bnxt_dev_configure_op,
3195 .dev_start = bnxt_dev_start_op,
3196 .dev_stop = bnxt_dev_stop_op,
3197 .dev_set_link_up = bnxt_dev_set_link_up_op,
3198 .dev_set_link_down = bnxt_dev_set_link_down_op,
3199 .stats_get = bnxt_stats_get_op,
3200 .stats_reset = bnxt_stats_reset_op,
3201 .rx_queue_setup = bnxt_rx_queue_setup_op,
3202 .rx_queue_release = bnxt_rx_queue_release_op,
3203 .tx_queue_setup = bnxt_tx_queue_setup_op,
3204 .tx_queue_release = bnxt_tx_queue_release_op,
3205 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3206 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3207 .reta_update = bnxt_reta_update_op,
3208 .reta_query = bnxt_reta_query_op,
3209 .rss_hash_update = bnxt_rss_hash_update_op,
3210 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3211 .link_update = bnxt_link_update_op,
3212 .promiscuous_enable = bnxt_promiscuous_enable_op,
3213 .promiscuous_disable = bnxt_promiscuous_disable_op,
3214 .allmulticast_enable = bnxt_allmulticast_enable_op,
3215 .allmulticast_disable = bnxt_allmulticast_disable_op,
3216 .mac_addr_add = bnxt_mac_addr_add_op,
3217 .mac_addr_remove = bnxt_mac_addr_remove_op,
3218 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3219 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3220 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3221 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3222 .vlan_filter_set = bnxt_vlan_filter_set_op,
3223 .vlan_offload_set = bnxt_vlan_offload_set_op,
3224 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3225 .mtu_set = bnxt_mtu_set_op,
3226 .mac_addr_set = bnxt_set_default_mac_addr_op,
3227 .xstats_get = bnxt_dev_xstats_get_op,
3228 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3229 .xstats_reset = bnxt_dev_xstats_reset_op,
3230 .fw_version_get = bnxt_fw_version_get,
3231 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3232 .rxq_info_get = bnxt_rxq_info_get_op,
3233 .txq_info_get = bnxt_txq_info_get_op,
3234 .dev_led_on = bnxt_dev_led_on_op,
3235 .dev_led_off = bnxt_dev_led_off_op,
3236 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3237 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3238 .rx_queue_count = bnxt_rx_queue_count_op,
3239 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3240 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3241 .rx_queue_start = bnxt_rx_queue_start,
3242 .rx_queue_stop = bnxt_rx_queue_stop,
3243 .tx_queue_start = bnxt_tx_queue_start,
3244 .tx_queue_stop = bnxt_tx_queue_stop,
3245 .filter_ctrl = bnxt_filter_ctrl_op,
3246 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3247 .get_eeprom_length = bnxt_get_eeprom_length_op,
3248 .get_eeprom = bnxt_get_eeprom_op,
3249 .set_eeprom = bnxt_set_eeprom_op,
3250 .timesync_enable = bnxt_timesync_enable,
3251 .timesync_disable = bnxt_timesync_disable,
3252 .timesync_read_time = bnxt_timesync_read_time,
3253 .timesync_write_time = bnxt_timesync_write_time,
3254 .timesync_adjust_time = bnxt_timesync_adjust_time,
3255 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3256 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3259 static bool bnxt_vf_pciid(uint16_t id)
3261 if (id == BROADCOM_DEV_ID_57304_VF ||
3262 id == BROADCOM_DEV_ID_57406_VF ||
3263 id == BROADCOM_DEV_ID_5731X_VF ||
3264 id == BROADCOM_DEV_ID_5741X_VF ||
3265 id == BROADCOM_DEV_ID_57414_VF ||
3266 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3267 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3268 id == BROADCOM_DEV_ID_58802_VF)
3273 bool bnxt_stratus_device(struct bnxt *bp)
3275 uint16_t id = bp->pdev->id.device_id;
3277 if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3278 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3279 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3284 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3286 struct bnxt *bp = eth_dev->data->dev_private;
3287 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3290 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3291 if (!pci_dev->mem_resource[0].addr) {
3293 "Cannot find PCI device base address, aborting\n");
3295 goto init_err_disable;
3298 bp->eth_dev = eth_dev;
3301 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3303 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3305 goto init_err_release;
3308 if (!pci_dev->mem_resource[2].addr) {
3310 "Cannot find PCI device BAR 2 address, aborting\n");
3312 goto init_err_release;
3314 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3322 if (bp->doorbell_base)
3323 bp->doorbell_base = NULL;
3331 #define ALLOW_FUNC(x) \
3333 typeof(x) arg = (x); \
3334 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3335 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3338 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3340 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3341 char mz_name[RTE_MEMZONE_NAMESIZE];
3342 const struct rte_memzone *mz = NULL;
3343 static int version_printed;
3344 uint32_t total_alloc_len;
3345 rte_iova_t mz_phys_addr;
3349 if (version_printed++ == 0)
3350 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3352 rte_eth_copy_pci_info(eth_dev, pci_dev);
3354 bp = eth_dev->data->dev_private;
3356 bp->dev_stopped = 1;
3358 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3361 if (bnxt_vf_pciid(pci_dev->id.device_id))
3362 bp->flags |= BNXT_FLAG_VF;
3364 rc = bnxt_init_board(eth_dev);
3367 "Board initialization failed rc: %x\n", rc);
3371 eth_dev->dev_ops = &bnxt_dev_ops;
3372 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3373 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3374 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3377 if (pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3378 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3379 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3380 pci_dev->addr.bus, pci_dev->addr.devid,
3381 pci_dev->addr.function, "rx_port_stats");
3382 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3383 mz = rte_memzone_lookup(mz_name);
3384 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3385 sizeof(struct rx_port_stats) +
3386 sizeof(struct rx_port_stats_ext) +
3389 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3392 RTE_MEMZONE_SIZE_HINT_ONLY |
3393 RTE_MEMZONE_IOVA_CONTIG);
3397 memset(mz->addr, 0, mz->len);
3398 mz_phys_addr = mz->iova;
3399 if ((unsigned long)mz->addr == mz_phys_addr) {
3401 "Memzone physical address same as virtual using rte_mem_virt2iova()\n");
3402 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3403 if (mz_phys_addr == 0) {
3405 "unable to map address to physical memory\n");
3410 bp->rx_mem_zone = (const void *)mz;
3411 bp->hw_rx_port_stats = mz->addr;
3412 bp->hw_rx_port_stats_map = mz_phys_addr;
3414 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3415 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3416 pci_dev->addr.bus, pci_dev->addr.devid,
3417 pci_dev->addr.function, "tx_port_stats");
3418 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3419 mz = rte_memzone_lookup(mz_name);
3420 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3421 sizeof(struct tx_port_stats) +
3422 sizeof(struct tx_port_stats_ext) +
3425 mz = rte_memzone_reserve(mz_name,
3429 RTE_MEMZONE_SIZE_HINT_ONLY |
3430 RTE_MEMZONE_IOVA_CONTIG);
3434 memset(mz->addr, 0, mz->len);
3435 mz_phys_addr = mz->iova;
3436 if ((unsigned long)mz->addr == mz_phys_addr) {
3437 PMD_DRV_LOG(WARNING,
3438 "Memzone physical address same as virtual.\n");
3439 PMD_DRV_LOG(WARNING,
3440 "Using rte_mem_virt2iova()\n");
3441 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3442 if (mz_phys_addr == 0) {
3444 "unable to map address to physical memory\n");
3449 bp->tx_mem_zone = (const void *)mz;
3450 bp->hw_tx_port_stats = mz->addr;
3451 bp->hw_tx_port_stats_map = mz_phys_addr;
3453 bp->flags |= BNXT_FLAG_PORT_STATS;
3455 /* Display extended statistics if FW supports it */
3456 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
3457 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0)
3458 goto skip_ext_stats;
3460 bp->hw_rx_port_stats_ext = (void *)
3461 (bp->hw_rx_port_stats + sizeof(struct rx_port_stats));
3462 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
3463 sizeof(struct rx_port_stats);
3464 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
3467 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2) {
3468 bp->hw_tx_port_stats_ext = (void *)
3469 (bp->hw_tx_port_stats + sizeof(struct tx_port_stats));
3470 bp->hw_tx_port_stats_ext_map =
3471 bp->hw_tx_port_stats_map +
3472 sizeof(struct tx_port_stats);
3473 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
3478 rc = bnxt_alloc_hwrm_resources(bp);
3481 "hwrm resource allocation failure rc: %x\n", rc);
3484 rc = bnxt_hwrm_ver_get(bp);
3487 rc = bnxt_hwrm_queue_qportcfg(bp);
3489 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3493 rc = bnxt_hwrm_func_qcfg(bp);
3495 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3499 /* Get the MAX capabilities for this function */
3500 rc = bnxt_hwrm_func_qcaps(bp);
3502 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3505 if (bp->max_tx_rings == 0) {
3506 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3510 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3511 RTE_ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3512 if (eth_dev->data->mac_addrs == NULL) {
3514 "Failed to alloc %u bytes needed to store MAC addr tbl",
3515 RTE_ETHER_ADDR_LEN * bp->max_l2_ctx);
3520 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
3522 "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
3523 bp->dflt_mac_addr[0], bp->dflt_mac_addr[1],
3524 bp->dflt_mac_addr[2], bp->dflt_mac_addr[3],
3525 bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]);
3529 /* Copy the permanent MAC from the qcap response address now. */
3530 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3531 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
3533 if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3534 /* 1 ring is for default completion ring */
3535 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3540 bp->grp_info = rte_zmalloc("bnxt_grp_info",
3541 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3542 if (!bp->grp_info) {
3544 "Failed to alloc %zu bytes to store group info table\n",
3545 sizeof(*bp->grp_info) * bp->max_ring_grps);
3550 /* Forward all requests if firmware is new enough */
3551 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3552 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3553 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3554 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3556 PMD_DRV_LOG(WARNING,
3557 "Firmware too old for VF mailbox functionality\n");
3558 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3562 * The following are used for driver cleanup. If we disallow these,
3563 * VF drivers can't clean up cleanly.
3565 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3566 ALLOW_FUNC(HWRM_VNIC_FREE);
3567 ALLOW_FUNC(HWRM_RING_FREE);
3568 ALLOW_FUNC(HWRM_RING_GRP_FREE);
3569 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3570 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3571 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3572 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3573 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3574 rc = bnxt_hwrm_func_driver_register(bp);
3577 "Failed to register driver");
3583 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3584 pci_dev->mem_resource[0].phys_addr,
3585 pci_dev->mem_resource[0].addr);
3587 rc = bnxt_hwrm_func_reset(bp);
3589 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3595 //if (bp->pf.active_vfs) {
3596 // TODO: Deallocate VF resources?
3598 if (bp->pdev->max_vfs) {
3599 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3601 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3605 rc = bnxt_hwrm_allocate_pf_only(bp);
3608 "Failed to allocate PF resources\n");
3614 bnxt_hwrm_port_led_qcaps(bp);
3616 rc = bnxt_setup_int(bp);
3620 rc = bnxt_alloc_mem(bp);
3622 goto error_free_int;
3624 rc = bnxt_request_int(bp);
3626 goto error_free_int;
3628 bnxt_enable_int(bp);
3634 bnxt_disable_int(bp);
3635 bnxt_hwrm_func_buf_unrgtr(bp);
3639 bnxt_dev_uninit(eth_dev);
3645 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
3647 struct bnxt *bp = eth_dev->data->dev_private;
3650 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3653 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
3654 bnxt_disable_int(bp);
3657 if (bp->grp_info != NULL) {
3658 rte_free(bp->grp_info);
3659 bp->grp_info = NULL;
3661 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3662 bnxt_free_hwrm_resources(bp);
3664 if (bp->tx_mem_zone) {
3665 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3666 bp->tx_mem_zone = NULL;
3669 if (bp->rx_mem_zone) {
3670 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3671 bp->rx_mem_zone = NULL;
3674 if (bp->dev_stopped == 0)
3675 bnxt_dev_close_op(eth_dev);
3677 rte_free(bp->pf.vf_info);
3678 eth_dev->dev_ops = NULL;
3679 eth_dev->rx_pkt_burst = NULL;
3680 eth_dev->tx_pkt_burst = NULL;
3685 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3686 struct rte_pci_device *pci_dev)
3688 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
3692 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
3694 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3695 return rte_eth_dev_pci_generic_remove(pci_dev,
3698 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
3701 static struct rte_pci_driver bnxt_rte_pmd = {
3702 .id_table = bnxt_pci_id_map,
3703 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
3704 RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_IOVA_AS_VA,
3705 .probe = bnxt_pci_probe,
3706 .remove = bnxt_pci_remove,
3710 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
3712 if (strcmp(dev->device->driver->name, drv->driver.name))
3718 bool is_bnxt_supported(struct rte_eth_dev *dev)
3720 return is_device_supported(dev, &bnxt_rte_pmd);
3723 RTE_INIT(bnxt_init_log)
3725 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
3726 if (bnxt_logtype_driver >= 0)
3727 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
3730 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
3731 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
3732 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");