1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
18 #include "bnxt_filter.h"
19 #include "bnxt_hwrm.h"
21 #include "bnxt_reps.h"
22 #include "bnxt_ring.h"
25 #include "bnxt_stats.h"
28 #include "bnxt_vnic.h"
29 #include "hsi_struct_def_dpdk.h"
30 #include "bnxt_nvm_defs.h"
31 #include "bnxt_tf_common.h"
32 #include "ulp_flow_db.h"
34 #define DRV_MODULE_NAME "bnxt"
35 static const char bnxt_version[] =
36 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
39 * The set of PCI devices this driver supports
41 static const struct rte_pci_id bnxt_pci_id_map[] = {
42 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
43 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
95 { .vendor_id = 0, /* sentinel */ },
98 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
99 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
100 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
101 #define BNXT_DEVARG_REPRESENTOR "representor"
103 static const char *const bnxt_dev_args[] = {
104 BNXT_DEVARG_REPRESENTOR,
106 BNXT_DEVARG_FLOW_XSTAT,
107 BNXT_DEVARG_MAX_NUM_KFLOWS,
112 * truflow == false to disable the feature
113 * truflow == true to enable the feature
115 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
118 * flow_xstat == false to disable the feature
119 * flow_xstat == true to enable the feature
121 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
124 * max_num_kflows must be >= 32
125 * and must be a power-of-2 supported value
126 * return: 1 -> invalid
129 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
131 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
136 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
137 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
138 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
139 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
140 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
141 static int bnxt_restore_vlan_filters(struct bnxt *bp);
142 static void bnxt_dev_recover(void *arg);
143 static void bnxt_free_error_recovery_info(struct bnxt *bp);
144 static void bnxt_free_rep_info(struct bnxt *bp);
146 int is_bnxt_in_error(struct bnxt *bp)
148 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
150 if (bp->flags & BNXT_FLAG_FW_RESET)
156 /***********************/
159 * High level utility functions
162 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
164 if (!BNXT_CHIP_THOR(bp))
167 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
168 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
169 BNXT_RSS_ENTRIES_PER_CTX_THOR;
172 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
174 if (!BNXT_CHIP_THOR(bp))
175 return HW_HASH_INDEX_SIZE;
177 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
180 static void bnxt_free_parent_info(struct bnxt *bp)
182 rte_free(bp->parent);
185 static void bnxt_free_pf_info(struct bnxt *bp)
190 static void bnxt_free_link_info(struct bnxt *bp)
192 rte_free(bp->link_info);
195 static void bnxt_free_leds_info(struct bnxt *bp)
201 static void bnxt_free_flow_stats_info(struct bnxt *bp)
203 rte_free(bp->flow_stat);
204 bp->flow_stat = NULL;
207 static void bnxt_free_cos_queues(struct bnxt *bp)
209 rte_free(bp->rx_cos_queue);
210 rte_free(bp->tx_cos_queue);
213 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
215 bnxt_free_filter_mem(bp);
216 bnxt_free_vnic_attributes(bp);
217 bnxt_free_vnic_mem(bp);
219 /* tx/rx rings are configured as part of *_queue_setup callbacks.
220 * If the number of rings change across fw update,
221 * we don't have much choice except to warn the user.
225 bnxt_free_tx_rings(bp);
226 bnxt_free_rx_rings(bp);
228 bnxt_free_async_cp_ring(bp);
229 bnxt_free_rxtx_nq_ring(bp);
231 rte_free(bp->grp_info);
235 static int bnxt_alloc_parent_info(struct bnxt *bp)
237 bp->parent = rte_zmalloc("bnxt_parent_info",
238 sizeof(struct bnxt_parent_info), 0);
239 if (bp->parent == NULL)
245 static int bnxt_alloc_pf_info(struct bnxt *bp)
247 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
254 static int bnxt_alloc_link_info(struct bnxt *bp)
257 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
258 if (bp->link_info == NULL)
264 static int bnxt_alloc_leds_info(struct bnxt *bp)
266 bp->leds = rte_zmalloc("bnxt_leds",
267 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
269 if (bp->leds == NULL)
275 static int bnxt_alloc_cos_queues(struct bnxt *bp)
278 rte_zmalloc("bnxt_rx_cosq",
279 BNXT_COS_QUEUE_COUNT *
280 sizeof(struct bnxt_cos_queue_info),
282 if (bp->rx_cos_queue == NULL)
286 rte_zmalloc("bnxt_tx_cosq",
287 BNXT_COS_QUEUE_COUNT *
288 sizeof(struct bnxt_cos_queue_info),
290 if (bp->tx_cos_queue == NULL)
296 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
298 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
299 sizeof(struct bnxt_flow_stat_info), 0);
300 if (bp->flow_stat == NULL)
306 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
310 rc = bnxt_alloc_ring_grps(bp);
314 rc = bnxt_alloc_async_ring_struct(bp);
318 rc = bnxt_alloc_vnic_mem(bp);
322 rc = bnxt_alloc_vnic_attributes(bp);
326 rc = bnxt_alloc_filter_mem(bp);
330 rc = bnxt_alloc_async_cp_ring(bp);
334 rc = bnxt_alloc_rxtx_nq_ring(bp);
338 if (BNXT_FLOW_XSTATS_EN(bp)) {
339 rc = bnxt_alloc_flow_stats_info(bp);
347 bnxt_free_mem(bp, reconfig);
351 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
353 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
354 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
355 uint64_t rx_offloads = dev_conf->rxmode.offloads;
356 struct bnxt_rx_queue *rxq;
360 rc = bnxt_vnic_grp_alloc(bp, vnic);
364 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
365 vnic_id, vnic, vnic->fw_grp_ids);
367 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
371 /* Alloc RSS context only if RSS mode is enabled */
372 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
373 int j, nr_ctxs = bnxt_rss_ctxts(bp);
376 for (j = 0; j < nr_ctxs; j++) {
377 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
383 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
387 vnic->num_lb_ctxts = nr_ctxs;
391 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
392 * setting is not available at this time, it will not be
393 * configured correctly in the CFA.
395 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
396 vnic->vlan_strip = true;
398 vnic->vlan_strip = false;
400 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
404 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
408 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
409 rxq = bp->eth_dev->data->rx_queues[j];
412 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
413 j, rxq->vnic, rxq->vnic->fw_grp_ids);
415 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
416 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
418 vnic->rx_queue_cnt++;
421 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
423 rc = bnxt_vnic_rss_configure(bp, vnic);
427 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
429 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
430 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
432 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
436 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
441 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
445 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
446 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
451 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
452 " rx_fc_in_tbl.ctx_id = %d\n",
453 bp->flow_stat->rx_fc_in_tbl.va,
454 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
455 bp->flow_stat->rx_fc_in_tbl.ctx_id);
457 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
458 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
463 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
464 " rx_fc_out_tbl.ctx_id = %d\n",
465 bp->flow_stat->rx_fc_out_tbl.va,
466 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
467 bp->flow_stat->rx_fc_out_tbl.ctx_id);
469 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
470 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
475 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
476 " tx_fc_in_tbl.ctx_id = %d\n",
477 bp->flow_stat->tx_fc_in_tbl.va,
478 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
479 bp->flow_stat->tx_fc_in_tbl.ctx_id);
481 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
482 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
487 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
488 " tx_fc_out_tbl.ctx_id = %d\n",
489 bp->flow_stat->tx_fc_out_tbl.va,
490 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
491 bp->flow_stat->tx_fc_out_tbl.ctx_id);
493 memset(bp->flow_stat->rx_fc_out_tbl.va,
495 bp->flow_stat->rx_fc_out_tbl.size);
496 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
497 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
498 bp->flow_stat->rx_fc_out_tbl.ctx_id,
499 bp->flow_stat->max_fc,
504 memset(bp->flow_stat->tx_fc_out_tbl.va,
506 bp->flow_stat->tx_fc_out_tbl.size);
507 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
508 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
509 bp->flow_stat->tx_fc_out_tbl.ctx_id,
510 bp->flow_stat->max_fc,
516 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
517 struct bnxt_ctx_mem_buf_info *ctx)
522 ctx->va = rte_zmalloc(type, size, 0);
525 rte_mem_lock_page(ctx->va);
527 ctx->dma = rte_mem_virt2iova(ctx->va);
528 if (ctx->dma == RTE_BAD_IOVA)
534 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
536 struct rte_pci_device *pdev = bp->pdev;
537 char type[RTE_MEMZONE_NAMESIZE];
541 max_fc = bp->flow_stat->max_fc;
543 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
544 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
545 /* 4 bytes for each counter-id */
546 rc = bnxt_alloc_ctx_mem_buf(type,
548 &bp->flow_stat->rx_fc_in_tbl);
552 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
553 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
554 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
555 rc = bnxt_alloc_ctx_mem_buf(type,
557 &bp->flow_stat->rx_fc_out_tbl);
561 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
562 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
563 /* 4 bytes for each counter-id */
564 rc = bnxt_alloc_ctx_mem_buf(type,
566 &bp->flow_stat->tx_fc_in_tbl);
570 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
571 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
572 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
573 rc = bnxt_alloc_ctx_mem_buf(type,
575 &bp->flow_stat->tx_fc_out_tbl);
579 rc = bnxt_register_fc_ctx_mem(bp);
584 static int bnxt_init_ctx_mem(struct bnxt *bp)
588 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
589 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
590 !BNXT_FLOW_XSTATS_EN(bp))
593 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
597 rc = bnxt_init_fc_ctx_mem(bp);
602 static int bnxt_init_chip(struct bnxt *bp)
604 struct rte_eth_link new;
605 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
606 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
607 uint32_t intr_vector = 0;
608 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
609 uint32_t vec = BNXT_MISC_VEC_ID;
613 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
614 bp->eth_dev->data->dev_conf.rxmode.offloads |=
615 DEV_RX_OFFLOAD_JUMBO_FRAME;
616 bp->flags |= BNXT_FLAG_JUMBO;
618 bp->eth_dev->data->dev_conf.rxmode.offloads &=
619 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
620 bp->flags &= ~BNXT_FLAG_JUMBO;
623 /* THOR does not support ring groups.
624 * But we will use the array to save RSS context IDs.
626 if (BNXT_CHIP_THOR(bp))
627 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
629 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
631 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
635 rc = bnxt_alloc_hwrm_rings(bp);
637 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
641 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
643 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
647 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
650 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
651 if (bp->rx_cos_queue[i].id != 0xff) {
652 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
656 "Num pools more than FW profile\n");
660 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
666 rc = bnxt_mq_rx_configure(bp);
668 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
672 /* VNIC configuration */
673 for (i = 0; i < bp->nr_vnics; i++) {
674 rc = bnxt_setup_one_vnic(bp, i);
679 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
682 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
686 /* check and configure queue intr-vector mapping */
687 if ((rte_intr_cap_multiple(intr_handle) ||
688 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
689 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
690 intr_vector = bp->eth_dev->data->nb_rx_queues;
691 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
692 if (intr_vector > bp->rx_cp_nr_rings) {
693 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
697 rc = rte_intr_efd_enable(intr_handle, intr_vector);
702 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
703 intr_handle->intr_vec =
704 rte_zmalloc("intr_vec",
705 bp->eth_dev->data->nb_rx_queues *
707 if (intr_handle->intr_vec == NULL) {
708 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
709 " intr_vec", bp->eth_dev->data->nb_rx_queues);
713 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
714 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
715 intr_handle->intr_vec, intr_handle->nb_efd,
716 intr_handle->max_intr);
717 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
719 intr_handle->intr_vec[queue_id] =
720 vec + BNXT_RX_VEC_START;
721 if (vec < base + intr_handle->nb_efd - 1)
726 /* enable uio/vfio intr/eventfd mapping */
727 rc = rte_intr_enable(intr_handle);
728 #ifndef RTE_EXEC_ENV_FREEBSD
729 /* In FreeBSD OS, nic_uio driver does not support interrupts */
734 rc = bnxt_get_hwrm_link_config(bp, &new);
736 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
740 if (!bp->link_info->link_up) {
741 rc = bnxt_set_hwrm_link_config(bp, true);
744 "HWRM link config failure rc: %x\n", rc);
748 bnxt_print_link_info(bp->eth_dev);
750 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
752 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
757 rte_free(intr_handle->intr_vec);
759 rte_intr_efd_disable(intr_handle);
761 /* Some of the error status returned by FW may not be from errno.h */
768 static int bnxt_shutdown_nic(struct bnxt *bp)
770 bnxt_free_all_hwrm_resources(bp);
771 bnxt_free_all_filters(bp);
772 bnxt_free_all_vnics(bp);
777 * Device configuration and status function
780 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
782 uint32_t link_speed = bp->link_info->support_speeds;
783 uint32_t speed_capa = 0;
785 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
786 speed_capa |= ETH_LINK_SPEED_100M;
787 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
788 speed_capa |= ETH_LINK_SPEED_100M_HD;
789 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
790 speed_capa |= ETH_LINK_SPEED_1G;
791 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
792 speed_capa |= ETH_LINK_SPEED_2_5G;
793 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
794 speed_capa |= ETH_LINK_SPEED_10G;
795 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
796 speed_capa |= ETH_LINK_SPEED_20G;
797 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
798 speed_capa |= ETH_LINK_SPEED_25G;
799 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
800 speed_capa |= ETH_LINK_SPEED_40G;
801 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
802 speed_capa |= ETH_LINK_SPEED_50G;
803 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
804 speed_capa |= ETH_LINK_SPEED_100G;
805 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
806 speed_capa |= ETH_LINK_SPEED_200G;
808 if (bp->link_info->auto_mode ==
809 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
810 speed_capa |= ETH_LINK_SPEED_FIXED;
812 speed_capa |= ETH_LINK_SPEED_AUTONEG;
817 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
818 struct rte_eth_dev_info *dev_info)
820 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
821 struct bnxt *bp = eth_dev->data->dev_private;
822 uint16_t max_vnics, i, j, vpool, vrxq;
823 unsigned int max_rx_rings;
826 rc = is_bnxt_in_error(bp);
831 dev_info->max_mac_addrs = bp->max_l2_ctx;
832 dev_info->max_hash_mac_addrs = 0;
834 /* PF/VF specifics */
836 dev_info->max_vfs = pdev->max_vfs;
838 max_rx_rings = BNXT_MAX_RINGS(bp);
839 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
840 dev_info->max_rx_queues = max_rx_rings;
841 dev_info->max_tx_queues = max_rx_rings;
842 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
843 dev_info->hash_key_size = 40;
844 max_vnics = bp->max_vnics;
847 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
848 dev_info->max_mtu = BNXT_MAX_MTU;
850 /* Fast path specifics */
851 dev_info->min_rx_bufsize = 1;
852 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
854 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
855 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
856 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
857 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
858 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
860 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
863 dev_info->default_rxconf = (struct rte_eth_rxconf) {
869 .rx_free_thresh = 32,
870 /* If no descriptors available, pkts are dropped by default */
874 dev_info->default_txconf = (struct rte_eth_txconf) {
880 .tx_free_thresh = 32,
883 eth_dev->data->dev_conf.intr_conf.lsc = 1;
885 eth_dev->data->dev_conf.intr_conf.rxq = 1;
886 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
887 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
888 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
889 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
894 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
895 * need further investigation.
899 vpool = 64; /* ETH_64_POOLS */
900 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
901 for (i = 0; i < 4; vpool >>= 1, i++) {
902 if (max_vnics > vpool) {
903 for (j = 0; j < 5; vrxq >>= 1, j++) {
904 if (dev_info->max_rx_queues > vrxq) {
910 /* Not enough resources to support VMDq */
914 /* Not enough resources to support VMDq */
918 dev_info->max_vmdq_pools = vpool;
919 dev_info->vmdq_queue_num = vrxq;
921 dev_info->vmdq_pool_base = 0;
922 dev_info->vmdq_queue_base = 0;
927 /* Configure the device based on the configuration provided */
928 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
930 struct bnxt *bp = eth_dev->data->dev_private;
931 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
934 bp->rx_queues = (void *)eth_dev->data->rx_queues;
935 bp->tx_queues = (void *)eth_dev->data->tx_queues;
936 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
937 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
939 rc = is_bnxt_in_error(bp);
943 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
944 rc = bnxt_hwrm_check_vf_rings(bp);
946 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
950 /* If a resource has already been allocated - in this case
951 * it is the async completion ring, free it. Reallocate it after
952 * resource reservation. This will ensure the resource counts
953 * are calculated correctly.
956 pthread_mutex_lock(&bp->def_cp_lock);
958 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
959 bnxt_disable_int(bp);
960 bnxt_free_cp_ring(bp, bp->async_cp_ring);
963 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
965 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
966 pthread_mutex_unlock(&bp->def_cp_lock);
970 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
971 rc = bnxt_alloc_async_cp_ring(bp);
973 pthread_mutex_unlock(&bp->def_cp_lock);
979 pthread_mutex_unlock(&bp->def_cp_lock);
981 /* legacy driver needs to get updated values */
982 rc = bnxt_hwrm_func_qcaps(bp);
984 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
989 /* Inherit new configurations */
990 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
991 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
992 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
993 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
994 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
998 if (BNXT_HAS_RING_GRPS(bp) &&
999 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1000 goto resource_error;
1002 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1003 bp->max_vnics < eth_dev->data->nb_rx_queues)
1004 goto resource_error;
1006 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1007 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1009 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1010 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1011 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1013 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1014 eth_dev->data->mtu =
1015 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1016 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1018 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1024 "Insufficient resources to support requested config\n");
1026 "Num Queues Requested: Tx %d, Rx %d\n",
1027 eth_dev->data->nb_tx_queues,
1028 eth_dev->data->nb_rx_queues);
1030 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1031 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1032 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1036 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1038 struct rte_eth_link *link = ð_dev->data->dev_link;
1040 if (link->link_status)
1041 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1042 eth_dev->data->port_id,
1043 (uint32_t)link->link_speed,
1044 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1045 ("full-duplex") : ("half-duplex\n"));
1047 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1048 eth_dev->data->port_id);
1052 * Determine whether the current configuration requires support for scattered
1053 * receive; return 1 if scattered receive is required and 0 if not.
1055 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1060 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1063 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1064 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1066 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1067 RTE_PKTMBUF_HEADROOM);
1068 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1074 static eth_rx_burst_t
1075 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1077 struct bnxt *bp = eth_dev->data->dev_private;
1079 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1080 #ifndef RTE_LIBRTE_IEEE1588
1082 * Vector mode receive can be enabled only if scatter rx is not
1083 * in use and rx offloads are limited to VLAN stripping and
1086 if (!eth_dev->data->scattered_rx &&
1087 !(eth_dev->data->dev_conf.rxmode.offloads &
1088 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1089 DEV_RX_OFFLOAD_KEEP_CRC |
1090 DEV_RX_OFFLOAD_JUMBO_FRAME |
1091 DEV_RX_OFFLOAD_IPV4_CKSUM |
1092 DEV_RX_OFFLOAD_UDP_CKSUM |
1093 DEV_RX_OFFLOAD_TCP_CKSUM |
1094 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1095 DEV_RX_OFFLOAD_RSS_HASH |
1096 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1097 !BNXT_TRUFLOW_EN(bp)) {
1098 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1099 eth_dev->data->port_id);
1100 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1101 return bnxt_recv_pkts_vec;
1103 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1104 eth_dev->data->port_id);
1106 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1107 eth_dev->data->port_id,
1108 eth_dev->data->scattered_rx,
1109 eth_dev->data->dev_conf.rxmode.offloads);
1112 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1113 return bnxt_recv_pkts;
1116 static eth_tx_burst_t
1117 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1119 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1120 #ifndef RTE_LIBRTE_IEEE1588
1121 struct bnxt *bp = eth_dev->data->dev_private;
1124 * Vector mode transmit can be enabled only if not using scatter rx
1127 if (!eth_dev->data->scattered_rx &&
1128 !eth_dev->data->dev_conf.txmode.offloads &&
1129 !BNXT_TRUFLOW_EN(bp)) {
1130 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1131 eth_dev->data->port_id);
1132 return bnxt_xmit_pkts_vec;
1134 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1135 eth_dev->data->port_id);
1137 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1138 eth_dev->data->port_id,
1139 eth_dev->data->scattered_rx,
1140 eth_dev->data->dev_conf.txmode.offloads);
1143 return bnxt_xmit_pkts;
1146 static int bnxt_handle_if_change_status(struct bnxt *bp)
1150 /* Since fw has undergone a reset and lost all contexts,
1151 * set fatal flag to not issue hwrm during cleanup
1153 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1154 bnxt_uninit_resources(bp, true);
1156 /* clear fatal flag so that re-init happens */
1157 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1158 rc = bnxt_init_resources(bp, true);
1160 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1166 bnxt_create_port_app_df_rule(struct bnxt *bp, uint8_t flow_type,
1169 uint16_t port_id = bp->eth_dev->data->port_id;
1170 struct ulp_tlv_param param_list[] = {
1172 .type = BNXT_ULP_DF_PARAM_TYPE_DEV_PORT_ID,
1174 .value = {(port_id >> 8) & 0xff, port_id & 0xff}
1177 .type = BNXT_ULP_DF_PARAM_TYPE_LAST,
1183 return ulp_default_flow_create(bp->eth_dev, param_list, flow_type,
1188 bnxt_create_df_rules(struct bnxt *bp)
1190 struct bnxt_ulp_data *cfg_data;
1193 cfg_data = bp->ulp_ctx->cfg_data;
1194 rc = bnxt_create_port_app_df_rule(bp, BNXT_ULP_DF_TPL_PORT_TO_VS,
1195 &cfg_data->port_to_app_flow_id);
1198 "Failed to create port to app default rule\n");
1202 BNXT_TF_DBG(DEBUG, "***** created port to app default rule ******\n");
1203 rc = bnxt_create_port_app_df_rule(bp, BNXT_ULP_DF_TPL_VS_TO_PORT,
1204 &cfg_data->app_to_port_flow_id);
1206 rc = ulp_default_flow_db_cfa_action_get(bp->ulp_ctx,
1207 cfg_data->app_to_port_flow_id,
1208 &cfg_data->tx_cfa_action);
1213 "***** created app to port default rule *****\n");
1218 BNXT_TF_DBG(DEBUG, "Failed to create app to port default rule\n");
1223 bnxt_destroy_df_rules(struct bnxt *bp)
1225 struct bnxt_ulp_data *cfg_data;
1227 cfg_data = bp->ulp_ctx->cfg_data;
1228 ulp_default_flow_destroy(bp->eth_dev, cfg_data->port_to_app_flow_id);
1229 ulp_default_flow_destroy(bp->eth_dev, cfg_data->app_to_port_flow_id);
1232 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1234 struct bnxt *bp = eth_dev->data->dev_private;
1235 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1237 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1239 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1240 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1244 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1246 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1247 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1251 rc = bnxt_hwrm_if_change(bp, true);
1252 if (rc == 0 || rc != -EAGAIN)
1255 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1256 } while (retry_cnt--);
1261 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1262 rc = bnxt_handle_if_change_status(bp);
1267 bnxt_enable_int(bp);
1269 rc = bnxt_init_chip(bp);
1273 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1274 eth_dev->data->dev_started = 1;
1276 bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1278 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1279 vlan_mask |= ETH_VLAN_FILTER_MASK;
1280 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1281 vlan_mask |= ETH_VLAN_STRIP_MASK;
1282 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1286 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1287 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1289 pthread_mutex_lock(&bp->def_cp_lock);
1290 bnxt_schedule_fw_health_check(bp);
1291 pthread_mutex_unlock(&bp->def_cp_lock);
1293 if (BNXT_TRUFLOW_EN(bp))
1299 bnxt_shutdown_nic(bp);
1300 bnxt_free_tx_mbufs(bp);
1301 bnxt_free_rx_mbufs(bp);
1302 bnxt_hwrm_if_change(bp, false);
1303 eth_dev->data->dev_started = 0;
1307 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1309 struct bnxt *bp = eth_dev->data->dev_private;
1312 if (!bp->link_info->link_up)
1313 rc = bnxt_set_hwrm_link_config(bp, true);
1315 eth_dev->data->dev_link.link_status = 1;
1317 bnxt_print_link_info(eth_dev);
1321 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1323 struct bnxt *bp = eth_dev->data->dev_private;
1325 eth_dev->data->dev_link.link_status = 0;
1326 bnxt_set_hwrm_link_config(bp, false);
1327 bp->link_info->link_up = 0;
1332 static void bnxt_free_switch_domain(struct bnxt *bp)
1334 if (bp->switch_domain_id)
1335 rte_eth_switch_domain_free(bp->switch_domain_id);
1338 /* Unload the driver, release resources */
1339 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1341 struct bnxt *bp = eth_dev->data->dev_private;
1342 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1343 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1345 eth_dev->data->dev_started = 0;
1346 /* Prevent crashes when queues are still in use */
1347 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1348 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1350 bnxt_disable_int(bp);
1352 /* disable uio/vfio intr/eventfd mapping */
1353 rte_intr_disable(intr_handle);
1355 bnxt_cancel_fw_health_check(bp);
1357 bnxt_dev_set_link_down_op(eth_dev);
1359 /* Wait for link to be reset and the async notification to process.
1360 * During reset recovery, there is no need to wait and
1361 * VF/NPAR functions do not have privilege to change PHY config.
1363 if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1364 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1366 /* Clean queue intr-vector mapping */
1367 rte_intr_efd_disable(intr_handle);
1368 if (intr_handle->intr_vec != NULL) {
1369 rte_free(intr_handle->intr_vec);
1370 intr_handle->intr_vec = NULL;
1373 bnxt_hwrm_port_clr_stats(bp);
1374 bnxt_free_tx_mbufs(bp);
1375 bnxt_free_rx_mbufs(bp);
1376 /* Process any remaining notifications in default completion queue */
1377 bnxt_int_handler(eth_dev);
1378 bnxt_shutdown_nic(bp);
1379 bnxt_hwrm_if_change(bp, false);
1381 rte_free(bp->mark_table);
1382 bp->mark_table = NULL;
1384 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1385 bp->rx_cosq_cnt = 0;
1386 /* All filters are deleted on a port stop. */
1387 if (BNXT_FLOW_XSTATS_EN(bp))
1388 bp->flow_stat->flow_count = 0;
1391 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1393 struct bnxt *bp = eth_dev->data->dev_private;
1395 /* cancel the recovery handler before remove dev */
1396 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1397 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1398 bnxt_cancel_fc_thread(bp);
1400 if (BNXT_TRUFLOW_EN(bp)) {
1401 if (bp->rep_info != NULL)
1402 bnxt_destroy_df_rules(bp);
1403 bnxt_ulp_deinit(bp);
1406 if (eth_dev->data->dev_started)
1407 bnxt_dev_stop_op(eth_dev);
1409 bnxt_free_switch_domain(bp);
1411 bnxt_uninit_resources(bp, false);
1413 bnxt_free_leds_info(bp);
1414 bnxt_free_cos_queues(bp);
1415 bnxt_free_link_info(bp);
1416 bnxt_free_pf_info(bp);
1417 bnxt_free_parent_info(bp);
1419 eth_dev->dev_ops = NULL;
1420 eth_dev->rx_pkt_burst = NULL;
1421 eth_dev->tx_pkt_burst = NULL;
1423 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1424 bp->tx_mem_zone = NULL;
1425 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1426 bp->rx_mem_zone = NULL;
1428 rte_free(bp->pf->vf_info);
1429 bp->pf->vf_info = NULL;
1431 rte_free(bp->grp_info);
1432 bp->grp_info = NULL;
1435 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1438 struct bnxt *bp = eth_dev->data->dev_private;
1439 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1440 struct bnxt_vnic_info *vnic;
1441 struct bnxt_filter_info *filter, *temp_filter;
1444 if (is_bnxt_in_error(bp))
1448 * Loop through all VNICs from the specified filter flow pools to
1449 * remove the corresponding MAC addr filter
1451 for (i = 0; i < bp->nr_vnics; i++) {
1452 if (!(pool_mask & (1ULL << i)))
1455 vnic = &bp->vnic_info[i];
1456 filter = STAILQ_FIRST(&vnic->filter);
1458 temp_filter = STAILQ_NEXT(filter, next);
1459 if (filter->mac_index == index) {
1460 STAILQ_REMOVE(&vnic->filter, filter,
1461 bnxt_filter_info, next);
1462 bnxt_hwrm_clear_l2_filter(bp, filter);
1463 bnxt_free_filter(bp, filter);
1465 filter = temp_filter;
1470 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1471 struct rte_ether_addr *mac_addr, uint32_t index,
1474 struct bnxt_filter_info *filter;
1477 /* Attach requested MAC address to the new l2_filter */
1478 STAILQ_FOREACH(filter, &vnic->filter, next) {
1479 if (filter->mac_index == index) {
1481 "MAC addr already existed for pool %d\n",
1487 filter = bnxt_alloc_filter(bp);
1489 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1493 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1494 * if the MAC that's been programmed now is a different one, then,
1495 * copy that addr to filter->l2_addr
1498 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1499 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1501 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1503 filter->mac_index = index;
1504 if (filter->mac_index == 0)
1505 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1507 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1509 bnxt_free_filter(bp, filter);
1515 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1516 struct rte_ether_addr *mac_addr,
1517 uint32_t index, uint32_t pool)
1519 struct bnxt *bp = eth_dev->data->dev_private;
1520 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1523 rc = is_bnxt_in_error(bp);
1527 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1528 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1533 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1537 /* Filter settings will get applied when port is started */
1538 if (!eth_dev->data->dev_started)
1541 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1546 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1547 bool exp_link_status)
1550 struct bnxt *bp = eth_dev->data->dev_private;
1551 struct rte_eth_link new;
1552 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1553 BNXT_LINK_DOWN_WAIT_CNT;
1555 rc = is_bnxt_in_error(bp);
1559 memset(&new, 0, sizeof(new));
1561 /* Retrieve link info from hardware */
1562 rc = bnxt_get_hwrm_link_config(bp, &new);
1564 new.link_speed = ETH_LINK_SPEED_100M;
1565 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1567 "Failed to retrieve link rc = 0x%x!\n", rc);
1571 if (!wait_to_complete || new.link_status == exp_link_status)
1574 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1578 /* Timed out or success */
1579 if (new.link_status != eth_dev->data->dev_link.link_status ||
1580 new.link_speed != eth_dev->data->dev_link.link_speed) {
1581 rte_eth_linkstatus_set(eth_dev, &new);
1583 _rte_eth_dev_callback_process(eth_dev,
1584 RTE_ETH_EVENT_INTR_LSC,
1587 bnxt_print_link_info(eth_dev);
1593 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1594 int wait_to_complete)
1596 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1599 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1601 struct bnxt *bp = eth_dev->data->dev_private;
1602 struct bnxt_vnic_info *vnic;
1606 rc = is_bnxt_in_error(bp);
1610 /* Filter settings will get applied when port is started */
1611 if (!eth_dev->data->dev_started)
1614 if (bp->vnic_info == NULL)
1617 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1619 old_flags = vnic->flags;
1620 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1621 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1623 vnic->flags = old_flags;
1628 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1630 struct bnxt *bp = eth_dev->data->dev_private;
1631 struct bnxt_vnic_info *vnic;
1635 rc = is_bnxt_in_error(bp);
1639 /* Filter settings will get applied when port is started */
1640 if (!eth_dev->data->dev_started)
1643 if (bp->vnic_info == NULL)
1646 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1648 old_flags = vnic->flags;
1649 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1650 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1652 vnic->flags = old_flags;
1654 if (BNXT_TRUFLOW_EN(bp) && bp->rep_info != NULL)
1655 bnxt_create_df_rules(bp);
1660 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1662 struct bnxt *bp = eth_dev->data->dev_private;
1663 struct bnxt_vnic_info *vnic;
1667 rc = is_bnxt_in_error(bp);
1671 /* Filter settings will get applied when port is started */
1672 if (!eth_dev->data->dev_started)
1675 if (bp->vnic_info == NULL)
1678 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1680 old_flags = vnic->flags;
1681 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1682 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1684 vnic->flags = old_flags;
1689 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1691 struct bnxt *bp = eth_dev->data->dev_private;
1692 struct bnxt_vnic_info *vnic;
1696 rc = is_bnxt_in_error(bp);
1700 /* Filter settings will get applied when port is started */
1701 if (!eth_dev->data->dev_started)
1704 if (bp->vnic_info == NULL)
1707 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1709 old_flags = vnic->flags;
1710 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1711 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1713 vnic->flags = old_flags;
1718 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1719 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1721 if (qid >= bp->rx_nr_rings)
1724 return bp->eth_dev->data->rx_queues[qid];
1727 /* Return rxq corresponding to a given rss table ring/group ID. */
1728 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1730 struct bnxt_rx_queue *rxq;
1733 if (!BNXT_HAS_RING_GRPS(bp)) {
1734 for (i = 0; i < bp->rx_nr_rings; i++) {
1735 rxq = bp->eth_dev->data->rx_queues[i];
1736 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1740 for (i = 0; i < bp->rx_nr_rings; i++) {
1741 if (bp->grp_info[i].fw_grp_id == fwr)
1746 return INVALID_HW_RING_ID;
1749 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1750 struct rte_eth_rss_reta_entry64 *reta_conf,
1753 struct bnxt *bp = eth_dev->data->dev_private;
1754 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1755 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1756 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1760 rc = is_bnxt_in_error(bp);
1764 if (!vnic->rss_table)
1767 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1770 if (reta_size != tbl_size) {
1771 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1772 "(%d) must equal the size supported by the hardware "
1773 "(%d)\n", reta_size, tbl_size);
1777 for (i = 0; i < reta_size; i++) {
1778 struct bnxt_rx_queue *rxq;
1780 idx = i / RTE_RETA_GROUP_SIZE;
1781 sft = i % RTE_RETA_GROUP_SIZE;
1783 if (!(reta_conf[idx].mask & (1ULL << sft)))
1786 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1788 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1792 if (BNXT_CHIP_THOR(bp)) {
1793 vnic->rss_table[i * 2] =
1794 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1795 vnic->rss_table[i * 2 + 1] =
1796 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1798 vnic->rss_table[i] =
1799 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1803 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1807 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1808 struct rte_eth_rss_reta_entry64 *reta_conf,
1811 struct bnxt *bp = eth_dev->data->dev_private;
1812 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1813 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1814 uint16_t idx, sft, i;
1817 rc = is_bnxt_in_error(bp);
1821 /* Retrieve from the default VNIC */
1824 if (!vnic->rss_table)
1827 if (reta_size != tbl_size) {
1828 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1829 "(%d) must equal the size supported by the hardware "
1830 "(%d)\n", reta_size, tbl_size);
1834 for (idx = 0, i = 0; i < reta_size; i++) {
1835 idx = i / RTE_RETA_GROUP_SIZE;
1836 sft = i % RTE_RETA_GROUP_SIZE;
1838 if (reta_conf[idx].mask & (1ULL << sft)) {
1841 if (BNXT_CHIP_THOR(bp))
1842 qid = bnxt_rss_to_qid(bp,
1843 vnic->rss_table[i * 2]);
1845 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1847 if (qid == INVALID_HW_RING_ID) {
1848 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1851 reta_conf[idx].reta[sft] = qid;
1858 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1859 struct rte_eth_rss_conf *rss_conf)
1861 struct bnxt *bp = eth_dev->data->dev_private;
1862 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1863 struct bnxt_vnic_info *vnic;
1866 rc = is_bnxt_in_error(bp);
1871 * If RSS enablement were different than dev_configure,
1872 * then return -EINVAL
1874 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1875 if (!rss_conf->rss_hf)
1876 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1878 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1882 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1883 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
1887 /* Update the default RSS VNIC(s) */
1888 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1889 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1892 * If hashkey is not specified, use the previously configured
1895 if (!rss_conf->rss_key)
1898 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1900 "Invalid hashkey length, should be 16 bytes\n");
1903 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1906 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1910 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1911 struct rte_eth_rss_conf *rss_conf)
1913 struct bnxt *bp = eth_dev->data->dev_private;
1914 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1916 uint32_t hash_types;
1918 rc = is_bnxt_in_error(bp);
1922 /* RSS configuration is the same for all VNICs */
1923 if (vnic && vnic->rss_hash_key) {
1924 if (rss_conf->rss_key) {
1925 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1926 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1927 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1930 hash_types = vnic->hash_type;
1931 rss_conf->rss_hf = 0;
1932 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1933 rss_conf->rss_hf |= ETH_RSS_IPV4;
1934 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1936 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1937 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1939 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1941 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1942 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1944 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1946 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1947 rss_conf->rss_hf |= ETH_RSS_IPV6;
1948 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1950 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1951 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1953 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1955 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1956 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1958 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1962 "Unknown RSS config from firmware (%08x), RSS disabled",
1967 rss_conf->rss_hf = 0;
1972 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1973 struct rte_eth_fc_conf *fc_conf)
1975 struct bnxt *bp = dev->data->dev_private;
1976 struct rte_eth_link link_info;
1979 rc = is_bnxt_in_error(bp);
1983 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1987 memset(fc_conf, 0, sizeof(*fc_conf));
1988 if (bp->link_info->auto_pause)
1989 fc_conf->autoneg = 1;
1990 switch (bp->link_info->pause) {
1992 fc_conf->mode = RTE_FC_NONE;
1994 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1995 fc_conf->mode = RTE_FC_TX_PAUSE;
1997 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1998 fc_conf->mode = RTE_FC_RX_PAUSE;
2000 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2001 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2002 fc_conf->mode = RTE_FC_FULL;
2008 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2009 struct rte_eth_fc_conf *fc_conf)
2011 struct bnxt *bp = dev->data->dev_private;
2014 rc = is_bnxt_in_error(bp);
2018 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2019 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2023 switch (fc_conf->mode) {
2025 bp->link_info->auto_pause = 0;
2026 bp->link_info->force_pause = 0;
2028 case RTE_FC_RX_PAUSE:
2029 if (fc_conf->autoneg) {
2030 bp->link_info->auto_pause =
2031 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2032 bp->link_info->force_pause = 0;
2034 bp->link_info->auto_pause = 0;
2035 bp->link_info->force_pause =
2036 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2039 case RTE_FC_TX_PAUSE:
2040 if (fc_conf->autoneg) {
2041 bp->link_info->auto_pause =
2042 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2043 bp->link_info->force_pause = 0;
2045 bp->link_info->auto_pause = 0;
2046 bp->link_info->force_pause =
2047 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2051 if (fc_conf->autoneg) {
2052 bp->link_info->auto_pause =
2053 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2054 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2055 bp->link_info->force_pause = 0;
2057 bp->link_info->auto_pause = 0;
2058 bp->link_info->force_pause =
2059 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2060 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2064 return bnxt_set_hwrm_link_config(bp, true);
2067 /* Add UDP tunneling port */
2069 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2070 struct rte_eth_udp_tunnel *udp_tunnel)
2072 struct bnxt *bp = eth_dev->data->dev_private;
2073 uint16_t tunnel_type = 0;
2076 rc = is_bnxt_in_error(bp);
2080 switch (udp_tunnel->prot_type) {
2081 case RTE_TUNNEL_TYPE_VXLAN:
2082 if (bp->vxlan_port_cnt) {
2083 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2084 udp_tunnel->udp_port);
2085 if (bp->vxlan_port != udp_tunnel->udp_port) {
2086 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2089 bp->vxlan_port_cnt++;
2093 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2094 bp->vxlan_port_cnt++;
2096 case RTE_TUNNEL_TYPE_GENEVE:
2097 if (bp->geneve_port_cnt) {
2098 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2099 udp_tunnel->udp_port);
2100 if (bp->geneve_port != udp_tunnel->udp_port) {
2101 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2104 bp->geneve_port_cnt++;
2108 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2109 bp->geneve_port_cnt++;
2112 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2115 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2121 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2122 struct rte_eth_udp_tunnel *udp_tunnel)
2124 struct bnxt *bp = eth_dev->data->dev_private;
2125 uint16_t tunnel_type = 0;
2129 rc = is_bnxt_in_error(bp);
2133 switch (udp_tunnel->prot_type) {
2134 case RTE_TUNNEL_TYPE_VXLAN:
2135 if (!bp->vxlan_port_cnt) {
2136 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2139 if (bp->vxlan_port != udp_tunnel->udp_port) {
2140 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2141 udp_tunnel->udp_port, bp->vxlan_port);
2144 if (--bp->vxlan_port_cnt)
2148 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2149 port = bp->vxlan_fw_dst_port_id;
2151 case RTE_TUNNEL_TYPE_GENEVE:
2152 if (!bp->geneve_port_cnt) {
2153 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2156 if (bp->geneve_port != udp_tunnel->udp_port) {
2157 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2158 udp_tunnel->udp_port, bp->geneve_port);
2161 if (--bp->geneve_port_cnt)
2165 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2166 port = bp->geneve_fw_dst_port_id;
2169 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2173 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2176 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2179 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2180 bp->geneve_port = 0;
2185 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2187 struct bnxt_filter_info *filter;
2188 struct bnxt_vnic_info *vnic;
2190 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2192 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2193 filter = STAILQ_FIRST(&vnic->filter);
2195 /* Search for this matching MAC+VLAN filter */
2196 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2197 /* Delete the filter */
2198 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2201 STAILQ_REMOVE(&vnic->filter, filter,
2202 bnxt_filter_info, next);
2203 bnxt_free_filter(bp, filter);
2205 "Deleted vlan filter for %d\n",
2209 filter = STAILQ_NEXT(filter, next);
2214 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2216 struct bnxt_filter_info *filter;
2217 struct bnxt_vnic_info *vnic;
2219 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2220 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2221 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2223 /* Implementation notes on the use of VNIC in this command:
2225 * By default, these filters belong to default vnic for the function.
2226 * Once these filters are set up, only destination VNIC can be modified.
2227 * If the destination VNIC is not specified in this command,
2228 * then the HWRM shall only create an l2 context id.
2231 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2232 filter = STAILQ_FIRST(&vnic->filter);
2233 /* Check if the VLAN has already been added */
2235 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2238 filter = STAILQ_NEXT(filter, next);
2241 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2242 * command to create MAC+VLAN filter with the right flags, enables set.
2244 filter = bnxt_alloc_filter(bp);
2247 "MAC/VLAN filter alloc failed\n");
2250 /* MAC + VLAN ID filter */
2251 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2252 * untagged packets are received
2254 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2255 * packets and only the programmed vlan's packets are received
2257 filter->l2_ivlan = vlan_id;
2258 filter->l2_ivlan_mask = 0x0FFF;
2259 filter->enables |= en;
2260 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2262 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2264 /* Free the newly allocated filter as we were
2265 * not able to create the filter in hardware.
2267 bnxt_free_filter(bp, filter);
2271 filter->mac_index = 0;
2272 /* Add this new filter to the list */
2274 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2276 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2279 "Added Vlan filter for %d\n", vlan_id);
2283 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2284 uint16_t vlan_id, int on)
2286 struct bnxt *bp = eth_dev->data->dev_private;
2289 rc = is_bnxt_in_error(bp);
2293 if (!eth_dev->data->dev_started) {
2294 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2298 /* These operations apply to ALL existing MAC/VLAN filters */
2300 return bnxt_add_vlan_filter(bp, vlan_id);
2302 return bnxt_del_vlan_filter(bp, vlan_id);
2305 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2306 struct bnxt_vnic_info *vnic)
2308 struct bnxt_filter_info *filter;
2311 filter = STAILQ_FIRST(&vnic->filter);
2313 if (filter->mac_index == 0 &&
2314 !memcmp(filter->l2_addr, bp->mac_addr,
2315 RTE_ETHER_ADDR_LEN)) {
2316 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2318 STAILQ_REMOVE(&vnic->filter, filter,
2319 bnxt_filter_info, next);
2320 bnxt_free_filter(bp, filter);
2324 filter = STAILQ_NEXT(filter, next);
2330 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2332 struct bnxt_vnic_info *vnic;
2336 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2337 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2338 /* Remove any VLAN filters programmed */
2339 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2340 bnxt_del_vlan_filter(bp, i);
2342 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2346 /* Default filter will allow packets that match the
2347 * dest mac. So, it has to be deleted, otherwise, we
2348 * will endup receiving vlan packets for which the
2349 * filter is not programmed, when hw-vlan-filter
2350 * configuration is ON
2352 bnxt_del_dflt_mac_filter(bp, vnic);
2353 /* This filter will allow only untagged packets */
2354 bnxt_add_vlan_filter(bp, 0);
2356 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2357 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2362 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2364 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2368 /* Destroy vnic filters and vnic */
2369 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2370 DEV_RX_OFFLOAD_VLAN_FILTER) {
2371 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2372 bnxt_del_vlan_filter(bp, i);
2374 bnxt_del_dflt_mac_filter(bp, vnic);
2376 rc = bnxt_hwrm_vnic_free(bp, vnic);
2380 rte_free(vnic->fw_grp_ids);
2381 vnic->fw_grp_ids = NULL;
2383 vnic->rx_queue_cnt = 0;
2389 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2391 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2394 /* Destroy, recreate and reconfigure the default vnic */
2395 rc = bnxt_free_one_vnic(bp, 0);
2399 /* default vnic 0 */
2400 rc = bnxt_setup_one_vnic(bp, 0);
2404 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2405 DEV_RX_OFFLOAD_VLAN_FILTER) {
2406 rc = bnxt_add_vlan_filter(bp, 0);
2409 rc = bnxt_restore_vlan_filters(bp);
2413 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2418 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2422 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2423 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2429 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2431 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2432 struct bnxt *bp = dev->data->dev_private;
2435 rc = is_bnxt_in_error(bp);
2439 /* Filter settings will get applied when port is started */
2440 if (!dev->data->dev_started)
2443 if (mask & ETH_VLAN_FILTER_MASK) {
2444 /* Enable or disable VLAN filtering */
2445 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2450 if (mask & ETH_VLAN_STRIP_MASK) {
2451 /* Enable or disable VLAN stripping */
2452 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2457 if (mask & ETH_VLAN_EXTEND_MASK) {
2458 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2459 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2461 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2468 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2471 struct bnxt *bp = dev->data->dev_private;
2472 int qinq = dev->data->dev_conf.rxmode.offloads &
2473 DEV_RX_OFFLOAD_VLAN_EXTEND;
2475 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2476 vlan_type != ETH_VLAN_TYPE_OUTER) {
2478 "Unsupported vlan type.");
2483 "QinQ not enabled. Needs to be ON as we can "
2484 "accelerate only outer vlan\n");
2488 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2490 case RTE_ETHER_TYPE_QINQ:
2492 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2494 case RTE_ETHER_TYPE_VLAN:
2496 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2498 case RTE_ETHER_TYPE_QINQ1:
2500 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2502 case RTE_ETHER_TYPE_QINQ2:
2504 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2506 case RTE_ETHER_TYPE_QINQ3:
2508 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2511 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2514 bp->outer_tpid_bd |= tpid;
2515 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2516 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2518 "Can accelerate only outer vlan in QinQ\n");
2526 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2527 struct rte_ether_addr *addr)
2529 struct bnxt *bp = dev->data->dev_private;
2530 /* Default Filter is tied to VNIC 0 */
2531 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2534 rc = is_bnxt_in_error(bp);
2538 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2541 if (rte_is_zero_ether_addr(addr))
2544 /* Filter settings will get applied when port is started */
2545 if (!dev->data->dev_started)
2548 /* Check if the requested MAC is already added */
2549 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2552 /* Destroy filter and re-create it */
2553 bnxt_del_dflt_mac_filter(bp, vnic);
2555 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2556 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2557 /* This filter will allow only untagged packets */
2558 rc = bnxt_add_vlan_filter(bp, 0);
2560 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2563 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2568 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2569 struct rte_ether_addr *mc_addr_set,
2570 uint32_t nb_mc_addr)
2572 struct bnxt *bp = eth_dev->data->dev_private;
2573 char *mc_addr_list = (char *)mc_addr_set;
2574 struct bnxt_vnic_info *vnic;
2575 uint32_t off = 0, i = 0;
2578 rc = is_bnxt_in_error(bp);
2582 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2584 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2585 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2589 /* TODO Check for Duplicate mcast addresses */
2590 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2591 for (i = 0; i < nb_mc_addr; i++) {
2592 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2593 RTE_ETHER_ADDR_LEN);
2594 off += RTE_ETHER_ADDR_LEN;
2597 vnic->mc_addr_cnt = i;
2598 if (vnic->mc_addr_cnt)
2599 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2601 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2604 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2608 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2610 struct bnxt *bp = dev->data->dev_private;
2611 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2612 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2613 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2614 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2617 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2618 fw_major, fw_minor, fw_updt, fw_rsvd);
2620 ret += 1; /* add the size of '\0' */
2621 if (fw_size < (uint32_t)ret)
2628 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2629 struct rte_eth_rxq_info *qinfo)
2631 struct bnxt *bp = dev->data->dev_private;
2632 struct bnxt_rx_queue *rxq;
2634 if (is_bnxt_in_error(bp))
2637 rxq = dev->data->rx_queues[queue_id];
2639 qinfo->mp = rxq->mb_pool;
2640 qinfo->scattered_rx = dev->data->scattered_rx;
2641 qinfo->nb_desc = rxq->nb_rx_desc;
2643 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2644 qinfo->conf.rx_drop_en = 0;
2645 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2649 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2650 struct rte_eth_txq_info *qinfo)
2652 struct bnxt *bp = dev->data->dev_private;
2653 struct bnxt_tx_queue *txq;
2655 if (is_bnxt_in_error(bp))
2658 txq = dev->data->tx_queues[queue_id];
2660 qinfo->nb_desc = txq->nb_tx_desc;
2662 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2663 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2664 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2666 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2667 qinfo->conf.tx_rs_thresh = 0;
2668 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2672 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2673 struct rte_eth_burst_mode *mode)
2675 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2677 if (pkt_burst == bnxt_recv_pkts) {
2678 snprintf(mode->info, sizeof(mode->info), "%s",
2682 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
2683 if (pkt_burst == bnxt_recv_pkts_vec) {
2684 snprintf(mode->info, sizeof(mode->info), "%s",
2694 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2695 struct rte_eth_burst_mode *mode)
2697 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2699 if (pkt_burst == bnxt_xmit_pkts) {
2700 snprintf(mode->info, sizeof(mode->info), "%s",
2704 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
2705 if (pkt_burst == bnxt_xmit_pkts_vec) {
2706 snprintf(mode->info, sizeof(mode->info), "%s",
2715 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2717 struct bnxt *bp = eth_dev->data->dev_private;
2718 uint32_t new_pkt_size;
2722 rc = is_bnxt_in_error(bp);
2726 /* Exit if receive queues are not configured yet */
2727 if (!eth_dev->data->nb_rx_queues)
2730 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2731 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2733 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
2735 * If vector-mode tx/rx is active, disallow any MTU change that would
2736 * require scattered receive support.
2738 if (eth_dev->data->dev_started &&
2739 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2740 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2742 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2744 "MTU change would require scattered rx support. ");
2745 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2750 if (new_mtu > RTE_ETHER_MTU) {
2751 bp->flags |= BNXT_FLAG_JUMBO;
2752 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2753 DEV_RX_OFFLOAD_JUMBO_FRAME;
2755 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2756 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2757 bp->flags &= ~BNXT_FLAG_JUMBO;
2760 /* Is there a change in mtu setting? */
2761 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2764 for (i = 0; i < bp->nr_vnics; i++) {
2765 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2768 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2769 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2773 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2774 size -= RTE_PKTMBUF_HEADROOM;
2776 if (size < new_mtu) {
2777 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2784 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2786 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2792 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2794 struct bnxt *bp = dev->data->dev_private;
2795 uint16_t vlan = bp->vlan;
2798 rc = is_bnxt_in_error(bp);
2802 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2804 "PVID cannot be modified for this function\n");
2807 bp->vlan = on ? pvid : 0;
2809 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2816 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2818 struct bnxt *bp = dev->data->dev_private;
2821 rc = is_bnxt_in_error(bp);
2825 return bnxt_hwrm_port_led_cfg(bp, true);
2829 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2831 struct bnxt *bp = dev->data->dev_private;
2834 rc = is_bnxt_in_error(bp);
2838 return bnxt_hwrm_port_led_cfg(bp, false);
2842 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2844 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2845 uint32_t desc = 0, raw_cons = 0, cons;
2846 struct bnxt_cp_ring_info *cpr;
2847 struct bnxt_rx_queue *rxq;
2848 struct rx_pkt_cmpl *rxcmp;
2851 rc = is_bnxt_in_error(bp);
2855 rxq = dev->data->rx_queues[rx_queue_id];
2857 raw_cons = cpr->cp_raw_cons;
2860 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2861 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2862 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2864 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2876 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2878 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2879 struct bnxt_rx_ring_info *rxr;
2880 struct bnxt_cp_ring_info *cpr;
2881 struct bnxt_sw_rx_bd *rx_buf;
2882 struct rx_pkt_cmpl *rxcmp;
2883 uint32_t cons, cp_cons;
2889 rc = is_bnxt_in_error(rxq->bp);
2896 if (offset >= rxq->nb_rx_desc)
2899 cons = RING_CMP(cpr->cp_ring_struct, offset);
2900 cp_cons = cpr->cp_raw_cons;
2901 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2903 if (cons > cp_cons) {
2904 if (CMPL_VALID(rxcmp, cpr->valid))
2905 return RTE_ETH_RX_DESC_DONE;
2907 if (CMPL_VALID(rxcmp, !cpr->valid))
2908 return RTE_ETH_RX_DESC_DONE;
2910 rx_buf = &rxr->rx_buf_ring[cons];
2911 if (rx_buf->mbuf == NULL)
2912 return RTE_ETH_RX_DESC_UNAVAIL;
2915 return RTE_ETH_RX_DESC_AVAIL;
2919 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2921 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2922 struct bnxt_tx_ring_info *txr;
2923 struct bnxt_cp_ring_info *cpr;
2924 struct bnxt_sw_tx_bd *tx_buf;
2925 struct tx_pkt_cmpl *txcmp;
2926 uint32_t cons, cp_cons;
2932 rc = is_bnxt_in_error(txq->bp);
2939 if (offset >= txq->nb_tx_desc)
2942 cons = RING_CMP(cpr->cp_ring_struct, offset);
2943 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2944 cp_cons = cpr->cp_raw_cons;
2946 if (cons > cp_cons) {
2947 if (CMPL_VALID(txcmp, cpr->valid))
2948 return RTE_ETH_TX_DESC_UNAVAIL;
2950 if (CMPL_VALID(txcmp, !cpr->valid))
2951 return RTE_ETH_TX_DESC_UNAVAIL;
2953 tx_buf = &txr->tx_buf_ring[cons];
2954 if (tx_buf->mbuf == NULL)
2955 return RTE_ETH_TX_DESC_DONE;
2957 return RTE_ETH_TX_DESC_FULL;
2960 static struct bnxt_filter_info *
2961 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2962 struct rte_eth_ethertype_filter *efilter,
2963 struct bnxt_vnic_info *vnic0,
2964 struct bnxt_vnic_info *vnic,
2967 struct bnxt_filter_info *mfilter = NULL;
2971 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2972 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2973 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2974 " ethertype filter.", efilter->ether_type);
2978 if (efilter->queue >= bp->rx_nr_rings) {
2979 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2984 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2985 vnic = &bp->vnic_info[efilter->queue];
2987 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2992 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2993 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2994 if ((!memcmp(efilter->mac_addr.addr_bytes,
2995 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2997 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2998 mfilter->ethertype == efilter->ether_type)) {
3004 STAILQ_FOREACH(mfilter, &vnic->filter, next)
3005 if ((!memcmp(efilter->mac_addr.addr_bytes,
3006 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3007 mfilter->ethertype == efilter->ether_type &&
3009 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
3023 bnxt_ethertype_filter(struct rte_eth_dev *dev,
3024 enum rte_filter_op filter_op,
3027 struct bnxt *bp = dev->data->dev_private;
3028 struct rte_eth_ethertype_filter *efilter =
3029 (struct rte_eth_ethertype_filter *)arg;
3030 struct bnxt_filter_info *bfilter, *filter1;
3031 struct bnxt_vnic_info *vnic, *vnic0;
3034 if (filter_op == RTE_ETH_FILTER_NOP)
3038 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3043 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3044 vnic = &bp->vnic_info[efilter->queue];
3046 switch (filter_op) {
3047 case RTE_ETH_FILTER_ADD:
3048 bnxt_match_and_validate_ether_filter(bp, efilter,
3053 bfilter = bnxt_get_unused_filter(bp);
3054 if (bfilter == NULL) {
3056 "Not enough resources for a new filter.\n");
3059 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3060 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
3061 RTE_ETHER_ADDR_LEN);
3062 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
3063 RTE_ETHER_ADDR_LEN);
3064 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3065 bfilter->ethertype = efilter->ether_type;
3066 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3068 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3069 if (filter1 == NULL) {
3074 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3075 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3077 bfilter->dst_id = vnic->fw_vnic_id;
3079 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3081 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3084 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3087 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3089 case RTE_ETH_FILTER_DELETE:
3090 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3092 if (ret == -EEXIST) {
3093 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3095 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3097 bnxt_free_filter(bp, filter1);
3098 } else if (ret == 0) {
3099 PMD_DRV_LOG(ERR, "No matching filter found\n");
3103 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3109 bnxt_free_filter(bp, bfilter);
3115 parse_ntuple_filter(struct bnxt *bp,
3116 struct rte_eth_ntuple_filter *nfilter,
3117 struct bnxt_filter_info *bfilter)
3121 if (nfilter->queue >= bp->rx_nr_rings) {
3122 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3126 switch (nfilter->dst_port_mask) {
3128 bfilter->dst_port_mask = -1;
3129 bfilter->dst_port = nfilter->dst_port;
3130 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3131 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3134 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3138 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3139 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3141 switch (nfilter->proto_mask) {
3143 if (nfilter->proto == 17) /* IPPROTO_UDP */
3144 bfilter->ip_protocol = 17;
3145 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3146 bfilter->ip_protocol = 6;
3149 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3152 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3156 switch (nfilter->dst_ip_mask) {
3158 bfilter->dst_ipaddr_mask[0] = -1;
3159 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3160 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3161 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3164 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3168 switch (nfilter->src_ip_mask) {
3170 bfilter->src_ipaddr_mask[0] = -1;
3171 bfilter->src_ipaddr[0] = nfilter->src_ip;
3172 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3173 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3176 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3180 switch (nfilter->src_port_mask) {
3182 bfilter->src_port_mask = -1;
3183 bfilter->src_port = nfilter->src_port;
3184 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3185 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3188 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3192 bfilter->enables = en;
3196 static struct bnxt_filter_info*
3197 bnxt_match_ntuple_filter(struct bnxt *bp,
3198 struct bnxt_filter_info *bfilter,
3199 struct bnxt_vnic_info **mvnic)
3201 struct bnxt_filter_info *mfilter = NULL;
3204 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3205 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3206 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3207 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3208 bfilter->src_ipaddr_mask[0] ==
3209 mfilter->src_ipaddr_mask[0] &&
3210 bfilter->src_port == mfilter->src_port &&
3211 bfilter->src_port_mask == mfilter->src_port_mask &&
3212 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3213 bfilter->dst_ipaddr_mask[0] ==
3214 mfilter->dst_ipaddr_mask[0] &&
3215 bfilter->dst_port == mfilter->dst_port &&
3216 bfilter->dst_port_mask == mfilter->dst_port_mask &&
3217 bfilter->flags == mfilter->flags &&
3218 bfilter->enables == mfilter->enables) {
3229 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3230 struct rte_eth_ntuple_filter *nfilter,
3231 enum rte_filter_op filter_op)
3233 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3234 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3237 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3238 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3242 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3243 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3247 bfilter = bnxt_get_unused_filter(bp);
3248 if (bfilter == NULL) {
3250 "Not enough resources for a new filter.\n");
3253 ret = parse_ntuple_filter(bp, nfilter, bfilter);
3257 vnic = &bp->vnic_info[nfilter->queue];
3258 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3259 filter1 = STAILQ_FIRST(&vnic0->filter);
3260 if (filter1 == NULL) {
3265 bfilter->dst_id = vnic->fw_vnic_id;
3266 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3268 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3269 bfilter->ethertype = 0x800;
3270 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3272 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3274 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3275 bfilter->dst_id == mfilter->dst_id) {
3276 PMD_DRV_LOG(ERR, "filter exists.\n");
3279 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3280 bfilter->dst_id != mfilter->dst_id) {
3281 mfilter->dst_id = vnic->fw_vnic_id;
3282 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3283 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3284 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3285 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3286 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3289 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3290 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3295 if (filter_op == RTE_ETH_FILTER_ADD) {
3296 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3297 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3300 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3302 if (mfilter == NULL) {
3303 /* This should not happen. But for Coverity! */
3307 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3309 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3310 bnxt_free_filter(bp, mfilter);
3311 bnxt_free_filter(bp, bfilter);
3316 bnxt_free_filter(bp, bfilter);
3321 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3322 enum rte_filter_op filter_op,
3325 struct bnxt *bp = dev->data->dev_private;
3328 if (filter_op == RTE_ETH_FILTER_NOP)
3332 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3337 switch (filter_op) {
3338 case RTE_ETH_FILTER_ADD:
3339 ret = bnxt_cfg_ntuple_filter(bp,
3340 (struct rte_eth_ntuple_filter *)arg,
3343 case RTE_ETH_FILTER_DELETE:
3344 ret = bnxt_cfg_ntuple_filter(bp,
3345 (struct rte_eth_ntuple_filter *)arg,
3349 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3357 bnxt_parse_fdir_filter(struct bnxt *bp,
3358 struct rte_eth_fdir_filter *fdir,
3359 struct bnxt_filter_info *filter)
3361 enum rte_fdir_mode fdir_mode =
3362 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3363 struct bnxt_vnic_info *vnic0, *vnic;
3364 struct bnxt_filter_info *filter1;
3368 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3371 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3372 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3374 switch (fdir->input.flow_type) {
3375 case RTE_ETH_FLOW_IPV4:
3376 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3378 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3379 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3380 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3381 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3382 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3383 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3384 filter->ip_addr_type =
3385 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3386 filter->src_ipaddr_mask[0] = 0xffffffff;
3387 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3388 filter->dst_ipaddr_mask[0] = 0xffffffff;
3389 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3390 filter->ethertype = 0x800;
3391 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3393 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3394 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3395 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3396 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3397 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3398 filter->dst_port_mask = 0xffff;
3399 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3400 filter->src_port_mask = 0xffff;
3401 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3402 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3403 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3404 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3405 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3406 filter->ip_protocol = 6;
3407 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3408 filter->ip_addr_type =
3409 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3410 filter->src_ipaddr_mask[0] = 0xffffffff;
3411 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3412 filter->dst_ipaddr_mask[0] = 0xffffffff;
3413 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3414 filter->ethertype = 0x800;
3415 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3417 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3418 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3419 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3420 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3421 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3422 filter->dst_port_mask = 0xffff;
3423 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3424 filter->src_port_mask = 0xffff;
3425 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3426 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3427 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3428 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3429 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3430 filter->ip_protocol = 17;
3431 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3432 filter->ip_addr_type =
3433 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3434 filter->src_ipaddr_mask[0] = 0xffffffff;
3435 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3436 filter->dst_ipaddr_mask[0] = 0xffffffff;
3437 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3438 filter->ethertype = 0x800;
3439 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3441 case RTE_ETH_FLOW_IPV6:
3442 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3444 filter->ip_addr_type =
3445 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3446 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3447 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3448 rte_memcpy(filter->src_ipaddr,
3449 fdir->input.flow.ipv6_flow.src_ip, 16);
3450 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3451 rte_memcpy(filter->dst_ipaddr,
3452 fdir->input.flow.ipv6_flow.dst_ip, 16);
3453 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3454 memset(filter->dst_ipaddr_mask, 0xff, 16);
3455 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3456 memset(filter->src_ipaddr_mask, 0xff, 16);
3457 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3458 filter->ethertype = 0x86dd;
3459 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3461 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3462 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3463 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3464 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3465 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3466 filter->dst_port_mask = 0xffff;
3467 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3468 filter->src_port_mask = 0xffff;
3469 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3470 filter->ip_addr_type =
3471 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3472 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3473 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3474 rte_memcpy(filter->src_ipaddr,
3475 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3476 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3477 rte_memcpy(filter->dst_ipaddr,
3478 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3479 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3480 memset(filter->dst_ipaddr_mask, 0xff, 16);
3481 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3482 memset(filter->src_ipaddr_mask, 0xff, 16);
3483 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3484 filter->ethertype = 0x86dd;
3485 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3487 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3488 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3489 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3490 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3491 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3492 filter->dst_port_mask = 0xffff;
3493 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3494 filter->src_port_mask = 0xffff;
3495 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3496 filter->ip_addr_type =
3497 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3498 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3499 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3500 rte_memcpy(filter->src_ipaddr,
3501 fdir->input.flow.udp6_flow.ip.src_ip, 16);
3502 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3503 rte_memcpy(filter->dst_ipaddr,
3504 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3505 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3506 memset(filter->dst_ipaddr_mask, 0xff, 16);
3507 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3508 memset(filter->src_ipaddr_mask, 0xff, 16);
3509 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3510 filter->ethertype = 0x86dd;
3511 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3513 case RTE_ETH_FLOW_L2_PAYLOAD:
3514 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3515 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3517 case RTE_ETH_FLOW_VXLAN:
3518 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3520 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3521 filter->tunnel_type =
3522 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3523 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3525 case RTE_ETH_FLOW_NVGRE:
3526 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3528 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3529 filter->tunnel_type =
3530 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3531 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3533 case RTE_ETH_FLOW_UNKNOWN:
3534 case RTE_ETH_FLOW_RAW:
3535 case RTE_ETH_FLOW_FRAG_IPV4:
3536 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3537 case RTE_ETH_FLOW_FRAG_IPV6:
3538 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3539 case RTE_ETH_FLOW_IPV6_EX:
3540 case RTE_ETH_FLOW_IPV6_TCP_EX:
3541 case RTE_ETH_FLOW_IPV6_UDP_EX:
3542 case RTE_ETH_FLOW_GENEVE:
3548 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3549 vnic = &bp->vnic_info[fdir->action.rx_queue];
3551 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3555 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3556 rte_memcpy(filter->dst_macaddr,
3557 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3558 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3561 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3562 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3563 filter1 = STAILQ_FIRST(&vnic0->filter);
3564 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3566 filter->dst_id = vnic->fw_vnic_id;
3567 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3568 if (filter->dst_macaddr[i] == 0x00)
3569 filter1 = STAILQ_FIRST(&vnic0->filter);
3571 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3574 if (filter1 == NULL)
3577 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3578 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3580 filter->enables = en;
3585 static struct bnxt_filter_info *
3586 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3587 struct bnxt_vnic_info **mvnic)
3589 struct bnxt_filter_info *mf = NULL;
3592 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3593 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3595 STAILQ_FOREACH(mf, &vnic->filter, next) {
3596 if (mf->filter_type == nf->filter_type &&
3597 mf->flags == nf->flags &&
3598 mf->src_port == nf->src_port &&
3599 mf->src_port_mask == nf->src_port_mask &&
3600 mf->dst_port == nf->dst_port &&
3601 mf->dst_port_mask == nf->dst_port_mask &&
3602 mf->ip_protocol == nf->ip_protocol &&
3603 mf->ip_addr_type == nf->ip_addr_type &&
3604 mf->ethertype == nf->ethertype &&
3605 mf->vni == nf->vni &&
3606 mf->tunnel_type == nf->tunnel_type &&
3607 mf->l2_ovlan == nf->l2_ovlan &&
3608 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3609 mf->l2_ivlan == nf->l2_ivlan &&
3610 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3611 !memcmp(mf->l2_addr, nf->l2_addr,
3612 RTE_ETHER_ADDR_LEN) &&
3613 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3614 RTE_ETHER_ADDR_LEN) &&
3615 !memcmp(mf->src_macaddr, nf->src_macaddr,
3616 RTE_ETHER_ADDR_LEN) &&
3617 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3618 RTE_ETHER_ADDR_LEN) &&
3619 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3620 sizeof(nf->src_ipaddr)) &&
3621 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3622 sizeof(nf->src_ipaddr_mask)) &&
3623 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3624 sizeof(nf->dst_ipaddr)) &&
3625 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3626 sizeof(nf->dst_ipaddr_mask))) {
3637 bnxt_fdir_filter(struct rte_eth_dev *dev,
3638 enum rte_filter_op filter_op,
3641 struct bnxt *bp = dev->data->dev_private;
3642 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3643 struct bnxt_filter_info *filter, *match;
3644 struct bnxt_vnic_info *vnic, *mvnic;
3647 if (filter_op == RTE_ETH_FILTER_NOP)
3650 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3653 switch (filter_op) {
3654 case RTE_ETH_FILTER_ADD:
3655 case RTE_ETH_FILTER_DELETE:
3657 filter = bnxt_get_unused_filter(bp);
3658 if (filter == NULL) {
3660 "Not enough resources for a new flow.\n");
3664 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3667 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3669 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3670 vnic = &bp->vnic_info[0];
3672 vnic = &bp->vnic_info[fdir->action.rx_queue];
3674 match = bnxt_match_fdir(bp, filter, &mvnic);
3675 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3676 if (match->dst_id == vnic->fw_vnic_id) {
3677 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3681 match->dst_id = vnic->fw_vnic_id;
3682 ret = bnxt_hwrm_set_ntuple_filter(bp,
3685 STAILQ_REMOVE(&mvnic->filter, match,
3686 bnxt_filter_info, next);
3687 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3689 "Filter with matching pattern exist\n");
3691 "Updated it to new destination q\n");
3695 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3696 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3701 if (filter_op == RTE_ETH_FILTER_ADD) {
3702 ret = bnxt_hwrm_set_ntuple_filter(bp,
3707 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3709 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3710 STAILQ_REMOVE(&vnic->filter, match,
3711 bnxt_filter_info, next);
3712 bnxt_free_filter(bp, match);
3713 bnxt_free_filter(bp, filter);
3716 case RTE_ETH_FILTER_FLUSH:
3717 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3718 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3720 STAILQ_FOREACH(filter, &vnic->filter, next) {
3721 if (filter->filter_type ==
3722 HWRM_CFA_NTUPLE_FILTER) {
3724 bnxt_hwrm_clear_ntuple_filter(bp,
3726 STAILQ_REMOVE(&vnic->filter, filter,
3727 bnxt_filter_info, next);
3732 case RTE_ETH_FILTER_UPDATE:
3733 case RTE_ETH_FILTER_STATS:
3734 case RTE_ETH_FILTER_INFO:
3735 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3738 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3745 bnxt_free_filter(bp, filter);
3750 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3751 enum rte_filter_type filter_type,
3752 enum rte_filter_op filter_op, void *arg)
3754 struct bnxt *bp = dev->data->dev_private;
3757 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3758 struct bnxt_vf_representor *vfr = dev->data->dev_private;
3759 bp = vfr->parent_dev->data->dev_private;
3762 ret = is_bnxt_in_error(bp);
3766 switch (filter_type) {
3767 case RTE_ETH_FILTER_TUNNEL:
3769 "filter type: %d: To be implemented\n", filter_type);
3771 case RTE_ETH_FILTER_FDIR:
3772 ret = bnxt_fdir_filter(dev, filter_op, arg);
3774 case RTE_ETH_FILTER_NTUPLE:
3775 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3777 case RTE_ETH_FILTER_ETHERTYPE:
3778 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3780 case RTE_ETH_FILTER_GENERIC:
3781 if (filter_op != RTE_ETH_FILTER_GET)
3783 if (BNXT_TRUFLOW_EN(bp))
3784 *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3786 *(const void **)arg = &bnxt_flow_ops;
3790 "Filter type (%d) not supported", filter_type);
3797 static const uint32_t *
3798 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3800 static const uint32_t ptypes[] = {
3801 RTE_PTYPE_L2_ETHER_VLAN,
3802 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3803 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3807 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3808 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3809 RTE_PTYPE_INNER_L4_ICMP,
3810 RTE_PTYPE_INNER_L4_TCP,
3811 RTE_PTYPE_INNER_L4_UDP,
3815 if (!dev->rx_pkt_burst)
3821 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3824 uint32_t reg_base = *reg_arr & 0xfffff000;
3828 for (i = 0; i < count; i++) {
3829 if ((reg_arr[i] & 0xfffff000) != reg_base)
3832 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3833 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3837 static int bnxt_map_ptp_regs(struct bnxt *bp)
3839 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3843 reg_arr = ptp->rx_regs;
3844 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3848 reg_arr = ptp->tx_regs;
3849 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3853 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3854 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3856 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3857 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3862 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3864 rte_write32(0, (uint8_t *)bp->bar0 +
3865 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3866 rte_write32(0, (uint8_t *)bp->bar0 +
3867 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3870 static uint64_t bnxt_cc_read(struct bnxt *bp)
3874 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3875 BNXT_GRCPF_REG_SYNC_TIME));
3876 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3877 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3881 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3883 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3886 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3887 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3888 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3891 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3892 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3893 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3894 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3895 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3896 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3901 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3903 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3904 struct bnxt_pf_info *pf = bp->pf;
3911 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3912 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3913 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3916 port_id = pf->port_id;
3917 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3918 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3920 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3921 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3922 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3923 /* bnxt_clr_rx_ts(bp); TBD */
3927 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3928 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3929 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3930 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3936 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3939 struct bnxt *bp = dev->data->dev_private;
3940 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3945 ns = rte_timespec_to_ns(ts);
3946 /* Set the timecounters to a new value. */
3953 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3955 struct bnxt *bp = dev->data->dev_private;
3956 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3957 uint64_t ns, systime_cycles = 0;
3963 if (BNXT_CHIP_THOR(bp))
3964 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3967 systime_cycles = bnxt_cc_read(bp);
3969 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3970 *ts = rte_ns_to_timespec(ns);
3975 bnxt_timesync_enable(struct rte_eth_dev *dev)
3977 struct bnxt *bp = dev->data->dev_private;
3978 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3986 ptp->tx_tstamp_en = 1;
3987 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3989 rc = bnxt_hwrm_ptp_cfg(bp);
3993 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3994 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3995 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3997 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3998 ptp->tc.cc_shift = shift;
3999 ptp->tc.nsec_mask = (1ULL << shift) - 1;
4001 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4002 ptp->rx_tstamp_tc.cc_shift = shift;
4003 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4005 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4006 ptp->tx_tstamp_tc.cc_shift = shift;
4007 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4009 if (!BNXT_CHIP_THOR(bp))
4010 bnxt_map_ptp_regs(bp);
4016 bnxt_timesync_disable(struct rte_eth_dev *dev)
4018 struct bnxt *bp = dev->data->dev_private;
4019 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4025 ptp->tx_tstamp_en = 0;
4028 bnxt_hwrm_ptp_cfg(bp);
4030 if (!BNXT_CHIP_THOR(bp))
4031 bnxt_unmap_ptp_regs(bp);
4037 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4038 struct timespec *timestamp,
4039 uint32_t flags __rte_unused)
4041 struct bnxt *bp = dev->data->dev_private;
4042 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4043 uint64_t rx_tstamp_cycles = 0;
4049 if (BNXT_CHIP_THOR(bp))
4050 rx_tstamp_cycles = ptp->rx_timestamp;
4052 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
4054 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
4055 *timestamp = rte_ns_to_timespec(ns);
4060 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4061 struct timespec *timestamp)
4063 struct bnxt *bp = dev->data->dev_private;
4064 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4065 uint64_t tx_tstamp_cycles = 0;
4072 if (BNXT_CHIP_THOR(bp))
4073 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4076 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4078 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4079 *timestamp = rte_ns_to_timespec(ns);
4085 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4087 struct bnxt *bp = dev->data->dev_private;
4088 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4093 ptp->tc.nsec += delta;
4099 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4101 struct bnxt *bp = dev->data->dev_private;
4103 uint32_t dir_entries;
4104 uint32_t entry_length;
4106 rc = is_bnxt_in_error(bp);
4110 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4111 bp->pdev->addr.domain, bp->pdev->addr.bus,
4112 bp->pdev->addr.devid, bp->pdev->addr.function);
4114 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4118 return dir_entries * entry_length;
4122 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4123 struct rte_dev_eeprom_info *in_eeprom)
4125 struct bnxt *bp = dev->data->dev_private;
4130 rc = is_bnxt_in_error(bp);
4134 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4135 bp->pdev->addr.domain, bp->pdev->addr.bus,
4136 bp->pdev->addr.devid, bp->pdev->addr.function,
4137 in_eeprom->offset, in_eeprom->length);
4139 if (in_eeprom->offset == 0) /* special offset value to get directory */
4140 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4143 index = in_eeprom->offset >> 24;
4144 offset = in_eeprom->offset & 0xffffff;
4147 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4148 in_eeprom->length, in_eeprom->data);
4153 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4156 case BNX_DIR_TYPE_CHIMP_PATCH:
4157 case BNX_DIR_TYPE_BOOTCODE:
4158 case BNX_DIR_TYPE_BOOTCODE_2:
4159 case BNX_DIR_TYPE_APE_FW:
4160 case BNX_DIR_TYPE_APE_PATCH:
4161 case BNX_DIR_TYPE_KONG_FW:
4162 case BNX_DIR_TYPE_KONG_PATCH:
4163 case BNX_DIR_TYPE_BONO_FW:
4164 case BNX_DIR_TYPE_BONO_PATCH:
4172 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4175 case BNX_DIR_TYPE_AVS:
4176 case BNX_DIR_TYPE_EXP_ROM_MBA:
4177 case BNX_DIR_TYPE_PCIE:
4178 case BNX_DIR_TYPE_TSCF_UCODE:
4179 case BNX_DIR_TYPE_EXT_PHY:
4180 case BNX_DIR_TYPE_CCM:
4181 case BNX_DIR_TYPE_ISCSI_BOOT:
4182 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4183 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4191 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4193 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4194 bnxt_dir_type_is_other_exec_format(dir_type);
4198 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4199 struct rte_dev_eeprom_info *in_eeprom)
4201 struct bnxt *bp = dev->data->dev_private;
4202 uint8_t index, dir_op;
4203 uint16_t type, ext, ordinal, attr;
4206 rc = is_bnxt_in_error(bp);
4210 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4211 bp->pdev->addr.domain, bp->pdev->addr.bus,
4212 bp->pdev->addr.devid, bp->pdev->addr.function,
4213 in_eeprom->offset, in_eeprom->length);
4216 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4220 type = in_eeprom->magic >> 16;
4222 if (type == 0xffff) { /* special value for directory operations */
4223 index = in_eeprom->magic & 0xff;
4224 dir_op = in_eeprom->magic >> 8;
4228 case 0x0e: /* erase */
4229 if (in_eeprom->offset != ~in_eeprom->magic)
4231 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4237 /* Create or re-write an NVM item: */
4238 if (bnxt_dir_type_is_executable(type) == true)
4240 ext = in_eeprom->magic & 0xffff;
4241 ordinal = in_eeprom->offset >> 16;
4242 attr = in_eeprom->offset & 0xffff;
4244 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4245 in_eeprom->data, in_eeprom->length);
4252 static const struct eth_dev_ops bnxt_dev_ops = {
4253 .dev_infos_get = bnxt_dev_info_get_op,
4254 .dev_close = bnxt_dev_close_op,
4255 .dev_configure = bnxt_dev_configure_op,
4256 .dev_start = bnxt_dev_start_op,
4257 .dev_stop = bnxt_dev_stop_op,
4258 .dev_set_link_up = bnxt_dev_set_link_up_op,
4259 .dev_set_link_down = bnxt_dev_set_link_down_op,
4260 .stats_get = bnxt_stats_get_op,
4261 .stats_reset = bnxt_stats_reset_op,
4262 .rx_queue_setup = bnxt_rx_queue_setup_op,
4263 .rx_queue_release = bnxt_rx_queue_release_op,
4264 .tx_queue_setup = bnxt_tx_queue_setup_op,
4265 .tx_queue_release = bnxt_tx_queue_release_op,
4266 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4267 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4268 .reta_update = bnxt_reta_update_op,
4269 .reta_query = bnxt_reta_query_op,
4270 .rss_hash_update = bnxt_rss_hash_update_op,
4271 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4272 .link_update = bnxt_link_update_op,
4273 .promiscuous_enable = bnxt_promiscuous_enable_op,
4274 .promiscuous_disable = bnxt_promiscuous_disable_op,
4275 .allmulticast_enable = bnxt_allmulticast_enable_op,
4276 .allmulticast_disable = bnxt_allmulticast_disable_op,
4277 .mac_addr_add = bnxt_mac_addr_add_op,
4278 .mac_addr_remove = bnxt_mac_addr_remove_op,
4279 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4280 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4281 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
4282 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
4283 .vlan_filter_set = bnxt_vlan_filter_set_op,
4284 .vlan_offload_set = bnxt_vlan_offload_set_op,
4285 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4286 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4287 .mtu_set = bnxt_mtu_set_op,
4288 .mac_addr_set = bnxt_set_default_mac_addr_op,
4289 .xstats_get = bnxt_dev_xstats_get_op,
4290 .xstats_get_names = bnxt_dev_xstats_get_names_op,
4291 .xstats_reset = bnxt_dev_xstats_reset_op,
4292 .fw_version_get = bnxt_fw_version_get,
4293 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4294 .rxq_info_get = bnxt_rxq_info_get_op,
4295 .txq_info_get = bnxt_txq_info_get_op,
4296 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4297 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4298 .dev_led_on = bnxt_dev_led_on_op,
4299 .dev_led_off = bnxt_dev_led_off_op,
4300 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4301 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4302 .rx_queue_count = bnxt_rx_queue_count_op,
4303 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
4304 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
4305 .rx_queue_start = bnxt_rx_queue_start,
4306 .rx_queue_stop = bnxt_rx_queue_stop,
4307 .tx_queue_start = bnxt_tx_queue_start,
4308 .tx_queue_stop = bnxt_tx_queue_stop,
4309 .filter_ctrl = bnxt_filter_ctrl_op,
4310 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4311 .get_eeprom_length = bnxt_get_eeprom_length_op,
4312 .get_eeprom = bnxt_get_eeprom_op,
4313 .set_eeprom = bnxt_set_eeprom_op,
4314 .timesync_enable = bnxt_timesync_enable,
4315 .timesync_disable = bnxt_timesync_disable,
4316 .timesync_read_time = bnxt_timesync_read_time,
4317 .timesync_write_time = bnxt_timesync_write_time,
4318 .timesync_adjust_time = bnxt_timesync_adjust_time,
4319 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4320 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4323 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4327 /* Only pre-map the reset GRC registers using window 3 */
4328 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4329 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4331 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4336 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4338 struct bnxt_error_recovery_info *info = bp->recovery_info;
4339 uint32_t reg_base = 0xffffffff;
4342 /* Only pre-map the monitoring GRC registers using window 2 */
4343 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4344 uint32_t reg = info->status_regs[i];
4346 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4349 if (reg_base == 0xffffffff)
4350 reg_base = reg & 0xfffff000;
4351 if ((reg & 0xfffff000) != reg_base)
4354 /* Use mask 0xffc as the Lower 2 bits indicates
4355 * address space location
4357 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4361 if (reg_base == 0xffffffff)
4364 rte_write32(reg_base, (uint8_t *)bp->bar0 +
4365 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4370 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4372 struct bnxt_error_recovery_info *info = bp->recovery_info;
4373 uint32_t delay = info->delay_after_reset[index];
4374 uint32_t val = info->reset_reg_val[index];
4375 uint32_t reg = info->reset_reg[index];
4376 uint32_t type, offset;
4378 type = BNXT_FW_STATUS_REG_TYPE(reg);
4379 offset = BNXT_FW_STATUS_REG_OFF(reg);
4382 case BNXT_FW_STATUS_REG_TYPE_CFG:
4383 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4385 case BNXT_FW_STATUS_REG_TYPE_GRC:
4386 offset = bnxt_map_reset_regs(bp, offset);
4387 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4389 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4390 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4393 /* wait on a specific interval of time until core reset is complete */
4395 rte_delay_ms(delay);
4398 static void bnxt_dev_cleanup(struct bnxt *bp)
4400 bnxt_set_hwrm_link_config(bp, false);
4401 bp->link_info->link_up = 0;
4402 if (bp->eth_dev->data->dev_started)
4403 bnxt_dev_stop_op(bp->eth_dev);
4405 bnxt_uninit_resources(bp, true);
4408 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4410 struct rte_eth_dev *dev = bp->eth_dev;
4411 struct rte_vlan_filter_conf *vfc;
4415 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4416 vfc = &dev->data->vlan_filter_conf;
4417 vidx = vlan_id / 64;
4418 vbit = vlan_id % 64;
4420 /* Each bit corresponds to a VLAN id */
4421 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4422 rc = bnxt_add_vlan_filter(bp, vlan_id);
4431 static int bnxt_restore_mac_filters(struct bnxt *bp)
4433 struct rte_eth_dev *dev = bp->eth_dev;
4434 struct rte_eth_dev_info dev_info;
4435 struct rte_ether_addr *addr;
4441 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
4444 rc = bnxt_dev_info_get_op(dev, &dev_info);
4448 /* replay MAC address configuration */
4449 for (i = 1; i < dev_info.max_mac_addrs; i++) {
4450 addr = &dev->data->mac_addrs[i];
4452 /* skip zero address */
4453 if (rte_is_zero_ether_addr(addr))
4457 pool_mask = dev->data->mac_pool_sel[i];
4460 if (pool_mask & 1ULL) {
4461 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4467 } while (pool_mask);
4473 static int bnxt_restore_filters(struct bnxt *bp)
4475 struct rte_eth_dev *dev = bp->eth_dev;
4478 if (dev->data->all_multicast) {
4479 ret = bnxt_allmulticast_enable_op(dev);
4483 if (dev->data->promiscuous) {
4484 ret = bnxt_promiscuous_enable_op(dev);
4489 ret = bnxt_restore_mac_filters(bp);
4493 ret = bnxt_restore_vlan_filters(bp);
4494 /* TODO restore other filters as well */
4498 static void bnxt_dev_recover(void *arg)
4500 struct bnxt *bp = arg;
4501 int timeout = bp->fw_reset_max_msecs;
4504 /* Clear Error flag so that device re-init should happen */
4505 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4508 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4511 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4512 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4513 } while (rc && timeout);
4516 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4520 rc = bnxt_init_resources(bp, true);
4523 "Failed to initialize resources after reset\n");
4526 /* clear reset flag as the device is initialized now */
4527 bp->flags &= ~BNXT_FLAG_FW_RESET;
4529 rc = bnxt_dev_start_op(bp->eth_dev);
4531 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4535 rc = bnxt_restore_filters(bp);
4539 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4542 bnxt_dev_stop_op(bp->eth_dev);
4544 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4545 bnxt_uninit_resources(bp, false);
4546 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4549 void bnxt_dev_reset_and_resume(void *arg)
4551 struct bnxt *bp = arg;
4554 bnxt_dev_cleanup(bp);
4556 bnxt_wait_for_device_shutdown(bp);
4558 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4559 bnxt_dev_recover, (void *)bp);
4561 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4564 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4566 struct bnxt_error_recovery_info *info = bp->recovery_info;
4567 uint32_t reg = info->status_regs[index];
4568 uint32_t type, offset, val = 0;
4570 type = BNXT_FW_STATUS_REG_TYPE(reg);
4571 offset = BNXT_FW_STATUS_REG_OFF(reg);
4574 case BNXT_FW_STATUS_REG_TYPE_CFG:
4575 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4577 case BNXT_FW_STATUS_REG_TYPE_GRC:
4578 offset = info->mapped_status_regs[index];
4580 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4581 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4589 static int bnxt_fw_reset_all(struct bnxt *bp)
4591 struct bnxt_error_recovery_info *info = bp->recovery_info;
4595 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4596 /* Reset through master function driver */
4597 for (i = 0; i < info->reg_array_cnt; i++)
4598 bnxt_write_fw_reset_reg(bp, i);
4599 /* Wait for time specified by FW after triggering reset */
4600 rte_delay_ms(info->master_func_wait_period_after_reset);
4601 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4602 /* Reset with the help of Kong processor */
4603 rc = bnxt_hwrm_fw_reset(bp);
4605 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4611 static void bnxt_fw_reset_cb(void *arg)
4613 struct bnxt *bp = arg;
4614 struct bnxt_error_recovery_info *info = bp->recovery_info;
4617 /* Only Master function can do FW reset */
4618 if (bnxt_is_master_func(bp) &&
4619 bnxt_is_recovery_enabled(bp)) {
4620 rc = bnxt_fw_reset_all(bp);
4622 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4627 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4628 * EXCEPTION_FATAL_ASYNC event to all the functions
4629 * (including MASTER FUNC). After receiving this Async, all the active
4630 * drivers should treat this case as FW initiated recovery
4632 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4633 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4634 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4636 /* To recover from error */
4637 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4642 /* Driver should poll FW heartbeat, reset_counter with the frequency
4643 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4644 * When the driver detects heartbeat stop or change in reset_counter,
4645 * it has to trigger a reset to recover from the error condition.
4646 * A “master PF” is the function who will have the privilege to
4647 * initiate the chimp reset. The master PF will be elected by the
4648 * firmware and will be notified through async message.
4650 static void bnxt_check_fw_health(void *arg)
4652 struct bnxt *bp = arg;
4653 struct bnxt_error_recovery_info *info = bp->recovery_info;
4654 uint32_t val = 0, wait_msec;
4656 if (!info || !bnxt_is_recovery_enabled(bp) ||
4657 is_bnxt_in_error(bp))
4660 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4661 if (val == info->last_heart_beat)
4664 info->last_heart_beat = val;
4666 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4667 if (val != info->last_reset_counter)
4670 info->last_reset_counter = val;
4672 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4673 bnxt_check_fw_health, (void *)bp);
4677 /* Stop DMA to/from device */
4678 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4679 bp->flags |= BNXT_FLAG_FW_RESET;
4681 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4683 if (bnxt_is_master_func(bp))
4684 wait_msec = info->master_func_wait_period;
4686 wait_msec = info->normal_func_wait_period;
4688 rte_eal_alarm_set(US_PER_MS * wait_msec,
4689 bnxt_fw_reset_cb, (void *)bp);
4692 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4694 uint32_t polling_freq;
4696 if (!bnxt_is_recovery_enabled(bp))
4699 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4702 polling_freq = bp->recovery_info->driver_polling_freq;
4704 rte_eal_alarm_set(US_PER_MS * polling_freq,
4705 bnxt_check_fw_health, (void *)bp);
4706 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4709 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4711 if (!bnxt_is_recovery_enabled(bp))
4714 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4715 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4718 static bool bnxt_vf_pciid(uint16_t device_id)
4720 switch (device_id) {
4721 case BROADCOM_DEV_ID_57304_VF:
4722 case BROADCOM_DEV_ID_57406_VF:
4723 case BROADCOM_DEV_ID_5731X_VF:
4724 case BROADCOM_DEV_ID_5741X_VF:
4725 case BROADCOM_DEV_ID_57414_VF:
4726 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4727 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4728 case BROADCOM_DEV_ID_58802_VF:
4729 case BROADCOM_DEV_ID_57500_VF1:
4730 case BROADCOM_DEV_ID_57500_VF2:
4738 static bool bnxt_thor_device(uint16_t device_id)
4740 switch (device_id) {
4741 case BROADCOM_DEV_ID_57508:
4742 case BROADCOM_DEV_ID_57504:
4743 case BROADCOM_DEV_ID_57502:
4744 case BROADCOM_DEV_ID_57508_MF1:
4745 case BROADCOM_DEV_ID_57504_MF1:
4746 case BROADCOM_DEV_ID_57502_MF1:
4747 case BROADCOM_DEV_ID_57508_MF2:
4748 case BROADCOM_DEV_ID_57504_MF2:
4749 case BROADCOM_DEV_ID_57502_MF2:
4750 case BROADCOM_DEV_ID_57500_VF1:
4751 case BROADCOM_DEV_ID_57500_VF2:
4759 bool bnxt_stratus_device(struct bnxt *bp)
4761 uint16_t device_id = bp->pdev->id.device_id;
4763 switch (device_id) {
4764 case BROADCOM_DEV_ID_STRATUS_NIC:
4765 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4766 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4774 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4776 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4777 struct bnxt *bp = eth_dev->data->dev_private;
4779 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4780 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4781 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4782 if (!bp->bar0 || !bp->doorbell_base) {
4783 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4787 bp->eth_dev = eth_dev;
4793 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4794 struct bnxt_ctx_pg_info *ctx_pg,
4799 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4800 const struct rte_memzone *mz = NULL;
4801 char mz_name[RTE_MEMZONE_NAMESIZE];
4802 rte_iova_t mz_phys_addr;
4803 uint64_t valid_bits = 0;
4810 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4812 rmem->page_size = BNXT_PAGE_SIZE;
4813 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4814 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4815 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4817 valid_bits = PTU_PTE_VALID;
4819 if (rmem->nr_pages > 1) {
4820 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4821 "bnxt_ctx_pg_tbl%s_%x_%d",
4822 suffix, idx, bp->eth_dev->data->port_id);
4823 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4824 mz = rte_memzone_lookup(mz_name);
4826 mz = rte_memzone_reserve_aligned(mz_name,
4830 RTE_MEMZONE_SIZE_HINT_ONLY |
4831 RTE_MEMZONE_IOVA_CONTIG,
4837 memset(mz->addr, 0, mz->len);
4838 mz_phys_addr = mz->iova;
4840 rmem->pg_tbl = mz->addr;
4841 rmem->pg_tbl_map = mz_phys_addr;
4842 rmem->pg_tbl_mz = mz;
4845 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4846 suffix, idx, bp->eth_dev->data->port_id);
4847 mz = rte_memzone_lookup(mz_name);
4849 mz = rte_memzone_reserve_aligned(mz_name,
4853 RTE_MEMZONE_SIZE_HINT_ONLY |
4854 RTE_MEMZONE_IOVA_CONTIG,
4860 memset(mz->addr, 0, mz->len);
4861 mz_phys_addr = mz->iova;
4863 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4864 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4865 rmem->dma_arr[i] = mz_phys_addr + sz;
4867 if (rmem->nr_pages > 1) {
4868 if (i == rmem->nr_pages - 2 &&
4869 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4870 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4871 else if (i == rmem->nr_pages - 1 &&
4872 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4873 valid_bits |= PTU_PTE_LAST;
4875 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4881 if (rmem->vmem_size)
4882 rmem->vmem = (void **)mz->addr;
4883 rmem->dma_arr[0] = mz_phys_addr;
4887 static void bnxt_free_ctx_mem(struct bnxt *bp)
4891 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4894 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4895 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4896 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4897 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4898 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4899 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4900 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4901 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4902 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4903 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4904 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4906 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4907 if (bp->ctx->tqm_mem[i])
4908 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4915 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4917 #define min_t(type, x, y) ({ \
4918 type __min1 = (x); \
4919 type __min2 = (y); \
4920 __min1 < __min2 ? __min1 : __min2; })
4922 #define max_t(type, x, y) ({ \
4923 type __max1 = (x); \
4924 type __max2 = (y); \
4925 __max1 > __max2 ? __max1 : __max2; })
4927 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4929 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4931 struct bnxt_ctx_pg_info *ctx_pg;
4932 struct bnxt_ctx_mem_info *ctx;
4933 uint32_t mem_size, ena, entries;
4934 uint32_t entries_sp, min;
4937 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4939 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4943 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4946 ctx_pg = &ctx->qp_mem;
4947 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4948 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4949 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4953 ctx_pg = &ctx->srq_mem;
4954 ctx_pg->entries = ctx->srq_max_l2_entries;
4955 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4956 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4960 ctx_pg = &ctx->cq_mem;
4961 ctx_pg->entries = ctx->cq_max_l2_entries;
4962 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4963 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4967 ctx_pg = &ctx->vnic_mem;
4968 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4969 ctx->vnic_max_ring_table_entries;
4970 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4971 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4975 ctx_pg = &ctx->stat_mem;
4976 ctx_pg->entries = ctx->stat_max_entries;
4977 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4978 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4982 min = ctx->tqm_min_entries_per_ring;
4984 entries_sp = ctx->qp_max_l2_entries +
4985 ctx->vnic_max_vnic_entries +
4986 2 * ctx->qp_min_qp1_entries + min;
4987 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4989 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4990 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4991 entries = clamp_t(uint32_t, entries, min,
4992 ctx->tqm_max_entries_per_ring);
4993 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4994 ctx_pg = ctx->tqm_mem[i];
4995 ctx_pg->entries = i ? entries : entries_sp;
4996 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4997 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
5000 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
5003 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
5004 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
5007 "Failed to configure context mem: rc = %d\n", rc);
5009 ctx->flags |= BNXT_CTX_FLAG_INITED;
5014 static int bnxt_alloc_stats_mem(struct bnxt *bp)
5016 struct rte_pci_device *pci_dev = bp->pdev;
5017 char mz_name[RTE_MEMZONE_NAMESIZE];
5018 const struct rte_memzone *mz = NULL;
5019 uint32_t total_alloc_len;
5020 rte_iova_t mz_phys_addr;
5022 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
5025 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5026 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5027 pci_dev->addr.bus, pci_dev->addr.devid,
5028 pci_dev->addr.function, "rx_port_stats");
5029 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5030 mz = rte_memzone_lookup(mz_name);
5032 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
5033 sizeof(struct rx_port_stats_ext) + 512);
5035 mz = rte_memzone_reserve(mz_name, total_alloc_len,
5038 RTE_MEMZONE_SIZE_HINT_ONLY |
5039 RTE_MEMZONE_IOVA_CONTIG);
5043 memset(mz->addr, 0, mz->len);
5044 mz_phys_addr = mz->iova;
5046 bp->rx_mem_zone = (const void *)mz;
5047 bp->hw_rx_port_stats = mz->addr;
5048 bp->hw_rx_port_stats_map = mz_phys_addr;
5050 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5051 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5052 pci_dev->addr.bus, pci_dev->addr.devid,
5053 pci_dev->addr.function, "tx_port_stats");
5054 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5055 mz = rte_memzone_lookup(mz_name);
5057 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
5058 sizeof(struct tx_port_stats_ext) + 512);
5060 mz = rte_memzone_reserve(mz_name,
5064 RTE_MEMZONE_SIZE_HINT_ONLY |
5065 RTE_MEMZONE_IOVA_CONTIG);
5069 memset(mz->addr, 0, mz->len);
5070 mz_phys_addr = mz->iova;
5072 bp->tx_mem_zone = (const void *)mz;
5073 bp->hw_tx_port_stats = mz->addr;
5074 bp->hw_tx_port_stats_map = mz_phys_addr;
5075 bp->flags |= BNXT_FLAG_PORT_STATS;
5077 /* Display extended statistics if FW supports it */
5078 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5079 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5080 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5083 bp->hw_rx_port_stats_ext = (void *)
5084 ((uint8_t *)bp->hw_rx_port_stats +
5085 sizeof(struct rx_port_stats));
5086 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5087 sizeof(struct rx_port_stats);
5088 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5090 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5091 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5092 bp->hw_tx_port_stats_ext = (void *)
5093 ((uint8_t *)bp->hw_tx_port_stats +
5094 sizeof(struct tx_port_stats));
5095 bp->hw_tx_port_stats_ext_map =
5096 bp->hw_tx_port_stats_map +
5097 sizeof(struct tx_port_stats);
5098 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5104 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5106 struct bnxt *bp = eth_dev->data->dev_private;
5109 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5110 RTE_ETHER_ADDR_LEN *
5113 if (eth_dev->data->mac_addrs == NULL) {
5114 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5118 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5122 /* Generate a random MAC address, if none was assigned by PF */
5123 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5124 bnxt_eth_hw_addr_random(bp->mac_addr);
5126 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5127 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5128 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5130 rc = bnxt_hwrm_set_mac(bp);
5135 /* Copy the permanent MAC from the FUNC_QCAPS response */
5136 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5141 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5145 /* MAC is already configured in FW */
5146 if (BNXT_HAS_DFLT_MAC_SET(bp))
5149 /* Restore the old MAC configured */
5150 rc = bnxt_hwrm_set_mac(bp);
5152 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5157 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5162 #define ALLOW_FUNC(x) \
5164 uint32_t arg = (x); \
5165 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5166 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5169 /* Forward all requests if firmware is new enough */
5170 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5171 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5172 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5173 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5175 PMD_DRV_LOG(WARNING,
5176 "Firmware too old for VF mailbox functionality\n");
5177 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5181 * The following are used for driver cleanup. If we disallow these,
5182 * VF drivers can't clean up cleanly.
5184 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5185 ALLOW_FUNC(HWRM_VNIC_FREE);
5186 ALLOW_FUNC(HWRM_RING_FREE);
5187 ALLOW_FUNC(HWRM_RING_GRP_FREE);
5188 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5189 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5190 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5191 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5192 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5196 bnxt_get_svif(uint16_t port_id, bool func_svif,
5197 enum bnxt_ulp_intf_type type)
5199 struct rte_eth_dev *eth_dev;
5202 eth_dev = &rte_eth_devices[port_id];
5203 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5204 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5208 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5211 eth_dev = vfr->parent_dev;
5214 bp = eth_dev->data->dev_private;
5216 return func_svif ? bp->func_svif : bp->port_svif;
5220 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5222 struct rte_eth_dev *eth_dev;
5223 struct bnxt_vnic_info *vnic;
5226 eth_dev = &rte_eth_devices[port];
5227 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5228 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5232 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5233 return vfr->dflt_vnic_id;
5235 eth_dev = vfr->parent_dev;
5238 bp = eth_dev->data->dev_private;
5240 vnic = BNXT_GET_DEFAULT_VNIC(bp);
5242 return vnic->fw_vnic_id;
5246 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5248 struct rte_eth_dev *eth_dev;
5251 eth_dev = &rte_eth_devices[port];
5252 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5253 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5257 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5260 eth_dev = vfr->parent_dev;
5263 bp = eth_dev->data->dev_private;
5268 enum bnxt_ulp_intf_type
5269 bnxt_get_interface_type(uint16_t port)
5271 struct rte_eth_dev *eth_dev;
5274 eth_dev = &rte_eth_devices[port];
5275 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5276 return BNXT_ULP_INTF_TYPE_VF_REP;
5278 bp = eth_dev->data->dev_private;
5280 return BNXT_ULP_INTF_TYPE_PF;
5281 else if (BNXT_VF_IS_TRUSTED(bp))
5282 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5283 else if (BNXT_VF(bp))
5284 return BNXT_ULP_INTF_TYPE_VF;
5286 return BNXT_ULP_INTF_TYPE_INVALID;
5290 bnxt_get_phy_port_id(uint16_t port_id)
5292 struct bnxt_vf_representor *vfr;
5293 struct rte_eth_dev *eth_dev;
5296 eth_dev = &rte_eth_devices[port_id];
5297 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5298 vfr = eth_dev->data->dev_private;
5302 eth_dev = vfr->parent_dev;
5305 bp = eth_dev->data->dev_private;
5307 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5311 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5313 struct rte_eth_dev *eth_dev;
5316 eth_dev = &rte_eth_devices[port_id];
5317 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5318 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5322 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5323 return vfr->fw_fid - 1;
5325 eth_dev = vfr->parent_dev;
5328 bp = eth_dev->data->dev_private;
5330 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5334 bnxt_get_vport(uint16_t port_id)
5336 return (1 << bnxt_get_phy_port_id(port_id));
5339 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5341 struct bnxt_error_recovery_info *info = bp->recovery_info;
5344 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5345 memset(info, 0, sizeof(*info));
5349 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5352 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5355 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5357 bp->recovery_info = info;
5360 static void bnxt_check_fw_status(struct bnxt *bp)
5364 if (!(bp->recovery_info &&
5365 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5368 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5369 if (fw_status != BNXT_FW_STATUS_HEALTHY)
5370 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5374 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5376 struct bnxt_error_recovery_info *info = bp->recovery_info;
5377 uint32_t status_loc;
5380 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5381 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5382 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5383 BNXT_GRCP_WINDOW_2_BASE +
5384 offsetof(struct hcomm_status,
5386 /* If the signature is absent, then FW does not support this feature */
5387 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5388 HCOMM_STATUS_SIGNATURE_VAL)
5392 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5396 bp->recovery_info = info;
5398 memset(info, 0, sizeof(*info));
5401 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5402 BNXT_GRCP_WINDOW_2_BASE +
5403 offsetof(struct hcomm_status,
5406 /* Only pre-map the FW health status GRC register */
5407 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5410 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5411 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5412 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5414 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5415 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5417 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5422 static int bnxt_init_fw(struct bnxt *bp)
5429 rc = bnxt_map_hcomm_fw_status_reg(bp);
5433 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5435 bnxt_check_fw_status(bp);
5439 rc = bnxt_hwrm_func_reset(bp);
5443 rc = bnxt_hwrm_vnic_qcaps(bp);
5447 rc = bnxt_hwrm_queue_qportcfg(bp);
5451 /* Get the MAX capabilities for this function.
5452 * This function also allocates context memory for TQM rings and
5453 * informs the firmware about this allocated backing store memory.
5455 rc = bnxt_hwrm_func_qcaps(bp);
5459 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5463 bnxt_hwrm_port_mac_qcfg(bp);
5465 bnxt_hwrm_parent_pf_qcfg(bp);
5467 bnxt_hwrm_port_phy_qcaps(bp);
5469 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5473 bnxt_alloc_error_recovery_info(bp);
5474 /* Get the adapter error recovery support info */
5475 rc = bnxt_hwrm_error_recovery_qcfg(bp);
5477 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5479 bnxt_hwrm_port_led_qcaps(bp);
5485 bnxt_init_locks(struct bnxt *bp)
5489 err = pthread_mutex_init(&bp->flow_lock, NULL);
5491 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5495 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5497 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5501 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5505 rc = bnxt_init_fw(bp);
5509 if (!reconfig_dev) {
5510 rc = bnxt_setup_mac_addr(bp->eth_dev);
5514 rc = bnxt_restore_dflt_mac(bp);
5519 bnxt_config_vf_req_fwd(bp);
5521 rc = bnxt_hwrm_func_driver_register(bp);
5523 PMD_DRV_LOG(ERR, "Failed to register driver");
5528 if (bp->pdev->max_vfs) {
5529 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5531 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5535 rc = bnxt_hwrm_allocate_pf_only(bp);
5538 "Failed to allocate PF resources");
5544 rc = bnxt_alloc_mem(bp, reconfig_dev);
5548 rc = bnxt_setup_int(bp);
5552 rc = bnxt_request_int(bp);
5556 rc = bnxt_init_ctx_mem(bp);
5558 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5562 rc = bnxt_init_locks(bp);
5570 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5571 const char *value, void *opaque_arg)
5573 struct bnxt *bp = opaque_arg;
5574 unsigned long truflow;
5577 if (!value || !opaque_arg) {
5579 "Invalid parameter passed to truflow devargs.\n");
5583 truflow = strtoul(value, &end, 10);
5584 if (end == NULL || *end != '\0' ||
5585 (truflow == ULONG_MAX && errno == ERANGE)) {
5587 "Invalid parameter passed to truflow devargs.\n");
5591 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5593 "Invalid value passed to truflow devargs.\n");
5597 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5598 if (BNXT_TRUFLOW_EN(bp))
5599 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5605 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5606 const char *value, void *opaque_arg)
5608 struct bnxt *bp = opaque_arg;
5609 unsigned long flow_xstat;
5612 if (!value || !opaque_arg) {
5614 "Invalid parameter passed to flow_xstat devarg.\n");
5618 flow_xstat = strtoul(value, &end, 10);
5619 if (end == NULL || *end != '\0' ||
5620 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5622 "Invalid parameter passed to flow_xstat devarg.\n");
5626 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5628 "Invalid value passed to flow_xstat devarg.\n");
5632 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5633 if (BNXT_FLOW_XSTATS_EN(bp))
5634 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5640 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5641 const char *value, void *opaque_arg)
5643 struct bnxt *bp = opaque_arg;
5644 unsigned long max_num_kflows;
5647 if (!value || !opaque_arg) {
5649 "Invalid parameter passed to max_num_kflows devarg.\n");
5653 max_num_kflows = strtoul(value, &end, 10);
5654 if (end == NULL || *end != '\0' ||
5655 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5657 "Invalid parameter passed to max_num_kflows devarg.\n");
5661 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5663 "Invalid value passed to max_num_kflows devarg.\n");
5667 bp->max_num_kflows = max_num_kflows;
5668 if (bp->max_num_kflows)
5669 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5676 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5678 struct rte_kvargs *kvlist;
5680 if (devargs == NULL)
5683 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5688 * Handler for "truflow" devarg.
5689 * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5691 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5692 bnxt_parse_devarg_truflow, bp);
5695 * Handler for "flow_xstat" devarg.
5696 * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5698 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5699 bnxt_parse_devarg_flow_xstat, bp);
5702 * Handler for "max_num_kflows" devarg.
5703 * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5705 rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5706 bnxt_parse_devarg_max_num_kflows, bp);
5708 rte_kvargs_free(kvlist);
5711 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5715 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5716 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5719 "Failed to alloc switch domain: %d\n", rc);
5722 "Switch domain allocated %d\n",
5723 bp->switch_domain_id);
5730 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5732 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5733 static int version_printed;
5737 if (version_printed++ == 0)
5738 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5740 eth_dev->dev_ops = &bnxt_dev_ops;
5741 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5742 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5745 * For secondary processes, we don't initialise any further
5746 * as primary has already done this work.
5748 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5751 rte_eth_copy_pci_info(eth_dev, pci_dev);
5753 bp = eth_dev->data->dev_private;
5755 /* Parse dev arguments passed on when starting the DPDK application. */
5756 bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5758 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5760 if (bnxt_vf_pciid(pci_dev->id.device_id))
5761 bp->flags |= BNXT_FLAG_VF;
5763 if (bnxt_thor_device(pci_dev->id.device_id))
5764 bp->flags |= BNXT_FLAG_THOR_CHIP;
5766 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5767 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5768 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5769 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5770 bp->flags |= BNXT_FLAG_STINGRAY;
5772 rc = bnxt_init_board(eth_dev);
5775 "Failed to initialize board rc: %x\n", rc);
5779 rc = bnxt_alloc_pf_info(bp);
5783 rc = bnxt_alloc_link_info(bp);
5787 rc = bnxt_alloc_parent_info(bp);
5791 rc = bnxt_alloc_hwrm_resources(bp);
5794 "Failed to allocate hwrm resource rc: %x\n", rc);
5797 rc = bnxt_alloc_leds_info(bp);
5801 rc = bnxt_alloc_cos_queues(bp);
5805 rc = bnxt_init_resources(bp, false);
5809 rc = bnxt_alloc_stats_mem(bp);
5813 bnxt_alloc_switch_domain(bp);
5815 /* Pass the information to the rte_eth_dev_close() that it should also
5816 * release the private port resources.
5818 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5821 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5822 pci_dev->mem_resource[0].phys_addr,
5823 pci_dev->mem_resource[0].addr);
5828 bnxt_dev_uninit(eth_dev);
5833 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5842 ctx->dma = RTE_BAD_IOVA;
5843 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5846 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5848 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5849 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5850 bp->flow_stat->rx_fc_out_tbl.ctx_id,
5851 bp->flow_stat->max_fc,
5854 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5855 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5856 bp->flow_stat->tx_fc_out_tbl.ctx_id,
5857 bp->flow_stat->max_fc,
5860 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5861 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5862 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5864 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5865 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5866 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5868 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5869 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5870 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5872 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5873 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5874 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5877 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5879 bnxt_unregister_fc_ctx_mem(bp);
5881 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5882 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5883 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5884 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5887 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5889 if (BNXT_FLOW_XSTATS_EN(bp))
5890 bnxt_uninit_fc_ctx_mem(bp);
5894 bnxt_free_error_recovery_info(struct bnxt *bp)
5896 rte_free(bp->recovery_info);
5897 bp->recovery_info = NULL;
5898 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5902 bnxt_uninit_locks(struct bnxt *bp)
5904 pthread_mutex_destroy(&bp->flow_lock);
5905 pthread_mutex_destroy(&bp->def_cp_lock);
5907 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5911 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5916 bnxt_free_mem(bp, reconfig_dev);
5917 bnxt_hwrm_func_buf_unrgtr(bp);
5918 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5919 bp->flags &= ~BNXT_FLAG_REGISTERED;
5920 bnxt_free_ctx_mem(bp);
5921 if (!reconfig_dev) {
5922 bnxt_free_hwrm_resources(bp);
5923 bnxt_free_error_recovery_info(bp);
5926 bnxt_uninit_ctx_mem(bp);
5928 bnxt_uninit_locks(bp);
5929 bnxt_free_flow_stats_info(bp);
5930 bnxt_free_rep_info(bp);
5931 rte_free(bp->ptp_cfg);
5937 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5939 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5942 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5944 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5945 bnxt_dev_close_op(eth_dev);
5950 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5952 struct bnxt *bp = eth_dev->data->dev_private;
5953 struct rte_eth_dev *vf_rep_eth_dev;
5959 for (i = 0; i < bp->num_reps; i++) {
5960 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5961 if (!vf_rep_eth_dev)
5963 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_vf_representor_uninit);
5965 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5970 static void bnxt_free_rep_info(struct bnxt *bp)
5972 rte_free(bp->rep_info);
5973 bp->rep_info = NULL;
5974 rte_free(bp->cfa_code_map);
5975 bp->cfa_code_map = NULL;
5978 static int bnxt_init_rep_info(struct bnxt *bp)
5985 bp->rep_info = rte_zmalloc("bnxt_rep_info",
5986 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5988 if (!bp->rep_info) {
5989 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5992 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5993 sizeof(*bp->cfa_code_map) *
5994 BNXT_MAX_CFA_CODE, 0);
5995 if (!bp->cfa_code_map) {
5996 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5997 bnxt_free_rep_info(bp);
6001 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6002 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6004 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6006 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6007 bnxt_free_rep_info(bp);
6013 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6014 struct rte_eth_devargs eth_da,
6015 struct rte_eth_dev *backing_eth_dev)
6017 struct rte_eth_dev *vf_rep_eth_dev;
6018 char name[RTE_ETH_NAME_MAX_LEN];
6019 struct bnxt *backing_bp;
6023 num_rep = eth_da.nb_representor_ports;
6024 if (num_rep > BNXT_MAX_VF_REPS) {
6025 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6026 num_rep, BNXT_MAX_VF_REPS);
6030 if (num_rep > RTE_MAX_ETHPORTS) {
6032 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6033 num_rep, RTE_MAX_ETHPORTS);
6037 backing_bp = backing_eth_dev->data->dev_private;
6039 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6041 "Not a PF or trusted VF. No Representor support\n");
6042 /* Returning an error is not an option.
6043 * Applications are not handling this correctly
6048 if (bnxt_init_rep_info(backing_bp))
6051 for (i = 0; i < num_rep; i++) {
6052 struct bnxt_vf_representor representor = {
6053 .vf_id = eth_da.representor_ports[i],
6054 .switch_domain_id = backing_bp->switch_domain_id,
6055 .parent_dev = backing_eth_dev
6058 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6059 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6060 representor.vf_id, BNXT_MAX_VF_REPS);
6064 /* representor port net_bdf_port */
6065 snprintf(name, sizeof(name), "net_%s_representor_%d",
6066 pci_dev->device.name, eth_da.representor_ports[i]);
6068 ret = rte_eth_dev_create(&pci_dev->device, name,
6069 sizeof(struct bnxt_vf_representor),
6071 bnxt_vf_representor_init,
6075 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6076 if (!vf_rep_eth_dev) {
6077 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6078 " for VF-Rep: %s.", name);
6079 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6083 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6085 backing_bp->num_reps++;
6087 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6088 "representor %s.", name);
6089 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6096 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6097 struct rte_pci_device *pci_dev)
6099 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6100 struct rte_eth_dev *backing_eth_dev;
6104 if (pci_dev->device.devargs) {
6105 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6111 num_rep = eth_da.nb_representor_ports;
6112 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6115 /* We could come here after first level of probe is already invoked
6116 * as part of an application bringup(OVS-DPDK vswitchd), so first check
6117 * for already allocated eth_dev for the backing device (PF/Trusted VF)
6119 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6120 if (backing_eth_dev == NULL) {
6121 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6122 sizeof(struct bnxt),
6123 eth_dev_pci_specific_init, pci_dev,
6124 bnxt_dev_init, NULL);
6126 if (ret || !num_rep)
6129 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6132 /* probe representor ports now */
6133 ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev);
6138 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6140 struct rte_eth_dev *eth_dev;
6142 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6144 return 0; /* Invoked typically only by OVS-DPDK, by the
6145 * time it comes here the eth_dev is already
6146 * deleted by rte_eth_dev_close(), so returning
6147 * +ve value will at least help in proper cleanup
6150 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6151 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6152 return rte_eth_dev_destroy(eth_dev,
6153 bnxt_vf_representor_uninit);
6155 return rte_eth_dev_destroy(eth_dev,
6158 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6162 static struct rte_pci_driver bnxt_rte_pmd = {
6163 .id_table = bnxt_pci_id_map,
6164 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6165 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6168 .probe = bnxt_pci_probe,
6169 .remove = bnxt_pci_remove,
6173 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6175 if (strcmp(dev->device->driver->name, drv->driver.name))
6181 bool is_bnxt_supported(struct rte_eth_dev *dev)
6183 return is_device_supported(dev, &bnxt_rte_pmd);
6186 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6187 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6188 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6189 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");