1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
18 #include "bnxt_filter.h"
19 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_stats.h"
27 #include "bnxt_vnic.h"
28 #include "hsi_struct_def_dpdk.h"
29 #include "bnxt_nvm_defs.h"
30 #include "bnxt_util.h"
32 #define DRV_MODULE_NAME "bnxt"
33 static const char bnxt_version[] =
34 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
35 int bnxt_logtype_driver;
37 #define PCI_VENDOR_ID_BROADCOM 0x14E4
39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
40 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
41 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
42 #define BROADCOM_DEV_ID_57414_VF 0x16c1
43 #define BROADCOM_DEV_ID_57301 0x16c8
44 #define BROADCOM_DEV_ID_57302 0x16c9
45 #define BROADCOM_DEV_ID_57304_PF 0x16ca
46 #define BROADCOM_DEV_ID_57304_VF 0x16cb
47 #define BROADCOM_DEV_ID_57417_MF 0x16cc
48 #define BROADCOM_DEV_ID_NS2 0x16cd
49 #define BROADCOM_DEV_ID_57311 0x16ce
50 #define BROADCOM_DEV_ID_57312 0x16cf
51 #define BROADCOM_DEV_ID_57402 0x16d0
52 #define BROADCOM_DEV_ID_57404 0x16d1
53 #define BROADCOM_DEV_ID_57406_PF 0x16d2
54 #define BROADCOM_DEV_ID_57406_VF 0x16d3
55 #define BROADCOM_DEV_ID_57402_MF 0x16d4
56 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
57 #define BROADCOM_DEV_ID_57412 0x16d6
58 #define BROADCOM_DEV_ID_57414 0x16d7
59 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
60 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
61 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
62 #define BROADCOM_DEV_ID_57412_MF 0x16de
63 #define BROADCOM_DEV_ID_57314 0x16df
64 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
65 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
66 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
67 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
68 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
69 #define BROADCOM_DEV_ID_57404_MF 0x16e7
70 #define BROADCOM_DEV_ID_57406_MF 0x16e8
71 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
72 #define BROADCOM_DEV_ID_57407_MF 0x16ea
73 #define BROADCOM_DEV_ID_57414_MF 0x16ec
74 #define BROADCOM_DEV_ID_57416_MF 0x16ee
75 #define BROADCOM_DEV_ID_57508 0x1750
76 #define BROADCOM_DEV_ID_57504 0x1751
77 #define BROADCOM_DEV_ID_57502 0x1752
78 #define BROADCOM_DEV_ID_57500_VF1 0x1806
79 #define BROADCOM_DEV_ID_57500_VF2 0x1807
80 #define BROADCOM_DEV_ID_58802 0xd802
81 #define BROADCOM_DEV_ID_58804 0xd804
82 #define BROADCOM_DEV_ID_58808 0x16f0
83 #define BROADCOM_DEV_ID_58802_VF 0xd800
85 static const struct rte_pci_id bnxt_pci_id_map[] = {
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
87 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
89 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
130 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
131 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
132 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
133 { .vendor_id = 0, /* sentinel */ },
136 #define BNXT_ETH_RSS_SUPPORT ( \
138 ETH_RSS_NONFRAG_IPV4_TCP | \
139 ETH_RSS_NONFRAG_IPV4_UDP | \
141 ETH_RSS_NONFRAG_IPV6_TCP | \
142 ETH_RSS_NONFRAG_IPV6_UDP)
144 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
145 DEV_TX_OFFLOAD_IPV4_CKSUM | \
146 DEV_TX_OFFLOAD_TCP_CKSUM | \
147 DEV_TX_OFFLOAD_UDP_CKSUM | \
148 DEV_TX_OFFLOAD_TCP_TSO | \
149 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
150 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
151 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
152 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
153 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
154 DEV_TX_OFFLOAD_MULTI_SEGS)
156 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
157 DEV_RX_OFFLOAD_VLAN_STRIP | \
158 DEV_RX_OFFLOAD_IPV4_CKSUM | \
159 DEV_RX_OFFLOAD_UDP_CKSUM | \
160 DEV_RX_OFFLOAD_TCP_CKSUM | \
161 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
162 DEV_RX_OFFLOAD_JUMBO_FRAME | \
163 DEV_RX_OFFLOAD_KEEP_CRC | \
164 DEV_RX_OFFLOAD_TCP_LRO)
166 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
167 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
168 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
169 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
170 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
171 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
173 int is_bnxt_in_error(struct bnxt *bp)
175 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
177 if (bp->flags & BNXT_FLAG_FW_RESET)
183 /***********************/
186 * High level utility functions
189 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
191 if (!BNXT_CHIP_THOR(bp))
194 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
195 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
196 BNXT_RSS_ENTRIES_PER_CTX_THOR;
199 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
201 if (!BNXT_CHIP_THOR(bp))
202 return HW_HASH_INDEX_SIZE;
204 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
207 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
209 bnxt_free_filter_mem(bp);
210 bnxt_free_vnic_attributes(bp);
211 bnxt_free_vnic_mem(bp);
213 /* tx/rx rings are configured as part of *_queue_setup callbacks.
214 * If the number of rings change across fw update,
215 * we don't have much choice except to warn the user.
219 bnxt_free_tx_rings(bp);
220 bnxt_free_rx_rings(bp);
222 bnxt_free_async_cp_ring(bp);
225 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
229 rc = bnxt_alloc_ring_grps(bp);
233 rc = bnxt_alloc_async_ring_struct(bp);
237 rc = bnxt_alloc_vnic_mem(bp);
241 rc = bnxt_alloc_vnic_attributes(bp);
245 rc = bnxt_alloc_filter_mem(bp);
249 rc = bnxt_alloc_async_cp_ring(bp);
256 bnxt_free_mem(bp, reconfig);
260 static int bnxt_init_chip(struct bnxt *bp)
262 struct bnxt_rx_queue *rxq;
263 struct rte_eth_link new;
264 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
265 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
266 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
267 uint64_t rx_offloads = dev_conf->rxmode.offloads;
268 uint32_t intr_vector = 0;
269 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
270 uint32_t vec = BNXT_MISC_VEC_ID;
274 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
275 bp->eth_dev->data->dev_conf.rxmode.offloads |=
276 DEV_RX_OFFLOAD_JUMBO_FRAME;
277 bp->flags |= BNXT_FLAG_JUMBO;
279 bp->eth_dev->data->dev_conf.rxmode.offloads &=
280 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
281 bp->flags &= ~BNXT_FLAG_JUMBO;
284 /* THOR does not support ring groups.
285 * But we will use the array to save RSS context IDs.
287 if (BNXT_CHIP_THOR(bp))
288 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
290 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
292 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
296 rc = bnxt_alloc_hwrm_rings(bp);
298 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
302 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
304 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
308 rc = bnxt_mq_rx_configure(bp);
310 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
314 /* VNIC configuration */
315 for (i = 0; i < bp->nr_vnics; i++) {
316 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
317 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
318 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
320 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
321 if (!vnic->fw_grp_ids) {
323 "Failed to alloc %d bytes for group ids\n",
328 memset(vnic->fw_grp_ids, -1, size);
330 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
331 i, vnic, vnic->fw_grp_ids);
333 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
335 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
340 /* Alloc RSS context only if RSS mode is enabled */
341 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
342 int j, nr_ctxs = bnxt_rss_ctxts(bp);
345 for (j = 0; j < nr_ctxs; j++) {
346 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
352 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
356 vnic->num_lb_ctxts = nr_ctxs;
360 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
361 * setting is not available at this time, it will not be
362 * configured correctly in the CFA.
364 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
365 vnic->vlan_strip = true;
367 vnic->vlan_strip = false;
369 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
371 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
376 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
379 "HWRM vnic %d filter failure rc: %x\n",
384 for (j = 0; j < bp->rx_nr_rings; j++) {
385 rxq = bp->eth_dev->data->rx_queues[j];
388 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
389 j, rxq->vnic, rxq->vnic->fw_grp_ids);
391 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
392 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
395 rc = bnxt_vnic_rss_configure(bp, vnic);
398 "HWRM vnic set RSS failure rc: %x\n", rc);
402 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
404 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
405 DEV_RX_OFFLOAD_TCP_LRO)
406 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
408 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
410 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
413 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
417 /* check and configure queue intr-vector mapping */
418 if ((rte_intr_cap_multiple(intr_handle) ||
419 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
420 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
421 intr_vector = bp->eth_dev->data->nb_rx_queues;
422 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
423 if (intr_vector > bp->rx_cp_nr_rings) {
424 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
428 rc = rte_intr_efd_enable(intr_handle, intr_vector);
433 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
434 intr_handle->intr_vec =
435 rte_zmalloc("intr_vec",
436 bp->eth_dev->data->nb_rx_queues *
438 if (intr_handle->intr_vec == NULL) {
439 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
440 " intr_vec", bp->eth_dev->data->nb_rx_queues);
444 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
445 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
446 intr_handle->intr_vec, intr_handle->nb_efd,
447 intr_handle->max_intr);
448 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
450 intr_handle->intr_vec[queue_id] =
451 vec + BNXT_RX_VEC_START;
452 if (vec < base + intr_handle->nb_efd - 1)
457 /* enable uio/vfio intr/eventfd mapping */
458 rc = rte_intr_enable(intr_handle);
462 rc = bnxt_get_hwrm_link_config(bp, &new);
464 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
468 if (!bp->link_info.link_up) {
469 rc = bnxt_set_hwrm_link_config(bp, true);
472 "HWRM link config failure rc: %x\n", rc);
476 bnxt_print_link_info(bp->eth_dev);
481 rte_free(intr_handle->intr_vec);
483 rte_intr_efd_disable(intr_handle);
485 /* Some of the error status returned by FW may not be from errno.h */
492 static int bnxt_shutdown_nic(struct bnxt *bp)
494 bnxt_free_all_hwrm_resources(bp);
495 bnxt_free_all_filters(bp);
496 bnxt_free_all_vnics(bp);
500 static int bnxt_init_nic(struct bnxt *bp)
504 if (BNXT_HAS_RING_GRPS(bp)) {
505 rc = bnxt_init_ring_grps(bp);
511 bnxt_init_filters(bp);
517 * Device configuration and status function
520 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
521 struct rte_eth_dev_info *dev_info)
523 struct bnxt *bp = eth_dev->data->dev_private;
524 uint16_t max_vnics, i, j, vpool, vrxq;
525 unsigned int max_rx_rings;
528 rc = is_bnxt_in_error(bp);
533 dev_info->max_mac_addrs = bp->max_l2_ctx;
534 dev_info->max_hash_mac_addrs = 0;
536 /* PF/VF specifics */
538 dev_info->max_vfs = bp->pdev->max_vfs;
539 max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
540 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
541 dev_info->max_rx_queues = max_rx_rings;
542 dev_info->max_tx_queues = max_rx_rings;
543 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
544 dev_info->hash_key_size = 40;
545 max_vnics = bp->max_vnics;
547 /* Fast path specifics */
548 dev_info->min_rx_bufsize = 1;
549 dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
550 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
552 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
553 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
554 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
555 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
556 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
559 dev_info->default_rxconf = (struct rte_eth_rxconf) {
565 .rx_free_thresh = 32,
566 /* If no descriptors available, pkts are dropped by default */
570 dev_info->default_txconf = (struct rte_eth_txconf) {
576 .tx_free_thresh = 32,
579 eth_dev->data->dev_conf.intr_conf.lsc = 1;
581 eth_dev->data->dev_conf.intr_conf.rxq = 1;
582 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
583 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
584 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
585 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
590 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
591 * need further investigation.
595 vpool = 64; /* ETH_64_POOLS */
596 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
597 for (i = 0; i < 4; vpool >>= 1, i++) {
598 if (max_vnics > vpool) {
599 for (j = 0; j < 5; vrxq >>= 1, j++) {
600 if (dev_info->max_rx_queues > vrxq) {
606 /* Not enough resources to support VMDq */
610 /* Not enough resources to support VMDq */
614 dev_info->max_vmdq_pools = vpool;
615 dev_info->vmdq_queue_num = vrxq;
617 dev_info->vmdq_pool_base = 0;
618 dev_info->vmdq_queue_base = 0;
623 /* Configure the device based on the configuration provided */
624 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
626 struct bnxt *bp = eth_dev->data->dev_private;
627 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
630 bp->rx_queues = (void *)eth_dev->data->rx_queues;
631 bp->tx_queues = (void *)eth_dev->data->tx_queues;
632 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
633 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
635 rc = is_bnxt_in_error(bp);
639 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
640 rc = bnxt_hwrm_check_vf_rings(bp);
642 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
646 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
648 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
652 /* legacy driver needs to get updated values */
653 rc = bnxt_hwrm_func_qcaps(bp);
655 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
660 /* Inherit new configurations */
661 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
662 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
663 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
664 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
665 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
669 if (BNXT_HAS_RING_GRPS(bp) &&
670 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
673 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
674 bp->max_vnics < eth_dev->data->nb_rx_queues)
677 bp->rx_cp_nr_rings = bp->rx_nr_rings;
678 bp->tx_cp_nr_rings = bp->tx_nr_rings;
680 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
682 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
683 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
685 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
691 "Insufficient resources to support requested config\n");
693 "Num Queues Requested: Tx %d, Rx %d\n",
694 eth_dev->data->nb_tx_queues,
695 eth_dev->data->nb_rx_queues);
697 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
698 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
699 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
703 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
705 struct rte_eth_link *link = ð_dev->data->dev_link;
707 if (link->link_status)
708 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
709 eth_dev->data->port_id,
710 (uint32_t)link->link_speed,
711 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
712 ("full-duplex") : ("half-duplex\n"));
714 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
715 eth_dev->data->port_id);
719 * Determine whether the current configuration requires support for scattered
720 * receive; return 1 if scattered receive is required and 0 if not.
722 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
727 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
728 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
730 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
731 RTE_PKTMBUF_HEADROOM);
732 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
738 static eth_rx_burst_t
739 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
743 * Vector mode receive can be enabled only if scatter rx is not
744 * in use and rx offloads are limited to VLAN stripping and
747 if (!eth_dev->data->scattered_rx &&
748 !(eth_dev->data->dev_conf.rxmode.offloads &
749 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
750 DEV_RX_OFFLOAD_KEEP_CRC |
751 DEV_RX_OFFLOAD_JUMBO_FRAME |
752 DEV_RX_OFFLOAD_IPV4_CKSUM |
753 DEV_RX_OFFLOAD_UDP_CKSUM |
754 DEV_RX_OFFLOAD_TCP_CKSUM |
755 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
756 DEV_RX_OFFLOAD_VLAN_FILTER))) {
757 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
758 eth_dev->data->port_id);
759 return bnxt_recv_pkts_vec;
761 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
762 eth_dev->data->port_id);
764 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
765 eth_dev->data->port_id,
766 eth_dev->data->scattered_rx,
767 eth_dev->data->dev_conf.rxmode.offloads);
769 return bnxt_recv_pkts;
772 static eth_tx_burst_t
773 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
777 * Vector mode transmit can be enabled only if not using scatter rx
780 if (!eth_dev->data->scattered_rx &&
781 !eth_dev->data->dev_conf.txmode.offloads) {
782 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
783 eth_dev->data->port_id);
784 return bnxt_xmit_pkts_vec;
786 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
787 eth_dev->data->port_id);
789 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
790 eth_dev->data->port_id,
791 eth_dev->data->scattered_rx,
792 eth_dev->data->dev_conf.txmode.offloads);
794 return bnxt_xmit_pkts;
797 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
799 struct bnxt *bp = eth_dev->data->dev_private;
800 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
804 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
806 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
807 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
810 rc = bnxt_init_chip(bp);
814 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
816 bnxt_link_update_op(eth_dev, 1);
818 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
819 vlan_mask |= ETH_VLAN_FILTER_MASK;
820 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
821 vlan_mask |= ETH_VLAN_STRIP_MASK;
822 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
826 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
827 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
830 bp->flags |= BNXT_FLAG_INIT_DONE;
831 eth_dev->data->dev_started = 1;
836 bnxt_shutdown_nic(bp);
837 bnxt_free_tx_mbufs(bp);
838 bnxt_free_rx_mbufs(bp);
842 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
844 struct bnxt *bp = eth_dev->data->dev_private;
847 if (!bp->link_info.link_up)
848 rc = bnxt_set_hwrm_link_config(bp, true);
850 eth_dev->data->dev_link.link_status = 1;
852 bnxt_print_link_info(eth_dev);
856 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
858 struct bnxt *bp = eth_dev->data->dev_private;
860 eth_dev->data->dev_link.link_status = 0;
861 bnxt_set_hwrm_link_config(bp, false);
862 bp->link_info.link_up = 0;
867 /* Unload the driver, release resources */
868 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
870 struct bnxt *bp = eth_dev->data->dev_private;
871 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
872 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
874 eth_dev->data->dev_started = 0;
875 /* Prevent crashes when queues are still in use */
876 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
877 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
879 bnxt_disable_int(bp);
881 /* disable uio/vfio intr/eventfd mapping */
882 rte_intr_disable(intr_handle);
884 bp->flags &= ~BNXT_FLAG_INIT_DONE;
885 if (bp->eth_dev->data->dev_started) {
886 /* TBD: STOP HW queues DMA */
887 eth_dev->data->dev_link.link_status = 0;
889 bnxt_set_hwrm_link_config(bp, false);
891 /* Clean queue intr-vector mapping */
892 rte_intr_efd_disable(intr_handle);
893 if (intr_handle->intr_vec != NULL) {
894 rte_free(intr_handle->intr_vec);
895 intr_handle->intr_vec = NULL;
898 bnxt_hwrm_port_clr_stats(bp);
899 bnxt_free_tx_mbufs(bp);
900 bnxt_free_rx_mbufs(bp);
901 bnxt_shutdown_nic(bp);
905 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
907 struct bnxt *bp = eth_dev->data->dev_private;
909 if (bp->dev_stopped == 0)
910 bnxt_dev_stop_op(eth_dev);
912 if (eth_dev->data->mac_addrs != NULL) {
913 rte_free(eth_dev->data->mac_addrs);
914 eth_dev->data->mac_addrs = NULL;
916 if (bp->grp_info != NULL) {
917 rte_free(bp->grp_info);
921 bnxt_dev_uninit(eth_dev);
924 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
927 struct bnxt *bp = eth_dev->data->dev_private;
928 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
929 struct bnxt_vnic_info *vnic;
930 struct bnxt_filter_info *filter, *temp_filter;
933 if (is_bnxt_in_error(bp))
937 * Loop through all VNICs from the specified filter flow pools to
938 * remove the corresponding MAC addr filter
940 for (i = 0; i < bp->nr_vnics; i++) {
941 if (!(pool_mask & (1ULL << i)))
944 vnic = &bp->vnic_info[i];
945 filter = STAILQ_FIRST(&vnic->filter);
947 temp_filter = STAILQ_NEXT(filter, next);
948 if (filter->mac_index == index) {
949 STAILQ_REMOVE(&vnic->filter, filter,
950 bnxt_filter_info, next);
951 bnxt_hwrm_clear_l2_filter(bp, filter);
952 filter->mac_index = INVALID_MAC_INDEX;
953 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
954 STAILQ_INSERT_TAIL(&bp->free_filter_list,
957 filter = temp_filter;
962 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
963 struct rte_ether_addr *mac_addr,
964 uint32_t index, uint32_t pool)
966 struct bnxt *bp = eth_dev->data->dev_private;
967 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
968 struct bnxt_filter_info *filter;
971 rc = is_bnxt_in_error(bp);
975 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
976 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
981 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
984 /* Attach requested MAC address to the new l2_filter */
985 STAILQ_FOREACH(filter, &vnic->filter, next) {
986 if (filter->mac_index == index) {
988 "MAC addr already existed for pool %d\n", pool);
992 filter = bnxt_alloc_filter(bp);
994 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
998 filter->mac_index = index;
999 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1001 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1003 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1005 filter->mac_index = INVALID_MAC_INDEX;
1006 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1007 bnxt_free_filter(bp, filter);
1013 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1016 struct bnxt *bp = eth_dev->data->dev_private;
1017 struct rte_eth_link new;
1018 unsigned int cnt = BNXT_LINK_WAIT_CNT;
1020 rc = is_bnxt_in_error(bp);
1024 memset(&new, 0, sizeof(new));
1026 /* Retrieve link info from hardware */
1027 rc = bnxt_get_hwrm_link_config(bp, &new);
1029 new.link_speed = ETH_LINK_SPEED_100M;
1030 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1032 "Failed to retrieve link rc = 0x%x!\n", rc);
1036 if (!wait_to_complete || new.link_status)
1039 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1043 /* Timed out or success */
1044 if (new.link_status != eth_dev->data->dev_link.link_status ||
1045 new.link_speed != eth_dev->data->dev_link.link_speed) {
1046 memcpy(ð_dev->data->dev_link, &new,
1047 sizeof(struct rte_eth_link));
1049 _rte_eth_dev_callback_process(eth_dev,
1050 RTE_ETH_EVENT_INTR_LSC,
1053 bnxt_print_link_info(eth_dev);
1059 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1061 struct bnxt *bp = eth_dev->data->dev_private;
1062 struct bnxt_vnic_info *vnic;
1066 rc = is_bnxt_in_error(bp);
1070 if (bp->vnic_info == NULL)
1073 vnic = &bp->vnic_info[0];
1075 old_flags = vnic->flags;
1076 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1077 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1079 vnic->flags = old_flags;
1084 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1086 struct bnxt *bp = eth_dev->data->dev_private;
1087 struct bnxt_vnic_info *vnic;
1091 rc = is_bnxt_in_error(bp);
1095 if (bp->vnic_info == NULL)
1098 vnic = &bp->vnic_info[0];
1100 old_flags = vnic->flags;
1101 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1102 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1104 vnic->flags = old_flags;
1109 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1111 struct bnxt *bp = eth_dev->data->dev_private;
1112 struct bnxt_vnic_info *vnic;
1116 rc = is_bnxt_in_error(bp);
1120 if (bp->vnic_info == NULL)
1123 vnic = &bp->vnic_info[0];
1125 old_flags = vnic->flags;
1126 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1127 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1129 vnic->flags = old_flags;
1134 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1136 struct bnxt *bp = eth_dev->data->dev_private;
1137 struct bnxt_vnic_info *vnic;
1141 rc = is_bnxt_in_error(bp);
1145 if (bp->vnic_info == NULL)
1148 vnic = &bp->vnic_info[0];
1150 old_flags = vnic->flags;
1151 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1152 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1154 vnic->flags = old_flags;
1159 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1160 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1162 if (qid >= bp->rx_nr_rings)
1165 return bp->eth_dev->data->rx_queues[qid];
1168 /* Return rxq corresponding to a given rss table ring/group ID. */
1169 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1171 struct bnxt_rx_queue *rxq;
1174 if (!BNXT_HAS_RING_GRPS(bp)) {
1175 for (i = 0; i < bp->rx_nr_rings; i++) {
1176 rxq = bp->eth_dev->data->rx_queues[i];
1177 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1181 for (i = 0; i < bp->rx_nr_rings; i++) {
1182 if (bp->grp_info[i].fw_grp_id == fwr)
1187 return INVALID_HW_RING_ID;
1190 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1191 struct rte_eth_rss_reta_entry64 *reta_conf,
1194 struct bnxt *bp = eth_dev->data->dev_private;
1195 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1196 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1197 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1201 rc = is_bnxt_in_error(bp);
1205 if (!vnic->rss_table)
1208 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1211 if (reta_size != tbl_size) {
1212 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1213 "(%d) must equal the size supported by the hardware "
1214 "(%d)\n", reta_size, tbl_size);
1218 for (i = 0; i < reta_size; i++) {
1219 struct bnxt_rx_queue *rxq;
1221 idx = i / RTE_RETA_GROUP_SIZE;
1222 sft = i % RTE_RETA_GROUP_SIZE;
1224 if (!(reta_conf[idx].mask & (1ULL << sft)))
1227 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1229 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1233 if (BNXT_CHIP_THOR(bp)) {
1234 vnic->rss_table[i * 2] =
1235 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1236 vnic->rss_table[i * 2 + 1] =
1237 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1239 vnic->rss_table[i] =
1240 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1243 vnic->rss_table[i] =
1244 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1247 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1251 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1252 struct rte_eth_rss_reta_entry64 *reta_conf,
1255 struct bnxt *bp = eth_dev->data->dev_private;
1256 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1257 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1258 uint16_t idx, sft, i;
1261 rc = is_bnxt_in_error(bp);
1265 /* Retrieve from the default VNIC */
1268 if (!vnic->rss_table)
1271 if (reta_size != tbl_size) {
1272 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1273 "(%d) must equal the size supported by the hardware "
1274 "(%d)\n", reta_size, tbl_size);
1278 for (idx = 0, i = 0; i < reta_size; i++) {
1279 idx = i / RTE_RETA_GROUP_SIZE;
1280 sft = i % RTE_RETA_GROUP_SIZE;
1282 if (reta_conf[idx].mask & (1ULL << sft)) {
1285 if (BNXT_CHIP_THOR(bp))
1286 qid = bnxt_rss_to_qid(bp,
1287 vnic->rss_table[i * 2]);
1289 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1291 if (qid == INVALID_HW_RING_ID) {
1292 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1295 reta_conf[idx].reta[sft] = qid;
1302 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1303 struct rte_eth_rss_conf *rss_conf)
1305 struct bnxt *bp = eth_dev->data->dev_private;
1306 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1307 struct bnxt_vnic_info *vnic;
1308 uint16_t hash_type = 0;
1312 rc = is_bnxt_in_error(bp);
1317 * If RSS enablement were different than dev_configure,
1318 * then return -EINVAL
1320 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1321 if (!rss_conf->rss_hf)
1322 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1324 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1328 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1329 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1331 if (rss_conf->rss_hf & ETH_RSS_IPV4)
1332 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1333 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1334 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1335 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1336 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1337 if (rss_conf->rss_hf & ETH_RSS_IPV6)
1338 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1339 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1340 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1341 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1342 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1344 /* Update the RSS VNIC(s) */
1345 for (i = 0; i < bp->nr_vnics; i++) {
1346 vnic = &bp->vnic_info[i];
1347 vnic->hash_type = hash_type;
1350 * Use the supplied key if the key length is
1351 * acceptable and the rss_key is not NULL
1353 if (rss_conf->rss_key &&
1354 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1355 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1356 rss_conf->rss_key_len);
1358 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1363 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1364 struct rte_eth_rss_conf *rss_conf)
1366 struct bnxt *bp = eth_dev->data->dev_private;
1367 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1369 uint32_t hash_types;
1371 rc = is_bnxt_in_error(bp);
1375 /* RSS configuration is the same for all VNICs */
1376 if (vnic && vnic->rss_hash_key) {
1377 if (rss_conf->rss_key) {
1378 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1379 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1380 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1383 hash_types = vnic->hash_type;
1384 rss_conf->rss_hf = 0;
1385 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1386 rss_conf->rss_hf |= ETH_RSS_IPV4;
1387 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1389 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1390 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1392 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1394 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1395 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1397 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1399 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1400 rss_conf->rss_hf |= ETH_RSS_IPV6;
1401 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1403 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1404 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1406 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1408 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1409 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1411 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1415 "Unknwon RSS config from firmware (%08x), RSS disabled",
1420 rss_conf->rss_hf = 0;
1425 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1426 struct rte_eth_fc_conf *fc_conf)
1428 struct bnxt *bp = dev->data->dev_private;
1429 struct rte_eth_link link_info;
1432 rc = is_bnxt_in_error(bp);
1436 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1440 memset(fc_conf, 0, sizeof(*fc_conf));
1441 if (bp->link_info.auto_pause)
1442 fc_conf->autoneg = 1;
1443 switch (bp->link_info.pause) {
1445 fc_conf->mode = RTE_FC_NONE;
1447 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1448 fc_conf->mode = RTE_FC_TX_PAUSE;
1450 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1451 fc_conf->mode = RTE_FC_RX_PAUSE;
1453 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1454 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1455 fc_conf->mode = RTE_FC_FULL;
1461 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1462 struct rte_eth_fc_conf *fc_conf)
1464 struct bnxt *bp = dev->data->dev_private;
1467 rc = is_bnxt_in_error(bp);
1471 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1472 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1476 switch (fc_conf->mode) {
1478 bp->link_info.auto_pause = 0;
1479 bp->link_info.force_pause = 0;
1481 case RTE_FC_RX_PAUSE:
1482 if (fc_conf->autoneg) {
1483 bp->link_info.auto_pause =
1484 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1485 bp->link_info.force_pause = 0;
1487 bp->link_info.auto_pause = 0;
1488 bp->link_info.force_pause =
1489 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1492 case RTE_FC_TX_PAUSE:
1493 if (fc_conf->autoneg) {
1494 bp->link_info.auto_pause =
1495 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1496 bp->link_info.force_pause = 0;
1498 bp->link_info.auto_pause = 0;
1499 bp->link_info.force_pause =
1500 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1504 if (fc_conf->autoneg) {
1505 bp->link_info.auto_pause =
1506 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1507 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1508 bp->link_info.force_pause = 0;
1510 bp->link_info.auto_pause = 0;
1511 bp->link_info.force_pause =
1512 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1513 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1517 return bnxt_set_hwrm_link_config(bp, true);
1520 /* Add UDP tunneling port */
1522 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1523 struct rte_eth_udp_tunnel *udp_tunnel)
1525 struct bnxt *bp = eth_dev->data->dev_private;
1526 uint16_t tunnel_type = 0;
1529 rc = is_bnxt_in_error(bp);
1533 switch (udp_tunnel->prot_type) {
1534 case RTE_TUNNEL_TYPE_VXLAN:
1535 if (bp->vxlan_port_cnt) {
1536 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1537 udp_tunnel->udp_port);
1538 if (bp->vxlan_port != udp_tunnel->udp_port) {
1539 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1542 bp->vxlan_port_cnt++;
1546 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1547 bp->vxlan_port_cnt++;
1549 case RTE_TUNNEL_TYPE_GENEVE:
1550 if (bp->geneve_port_cnt) {
1551 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1552 udp_tunnel->udp_port);
1553 if (bp->geneve_port != udp_tunnel->udp_port) {
1554 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1557 bp->geneve_port_cnt++;
1561 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1562 bp->geneve_port_cnt++;
1565 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1568 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1574 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1575 struct rte_eth_udp_tunnel *udp_tunnel)
1577 struct bnxt *bp = eth_dev->data->dev_private;
1578 uint16_t tunnel_type = 0;
1582 rc = is_bnxt_in_error(bp);
1586 switch (udp_tunnel->prot_type) {
1587 case RTE_TUNNEL_TYPE_VXLAN:
1588 if (!bp->vxlan_port_cnt) {
1589 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1592 if (bp->vxlan_port != udp_tunnel->udp_port) {
1593 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1594 udp_tunnel->udp_port, bp->vxlan_port);
1597 if (--bp->vxlan_port_cnt)
1601 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1602 port = bp->vxlan_fw_dst_port_id;
1604 case RTE_TUNNEL_TYPE_GENEVE:
1605 if (!bp->geneve_port_cnt) {
1606 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1609 if (bp->geneve_port != udp_tunnel->udp_port) {
1610 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1611 udp_tunnel->udp_port, bp->geneve_port);
1614 if (--bp->geneve_port_cnt)
1618 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1619 port = bp->geneve_fw_dst_port_id;
1622 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1626 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1629 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1632 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1633 bp->geneve_port = 0;
1638 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1640 struct bnxt_filter_info *filter;
1641 struct bnxt_vnic_info *vnic;
1643 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1645 /* if VLAN exists && VLAN matches vlan_id
1646 * remove the MAC+VLAN filter
1647 * add a new MAC only filter
1649 * VLAN filter doesn't exist, just skip and continue
1651 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1652 filter = STAILQ_FIRST(&vnic->filter);
1654 /* Search for this matching MAC+VLAN filter */
1655 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1656 !memcmp(filter->l2_addr,
1658 RTE_ETHER_ADDR_LEN)) {
1659 /* Delete the filter */
1660 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1663 STAILQ_REMOVE(&vnic->filter, filter,
1664 bnxt_filter_info, next);
1665 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1668 "Del Vlan filter for %d\n",
1672 filter = STAILQ_NEXT(filter, next);
1677 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1679 struct bnxt_filter_info *filter;
1680 struct bnxt_vnic_info *vnic;
1682 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1683 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1684 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1686 /* Implementation notes on the use of VNIC in this command:
1688 * By default, these filters belong to default vnic for the function.
1689 * Once these filters are set up, only destination VNIC can be modified.
1690 * If the destination VNIC is not specified in this command,
1691 * then the HWRM shall only create an l2 context id.
1694 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1695 filter = STAILQ_FIRST(&vnic->filter);
1696 /* Check if the VLAN has already been added */
1698 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1699 !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN))
1702 filter = STAILQ_NEXT(filter, next);
1705 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1706 * command to create MAC+VLAN filter with the right flags, enables set.
1708 filter = bnxt_alloc_filter(bp);
1711 "MAC/VLAN filter alloc failed\n");
1714 /* MAC + VLAN ID filter */
1715 filter->l2_ivlan = vlan_id;
1716 filter->l2_ivlan_mask = 0x0FFF;
1717 filter->enables |= en;
1718 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1720 /* Free the newly allocated filter as we were
1721 * not able to create the filter in hardware.
1723 filter->fw_l2_filter_id = UINT64_MAX;
1724 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1728 /* Add this new filter to the list */
1729 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1731 "Added Vlan filter for %d\n", vlan_id);
1735 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1736 uint16_t vlan_id, int on)
1738 struct bnxt *bp = eth_dev->data->dev_private;
1741 rc = is_bnxt_in_error(bp);
1745 /* These operations apply to ALL existing MAC/VLAN filters */
1747 return bnxt_add_vlan_filter(bp, vlan_id);
1749 return bnxt_del_vlan_filter(bp, vlan_id);
1753 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1755 struct bnxt *bp = dev->data->dev_private;
1756 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1760 rc = is_bnxt_in_error(bp);
1764 if (mask & ETH_VLAN_FILTER_MASK) {
1765 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1766 /* Remove any VLAN filters programmed */
1767 for (i = 0; i < 4095; i++)
1768 bnxt_del_vlan_filter(bp, i);
1770 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1771 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1774 if (mask & ETH_VLAN_STRIP_MASK) {
1775 /* Enable or disable VLAN stripping */
1776 for (i = 0; i < bp->nr_vnics; i++) {
1777 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1778 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1779 vnic->vlan_strip = true;
1781 vnic->vlan_strip = false;
1782 bnxt_hwrm_vnic_cfg(bp, vnic);
1784 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1785 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1788 if (mask & ETH_VLAN_EXTEND_MASK)
1789 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1795 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1796 struct rte_ether_addr *addr)
1798 struct bnxt *bp = dev->data->dev_private;
1799 /* Default Filter is tied to VNIC 0 */
1800 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1801 struct bnxt_filter_info *filter;
1804 rc = is_bnxt_in_error(bp);
1808 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1811 if (rte_is_zero_ether_addr(addr))
1814 STAILQ_FOREACH(filter, &vnic->filter, next) {
1815 /* Default Filter is at Index 0 */
1816 if (filter->mac_index != 0)
1819 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1820 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1821 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1823 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1824 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1826 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1830 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1831 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1839 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1840 struct rte_ether_addr *mc_addr_set,
1841 uint32_t nb_mc_addr)
1843 struct bnxt *bp = eth_dev->data->dev_private;
1844 char *mc_addr_list = (char *)mc_addr_set;
1845 struct bnxt_vnic_info *vnic;
1846 uint32_t off = 0, i = 0;
1849 rc = is_bnxt_in_error(bp);
1853 vnic = &bp->vnic_info[0];
1855 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1856 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1860 /* TODO Check for Duplicate mcast addresses */
1861 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1862 for (i = 0; i < nb_mc_addr; i++) {
1863 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1864 RTE_ETHER_ADDR_LEN);
1865 off += RTE_ETHER_ADDR_LEN;
1868 vnic->mc_addr_cnt = i;
1871 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1875 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1877 struct bnxt *bp = dev->data->dev_private;
1878 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1879 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1880 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1883 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1884 fw_major, fw_minor, fw_updt);
1886 ret += 1; /* add the size of '\0' */
1887 if (fw_size < (uint32_t)ret)
1894 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1895 struct rte_eth_rxq_info *qinfo)
1897 struct bnxt_rx_queue *rxq;
1899 rxq = dev->data->rx_queues[queue_id];
1901 qinfo->mp = rxq->mb_pool;
1902 qinfo->scattered_rx = dev->data->scattered_rx;
1903 qinfo->nb_desc = rxq->nb_rx_desc;
1905 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1906 qinfo->conf.rx_drop_en = 0;
1907 qinfo->conf.rx_deferred_start = 0;
1911 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1912 struct rte_eth_txq_info *qinfo)
1914 struct bnxt_tx_queue *txq;
1916 txq = dev->data->tx_queues[queue_id];
1918 qinfo->nb_desc = txq->nb_tx_desc;
1920 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1921 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1922 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1924 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1925 qinfo->conf.tx_rs_thresh = 0;
1926 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1929 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1931 struct bnxt *bp = eth_dev->data->dev_private;
1932 struct rte_eth_dev_info dev_info;
1933 uint32_t new_pkt_size;
1937 rc = is_bnxt_in_error(bp);
1941 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1942 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1944 rc = bnxt_dev_info_get_op(eth_dev, &dev_info);
1946 PMD_DRV_LOG(ERR, "Error during getting ethernet device info\n");
1950 if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
1951 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1952 RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
1958 * If vector-mode tx/rx is active, disallow any MTU change that would
1959 * require scattered receive support.
1961 if (eth_dev->data->dev_started &&
1962 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1963 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1965 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1967 "MTU change would require scattered rx support. ");
1968 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
1973 if (new_mtu > RTE_ETHER_MTU) {
1974 bp->flags |= BNXT_FLAG_JUMBO;
1975 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1976 DEV_RX_OFFLOAD_JUMBO_FRAME;
1978 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1979 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1980 bp->flags &= ~BNXT_FLAG_JUMBO;
1983 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
1985 eth_dev->data->mtu = new_mtu;
1986 PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1988 for (i = 0; i < bp->nr_vnics; i++) {
1989 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1992 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
1993 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1994 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1998 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
1999 size -= RTE_PKTMBUF_HEADROOM;
2001 if (size < new_mtu) {
2002 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2012 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2014 struct bnxt *bp = dev->data->dev_private;
2015 uint16_t vlan = bp->vlan;
2018 rc = is_bnxt_in_error(bp);
2022 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2024 "PVID cannot be modified for this function\n");
2027 bp->vlan = on ? pvid : 0;
2029 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2036 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2038 struct bnxt *bp = dev->data->dev_private;
2041 rc = is_bnxt_in_error(bp);
2045 return bnxt_hwrm_port_led_cfg(bp, true);
2049 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2051 struct bnxt *bp = dev->data->dev_private;
2054 rc = is_bnxt_in_error(bp);
2058 return bnxt_hwrm_port_led_cfg(bp, false);
2062 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2064 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2065 uint32_t desc = 0, raw_cons = 0, cons;
2066 struct bnxt_cp_ring_info *cpr;
2067 struct bnxt_rx_queue *rxq;
2068 struct rx_pkt_cmpl *rxcmp;
2074 rc = is_bnxt_in_error(bp);
2078 rxq = dev->data->rx_queues[rx_queue_id];
2082 while (raw_cons < rxq->nb_rx_desc) {
2083 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2084 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2086 if (!CMPL_VALID(rxcmp, valid))
2088 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
2089 cmp_type = CMP_TYPE(rxcmp);
2090 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
2091 cmp = (rte_le_to_cpu_32(
2092 ((struct rx_tpa_end_cmpl *)
2093 (rxcmp))->agg_bufs_v1) &
2094 RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
2095 RX_TPA_END_CMPL_AGG_BUFS_SFT;
2097 } else if (cmp_type == 0x11) {
2099 cmp = (rxcmp->agg_bufs_v1 &
2100 RX_PKT_CMPL_AGG_BUFS_MASK) >>
2101 RX_PKT_CMPL_AGG_BUFS_SFT;
2106 raw_cons += cmp ? cmp : 2;
2113 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2115 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2116 struct bnxt_rx_ring_info *rxr;
2117 struct bnxt_cp_ring_info *cpr;
2118 struct bnxt_sw_rx_bd *rx_buf;
2119 struct rx_pkt_cmpl *rxcmp;
2120 uint32_t cons, cp_cons;
2126 rc = is_bnxt_in_error(rxq->bp);
2133 if (offset >= rxq->nb_rx_desc)
2136 cons = RING_CMP(cpr->cp_ring_struct, offset);
2137 cp_cons = cpr->cp_raw_cons;
2138 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2140 if (cons > cp_cons) {
2141 if (CMPL_VALID(rxcmp, cpr->valid))
2142 return RTE_ETH_RX_DESC_DONE;
2144 if (CMPL_VALID(rxcmp, !cpr->valid))
2145 return RTE_ETH_RX_DESC_DONE;
2147 rx_buf = &rxr->rx_buf_ring[cons];
2148 if (rx_buf->mbuf == NULL)
2149 return RTE_ETH_RX_DESC_UNAVAIL;
2152 return RTE_ETH_RX_DESC_AVAIL;
2156 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2158 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2159 struct bnxt_tx_ring_info *txr;
2160 struct bnxt_cp_ring_info *cpr;
2161 struct bnxt_sw_tx_bd *tx_buf;
2162 struct tx_pkt_cmpl *txcmp;
2163 uint32_t cons, cp_cons;
2169 rc = is_bnxt_in_error(txq->bp);
2176 if (offset >= txq->nb_tx_desc)
2179 cons = RING_CMP(cpr->cp_ring_struct, offset);
2180 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2181 cp_cons = cpr->cp_raw_cons;
2183 if (cons > cp_cons) {
2184 if (CMPL_VALID(txcmp, cpr->valid))
2185 return RTE_ETH_TX_DESC_UNAVAIL;
2187 if (CMPL_VALID(txcmp, !cpr->valid))
2188 return RTE_ETH_TX_DESC_UNAVAIL;
2190 tx_buf = &txr->tx_buf_ring[cons];
2191 if (tx_buf->mbuf == NULL)
2192 return RTE_ETH_TX_DESC_DONE;
2194 return RTE_ETH_TX_DESC_FULL;
2197 static struct bnxt_filter_info *
2198 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2199 struct rte_eth_ethertype_filter *efilter,
2200 struct bnxt_vnic_info *vnic0,
2201 struct bnxt_vnic_info *vnic,
2204 struct bnxt_filter_info *mfilter = NULL;
2208 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2209 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2210 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2211 " ethertype filter.", efilter->ether_type);
2215 if (efilter->queue >= bp->rx_nr_rings) {
2216 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2221 vnic0 = &bp->vnic_info[0];
2222 vnic = &bp->vnic_info[efilter->queue];
2224 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2229 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2230 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2231 if ((!memcmp(efilter->mac_addr.addr_bytes,
2232 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2234 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2235 mfilter->ethertype == efilter->ether_type)) {
2241 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2242 if ((!memcmp(efilter->mac_addr.addr_bytes,
2243 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2244 mfilter->ethertype == efilter->ether_type &&
2246 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2260 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2261 enum rte_filter_op filter_op,
2264 struct bnxt *bp = dev->data->dev_private;
2265 struct rte_eth_ethertype_filter *efilter =
2266 (struct rte_eth_ethertype_filter *)arg;
2267 struct bnxt_filter_info *bfilter, *filter1;
2268 struct bnxt_vnic_info *vnic, *vnic0;
2271 if (filter_op == RTE_ETH_FILTER_NOP)
2275 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2280 vnic0 = &bp->vnic_info[0];
2281 vnic = &bp->vnic_info[efilter->queue];
2283 switch (filter_op) {
2284 case RTE_ETH_FILTER_ADD:
2285 bnxt_match_and_validate_ether_filter(bp, efilter,
2290 bfilter = bnxt_get_unused_filter(bp);
2291 if (bfilter == NULL) {
2293 "Not enough resources for a new filter.\n");
2296 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2297 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2298 RTE_ETHER_ADDR_LEN);
2299 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2300 RTE_ETHER_ADDR_LEN);
2301 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2302 bfilter->ethertype = efilter->ether_type;
2303 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2305 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2306 if (filter1 == NULL) {
2311 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2312 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2314 bfilter->dst_id = vnic->fw_vnic_id;
2316 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2318 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2321 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2324 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2326 case RTE_ETH_FILTER_DELETE:
2327 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2329 if (ret == -EEXIST) {
2330 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2332 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2334 bnxt_free_filter(bp, filter1);
2335 } else if (ret == 0) {
2336 PMD_DRV_LOG(ERR, "No matching filter found\n");
2340 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2346 bnxt_free_filter(bp, bfilter);
2352 parse_ntuple_filter(struct bnxt *bp,
2353 struct rte_eth_ntuple_filter *nfilter,
2354 struct bnxt_filter_info *bfilter)
2358 if (nfilter->queue >= bp->rx_nr_rings) {
2359 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2363 switch (nfilter->dst_port_mask) {
2365 bfilter->dst_port_mask = -1;
2366 bfilter->dst_port = nfilter->dst_port;
2367 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2368 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2371 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2375 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2376 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2378 switch (nfilter->proto_mask) {
2380 if (nfilter->proto == 17) /* IPPROTO_UDP */
2381 bfilter->ip_protocol = 17;
2382 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2383 bfilter->ip_protocol = 6;
2386 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2389 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2393 switch (nfilter->dst_ip_mask) {
2395 bfilter->dst_ipaddr_mask[0] = -1;
2396 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2397 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2398 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2401 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2405 switch (nfilter->src_ip_mask) {
2407 bfilter->src_ipaddr_mask[0] = -1;
2408 bfilter->src_ipaddr[0] = nfilter->src_ip;
2409 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2410 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2413 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2417 switch (nfilter->src_port_mask) {
2419 bfilter->src_port_mask = -1;
2420 bfilter->src_port = nfilter->src_port;
2421 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2422 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2425 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2430 //nfilter->priority = (uint8_t)filter->priority;
2432 bfilter->enables = en;
2436 static struct bnxt_filter_info*
2437 bnxt_match_ntuple_filter(struct bnxt *bp,
2438 struct bnxt_filter_info *bfilter,
2439 struct bnxt_vnic_info **mvnic)
2441 struct bnxt_filter_info *mfilter = NULL;
2444 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2445 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2446 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2447 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2448 bfilter->src_ipaddr_mask[0] ==
2449 mfilter->src_ipaddr_mask[0] &&
2450 bfilter->src_port == mfilter->src_port &&
2451 bfilter->src_port_mask == mfilter->src_port_mask &&
2452 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2453 bfilter->dst_ipaddr_mask[0] ==
2454 mfilter->dst_ipaddr_mask[0] &&
2455 bfilter->dst_port == mfilter->dst_port &&
2456 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2457 bfilter->flags == mfilter->flags &&
2458 bfilter->enables == mfilter->enables) {
2469 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2470 struct rte_eth_ntuple_filter *nfilter,
2471 enum rte_filter_op filter_op)
2473 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2474 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2477 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2478 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2482 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2483 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2487 bfilter = bnxt_get_unused_filter(bp);
2488 if (bfilter == NULL) {
2490 "Not enough resources for a new filter.\n");
2493 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2497 vnic = &bp->vnic_info[nfilter->queue];
2498 vnic0 = &bp->vnic_info[0];
2499 filter1 = STAILQ_FIRST(&vnic0->filter);
2500 if (filter1 == NULL) {
2505 bfilter->dst_id = vnic->fw_vnic_id;
2506 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2508 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2509 bfilter->ethertype = 0x800;
2510 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2512 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2514 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2515 bfilter->dst_id == mfilter->dst_id) {
2516 PMD_DRV_LOG(ERR, "filter exists.\n");
2519 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2520 bfilter->dst_id != mfilter->dst_id) {
2521 mfilter->dst_id = vnic->fw_vnic_id;
2522 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2523 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2524 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2525 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2526 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2529 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2530 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2535 if (filter_op == RTE_ETH_FILTER_ADD) {
2536 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2537 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2540 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2542 if (mfilter == NULL) {
2543 /* This should not happen. But for Coverity! */
2547 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2549 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2550 bnxt_free_filter(bp, mfilter);
2551 mfilter->fw_l2_filter_id = -1;
2552 bnxt_free_filter(bp, bfilter);
2553 bfilter->fw_l2_filter_id = -1;
2558 bfilter->fw_l2_filter_id = -1;
2559 bnxt_free_filter(bp, bfilter);
2564 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2565 enum rte_filter_op filter_op,
2568 struct bnxt *bp = dev->data->dev_private;
2571 if (filter_op == RTE_ETH_FILTER_NOP)
2575 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2580 switch (filter_op) {
2581 case RTE_ETH_FILTER_ADD:
2582 ret = bnxt_cfg_ntuple_filter(bp,
2583 (struct rte_eth_ntuple_filter *)arg,
2586 case RTE_ETH_FILTER_DELETE:
2587 ret = bnxt_cfg_ntuple_filter(bp,
2588 (struct rte_eth_ntuple_filter *)arg,
2592 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2600 bnxt_parse_fdir_filter(struct bnxt *bp,
2601 struct rte_eth_fdir_filter *fdir,
2602 struct bnxt_filter_info *filter)
2604 enum rte_fdir_mode fdir_mode =
2605 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2606 struct bnxt_vnic_info *vnic0, *vnic;
2607 struct bnxt_filter_info *filter1;
2611 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2614 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2615 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2617 switch (fdir->input.flow_type) {
2618 case RTE_ETH_FLOW_IPV4:
2619 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2621 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2622 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2623 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2624 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2625 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2626 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2627 filter->ip_addr_type =
2628 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2629 filter->src_ipaddr_mask[0] = 0xffffffff;
2630 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2631 filter->dst_ipaddr_mask[0] = 0xffffffff;
2632 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2633 filter->ethertype = 0x800;
2634 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2636 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2637 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2638 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2639 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2640 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2641 filter->dst_port_mask = 0xffff;
2642 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2643 filter->src_port_mask = 0xffff;
2644 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2645 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2646 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2647 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2648 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2649 filter->ip_protocol = 6;
2650 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2651 filter->ip_addr_type =
2652 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2653 filter->src_ipaddr_mask[0] = 0xffffffff;
2654 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2655 filter->dst_ipaddr_mask[0] = 0xffffffff;
2656 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2657 filter->ethertype = 0x800;
2658 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2660 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2661 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2662 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2663 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2664 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2665 filter->dst_port_mask = 0xffff;
2666 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2667 filter->src_port_mask = 0xffff;
2668 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2669 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2670 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2671 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2672 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2673 filter->ip_protocol = 17;
2674 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2675 filter->ip_addr_type =
2676 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2677 filter->src_ipaddr_mask[0] = 0xffffffff;
2678 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2679 filter->dst_ipaddr_mask[0] = 0xffffffff;
2680 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2681 filter->ethertype = 0x800;
2682 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2684 case RTE_ETH_FLOW_IPV6:
2685 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2687 filter->ip_addr_type =
2688 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2689 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2690 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2691 rte_memcpy(filter->src_ipaddr,
2692 fdir->input.flow.ipv6_flow.src_ip, 16);
2693 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2694 rte_memcpy(filter->dst_ipaddr,
2695 fdir->input.flow.ipv6_flow.dst_ip, 16);
2696 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2697 memset(filter->dst_ipaddr_mask, 0xff, 16);
2698 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2699 memset(filter->src_ipaddr_mask, 0xff, 16);
2700 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2701 filter->ethertype = 0x86dd;
2702 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2704 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2705 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2706 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2707 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2708 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2709 filter->dst_port_mask = 0xffff;
2710 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2711 filter->src_port_mask = 0xffff;
2712 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2713 filter->ip_addr_type =
2714 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2715 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2716 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2717 rte_memcpy(filter->src_ipaddr,
2718 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2719 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2720 rte_memcpy(filter->dst_ipaddr,
2721 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2722 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2723 memset(filter->dst_ipaddr_mask, 0xff, 16);
2724 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2725 memset(filter->src_ipaddr_mask, 0xff, 16);
2726 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2727 filter->ethertype = 0x86dd;
2728 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2730 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2731 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2732 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2733 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2734 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2735 filter->dst_port_mask = 0xffff;
2736 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2737 filter->src_port_mask = 0xffff;
2738 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2739 filter->ip_addr_type =
2740 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2741 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2742 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2743 rte_memcpy(filter->src_ipaddr,
2744 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2745 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2746 rte_memcpy(filter->dst_ipaddr,
2747 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2748 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2749 memset(filter->dst_ipaddr_mask, 0xff, 16);
2750 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2751 memset(filter->src_ipaddr_mask, 0xff, 16);
2752 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2753 filter->ethertype = 0x86dd;
2754 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2756 case RTE_ETH_FLOW_L2_PAYLOAD:
2757 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2758 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2760 case RTE_ETH_FLOW_VXLAN:
2761 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2763 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2764 filter->tunnel_type =
2765 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2766 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2768 case RTE_ETH_FLOW_NVGRE:
2769 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2771 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2772 filter->tunnel_type =
2773 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2774 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2776 case RTE_ETH_FLOW_UNKNOWN:
2777 case RTE_ETH_FLOW_RAW:
2778 case RTE_ETH_FLOW_FRAG_IPV4:
2779 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2780 case RTE_ETH_FLOW_FRAG_IPV6:
2781 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2782 case RTE_ETH_FLOW_IPV6_EX:
2783 case RTE_ETH_FLOW_IPV6_TCP_EX:
2784 case RTE_ETH_FLOW_IPV6_UDP_EX:
2785 case RTE_ETH_FLOW_GENEVE:
2791 vnic0 = &bp->vnic_info[0];
2792 vnic = &bp->vnic_info[fdir->action.rx_queue];
2794 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2799 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2800 rte_memcpy(filter->dst_macaddr,
2801 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2802 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2805 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2806 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2807 filter1 = STAILQ_FIRST(&vnic0->filter);
2808 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2810 filter->dst_id = vnic->fw_vnic_id;
2811 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2812 if (filter->dst_macaddr[i] == 0x00)
2813 filter1 = STAILQ_FIRST(&vnic0->filter);
2815 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2818 if (filter1 == NULL)
2821 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2822 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2824 filter->enables = en;
2829 static struct bnxt_filter_info *
2830 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2831 struct bnxt_vnic_info **mvnic)
2833 struct bnxt_filter_info *mf = NULL;
2836 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2837 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2839 STAILQ_FOREACH(mf, &vnic->filter, next) {
2840 if (mf->filter_type == nf->filter_type &&
2841 mf->flags == nf->flags &&
2842 mf->src_port == nf->src_port &&
2843 mf->src_port_mask == nf->src_port_mask &&
2844 mf->dst_port == nf->dst_port &&
2845 mf->dst_port_mask == nf->dst_port_mask &&
2846 mf->ip_protocol == nf->ip_protocol &&
2847 mf->ip_addr_type == nf->ip_addr_type &&
2848 mf->ethertype == nf->ethertype &&
2849 mf->vni == nf->vni &&
2850 mf->tunnel_type == nf->tunnel_type &&
2851 mf->l2_ovlan == nf->l2_ovlan &&
2852 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2853 mf->l2_ivlan == nf->l2_ivlan &&
2854 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2855 !memcmp(mf->l2_addr, nf->l2_addr,
2856 RTE_ETHER_ADDR_LEN) &&
2857 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2858 RTE_ETHER_ADDR_LEN) &&
2859 !memcmp(mf->src_macaddr, nf->src_macaddr,
2860 RTE_ETHER_ADDR_LEN) &&
2861 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2862 RTE_ETHER_ADDR_LEN) &&
2863 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2864 sizeof(nf->src_ipaddr)) &&
2865 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2866 sizeof(nf->src_ipaddr_mask)) &&
2867 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2868 sizeof(nf->dst_ipaddr)) &&
2869 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2870 sizeof(nf->dst_ipaddr_mask))) {
2881 bnxt_fdir_filter(struct rte_eth_dev *dev,
2882 enum rte_filter_op filter_op,
2885 struct bnxt *bp = dev->data->dev_private;
2886 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2887 struct bnxt_filter_info *filter, *match;
2888 struct bnxt_vnic_info *vnic, *mvnic;
2891 if (filter_op == RTE_ETH_FILTER_NOP)
2894 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2897 switch (filter_op) {
2898 case RTE_ETH_FILTER_ADD:
2899 case RTE_ETH_FILTER_DELETE:
2901 filter = bnxt_get_unused_filter(bp);
2902 if (filter == NULL) {
2904 "Not enough resources for a new flow.\n");
2908 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2911 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2913 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2914 vnic = &bp->vnic_info[0];
2916 vnic = &bp->vnic_info[fdir->action.rx_queue];
2918 match = bnxt_match_fdir(bp, filter, &mvnic);
2919 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2920 if (match->dst_id == vnic->fw_vnic_id) {
2921 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2925 match->dst_id = vnic->fw_vnic_id;
2926 ret = bnxt_hwrm_set_ntuple_filter(bp,
2929 STAILQ_REMOVE(&mvnic->filter, match,
2930 bnxt_filter_info, next);
2931 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2933 "Filter with matching pattern exist\n");
2935 "Updated it to new destination q\n");
2939 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2940 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2945 if (filter_op == RTE_ETH_FILTER_ADD) {
2946 ret = bnxt_hwrm_set_ntuple_filter(bp,
2951 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2953 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2954 STAILQ_REMOVE(&vnic->filter, match,
2955 bnxt_filter_info, next);
2956 bnxt_free_filter(bp, match);
2957 filter->fw_l2_filter_id = -1;
2958 bnxt_free_filter(bp, filter);
2961 case RTE_ETH_FILTER_FLUSH:
2962 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2963 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2965 STAILQ_FOREACH(filter, &vnic->filter, next) {
2966 if (filter->filter_type ==
2967 HWRM_CFA_NTUPLE_FILTER) {
2969 bnxt_hwrm_clear_ntuple_filter(bp,
2971 STAILQ_REMOVE(&vnic->filter, filter,
2972 bnxt_filter_info, next);
2977 case RTE_ETH_FILTER_UPDATE:
2978 case RTE_ETH_FILTER_STATS:
2979 case RTE_ETH_FILTER_INFO:
2980 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2983 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2990 filter->fw_l2_filter_id = -1;
2991 bnxt_free_filter(bp, filter);
2996 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2997 enum rte_filter_type filter_type,
2998 enum rte_filter_op filter_op, void *arg)
3002 ret = is_bnxt_in_error(dev->data->dev_private);
3006 switch (filter_type) {
3007 case RTE_ETH_FILTER_TUNNEL:
3009 "filter type: %d: To be implemented\n", filter_type);
3011 case RTE_ETH_FILTER_FDIR:
3012 ret = bnxt_fdir_filter(dev, filter_op, arg);
3014 case RTE_ETH_FILTER_NTUPLE:
3015 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3017 case RTE_ETH_FILTER_ETHERTYPE:
3018 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3020 case RTE_ETH_FILTER_GENERIC:
3021 if (filter_op != RTE_ETH_FILTER_GET)
3023 *(const void **)arg = &bnxt_flow_ops;
3027 "Filter type (%d) not supported", filter_type);
3034 static const uint32_t *
3035 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3037 static const uint32_t ptypes[] = {
3038 RTE_PTYPE_L2_ETHER_VLAN,
3039 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3040 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3044 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3045 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3046 RTE_PTYPE_INNER_L4_ICMP,
3047 RTE_PTYPE_INNER_L4_TCP,
3048 RTE_PTYPE_INNER_L4_UDP,
3052 if (!dev->rx_pkt_burst)
3058 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3061 uint32_t reg_base = *reg_arr & 0xfffff000;
3065 for (i = 0; i < count; i++) {
3066 if ((reg_arr[i] & 0xfffff000) != reg_base)
3069 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3070 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3074 static int bnxt_map_ptp_regs(struct bnxt *bp)
3076 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3080 reg_arr = ptp->rx_regs;
3081 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3085 reg_arr = ptp->tx_regs;
3086 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3090 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3091 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3093 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3094 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3099 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3101 rte_write32(0, (uint8_t *)bp->bar0 +
3102 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3103 rte_write32(0, (uint8_t *)bp->bar0 +
3104 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3107 static uint64_t bnxt_cc_read(struct bnxt *bp)
3111 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3112 BNXT_GRCPF_REG_SYNC_TIME));
3113 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3114 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3118 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3120 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3123 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3124 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3125 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3128 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3129 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3130 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3131 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3132 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3133 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3138 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3140 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3141 struct bnxt_pf_info *pf = &bp->pf;
3148 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3149 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3150 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3153 port_id = pf->port_id;
3154 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3155 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3157 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3158 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3159 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3160 /* bnxt_clr_rx_ts(bp); TBD */
3164 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3165 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3166 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3167 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3173 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3176 struct bnxt *bp = dev->data->dev_private;
3177 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3182 ns = rte_timespec_to_ns(ts);
3183 /* Set the timecounters to a new value. */
3190 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3192 uint64_t ns, systime_cycles;
3193 struct bnxt *bp = dev->data->dev_private;
3194 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3199 systime_cycles = bnxt_cc_read(bp);
3200 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3201 *ts = rte_ns_to_timespec(ns);
3206 bnxt_timesync_enable(struct rte_eth_dev *dev)
3208 struct bnxt *bp = dev->data->dev_private;
3209 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3216 ptp->tx_tstamp_en = 1;
3217 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3219 if (!bnxt_hwrm_ptp_cfg(bp))
3220 bnxt_map_ptp_regs(bp);
3222 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3223 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3224 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3226 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3227 ptp->tc.cc_shift = shift;
3228 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3230 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3231 ptp->rx_tstamp_tc.cc_shift = shift;
3232 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3234 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3235 ptp->tx_tstamp_tc.cc_shift = shift;
3236 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3242 bnxt_timesync_disable(struct rte_eth_dev *dev)
3244 struct bnxt *bp = dev->data->dev_private;
3245 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3251 ptp->tx_tstamp_en = 0;
3254 bnxt_hwrm_ptp_cfg(bp);
3256 bnxt_unmap_ptp_regs(bp);
3262 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3263 struct timespec *timestamp,
3264 uint32_t flags __rte_unused)
3266 struct bnxt *bp = dev->data->dev_private;
3267 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3268 uint64_t rx_tstamp_cycles = 0;
3274 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3275 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3276 *timestamp = rte_ns_to_timespec(ns);
3281 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3282 struct timespec *timestamp)
3284 struct bnxt *bp = dev->data->dev_private;
3285 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3286 uint64_t tx_tstamp_cycles = 0;
3292 bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3293 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3294 *timestamp = rte_ns_to_timespec(ns);
3300 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3302 struct bnxt *bp = dev->data->dev_private;
3303 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3308 ptp->tc.nsec += delta;
3314 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3316 struct bnxt *bp = dev->data->dev_private;
3318 uint32_t dir_entries;
3319 uint32_t entry_length;
3321 rc = is_bnxt_in_error(bp);
3325 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3326 bp->pdev->addr.domain, bp->pdev->addr.bus,
3327 bp->pdev->addr.devid, bp->pdev->addr.function);
3329 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3333 return dir_entries * entry_length;
3337 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3338 struct rte_dev_eeprom_info *in_eeprom)
3340 struct bnxt *bp = dev->data->dev_private;
3345 rc = is_bnxt_in_error(bp);
3349 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3350 "len = %d\n", bp->pdev->addr.domain,
3351 bp->pdev->addr.bus, bp->pdev->addr.devid,
3352 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3354 if (in_eeprom->offset == 0) /* special offset value to get directory */
3355 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3358 index = in_eeprom->offset >> 24;
3359 offset = in_eeprom->offset & 0xffffff;
3362 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3363 in_eeprom->length, in_eeprom->data);
3368 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3371 case BNX_DIR_TYPE_CHIMP_PATCH:
3372 case BNX_DIR_TYPE_BOOTCODE:
3373 case BNX_DIR_TYPE_BOOTCODE_2:
3374 case BNX_DIR_TYPE_APE_FW:
3375 case BNX_DIR_TYPE_APE_PATCH:
3376 case BNX_DIR_TYPE_KONG_FW:
3377 case BNX_DIR_TYPE_KONG_PATCH:
3378 case BNX_DIR_TYPE_BONO_FW:
3379 case BNX_DIR_TYPE_BONO_PATCH:
3387 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3390 case BNX_DIR_TYPE_AVS:
3391 case BNX_DIR_TYPE_EXP_ROM_MBA:
3392 case BNX_DIR_TYPE_PCIE:
3393 case BNX_DIR_TYPE_TSCF_UCODE:
3394 case BNX_DIR_TYPE_EXT_PHY:
3395 case BNX_DIR_TYPE_CCM:
3396 case BNX_DIR_TYPE_ISCSI_BOOT:
3397 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3398 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3406 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3408 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3409 bnxt_dir_type_is_other_exec_format(dir_type);
3413 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3414 struct rte_dev_eeprom_info *in_eeprom)
3416 struct bnxt *bp = dev->data->dev_private;
3417 uint8_t index, dir_op;
3418 uint16_t type, ext, ordinal, attr;
3421 rc = is_bnxt_in_error(bp);
3425 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3426 "len = %d\n", bp->pdev->addr.domain,
3427 bp->pdev->addr.bus, bp->pdev->addr.devid,
3428 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3431 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3435 type = in_eeprom->magic >> 16;
3437 if (type == 0xffff) { /* special value for directory operations */
3438 index = in_eeprom->magic & 0xff;
3439 dir_op = in_eeprom->magic >> 8;
3443 case 0x0e: /* erase */
3444 if (in_eeprom->offset != ~in_eeprom->magic)
3446 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3452 /* Create or re-write an NVM item: */
3453 if (bnxt_dir_type_is_executable(type) == true)
3455 ext = in_eeprom->magic & 0xffff;
3456 ordinal = in_eeprom->offset >> 16;
3457 attr = in_eeprom->offset & 0xffff;
3459 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3460 in_eeprom->data, in_eeprom->length);
3467 static const struct eth_dev_ops bnxt_dev_ops = {
3468 .dev_infos_get = bnxt_dev_info_get_op,
3469 .dev_close = bnxt_dev_close_op,
3470 .dev_configure = bnxt_dev_configure_op,
3471 .dev_start = bnxt_dev_start_op,
3472 .dev_stop = bnxt_dev_stop_op,
3473 .dev_set_link_up = bnxt_dev_set_link_up_op,
3474 .dev_set_link_down = bnxt_dev_set_link_down_op,
3475 .stats_get = bnxt_stats_get_op,
3476 .stats_reset = bnxt_stats_reset_op,
3477 .rx_queue_setup = bnxt_rx_queue_setup_op,
3478 .rx_queue_release = bnxt_rx_queue_release_op,
3479 .tx_queue_setup = bnxt_tx_queue_setup_op,
3480 .tx_queue_release = bnxt_tx_queue_release_op,
3481 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3482 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3483 .reta_update = bnxt_reta_update_op,
3484 .reta_query = bnxt_reta_query_op,
3485 .rss_hash_update = bnxt_rss_hash_update_op,
3486 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3487 .link_update = bnxt_link_update_op,
3488 .promiscuous_enable = bnxt_promiscuous_enable_op,
3489 .promiscuous_disable = bnxt_promiscuous_disable_op,
3490 .allmulticast_enable = bnxt_allmulticast_enable_op,
3491 .allmulticast_disable = bnxt_allmulticast_disable_op,
3492 .mac_addr_add = bnxt_mac_addr_add_op,
3493 .mac_addr_remove = bnxt_mac_addr_remove_op,
3494 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3495 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3496 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3497 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3498 .vlan_filter_set = bnxt_vlan_filter_set_op,
3499 .vlan_offload_set = bnxt_vlan_offload_set_op,
3500 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3501 .mtu_set = bnxt_mtu_set_op,
3502 .mac_addr_set = bnxt_set_default_mac_addr_op,
3503 .xstats_get = bnxt_dev_xstats_get_op,
3504 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3505 .xstats_reset = bnxt_dev_xstats_reset_op,
3506 .fw_version_get = bnxt_fw_version_get,
3507 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3508 .rxq_info_get = bnxt_rxq_info_get_op,
3509 .txq_info_get = bnxt_txq_info_get_op,
3510 .dev_led_on = bnxt_dev_led_on_op,
3511 .dev_led_off = bnxt_dev_led_off_op,
3512 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3513 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3514 .rx_queue_count = bnxt_rx_queue_count_op,
3515 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3516 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3517 .rx_queue_start = bnxt_rx_queue_start,
3518 .rx_queue_stop = bnxt_rx_queue_stop,
3519 .tx_queue_start = bnxt_tx_queue_start,
3520 .tx_queue_stop = bnxt_tx_queue_stop,
3521 .filter_ctrl = bnxt_filter_ctrl_op,
3522 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3523 .get_eeprom_length = bnxt_get_eeprom_length_op,
3524 .get_eeprom = bnxt_get_eeprom_op,
3525 .set_eeprom = bnxt_set_eeprom_op,
3526 .timesync_enable = bnxt_timesync_enable,
3527 .timesync_disable = bnxt_timesync_disable,
3528 .timesync_read_time = bnxt_timesync_read_time,
3529 .timesync_write_time = bnxt_timesync_write_time,
3530 .timesync_adjust_time = bnxt_timesync_adjust_time,
3531 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3532 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3535 static void bnxt_dev_cleanup(struct bnxt *bp)
3537 bnxt_set_hwrm_link_config(bp, false);
3538 bp->link_info.link_up = 0;
3539 if (bp->dev_stopped == 0)
3540 bnxt_dev_stop_op(bp->eth_dev);
3542 bnxt_uninit_resources(bp, true);
3545 static int bnxt_restore_filters(struct bnxt *bp)
3547 struct rte_eth_dev *dev = bp->eth_dev;
3550 if (dev->data->all_multicast)
3551 ret = bnxt_allmulticast_enable_op(dev);
3552 if (dev->data->promiscuous)
3553 ret = bnxt_promiscuous_enable_op(dev);
3555 /* TODO restore other filters as well */
3559 static void bnxt_dev_recover(void *arg)
3561 struct bnxt *bp = arg;
3562 int timeout = bp->fw_reset_max_msecs;
3566 rc = bnxt_hwrm_ver_get(bp);
3569 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3570 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3571 } while (rc && timeout);
3574 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3578 rc = bnxt_init_resources(bp, true);
3581 "Failed to initialize resources after reset\n");
3584 /* clear reset flag as the device is initialized now */
3585 bp->flags &= ~BNXT_FLAG_FW_RESET;
3587 rc = bnxt_dev_start_op(bp->eth_dev);
3589 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3593 rc = bnxt_restore_filters(bp);
3597 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3600 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3601 bnxt_uninit_resources(bp, false);
3602 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3605 void bnxt_dev_reset_and_resume(void *arg)
3607 struct bnxt *bp = arg;
3610 bnxt_dev_cleanup(bp);
3612 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3613 bnxt_dev_recover, (void *)bp);
3615 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3618 static bool bnxt_vf_pciid(uint16_t id)
3620 if (id == BROADCOM_DEV_ID_57304_VF ||
3621 id == BROADCOM_DEV_ID_57406_VF ||
3622 id == BROADCOM_DEV_ID_5731X_VF ||
3623 id == BROADCOM_DEV_ID_5741X_VF ||
3624 id == BROADCOM_DEV_ID_57414_VF ||
3625 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3626 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3627 id == BROADCOM_DEV_ID_58802_VF ||
3628 id == BROADCOM_DEV_ID_57500_VF1 ||
3629 id == BROADCOM_DEV_ID_57500_VF2)
3634 bool bnxt_stratus_device(struct bnxt *bp)
3636 uint16_t id = bp->pdev->id.device_id;
3638 if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3639 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3640 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3645 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3647 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3648 struct bnxt *bp = eth_dev->data->dev_private;
3650 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3651 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3652 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3653 if (!bp->bar0 || !bp->doorbell_base) {
3654 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
3658 bp->eth_dev = eth_dev;
3664 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3665 struct bnxt_ctx_pg_info *ctx_pg,
3670 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3671 const struct rte_memzone *mz = NULL;
3672 char mz_name[RTE_MEMZONE_NAMESIZE];
3673 rte_iova_t mz_phys_addr;
3674 uint64_t valid_bits = 0;
3681 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3683 rmem->page_size = BNXT_PAGE_SIZE;
3684 rmem->pg_arr = ctx_pg->ctx_pg_arr;
3685 rmem->dma_arr = ctx_pg->ctx_dma_arr;
3686 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3688 valid_bits = PTU_PTE_VALID;
3690 if (rmem->nr_pages > 1) {
3691 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3692 "bnxt_ctx_pg_tbl%s_%x_%d",
3693 suffix, idx, bp->eth_dev->data->port_id);
3694 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3695 mz = rte_memzone_lookup(mz_name);
3697 mz = rte_memzone_reserve_aligned(mz_name,
3701 RTE_MEMZONE_SIZE_HINT_ONLY |
3702 RTE_MEMZONE_IOVA_CONTIG,
3708 memset(mz->addr, 0, mz->len);
3709 mz_phys_addr = mz->iova;
3710 if ((unsigned long)mz->addr == mz_phys_addr) {
3711 PMD_DRV_LOG(WARNING,
3712 "Memzone physical address same as virtual.\n");
3713 PMD_DRV_LOG(WARNING,
3714 "Using rte_mem_virt2iova()\n");
3715 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3716 if (mz_phys_addr == RTE_BAD_IOVA) {
3718 "unable to map addr to phys memory\n");
3722 rte_mem_lock_page(((char *)mz->addr));
3724 rmem->pg_tbl = mz->addr;
3725 rmem->pg_tbl_map = mz_phys_addr;
3726 rmem->pg_tbl_mz = mz;
3729 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
3730 suffix, idx, bp->eth_dev->data->port_id);
3731 mz = rte_memzone_lookup(mz_name);
3733 mz = rte_memzone_reserve_aligned(mz_name,
3737 RTE_MEMZONE_SIZE_HINT_ONLY |
3738 RTE_MEMZONE_IOVA_CONTIG,
3744 memset(mz->addr, 0, mz->len);
3745 mz_phys_addr = mz->iova;
3746 if ((unsigned long)mz->addr == mz_phys_addr) {
3747 PMD_DRV_LOG(WARNING,
3748 "Memzone physical address same as virtual.\n");
3749 PMD_DRV_LOG(WARNING,
3750 "Using rte_mem_virt2iova()\n");
3751 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
3752 rte_mem_lock_page(((char *)mz->addr) + sz);
3753 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3754 if (mz_phys_addr == RTE_BAD_IOVA) {
3756 "unable to map addr to phys memory\n");
3761 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
3762 rte_mem_lock_page(((char *)mz->addr) + sz);
3763 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
3764 rmem->dma_arr[i] = mz_phys_addr + sz;
3766 if (rmem->nr_pages > 1) {
3767 if (i == rmem->nr_pages - 2 &&
3768 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3769 valid_bits |= PTU_PTE_NEXT_TO_LAST;
3770 else if (i == rmem->nr_pages - 1 &&
3771 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
3772 valid_bits |= PTU_PTE_LAST;
3774 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
3780 if (rmem->vmem_size)
3781 rmem->vmem = (void **)mz->addr;
3782 rmem->dma_arr[0] = mz_phys_addr;
3786 static void bnxt_free_ctx_mem(struct bnxt *bp)
3790 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
3793 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
3794 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
3795 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
3796 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
3797 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
3798 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
3799 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
3800 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
3801 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
3802 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
3803 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
3805 for (i = 0; i < BNXT_MAX_Q; i++) {
3806 if (bp->ctx->tqm_mem[i])
3807 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
3814 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
3816 #define min_t(type, x, y) ({ \
3817 type __min1 = (x); \
3818 type __min2 = (y); \
3819 __min1 < __min2 ? __min1 : __min2; })
3821 #define max_t(type, x, y) ({ \
3822 type __max1 = (x); \
3823 type __max2 = (y); \
3824 __max1 > __max2 ? __max1 : __max2; })
3826 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
3828 int bnxt_alloc_ctx_mem(struct bnxt *bp)
3830 struct bnxt_ctx_pg_info *ctx_pg;
3831 struct bnxt_ctx_mem_info *ctx;
3832 uint32_t mem_size, ena, entries;
3835 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
3837 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
3841 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
3844 ctx_pg = &ctx->qp_mem;
3845 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
3846 mem_size = ctx->qp_entry_size * ctx_pg->entries;
3847 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
3851 ctx_pg = &ctx->srq_mem;
3852 ctx_pg->entries = ctx->srq_max_l2_entries;
3853 mem_size = ctx->srq_entry_size * ctx_pg->entries;
3854 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
3858 ctx_pg = &ctx->cq_mem;
3859 ctx_pg->entries = ctx->cq_max_l2_entries;
3860 mem_size = ctx->cq_entry_size * ctx_pg->entries;
3861 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
3865 ctx_pg = &ctx->vnic_mem;
3866 ctx_pg->entries = ctx->vnic_max_vnic_entries +
3867 ctx->vnic_max_ring_table_entries;
3868 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
3869 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
3873 ctx_pg = &ctx->stat_mem;
3874 ctx_pg->entries = ctx->stat_max_entries;
3875 mem_size = ctx->stat_entry_size * ctx_pg->entries;
3876 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
3880 entries = ctx->qp_max_l2_entries;
3881 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
3882 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
3883 ctx->tqm_max_entries_per_ring);
3884 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
3885 ctx_pg = ctx->tqm_mem[i];
3886 /* use min tqm entries for now. */
3887 ctx_pg->entries = entries;
3888 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
3889 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
3892 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
3895 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
3896 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
3899 "Failed to configure context mem: rc = %d\n", rc);
3901 ctx->flags |= BNXT_CTX_FLAG_INITED;
3906 static int bnxt_alloc_stats_mem(struct bnxt *bp)
3908 struct rte_pci_device *pci_dev = bp->pdev;
3909 char mz_name[RTE_MEMZONE_NAMESIZE];
3910 const struct rte_memzone *mz = NULL;
3911 uint32_t total_alloc_len;
3912 rte_iova_t mz_phys_addr;
3914 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
3917 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3918 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3919 pci_dev->addr.bus, pci_dev->addr.devid,
3920 pci_dev->addr.function, "rx_port_stats");
3921 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3922 mz = rte_memzone_lookup(mz_name);
3924 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
3925 sizeof(struct rx_port_stats_ext) + 512);
3927 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3930 RTE_MEMZONE_SIZE_HINT_ONLY |
3931 RTE_MEMZONE_IOVA_CONTIG);
3935 memset(mz->addr, 0, mz->len);
3936 mz_phys_addr = mz->iova;
3937 if ((unsigned long)mz->addr == mz_phys_addr) {
3938 PMD_DRV_LOG(WARNING,
3939 "Memzone physical address same as virtual.\n");
3940 PMD_DRV_LOG(WARNING,
3941 "Using rte_mem_virt2iova()\n");
3942 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3943 if (mz_phys_addr == RTE_BAD_IOVA) {
3945 "Can't map address to physical memory\n");
3950 bp->rx_mem_zone = (const void *)mz;
3951 bp->hw_rx_port_stats = mz->addr;
3952 bp->hw_rx_port_stats_map = mz_phys_addr;
3954 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3955 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
3956 pci_dev->addr.bus, pci_dev->addr.devid,
3957 pci_dev->addr.function, "tx_port_stats");
3958 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3959 mz = rte_memzone_lookup(mz_name);
3961 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
3962 sizeof(struct tx_port_stats_ext) + 512);
3964 mz = rte_memzone_reserve(mz_name,
3968 RTE_MEMZONE_SIZE_HINT_ONLY |
3969 RTE_MEMZONE_IOVA_CONTIG);
3973 memset(mz->addr, 0, mz->len);
3974 mz_phys_addr = mz->iova;
3975 if ((unsigned long)mz->addr == mz_phys_addr) {
3976 PMD_DRV_LOG(WARNING,
3977 "Memzone physical address same as virtual\n");
3978 PMD_DRV_LOG(WARNING,
3979 "Using rte_mem_virt2iova()\n");
3980 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3981 if (mz_phys_addr == RTE_BAD_IOVA) {
3983 "Can't map address to physical memory\n");
3988 bp->tx_mem_zone = (const void *)mz;
3989 bp->hw_tx_port_stats = mz->addr;
3990 bp->hw_tx_port_stats_map = mz_phys_addr;
3991 bp->flags |= BNXT_FLAG_PORT_STATS;
3993 /* Display extended statistics if FW supports it */
3994 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
3995 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
3996 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
3999 bp->hw_rx_port_stats_ext = (void *)
4000 ((uint8_t *)bp->hw_rx_port_stats +
4001 sizeof(struct rx_port_stats));
4002 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4003 sizeof(struct rx_port_stats);
4004 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4006 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4007 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4008 bp->hw_tx_port_stats_ext = (void *)
4009 ((uint8_t *)bp->hw_tx_port_stats +
4010 sizeof(struct tx_port_stats));
4011 bp->hw_tx_port_stats_ext_map =
4012 bp->hw_tx_port_stats_map +
4013 sizeof(struct tx_port_stats);
4014 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4020 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4022 struct bnxt *bp = eth_dev->data->dev_private;
4025 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4026 RTE_ETHER_ADDR_LEN *
4029 if (eth_dev->data->mac_addrs == NULL) {
4030 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4034 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4038 /* Generate a random MAC address, if none was assigned by PF */
4039 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4040 bnxt_eth_hw_addr_random(bp->mac_addr);
4042 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4043 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4044 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4046 rc = bnxt_hwrm_set_mac(bp);
4048 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4049 RTE_ETHER_ADDR_LEN);
4053 /* Copy the permanent MAC from the FUNC_QCAPS response */
4054 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4055 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4060 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4064 /* MAC is already configured in FW */
4065 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4068 /* Restore the old MAC configured */
4069 rc = bnxt_hwrm_set_mac(bp);
4071 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4076 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4081 #define ALLOW_FUNC(x) \
4083 uint32_t arg = (x); \
4084 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4085 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4088 /* Forward all requests if firmware is new enough */
4089 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4090 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4091 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4092 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4094 PMD_DRV_LOG(WARNING,
4095 "Firmware too old for VF mailbox functionality\n");
4096 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4100 * The following are used for driver cleanup. If we disallow these,
4101 * VF drivers can't clean up cleanly.
4103 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4104 ALLOW_FUNC(HWRM_VNIC_FREE);
4105 ALLOW_FUNC(HWRM_RING_FREE);
4106 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4107 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4108 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4109 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4110 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4111 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4114 static int bnxt_init_fw(struct bnxt *bp)
4119 rc = bnxt_hwrm_ver_get(bp);
4123 rc = bnxt_hwrm_func_reset(bp);
4127 rc = bnxt_hwrm_queue_qportcfg(bp);
4131 /* Get the MAX capabilities for this function */
4132 rc = bnxt_hwrm_func_qcaps(bp);
4136 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4140 if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4141 mtu != bp->eth_dev->data->mtu)
4142 bp->eth_dev->data->mtu = mtu;
4144 bnxt_hwrm_port_led_qcaps(bp);
4149 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4153 rc = bnxt_init_fw(bp);
4157 if (!reconfig_dev) {
4158 rc = bnxt_setup_mac_addr(bp->eth_dev);
4162 rc = bnxt_restore_dflt_mac(bp);
4167 bnxt_config_vf_req_fwd(bp);
4169 rc = bnxt_hwrm_func_driver_register(bp);
4171 PMD_DRV_LOG(ERR, "Failed to register driver");
4176 if (bp->pdev->max_vfs) {
4177 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4179 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4183 rc = bnxt_hwrm_allocate_pf_only(bp);
4186 "Failed to allocate PF resources");
4192 rc = bnxt_alloc_mem(bp, reconfig_dev);
4196 rc = bnxt_setup_int(bp);
4202 rc = bnxt_request_int(bp);
4210 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4212 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4213 static int version_printed;
4217 if (version_printed++ == 0)
4218 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4220 rte_eth_copy_pci_info(eth_dev, pci_dev);
4222 bp = eth_dev->data->dev_private;
4224 bp->dev_stopped = 1;
4226 eth_dev->dev_ops = &bnxt_dev_ops;
4227 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4228 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4231 * For secondary processes, we don't initialise any further
4232 * as primary has already done this work.
4234 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4237 if (bnxt_vf_pciid(pci_dev->id.device_id))
4238 bp->flags |= BNXT_FLAG_VF;
4240 if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4241 pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4242 pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4243 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4244 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4245 bp->flags |= BNXT_FLAG_THOR_CHIP;
4247 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4248 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4249 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4250 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4251 bp->flags |= BNXT_FLAG_STINGRAY;
4253 rc = bnxt_init_board(eth_dev);
4256 "Failed to initialize board rc: %x\n", rc);
4260 rc = bnxt_alloc_hwrm_resources(bp);
4263 "Failed to allocate hwrm resource rc: %x\n", rc);
4266 rc = bnxt_init_resources(bp, false);
4270 rc = bnxt_alloc_stats_mem(bp);
4275 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4276 pci_dev->mem_resource[0].phys_addr,
4277 pci_dev->mem_resource[0].addr);
4282 bnxt_dev_uninit(eth_dev);
4287 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4291 bnxt_disable_int(bp);
4293 bnxt_free_mem(bp, reconfig_dev);
4294 bnxt_hwrm_func_buf_unrgtr(bp);
4295 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4296 bp->flags &= ~BNXT_FLAG_REGISTERED;
4297 bnxt_free_ctx_mem(bp);
4299 bnxt_free_hwrm_resources(bp);
4305 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4307 struct bnxt *bp = eth_dev->data->dev_private;
4310 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4313 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4315 rc = bnxt_uninit_resources(bp, false);
4317 if (bp->grp_info != NULL) {
4318 rte_free(bp->grp_info);
4319 bp->grp_info = NULL;
4322 if (bp->tx_mem_zone) {
4323 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4324 bp->tx_mem_zone = NULL;
4327 if (bp->rx_mem_zone) {
4328 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4329 bp->rx_mem_zone = NULL;
4332 if (bp->dev_stopped == 0)
4333 bnxt_dev_close_op(eth_dev);
4335 rte_free(bp->pf.vf_info);
4336 eth_dev->dev_ops = NULL;
4337 eth_dev->rx_pkt_burst = NULL;
4338 eth_dev->tx_pkt_burst = NULL;
4343 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4344 struct rte_pci_device *pci_dev)
4346 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4350 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4352 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4353 return rte_eth_dev_pci_generic_remove(pci_dev,
4356 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4359 static struct rte_pci_driver bnxt_rte_pmd = {
4360 .id_table = bnxt_pci_id_map,
4361 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4362 .probe = bnxt_pci_probe,
4363 .remove = bnxt_pci_remove,
4367 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4369 if (strcmp(dev->device->driver->name, drv->driver.name))
4375 bool is_bnxt_supported(struct rte_eth_dev *dev)
4377 return is_device_supported(dev, &bnxt_rte_pmd);
4380 RTE_INIT(bnxt_init_log)
4382 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4383 if (bnxt_logtype_driver >= 0)
4384 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4387 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4388 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4389 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");