6c4a2ae8596c96635e636b9cd2d212d3774a55f9
[dpdk.git] / drivers / net / bnxt / bnxt_ethdev.c
1 /*-
2  *   BSD LICENSE
3  *
4  *   Copyright(c) Broadcom Limited.
5  *   All rights reserved.
6  *
7  *   Redistribution and use in source and binary forms, with or without
8  *   modification, are permitted provided that the following conditions
9  *   are met:
10  *
11  *     * Redistributions of source code must retain the above copyright
12  *       notice, this list of conditions and the following disclaimer.
13  *     * Redistributions in binary form must reproduce the above copyright
14  *       notice, this list of conditions and the following disclaimer in
15  *       the documentation and/or other materials provided with the
16  *       distribution.
17  *     * Neither the name of Broadcom Corporation nor the names of its
18  *       contributors may be used to endorse or promote products derived
19  *       from this software without specific prior written permission.
20  *
21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  */
33
34 #include <inttypes.h>
35 #include <stdbool.h>
36
37 #include <rte_dev.h>
38 #include <rte_ethdev.h>
39 #include <rte_malloc.h>
40 #include <rte_cycles.h>
41
42 #include "bnxt.h"
43 #include "bnxt_cpr.h"
44 #include "bnxt_filter.h"
45 #include "bnxt_hwrm.h"
46 #include "bnxt_ring.h"
47 #include "bnxt_rxq.h"
48 #include "bnxt_rxr.h"
49 #include "bnxt_stats.h"
50 #include "bnxt_txq.h"
51 #include "bnxt_txr.h"
52 #include "bnxt_vnic.h"
53 #include "hsi_struct_def_dpdk.h"
54
55 #define DRV_MODULE_NAME         "bnxt"
56 static const char bnxt_version[] =
57         "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
58
59 #define PCI_VENDOR_ID_BROADCOM 0x14E4
60
61 #define BROADCOM_DEV_ID_57301 0x16c8
62 #define BROADCOM_DEV_ID_57302 0x16c9
63 #define BROADCOM_DEV_ID_57304_PF 0x16ca
64 #define BROADCOM_DEV_ID_57304_VF 0x16cb
65 #define BROADCOM_DEV_ID_57417_MF 0x16cc
66 #define BROADCOM_DEV_ID_NS2 0x16cd
67 #define BROADCOM_DEV_ID_57311 0x16ce
68 #define BROADCOM_DEV_ID_57312 0x16cf
69 #define BROADCOM_DEV_ID_57402 0x16d0
70 #define BROADCOM_DEV_ID_57404 0x16d1
71 #define BROADCOM_DEV_ID_57406_PF 0x16d2
72 #define BROADCOM_DEV_ID_57406_VF 0x16d3
73 #define BROADCOM_DEV_ID_57402_MF 0x16d4
74 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
75 #define BROADCOM_DEV_ID_57412 0x16d6
76 #define BROADCOM_DEV_ID_57414 0x16d7
77 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
78 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
79 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
80 #define BROADCOM_DEV_ID_57412_MF 0x16de
81 #define BROADCOM_DEV_ID_57314 0x16df
82 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
83 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
84 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
85 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
86 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
87 #define BROADCOM_DEV_ID_57404_MF 0x16e7
88 #define BROADCOM_DEV_ID_57406_MF 0x16e8
89 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
90 #define BROADCOM_DEV_ID_57407_MF 0x16ea
91 #define BROADCOM_DEV_ID_57414_MF 0x16ec
92 #define BROADCOM_DEV_ID_57416_MF 0x16ee
93
94 static struct rte_pci_id bnxt_pci_id_map[] = {
95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
127         { .vendor_id = 0, /* sentinel */ },
128 };
129
130 #define BNXT_ETH_RSS_SUPPORT (  \
131         ETH_RSS_IPV4 |          \
132         ETH_RSS_NONFRAG_IPV4_TCP |      \
133         ETH_RSS_NONFRAG_IPV4_UDP |      \
134         ETH_RSS_IPV6 |          \
135         ETH_RSS_NONFRAG_IPV6_TCP |      \
136         ETH_RSS_NONFRAG_IPV6_UDP)
137
138 /***********************/
139
140 /*
141  * High level utility functions
142  */
143
144 static void bnxt_free_mem(struct bnxt *bp)
145 {
146         bnxt_free_filter_mem(bp);
147         bnxt_free_vnic_attributes(bp);
148         bnxt_free_vnic_mem(bp);
149
150         bnxt_free_stats(bp);
151         bnxt_free_tx_rings(bp);
152         bnxt_free_rx_rings(bp);
153         bnxt_free_def_cp_ring(bp);
154 }
155
156 static int bnxt_alloc_mem(struct bnxt *bp)
157 {
158         int rc;
159
160         /* Default completion ring */
161         rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
162         if (rc)
163                 goto alloc_mem_err;
164
165         rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
166                               bp->def_cp_ring, "def_cp");
167         if (rc)
168                 goto alloc_mem_err;
169
170         rc = bnxt_alloc_vnic_mem(bp);
171         if (rc)
172                 goto alloc_mem_err;
173
174         rc = bnxt_alloc_vnic_attributes(bp);
175         if (rc)
176                 goto alloc_mem_err;
177
178         rc = bnxt_alloc_filter_mem(bp);
179         if (rc)
180                 goto alloc_mem_err;
181
182         return 0;
183
184 alloc_mem_err:
185         bnxt_free_mem(bp);
186         return rc;
187 }
188
189 static int bnxt_init_chip(struct bnxt *bp)
190 {
191         unsigned int i, rss_idx, fw_idx;
192         int rc;
193
194         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
195         if (rc) {
196                 RTE_LOG(ERR, PMD, "HWRM stat ctx alloc failure rc: %x\n", rc);
197                 goto err_out;
198         }
199
200         rc = bnxt_alloc_hwrm_rings(bp);
201         if (rc) {
202                 RTE_LOG(ERR, PMD, "HWRM ring alloc failure rc: %x\n", rc);
203                 goto err_out;
204         }
205
206         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
207         if (rc) {
208                 RTE_LOG(ERR, PMD, "HWRM ring grp alloc failure: %x\n", rc);
209                 goto err_out;
210         }
211
212         rc = bnxt_mq_rx_configure(bp);
213         if (rc) {
214                 RTE_LOG(ERR, PMD, "MQ mode configure failure rc: %x\n", rc);
215                 goto err_out;
216         }
217
218         /* VNIC configuration */
219         for (i = 0; i < bp->nr_vnics; i++) {
220                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
221
222                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
223                 if (rc) {
224                         RTE_LOG(ERR, PMD, "HWRM vnic alloc failure rc: %x\n",
225                                 rc);
226                         goto err_out;
227                 }
228
229                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
230                 if (rc) {
231                         RTE_LOG(ERR, PMD,
232                                 "HWRM vnic ctx alloc failure rc: %x\n", rc);
233                         goto err_out;
234                 }
235
236                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
237                 if (rc) {
238                         RTE_LOG(ERR, PMD, "HWRM vnic cfg failure rc: %x\n", rc);
239                         goto err_out;
240                 }
241
242                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
243                 if (rc) {
244                         RTE_LOG(ERR, PMD, "HWRM vnic filter failure rc: %x\n",
245                                 rc);
246                         goto err_out;
247                 }
248                 if (vnic->rss_table && vnic->hash_type) {
249                         /*
250                          * Fill the RSS hash & redirection table with
251                          * ring group ids for all VNICs
252                          */
253                         for (rss_idx = 0, fw_idx = 0;
254                              rss_idx < HW_HASH_INDEX_SIZE;
255                              rss_idx++, fw_idx++) {
256                                 if (vnic->fw_grp_ids[fw_idx] ==
257                                     INVALID_HW_RING_ID)
258                                         fw_idx = 0;
259                                 vnic->rss_table[rss_idx] =
260                                                 vnic->fw_grp_ids[fw_idx];
261                         }
262                         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
263                         if (rc) {
264                                 RTE_LOG(ERR, PMD,
265                                         "HWRM vnic set RSS failure rc: %x\n",
266                                         rc);
267                                 goto err_out;
268                         }
269                 }
270         }
271         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0]);
272         if (rc) {
273                 RTE_LOG(ERR, PMD,
274                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
275                 goto err_out;
276         }
277
278         return 0;
279
280 err_out:
281         bnxt_free_all_hwrm_resources(bp);
282
283         return rc;
284 }
285
286 static int bnxt_shutdown_nic(struct bnxt *bp)
287 {
288         bnxt_free_all_hwrm_resources(bp);
289         bnxt_free_all_filters(bp);
290         bnxt_free_all_vnics(bp);
291         return 0;
292 }
293
294 static int bnxt_init_nic(struct bnxt *bp)
295 {
296         int rc;
297
298         bnxt_init_ring_grps(bp);
299         bnxt_init_vnics(bp);
300         bnxt_init_filters(bp);
301
302         rc = bnxt_init_chip(bp);
303         if (rc)
304                 return rc;
305
306         return 0;
307 }
308
309 /*
310  * Device configuration and status function
311  */
312
313 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
314                                   struct rte_eth_dev_info *dev_info)
315 {
316         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
317         uint16_t max_vnics, i, j, vpool, vrxq;
318
319         /* MAC Specifics */
320         dev_info->max_mac_addrs = MAX_NUM_MAC_ADDR;
321         dev_info->max_hash_mac_addrs = 0;
322
323         /* PF/VF specifics */
324         if (BNXT_PF(bp)) {
325                 dev_info->max_rx_queues = bp->pf.max_rx_rings;
326                 dev_info->max_tx_queues = bp->pf.max_tx_rings;
327                 dev_info->max_vfs = bp->pf.active_vfs;
328                 dev_info->reta_size = bp->pf.max_rsscos_ctx;
329                 max_vnics = bp->pf.max_vnics;
330         } else {
331                 dev_info->max_rx_queues = bp->vf.max_rx_rings;
332                 dev_info->max_tx_queues = bp->vf.max_tx_rings;
333                 dev_info->reta_size = bp->vf.max_rsscos_ctx;
334                 max_vnics = bp->vf.max_vnics;
335         }
336
337         /* Fast path specifics */
338         dev_info->min_rx_bufsize = 1;
339         dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
340                                   + VLAN_TAG_SIZE;
341         dev_info->rx_offload_capa = 0;
342         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_IPV4_CKSUM |
343                                         DEV_TX_OFFLOAD_TCP_CKSUM |
344                                         DEV_TX_OFFLOAD_UDP_CKSUM |
345                                         DEV_TX_OFFLOAD_TCP_TSO;
346
347         /* *INDENT-OFF* */
348         dev_info->default_rxconf = (struct rte_eth_rxconf) {
349                 .rx_thresh = {
350                         .pthresh = 8,
351                         .hthresh = 8,
352                         .wthresh = 0,
353                 },
354                 .rx_free_thresh = 32,
355                 .rx_drop_en = 0,
356         };
357
358         dev_info->default_txconf = (struct rte_eth_txconf) {
359                 .tx_thresh = {
360                         .pthresh = 32,
361                         .hthresh = 0,
362                         .wthresh = 0,
363                 },
364                 .tx_free_thresh = 32,
365                 .tx_rs_thresh = 32,
366                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
367                              ETH_TXQ_FLAGS_NOOFFLOADS,
368         };
369         /* *INDENT-ON* */
370
371         /*
372          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
373          *       need further investigation.
374          */
375
376         /* VMDq resources */
377         vpool = 64; /* ETH_64_POOLS */
378         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
379         for (i = 0; i < 4; vpool >>= 1, i++) {
380                 if (max_vnics > vpool) {
381                         for (j = 0; j < 5; vrxq >>= 1, j++) {
382                                 if (dev_info->max_rx_queues > vrxq) {
383                                         if (vpool > vrxq)
384                                                 vpool = vrxq;
385                                         goto found;
386                                 }
387                         }
388                         /* Not enough resources to support VMDq */
389                         break;
390                 }
391         }
392         /* Not enough resources to support VMDq */
393         vpool = 0;
394         vrxq = 0;
395 found:
396         dev_info->max_vmdq_pools = vpool;
397         dev_info->vmdq_queue_num = vrxq;
398
399         dev_info->vmdq_pool_base = 0;
400         dev_info->vmdq_queue_base = 0;
401 }
402
403 /* Configure the device based on the configuration provided */
404 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
405 {
406         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
407         int rc;
408
409         bp->rx_queues = (void *)eth_dev->data->rx_queues;
410         bp->tx_queues = (void *)eth_dev->data->tx_queues;
411
412         /* Inherit new configurations */
413         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
414         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
415         bp->rx_cp_nr_rings = bp->rx_nr_rings;
416         bp->tx_cp_nr_rings = bp->tx_nr_rings;
417
418         if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
419                 eth_dev->data->mtu =
420                                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
421                                 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
422         rc = bnxt_set_hwrm_link_config(bp, true);
423         return rc;
424 }
425
426 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
427 {
428         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
429         int rc;
430
431         rc = bnxt_hwrm_func_reset(bp);
432         if (rc) {
433                 RTE_LOG(ERR, PMD, "hwrm chip reset failure rc: %x\n", rc);
434                 rc = -1;
435                 goto error;
436         }
437
438         rc = bnxt_alloc_mem(bp);
439         if (rc)
440                 goto error;
441
442         rc = bnxt_init_nic(bp);
443         if (rc)
444                 goto error;
445
446         return 0;
447
448 error:
449         bnxt_shutdown_nic(bp);
450         bnxt_free_tx_mbufs(bp);
451         bnxt_free_rx_mbufs(bp);
452         bnxt_free_mem(bp);
453         return rc;
454 }
455
456 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
457 {
458         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
459
460         eth_dev->data->dev_link.link_status = 1;
461         bnxt_set_hwrm_link_config(bp, true);
462         return 0;
463 }
464
465 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
466 {
467         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
468
469         eth_dev->data->dev_link.link_status = 0;
470         bnxt_set_hwrm_link_config(bp, false);
471         return 0;
472 }
473
474 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
475 {
476         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
477
478         bnxt_free_tx_mbufs(bp);
479         bnxt_free_rx_mbufs(bp);
480         bnxt_free_mem(bp);
481         rte_free(eth_dev->data->mac_addrs);
482 }
483
484 /* Unload the driver, release resources */
485 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
486 {
487         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
488
489         if (bp->eth_dev->data->dev_started) {
490                 /* TBD: STOP HW queues DMA */
491                 eth_dev->data->dev_link.link_status = 0;
492         }
493         bnxt_shutdown_nic(bp);
494 }
495
496 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
497                                     uint32_t index)
498 {
499         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
500         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
501         struct bnxt_vnic_info *vnic;
502         struct bnxt_filter_info *filter, *temp_filter;
503         int i;
504
505         /*
506          * Loop through all VNICs from the specified filter flow pools to
507          * remove the corresponding MAC addr filter
508          */
509         for (i = 0; i < MAX_FF_POOLS; i++) {
510                 if (!(pool_mask & (1 << i)))
511                         continue;
512
513                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
514                         filter = STAILQ_FIRST(&vnic->filter);
515                         while (filter) {
516                                 temp_filter = STAILQ_NEXT(filter, next);
517                                 if (filter->mac_index == index) {
518                                         STAILQ_REMOVE(&vnic->filter, filter,
519                                                       bnxt_filter_info, next);
520                                         bnxt_hwrm_clear_filter(bp, filter);
521                                         filter->mac_index = INVALID_MAC_INDEX;
522                                         memset(&filter->l2_addr, 0,
523                                                ETHER_ADDR_LEN);
524                                         STAILQ_INSERT_TAIL(
525                                                         &bp->free_filter_list,
526                                                         filter, next);
527                                 }
528                                 filter = temp_filter;
529                         }
530                 }
531         }
532 }
533
534 static void bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
535                                  struct ether_addr *mac_addr,
536                                  uint32_t index, uint32_t pool)
537 {
538         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
539         struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
540         struct bnxt_filter_info *filter;
541
542         if (!vnic) {
543                 RTE_LOG(ERR, PMD, "VNIC not found for pool %d!\n", pool);
544                 return;
545         }
546         /* Attach requested MAC address to the new l2_filter */
547         STAILQ_FOREACH(filter, &vnic->filter, next) {
548                 if (filter->mac_index == index) {
549                         RTE_LOG(ERR, PMD,
550                                 "MAC addr already existed for pool %d\n", pool);
551                         return;
552                 }
553         }
554         filter = bnxt_alloc_filter(bp);
555         if (!filter) {
556                 RTE_LOG(ERR, PMD, "L2 filter alloc failed\n");
557                 return;
558         }
559         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
560         filter->mac_index = index;
561         memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
562         bnxt_hwrm_set_filter(bp, vnic, filter);
563 }
564
565 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
566                                int wait_to_complete)
567 {
568         int rc = 0;
569         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
570         struct rte_eth_link new;
571         unsigned int cnt = BNXT_LINK_WAIT_CNT;
572
573         memset(&new, 0, sizeof(new));
574         do {
575                 /* Retrieve link info from hardware */
576                 rc = bnxt_get_hwrm_link_config(bp, &new);
577                 if (rc) {
578                         new.link_speed = ETH_LINK_SPEED_100M;
579                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
580                         RTE_LOG(ERR, PMD,
581                                 "Failed to retrieve link rc = 0x%x!", rc);
582                         goto out;
583                 }
584                 if (!wait_to_complete)
585                         break;
586
587                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
588
589         } while (!new.link_status && cnt--);
590
591         /* Timed out or success */
592         if (new.link_status) {
593                 /* Update only if success */
594                 eth_dev->data->dev_link.link_duplex = new.link_duplex;
595                 eth_dev->data->dev_link.link_speed = new.link_speed;
596         }
597         eth_dev->data->dev_link.link_status = new.link_status;
598 out:
599         return rc;
600 }
601
602 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
603 {
604         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
605         struct bnxt_vnic_info *vnic;
606
607         if (bp->vnic_info == NULL)
608                 return;
609
610         vnic = &bp->vnic_info[0];
611
612         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
613         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
614 }
615
616 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
617 {
618         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
619         struct bnxt_vnic_info *vnic;
620
621         if (bp->vnic_info == NULL)
622                 return;
623
624         vnic = &bp->vnic_info[0];
625
626         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
627         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
628 }
629
630 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
631 {
632         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
633         struct bnxt_vnic_info *vnic;
634
635         if (bp->vnic_info == NULL)
636                 return;
637
638         vnic = &bp->vnic_info[0];
639
640         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
641         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
642 }
643
644 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
645 {
646         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
647         struct bnxt_vnic_info *vnic;
648
649         if (bp->vnic_info == NULL)
650                 return;
651
652         vnic = &bp->vnic_info[0];
653
654         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
655         bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic);
656 }
657
658 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
659                             struct rte_eth_rss_reta_entry64 *reta_conf,
660                             uint16_t reta_size)
661 {
662         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
663         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
664         struct bnxt_vnic_info *vnic;
665         int i;
666
667         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
668                 return -EINVAL;
669
670         if (reta_size != HW_HASH_INDEX_SIZE) {
671                 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
672                         "(%d) must equal the size supported by the hardware "
673                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
674                 return -EINVAL;
675         }
676         /* Update the RSS VNIC(s) */
677         for (i = 0; i < MAX_FF_POOLS; i++) {
678                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
679                         memcpy(vnic->rss_table, reta_conf, reta_size);
680
681                         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
682                 }
683         }
684         return 0;
685 }
686
687 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
688                               struct rte_eth_rss_reta_entry64 *reta_conf,
689                               uint16_t reta_size)
690 {
691         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
692         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
693
694         /* Retrieve from the default VNIC */
695         if (!vnic)
696                 return -EINVAL;
697         if (!vnic->rss_table)
698                 return -EINVAL;
699
700         if (reta_size != HW_HASH_INDEX_SIZE) {
701                 RTE_LOG(ERR, PMD, "The configured hash table lookup size "
702                         "(%d) must equal the size supported by the hardware "
703                         "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
704                 return -EINVAL;
705         }
706         /* EW - need to revisit here copying from u64 to u16 */
707         memcpy(reta_conf, vnic->rss_table, reta_size);
708
709         return 0;
710 }
711
712 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
713                                    struct rte_eth_rss_conf *rss_conf)
714 {
715         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
716         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
717         struct bnxt_vnic_info *vnic;
718         uint16_t hash_type = 0;
719         int i;
720
721         /*
722          * If RSS enablement were different than dev_configure,
723          * then return -EINVAL
724          */
725         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
726                 if (!rss_conf->rss_hf)
727                         return -EINVAL;
728         } else {
729                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
730                         return -EINVAL;
731         }
732         if (rss_conf->rss_hf & ETH_RSS_IPV4)
733                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
734         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
735                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
736         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
737                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
738         if (rss_conf->rss_hf & ETH_RSS_IPV6)
739                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
740         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
741                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
742         if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
743                 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
744
745         /* Update the RSS VNIC(s) */
746         for (i = 0; i < MAX_FF_POOLS; i++) {
747                 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
748                         vnic->hash_type = hash_type;
749
750                         /*
751                          * Use the supplied key if the key length is
752                          * acceptable and the rss_key is not NULL
753                          */
754                         if (rss_conf->rss_key &&
755                             rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
756                                 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
757                                        rss_conf->rss_key_len);
758
759                         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
760                 }
761         }
762         return 0;
763 }
764
765 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
766                                      struct rte_eth_rss_conf *rss_conf)
767 {
768         struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
769         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
770         int len;
771         uint32_t hash_types;
772
773         /* RSS configuration is the same for all VNICs */
774         if (vnic && vnic->rss_hash_key) {
775                 if (rss_conf->rss_key) {
776                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
777                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
778                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
779                 }
780
781                 hash_types = vnic->hash_type;
782                 rss_conf->rss_hf = 0;
783                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
784                         rss_conf->rss_hf |= ETH_RSS_IPV4;
785                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
786                 }
787                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
788                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
789                         hash_types &=
790                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
791                 }
792                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
793                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
794                         hash_types &=
795                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
796                 }
797                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
798                         rss_conf->rss_hf |= ETH_RSS_IPV6;
799                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
800                 }
801                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
802                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
803                         hash_types &=
804                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
805                 }
806                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
807                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
808                         hash_types &=
809                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
810                 }
811                 if (hash_types) {
812                         RTE_LOG(ERR, PMD,
813                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
814                                 vnic->hash_type);
815                         return -ENOTSUP;
816                 }
817         } else {
818                 rss_conf->rss_hf = 0;
819         }
820         return 0;
821 }
822
823 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
824                                struct rte_eth_fc_conf *fc_conf __rte_unused)
825 {
826         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
827         struct rte_eth_link link_info;
828         int rc;
829
830         rc = bnxt_get_hwrm_link_config(bp, &link_info);
831         if (rc)
832                 return rc;
833
834         memset(fc_conf, 0, sizeof(*fc_conf));
835         if (bp->link_info.auto_pause)
836                 fc_conf->autoneg = 1;
837         switch (bp->link_info.pause) {
838         case 0:
839                 fc_conf->mode = RTE_FC_NONE;
840                 break;
841         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
842                 fc_conf->mode = RTE_FC_TX_PAUSE;
843                 break;
844         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
845                 fc_conf->mode = RTE_FC_RX_PAUSE;
846                 break;
847         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
848                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
849                 fc_conf->mode = RTE_FC_FULL;
850                 break;
851         }
852         return 0;
853 }
854
855 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
856                                struct rte_eth_fc_conf *fc_conf)
857 {
858         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
859
860         if (BNXT_NPAR_PF(bp))
861                 return 0;
862
863         switch (fc_conf->mode) {
864         case RTE_FC_NONE:
865                 bp->link_info.auto_pause = 0;
866                 bp->link_info.force_pause = 0;
867                 break;
868         case RTE_FC_RX_PAUSE:
869                 if (fc_conf->autoneg) {
870                         bp->link_info.auto_pause =
871                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
872                         bp->link_info.force_pause = 0;
873                 } else {
874                         bp->link_info.auto_pause = 0;
875                         bp->link_info.force_pause =
876                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
877                 }
878                 break;
879         case RTE_FC_TX_PAUSE:
880                 if (fc_conf->autoneg) {
881                         bp->link_info.auto_pause =
882                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
883                         bp->link_info.force_pause = 0;
884                 } else {
885                         bp->link_info.auto_pause = 0;
886                         bp->link_info.force_pause =
887                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
888                 }
889                 break;
890         case RTE_FC_FULL:
891                 if (fc_conf->autoneg) {
892                         bp->link_info.auto_pause =
893                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
894                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
895                         bp->link_info.force_pause = 0;
896                 } else {
897                         bp->link_info.auto_pause = 0;
898                         bp->link_info.force_pause =
899                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
900                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
901                 }
902                 break;
903         }
904         return bnxt_set_hwrm_link_config(bp, true);
905 }
906
907 /*
908  * Initialization
909  */
910
911 static struct eth_dev_ops bnxt_dev_ops = {
912         .dev_infos_get = bnxt_dev_info_get_op,
913         .dev_close = bnxt_dev_close_op,
914         .dev_configure = bnxt_dev_configure_op,
915         .dev_start = bnxt_dev_start_op,
916         .dev_stop = bnxt_dev_stop_op,
917         .dev_set_link_up = bnxt_dev_set_link_up_op,
918         .dev_set_link_down = bnxt_dev_set_link_down_op,
919         .stats_get = bnxt_stats_get_op,
920         .stats_reset = bnxt_stats_reset_op,
921         .rx_queue_setup = bnxt_rx_queue_setup_op,
922         .rx_queue_release = bnxt_rx_queue_release_op,
923         .tx_queue_setup = bnxt_tx_queue_setup_op,
924         .tx_queue_release = bnxt_tx_queue_release_op,
925         .reta_update = bnxt_reta_update_op,
926         .reta_query = bnxt_reta_query_op,
927         .rss_hash_update = bnxt_rss_hash_update_op,
928         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
929         .link_update = bnxt_link_update_op,
930         .promiscuous_enable = bnxt_promiscuous_enable_op,
931         .promiscuous_disable = bnxt_promiscuous_disable_op,
932         .allmulticast_enable = bnxt_allmulticast_enable_op,
933         .allmulticast_disable = bnxt_allmulticast_disable_op,
934         .mac_addr_add = bnxt_mac_addr_add_op,
935         .mac_addr_remove = bnxt_mac_addr_remove_op,
936         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
937         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
938 };
939
940 static bool bnxt_vf_pciid(uint16_t id)
941 {
942         if (id == BROADCOM_DEV_ID_57304_VF ||
943             id == BROADCOM_DEV_ID_57406_VF)
944                 return true;
945         return false;
946 }
947
948 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
949 {
950         int rc;
951         struct bnxt *bp = eth_dev->data->dev_private;
952
953         /* enable device (incl. PCI PM wakeup), and bus-mastering */
954         if (!eth_dev->pci_dev->mem_resource[0].addr) {
955                 RTE_LOG(ERR, PMD,
956                         "Cannot find PCI device base address, aborting\n");
957                 rc = -ENODEV;
958                 goto init_err_disable;
959         }
960
961         bp->eth_dev = eth_dev;
962         bp->pdev = eth_dev->pci_dev;
963
964         bp->bar0 = (void *)eth_dev->pci_dev->mem_resource[0].addr;
965         if (!bp->bar0) {
966                 RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n");
967                 rc = -ENOMEM;
968                 goto init_err_release;
969         }
970         return 0;
971
972 init_err_release:
973         if (bp->bar0)
974                 bp->bar0 = NULL;
975
976 init_err_disable:
977
978         return rc;
979 }
980
981 static int
982 bnxt_dev_init(struct rte_eth_dev *eth_dev)
983 {
984         static int version_printed;
985         struct bnxt *bp;
986         int rc;
987
988         if (version_printed++ == 0)
989                 RTE_LOG(INFO, PMD, "%s", bnxt_version);
990
991         rte_eth_copy_pci_info(eth_dev, eth_dev->pci_dev);
992         bp = eth_dev->data->dev_private;
993
994         if (bnxt_vf_pciid(eth_dev->pci_dev->id.device_id))
995                 bp->flags |= BNXT_FLAG_VF;
996
997         rc = bnxt_init_board(eth_dev);
998         if (rc) {
999                 RTE_LOG(ERR, PMD,
1000                         "Board initialization failed rc: %x\n", rc);
1001                 goto error;
1002         }
1003         eth_dev->dev_ops = &bnxt_dev_ops;
1004         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
1005         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
1006
1007         rc = bnxt_alloc_hwrm_resources(bp);
1008         if (rc) {
1009                 RTE_LOG(ERR, PMD,
1010                         "hwrm resource allocation failure rc: %x\n", rc);
1011                 goto error_free;
1012         }
1013         rc = bnxt_hwrm_ver_get(bp);
1014         if (rc)
1015                 goto error_free;
1016         bnxt_hwrm_queue_qportcfg(bp);
1017
1018         bnxt_hwrm_func_qcfg(bp);
1019
1020         /* Get the MAX capabilities for this function */
1021         rc = bnxt_hwrm_func_qcaps(bp);
1022         if (rc) {
1023                 RTE_LOG(ERR, PMD, "hwrm query capability failure rc: %x\n", rc);
1024                 goto error_free;
1025         }
1026         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
1027                                         ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR, 0);
1028         if (eth_dev->data->mac_addrs == NULL) {
1029                 RTE_LOG(ERR, PMD,
1030                         "Failed to alloc %u bytes needed to store MAC addr tbl",
1031                         ETHER_ADDR_LEN * MAX_NUM_MAC_ADDR);
1032                 rc = -ENOMEM;
1033                 goto error_free;
1034         }
1035         /* Copy the permanent MAC from the qcap response address now. */
1036         if (BNXT_PF(bp))
1037                 memcpy(bp->mac_addr, bp->pf.mac_addr, sizeof(bp->mac_addr));
1038         else
1039                 memcpy(bp->mac_addr, bp->vf.mac_addr, sizeof(bp->mac_addr));
1040         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
1041         bp->grp_info = rte_zmalloc("bnxt_grp_info",
1042                                 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
1043         if (!bp->grp_info) {
1044                 RTE_LOG(ERR, PMD,
1045                         "Failed to alloc %zu bytes needed to store group info table\n",
1046                         sizeof(*bp->grp_info) * bp->max_ring_grps);
1047                 rc = -ENOMEM;
1048                 goto error_free;
1049         }
1050
1051         rc = bnxt_hwrm_func_driver_register(bp, 0,
1052                                             bp->pf.vf_req_fwd);
1053         if (rc) {
1054                 RTE_LOG(ERR, PMD,
1055                         "Failed to register driver");
1056                 rc = -EBUSY;
1057                 goto error_free;
1058         }
1059
1060         RTE_LOG(INFO, PMD,
1061                 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
1062                 eth_dev->pci_dev->mem_resource[0].phys_addr,
1063                 eth_dev->pci_dev->mem_resource[0].addr);
1064
1065         return 0;
1066
1067 error_free:
1068         eth_dev->driver->eth_dev_uninit(eth_dev);
1069 error:
1070         return rc;
1071 }
1072
1073 static int
1074 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
1075         struct bnxt *bp = eth_dev->data->dev_private;
1076         int rc;
1077
1078         if (eth_dev->data->mac_addrs)
1079                 rte_free(eth_dev->data->mac_addrs);
1080         if (bp->grp_info)
1081                 rte_free(bp->grp_info);
1082         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
1083         bnxt_free_hwrm_resources(bp);
1084         return rc;
1085 }
1086
1087 static struct eth_driver bnxt_rte_pmd = {
1088         .pci_drv = {
1089                     .id_table = bnxt_pci_id_map,
1090                     .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1091                     .probe = rte_eth_dev_pci_probe,
1092                     .remove = rte_eth_dev_pci_remove
1093                     },
1094         .eth_dev_init = bnxt_dev_init,
1095         .eth_dev_uninit = bnxt_dev_uninit,
1096         .dev_private_size = sizeof(struct bnxt),
1097 };
1098
1099 DRIVER_REGISTER_PCI(net_bnxt, bnxt_rte_pmd.pci_drv);
1100 DRIVER_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);