1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
18 #include "bnxt_filter.h"
19 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_stats.h"
27 #include "bnxt_vnic.h"
28 #include "hsi_struct_def_dpdk.h"
29 #include "bnxt_nvm_defs.h"
31 #define DRV_MODULE_NAME "bnxt"
32 static const char bnxt_version[] =
33 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
34 int bnxt_logtype_driver;
37 * The set of PCI devices this driver supports
39 static const struct rte_pci_id bnxt_pci_id_map[] = {
40 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
41 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
42 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
43 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
45 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
93 { .vendor_id = 0, /* sentinel */ },
96 #define BNXT_ETH_RSS_SUPPORT ( \
98 ETH_RSS_NONFRAG_IPV4_TCP | \
99 ETH_RSS_NONFRAG_IPV4_UDP | \
101 ETH_RSS_NONFRAG_IPV6_TCP | \
102 ETH_RSS_NONFRAG_IPV6_UDP)
104 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
105 DEV_TX_OFFLOAD_IPV4_CKSUM | \
106 DEV_TX_OFFLOAD_TCP_CKSUM | \
107 DEV_TX_OFFLOAD_UDP_CKSUM | \
108 DEV_TX_OFFLOAD_TCP_TSO | \
109 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
110 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
111 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
112 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
113 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
114 DEV_TX_OFFLOAD_QINQ_INSERT | \
115 DEV_TX_OFFLOAD_MULTI_SEGS)
117 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
118 DEV_RX_OFFLOAD_VLAN_STRIP | \
119 DEV_RX_OFFLOAD_IPV4_CKSUM | \
120 DEV_RX_OFFLOAD_UDP_CKSUM | \
121 DEV_RX_OFFLOAD_TCP_CKSUM | \
122 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
123 DEV_RX_OFFLOAD_JUMBO_FRAME | \
124 DEV_RX_OFFLOAD_KEEP_CRC | \
125 DEV_RX_OFFLOAD_VLAN_EXTEND | \
126 DEV_RX_OFFLOAD_TCP_LRO | \
127 DEV_RX_OFFLOAD_SCATTER | \
128 DEV_RX_OFFLOAD_RSS_HASH)
130 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
131 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
132 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
133 static const char *const bnxt_dev_args[] = {
135 BNXT_DEVARG_FLOW_XSTAT,
136 BNXT_DEVARG_MAX_NUM_KFLOWS,
141 * truflow == false to disable the feature
142 * truflow == true to enable the feature
144 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
147 * flow_xstat == false to disable the feature
148 * flow_xstat == true to enable the feature
150 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
153 * max_num_kflows must be >= 32
154 * and must be a power-of-2 supported value
155 * return: 1 -> invalid
158 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
160 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
165 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
166 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
167 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
168 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
169 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
170 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
171 static int bnxt_restore_vlan_filters(struct bnxt *bp);
172 static void bnxt_dev_recover(void *arg);
173 static void bnxt_free_error_recovery_info(struct bnxt *bp);
175 int is_bnxt_in_error(struct bnxt *bp)
177 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
179 if (bp->flags & BNXT_FLAG_FW_RESET)
185 /***********************/
188 * High level utility functions
191 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
193 if (!BNXT_CHIP_THOR(bp))
196 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
197 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
198 BNXT_RSS_ENTRIES_PER_CTX_THOR;
201 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
203 if (!BNXT_CHIP_THOR(bp))
204 return HW_HASH_INDEX_SIZE;
206 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
209 static void bnxt_free_pf_info(struct bnxt *bp)
214 static void bnxt_free_link_info(struct bnxt *bp)
216 rte_free(bp->link_info);
219 static void bnxt_free_leds_info(struct bnxt *bp)
225 static void bnxt_free_flow_stats_info(struct bnxt *bp)
227 rte_free(bp->flow_stat);
228 bp->flow_stat = NULL;
231 static void bnxt_free_cos_queues(struct bnxt *bp)
233 rte_free(bp->rx_cos_queue);
234 rte_free(bp->tx_cos_queue);
237 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
239 bnxt_free_filter_mem(bp);
240 bnxt_free_vnic_attributes(bp);
241 bnxt_free_vnic_mem(bp);
243 /* tx/rx rings are configured as part of *_queue_setup callbacks.
244 * If the number of rings change across fw update,
245 * we don't have much choice except to warn the user.
249 bnxt_free_tx_rings(bp);
250 bnxt_free_rx_rings(bp);
252 bnxt_free_async_cp_ring(bp);
253 bnxt_free_rxtx_nq_ring(bp);
255 rte_free(bp->grp_info);
259 static int bnxt_alloc_pf_info(struct bnxt *bp)
261 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
268 static int bnxt_alloc_link_info(struct bnxt *bp)
271 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
272 if (bp->link_info == NULL)
278 static int bnxt_alloc_leds_info(struct bnxt *bp)
280 bp->leds = rte_zmalloc("bnxt_leds",
281 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
283 if (bp->leds == NULL)
289 static int bnxt_alloc_cos_queues(struct bnxt *bp)
292 rte_zmalloc("bnxt_rx_cosq",
293 BNXT_COS_QUEUE_COUNT *
294 sizeof(struct bnxt_cos_queue_info),
296 if (bp->rx_cos_queue == NULL)
300 rte_zmalloc("bnxt_tx_cosq",
301 BNXT_COS_QUEUE_COUNT *
302 sizeof(struct bnxt_cos_queue_info),
304 if (bp->tx_cos_queue == NULL)
310 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
312 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
313 sizeof(struct bnxt_flow_stat_info), 0);
314 if (bp->flow_stat == NULL)
320 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
324 rc = bnxt_alloc_ring_grps(bp);
328 rc = bnxt_alloc_async_ring_struct(bp);
332 rc = bnxt_alloc_vnic_mem(bp);
336 rc = bnxt_alloc_vnic_attributes(bp);
340 rc = bnxt_alloc_filter_mem(bp);
344 rc = bnxt_alloc_async_cp_ring(bp);
348 rc = bnxt_alloc_rxtx_nq_ring(bp);
352 if (BNXT_FLOW_XSTATS_EN(bp)) {
353 rc = bnxt_alloc_flow_stats_info(bp);
361 bnxt_free_mem(bp, reconfig);
365 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
367 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
368 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
369 uint64_t rx_offloads = dev_conf->rxmode.offloads;
370 struct bnxt_rx_queue *rxq;
374 rc = bnxt_vnic_grp_alloc(bp, vnic);
378 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
379 vnic_id, vnic, vnic->fw_grp_ids);
381 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
385 /* Alloc RSS context only if RSS mode is enabled */
386 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
387 int j, nr_ctxs = bnxt_rss_ctxts(bp);
390 for (j = 0; j < nr_ctxs; j++) {
391 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
397 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
401 vnic->num_lb_ctxts = nr_ctxs;
405 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
406 * setting is not available at this time, it will not be
407 * configured correctly in the CFA.
409 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
410 vnic->vlan_strip = true;
412 vnic->vlan_strip = false;
414 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
418 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
422 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
423 rxq = bp->eth_dev->data->rx_queues[j];
426 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
427 j, rxq->vnic, rxq->vnic->fw_grp_ids);
429 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
430 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
432 vnic->rx_queue_cnt++;
435 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
437 rc = bnxt_vnic_rss_configure(bp, vnic);
441 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
443 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
444 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
446 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
450 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
455 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
459 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
460 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
465 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
466 " rx_fc_in_tbl.ctx_id = %d\n",
467 bp->flow_stat->rx_fc_in_tbl.va,
468 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
469 bp->flow_stat->rx_fc_in_tbl.ctx_id);
471 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
472 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
477 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
478 " rx_fc_out_tbl.ctx_id = %d\n",
479 bp->flow_stat->rx_fc_out_tbl.va,
480 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
481 bp->flow_stat->rx_fc_out_tbl.ctx_id);
483 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
484 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
489 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
490 " tx_fc_in_tbl.ctx_id = %d\n",
491 bp->flow_stat->tx_fc_in_tbl.va,
492 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
493 bp->flow_stat->tx_fc_in_tbl.ctx_id);
495 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
496 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
501 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
502 " tx_fc_out_tbl.ctx_id = %d\n",
503 bp->flow_stat->tx_fc_out_tbl.va,
504 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
505 bp->flow_stat->tx_fc_out_tbl.ctx_id);
507 memset(bp->flow_stat->rx_fc_out_tbl.va,
509 bp->flow_stat->rx_fc_out_tbl.size);
510 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
511 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
512 bp->flow_stat->rx_fc_out_tbl.ctx_id,
513 bp->flow_stat->max_fc,
518 memset(bp->flow_stat->tx_fc_out_tbl.va,
520 bp->flow_stat->tx_fc_out_tbl.size);
521 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
522 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
523 bp->flow_stat->tx_fc_out_tbl.ctx_id,
524 bp->flow_stat->max_fc,
530 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
531 struct bnxt_ctx_mem_buf_info *ctx)
536 ctx->va = rte_zmalloc(type, size, 0);
539 rte_mem_lock_page(ctx->va);
541 ctx->dma = rte_mem_virt2iova(ctx->va);
542 if (ctx->dma == RTE_BAD_IOVA)
548 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
550 struct rte_pci_device *pdev = bp->pdev;
551 char type[RTE_MEMZONE_NAMESIZE];
555 max_fc = bp->flow_stat->max_fc;
557 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
558 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
559 /* 4 bytes for each counter-id */
560 rc = bnxt_alloc_ctx_mem_buf(type,
562 &bp->flow_stat->rx_fc_in_tbl);
566 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
567 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
568 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
569 rc = bnxt_alloc_ctx_mem_buf(type,
571 &bp->flow_stat->rx_fc_out_tbl);
575 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
576 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
577 /* 4 bytes for each counter-id */
578 rc = bnxt_alloc_ctx_mem_buf(type,
580 &bp->flow_stat->tx_fc_in_tbl);
584 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
585 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
586 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
587 rc = bnxt_alloc_ctx_mem_buf(type,
589 &bp->flow_stat->tx_fc_out_tbl);
593 rc = bnxt_register_fc_ctx_mem(bp);
598 static int bnxt_init_ctx_mem(struct bnxt *bp)
602 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
603 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
604 !BNXT_FLOW_XSTATS_EN(bp))
607 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
611 rc = bnxt_init_fc_ctx_mem(bp);
616 static int bnxt_init_chip(struct bnxt *bp)
618 struct rte_eth_link new;
619 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
620 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
621 uint32_t intr_vector = 0;
622 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
623 uint32_t vec = BNXT_MISC_VEC_ID;
627 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
628 bp->eth_dev->data->dev_conf.rxmode.offloads |=
629 DEV_RX_OFFLOAD_JUMBO_FRAME;
630 bp->flags |= BNXT_FLAG_JUMBO;
632 bp->eth_dev->data->dev_conf.rxmode.offloads &=
633 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
634 bp->flags &= ~BNXT_FLAG_JUMBO;
637 /* THOR does not support ring groups.
638 * But we will use the array to save RSS context IDs.
640 if (BNXT_CHIP_THOR(bp))
641 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
643 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
645 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
649 rc = bnxt_alloc_hwrm_rings(bp);
651 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
655 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
657 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
661 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
664 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
665 if (bp->rx_cos_queue[i].id != 0xff) {
666 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
670 "Num pools more than FW profile\n");
674 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
680 rc = bnxt_mq_rx_configure(bp);
682 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
686 /* VNIC configuration */
687 for (i = 0; i < bp->nr_vnics; i++) {
688 rc = bnxt_setup_one_vnic(bp, i);
693 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
696 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
700 /* check and configure queue intr-vector mapping */
701 if ((rte_intr_cap_multiple(intr_handle) ||
702 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
703 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
704 intr_vector = bp->eth_dev->data->nb_rx_queues;
705 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
706 if (intr_vector > bp->rx_cp_nr_rings) {
707 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
711 rc = rte_intr_efd_enable(intr_handle, intr_vector);
716 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
717 intr_handle->intr_vec =
718 rte_zmalloc("intr_vec",
719 bp->eth_dev->data->nb_rx_queues *
721 if (intr_handle->intr_vec == NULL) {
722 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
723 " intr_vec", bp->eth_dev->data->nb_rx_queues);
727 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
728 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
729 intr_handle->intr_vec, intr_handle->nb_efd,
730 intr_handle->max_intr);
731 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
733 intr_handle->intr_vec[queue_id] =
734 vec + BNXT_RX_VEC_START;
735 if (vec < base + intr_handle->nb_efd - 1)
740 /* enable uio/vfio intr/eventfd mapping */
741 rc = rte_intr_enable(intr_handle);
742 #ifndef RTE_EXEC_ENV_FREEBSD
743 /* In FreeBSD OS, nic_uio driver does not support interrupts */
748 rc = bnxt_get_hwrm_link_config(bp, &new);
750 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
754 if (!bp->link_info->link_up) {
755 rc = bnxt_set_hwrm_link_config(bp, true);
758 "HWRM link config failure rc: %x\n", rc);
762 bnxt_print_link_info(bp->eth_dev);
764 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
766 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
771 rte_free(intr_handle->intr_vec);
773 rte_intr_efd_disable(intr_handle);
775 /* Some of the error status returned by FW may not be from errno.h */
782 static int bnxt_shutdown_nic(struct bnxt *bp)
784 bnxt_free_all_hwrm_resources(bp);
785 bnxt_free_all_filters(bp);
786 bnxt_free_all_vnics(bp);
791 * Device configuration and status function
794 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
796 uint32_t link_speed = bp->link_info->support_speeds;
797 uint32_t speed_capa = 0;
799 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
800 speed_capa |= ETH_LINK_SPEED_100M;
801 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
802 speed_capa |= ETH_LINK_SPEED_100M_HD;
803 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
804 speed_capa |= ETH_LINK_SPEED_1G;
805 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
806 speed_capa |= ETH_LINK_SPEED_2_5G;
807 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
808 speed_capa |= ETH_LINK_SPEED_10G;
809 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
810 speed_capa |= ETH_LINK_SPEED_20G;
811 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
812 speed_capa |= ETH_LINK_SPEED_25G;
813 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
814 speed_capa |= ETH_LINK_SPEED_40G;
815 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
816 speed_capa |= ETH_LINK_SPEED_50G;
817 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
818 speed_capa |= ETH_LINK_SPEED_100G;
819 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
820 speed_capa |= ETH_LINK_SPEED_200G;
822 if (bp->link_info->auto_mode ==
823 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
824 speed_capa |= ETH_LINK_SPEED_FIXED;
826 speed_capa |= ETH_LINK_SPEED_AUTONEG;
831 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
832 struct rte_eth_dev_info *dev_info)
834 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
835 struct bnxt *bp = eth_dev->data->dev_private;
836 uint16_t max_vnics, i, j, vpool, vrxq;
837 unsigned int max_rx_rings;
840 rc = is_bnxt_in_error(bp);
845 dev_info->max_mac_addrs = bp->max_l2_ctx;
846 dev_info->max_hash_mac_addrs = 0;
848 /* PF/VF specifics */
850 dev_info->max_vfs = pdev->max_vfs;
852 max_rx_rings = BNXT_MAX_RINGS(bp);
853 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
854 dev_info->max_rx_queues = max_rx_rings;
855 dev_info->max_tx_queues = max_rx_rings;
856 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
857 dev_info->hash_key_size = 40;
858 max_vnics = bp->max_vnics;
861 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
862 dev_info->max_mtu = BNXT_MAX_MTU;
864 /* Fast path specifics */
865 dev_info->min_rx_bufsize = 1;
866 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
868 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
869 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
870 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
871 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
872 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
874 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
877 dev_info->default_rxconf = (struct rte_eth_rxconf) {
883 .rx_free_thresh = 32,
884 /* If no descriptors available, pkts are dropped by default */
888 dev_info->default_txconf = (struct rte_eth_txconf) {
894 .tx_free_thresh = 32,
897 eth_dev->data->dev_conf.intr_conf.lsc = 1;
899 eth_dev->data->dev_conf.intr_conf.rxq = 1;
900 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
901 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
902 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
903 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
908 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
909 * need further investigation.
913 vpool = 64; /* ETH_64_POOLS */
914 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
915 for (i = 0; i < 4; vpool >>= 1, i++) {
916 if (max_vnics > vpool) {
917 for (j = 0; j < 5; vrxq >>= 1, j++) {
918 if (dev_info->max_rx_queues > vrxq) {
924 /* Not enough resources to support VMDq */
928 /* Not enough resources to support VMDq */
932 dev_info->max_vmdq_pools = vpool;
933 dev_info->vmdq_queue_num = vrxq;
935 dev_info->vmdq_pool_base = 0;
936 dev_info->vmdq_queue_base = 0;
941 /* Configure the device based on the configuration provided */
942 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
944 struct bnxt *bp = eth_dev->data->dev_private;
945 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
948 bp->rx_queues = (void *)eth_dev->data->rx_queues;
949 bp->tx_queues = (void *)eth_dev->data->tx_queues;
950 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
951 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
953 rc = is_bnxt_in_error(bp);
957 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
958 rc = bnxt_hwrm_check_vf_rings(bp);
960 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
964 /* If a resource has already been allocated - in this case
965 * it is the async completion ring, free it. Reallocate it after
966 * resource reservation. This will ensure the resource counts
967 * are calculated correctly.
970 pthread_mutex_lock(&bp->def_cp_lock);
972 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
973 bnxt_disable_int(bp);
974 bnxt_free_cp_ring(bp, bp->async_cp_ring);
977 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
979 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
980 pthread_mutex_unlock(&bp->def_cp_lock);
984 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
985 rc = bnxt_alloc_async_cp_ring(bp);
987 pthread_mutex_unlock(&bp->def_cp_lock);
993 pthread_mutex_unlock(&bp->def_cp_lock);
995 /* legacy driver needs to get updated values */
996 rc = bnxt_hwrm_func_qcaps(bp);
998 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
1003 /* Inherit new configurations */
1004 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1005 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1006 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1007 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1008 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1010 goto resource_error;
1012 if (BNXT_HAS_RING_GRPS(bp) &&
1013 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1014 goto resource_error;
1016 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1017 bp->max_vnics < eth_dev->data->nb_rx_queues)
1018 goto resource_error;
1020 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1021 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1023 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1024 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1025 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1027 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1028 eth_dev->data->mtu =
1029 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1030 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1032 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1038 "Insufficient resources to support requested config\n");
1040 "Num Queues Requested: Tx %d, Rx %d\n",
1041 eth_dev->data->nb_tx_queues,
1042 eth_dev->data->nb_rx_queues);
1044 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1045 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1046 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1050 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1052 struct rte_eth_link *link = ð_dev->data->dev_link;
1054 if (link->link_status)
1055 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1056 eth_dev->data->port_id,
1057 (uint32_t)link->link_speed,
1058 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1059 ("full-duplex") : ("half-duplex\n"));
1061 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1062 eth_dev->data->port_id);
1066 * Determine whether the current configuration requires support for scattered
1067 * receive; return 1 if scattered receive is required and 0 if not.
1069 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1074 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1077 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1078 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1080 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1081 RTE_PKTMBUF_HEADROOM);
1082 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1088 static eth_rx_burst_t
1089 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1091 struct bnxt *bp = eth_dev->data->dev_private;
1094 #ifndef RTE_LIBRTE_IEEE1588
1096 * Vector mode receive can be enabled only if scatter rx is not
1097 * in use and rx offloads are limited to VLAN stripping and
1100 if (!eth_dev->data->scattered_rx &&
1101 !(eth_dev->data->dev_conf.rxmode.offloads &
1102 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1103 DEV_RX_OFFLOAD_KEEP_CRC |
1104 DEV_RX_OFFLOAD_JUMBO_FRAME |
1105 DEV_RX_OFFLOAD_IPV4_CKSUM |
1106 DEV_RX_OFFLOAD_UDP_CKSUM |
1107 DEV_RX_OFFLOAD_TCP_CKSUM |
1108 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1109 DEV_RX_OFFLOAD_RSS_HASH |
1110 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1111 !BNXT_TRUFLOW_EN(bp)) {
1112 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1113 eth_dev->data->port_id);
1114 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1115 return bnxt_recv_pkts_vec;
1117 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1118 eth_dev->data->port_id);
1120 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1121 eth_dev->data->port_id,
1122 eth_dev->data->scattered_rx,
1123 eth_dev->data->dev_conf.rxmode.offloads);
1126 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1127 return bnxt_recv_pkts;
1130 static eth_tx_burst_t
1131 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1134 #ifndef RTE_LIBRTE_IEEE1588
1136 * Vector mode transmit can be enabled only if not using scatter rx
1139 if (!eth_dev->data->scattered_rx &&
1140 !eth_dev->data->dev_conf.txmode.offloads) {
1141 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1142 eth_dev->data->port_id);
1143 return bnxt_xmit_pkts_vec;
1145 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1146 eth_dev->data->port_id);
1148 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1149 eth_dev->data->port_id,
1150 eth_dev->data->scattered_rx,
1151 eth_dev->data->dev_conf.txmode.offloads);
1154 return bnxt_xmit_pkts;
1157 static int bnxt_handle_if_change_status(struct bnxt *bp)
1161 /* Since fw has undergone a reset and lost all contexts,
1162 * set fatal flag to not issue hwrm during cleanup
1164 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1165 bnxt_uninit_resources(bp, true);
1167 /* clear fatal flag so that re-init happens */
1168 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1169 rc = bnxt_init_resources(bp, true);
1171 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1176 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1178 struct bnxt *bp = eth_dev->data->dev_private;
1179 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1181 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1183 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1184 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1188 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1190 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1191 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1195 rc = bnxt_hwrm_if_change(bp, true);
1196 if (rc == 0 || rc != -EAGAIN)
1199 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1200 } while (retry_cnt--);
1205 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1206 rc = bnxt_handle_if_change_status(bp);
1211 bnxt_enable_int(bp);
1213 rc = bnxt_init_chip(bp);
1217 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1218 eth_dev->data->dev_started = 1;
1220 bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1222 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1223 vlan_mask |= ETH_VLAN_FILTER_MASK;
1224 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1225 vlan_mask |= ETH_VLAN_STRIP_MASK;
1226 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1230 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1231 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1233 pthread_mutex_lock(&bp->def_cp_lock);
1234 bnxt_schedule_fw_health_check(bp);
1235 pthread_mutex_unlock(&bp->def_cp_lock);
1237 if (BNXT_TRUFLOW_EN(bp))
1243 bnxt_shutdown_nic(bp);
1244 bnxt_free_tx_mbufs(bp);
1245 bnxt_free_rx_mbufs(bp);
1246 bnxt_hwrm_if_change(bp, false);
1247 eth_dev->data->dev_started = 0;
1251 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1253 struct bnxt *bp = eth_dev->data->dev_private;
1256 if (!bp->link_info->link_up)
1257 rc = bnxt_set_hwrm_link_config(bp, true);
1259 eth_dev->data->dev_link.link_status = 1;
1261 bnxt_print_link_info(eth_dev);
1265 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1267 struct bnxt *bp = eth_dev->data->dev_private;
1269 eth_dev->data->dev_link.link_status = 0;
1270 bnxt_set_hwrm_link_config(bp, false);
1271 bp->link_info->link_up = 0;
1276 /* Unload the driver, release resources */
1277 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1279 struct bnxt *bp = eth_dev->data->dev_private;
1280 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1281 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1283 if (BNXT_TRUFLOW_EN(bp))
1284 bnxt_ulp_deinit(bp);
1286 eth_dev->data->dev_started = 0;
1287 /* Prevent crashes when queues are still in use */
1288 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1289 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1291 bnxt_disable_int(bp);
1293 /* disable uio/vfio intr/eventfd mapping */
1294 rte_intr_disable(intr_handle);
1296 bnxt_cancel_fw_health_check(bp);
1298 bnxt_dev_set_link_down_op(eth_dev);
1300 /* Wait for link to be reset and the async notification to process.
1301 * During reset recovery, there is no need to wait and
1302 * VF/NPAR functions do not have privilege to change PHY config.
1304 if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1305 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1307 /* Clean queue intr-vector mapping */
1308 rte_intr_efd_disable(intr_handle);
1309 if (intr_handle->intr_vec != NULL) {
1310 rte_free(intr_handle->intr_vec);
1311 intr_handle->intr_vec = NULL;
1314 bnxt_hwrm_port_clr_stats(bp);
1315 bnxt_free_tx_mbufs(bp);
1316 bnxt_free_rx_mbufs(bp);
1317 /* Process any remaining notifications in default completion queue */
1318 bnxt_int_handler(eth_dev);
1319 bnxt_shutdown_nic(bp);
1320 bnxt_hwrm_if_change(bp, false);
1322 rte_free(bp->mark_table);
1323 bp->mark_table = NULL;
1325 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1326 bp->rx_cosq_cnt = 0;
1327 /* All filters are deleted on a port stop. */
1328 if (BNXT_FLOW_XSTATS_EN(bp))
1329 bp->flow_stat->flow_count = 0;
1332 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1334 struct bnxt *bp = eth_dev->data->dev_private;
1336 /* cancel the recovery handler before remove dev */
1337 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1338 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1339 bnxt_cancel_fc_thread(bp);
1341 if (eth_dev->data->dev_started)
1342 bnxt_dev_stop_op(eth_dev);
1344 bnxt_uninit_resources(bp, false);
1346 bnxt_free_leds_info(bp);
1347 bnxt_free_cos_queues(bp);
1348 bnxt_free_link_info(bp);
1349 bnxt_free_pf_info(bp);
1351 eth_dev->dev_ops = NULL;
1352 eth_dev->rx_pkt_burst = NULL;
1353 eth_dev->tx_pkt_burst = NULL;
1355 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1356 bp->tx_mem_zone = NULL;
1357 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1358 bp->rx_mem_zone = NULL;
1360 rte_free(bp->pf->vf_info);
1361 bp->pf->vf_info = NULL;
1363 rte_free(bp->grp_info);
1364 bp->grp_info = NULL;
1367 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1370 struct bnxt *bp = eth_dev->data->dev_private;
1371 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1372 struct bnxt_vnic_info *vnic;
1373 struct bnxt_filter_info *filter, *temp_filter;
1376 if (is_bnxt_in_error(bp))
1380 * Loop through all VNICs from the specified filter flow pools to
1381 * remove the corresponding MAC addr filter
1383 for (i = 0; i < bp->nr_vnics; i++) {
1384 if (!(pool_mask & (1ULL << i)))
1387 vnic = &bp->vnic_info[i];
1388 filter = STAILQ_FIRST(&vnic->filter);
1390 temp_filter = STAILQ_NEXT(filter, next);
1391 if (filter->mac_index == index) {
1392 STAILQ_REMOVE(&vnic->filter, filter,
1393 bnxt_filter_info, next);
1394 bnxt_hwrm_clear_l2_filter(bp, filter);
1395 bnxt_free_filter(bp, filter);
1397 filter = temp_filter;
1402 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1403 struct rte_ether_addr *mac_addr, uint32_t index,
1406 struct bnxt_filter_info *filter;
1409 /* Attach requested MAC address to the new l2_filter */
1410 STAILQ_FOREACH(filter, &vnic->filter, next) {
1411 if (filter->mac_index == index) {
1413 "MAC addr already existed for pool %d\n",
1419 filter = bnxt_alloc_filter(bp);
1421 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1425 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1426 * if the MAC that's been programmed now is a different one, then,
1427 * copy that addr to filter->l2_addr
1430 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1431 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1433 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1435 filter->mac_index = index;
1436 if (filter->mac_index == 0)
1437 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1439 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1441 bnxt_free_filter(bp, filter);
1447 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1448 struct rte_ether_addr *mac_addr,
1449 uint32_t index, uint32_t pool)
1451 struct bnxt *bp = eth_dev->data->dev_private;
1452 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1455 rc = is_bnxt_in_error(bp);
1459 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1460 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1465 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1469 /* Filter settings will get applied when port is started */
1470 if (!eth_dev->data->dev_started)
1473 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1478 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1479 bool exp_link_status)
1482 struct bnxt *bp = eth_dev->data->dev_private;
1483 struct rte_eth_link new;
1484 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1485 BNXT_LINK_DOWN_WAIT_CNT;
1487 rc = is_bnxt_in_error(bp);
1491 memset(&new, 0, sizeof(new));
1493 /* Retrieve link info from hardware */
1494 rc = bnxt_get_hwrm_link_config(bp, &new);
1496 new.link_speed = ETH_LINK_SPEED_100M;
1497 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1499 "Failed to retrieve link rc = 0x%x!\n", rc);
1503 if (!wait_to_complete || new.link_status == exp_link_status)
1506 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1510 /* Timed out or success */
1511 if (new.link_status != eth_dev->data->dev_link.link_status ||
1512 new.link_speed != eth_dev->data->dev_link.link_speed) {
1513 rte_eth_linkstatus_set(eth_dev, &new);
1515 _rte_eth_dev_callback_process(eth_dev,
1516 RTE_ETH_EVENT_INTR_LSC,
1519 bnxt_print_link_info(eth_dev);
1525 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1526 int wait_to_complete)
1528 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1531 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1533 struct bnxt *bp = eth_dev->data->dev_private;
1534 struct bnxt_vnic_info *vnic;
1538 rc = is_bnxt_in_error(bp);
1542 /* Filter settings will get applied when port is started */
1543 if (!eth_dev->data->dev_started)
1546 if (bp->vnic_info == NULL)
1549 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1551 old_flags = vnic->flags;
1552 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1553 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1555 vnic->flags = old_flags;
1560 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1562 struct bnxt *bp = eth_dev->data->dev_private;
1563 struct bnxt_vnic_info *vnic;
1567 rc = is_bnxt_in_error(bp);
1571 /* Filter settings will get applied when port is started */
1572 if (!eth_dev->data->dev_started)
1575 if (bp->vnic_info == NULL)
1578 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1580 old_flags = vnic->flags;
1581 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1582 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1584 vnic->flags = old_flags;
1589 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1591 struct bnxt *bp = eth_dev->data->dev_private;
1592 struct bnxt_vnic_info *vnic;
1596 rc = is_bnxt_in_error(bp);
1600 /* Filter settings will get applied when port is started */
1601 if (!eth_dev->data->dev_started)
1604 if (bp->vnic_info == NULL)
1607 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1609 old_flags = vnic->flags;
1610 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1611 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1613 vnic->flags = old_flags;
1618 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1620 struct bnxt *bp = eth_dev->data->dev_private;
1621 struct bnxt_vnic_info *vnic;
1625 rc = is_bnxt_in_error(bp);
1629 /* Filter settings will get applied when port is started */
1630 if (!eth_dev->data->dev_started)
1633 if (bp->vnic_info == NULL)
1636 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1638 old_flags = vnic->flags;
1639 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1640 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1642 vnic->flags = old_flags;
1647 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1648 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1650 if (qid >= bp->rx_nr_rings)
1653 return bp->eth_dev->data->rx_queues[qid];
1656 /* Return rxq corresponding to a given rss table ring/group ID. */
1657 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1659 struct bnxt_rx_queue *rxq;
1662 if (!BNXT_HAS_RING_GRPS(bp)) {
1663 for (i = 0; i < bp->rx_nr_rings; i++) {
1664 rxq = bp->eth_dev->data->rx_queues[i];
1665 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1669 for (i = 0; i < bp->rx_nr_rings; i++) {
1670 if (bp->grp_info[i].fw_grp_id == fwr)
1675 return INVALID_HW_RING_ID;
1678 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1679 struct rte_eth_rss_reta_entry64 *reta_conf,
1682 struct bnxt *bp = eth_dev->data->dev_private;
1683 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1684 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1685 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1689 rc = is_bnxt_in_error(bp);
1693 if (!vnic->rss_table)
1696 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1699 if (reta_size != tbl_size) {
1700 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1701 "(%d) must equal the size supported by the hardware "
1702 "(%d)\n", reta_size, tbl_size);
1706 for (i = 0; i < reta_size; i++) {
1707 struct bnxt_rx_queue *rxq;
1709 idx = i / RTE_RETA_GROUP_SIZE;
1710 sft = i % RTE_RETA_GROUP_SIZE;
1712 if (!(reta_conf[idx].mask & (1ULL << sft)))
1715 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1717 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1721 if (BNXT_CHIP_THOR(bp)) {
1722 vnic->rss_table[i * 2] =
1723 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1724 vnic->rss_table[i * 2 + 1] =
1725 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1727 vnic->rss_table[i] =
1728 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1732 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1736 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1737 struct rte_eth_rss_reta_entry64 *reta_conf,
1740 struct bnxt *bp = eth_dev->data->dev_private;
1741 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1742 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1743 uint16_t idx, sft, i;
1746 rc = is_bnxt_in_error(bp);
1750 /* Retrieve from the default VNIC */
1753 if (!vnic->rss_table)
1756 if (reta_size != tbl_size) {
1757 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1758 "(%d) must equal the size supported by the hardware "
1759 "(%d)\n", reta_size, tbl_size);
1763 for (idx = 0, i = 0; i < reta_size; i++) {
1764 idx = i / RTE_RETA_GROUP_SIZE;
1765 sft = i % RTE_RETA_GROUP_SIZE;
1767 if (reta_conf[idx].mask & (1ULL << sft)) {
1770 if (BNXT_CHIP_THOR(bp))
1771 qid = bnxt_rss_to_qid(bp,
1772 vnic->rss_table[i * 2]);
1774 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1776 if (qid == INVALID_HW_RING_ID) {
1777 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1780 reta_conf[idx].reta[sft] = qid;
1787 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1788 struct rte_eth_rss_conf *rss_conf)
1790 struct bnxt *bp = eth_dev->data->dev_private;
1791 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1792 struct bnxt_vnic_info *vnic;
1795 rc = is_bnxt_in_error(bp);
1800 * If RSS enablement were different than dev_configure,
1801 * then return -EINVAL
1803 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1804 if (!rss_conf->rss_hf)
1805 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1807 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1811 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1812 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
1816 /* Update the default RSS VNIC(s) */
1817 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1818 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1821 * If hashkey is not specified, use the previously configured
1824 if (!rss_conf->rss_key)
1827 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1829 "Invalid hashkey length, should be 16 bytes\n");
1832 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1835 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1839 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1840 struct rte_eth_rss_conf *rss_conf)
1842 struct bnxt *bp = eth_dev->data->dev_private;
1843 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1845 uint32_t hash_types;
1847 rc = is_bnxt_in_error(bp);
1851 /* RSS configuration is the same for all VNICs */
1852 if (vnic && vnic->rss_hash_key) {
1853 if (rss_conf->rss_key) {
1854 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1855 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1856 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1859 hash_types = vnic->hash_type;
1860 rss_conf->rss_hf = 0;
1861 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1862 rss_conf->rss_hf |= ETH_RSS_IPV4;
1863 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1865 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1866 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1868 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1870 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1871 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1873 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1875 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1876 rss_conf->rss_hf |= ETH_RSS_IPV6;
1877 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1879 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1880 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1882 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1884 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1885 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1887 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1891 "Unknown RSS config from firmware (%08x), RSS disabled",
1896 rss_conf->rss_hf = 0;
1901 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1902 struct rte_eth_fc_conf *fc_conf)
1904 struct bnxt *bp = dev->data->dev_private;
1905 struct rte_eth_link link_info;
1908 rc = is_bnxt_in_error(bp);
1912 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1916 memset(fc_conf, 0, sizeof(*fc_conf));
1917 if (bp->link_info->auto_pause)
1918 fc_conf->autoneg = 1;
1919 switch (bp->link_info->pause) {
1921 fc_conf->mode = RTE_FC_NONE;
1923 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1924 fc_conf->mode = RTE_FC_TX_PAUSE;
1926 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1927 fc_conf->mode = RTE_FC_RX_PAUSE;
1929 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1930 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1931 fc_conf->mode = RTE_FC_FULL;
1937 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1938 struct rte_eth_fc_conf *fc_conf)
1940 struct bnxt *bp = dev->data->dev_private;
1943 rc = is_bnxt_in_error(bp);
1947 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1948 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1952 switch (fc_conf->mode) {
1954 bp->link_info->auto_pause = 0;
1955 bp->link_info->force_pause = 0;
1957 case RTE_FC_RX_PAUSE:
1958 if (fc_conf->autoneg) {
1959 bp->link_info->auto_pause =
1960 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1961 bp->link_info->force_pause = 0;
1963 bp->link_info->auto_pause = 0;
1964 bp->link_info->force_pause =
1965 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1968 case RTE_FC_TX_PAUSE:
1969 if (fc_conf->autoneg) {
1970 bp->link_info->auto_pause =
1971 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1972 bp->link_info->force_pause = 0;
1974 bp->link_info->auto_pause = 0;
1975 bp->link_info->force_pause =
1976 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1980 if (fc_conf->autoneg) {
1981 bp->link_info->auto_pause =
1982 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1983 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1984 bp->link_info->force_pause = 0;
1986 bp->link_info->auto_pause = 0;
1987 bp->link_info->force_pause =
1988 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1989 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1993 return bnxt_set_hwrm_link_config(bp, true);
1996 /* Add UDP tunneling port */
1998 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1999 struct rte_eth_udp_tunnel *udp_tunnel)
2001 struct bnxt *bp = eth_dev->data->dev_private;
2002 uint16_t tunnel_type = 0;
2005 rc = is_bnxt_in_error(bp);
2009 switch (udp_tunnel->prot_type) {
2010 case RTE_TUNNEL_TYPE_VXLAN:
2011 if (bp->vxlan_port_cnt) {
2012 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2013 udp_tunnel->udp_port);
2014 if (bp->vxlan_port != udp_tunnel->udp_port) {
2015 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2018 bp->vxlan_port_cnt++;
2022 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2023 bp->vxlan_port_cnt++;
2025 case RTE_TUNNEL_TYPE_GENEVE:
2026 if (bp->geneve_port_cnt) {
2027 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2028 udp_tunnel->udp_port);
2029 if (bp->geneve_port != udp_tunnel->udp_port) {
2030 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2033 bp->geneve_port_cnt++;
2037 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2038 bp->geneve_port_cnt++;
2041 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2044 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2050 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2051 struct rte_eth_udp_tunnel *udp_tunnel)
2053 struct bnxt *bp = eth_dev->data->dev_private;
2054 uint16_t tunnel_type = 0;
2058 rc = is_bnxt_in_error(bp);
2062 switch (udp_tunnel->prot_type) {
2063 case RTE_TUNNEL_TYPE_VXLAN:
2064 if (!bp->vxlan_port_cnt) {
2065 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2068 if (bp->vxlan_port != udp_tunnel->udp_port) {
2069 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2070 udp_tunnel->udp_port, bp->vxlan_port);
2073 if (--bp->vxlan_port_cnt)
2077 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2078 port = bp->vxlan_fw_dst_port_id;
2080 case RTE_TUNNEL_TYPE_GENEVE:
2081 if (!bp->geneve_port_cnt) {
2082 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2085 if (bp->geneve_port != udp_tunnel->udp_port) {
2086 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2087 udp_tunnel->udp_port, bp->geneve_port);
2090 if (--bp->geneve_port_cnt)
2094 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2095 port = bp->geneve_fw_dst_port_id;
2098 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2102 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2105 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2108 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2109 bp->geneve_port = 0;
2114 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2116 struct bnxt_filter_info *filter;
2117 struct bnxt_vnic_info *vnic;
2119 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2121 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2122 filter = STAILQ_FIRST(&vnic->filter);
2124 /* Search for this matching MAC+VLAN filter */
2125 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2126 /* Delete the filter */
2127 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2130 STAILQ_REMOVE(&vnic->filter, filter,
2131 bnxt_filter_info, next);
2132 bnxt_free_filter(bp, filter);
2134 "Deleted vlan filter for %d\n",
2138 filter = STAILQ_NEXT(filter, next);
2143 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2145 struct bnxt_filter_info *filter;
2146 struct bnxt_vnic_info *vnic;
2148 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2149 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2150 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2152 /* Implementation notes on the use of VNIC in this command:
2154 * By default, these filters belong to default vnic for the function.
2155 * Once these filters are set up, only destination VNIC can be modified.
2156 * If the destination VNIC is not specified in this command,
2157 * then the HWRM shall only create an l2 context id.
2160 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2161 filter = STAILQ_FIRST(&vnic->filter);
2162 /* Check if the VLAN has already been added */
2164 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2167 filter = STAILQ_NEXT(filter, next);
2170 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2171 * command to create MAC+VLAN filter with the right flags, enables set.
2173 filter = bnxt_alloc_filter(bp);
2176 "MAC/VLAN filter alloc failed\n");
2179 /* MAC + VLAN ID filter */
2180 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2181 * untagged packets are received
2183 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2184 * packets and only the programmed vlan's packets are received
2186 filter->l2_ivlan = vlan_id;
2187 filter->l2_ivlan_mask = 0x0FFF;
2188 filter->enables |= en;
2189 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2191 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2193 /* Free the newly allocated filter as we were
2194 * not able to create the filter in hardware.
2196 bnxt_free_filter(bp, filter);
2200 filter->mac_index = 0;
2201 /* Add this new filter to the list */
2203 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2205 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2208 "Added Vlan filter for %d\n", vlan_id);
2212 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2213 uint16_t vlan_id, int on)
2215 struct bnxt *bp = eth_dev->data->dev_private;
2218 rc = is_bnxt_in_error(bp);
2222 if (!eth_dev->data->dev_started) {
2223 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2227 /* These operations apply to ALL existing MAC/VLAN filters */
2229 return bnxt_add_vlan_filter(bp, vlan_id);
2231 return bnxt_del_vlan_filter(bp, vlan_id);
2234 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2235 struct bnxt_vnic_info *vnic)
2237 struct bnxt_filter_info *filter;
2240 filter = STAILQ_FIRST(&vnic->filter);
2242 if (filter->mac_index == 0 &&
2243 !memcmp(filter->l2_addr, bp->mac_addr,
2244 RTE_ETHER_ADDR_LEN)) {
2245 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2247 STAILQ_REMOVE(&vnic->filter, filter,
2248 bnxt_filter_info, next);
2249 bnxt_free_filter(bp, filter);
2253 filter = STAILQ_NEXT(filter, next);
2259 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2261 struct bnxt_vnic_info *vnic;
2265 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2266 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2267 /* Remove any VLAN filters programmed */
2268 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2269 bnxt_del_vlan_filter(bp, i);
2271 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2275 /* Default filter will allow packets that match the
2276 * dest mac. So, it has to be deleted, otherwise, we
2277 * will endup receiving vlan packets for which the
2278 * filter is not programmed, when hw-vlan-filter
2279 * configuration is ON
2281 bnxt_del_dflt_mac_filter(bp, vnic);
2282 /* This filter will allow only untagged packets */
2283 bnxt_add_vlan_filter(bp, 0);
2285 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2286 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2291 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2293 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2297 /* Destroy vnic filters and vnic */
2298 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2299 DEV_RX_OFFLOAD_VLAN_FILTER) {
2300 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2301 bnxt_del_vlan_filter(bp, i);
2303 bnxt_del_dflt_mac_filter(bp, vnic);
2305 rc = bnxt_hwrm_vnic_free(bp, vnic);
2309 rte_free(vnic->fw_grp_ids);
2310 vnic->fw_grp_ids = NULL;
2312 vnic->rx_queue_cnt = 0;
2318 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2320 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2323 /* Destroy, recreate and reconfigure the default vnic */
2324 rc = bnxt_free_one_vnic(bp, 0);
2328 /* default vnic 0 */
2329 rc = bnxt_setup_one_vnic(bp, 0);
2333 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2334 DEV_RX_OFFLOAD_VLAN_FILTER) {
2335 rc = bnxt_add_vlan_filter(bp, 0);
2338 rc = bnxt_restore_vlan_filters(bp);
2342 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2347 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2351 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2352 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2358 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2360 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2361 struct bnxt *bp = dev->data->dev_private;
2364 rc = is_bnxt_in_error(bp);
2368 /* Filter settings will get applied when port is started */
2369 if (!dev->data->dev_started)
2372 if (mask & ETH_VLAN_FILTER_MASK) {
2373 /* Enable or disable VLAN filtering */
2374 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2379 if (mask & ETH_VLAN_STRIP_MASK) {
2380 /* Enable or disable VLAN stripping */
2381 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2386 if (mask & ETH_VLAN_EXTEND_MASK) {
2387 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2388 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2390 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2397 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2400 struct bnxt *bp = dev->data->dev_private;
2401 int qinq = dev->data->dev_conf.rxmode.offloads &
2402 DEV_RX_OFFLOAD_VLAN_EXTEND;
2404 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2405 vlan_type != ETH_VLAN_TYPE_OUTER) {
2407 "Unsupported vlan type.");
2412 "QinQ not enabled. Needs to be ON as we can "
2413 "accelerate only outer vlan\n");
2417 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2419 case RTE_ETHER_TYPE_QINQ:
2421 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2423 case RTE_ETHER_TYPE_VLAN:
2425 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2429 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2433 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2437 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2440 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2443 bp->outer_tpid_bd |= tpid;
2444 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2445 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2447 "Can accelerate only outer vlan in QinQ\n");
2455 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2456 struct rte_ether_addr *addr)
2458 struct bnxt *bp = dev->data->dev_private;
2459 /* Default Filter is tied to VNIC 0 */
2460 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2463 rc = is_bnxt_in_error(bp);
2467 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2470 if (rte_is_zero_ether_addr(addr))
2473 /* Filter settings will get applied when port is started */
2474 if (!dev->data->dev_started)
2477 /* Check if the requested MAC is already added */
2478 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2481 /* Destroy filter and re-create it */
2482 bnxt_del_dflt_mac_filter(bp, vnic);
2484 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2485 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2486 /* This filter will allow only untagged packets */
2487 rc = bnxt_add_vlan_filter(bp, 0);
2489 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2492 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2497 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2498 struct rte_ether_addr *mc_addr_set,
2499 uint32_t nb_mc_addr)
2501 struct bnxt *bp = eth_dev->data->dev_private;
2502 char *mc_addr_list = (char *)mc_addr_set;
2503 struct bnxt_vnic_info *vnic;
2504 uint32_t off = 0, i = 0;
2507 rc = is_bnxt_in_error(bp);
2511 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2513 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2514 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2518 /* TODO Check for Duplicate mcast addresses */
2519 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2520 for (i = 0; i < nb_mc_addr; i++) {
2521 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2522 RTE_ETHER_ADDR_LEN);
2523 off += RTE_ETHER_ADDR_LEN;
2526 vnic->mc_addr_cnt = i;
2527 if (vnic->mc_addr_cnt)
2528 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2530 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2533 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2537 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2539 struct bnxt *bp = dev->data->dev_private;
2540 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2541 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2542 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2543 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2546 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2547 fw_major, fw_minor, fw_updt, fw_rsvd);
2549 ret += 1; /* add the size of '\0' */
2550 if (fw_size < (uint32_t)ret)
2557 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2558 struct rte_eth_rxq_info *qinfo)
2560 struct bnxt *bp = dev->data->dev_private;
2561 struct bnxt_rx_queue *rxq;
2563 if (is_bnxt_in_error(bp))
2566 rxq = dev->data->rx_queues[queue_id];
2568 qinfo->mp = rxq->mb_pool;
2569 qinfo->scattered_rx = dev->data->scattered_rx;
2570 qinfo->nb_desc = rxq->nb_rx_desc;
2572 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2573 qinfo->conf.rx_drop_en = 0;
2574 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2578 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2579 struct rte_eth_txq_info *qinfo)
2581 struct bnxt *bp = dev->data->dev_private;
2582 struct bnxt_tx_queue *txq;
2584 if (is_bnxt_in_error(bp))
2587 txq = dev->data->tx_queues[queue_id];
2589 qinfo->nb_desc = txq->nb_tx_desc;
2591 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2592 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2593 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2595 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2596 qinfo->conf.tx_rs_thresh = 0;
2597 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2600 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2602 struct bnxt *bp = eth_dev->data->dev_private;
2603 uint32_t new_pkt_size;
2607 rc = is_bnxt_in_error(bp);
2611 /* Exit if receive queues are not configured yet */
2612 if (!eth_dev->data->nb_rx_queues)
2615 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2616 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2620 * If vector-mode tx/rx is active, disallow any MTU change that would
2621 * require scattered receive support.
2623 if (eth_dev->data->dev_started &&
2624 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2625 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2627 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2629 "MTU change would require scattered rx support. ");
2630 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2635 if (new_mtu > RTE_ETHER_MTU) {
2636 bp->flags |= BNXT_FLAG_JUMBO;
2637 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2638 DEV_RX_OFFLOAD_JUMBO_FRAME;
2640 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2641 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2642 bp->flags &= ~BNXT_FLAG_JUMBO;
2645 /* Is there a change in mtu setting? */
2646 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2649 for (i = 0; i < bp->nr_vnics; i++) {
2650 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2653 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2654 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2658 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2659 size -= RTE_PKTMBUF_HEADROOM;
2661 if (size < new_mtu) {
2662 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2669 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2671 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2677 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2679 struct bnxt *bp = dev->data->dev_private;
2680 uint16_t vlan = bp->vlan;
2683 rc = is_bnxt_in_error(bp);
2687 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2689 "PVID cannot be modified for this function\n");
2692 bp->vlan = on ? pvid : 0;
2694 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2701 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2703 struct bnxt *bp = dev->data->dev_private;
2706 rc = is_bnxt_in_error(bp);
2710 return bnxt_hwrm_port_led_cfg(bp, true);
2714 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2716 struct bnxt *bp = dev->data->dev_private;
2719 rc = is_bnxt_in_error(bp);
2723 return bnxt_hwrm_port_led_cfg(bp, false);
2727 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2729 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2730 uint32_t desc = 0, raw_cons = 0, cons;
2731 struct bnxt_cp_ring_info *cpr;
2732 struct bnxt_rx_queue *rxq;
2733 struct rx_pkt_cmpl *rxcmp;
2736 rc = is_bnxt_in_error(bp);
2740 rxq = dev->data->rx_queues[rx_queue_id];
2742 raw_cons = cpr->cp_raw_cons;
2745 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2746 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2747 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2749 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2761 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2763 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2764 struct bnxt_rx_ring_info *rxr;
2765 struct bnxt_cp_ring_info *cpr;
2766 struct bnxt_sw_rx_bd *rx_buf;
2767 struct rx_pkt_cmpl *rxcmp;
2768 uint32_t cons, cp_cons;
2774 rc = is_bnxt_in_error(rxq->bp);
2781 if (offset >= rxq->nb_rx_desc)
2784 cons = RING_CMP(cpr->cp_ring_struct, offset);
2785 cp_cons = cpr->cp_raw_cons;
2786 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2788 if (cons > cp_cons) {
2789 if (CMPL_VALID(rxcmp, cpr->valid))
2790 return RTE_ETH_RX_DESC_DONE;
2792 if (CMPL_VALID(rxcmp, !cpr->valid))
2793 return RTE_ETH_RX_DESC_DONE;
2795 rx_buf = &rxr->rx_buf_ring[cons];
2796 if (rx_buf->mbuf == NULL)
2797 return RTE_ETH_RX_DESC_UNAVAIL;
2800 return RTE_ETH_RX_DESC_AVAIL;
2804 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2806 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2807 struct bnxt_tx_ring_info *txr;
2808 struct bnxt_cp_ring_info *cpr;
2809 struct bnxt_sw_tx_bd *tx_buf;
2810 struct tx_pkt_cmpl *txcmp;
2811 uint32_t cons, cp_cons;
2817 rc = is_bnxt_in_error(txq->bp);
2824 if (offset >= txq->nb_tx_desc)
2827 cons = RING_CMP(cpr->cp_ring_struct, offset);
2828 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2829 cp_cons = cpr->cp_raw_cons;
2831 if (cons > cp_cons) {
2832 if (CMPL_VALID(txcmp, cpr->valid))
2833 return RTE_ETH_TX_DESC_UNAVAIL;
2835 if (CMPL_VALID(txcmp, !cpr->valid))
2836 return RTE_ETH_TX_DESC_UNAVAIL;
2838 tx_buf = &txr->tx_buf_ring[cons];
2839 if (tx_buf->mbuf == NULL)
2840 return RTE_ETH_TX_DESC_DONE;
2842 return RTE_ETH_TX_DESC_FULL;
2845 static struct bnxt_filter_info *
2846 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2847 struct rte_eth_ethertype_filter *efilter,
2848 struct bnxt_vnic_info *vnic0,
2849 struct bnxt_vnic_info *vnic,
2852 struct bnxt_filter_info *mfilter = NULL;
2856 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2857 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2858 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2859 " ethertype filter.", efilter->ether_type);
2863 if (efilter->queue >= bp->rx_nr_rings) {
2864 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2869 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2870 vnic = &bp->vnic_info[efilter->queue];
2872 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2877 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2878 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2879 if ((!memcmp(efilter->mac_addr.addr_bytes,
2880 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2882 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2883 mfilter->ethertype == efilter->ether_type)) {
2889 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2890 if ((!memcmp(efilter->mac_addr.addr_bytes,
2891 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2892 mfilter->ethertype == efilter->ether_type &&
2894 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2908 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2909 enum rte_filter_op filter_op,
2912 struct bnxt *bp = dev->data->dev_private;
2913 struct rte_eth_ethertype_filter *efilter =
2914 (struct rte_eth_ethertype_filter *)arg;
2915 struct bnxt_filter_info *bfilter, *filter1;
2916 struct bnxt_vnic_info *vnic, *vnic0;
2919 if (filter_op == RTE_ETH_FILTER_NOP)
2923 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2928 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2929 vnic = &bp->vnic_info[efilter->queue];
2931 switch (filter_op) {
2932 case RTE_ETH_FILTER_ADD:
2933 bnxt_match_and_validate_ether_filter(bp, efilter,
2938 bfilter = bnxt_get_unused_filter(bp);
2939 if (bfilter == NULL) {
2941 "Not enough resources for a new filter.\n");
2944 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2945 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2946 RTE_ETHER_ADDR_LEN);
2947 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2948 RTE_ETHER_ADDR_LEN);
2949 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2950 bfilter->ethertype = efilter->ether_type;
2951 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2953 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2954 if (filter1 == NULL) {
2959 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2960 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2962 bfilter->dst_id = vnic->fw_vnic_id;
2964 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2966 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2969 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2972 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2974 case RTE_ETH_FILTER_DELETE:
2975 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2977 if (ret == -EEXIST) {
2978 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2980 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2982 bnxt_free_filter(bp, filter1);
2983 } else if (ret == 0) {
2984 PMD_DRV_LOG(ERR, "No matching filter found\n");
2988 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2994 bnxt_free_filter(bp, bfilter);
3000 parse_ntuple_filter(struct bnxt *bp,
3001 struct rte_eth_ntuple_filter *nfilter,
3002 struct bnxt_filter_info *bfilter)
3006 if (nfilter->queue >= bp->rx_nr_rings) {
3007 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3011 switch (nfilter->dst_port_mask) {
3013 bfilter->dst_port_mask = -1;
3014 bfilter->dst_port = nfilter->dst_port;
3015 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3016 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3019 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3023 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3024 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3026 switch (nfilter->proto_mask) {
3028 if (nfilter->proto == 17) /* IPPROTO_UDP */
3029 bfilter->ip_protocol = 17;
3030 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3031 bfilter->ip_protocol = 6;
3034 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3037 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3041 switch (nfilter->dst_ip_mask) {
3043 bfilter->dst_ipaddr_mask[0] = -1;
3044 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3045 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3046 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3049 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3053 switch (nfilter->src_ip_mask) {
3055 bfilter->src_ipaddr_mask[0] = -1;
3056 bfilter->src_ipaddr[0] = nfilter->src_ip;
3057 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3058 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3061 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3065 switch (nfilter->src_port_mask) {
3067 bfilter->src_port_mask = -1;
3068 bfilter->src_port = nfilter->src_port;
3069 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3070 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3073 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3077 bfilter->enables = en;
3081 static struct bnxt_filter_info*
3082 bnxt_match_ntuple_filter(struct bnxt *bp,
3083 struct bnxt_filter_info *bfilter,
3084 struct bnxt_vnic_info **mvnic)
3086 struct bnxt_filter_info *mfilter = NULL;
3089 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3090 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3091 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3092 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3093 bfilter->src_ipaddr_mask[0] ==
3094 mfilter->src_ipaddr_mask[0] &&
3095 bfilter->src_port == mfilter->src_port &&
3096 bfilter->src_port_mask == mfilter->src_port_mask &&
3097 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3098 bfilter->dst_ipaddr_mask[0] ==
3099 mfilter->dst_ipaddr_mask[0] &&
3100 bfilter->dst_port == mfilter->dst_port &&
3101 bfilter->dst_port_mask == mfilter->dst_port_mask &&
3102 bfilter->flags == mfilter->flags &&
3103 bfilter->enables == mfilter->enables) {
3114 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3115 struct rte_eth_ntuple_filter *nfilter,
3116 enum rte_filter_op filter_op)
3118 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3119 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3122 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3123 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3127 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3128 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3132 bfilter = bnxt_get_unused_filter(bp);
3133 if (bfilter == NULL) {
3135 "Not enough resources for a new filter.\n");
3138 ret = parse_ntuple_filter(bp, nfilter, bfilter);
3142 vnic = &bp->vnic_info[nfilter->queue];
3143 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3144 filter1 = STAILQ_FIRST(&vnic0->filter);
3145 if (filter1 == NULL) {
3150 bfilter->dst_id = vnic->fw_vnic_id;
3151 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3153 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3154 bfilter->ethertype = 0x800;
3155 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3157 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3159 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3160 bfilter->dst_id == mfilter->dst_id) {
3161 PMD_DRV_LOG(ERR, "filter exists.\n");
3164 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3165 bfilter->dst_id != mfilter->dst_id) {
3166 mfilter->dst_id = vnic->fw_vnic_id;
3167 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3168 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3169 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3170 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3171 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3174 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3175 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3180 if (filter_op == RTE_ETH_FILTER_ADD) {
3181 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3182 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3185 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3187 if (mfilter == NULL) {
3188 /* This should not happen. But for Coverity! */
3192 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3194 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3195 bnxt_free_filter(bp, mfilter);
3196 bnxt_free_filter(bp, bfilter);
3201 bnxt_free_filter(bp, bfilter);
3206 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3207 enum rte_filter_op filter_op,
3210 struct bnxt *bp = dev->data->dev_private;
3213 if (filter_op == RTE_ETH_FILTER_NOP)
3217 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3222 switch (filter_op) {
3223 case RTE_ETH_FILTER_ADD:
3224 ret = bnxt_cfg_ntuple_filter(bp,
3225 (struct rte_eth_ntuple_filter *)arg,
3228 case RTE_ETH_FILTER_DELETE:
3229 ret = bnxt_cfg_ntuple_filter(bp,
3230 (struct rte_eth_ntuple_filter *)arg,
3234 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3242 bnxt_parse_fdir_filter(struct bnxt *bp,
3243 struct rte_eth_fdir_filter *fdir,
3244 struct bnxt_filter_info *filter)
3246 enum rte_fdir_mode fdir_mode =
3247 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3248 struct bnxt_vnic_info *vnic0, *vnic;
3249 struct bnxt_filter_info *filter1;
3253 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3256 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3257 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3259 switch (fdir->input.flow_type) {
3260 case RTE_ETH_FLOW_IPV4:
3261 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3263 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3264 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3265 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3266 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3267 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3268 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3269 filter->ip_addr_type =
3270 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3271 filter->src_ipaddr_mask[0] = 0xffffffff;
3272 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3273 filter->dst_ipaddr_mask[0] = 0xffffffff;
3274 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3275 filter->ethertype = 0x800;
3276 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3278 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3279 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3280 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3281 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3282 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3283 filter->dst_port_mask = 0xffff;
3284 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3285 filter->src_port_mask = 0xffff;
3286 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3287 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3288 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3289 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3290 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3291 filter->ip_protocol = 6;
3292 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3293 filter->ip_addr_type =
3294 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3295 filter->src_ipaddr_mask[0] = 0xffffffff;
3296 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3297 filter->dst_ipaddr_mask[0] = 0xffffffff;
3298 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3299 filter->ethertype = 0x800;
3300 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3302 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3303 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3304 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3305 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3306 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3307 filter->dst_port_mask = 0xffff;
3308 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3309 filter->src_port_mask = 0xffff;
3310 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3311 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3312 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3313 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3314 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3315 filter->ip_protocol = 17;
3316 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3317 filter->ip_addr_type =
3318 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3319 filter->src_ipaddr_mask[0] = 0xffffffff;
3320 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3321 filter->dst_ipaddr_mask[0] = 0xffffffff;
3322 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3323 filter->ethertype = 0x800;
3324 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3326 case RTE_ETH_FLOW_IPV6:
3327 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3329 filter->ip_addr_type =
3330 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3331 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3332 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3333 rte_memcpy(filter->src_ipaddr,
3334 fdir->input.flow.ipv6_flow.src_ip, 16);
3335 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3336 rte_memcpy(filter->dst_ipaddr,
3337 fdir->input.flow.ipv6_flow.dst_ip, 16);
3338 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3339 memset(filter->dst_ipaddr_mask, 0xff, 16);
3340 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3341 memset(filter->src_ipaddr_mask, 0xff, 16);
3342 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3343 filter->ethertype = 0x86dd;
3344 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3346 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3347 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3348 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3349 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3350 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3351 filter->dst_port_mask = 0xffff;
3352 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3353 filter->src_port_mask = 0xffff;
3354 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3355 filter->ip_addr_type =
3356 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3357 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3358 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3359 rte_memcpy(filter->src_ipaddr,
3360 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3361 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3362 rte_memcpy(filter->dst_ipaddr,
3363 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3364 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3365 memset(filter->dst_ipaddr_mask, 0xff, 16);
3366 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3367 memset(filter->src_ipaddr_mask, 0xff, 16);
3368 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3369 filter->ethertype = 0x86dd;
3370 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3372 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3373 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3374 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3375 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3376 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3377 filter->dst_port_mask = 0xffff;
3378 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3379 filter->src_port_mask = 0xffff;
3380 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3381 filter->ip_addr_type =
3382 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3383 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3384 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3385 rte_memcpy(filter->src_ipaddr,
3386 fdir->input.flow.udp6_flow.ip.src_ip, 16);
3387 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3388 rte_memcpy(filter->dst_ipaddr,
3389 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3390 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3391 memset(filter->dst_ipaddr_mask, 0xff, 16);
3392 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3393 memset(filter->src_ipaddr_mask, 0xff, 16);
3394 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3395 filter->ethertype = 0x86dd;
3396 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3398 case RTE_ETH_FLOW_L2_PAYLOAD:
3399 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3400 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3402 case RTE_ETH_FLOW_VXLAN:
3403 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3405 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3406 filter->tunnel_type =
3407 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3408 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3410 case RTE_ETH_FLOW_NVGRE:
3411 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3413 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3414 filter->tunnel_type =
3415 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3416 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3418 case RTE_ETH_FLOW_UNKNOWN:
3419 case RTE_ETH_FLOW_RAW:
3420 case RTE_ETH_FLOW_FRAG_IPV4:
3421 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3422 case RTE_ETH_FLOW_FRAG_IPV6:
3423 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3424 case RTE_ETH_FLOW_IPV6_EX:
3425 case RTE_ETH_FLOW_IPV6_TCP_EX:
3426 case RTE_ETH_FLOW_IPV6_UDP_EX:
3427 case RTE_ETH_FLOW_GENEVE:
3433 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3434 vnic = &bp->vnic_info[fdir->action.rx_queue];
3436 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3440 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3441 rte_memcpy(filter->dst_macaddr,
3442 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3443 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3446 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3447 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3448 filter1 = STAILQ_FIRST(&vnic0->filter);
3449 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3451 filter->dst_id = vnic->fw_vnic_id;
3452 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3453 if (filter->dst_macaddr[i] == 0x00)
3454 filter1 = STAILQ_FIRST(&vnic0->filter);
3456 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3459 if (filter1 == NULL)
3462 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3463 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3465 filter->enables = en;
3470 static struct bnxt_filter_info *
3471 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3472 struct bnxt_vnic_info **mvnic)
3474 struct bnxt_filter_info *mf = NULL;
3477 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3478 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3480 STAILQ_FOREACH(mf, &vnic->filter, next) {
3481 if (mf->filter_type == nf->filter_type &&
3482 mf->flags == nf->flags &&
3483 mf->src_port == nf->src_port &&
3484 mf->src_port_mask == nf->src_port_mask &&
3485 mf->dst_port == nf->dst_port &&
3486 mf->dst_port_mask == nf->dst_port_mask &&
3487 mf->ip_protocol == nf->ip_protocol &&
3488 mf->ip_addr_type == nf->ip_addr_type &&
3489 mf->ethertype == nf->ethertype &&
3490 mf->vni == nf->vni &&
3491 mf->tunnel_type == nf->tunnel_type &&
3492 mf->l2_ovlan == nf->l2_ovlan &&
3493 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3494 mf->l2_ivlan == nf->l2_ivlan &&
3495 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3496 !memcmp(mf->l2_addr, nf->l2_addr,
3497 RTE_ETHER_ADDR_LEN) &&
3498 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3499 RTE_ETHER_ADDR_LEN) &&
3500 !memcmp(mf->src_macaddr, nf->src_macaddr,
3501 RTE_ETHER_ADDR_LEN) &&
3502 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3503 RTE_ETHER_ADDR_LEN) &&
3504 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3505 sizeof(nf->src_ipaddr)) &&
3506 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3507 sizeof(nf->src_ipaddr_mask)) &&
3508 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3509 sizeof(nf->dst_ipaddr)) &&
3510 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3511 sizeof(nf->dst_ipaddr_mask))) {
3522 bnxt_fdir_filter(struct rte_eth_dev *dev,
3523 enum rte_filter_op filter_op,
3526 struct bnxt *bp = dev->data->dev_private;
3527 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3528 struct bnxt_filter_info *filter, *match;
3529 struct bnxt_vnic_info *vnic, *mvnic;
3532 if (filter_op == RTE_ETH_FILTER_NOP)
3535 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3538 switch (filter_op) {
3539 case RTE_ETH_FILTER_ADD:
3540 case RTE_ETH_FILTER_DELETE:
3542 filter = bnxt_get_unused_filter(bp);
3543 if (filter == NULL) {
3545 "Not enough resources for a new flow.\n");
3549 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3552 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3554 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3555 vnic = &bp->vnic_info[0];
3557 vnic = &bp->vnic_info[fdir->action.rx_queue];
3559 match = bnxt_match_fdir(bp, filter, &mvnic);
3560 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3561 if (match->dst_id == vnic->fw_vnic_id) {
3562 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3566 match->dst_id = vnic->fw_vnic_id;
3567 ret = bnxt_hwrm_set_ntuple_filter(bp,
3570 STAILQ_REMOVE(&mvnic->filter, match,
3571 bnxt_filter_info, next);
3572 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3574 "Filter with matching pattern exist\n");
3576 "Updated it to new destination q\n");
3580 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3581 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3586 if (filter_op == RTE_ETH_FILTER_ADD) {
3587 ret = bnxt_hwrm_set_ntuple_filter(bp,
3592 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3594 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3595 STAILQ_REMOVE(&vnic->filter, match,
3596 bnxt_filter_info, next);
3597 bnxt_free_filter(bp, match);
3598 bnxt_free_filter(bp, filter);
3601 case RTE_ETH_FILTER_FLUSH:
3602 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3603 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3605 STAILQ_FOREACH(filter, &vnic->filter, next) {
3606 if (filter->filter_type ==
3607 HWRM_CFA_NTUPLE_FILTER) {
3609 bnxt_hwrm_clear_ntuple_filter(bp,
3611 STAILQ_REMOVE(&vnic->filter, filter,
3612 bnxt_filter_info, next);
3617 case RTE_ETH_FILTER_UPDATE:
3618 case RTE_ETH_FILTER_STATS:
3619 case RTE_ETH_FILTER_INFO:
3620 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3623 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3630 bnxt_free_filter(bp, filter);
3635 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3636 enum rte_filter_type filter_type,
3637 enum rte_filter_op filter_op, void *arg)
3639 struct bnxt *bp = dev->data->dev_private;
3642 ret = is_bnxt_in_error(dev->data->dev_private);
3646 switch (filter_type) {
3647 case RTE_ETH_FILTER_TUNNEL:
3649 "filter type: %d: To be implemented\n", filter_type);
3651 case RTE_ETH_FILTER_FDIR:
3652 ret = bnxt_fdir_filter(dev, filter_op, arg);
3654 case RTE_ETH_FILTER_NTUPLE:
3655 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3657 case RTE_ETH_FILTER_ETHERTYPE:
3658 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3660 case RTE_ETH_FILTER_GENERIC:
3661 if (filter_op != RTE_ETH_FILTER_GET)
3663 if (BNXT_TRUFLOW_EN(bp))
3664 *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3666 *(const void **)arg = &bnxt_flow_ops;
3670 "Filter type (%d) not supported", filter_type);
3677 static const uint32_t *
3678 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3680 static const uint32_t ptypes[] = {
3681 RTE_PTYPE_L2_ETHER_VLAN,
3682 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3683 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3687 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3688 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3689 RTE_PTYPE_INNER_L4_ICMP,
3690 RTE_PTYPE_INNER_L4_TCP,
3691 RTE_PTYPE_INNER_L4_UDP,
3695 if (!dev->rx_pkt_burst)
3701 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3704 uint32_t reg_base = *reg_arr & 0xfffff000;
3708 for (i = 0; i < count; i++) {
3709 if ((reg_arr[i] & 0xfffff000) != reg_base)
3712 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3713 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3717 static int bnxt_map_ptp_regs(struct bnxt *bp)
3719 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3723 reg_arr = ptp->rx_regs;
3724 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3728 reg_arr = ptp->tx_regs;
3729 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3733 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3734 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3736 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3737 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3742 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3744 rte_write32(0, (uint8_t *)bp->bar0 +
3745 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3746 rte_write32(0, (uint8_t *)bp->bar0 +
3747 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3750 static uint64_t bnxt_cc_read(struct bnxt *bp)
3754 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3755 BNXT_GRCPF_REG_SYNC_TIME));
3756 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3757 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3761 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3763 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3766 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3767 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3768 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3771 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3772 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3773 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3774 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3775 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3776 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3781 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3783 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3784 struct bnxt_pf_info *pf = bp->pf;
3791 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3792 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3793 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3796 port_id = pf->port_id;
3797 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3798 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3800 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3801 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3802 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3803 /* bnxt_clr_rx_ts(bp); TBD */
3807 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3808 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3809 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3810 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3816 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3819 struct bnxt *bp = dev->data->dev_private;
3820 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3825 ns = rte_timespec_to_ns(ts);
3826 /* Set the timecounters to a new value. */
3833 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3835 struct bnxt *bp = dev->data->dev_private;
3836 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3837 uint64_t ns, systime_cycles = 0;
3843 if (BNXT_CHIP_THOR(bp))
3844 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3847 systime_cycles = bnxt_cc_read(bp);
3849 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3850 *ts = rte_ns_to_timespec(ns);
3855 bnxt_timesync_enable(struct rte_eth_dev *dev)
3857 struct bnxt *bp = dev->data->dev_private;
3858 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3866 ptp->tx_tstamp_en = 1;
3867 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3869 rc = bnxt_hwrm_ptp_cfg(bp);
3873 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3874 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3875 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3877 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3878 ptp->tc.cc_shift = shift;
3879 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3881 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3882 ptp->rx_tstamp_tc.cc_shift = shift;
3883 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3885 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3886 ptp->tx_tstamp_tc.cc_shift = shift;
3887 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3889 if (!BNXT_CHIP_THOR(bp))
3890 bnxt_map_ptp_regs(bp);
3896 bnxt_timesync_disable(struct rte_eth_dev *dev)
3898 struct bnxt *bp = dev->data->dev_private;
3899 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3905 ptp->tx_tstamp_en = 0;
3908 bnxt_hwrm_ptp_cfg(bp);
3910 if (!BNXT_CHIP_THOR(bp))
3911 bnxt_unmap_ptp_regs(bp);
3917 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3918 struct timespec *timestamp,
3919 uint32_t flags __rte_unused)
3921 struct bnxt *bp = dev->data->dev_private;
3922 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3923 uint64_t rx_tstamp_cycles = 0;
3929 if (BNXT_CHIP_THOR(bp))
3930 rx_tstamp_cycles = ptp->rx_timestamp;
3932 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3934 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3935 *timestamp = rte_ns_to_timespec(ns);
3940 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3941 struct timespec *timestamp)
3943 struct bnxt *bp = dev->data->dev_private;
3944 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3945 uint64_t tx_tstamp_cycles = 0;
3952 if (BNXT_CHIP_THOR(bp))
3953 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3956 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3958 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3959 *timestamp = rte_ns_to_timespec(ns);
3965 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3967 struct bnxt *bp = dev->data->dev_private;
3968 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3973 ptp->tc.nsec += delta;
3979 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3981 struct bnxt *bp = dev->data->dev_private;
3983 uint32_t dir_entries;
3984 uint32_t entry_length;
3986 rc = is_bnxt_in_error(bp);
3990 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3991 bp->pdev->addr.domain, bp->pdev->addr.bus,
3992 bp->pdev->addr.devid, bp->pdev->addr.function);
3994 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3998 return dir_entries * entry_length;
4002 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4003 struct rte_dev_eeprom_info *in_eeprom)
4005 struct bnxt *bp = dev->data->dev_private;
4010 rc = is_bnxt_in_error(bp);
4014 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4015 bp->pdev->addr.domain, bp->pdev->addr.bus,
4016 bp->pdev->addr.devid, bp->pdev->addr.function,
4017 in_eeprom->offset, in_eeprom->length);
4019 if (in_eeprom->offset == 0) /* special offset value to get directory */
4020 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4023 index = in_eeprom->offset >> 24;
4024 offset = in_eeprom->offset & 0xffffff;
4027 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4028 in_eeprom->length, in_eeprom->data);
4033 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4036 case BNX_DIR_TYPE_CHIMP_PATCH:
4037 case BNX_DIR_TYPE_BOOTCODE:
4038 case BNX_DIR_TYPE_BOOTCODE_2:
4039 case BNX_DIR_TYPE_APE_FW:
4040 case BNX_DIR_TYPE_APE_PATCH:
4041 case BNX_DIR_TYPE_KONG_FW:
4042 case BNX_DIR_TYPE_KONG_PATCH:
4043 case BNX_DIR_TYPE_BONO_FW:
4044 case BNX_DIR_TYPE_BONO_PATCH:
4052 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4055 case BNX_DIR_TYPE_AVS:
4056 case BNX_DIR_TYPE_EXP_ROM_MBA:
4057 case BNX_DIR_TYPE_PCIE:
4058 case BNX_DIR_TYPE_TSCF_UCODE:
4059 case BNX_DIR_TYPE_EXT_PHY:
4060 case BNX_DIR_TYPE_CCM:
4061 case BNX_DIR_TYPE_ISCSI_BOOT:
4062 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4063 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4071 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4073 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4074 bnxt_dir_type_is_other_exec_format(dir_type);
4078 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4079 struct rte_dev_eeprom_info *in_eeprom)
4081 struct bnxt *bp = dev->data->dev_private;
4082 uint8_t index, dir_op;
4083 uint16_t type, ext, ordinal, attr;
4086 rc = is_bnxt_in_error(bp);
4090 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4091 bp->pdev->addr.domain, bp->pdev->addr.bus,
4092 bp->pdev->addr.devid, bp->pdev->addr.function,
4093 in_eeprom->offset, in_eeprom->length);
4096 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4100 type = in_eeprom->magic >> 16;
4102 if (type == 0xffff) { /* special value for directory operations */
4103 index = in_eeprom->magic & 0xff;
4104 dir_op = in_eeprom->magic >> 8;
4108 case 0x0e: /* erase */
4109 if (in_eeprom->offset != ~in_eeprom->magic)
4111 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4117 /* Create or re-write an NVM item: */
4118 if (bnxt_dir_type_is_executable(type) == true)
4120 ext = in_eeprom->magic & 0xffff;
4121 ordinal = in_eeprom->offset >> 16;
4122 attr = in_eeprom->offset & 0xffff;
4124 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4125 in_eeprom->data, in_eeprom->length);
4132 static const struct eth_dev_ops bnxt_dev_ops = {
4133 .dev_infos_get = bnxt_dev_info_get_op,
4134 .dev_close = bnxt_dev_close_op,
4135 .dev_configure = bnxt_dev_configure_op,
4136 .dev_start = bnxt_dev_start_op,
4137 .dev_stop = bnxt_dev_stop_op,
4138 .dev_set_link_up = bnxt_dev_set_link_up_op,
4139 .dev_set_link_down = bnxt_dev_set_link_down_op,
4140 .stats_get = bnxt_stats_get_op,
4141 .stats_reset = bnxt_stats_reset_op,
4142 .rx_queue_setup = bnxt_rx_queue_setup_op,
4143 .rx_queue_release = bnxt_rx_queue_release_op,
4144 .tx_queue_setup = bnxt_tx_queue_setup_op,
4145 .tx_queue_release = bnxt_tx_queue_release_op,
4146 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4147 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4148 .reta_update = bnxt_reta_update_op,
4149 .reta_query = bnxt_reta_query_op,
4150 .rss_hash_update = bnxt_rss_hash_update_op,
4151 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4152 .link_update = bnxt_link_update_op,
4153 .promiscuous_enable = bnxt_promiscuous_enable_op,
4154 .promiscuous_disable = bnxt_promiscuous_disable_op,
4155 .allmulticast_enable = bnxt_allmulticast_enable_op,
4156 .allmulticast_disable = bnxt_allmulticast_disable_op,
4157 .mac_addr_add = bnxt_mac_addr_add_op,
4158 .mac_addr_remove = bnxt_mac_addr_remove_op,
4159 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4160 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4161 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
4162 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
4163 .vlan_filter_set = bnxt_vlan_filter_set_op,
4164 .vlan_offload_set = bnxt_vlan_offload_set_op,
4165 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4166 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4167 .mtu_set = bnxt_mtu_set_op,
4168 .mac_addr_set = bnxt_set_default_mac_addr_op,
4169 .xstats_get = bnxt_dev_xstats_get_op,
4170 .xstats_get_names = bnxt_dev_xstats_get_names_op,
4171 .xstats_reset = bnxt_dev_xstats_reset_op,
4172 .fw_version_get = bnxt_fw_version_get,
4173 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4174 .rxq_info_get = bnxt_rxq_info_get_op,
4175 .txq_info_get = bnxt_txq_info_get_op,
4176 .dev_led_on = bnxt_dev_led_on_op,
4177 .dev_led_off = bnxt_dev_led_off_op,
4178 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4179 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4180 .rx_queue_count = bnxt_rx_queue_count_op,
4181 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
4182 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
4183 .rx_queue_start = bnxt_rx_queue_start,
4184 .rx_queue_stop = bnxt_rx_queue_stop,
4185 .tx_queue_start = bnxt_tx_queue_start,
4186 .tx_queue_stop = bnxt_tx_queue_stop,
4187 .filter_ctrl = bnxt_filter_ctrl_op,
4188 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4189 .get_eeprom_length = bnxt_get_eeprom_length_op,
4190 .get_eeprom = bnxt_get_eeprom_op,
4191 .set_eeprom = bnxt_set_eeprom_op,
4192 .timesync_enable = bnxt_timesync_enable,
4193 .timesync_disable = bnxt_timesync_disable,
4194 .timesync_read_time = bnxt_timesync_read_time,
4195 .timesync_write_time = bnxt_timesync_write_time,
4196 .timesync_adjust_time = bnxt_timesync_adjust_time,
4197 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4198 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4201 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4205 /* Only pre-map the reset GRC registers using window 3 */
4206 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4207 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4209 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4214 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4216 struct bnxt_error_recovery_info *info = bp->recovery_info;
4217 uint32_t reg_base = 0xffffffff;
4220 /* Only pre-map the monitoring GRC registers using window 2 */
4221 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4222 uint32_t reg = info->status_regs[i];
4224 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4227 if (reg_base == 0xffffffff)
4228 reg_base = reg & 0xfffff000;
4229 if ((reg & 0xfffff000) != reg_base)
4232 /* Use mask 0xffc as the Lower 2 bits indicates
4233 * address space location
4235 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4239 if (reg_base == 0xffffffff)
4242 rte_write32(reg_base, (uint8_t *)bp->bar0 +
4243 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4248 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4250 struct bnxt_error_recovery_info *info = bp->recovery_info;
4251 uint32_t delay = info->delay_after_reset[index];
4252 uint32_t val = info->reset_reg_val[index];
4253 uint32_t reg = info->reset_reg[index];
4254 uint32_t type, offset;
4256 type = BNXT_FW_STATUS_REG_TYPE(reg);
4257 offset = BNXT_FW_STATUS_REG_OFF(reg);
4260 case BNXT_FW_STATUS_REG_TYPE_CFG:
4261 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4263 case BNXT_FW_STATUS_REG_TYPE_GRC:
4264 offset = bnxt_map_reset_regs(bp, offset);
4265 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4267 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4268 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4271 /* wait on a specific interval of time until core reset is complete */
4273 rte_delay_ms(delay);
4276 static void bnxt_dev_cleanup(struct bnxt *bp)
4278 bnxt_set_hwrm_link_config(bp, false);
4279 bp->link_info->link_up = 0;
4280 if (bp->eth_dev->data->dev_started)
4281 bnxt_dev_stop_op(bp->eth_dev);
4283 bnxt_uninit_resources(bp, true);
4286 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4288 struct rte_eth_dev *dev = bp->eth_dev;
4289 struct rte_vlan_filter_conf *vfc;
4293 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4294 vfc = &dev->data->vlan_filter_conf;
4295 vidx = vlan_id / 64;
4296 vbit = vlan_id % 64;
4298 /* Each bit corresponds to a VLAN id */
4299 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4300 rc = bnxt_add_vlan_filter(bp, vlan_id);
4309 static int bnxt_restore_mac_filters(struct bnxt *bp)
4311 struct rte_eth_dev *dev = bp->eth_dev;
4312 struct rte_eth_dev_info dev_info;
4313 struct rte_ether_addr *addr;
4319 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
4322 rc = bnxt_dev_info_get_op(dev, &dev_info);
4326 /* replay MAC address configuration */
4327 for (i = 1; i < dev_info.max_mac_addrs; i++) {
4328 addr = &dev->data->mac_addrs[i];
4330 /* skip zero address */
4331 if (rte_is_zero_ether_addr(addr))
4335 pool_mask = dev->data->mac_pool_sel[i];
4338 if (pool_mask & 1ULL) {
4339 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4345 } while (pool_mask);
4351 static int bnxt_restore_filters(struct bnxt *bp)
4353 struct rte_eth_dev *dev = bp->eth_dev;
4356 if (dev->data->all_multicast) {
4357 ret = bnxt_allmulticast_enable_op(dev);
4361 if (dev->data->promiscuous) {
4362 ret = bnxt_promiscuous_enable_op(dev);
4367 ret = bnxt_restore_mac_filters(bp);
4371 ret = bnxt_restore_vlan_filters(bp);
4372 /* TODO restore other filters as well */
4376 static void bnxt_dev_recover(void *arg)
4378 struct bnxt *bp = arg;
4379 int timeout = bp->fw_reset_max_msecs;
4382 /* Clear Error flag so that device re-init should happen */
4383 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4386 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4389 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4390 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4391 } while (rc && timeout);
4394 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4398 rc = bnxt_init_resources(bp, true);
4401 "Failed to initialize resources after reset\n");
4404 /* clear reset flag as the device is initialized now */
4405 bp->flags &= ~BNXT_FLAG_FW_RESET;
4407 rc = bnxt_dev_start_op(bp->eth_dev);
4409 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4413 rc = bnxt_restore_filters(bp);
4417 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4420 bnxt_dev_stop_op(bp->eth_dev);
4422 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4423 bnxt_uninit_resources(bp, false);
4424 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4427 void bnxt_dev_reset_and_resume(void *arg)
4429 struct bnxt *bp = arg;
4432 bnxt_dev_cleanup(bp);
4434 bnxt_wait_for_device_shutdown(bp);
4436 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4437 bnxt_dev_recover, (void *)bp);
4439 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4442 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4444 struct bnxt_error_recovery_info *info = bp->recovery_info;
4445 uint32_t reg = info->status_regs[index];
4446 uint32_t type, offset, val = 0;
4448 type = BNXT_FW_STATUS_REG_TYPE(reg);
4449 offset = BNXT_FW_STATUS_REG_OFF(reg);
4452 case BNXT_FW_STATUS_REG_TYPE_CFG:
4453 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4455 case BNXT_FW_STATUS_REG_TYPE_GRC:
4456 offset = info->mapped_status_regs[index];
4458 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4459 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4467 static int bnxt_fw_reset_all(struct bnxt *bp)
4469 struct bnxt_error_recovery_info *info = bp->recovery_info;
4473 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4474 /* Reset through master function driver */
4475 for (i = 0; i < info->reg_array_cnt; i++)
4476 bnxt_write_fw_reset_reg(bp, i);
4477 /* Wait for time specified by FW after triggering reset */
4478 rte_delay_ms(info->master_func_wait_period_after_reset);
4479 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4480 /* Reset with the help of Kong processor */
4481 rc = bnxt_hwrm_fw_reset(bp);
4483 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4489 static void bnxt_fw_reset_cb(void *arg)
4491 struct bnxt *bp = arg;
4492 struct bnxt_error_recovery_info *info = bp->recovery_info;
4495 /* Only Master function can do FW reset */
4496 if (bnxt_is_master_func(bp) &&
4497 bnxt_is_recovery_enabled(bp)) {
4498 rc = bnxt_fw_reset_all(bp);
4500 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4505 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4506 * EXCEPTION_FATAL_ASYNC event to all the functions
4507 * (including MASTER FUNC). After receiving this Async, all the active
4508 * drivers should treat this case as FW initiated recovery
4510 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4511 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4512 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4514 /* To recover from error */
4515 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4520 /* Driver should poll FW heartbeat, reset_counter with the frequency
4521 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4522 * When the driver detects heartbeat stop or change in reset_counter,
4523 * it has to trigger a reset to recover from the error condition.
4524 * A “master PF” is the function who will have the privilege to
4525 * initiate the chimp reset. The master PF will be elected by the
4526 * firmware and will be notified through async message.
4528 static void bnxt_check_fw_health(void *arg)
4530 struct bnxt *bp = arg;
4531 struct bnxt_error_recovery_info *info = bp->recovery_info;
4532 uint32_t val = 0, wait_msec;
4534 if (!info || !bnxt_is_recovery_enabled(bp) ||
4535 is_bnxt_in_error(bp))
4538 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4539 if (val == info->last_heart_beat)
4542 info->last_heart_beat = val;
4544 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4545 if (val != info->last_reset_counter)
4548 info->last_reset_counter = val;
4550 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4551 bnxt_check_fw_health, (void *)bp);
4555 /* Stop DMA to/from device */
4556 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4557 bp->flags |= BNXT_FLAG_FW_RESET;
4559 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4561 if (bnxt_is_master_func(bp))
4562 wait_msec = info->master_func_wait_period;
4564 wait_msec = info->normal_func_wait_period;
4566 rte_eal_alarm_set(US_PER_MS * wait_msec,
4567 bnxt_fw_reset_cb, (void *)bp);
4570 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4572 uint32_t polling_freq;
4574 if (!bnxt_is_recovery_enabled(bp))
4577 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4580 polling_freq = bp->recovery_info->driver_polling_freq;
4582 rte_eal_alarm_set(US_PER_MS * polling_freq,
4583 bnxt_check_fw_health, (void *)bp);
4584 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4587 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4589 if (!bnxt_is_recovery_enabled(bp))
4592 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4593 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4596 static bool bnxt_vf_pciid(uint16_t device_id)
4598 switch (device_id) {
4599 case BROADCOM_DEV_ID_57304_VF:
4600 case BROADCOM_DEV_ID_57406_VF:
4601 case BROADCOM_DEV_ID_5731X_VF:
4602 case BROADCOM_DEV_ID_5741X_VF:
4603 case BROADCOM_DEV_ID_57414_VF:
4604 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4605 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4606 case BROADCOM_DEV_ID_58802_VF:
4607 case BROADCOM_DEV_ID_57500_VF1:
4608 case BROADCOM_DEV_ID_57500_VF2:
4616 static bool bnxt_thor_device(uint16_t device_id)
4618 switch (device_id) {
4619 case BROADCOM_DEV_ID_57508:
4620 case BROADCOM_DEV_ID_57504:
4621 case BROADCOM_DEV_ID_57502:
4622 case BROADCOM_DEV_ID_57508_MF1:
4623 case BROADCOM_DEV_ID_57504_MF1:
4624 case BROADCOM_DEV_ID_57502_MF1:
4625 case BROADCOM_DEV_ID_57508_MF2:
4626 case BROADCOM_DEV_ID_57504_MF2:
4627 case BROADCOM_DEV_ID_57502_MF2:
4628 case BROADCOM_DEV_ID_57500_VF1:
4629 case BROADCOM_DEV_ID_57500_VF2:
4637 bool bnxt_stratus_device(struct bnxt *bp)
4639 uint16_t device_id = bp->pdev->id.device_id;
4641 switch (device_id) {
4642 case BROADCOM_DEV_ID_STRATUS_NIC:
4643 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4644 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4652 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4654 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4655 struct bnxt *bp = eth_dev->data->dev_private;
4657 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4658 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4659 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4660 if (!bp->bar0 || !bp->doorbell_base) {
4661 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4665 bp->eth_dev = eth_dev;
4671 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4672 struct bnxt_ctx_pg_info *ctx_pg,
4677 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4678 const struct rte_memzone *mz = NULL;
4679 char mz_name[RTE_MEMZONE_NAMESIZE];
4680 rte_iova_t mz_phys_addr;
4681 uint64_t valid_bits = 0;
4688 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4690 rmem->page_size = BNXT_PAGE_SIZE;
4691 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4692 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4693 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4695 valid_bits = PTU_PTE_VALID;
4697 if (rmem->nr_pages > 1) {
4698 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4699 "bnxt_ctx_pg_tbl%s_%x_%d",
4700 suffix, idx, bp->eth_dev->data->port_id);
4701 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4702 mz = rte_memzone_lookup(mz_name);
4704 mz = rte_memzone_reserve_aligned(mz_name,
4708 RTE_MEMZONE_SIZE_HINT_ONLY |
4709 RTE_MEMZONE_IOVA_CONTIG,
4715 memset(mz->addr, 0, mz->len);
4716 mz_phys_addr = mz->iova;
4718 rmem->pg_tbl = mz->addr;
4719 rmem->pg_tbl_map = mz_phys_addr;
4720 rmem->pg_tbl_mz = mz;
4723 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4724 suffix, idx, bp->eth_dev->data->port_id);
4725 mz = rte_memzone_lookup(mz_name);
4727 mz = rte_memzone_reserve_aligned(mz_name,
4731 RTE_MEMZONE_SIZE_HINT_ONLY |
4732 RTE_MEMZONE_IOVA_CONTIG,
4738 memset(mz->addr, 0, mz->len);
4739 mz_phys_addr = mz->iova;
4741 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4742 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4743 rmem->dma_arr[i] = mz_phys_addr + sz;
4745 if (rmem->nr_pages > 1) {
4746 if (i == rmem->nr_pages - 2 &&
4747 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4748 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4749 else if (i == rmem->nr_pages - 1 &&
4750 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4751 valid_bits |= PTU_PTE_LAST;
4753 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4759 if (rmem->vmem_size)
4760 rmem->vmem = (void **)mz->addr;
4761 rmem->dma_arr[0] = mz_phys_addr;
4765 static void bnxt_free_ctx_mem(struct bnxt *bp)
4769 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4772 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4773 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4774 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4775 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4776 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4777 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4778 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4779 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4780 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4781 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4782 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4784 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4785 if (bp->ctx->tqm_mem[i])
4786 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4793 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4795 #define min_t(type, x, y) ({ \
4796 type __min1 = (x); \
4797 type __min2 = (y); \
4798 __min1 < __min2 ? __min1 : __min2; })
4800 #define max_t(type, x, y) ({ \
4801 type __max1 = (x); \
4802 type __max2 = (y); \
4803 __max1 > __max2 ? __max1 : __max2; })
4805 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4807 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4809 struct bnxt_ctx_pg_info *ctx_pg;
4810 struct bnxt_ctx_mem_info *ctx;
4811 uint32_t mem_size, ena, entries;
4812 uint32_t entries_sp, min;
4815 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4817 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4821 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4824 ctx_pg = &ctx->qp_mem;
4825 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4826 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4827 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4831 ctx_pg = &ctx->srq_mem;
4832 ctx_pg->entries = ctx->srq_max_l2_entries;
4833 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4834 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4838 ctx_pg = &ctx->cq_mem;
4839 ctx_pg->entries = ctx->cq_max_l2_entries;
4840 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4841 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4845 ctx_pg = &ctx->vnic_mem;
4846 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4847 ctx->vnic_max_ring_table_entries;
4848 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4849 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4853 ctx_pg = &ctx->stat_mem;
4854 ctx_pg->entries = ctx->stat_max_entries;
4855 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4856 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4860 min = ctx->tqm_min_entries_per_ring;
4862 entries_sp = ctx->qp_max_l2_entries +
4863 ctx->vnic_max_vnic_entries +
4864 2 * ctx->qp_min_qp1_entries + min;
4865 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4867 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4868 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4869 entries = clamp_t(uint32_t, entries, min,
4870 ctx->tqm_max_entries_per_ring);
4871 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4872 ctx_pg = ctx->tqm_mem[i];
4873 ctx_pg->entries = i ? entries : entries_sp;
4874 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4875 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4878 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4881 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4882 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4885 "Failed to configure context mem: rc = %d\n", rc);
4887 ctx->flags |= BNXT_CTX_FLAG_INITED;
4892 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4894 struct rte_pci_device *pci_dev = bp->pdev;
4895 char mz_name[RTE_MEMZONE_NAMESIZE];
4896 const struct rte_memzone *mz = NULL;
4897 uint32_t total_alloc_len;
4898 rte_iova_t mz_phys_addr;
4900 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4903 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4904 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4905 pci_dev->addr.bus, pci_dev->addr.devid,
4906 pci_dev->addr.function, "rx_port_stats");
4907 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4908 mz = rte_memzone_lookup(mz_name);
4910 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4911 sizeof(struct rx_port_stats_ext) + 512);
4913 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4916 RTE_MEMZONE_SIZE_HINT_ONLY |
4917 RTE_MEMZONE_IOVA_CONTIG);
4921 memset(mz->addr, 0, mz->len);
4922 mz_phys_addr = mz->iova;
4924 bp->rx_mem_zone = (const void *)mz;
4925 bp->hw_rx_port_stats = mz->addr;
4926 bp->hw_rx_port_stats_map = mz_phys_addr;
4928 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4929 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4930 pci_dev->addr.bus, pci_dev->addr.devid,
4931 pci_dev->addr.function, "tx_port_stats");
4932 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4933 mz = rte_memzone_lookup(mz_name);
4935 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4936 sizeof(struct tx_port_stats_ext) + 512);
4938 mz = rte_memzone_reserve(mz_name,
4942 RTE_MEMZONE_SIZE_HINT_ONLY |
4943 RTE_MEMZONE_IOVA_CONTIG);
4947 memset(mz->addr, 0, mz->len);
4948 mz_phys_addr = mz->iova;
4950 bp->tx_mem_zone = (const void *)mz;
4951 bp->hw_tx_port_stats = mz->addr;
4952 bp->hw_tx_port_stats_map = mz_phys_addr;
4953 bp->flags |= BNXT_FLAG_PORT_STATS;
4955 /* Display extended statistics if FW supports it */
4956 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4957 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4958 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4961 bp->hw_rx_port_stats_ext = (void *)
4962 ((uint8_t *)bp->hw_rx_port_stats +
4963 sizeof(struct rx_port_stats));
4964 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4965 sizeof(struct rx_port_stats);
4966 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4968 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4969 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4970 bp->hw_tx_port_stats_ext = (void *)
4971 ((uint8_t *)bp->hw_tx_port_stats +
4972 sizeof(struct tx_port_stats));
4973 bp->hw_tx_port_stats_ext_map =
4974 bp->hw_tx_port_stats_map +
4975 sizeof(struct tx_port_stats);
4976 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4982 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4984 struct bnxt *bp = eth_dev->data->dev_private;
4987 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4988 RTE_ETHER_ADDR_LEN *
4991 if (eth_dev->data->mac_addrs == NULL) {
4992 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4996 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5000 /* Generate a random MAC address, if none was assigned by PF */
5001 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5002 bnxt_eth_hw_addr_random(bp->mac_addr);
5004 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5005 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5006 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5008 rc = bnxt_hwrm_set_mac(bp);
5013 /* Copy the permanent MAC from the FUNC_QCAPS response */
5014 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5019 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5023 /* MAC is already configured in FW */
5024 if (BNXT_HAS_DFLT_MAC_SET(bp))
5027 /* Restore the old MAC configured */
5028 rc = bnxt_hwrm_set_mac(bp);
5030 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5035 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5040 #define ALLOW_FUNC(x) \
5042 uint32_t arg = (x); \
5043 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5044 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5047 /* Forward all requests if firmware is new enough */
5048 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5049 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5050 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5051 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5053 PMD_DRV_LOG(WARNING,
5054 "Firmware too old for VF mailbox functionality\n");
5055 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5059 * The following are used for driver cleanup. If we disallow these,
5060 * VF drivers can't clean up cleanly.
5062 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5063 ALLOW_FUNC(HWRM_VNIC_FREE);
5064 ALLOW_FUNC(HWRM_RING_FREE);
5065 ALLOW_FUNC(HWRM_RING_GRP_FREE);
5066 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5067 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5068 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5069 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5070 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5074 bnxt_get_svif(uint16_t port_id, bool func_svif)
5076 struct rte_eth_dev *eth_dev;
5079 eth_dev = &rte_eth_devices[port_id];
5080 bp = eth_dev->data->dev_private;
5082 return func_svif ? bp->func_svif : bp->port_svif;
5086 bnxt_get_vnic_id(uint16_t port)
5088 struct rte_eth_dev *eth_dev;
5089 struct bnxt_vnic_info *vnic;
5092 eth_dev = &rte_eth_devices[port];
5093 bp = eth_dev->data->dev_private;
5095 vnic = BNXT_GET_DEFAULT_VNIC(bp);
5097 return vnic->fw_vnic_id;
5101 bnxt_get_fw_func_id(uint16_t port)
5103 struct rte_eth_dev *eth_dev;
5106 eth_dev = &rte_eth_devices[port];
5107 bp = eth_dev->data->dev_private;
5112 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5114 struct bnxt_error_recovery_info *info = bp->recovery_info;
5117 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5118 memset(info, 0, sizeof(*info));
5122 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5125 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5128 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5130 bp->recovery_info = info;
5133 static void bnxt_check_fw_status(struct bnxt *bp)
5137 if (!(bp->recovery_info &&
5138 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5141 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5142 if (fw_status != BNXT_FW_STATUS_HEALTHY)
5143 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5147 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5149 struct bnxt_error_recovery_info *info = bp->recovery_info;
5150 uint32_t status_loc;
5153 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5154 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5155 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5156 BNXT_GRCP_WINDOW_2_BASE +
5157 offsetof(struct hcomm_status,
5159 /* If the signature is absent, then FW does not support this feature */
5160 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5161 HCOMM_STATUS_SIGNATURE_VAL)
5165 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5169 bp->recovery_info = info;
5171 memset(info, 0, sizeof(*info));
5174 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5175 BNXT_GRCP_WINDOW_2_BASE +
5176 offsetof(struct hcomm_status,
5179 /* Only pre-map the FW health status GRC register */
5180 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5183 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5184 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5185 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5187 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5188 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5190 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5195 static int bnxt_init_fw(struct bnxt *bp)
5202 rc = bnxt_map_hcomm_fw_status_reg(bp);
5206 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5208 bnxt_check_fw_status(bp);
5212 rc = bnxt_hwrm_func_reset(bp);
5216 rc = bnxt_hwrm_vnic_qcaps(bp);
5220 rc = bnxt_hwrm_queue_qportcfg(bp);
5224 /* Get the MAX capabilities for this function.
5225 * This function also allocates context memory for TQM rings and
5226 * informs the firmware about this allocated backing store memory.
5228 rc = bnxt_hwrm_func_qcaps(bp);
5232 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5236 bnxt_hwrm_port_mac_qcfg(bp);
5238 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5242 bnxt_alloc_error_recovery_info(bp);
5243 /* Get the adapter error recovery support info */
5244 rc = bnxt_hwrm_error_recovery_qcfg(bp);
5246 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5248 bnxt_hwrm_port_led_qcaps(bp);
5254 bnxt_init_locks(struct bnxt *bp)
5258 err = pthread_mutex_init(&bp->flow_lock, NULL);
5260 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5264 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5266 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5270 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5274 rc = bnxt_init_fw(bp);
5278 if (!reconfig_dev) {
5279 rc = bnxt_setup_mac_addr(bp->eth_dev);
5283 rc = bnxt_restore_dflt_mac(bp);
5288 bnxt_config_vf_req_fwd(bp);
5290 rc = bnxt_hwrm_func_driver_register(bp);
5292 PMD_DRV_LOG(ERR, "Failed to register driver");
5297 if (bp->pdev->max_vfs) {
5298 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5300 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5304 rc = bnxt_hwrm_allocate_pf_only(bp);
5307 "Failed to allocate PF resources");
5313 rc = bnxt_alloc_mem(bp, reconfig_dev);
5317 rc = bnxt_setup_int(bp);
5321 rc = bnxt_request_int(bp);
5325 rc = bnxt_init_ctx_mem(bp);
5327 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5331 rc = bnxt_init_locks(bp);
5339 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5340 const char *value, void *opaque_arg)
5342 struct bnxt *bp = opaque_arg;
5343 unsigned long truflow;
5346 if (!value || !opaque_arg) {
5348 "Invalid parameter passed to truflow devargs.\n");
5352 truflow = strtoul(value, &end, 10);
5353 if (end == NULL || *end != '\0' ||
5354 (truflow == ULONG_MAX && errno == ERANGE)) {
5356 "Invalid parameter passed to truflow devargs.\n");
5360 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5362 "Invalid value passed to truflow devargs.\n");
5366 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5367 if (BNXT_TRUFLOW_EN(bp))
5368 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5374 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5375 const char *value, void *opaque_arg)
5377 struct bnxt *bp = opaque_arg;
5378 unsigned long flow_xstat;
5381 if (!value || !opaque_arg) {
5383 "Invalid parameter passed to flow_xstat devarg.\n");
5387 flow_xstat = strtoul(value, &end, 10);
5388 if (end == NULL || *end != '\0' ||
5389 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5391 "Invalid parameter passed to flow_xstat devarg.\n");
5395 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5397 "Invalid value passed to flow_xstat devarg.\n");
5401 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5402 if (BNXT_FLOW_XSTATS_EN(bp))
5403 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5409 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5410 const char *value, void *opaque_arg)
5412 struct bnxt *bp = opaque_arg;
5413 unsigned long max_num_kflows;
5416 if (!value || !opaque_arg) {
5418 "Invalid parameter passed to max_num_kflows devarg.\n");
5422 max_num_kflows = strtoul(value, &end, 10);
5423 if (end == NULL || *end != '\0' ||
5424 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5426 "Invalid parameter passed to max_num_kflows devarg.\n");
5430 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5432 "Invalid value passed to max_num_kflows devarg.\n");
5436 bp->max_num_kflows = max_num_kflows;
5437 if (bp->max_num_kflows)
5438 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5445 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5447 struct rte_kvargs *kvlist;
5449 if (devargs == NULL)
5452 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5457 * Handler for "truflow" devarg.
5458 * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5460 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5461 bnxt_parse_devarg_truflow, bp);
5464 * Handler for "flow_xstat" devarg.
5465 * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5467 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5468 bnxt_parse_devarg_flow_xstat, bp);
5471 * Handler for "max_num_kflows" devarg.
5472 * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5474 rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5475 bnxt_parse_devarg_max_num_kflows, bp);
5477 rte_kvargs_free(kvlist);
5481 bnxt_dev_init(struct rte_eth_dev *eth_dev)
5483 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5484 static int version_printed;
5488 if (version_printed++ == 0)
5489 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5491 eth_dev->dev_ops = &bnxt_dev_ops;
5492 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5493 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5496 * For secondary processes, we don't initialise any further
5497 * as primary has already done this work.
5499 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5502 rte_eth_copy_pci_info(eth_dev, pci_dev);
5504 bp = eth_dev->data->dev_private;
5506 /* Parse dev arguments passed on when starting the DPDK application. */
5507 bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5509 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5511 if (bnxt_vf_pciid(pci_dev->id.device_id))
5512 bp->flags |= BNXT_FLAG_VF;
5514 if (bnxt_thor_device(pci_dev->id.device_id))
5515 bp->flags |= BNXT_FLAG_THOR_CHIP;
5517 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5518 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5519 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5520 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5521 bp->flags |= BNXT_FLAG_STINGRAY;
5523 rc = bnxt_init_board(eth_dev);
5526 "Failed to initialize board rc: %x\n", rc);
5530 rc = bnxt_alloc_pf_info(bp);
5534 rc = bnxt_alloc_link_info(bp);
5538 rc = bnxt_alloc_hwrm_resources(bp);
5541 "Failed to allocate hwrm resource rc: %x\n", rc);
5544 rc = bnxt_alloc_leds_info(bp);
5548 rc = bnxt_alloc_cos_queues(bp);
5552 rc = bnxt_init_resources(bp, false);
5556 rc = bnxt_alloc_stats_mem(bp);
5560 /* Pass the information to the rte_eth_dev_close() that it should also
5561 * release the private port resources.
5563 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5566 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5567 pci_dev->mem_resource[0].phys_addr,
5568 pci_dev->mem_resource[0].addr);
5573 bnxt_dev_uninit(eth_dev);
5578 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5587 ctx->dma = RTE_BAD_IOVA;
5588 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5591 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5593 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5594 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5595 bp->flow_stat->rx_fc_out_tbl.ctx_id,
5596 bp->flow_stat->max_fc,
5599 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5600 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5601 bp->flow_stat->tx_fc_out_tbl.ctx_id,
5602 bp->flow_stat->max_fc,
5605 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5606 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5607 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5609 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5610 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5611 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5613 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5614 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5615 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5617 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5618 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5619 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5622 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5624 bnxt_unregister_fc_ctx_mem(bp);
5626 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5627 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5628 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5629 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5632 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5634 if (BNXT_FLOW_XSTATS_EN(bp))
5635 bnxt_uninit_fc_ctx_mem(bp);
5639 bnxt_free_error_recovery_info(struct bnxt *bp)
5641 rte_free(bp->recovery_info);
5642 bp->recovery_info = NULL;
5643 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5647 bnxt_uninit_locks(struct bnxt *bp)
5649 pthread_mutex_destroy(&bp->flow_lock);
5650 pthread_mutex_destroy(&bp->def_cp_lock);
5654 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5659 bnxt_free_mem(bp, reconfig_dev);
5660 bnxt_hwrm_func_buf_unrgtr(bp);
5661 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5662 bp->flags &= ~BNXT_FLAG_REGISTERED;
5663 bnxt_free_ctx_mem(bp);
5664 if (!reconfig_dev) {
5665 bnxt_free_hwrm_resources(bp);
5666 bnxt_free_error_recovery_info(bp);
5669 bnxt_uninit_ctx_mem(bp);
5671 bnxt_uninit_locks(bp);
5672 bnxt_free_flow_stats_info(bp);
5673 rte_free(bp->ptp_cfg);
5679 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5681 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5684 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5686 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5687 bnxt_dev_close_op(eth_dev);
5692 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5693 struct rte_pci_device *pci_dev)
5695 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
5699 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5701 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
5702 return rte_eth_dev_pci_generic_remove(pci_dev,
5705 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5708 static struct rte_pci_driver bnxt_rte_pmd = {
5709 .id_table = bnxt_pci_id_map,
5710 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5711 .probe = bnxt_pci_probe,
5712 .remove = bnxt_pci_remove,
5716 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5718 if (strcmp(dev->device->driver->name, drv->driver.name))
5724 bool is_bnxt_supported(struct rte_eth_dev *dev)
5726 return is_device_supported(dev, &bnxt_rte_pmd);
5729 RTE_INIT(bnxt_init_log)
5731 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
5732 if (bnxt_logtype_driver >= 0)
5733 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
5736 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5737 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5738 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");