drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_ring.h"
  22 #include "bnxt_rxq.h"
  23 #include "bnxt_rxr.h"
  24 #include "bnxt_stats.h"
  25 #include "bnxt_txq.h"
  26 #include "bnxt_txr.h"
  27 #include "bnxt_vnic.h"
  28 #include "hsi_struct_def_dpdk.h"
  29 #include "bnxt_nvm_defs.h"
  30
  31 #define DRV_MODULE_NAME         "bnxt"
  32 static const char bnxt_version[] =
  33         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  34 int bnxt_logtype_driver;
  35
  36 /*
  37  * The set of PCI devices this driver supports
  38  */
  39 static const struct rte_pci_id bnxt_pci_id_map[] = {
  40         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  41                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  45         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  93         { .vendor_id = 0, /* sentinel */ },
  94 };
  95
  96 #define BNXT_ETH_RSS_SUPPORT (  \
  97         ETH_RSS_IPV4 |          \
  98         ETH_RSS_NONFRAG_IPV4_TCP |      \
  99         ETH_RSS_NONFRAG_IPV4_UDP |      \
 100         ETH_RSS_IPV6 |          \
 101         ETH_RSS_NONFRAG_IPV6_TCP |      \
 102         ETH_RSS_NONFRAG_IPV6_UDP)
 103
 104 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 105                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 106                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 107                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 108                                      DEV_TX_OFFLOAD_TCP_TSO | \
 109                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 110                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 111                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 112                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 113                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 114                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 115                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 116
 117 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 118                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 119                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 120                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 121                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 122                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 123                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 124                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 125                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 126                                      DEV_RX_OFFLOAD_TCP_LRO | \
 127                                      DEV_RX_OFFLOAD_SCATTER | \
 128                                      DEV_RX_OFFLOAD_RSS_HASH)
 129
 130 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
 131 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 132 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
 133 static const char *const bnxt_dev_args[] = {
 134         BNXT_DEVARG_TRUFLOW,
 135         BNXT_DEVARG_FLOW_XSTAT,
 136         BNXT_DEVARG_MAX_NUM_KFLOWS,
 137         NULL
 138 };
 139
 140 /*
 141  * truflow == false to disable the feature
 142  * truflow == true to enable the feature
 143  */
 144 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 145
 146 /*
 147  * flow_xstat == false to disable the feature
 148  * flow_xstat == true to enable the feature
 149  */
 150 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 151
 152 /*
 153  * max_num_kflows must be >= 32
 154  * and must be a power-of-2 supported value
 155  * return: 1 -> invalid
 156  *         0 -> valid
 157  */
 158 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 159 {
 160         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 161                 return 1;
 162         return 0;
 163 }
 164
 165 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 166 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 167 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 168 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 169 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 170 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 171 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 172 static void bnxt_dev_recover(void *arg);
 173 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 174
 175 int is_bnxt_in_error(struct bnxt *bp)
 176 {
 177         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 178                 return -EIO;
 179         if (bp->flags & BNXT_FLAG_FW_RESET)
 180                 return -EBUSY;
 181
 182         return 0;
 183 }
 184
 185 /***********************/
 186
 187 /*
 188  * High level utility functions
 189  */
 190
 191 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 192 {
 193         if (!BNXT_CHIP_THOR(bp))
 194                 return 1;
 195
 196         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 197                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 198                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 199 }
 200
 201 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 202 {
 203         if (!BNXT_CHIP_THOR(bp))
 204                 return HW_HASH_INDEX_SIZE;
 205
 206         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 207 }
 208
 209 static void bnxt_free_pf_info(struct bnxt *bp)
 210 {
 211         rte_free(bp->pf);
 212 }
 213
 214 static void bnxt_free_link_info(struct bnxt *bp)
 215 {
 216         rte_free(bp->link_info);
 217 }
 218
 219 static void bnxt_free_leds_info(struct bnxt *bp)
 220 {
 221         rte_free(bp->leds);
 222         bp->leds = NULL;
 223 }
 224
 225 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 226 {
 227         rte_free(bp->flow_stat);
 228         bp->flow_stat = NULL;
 229 }
 230
 231 static void bnxt_free_cos_queues(struct bnxt *bp)
 232 {
 233         rte_free(bp->rx_cos_queue);
 234         rte_free(bp->tx_cos_queue);
 235 }
 236
 237 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 238 {
 239         bnxt_free_filter_mem(bp);
 240         bnxt_free_vnic_attributes(bp);
 241         bnxt_free_vnic_mem(bp);
 242
 243         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 244          * If the number of rings change across fw update,
 245          * we don't have much choice except to warn the user.
 246          */
 247         if (!reconfig) {
 248                 bnxt_free_stats(bp);
 249                 bnxt_free_tx_rings(bp);
 250                 bnxt_free_rx_rings(bp);
 251         }
 252         bnxt_free_async_cp_ring(bp);
 253         bnxt_free_rxtx_nq_ring(bp);
 254
 255         rte_free(bp->grp_info);
 256         bp->grp_info = NULL;
 257 }
 258
 259 static int bnxt_alloc_pf_info(struct bnxt *bp)
 260 {
 261         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 262         if (bp->pf == NULL)
 263                 return -ENOMEM;
 264
 265         return 0;
 266 }
 267
 268 static int bnxt_alloc_link_info(struct bnxt *bp)
 269 {
 270         bp->link_info =
 271                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 272         if (bp->link_info == NULL)
 273                 return -ENOMEM;
 274
 275         return 0;
 276 }
 277
 278 static int bnxt_alloc_leds_info(struct bnxt *bp)
 279 {
 280         bp->leds = rte_zmalloc("bnxt_leds",
 281                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 282                                0);
 283         if (bp->leds == NULL)
 284                 return -ENOMEM;
 285
 286         return 0;
 287 }
 288
 289 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 290 {
 291         bp->rx_cos_queue =
 292                 rte_zmalloc("bnxt_rx_cosq",
 293                             BNXT_COS_QUEUE_COUNT *
 294                             sizeof(struct bnxt_cos_queue_info),
 295                             0);
 296         if (bp->rx_cos_queue == NULL)
 297                 return -ENOMEM;
 298
 299         bp->tx_cos_queue =
 300                 rte_zmalloc("bnxt_tx_cosq",
 301                             BNXT_COS_QUEUE_COUNT *
 302                             sizeof(struct bnxt_cos_queue_info),
 303                             0);
 304         if (bp->tx_cos_queue == NULL)
 305                 return -ENOMEM;
 306
 307         return 0;
 308 }
 309
 310 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 311 {
 312         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 313                                     sizeof(struct bnxt_flow_stat_info), 0);
 314         if (bp->flow_stat == NULL)
 315                 return -ENOMEM;
 316
 317         return 0;
 318 }
 319
 320 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 321 {
 322         int rc;
 323
 324         rc = bnxt_alloc_ring_grps(bp);
 325         if (rc)
 326                 goto alloc_mem_err;
 327
 328         rc = bnxt_alloc_async_ring_struct(bp);
 329         if (rc)
 330                 goto alloc_mem_err;
 331
 332         rc = bnxt_alloc_vnic_mem(bp);
 333         if (rc)
 334                 goto alloc_mem_err;
 335
 336         rc = bnxt_alloc_vnic_attributes(bp);
 337         if (rc)
 338                 goto alloc_mem_err;
 339
 340         rc = bnxt_alloc_filter_mem(bp);
 341         if (rc)
 342                 goto alloc_mem_err;
 343
 344         rc = bnxt_alloc_async_cp_ring(bp);
 345         if (rc)
 346                 goto alloc_mem_err;
 347
 348         rc = bnxt_alloc_rxtx_nq_ring(bp);
 349         if (rc)
 350                 goto alloc_mem_err;
 351
 352         if (BNXT_FLOW_XSTATS_EN(bp)) {
 353                 rc = bnxt_alloc_flow_stats_info(bp);
 354                 if (rc)
 355                         goto alloc_mem_err;
 356         }
 357
 358         return 0;
 359
 360 alloc_mem_err:
 361         bnxt_free_mem(bp, reconfig);
 362         return rc;
 363 }
 364
 365 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 366 {
 367         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 368         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 369         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 370         struct bnxt_rx_queue *rxq;
 371         unsigned int j;
 372         int rc;
 373
 374         rc = bnxt_vnic_grp_alloc(bp, vnic);
 375         if (rc)
 376                 goto err_out;
 377
 378         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 379                     vnic_id, vnic, vnic->fw_grp_ids);
 380
 381         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 382         if (rc)
 383                 goto err_out;
 384
 385         /* Alloc RSS context only if RSS mode is enabled */
 386         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 387                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 388
 389                 rc = 0;
 390                 for (j = 0; j < nr_ctxs; j++) {
 391                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 392                         if (rc)
 393                                 break;
 394                 }
 395                 if (rc) {
 396                         PMD_DRV_LOG(ERR,
 397                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 398                                     vnic_id, j, rc);
 399                         goto err_out;
 400                 }
 401                 vnic->num_lb_ctxts = nr_ctxs;
 402         }
 403
 404         /*
 405          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 406          * setting is not available at this time, it will not be
 407          * configured correctly in the CFA.
 408          */
 409         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 410                 vnic->vlan_strip = true;
 411         else
 412                 vnic->vlan_strip = false;
 413
 414         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 415         if (rc)
 416                 goto err_out;
 417
 418         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 419         if (rc)
 420                 goto err_out;
 421
 422         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 423                 rxq = bp->eth_dev->data->rx_queues[j];
 424
 425                 PMD_DRV_LOG(DEBUG,
 426                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 427                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 428
 429                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 430                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 431                 else
 432                         vnic->rx_queue_cnt++;
 433         }
 434
 435         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 436
 437         rc = bnxt_vnic_rss_configure(bp, vnic);
 438         if (rc)
 439                 goto err_out;
 440
 441         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 442
 443         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 444                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 445         else
 446                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 447
 448         return 0;
 449 err_out:
 450         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 451                     vnic_id, rc);
 452         return rc;
 453 }
 454
 455 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 456 {
 457         int rc = 0;
 458
 459         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 460                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 461         if (rc)
 462                 return rc;
 463
 464         PMD_DRV_LOG(DEBUG,
 465                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 466                     " rx_fc_in_tbl.ctx_id = %d\n",
 467                     bp->flow_stat->rx_fc_in_tbl.va,
 468                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 469                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 470
 471         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 472                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 473         if (rc)
 474                 return rc;
 475
 476         PMD_DRV_LOG(DEBUG,
 477                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 478                     " rx_fc_out_tbl.ctx_id = %d\n",
 479                     bp->flow_stat->rx_fc_out_tbl.va,
 480                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 481                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 482
 483         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 484                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 485         if (rc)
 486                 return rc;
 487
 488         PMD_DRV_LOG(DEBUG,
 489                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 490                     " tx_fc_in_tbl.ctx_id = %d\n",
 491                     bp->flow_stat->tx_fc_in_tbl.va,
 492                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 493                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 494
 495         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 496                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 497         if (rc)
 498                 return rc;
 499
 500         PMD_DRV_LOG(DEBUG,
 501                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 502                     " tx_fc_out_tbl.ctx_id = %d\n",
 503                     bp->flow_stat->tx_fc_out_tbl.va,
 504                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 505                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 506
 507         memset(bp->flow_stat->rx_fc_out_tbl.va,
 508                0,
 509                bp->flow_stat->rx_fc_out_tbl.size);
 510         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 511                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 512                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 513                                        bp->flow_stat->max_fc,
 514                                        true);
 515         if (rc)
 516                 return rc;
 517
 518         memset(bp->flow_stat->tx_fc_out_tbl.va,
 519                0,
 520                bp->flow_stat->tx_fc_out_tbl.size);
 521         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 522                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 523                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 524                                        bp->flow_stat->max_fc,
 525                                        true);
 526
 527         return rc;
 528 }
 529
 530 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 531                                   struct bnxt_ctx_mem_buf_info *ctx)
 532 {
 533         if (!ctx)
 534                 return -EINVAL;
 535
 536         ctx->va = rte_zmalloc(type, size, 0);
 537         if (ctx->va == NULL)
 538                 return -ENOMEM;
 539         rte_mem_lock_page(ctx->va);
 540         ctx->size = size;
 541         ctx->dma = rte_mem_virt2iova(ctx->va);
 542         if (ctx->dma == RTE_BAD_IOVA)
 543                 return -ENOMEM;
 544
 545         return 0;
 546 }
 547
 548 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 549 {
 550         struct rte_pci_device *pdev = bp->pdev;
 551         char type[RTE_MEMZONE_NAMESIZE];
 552         uint16_t max_fc;
 553         int rc = 0;
 554
 555         max_fc = bp->flow_stat->max_fc;
 556
 557         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 558                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 559         /* 4 bytes for each counter-id */
 560         rc = bnxt_alloc_ctx_mem_buf(type,
 561                                     max_fc * 4,
 562                                     &bp->flow_stat->rx_fc_in_tbl);
 563         if (rc)
 564                 return rc;
 565
 566         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 567                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 568         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 569         rc = bnxt_alloc_ctx_mem_buf(type,
 570                                     max_fc * 16,
 571                                     &bp->flow_stat->rx_fc_out_tbl);
 572         if (rc)
 573                 return rc;
 574
 575         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 576                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 577         /* 4 bytes for each counter-id */
 578         rc = bnxt_alloc_ctx_mem_buf(type,
 579                                     max_fc * 4,
 580                                     &bp->flow_stat->tx_fc_in_tbl);
 581         if (rc)
 582                 return rc;
 583
 584         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 585                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 586         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 587         rc = bnxt_alloc_ctx_mem_buf(type,
 588                                     max_fc * 16,
 589                                     &bp->flow_stat->tx_fc_out_tbl);
 590         if (rc)
 591                 return rc;
 592
 593         rc = bnxt_register_fc_ctx_mem(bp);
 594
 595         return rc;
 596 }
 597
 598 static int bnxt_init_ctx_mem(struct bnxt *bp)
 599 {
 600         int rc = 0;
 601
 602         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 603             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 604             !BNXT_FLOW_XSTATS_EN(bp))
 605                 return 0;
 606
 607         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 608         if (rc)
 609                 return rc;
 610
 611         rc = bnxt_init_fc_ctx_mem(bp);
 612
 613         return rc;
 614 }
 615
 616 static int bnxt_init_chip(struct bnxt *bp)
 617 {
 618         struct rte_eth_link new;
 619         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 620         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 621         uint32_t intr_vector = 0;
 622         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 623         uint32_t vec = BNXT_MISC_VEC_ID;
 624         unsigned int i, j;
 625         int rc;
 626
 627         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 628                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 629                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 630                 bp->flags |= BNXT_FLAG_JUMBO;
 631         } else {
 632                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 633                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 634                 bp->flags &= ~BNXT_FLAG_JUMBO;
 635         }
 636
 637         /* THOR does not support ring groups.
 638          * But we will use the array to save RSS context IDs.
 639          */
 640         if (BNXT_CHIP_THOR(bp))
 641                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 642
 643         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 644         if (rc) {
 645                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 646                 goto err_out;
 647         }
 648
 649         rc = bnxt_alloc_hwrm_rings(bp);
 650         if (rc) {
 651                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 652                 goto err_out;
 653         }
 654
 655         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 656         if (rc) {
 657                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 658                 goto err_out;
 659         }
 660
 661         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 662                 goto skip_cosq_cfg;
 663
 664         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 665                 if (bp->rx_cos_queue[i].id != 0xff) {
 666                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 667
 668                         if (!vnic) {
 669                                 PMD_DRV_LOG(ERR,
 670                                             "Num pools more than FW profile\n");
 671                                 rc = -EINVAL;
 672                                 goto err_out;
 673                         }
 674                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 675                         bp->rx_cosq_cnt++;
 676                 }
 677         }
 678
 679 skip_cosq_cfg:
 680         rc = bnxt_mq_rx_configure(bp);
 681         if (rc) {
 682                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 683                 goto err_out;
 684         }
 685
 686         /* VNIC configuration */
 687         for (i = 0; i < bp->nr_vnics; i++) {
 688                 rc = bnxt_setup_one_vnic(bp, i);
 689                 if (rc)
 690                         goto err_out;
 691         }
 692
 693         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 694         if (rc) {
 695                 PMD_DRV_LOG(ERR,
 696                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 697                 goto err_out;
 698         }
 699
 700         /* check and configure queue intr-vector mapping */
 701         if ((rte_intr_cap_multiple(intr_handle) ||
 702              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 703             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 704                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 705                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 706                 if (intr_vector > bp->rx_cp_nr_rings) {
 707                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 708                                         bp->rx_cp_nr_rings);
 709                         return -ENOTSUP;
 710                 }
 711                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 712                 if (rc)
 713                         return rc;
 714         }
 715
 716         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 717                 intr_handle->intr_vec =
 718                         rte_zmalloc("intr_vec",
 719                                     bp->eth_dev->data->nb_rx_queues *
 720                                     sizeof(int), 0);
 721                 if (intr_handle->intr_vec == NULL) {
 722                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 723                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 724                         rc = -ENOMEM;
 725                         goto err_disable;
 726                 }
 727                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 728                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 729                          intr_handle->intr_vec, intr_handle->nb_efd,
 730                         intr_handle->max_intr);
 731                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 732                      queue_id++) {
 733                         intr_handle->intr_vec[queue_id] =
 734                                                         vec + BNXT_RX_VEC_START;
 735                         if (vec < base + intr_handle->nb_efd - 1)
 736                                 vec++;
 737                 }
 738         }
 739
 740         /* enable uio/vfio intr/eventfd mapping */
 741         rc = rte_intr_enable(intr_handle);
 742 #ifndef RTE_EXEC_ENV_FREEBSD
 743         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 744         if (rc)
 745                 goto err_free;
 746 #endif
 747
 748         rc = bnxt_get_hwrm_link_config(bp, &new);
 749         if (rc) {
 750                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 751                 goto err_free;
 752         }
 753
 754         if (!bp->link_info->link_up) {
 755                 rc = bnxt_set_hwrm_link_config(bp, true);
 756                 if (rc) {
 757                         PMD_DRV_LOG(ERR,
 758                                 "HWRM link config failure rc: %x\n", rc);
 759                         goto err_free;
 760                 }
 761         }
 762         bnxt_print_link_info(bp->eth_dev);
 763
 764         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 765         if (!bp->mark_table)
 766                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 767
 768         return 0;
 769
 770 err_free:
 771         rte_free(intr_handle->intr_vec);
 772 err_disable:
 773         rte_intr_efd_disable(intr_handle);
 774 err_out:
 775         /* Some of the error status returned by FW may not be from errno.h */
 776         if (rc > 0)
 777                 rc = -EIO;
 778
 779         return rc;
 780 }
 781
 782 static int bnxt_shutdown_nic(struct bnxt *bp)
 783 {
 784         bnxt_free_all_hwrm_resources(bp);
 785         bnxt_free_all_filters(bp);
 786         bnxt_free_all_vnics(bp);
 787         return 0;
 788 }
 789
 790 /*
 791  * Device configuration and status function
 792  */
 793
 794 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 795 {
 796         uint32_t link_speed = bp->link_info->support_speeds;
 797         uint32_t speed_capa = 0;
 798
 799         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 800                 speed_capa |= ETH_LINK_SPEED_100M;
 801         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 802                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 803         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 804                 speed_capa |= ETH_LINK_SPEED_1G;
 805         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 806                 speed_capa |= ETH_LINK_SPEED_2_5G;
 807         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 808                 speed_capa |= ETH_LINK_SPEED_10G;
 809         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 810                 speed_capa |= ETH_LINK_SPEED_20G;
 811         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 812                 speed_capa |= ETH_LINK_SPEED_25G;
 813         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 814                 speed_capa |= ETH_LINK_SPEED_40G;
 815         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 816                 speed_capa |= ETH_LINK_SPEED_50G;
 817         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 818                 speed_capa |= ETH_LINK_SPEED_100G;
 819         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
 820                 speed_capa |= ETH_LINK_SPEED_200G;
 821
 822         if (bp->link_info->auto_mode ==
 823             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 824                 speed_capa |= ETH_LINK_SPEED_FIXED;
 825         else
 826                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 827
 828         return speed_capa;
 829 }
 830
 831 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 832                                 struct rte_eth_dev_info *dev_info)
 833 {
 834         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 835         struct bnxt *bp = eth_dev->data->dev_private;
 836         uint16_t max_vnics, i, j, vpool, vrxq;
 837         unsigned int max_rx_rings;
 838         int rc;
 839
 840         rc = is_bnxt_in_error(bp);
 841         if (rc)
 842                 return rc;
 843
 844         /* MAC Specifics */
 845         dev_info->max_mac_addrs = bp->max_l2_ctx;
 846         dev_info->max_hash_mac_addrs = 0;
 847
 848         /* PF/VF specifics */
 849         if (BNXT_PF(bp))
 850                 dev_info->max_vfs = pdev->max_vfs;
 851
 852         max_rx_rings = BNXT_MAX_RINGS(bp);
 853         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 854         dev_info->max_rx_queues = max_rx_rings;
 855         dev_info->max_tx_queues = max_rx_rings;
 856         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 857         dev_info->hash_key_size = 40;
 858         max_vnics = bp->max_vnics;
 859
 860         /* MTU specifics */
 861         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 862         dev_info->max_mtu = BNXT_MAX_MTU;
 863
 864         /* Fast path specifics */
 865         dev_info->min_rx_bufsize = 1;
 866         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 867
 868         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 869         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 870                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 871         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 872         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 873
 874         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 875
 876         /* *INDENT-OFF* */
 877         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 878                 .rx_thresh = {
 879                         .pthresh = 8,
 880                         .hthresh = 8,
 881                         .wthresh = 0,
 882                 },
 883                 .rx_free_thresh = 32,
 884                 /* If no descriptors available, pkts are dropped by default */
 885                 .rx_drop_en = 1,
 886         };
 887
 888         dev_info->default_txconf = (struct rte_eth_txconf) {
 889                 .tx_thresh = {
 890                         .pthresh = 32,
 891                         .hthresh = 0,
 892                         .wthresh = 0,
 893                 },
 894                 .tx_free_thresh = 32,
 895                 .tx_rs_thresh = 32,
 896         };
 897         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 898
 899         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 900         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 901         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 902         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 903         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 904
 905         /* *INDENT-ON* */
 906
 907         /*
 908          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 909          *       need further investigation.
 910          */
 911
 912         /* VMDq resources */
 913         vpool = 64; /* ETH_64_POOLS */
 914         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 915         for (i = 0; i < 4; vpool >>= 1, i++) {
 916                 if (max_vnics > vpool) {
 917                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 918                                 if (dev_info->max_rx_queues > vrxq) {
 919                                         if (vpool > vrxq)
 920                                                 vpool = vrxq;
 921                                         goto found;
 922                                 }
 923                         }
 924                         /* Not enough resources to support VMDq */
 925                         break;
 926                 }
 927         }
 928         /* Not enough resources to support VMDq */
 929         vpool = 0;
 930         vrxq = 0;
 931 found:
 932         dev_info->max_vmdq_pools = vpool;
 933         dev_info->vmdq_queue_num = vrxq;
 934
 935         dev_info->vmdq_pool_base = 0;
 936         dev_info->vmdq_queue_base = 0;
 937
 938         return 0;
 939 }
 940
 941 /* Configure the device based on the configuration provided */
 942 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 943 {
 944         struct bnxt *bp = eth_dev->data->dev_private;
 945         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 946         int rc;
 947
 948         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 949         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 950         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 951         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 952
 953         rc = is_bnxt_in_error(bp);
 954         if (rc)
 955                 return rc;
 956
 957         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 958                 rc = bnxt_hwrm_check_vf_rings(bp);
 959                 if (rc) {
 960                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 961                         return -ENOSPC;
 962                 }
 963
 964                 /* If a resource has already been allocated - in this case
 965                  * it is the async completion ring, free it. Reallocate it after
 966                  * resource reservation. This will ensure the resource counts
 967                  * are calculated correctly.
 968                  */
 969
 970                 pthread_mutex_lock(&bp->def_cp_lock);
 971
 972                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 973                         bnxt_disable_int(bp);
 974                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 975                 }
 976
 977                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 978                 if (rc) {
 979                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 980                         pthread_mutex_unlock(&bp->def_cp_lock);
 981                         return -ENOSPC;
 982                 }
 983
 984                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 985                         rc = bnxt_alloc_async_cp_ring(bp);
 986                         if (rc) {
 987                                 pthread_mutex_unlock(&bp->def_cp_lock);
 988                                 return rc;
 989                         }
 990                         bnxt_enable_int(bp);
 991                 }
 992
 993                 pthread_mutex_unlock(&bp->def_cp_lock);
 994         } else {
 995                 /* legacy driver needs to get updated values */
 996                 rc = bnxt_hwrm_func_qcaps(bp);
 997                 if (rc) {
 998                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 999                         return rc;
1000                 }
1001         }
1002
1003         /* Inherit new configurations */
1004         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1005             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1006             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1007                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1008             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1009             bp->max_stat_ctx)
1010                 goto resource_error;
1011
1012         if (BNXT_HAS_RING_GRPS(bp) &&
1013             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1014                 goto resource_error;
1015
1016         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1017             bp->max_vnics < eth_dev->data->nb_rx_queues)
1018                 goto resource_error;
1019
1020         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1021         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1022
1023         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1024                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1025         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1026
1027         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1028                 eth_dev->data->mtu =
1029                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1030                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1031                         BNXT_NUM_VLANS;
1032                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1033         }
1034         return 0;
1035
1036 resource_error:
1037         PMD_DRV_LOG(ERR,
1038                     "Insufficient resources to support requested config\n");
1039         PMD_DRV_LOG(ERR,
1040                     "Num Queues Requested: Tx %d, Rx %d\n",
1041                     eth_dev->data->nb_tx_queues,
1042                     eth_dev->data->nb_rx_queues);
1043         PMD_DRV_LOG(ERR,
1044                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1045                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1046                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1047         return -ENOSPC;
1048 }
1049
1050 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1051 {
1052         struct rte_eth_link *link = &eth_dev->data->dev_link;
1053
1054         if (link->link_status)
1055                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1056                         eth_dev->data->port_id,
1057                         (uint32_t)link->link_speed,
1058                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1059                         ("full-duplex") : ("half-duplex\n"));
1060         else
1061                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1062                         eth_dev->data->port_id);
1063 }
1064
1065 /*
1066  * Determine whether the current configuration requires support for scattered
1067  * receive; return 1 if scattered receive is required and 0 if not.
1068  */
1069 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1070 {
1071         uint16_t buf_size;
1072         int i;
1073
1074         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1075                 return 1;
1076
1077         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1078                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1079
1080                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1081                                       RTE_PKTMBUF_HEADROOM);
1082                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1083                         return 1;
1084         }
1085         return 0;
1086 }
1087
1088 static eth_rx_burst_t
1089 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1090 {
1091         struct bnxt *bp = eth_dev->data->dev_private;
1092
1093 #ifdef RTE_ARCH_X86
1094 #ifndef RTE_LIBRTE_IEEE1588
1095         /*
1096          * Vector mode receive can be enabled only if scatter rx is not
1097          * in use and rx offloads are limited to VLAN stripping and
1098          * CRC stripping.
1099          */
1100         if (!eth_dev->data->scattered_rx &&
1101             !(eth_dev->data->dev_conf.rxmode.offloads &
1102               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1103                 DEV_RX_OFFLOAD_KEEP_CRC |
1104                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1105                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1106                 DEV_RX_OFFLOAD_UDP_CKSUM |
1107                 DEV_RX_OFFLOAD_TCP_CKSUM |
1108                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1109                 DEV_RX_OFFLOAD_RSS_HASH |
1110                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1111             !BNXT_TRUFLOW_EN(bp)) {
1112                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1113                             eth_dev->data->port_id);
1114                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1115                 return bnxt_recv_pkts_vec;
1116         }
1117         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1118                     eth_dev->data->port_id);
1119         PMD_DRV_LOG(INFO,
1120                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1121                     eth_dev->data->port_id,
1122                     eth_dev->data->scattered_rx,
1123                     eth_dev->data->dev_conf.rxmode.offloads);
1124 #endif
1125 #endif
1126         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1127         return bnxt_recv_pkts;
1128 }
1129
1130 static eth_tx_burst_t
1131 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1132 {
1133 #ifdef RTE_ARCH_X86
1134 #ifndef RTE_LIBRTE_IEEE1588
1135         /*
1136          * Vector mode transmit can be enabled only if not using scatter rx
1137          * or tx offloads.
1138          */
1139         if (!eth_dev->data->scattered_rx &&
1140             !eth_dev->data->dev_conf.txmode.offloads) {
1141                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1142                             eth_dev->data->port_id);
1143                 return bnxt_xmit_pkts_vec;
1144         }
1145         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1146                     eth_dev->data->port_id);
1147         PMD_DRV_LOG(INFO,
1148                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1149                     eth_dev->data->port_id,
1150                     eth_dev->data->scattered_rx,
1151                     eth_dev->data->dev_conf.txmode.offloads);
1152 #endif
1153 #endif
1154         return bnxt_xmit_pkts;
1155 }
1156
1157 static int bnxt_handle_if_change_status(struct bnxt *bp)
1158 {
1159         int rc;
1160
1161         /* Since fw has undergone a reset and lost all contexts,
1162          * set fatal flag to not issue hwrm during cleanup
1163          */
1164         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1165         bnxt_uninit_resources(bp, true);
1166
1167         /* clear fatal flag so that re-init happens */
1168         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1169         rc = bnxt_init_resources(bp, true);
1170
1171         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1172
1173         return rc;
1174 }
1175
1176 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1177 {
1178         struct bnxt *bp = eth_dev->data->dev_private;
1179         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1180         int vlan_mask = 0;
1181         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1182
1183         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1184                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1185                 return -EINVAL;
1186         }
1187
1188         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1189                 PMD_DRV_LOG(ERR,
1190                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1191                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1192         }
1193
1194         do {
1195                 rc = bnxt_hwrm_if_change(bp, true);
1196                 if (rc == 0 || rc != -EAGAIN)
1197                         break;
1198
1199                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1200         } while (retry_cnt--);
1201
1202         if (rc)
1203                 return rc;
1204
1205         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1206                 rc = bnxt_handle_if_change_status(bp);
1207                 if (rc)
1208                         return rc;
1209         }
1210
1211         bnxt_enable_int(bp);
1212
1213         rc = bnxt_init_chip(bp);
1214         if (rc)
1215                 goto error;
1216
1217         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1218         eth_dev->data->dev_started = 1;
1219
1220         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1221
1222         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1223                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1224         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1225                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1226         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1227         if (rc)
1228                 goto error;
1229
1230         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1231         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1232
1233         pthread_mutex_lock(&bp->def_cp_lock);
1234         bnxt_schedule_fw_health_check(bp);
1235         pthread_mutex_unlock(&bp->def_cp_lock);
1236
1237         if (BNXT_TRUFLOW_EN(bp))
1238                 bnxt_ulp_init(bp);
1239
1240         return 0;
1241
1242 error:
1243         bnxt_shutdown_nic(bp);
1244         bnxt_free_tx_mbufs(bp);
1245         bnxt_free_rx_mbufs(bp);
1246         bnxt_hwrm_if_change(bp, false);
1247         eth_dev->data->dev_started = 0;
1248         return rc;
1249 }
1250
1251 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1252 {
1253         struct bnxt *bp = eth_dev->data->dev_private;
1254         int rc = 0;
1255
1256         if (!bp->link_info->link_up)
1257                 rc = bnxt_set_hwrm_link_config(bp, true);
1258         if (!rc)
1259                 eth_dev->data->dev_link.link_status = 1;
1260
1261         bnxt_print_link_info(eth_dev);
1262         return rc;
1263 }
1264
1265 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1266 {
1267         struct bnxt *bp = eth_dev->data->dev_private;
1268
1269         eth_dev->data->dev_link.link_status = 0;
1270         bnxt_set_hwrm_link_config(bp, false);
1271         bp->link_info->link_up = 0;
1272
1273         return 0;
1274 }
1275
1276 /* Unload the driver, release resources */
1277 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1278 {
1279         struct bnxt *bp = eth_dev->data->dev_private;
1280         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1281         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1282
1283         if (BNXT_TRUFLOW_EN(bp))
1284                 bnxt_ulp_deinit(bp);
1285
1286         eth_dev->data->dev_started = 0;
1287         /* Prevent crashes when queues are still in use */
1288         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1289         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1290
1291         bnxt_disable_int(bp);
1292
1293         /* disable uio/vfio intr/eventfd mapping */
1294         rte_intr_disable(intr_handle);
1295
1296         bnxt_cancel_fw_health_check(bp);
1297
1298         bnxt_dev_set_link_down_op(eth_dev);
1299
1300         /* Wait for link to be reset and the async notification to process.
1301          * During reset recovery, there is no need to wait and
1302          * VF/NPAR functions do not have privilege to change PHY config.
1303          */
1304         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1305                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1306
1307         /* Clean queue intr-vector mapping */
1308         rte_intr_efd_disable(intr_handle);
1309         if (intr_handle->intr_vec != NULL) {
1310                 rte_free(intr_handle->intr_vec);
1311                 intr_handle->intr_vec = NULL;
1312         }
1313
1314         bnxt_hwrm_port_clr_stats(bp);
1315         bnxt_free_tx_mbufs(bp);
1316         bnxt_free_rx_mbufs(bp);
1317         /* Process any remaining notifications in default completion queue */
1318         bnxt_int_handler(eth_dev);
1319         bnxt_shutdown_nic(bp);
1320         bnxt_hwrm_if_change(bp, false);
1321
1322         rte_free(bp->mark_table);
1323         bp->mark_table = NULL;
1324
1325         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1326         bp->rx_cosq_cnt = 0;
1327         /* All filters are deleted on a port stop. */
1328         if (BNXT_FLOW_XSTATS_EN(bp))
1329                 bp->flow_stat->flow_count = 0;
1330 }
1331
1332 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1333 {
1334         struct bnxt *bp = eth_dev->data->dev_private;
1335
1336         /* cancel the recovery handler before remove dev */
1337         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1338         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1339         bnxt_cancel_fc_thread(bp);
1340
1341         if (eth_dev->data->dev_started)
1342                 bnxt_dev_stop_op(eth_dev);
1343
1344         bnxt_uninit_resources(bp, false);
1345
1346         bnxt_free_leds_info(bp);
1347         bnxt_free_cos_queues(bp);
1348         bnxt_free_link_info(bp);
1349         bnxt_free_pf_info(bp);
1350
1351         eth_dev->dev_ops = NULL;
1352         eth_dev->rx_pkt_burst = NULL;
1353         eth_dev->tx_pkt_burst = NULL;
1354
1355         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1356         bp->tx_mem_zone = NULL;
1357         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1358         bp->rx_mem_zone = NULL;
1359
1360         rte_free(bp->pf->vf_info);
1361         bp->pf->vf_info = NULL;
1362
1363         rte_free(bp->grp_info);
1364         bp->grp_info = NULL;
1365 }
1366
1367 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1368                                     uint32_t index)
1369 {
1370         struct bnxt *bp = eth_dev->data->dev_private;
1371         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1372         struct bnxt_vnic_info *vnic;
1373         struct bnxt_filter_info *filter, *temp_filter;
1374         uint32_t i;
1375
1376         if (is_bnxt_in_error(bp))
1377                 return;
1378
1379         /*
1380          * Loop through all VNICs from the specified filter flow pools to
1381          * remove the corresponding MAC addr filter
1382          */
1383         for (i = 0; i < bp->nr_vnics; i++) {
1384                 if (!(pool_mask & (1ULL << i)))
1385                         continue;
1386
1387                 vnic = &bp->vnic_info[i];
1388                 filter = STAILQ_FIRST(&vnic->filter);
1389                 while (filter) {
1390                         temp_filter = STAILQ_NEXT(filter, next);
1391                         if (filter->mac_index == index) {
1392                                 STAILQ_REMOVE(&vnic->filter, filter,
1393                                                 bnxt_filter_info, next);
1394                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1395                                 bnxt_free_filter(bp, filter);
1396                         }
1397                         filter = temp_filter;
1398                 }
1399         }
1400 }
1401
1402 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1403                                struct rte_ether_addr *mac_addr, uint32_t index,
1404                                uint32_t pool)
1405 {
1406         struct bnxt_filter_info *filter;
1407         int rc = 0;
1408
1409         /* Attach requested MAC address to the new l2_filter */
1410         STAILQ_FOREACH(filter, &vnic->filter, next) {
1411                 if (filter->mac_index == index) {
1412                         PMD_DRV_LOG(DEBUG,
1413                                     "MAC addr already existed for pool %d\n",
1414                                     pool);
1415                         return 0;
1416                 }
1417         }
1418
1419         filter = bnxt_alloc_filter(bp);
1420         if (!filter) {
1421                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1422                 return -ENODEV;
1423         }
1424
1425         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1426          * if the MAC that's been programmed now is a different one, then,
1427          * copy that addr to filter->l2_addr
1428          */
1429         if (mac_addr)
1430                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1431         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1432
1433         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1434         if (!rc) {
1435                 filter->mac_index = index;
1436                 if (filter->mac_index == 0)
1437                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1438                 else
1439                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1440         } else {
1441                 bnxt_free_filter(bp, filter);
1442         }
1443
1444         return rc;
1445 }
1446
1447 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1448                                 struct rte_ether_addr *mac_addr,
1449                                 uint32_t index, uint32_t pool)
1450 {
1451         struct bnxt *bp = eth_dev->data->dev_private;
1452         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1453         int rc = 0;
1454
1455         rc = is_bnxt_in_error(bp);
1456         if (rc)
1457                 return rc;
1458
1459         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1460                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1461                 return -ENOTSUP;
1462         }
1463
1464         if (!vnic) {
1465                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1466                 return -EINVAL;
1467         }
1468
1469         /* Filter settings will get applied when port is started */
1470         if (!eth_dev->data->dev_started)
1471                 return 0;
1472
1473         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1474
1475         return rc;
1476 }
1477
1478 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1479                      bool exp_link_status)
1480 {
1481         int rc = 0;
1482         struct bnxt *bp = eth_dev->data->dev_private;
1483         struct rte_eth_link new;
1484         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1485                   BNXT_LINK_DOWN_WAIT_CNT;
1486
1487         rc = is_bnxt_in_error(bp);
1488         if (rc)
1489                 return rc;
1490
1491         memset(&new, 0, sizeof(new));
1492         do {
1493                 /* Retrieve link info from hardware */
1494                 rc = bnxt_get_hwrm_link_config(bp, &new);
1495                 if (rc) {
1496                         new.link_speed = ETH_LINK_SPEED_100M;
1497                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1498                         PMD_DRV_LOG(ERR,
1499                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1500                         goto out;
1501                 }
1502
1503                 if (!wait_to_complete || new.link_status == exp_link_status)
1504                         break;
1505
1506                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1507         } while (cnt--);
1508
1509 out:
1510         /* Timed out or success */
1511         if (new.link_status != eth_dev->data->dev_link.link_status ||
1512         new.link_speed != eth_dev->data->dev_link.link_speed) {
1513                 rte_eth_linkstatus_set(eth_dev, &new);
1514
1515                 _rte_eth_dev_callback_process(eth_dev,
1516                                               RTE_ETH_EVENT_INTR_LSC,
1517                                               NULL);
1518
1519                 bnxt_print_link_info(eth_dev);
1520         }
1521
1522         return rc;
1523 }
1524
1525 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1526                                int wait_to_complete)
1527 {
1528         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1529 }
1530
1531 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1532 {
1533         struct bnxt *bp = eth_dev->data->dev_private;
1534         struct bnxt_vnic_info *vnic;
1535         uint32_t old_flags;
1536         int rc;
1537
1538         rc = is_bnxt_in_error(bp);
1539         if (rc)
1540                 return rc;
1541
1542         /* Filter settings will get applied when port is started */
1543         if (!eth_dev->data->dev_started)
1544                 return 0;
1545
1546         if (bp->vnic_info == NULL)
1547                 return 0;
1548
1549         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1550
1551         old_flags = vnic->flags;
1552         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1553         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1554         if (rc != 0)
1555                 vnic->flags = old_flags;
1556
1557         return rc;
1558 }
1559
1560 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1561 {
1562         struct bnxt *bp = eth_dev->data->dev_private;
1563         struct bnxt_vnic_info *vnic;
1564         uint32_t old_flags;
1565         int rc;
1566
1567         rc = is_bnxt_in_error(bp);
1568         if (rc)
1569                 return rc;
1570
1571         /* Filter settings will get applied when port is started */
1572         if (!eth_dev->data->dev_started)
1573                 return 0;
1574
1575         if (bp->vnic_info == NULL)
1576                 return 0;
1577
1578         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1579
1580         old_flags = vnic->flags;
1581         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1582         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1583         if (rc != 0)
1584                 vnic->flags = old_flags;
1585
1586         return rc;
1587 }
1588
1589 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1590 {
1591         struct bnxt *bp = eth_dev->data->dev_private;
1592         struct bnxt_vnic_info *vnic;
1593         uint32_t old_flags;
1594         int rc;
1595
1596         rc = is_bnxt_in_error(bp);
1597         if (rc)
1598                 return rc;
1599
1600         /* Filter settings will get applied when port is started */
1601         if (!eth_dev->data->dev_started)
1602                 return 0;
1603
1604         if (bp->vnic_info == NULL)
1605                 return 0;
1606
1607         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1608
1609         old_flags = vnic->flags;
1610         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1611         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1612         if (rc != 0)
1613                 vnic->flags = old_flags;
1614
1615         return rc;
1616 }
1617
1618 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1619 {
1620         struct bnxt *bp = eth_dev->data->dev_private;
1621         struct bnxt_vnic_info *vnic;
1622         uint32_t old_flags;
1623         int rc;
1624
1625         rc = is_bnxt_in_error(bp);
1626         if (rc)
1627                 return rc;
1628
1629         /* Filter settings will get applied when port is started */
1630         if (!eth_dev->data->dev_started)
1631                 return 0;
1632
1633         if (bp->vnic_info == NULL)
1634                 return 0;
1635
1636         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1637
1638         old_flags = vnic->flags;
1639         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1640         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1641         if (rc != 0)
1642                 vnic->flags = old_flags;
1643
1644         return rc;
1645 }
1646
1647 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1648 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1649 {
1650         if (qid >= bp->rx_nr_rings)
1651                 return NULL;
1652
1653         return bp->eth_dev->data->rx_queues[qid];
1654 }
1655
1656 /* Return rxq corresponding to a given rss table ring/group ID. */
1657 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1658 {
1659         struct bnxt_rx_queue *rxq;
1660         unsigned int i;
1661
1662         if (!BNXT_HAS_RING_GRPS(bp)) {
1663                 for (i = 0; i < bp->rx_nr_rings; i++) {
1664                         rxq = bp->eth_dev->data->rx_queues[i];
1665                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1666                                 return rxq->index;
1667                 }
1668         } else {
1669                 for (i = 0; i < bp->rx_nr_rings; i++) {
1670                         if (bp->grp_info[i].fw_grp_id == fwr)
1671                                 return i;
1672                 }
1673         }
1674
1675         return INVALID_HW_RING_ID;
1676 }
1677
1678 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1679                             struct rte_eth_rss_reta_entry64 *reta_conf,
1680                             uint16_t reta_size)
1681 {
1682         struct bnxt *bp = eth_dev->data->dev_private;
1683         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1684         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1685         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1686         uint16_t idx, sft;
1687         int i, rc;
1688
1689         rc = is_bnxt_in_error(bp);
1690         if (rc)
1691                 return rc;
1692
1693         if (!vnic->rss_table)
1694                 return -EINVAL;
1695
1696         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1697                 return -EINVAL;
1698
1699         if (reta_size != tbl_size) {
1700                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1701                         "(%d) must equal the size supported by the hardware "
1702                         "(%d)\n", reta_size, tbl_size);
1703                 return -EINVAL;
1704         }
1705
1706         for (i = 0; i < reta_size; i++) {
1707                 struct bnxt_rx_queue *rxq;
1708
1709                 idx = i / RTE_RETA_GROUP_SIZE;
1710                 sft = i % RTE_RETA_GROUP_SIZE;
1711
1712                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1713                         continue;
1714
1715                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1716                 if (!rxq) {
1717                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1718                         return -EINVAL;
1719                 }
1720
1721                 if (BNXT_CHIP_THOR(bp)) {
1722                         vnic->rss_table[i * 2] =
1723                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1724                         vnic->rss_table[i * 2 + 1] =
1725                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1726                 } else {
1727                         vnic->rss_table[i] =
1728                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1729                 }
1730         }
1731
1732         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1733         return 0;
1734 }
1735
1736 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1737                               struct rte_eth_rss_reta_entry64 *reta_conf,
1738                               uint16_t reta_size)
1739 {
1740         struct bnxt *bp = eth_dev->data->dev_private;
1741         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1742         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1743         uint16_t idx, sft, i;
1744         int rc;
1745
1746         rc = is_bnxt_in_error(bp);
1747         if (rc)
1748                 return rc;
1749
1750         /* Retrieve from the default VNIC */
1751         if (!vnic)
1752                 return -EINVAL;
1753         if (!vnic->rss_table)
1754                 return -EINVAL;
1755
1756         if (reta_size != tbl_size) {
1757                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1758                         "(%d) must equal the size supported by the hardware "
1759                         "(%d)\n", reta_size, tbl_size);
1760                 return -EINVAL;
1761         }
1762
1763         for (idx = 0, i = 0; i < reta_size; i++) {
1764                 idx = i / RTE_RETA_GROUP_SIZE;
1765                 sft = i % RTE_RETA_GROUP_SIZE;
1766
1767                 if (reta_conf[idx].mask & (1ULL << sft)) {
1768                         uint16_t qid;
1769
1770                         if (BNXT_CHIP_THOR(bp))
1771                                 qid = bnxt_rss_to_qid(bp,
1772                                                       vnic->rss_table[i * 2]);
1773                         else
1774                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1775
1776                         if (qid == INVALID_HW_RING_ID) {
1777                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1778                                 return -EINVAL;
1779                         }
1780                         reta_conf[idx].reta[sft] = qid;
1781                 }
1782         }
1783
1784         return 0;
1785 }
1786
1787 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1788                                    struct rte_eth_rss_conf *rss_conf)
1789 {
1790         struct bnxt *bp = eth_dev->data->dev_private;
1791         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1792         struct bnxt_vnic_info *vnic;
1793         int rc;
1794
1795         rc = is_bnxt_in_error(bp);
1796         if (rc)
1797                 return rc;
1798
1799         /*
1800          * If RSS enablement were different than dev_configure,
1801          * then return -EINVAL
1802          */
1803         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1804                 if (!rss_conf->rss_hf)
1805                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1806         } else {
1807                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1808                         return -EINVAL;
1809         }
1810
1811         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1812         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1813                rss_conf,
1814                sizeof(*rss_conf));
1815
1816         /* Update the default RSS VNIC(s) */
1817         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1818         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1819
1820         /*
1821          * If hashkey is not specified, use the previously configured
1822          * hashkey
1823          */
1824         if (!rss_conf->rss_key)
1825                 goto rss_config;
1826
1827         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1828                 PMD_DRV_LOG(ERR,
1829                             "Invalid hashkey length, should be 16 bytes\n");
1830                 return -EINVAL;
1831         }
1832         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1833
1834 rss_config:
1835         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1836         return 0;
1837 }
1838
1839 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1840                                      struct rte_eth_rss_conf *rss_conf)
1841 {
1842         struct bnxt *bp = eth_dev->data->dev_private;
1843         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1844         int len, rc;
1845         uint32_t hash_types;
1846
1847         rc = is_bnxt_in_error(bp);
1848         if (rc)
1849                 return rc;
1850
1851         /* RSS configuration is the same for all VNICs */
1852         if (vnic && vnic->rss_hash_key) {
1853                 if (rss_conf->rss_key) {
1854                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1855                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1856                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1857                 }
1858
1859                 hash_types = vnic->hash_type;
1860                 rss_conf->rss_hf = 0;
1861                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1862                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1863                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1864                 }
1865                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1866                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1867                         hash_types &=
1868                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1869                 }
1870                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1871                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1872                         hash_types &=
1873                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1874                 }
1875                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1876                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1877                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1878                 }
1879                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1880                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1881                         hash_types &=
1882                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1883                 }
1884                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1885                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1886                         hash_types &=
1887                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1888                 }
1889                 if (hash_types) {
1890                         PMD_DRV_LOG(ERR,
1891                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1892                                 vnic->hash_type);
1893                         return -ENOTSUP;
1894                 }
1895         } else {
1896                 rss_conf->rss_hf = 0;
1897         }
1898         return 0;
1899 }
1900
1901 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1902                                struct rte_eth_fc_conf *fc_conf)
1903 {
1904         struct bnxt *bp = dev->data->dev_private;
1905         struct rte_eth_link link_info;
1906         int rc;
1907
1908         rc = is_bnxt_in_error(bp);
1909         if (rc)
1910                 return rc;
1911
1912         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1913         if (rc)
1914                 return rc;
1915
1916         memset(fc_conf, 0, sizeof(*fc_conf));
1917         if (bp->link_info->auto_pause)
1918                 fc_conf->autoneg = 1;
1919         switch (bp->link_info->pause) {
1920         case 0:
1921                 fc_conf->mode = RTE_FC_NONE;
1922                 break;
1923         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1924                 fc_conf->mode = RTE_FC_TX_PAUSE;
1925                 break;
1926         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1927                 fc_conf->mode = RTE_FC_RX_PAUSE;
1928                 break;
1929         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1930                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1931                 fc_conf->mode = RTE_FC_FULL;
1932                 break;
1933         }
1934         return 0;
1935 }
1936
1937 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1938                                struct rte_eth_fc_conf *fc_conf)
1939 {
1940         struct bnxt *bp = dev->data->dev_private;
1941         int rc;
1942
1943         rc = is_bnxt_in_error(bp);
1944         if (rc)
1945                 return rc;
1946
1947         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1948                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1949                 return -ENOTSUP;
1950         }
1951
1952         switch (fc_conf->mode) {
1953         case RTE_FC_NONE:
1954                 bp->link_info->auto_pause = 0;
1955                 bp->link_info->force_pause = 0;
1956                 break;
1957         case RTE_FC_RX_PAUSE:
1958                 if (fc_conf->autoneg) {
1959                         bp->link_info->auto_pause =
1960                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1961                         bp->link_info->force_pause = 0;
1962                 } else {
1963                         bp->link_info->auto_pause = 0;
1964                         bp->link_info->force_pause =
1965                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1966                 }
1967                 break;
1968         case RTE_FC_TX_PAUSE:
1969                 if (fc_conf->autoneg) {
1970                         bp->link_info->auto_pause =
1971                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1972                         bp->link_info->force_pause = 0;
1973                 } else {
1974                         bp->link_info->auto_pause = 0;
1975                         bp->link_info->force_pause =
1976                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1977                 }
1978                 break;
1979         case RTE_FC_FULL:
1980                 if (fc_conf->autoneg) {
1981                         bp->link_info->auto_pause =
1982                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1983                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1984                         bp->link_info->force_pause = 0;
1985                 } else {
1986                         bp->link_info->auto_pause = 0;
1987                         bp->link_info->force_pause =
1988                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1989                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1990                 }
1991                 break;
1992         }
1993         return bnxt_set_hwrm_link_config(bp, true);
1994 }
1995
1996 /* Add UDP tunneling port */
1997 static int
1998 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1999                          struct rte_eth_udp_tunnel *udp_tunnel)
2000 {
2001         struct bnxt *bp = eth_dev->data->dev_private;
2002         uint16_t tunnel_type = 0;
2003         int rc = 0;
2004
2005         rc = is_bnxt_in_error(bp);
2006         if (rc)
2007                 return rc;
2008
2009         switch (udp_tunnel->prot_type) {
2010         case RTE_TUNNEL_TYPE_VXLAN:
2011                 if (bp->vxlan_port_cnt) {
2012                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2013                                 udp_tunnel->udp_port);
2014                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2015                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2016                                 return -ENOSPC;
2017                         }
2018                         bp->vxlan_port_cnt++;
2019                         return 0;
2020                 }
2021                 tunnel_type =
2022                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2023                 bp->vxlan_port_cnt++;
2024                 break;
2025         case RTE_TUNNEL_TYPE_GENEVE:
2026                 if (bp->geneve_port_cnt) {
2027                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2028                                 udp_tunnel->udp_port);
2029                         if (bp->geneve_port != udp_tunnel->udp_port) {
2030                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2031                                 return -ENOSPC;
2032                         }
2033                         bp->geneve_port_cnt++;
2034                         return 0;
2035                 }
2036                 tunnel_type =
2037                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2038                 bp->geneve_port_cnt++;
2039                 break;
2040         default:
2041                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2042                 return -ENOTSUP;
2043         }
2044         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2045                                              tunnel_type);
2046         return rc;
2047 }
2048
2049 static int
2050 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2051                          struct rte_eth_udp_tunnel *udp_tunnel)
2052 {
2053         struct bnxt *bp = eth_dev->data->dev_private;
2054         uint16_t tunnel_type = 0;
2055         uint16_t port = 0;
2056         int rc = 0;
2057
2058         rc = is_bnxt_in_error(bp);
2059         if (rc)
2060                 return rc;
2061
2062         switch (udp_tunnel->prot_type) {
2063         case RTE_TUNNEL_TYPE_VXLAN:
2064                 if (!bp->vxlan_port_cnt) {
2065                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2066                         return -EINVAL;
2067                 }
2068                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2069                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2070                                 udp_tunnel->udp_port, bp->vxlan_port);
2071                         return -EINVAL;
2072                 }
2073                 if (--bp->vxlan_port_cnt)
2074                         return 0;
2075
2076                 tunnel_type =
2077                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2078                 port = bp->vxlan_fw_dst_port_id;
2079                 break;
2080         case RTE_TUNNEL_TYPE_GENEVE:
2081                 if (!bp->geneve_port_cnt) {
2082                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2083                         return -EINVAL;
2084                 }
2085                 if (bp->geneve_port != udp_tunnel->udp_port) {
2086                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2087                                 udp_tunnel->udp_port, bp->geneve_port);
2088                         return -EINVAL;
2089                 }
2090                 if (--bp->geneve_port_cnt)
2091                         return 0;
2092
2093                 tunnel_type =
2094                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2095                 port = bp->geneve_fw_dst_port_id;
2096                 break;
2097         default:
2098                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2099                 return -ENOTSUP;
2100         }
2101
2102         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2103         if (!rc) {
2104                 if (tunnel_type ==
2105                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2106                         bp->vxlan_port = 0;
2107                 if (tunnel_type ==
2108                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2109                         bp->geneve_port = 0;
2110         }
2111         return rc;
2112 }
2113
2114 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2115 {
2116         struct bnxt_filter_info *filter;
2117         struct bnxt_vnic_info *vnic;
2118         int rc = 0;
2119         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2120
2121         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2122         filter = STAILQ_FIRST(&vnic->filter);
2123         while (filter) {
2124                 /* Search for this matching MAC+VLAN filter */
2125                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2126                         /* Delete the filter */
2127                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2128                         if (rc)
2129                                 return rc;
2130                         STAILQ_REMOVE(&vnic->filter, filter,
2131                                       bnxt_filter_info, next);
2132                         bnxt_free_filter(bp, filter);
2133                         PMD_DRV_LOG(INFO,
2134                                     "Deleted vlan filter for %d\n",
2135                                     vlan_id);
2136                         return 0;
2137                 }
2138                 filter = STAILQ_NEXT(filter, next);
2139         }
2140         return -ENOENT;
2141 }
2142
2143 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2144 {
2145         struct bnxt_filter_info *filter;
2146         struct bnxt_vnic_info *vnic;
2147         int rc = 0;
2148         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2149                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2150         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2151
2152         /* Implementation notes on the use of VNIC in this command:
2153          *
2154          * By default, these filters belong to default vnic for the function.
2155          * Once these filters are set up, only destination VNIC can be modified.
2156          * If the destination VNIC is not specified in this command,
2157          * then the HWRM shall only create an l2 context id.
2158          */
2159
2160         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2161         filter = STAILQ_FIRST(&vnic->filter);
2162         /* Check if the VLAN has already been added */
2163         while (filter) {
2164                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2165                         return -EEXIST;
2166
2167                 filter = STAILQ_NEXT(filter, next);
2168         }
2169
2170         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2171          * command to create MAC+VLAN filter with the right flags, enables set.
2172          */
2173         filter = bnxt_alloc_filter(bp);
2174         if (!filter) {
2175                 PMD_DRV_LOG(ERR,
2176                             "MAC/VLAN filter alloc failed\n");
2177                 return -ENOMEM;
2178         }
2179         /* MAC + VLAN ID filter */
2180         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2181          * untagged packets are received
2182          *
2183          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2184          * packets and only the programmed vlan's packets are received
2185          */
2186         filter->l2_ivlan = vlan_id;
2187         filter->l2_ivlan_mask = 0x0FFF;
2188         filter->enables |= en;
2189         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2190
2191         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2192         if (rc) {
2193                 /* Free the newly allocated filter as we were
2194                  * not able to create the filter in hardware.
2195                  */
2196                 bnxt_free_filter(bp, filter);
2197                 return rc;
2198         }
2199
2200         filter->mac_index = 0;
2201         /* Add this new filter to the list */
2202         if (vlan_id == 0)
2203                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2204         else
2205                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2206
2207         PMD_DRV_LOG(INFO,
2208                     "Added Vlan filter for %d\n", vlan_id);
2209         return rc;
2210 }
2211
2212 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2213                 uint16_t vlan_id, int on)
2214 {
2215         struct bnxt *bp = eth_dev->data->dev_private;
2216         int rc;
2217
2218         rc = is_bnxt_in_error(bp);
2219         if (rc)
2220                 return rc;
2221
2222         if (!eth_dev->data->dev_started) {
2223                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2224                 return -EINVAL;
2225         }
2226
2227         /* These operations apply to ALL existing MAC/VLAN filters */
2228         if (on)
2229                 return bnxt_add_vlan_filter(bp, vlan_id);
2230         else
2231                 return bnxt_del_vlan_filter(bp, vlan_id);
2232 }
2233
2234 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2235                                     struct bnxt_vnic_info *vnic)
2236 {
2237         struct bnxt_filter_info *filter;
2238         int rc;
2239
2240         filter = STAILQ_FIRST(&vnic->filter);
2241         while (filter) {
2242                 if (filter->mac_index == 0 &&
2243                     !memcmp(filter->l2_addr, bp->mac_addr,
2244                             RTE_ETHER_ADDR_LEN)) {
2245                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2246                         if (!rc) {
2247                                 STAILQ_REMOVE(&vnic->filter, filter,
2248                                               bnxt_filter_info, next);
2249                                 bnxt_free_filter(bp, filter);
2250                         }
2251                         return rc;
2252                 }
2253                 filter = STAILQ_NEXT(filter, next);
2254         }
2255         return 0;
2256 }
2257
2258 static int
2259 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2260 {
2261         struct bnxt_vnic_info *vnic;
2262         unsigned int i;
2263         int rc;
2264
2265         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2266         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2267                 /* Remove any VLAN filters programmed */
2268                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2269                         bnxt_del_vlan_filter(bp, i);
2270
2271                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2272                 if (rc)
2273                         return rc;
2274         } else {
2275                 /* Default filter will allow packets that match the
2276                  * dest mac. So, it has to be deleted, otherwise, we
2277                  * will endup receiving vlan packets for which the
2278                  * filter is not programmed, when hw-vlan-filter
2279                  * configuration is ON
2280                  */
2281                 bnxt_del_dflt_mac_filter(bp, vnic);
2282                 /* This filter will allow only untagged packets */
2283                 bnxt_add_vlan_filter(bp, 0);
2284         }
2285         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2286                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2287
2288         return 0;
2289 }
2290
2291 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2292 {
2293         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2294         unsigned int i;
2295         int rc;
2296
2297         /* Destroy vnic filters and vnic */
2298         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2299             DEV_RX_OFFLOAD_VLAN_FILTER) {
2300                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2301                         bnxt_del_vlan_filter(bp, i);
2302         }
2303         bnxt_del_dflt_mac_filter(bp, vnic);
2304
2305         rc = bnxt_hwrm_vnic_free(bp, vnic);
2306         if (rc)
2307                 return rc;
2308
2309         rte_free(vnic->fw_grp_ids);
2310         vnic->fw_grp_ids = NULL;
2311
2312         vnic->rx_queue_cnt = 0;
2313
2314         return 0;
2315 }
2316
2317 static int
2318 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2319 {
2320         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2321         int rc;
2322
2323         /* Destroy, recreate and reconfigure the default vnic */
2324         rc = bnxt_free_one_vnic(bp, 0);
2325         if (rc)
2326                 return rc;
2327
2328         /* default vnic 0 */
2329         rc = bnxt_setup_one_vnic(bp, 0);
2330         if (rc)
2331                 return rc;
2332
2333         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2334             DEV_RX_OFFLOAD_VLAN_FILTER) {
2335                 rc = bnxt_add_vlan_filter(bp, 0);
2336                 if (rc)
2337                         return rc;
2338                 rc = bnxt_restore_vlan_filters(bp);
2339                 if (rc)
2340                         return rc;
2341         } else {
2342                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2343                 if (rc)
2344                         return rc;
2345         }
2346
2347         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2348         if (rc)
2349                 return rc;
2350
2351         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2352                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2353
2354         return rc;
2355 }
2356
2357 static int
2358 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2359 {
2360         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2361         struct bnxt *bp = dev->data->dev_private;
2362         int rc;
2363
2364         rc = is_bnxt_in_error(bp);
2365         if (rc)
2366                 return rc;
2367
2368         /* Filter settings will get applied when port is started */
2369         if (!dev->data->dev_started)
2370                 return 0;
2371
2372         if (mask & ETH_VLAN_FILTER_MASK) {
2373                 /* Enable or disable VLAN filtering */
2374                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2375                 if (rc)
2376                         return rc;
2377         }
2378
2379         if (mask & ETH_VLAN_STRIP_MASK) {
2380                 /* Enable or disable VLAN stripping */
2381                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2382                 if (rc)
2383                         return rc;
2384         }
2385
2386         if (mask & ETH_VLAN_EXTEND_MASK) {
2387                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2388                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2389                 else
2390                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2391         }
2392
2393         return 0;
2394 }
2395
2396 static int
2397 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2398                       uint16_t tpid)
2399 {
2400         struct bnxt *bp = dev->data->dev_private;
2401         int qinq = dev->data->dev_conf.rxmode.offloads &
2402                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2403
2404         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2405             vlan_type != ETH_VLAN_TYPE_OUTER) {
2406                 PMD_DRV_LOG(ERR,
2407                             "Unsupported vlan type.");
2408                 return -EINVAL;
2409         }
2410         if (!qinq) {
2411                 PMD_DRV_LOG(ERR,
2412                             "QinQ not enabled. Needs to be ON as we can "
2413                             "accelerate only outer vlan\n");
2414                 return -EINVAL;
2415         }
2416
2417         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2418                 switch (tpid) {
2419                 case RTE_ETHER_TYPE_QINQ:
2420                         bp->outer_tpid_bd =
2421                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2422                                 break;
2423                 case RTE_ETHER_TYPE_VLAN:
2424                         bp->outer_tpid_bd =
2425                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2426                                 break;
2427                 case 0x9100:
2428                         bp->outer_tpid_bd =
2429                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2430                                 break;
2431                 case 0x9200:
2432                         bp->outer_tpid_bd =
2433                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2434                                 break;
2435                 case 0x9300:
2436                         bp->outer_tpid_bd =
2437                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2438                                 break;
2439                 default:
2440                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2441                         return -EINVAL;
2442                 }
2443                 bp->outer_tpid_bd |= tpid;
2444                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2445         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2446                 PMD_DRV_LOG(ERR,
2447                             "Can accelerate only outer vlan in QinQ\n");
2448                 return -EINVAL;
2449         }
2450
2451         return 0;
2452 }
2453
2454 static int
2455 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2456                              struct rte_ether_addr *addr)
2457 {
2458         struct bnxt *bp = dev->data->dev_private;
2459         /* Default Filter is tied to VNIC 0 */
2460         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2461         int rc;
2462
2463         rc = is_bnxt_in_error(bp);
2464         if (rc)
2465                 return rc;
2466
2467         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2468                 return -EPERM;
2469
2470         if (rte_is_zero_ether_addr(addr))
2471                 return -EINVAL;
2472
2473         /* Filter settings will get applied when port is started */
2474         if (!dev->data->dev_started)
2475                 return 0;
2476
2477         /* Check if the requested MAC is already added */
2478         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2479                 return 0;
2480
2481         /* Destroy filter and re-create it */
2482         bnxt_del_dflt_mac_filter(bp, vnic);
2483
2484         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2485         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2486                 /* This filter will allow only untagged packets */
2487                 rc = bnxt_add_vlan_filter(bp, 0);
2488         } else {
2489                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2490         }
2491
2492         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2493         return rc;
2494 }
2495
2496 static int
2497 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2498                           struct rte_ether_addr *mc_addr_set,
2499                           uint32_t nb_mc_addr)
2500 {
2501         struct bnxt *bp = eth_dev->data->dev_private;
2502         char *mc_addr_list = (char *)mc_addr_set;
2503         struct bnxt_vnic_info *vnic;
2504         uint32_t off = 0, i = 0;
2505         int rc;
2506
2507         rc = is_bnxt_in_error(bp);
2508         if (rc)
2509                 return rc;
2510
2511         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2512
2513         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2514                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2515                 goto allmulti;
2516         }
2517
2518         /* TODO Check for Duplicate mcast addresses */
2519         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2520         for (i = 0; i < nb_mc_addr; i++) {
2521                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2522                         RTE_ETHER_ADDR_LEN);
2523                 off += RTE_ETHER_ADDR_LEN;
2524         }
2525
2526         vnic->mc_addr_cnt = i;
2527         if (vnic->mc_addr_cnt)
2528                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2529         else
2530                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2531
2532 allmulti:
2533         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2534 }
2535
2536 static int
2537 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2538 {
2539         struct bnxt *bp = dev->data->dev_private;
2540         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2541         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2542         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2543         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2544         int ret;
2545
2546         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2547                         fw_major, fw_minor, fw_updt, fw_rsvd);
2548
2549         ret += 1; /* add the size of '\0' */
2550         if (fw_size < (uint32_t)ret)
2551                 return ret;
2552         else
2553                 return 0;
2554 }
2555
2556 static void
2557 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2558         struct rte_eth_rxq_info *qinfo)
2559 {
2560         struct bnxt *bp = dev->data->dev_private;
2561         struct bnxt_rx_queue *rxq;
2562
2563         if (is_bnxt_in_error(bp))
2564                 return;
2565
2566         rxq = dev->data->rx_queues[queue_id];
2567
2568         qinfo->mp = rxq->mb_pool;
2569         qinfo->scattered_rx = dev->data->scattered_rx;
2570         qinfo->nb_desc = rxq->nb_rx_desc;
2571
2572         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2573         qinfo->conf.rx_drop_en = 0;
2574         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2575 }
2576
2577 static void
2578 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2579         struct rte_eth_txq_info *qinfo)
2580 {
2581         struct bnxt *bp = dev->data->dev_private;
2582         struct bnxt_tx_queue *txq;
2583
2584         if (is_bnxt_in_error(bp))
2585                 return;
2586
2587         txq = dev->data->tx_queues[queue_id];
2588
2589         qinfo->nb_desc = txq->nb_tx_desc;
2590
2591         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2592         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2593         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2594
2595         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2596         qinfo->conf.tx_rs_thresh = 0;
2597         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2598 }
2599
2600 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2601 {
2602         struct bnxt *bp = eth_dev->data->dev_private;
2603         uint32_t new_pkt_size;
2604         uint32_t rc = 0;
2605         uint32_t i;
2606
2607         rc = is_bnxt_in_error(bp);
2608         if (rc)
2609                 return rc;
2610
2611         /* Exit if receive queues are not configured yet */
2612         if (!eth_dev->data->nb_rx_queues)
2613                 return rc;
2614
2615         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2616                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2617
2618 #ifdef RTE_ARCH_X86
2619         /*
2620          * If vector-mode tx/rx is active, disallow any MTU change that would
2621          * require scattered receive support.
2622          */
2623         if (eth_dev->data->dev_started &&
2624             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2625              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2626             (new_pkt_size >
2627              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2628                 PMD_DRV_LOG(ERR,
2629                             "MTU change would require scattered rx support. ");
2630                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2631                 return -EINVAL;
2632         }
2633 #endif
2634
2635         if (new_mtu > RTE_ETHER_MTU) {
2636                 bp->flags |= BNXT_FLAG_JUMBO;
2637                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2638                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2639         } else {
2640                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2641                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2642                 bp->flags &= ~BNXT_FLAG_JUMBO;
2643         }
2644
2645         /* Is there a change in mtu setting? */
2646         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2647                 return rc;
2648
2649         for (i = 0; i < bp->nr_vnics; i++) {
2650                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2651                 uint16_t size = 0;
2652
2653                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2654                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2655                 if (rc)
2656                         break;
2657
2658                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2659                 size -= RTE_PKTMBUF_HEADROOM;
2660
2661                 if (size < new_mtu) {
2662                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2663                         if (rc)
2664                                 return rc;
2665                 }
2666         }
2667
2668         if (!rc)
2669                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2670
2671         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2672
2673         return rc;
2674 }
2675
2676 static int
2677 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2678 {
2679         struct bnxt *bp = dev->data->dev_private;
2680         uint16_t vlan = bp->vlan;
2681         int rc;
2682
2683         rc = is_bnxt_in_error(bp);
2684         if (rc)
2685                 return rc;
2686
2687         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2688                 PMD_DRV_LOG(ERR,
2689                         "PVID cannot be modified for this function\n");
2690                 return -ENOTSUP;
2691         }
2692         bp->vlan = on ? pvid : 0;
2693
2694         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2695         if (rc)
2696                 bp->vlan = vlan;
2697         return rc;
2698 }
2699
2700 static int
2701 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2702 {
2703         struct bnxt *bp = dev->data->dev_private;
2704         int rc;
2705
2706         rc = is_bnxt_in_error(bp);
2707         if (rc)
2708                 return rc;
2709
2710         return bnxt_hwrm_port_led_cfg(bp, true);
2711 }
2712
2713 static int
2714 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2715 {
2716         struct bnxt *bp = dev->data->dev_private;
2717         int rc;
2718
2719         rc = is_bnxt_in_error(bp);
2720         if (rc)
2721                 return rc;
2722
2723         return bnxt_hwrm_port_led_cfg(bp, false);
2724 }
2725
2726 static uint32_t
2727 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2728 {
2729         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2730         uint32_t desc = 0, raw_cons = 0, cons;
2731         struct bnxt_cp_ring_info *cpr;
2732         struct bnxt_rx_queue *rxq;
2733         struct rx_pkt_cmpl *rxcmp;
2734         int rc;
2735
2736         rc = is_bnxt_in_error(bp);
2737         if (rc)
2738                 return rc;
2739
2740         rxq = dev->data->rx_queues[rx_queue_id];
2741         cpr = rxq->cp_ring;
2742         raw_cons = cpr->cp_raw_cons;
2743
2744         while (1) {
2745                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2746                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2747                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2748
2749                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2750                         break;
2751                 } else {
2752                         raw_cons++;
2753                         desc++;
2754                 }
2755         }
2756
2757         return desc;
2758 }
2759
2760 static int
2761 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2762 {
2763         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2764         struct bnxt_rx_ring_info *rxr;
2765         struct bnxt_cp_ring_info *cpr;
2766         struct bnxt_sw_rx_bd *rx_buf;
2767         struct rx_pkt_cmpl *rxcmp;
2768         uint32_t cons, cp_cons;
2769         int rc;
2770
2771         if (!rxq)
2772                 return -EINVAL;
2773
2774         rc = is_bnxt_in_error(rxq->bp);
2775         if (rc)
2776                 return rc;
2777
2778         cpr = rxq->cp_ring;
2779         rxr = rxq->rx_ring;
2780
2781         if (offset >= rxq->nb_rx_desc)
2782                 return -EINVAL;
2783
2784         cons = RING_CMP(cpr->cp_ring_struct, offset);
2785         cp_cons = cpr->cp_raw_cons;
2786         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2787
2788         if (cons > cp_cons) {
2789                 if (CMPL_VALID(rxcmp, cpr->valid))
2790                         return RTE_ETH_RX_DESC_DONE;
2791         } else {
2792                 if (CMPL_VALID(rxcmp, !cpr->valid))
2793                         return RTE_ETH_RX_DESC_DONE;
2794         }
2795         rx_buf = &rxr->rx_buf_ring[cons];
2796         if (rx_buf->mbuf == NULL)
2797                 return RTE_ETH_RX_DESC_UNAVAIL;
2798
2799
2800         return RTE_ETH_RX_DESC_AVAIL;
2801 }
2802
2803 static int
2804 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2805 {
2806         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2807         struct bnxt_tx_ring_info *txr;
2808         struct bnxt_cp_ring_info *cpr;
2809         struct bnxt_sw_tx_bd *tx_buf;
2810         struct tx_pkt_cmpl *txcmp;
2811         uint32_t cons, cp_cons;
2812         int rc;
2813
2814         if (!txq)
2815                 return -EINVAL;
2816
2817         rc = is_bnxt_in_error(txq->bp);
2818         if (rc)
2819                 return rc;
2820
2821         cpr = txq->cp_ring;
2822         txr = txq->tx_ring;
2823
2824         if (offset >= txq->nb_tx_desc)
2825                 return -EINVAL;
2826
2827         cons = RING_CMP(cpr->cp_ring_struct, offset);
2828         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2829         cp_cons = cpr->cp_raw_cons;
2830
2831         if (cons > cp_cons) {
2832                 if (CMPL_VALID(txcmp, cpr->valid))
2833                         return RTE_ETH_TX_DESC_UNAVAIL;
2834         } else {
2835                 if (CMPL_VALID(txcmp, !cpr->valid))
2836                         return RTE_ETH_TX_DESC_UNAVAIL;
2837         }
2838         tx_buf = &txr->tx_buf_ring[cons];
2839         if (tx_buf->mbuf == NULL)
2840                 return RTE_ETH_TX_DESC_DONE;
2841
2842         return RTE_ETH_TX_DESC_FULL;
2843 }
2844
2845 static struct bnxt_filter_info *
2846 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2847                                 struct rte_eth_ethertype_filter *efilter,
2848                                 struct bnxt_vnic_info *vnic0,
2849                                 struct bnxt_vnic_info *vnic,
2850                                 int *ret)
2851 {
2852         struct bnxt_filter_info *mfilter = NULL;
2853         int match = 0;
2854         *ret = 0;
2855
2856         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2857                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2858                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2859                         " ethertype filter.", efilter->ether_type);
2860                 *ret = -EINVAL;
2861                 goto exit;
2862         }
2863         if (efilter->queue >= bp->rx_nr_rings) {
2864                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2865                 *ret = -EINVAL;
2866                 goto exit;
2867         }
2868
2869         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2870         vnic = &bp->vnic_info[efilter->queue];
2871         if (vnic == NULL) {
2872                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2873                 *ret = -EINVAL;
2874                 goto exit;
2875         }
2876
2877         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2878                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2879                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2880                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2881                              mfilter->flags ==
2882                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2883                              mfilter->ethertype == efilter->ether_type)) {
2884                                 match = 1;
2885                                 break;
2886                         }
2887                 }
2888         } else {
2889                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2890                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2891                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2892                              mfilter->ethertype == efilter->ether_type &&
2893                              mfilter->flags ==
2894                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2895                                 match = 1;
2896                                 break;
2897                         }
2898         }
2899
2900         if (match)
2901                 *ret = -EEXIST;
2902
2903 exit:
2904         return mfilter;
2905 }
2906
2907 static int
2908 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2909                         enum rte_filter_op filter_op,
2910                         void *arg)
2911 {
2912         struct bnxt *bp = dev->data->dev_private;
2913         struct rte_eth_ethertype_filter *efilter =
2914                         (struct rte_eth_ethertype_filter *)arg;
2915         struct bnxt_filter_info *bfilter, *filter1;
2916         struct bnxt_vnic_info *vnic, *vnic0;
2917         int ret;
2918
2919         if (filter_op == RTE_ETH_FILTER_NOP)
2920                 return 0;
2921
2922         if (arg == NULL) {
2923                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2924                             filter_op);
2925                 return -EINVAL;
2926         }
2927
2928         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2929         vnic = &bp->vnic_info[efilter->queue];
2930
2931         switch (filter_op) {
2932         case RTE_ETH_FILTER_ADD:
2933                 bnxt_match_and_validate_ether_filter(bp, efilter,
2934                                                         vnic0, vnic, &ret);
2935                 if (ret < 0)
2936                         return ret;
2937
2938                 bfilter = bnxt_get_unused_filter(bp);
2939                 if (bfilter == NULL) {
2940                         PMD_DRV_LOG(ERR,
2941                                 "Not enough resources for a new filter.\n");
2942                         return -ENOMEM;
2943                 }
2944                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2945                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2946                        RTE_ETHER_ADDR_LEN);
2947                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2948                        RTE_ETHER_ADDR_LEN);
2949                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2950                 bfilter->ethertype = efilter->ether_type;
2951                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2952
2953                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2954                 if (filter1 == NULL) {
2955                         ret = -EINVAL;
2956                         goto cleanup;
2957                 }
2958                 bfilter->enables |=
2959                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2960                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2961
2962                 bfilter->dst_id = vnic->fw_vnic_id;
2963
2964                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2965                         bfilter->flags =
2966                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2967                 }
2968
2969                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2970                 if (ret)
2971                         goto cleanup;
2972                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2973                 break;
2974         case RTE_ETH_FILTER_DELETE:
2975                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2976                                                         vnic0, vnic, &ret);
2977                 if (ret == -EEXIST) {
2978                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2979
2980                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2981                                       next);
2982                         bnxt_free_filter(bp, filter1);
2983                 } else if (ret == 0) {
2984                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2985                 }
2986                 break;
2987         default:
2988                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2989                 ret = -EINVAL;
2990                 goto error;
2991         }
2992         return ret;
2993 cleanup:
2994         bnxt_free_filter(bp, bfilter);
2995 error:
2996         return ret;
2997 }
2998
2999 static inline int
3000 parse_ntuple_filter(struct bnxt *bp,
3001                     struct rte_eth_ntuple_filter *nfilter,
3002                     struct bnxt_filter_info *bfilter)
3003 {
3004         uint32_t en = 0;
3005
3006         if (nfilter->queue >= bp->rx_nr_rings) {
3007                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3008                 return -EINVAL;
3009         }
3010
3011         switch (nfilter->dst_port_mask) {
3012         case UINT16_MAX:
3013                 bfilter->dst_port_mask = -1;
3014                 bfilter->dst_port = nfilter->dst_port;
3015                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3016                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3017                 break;
3018         default:
3019                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3020                 return -EINVAL;
3021         }
3022
3023         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3024         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3025
3026         switch (nfilter->proto_mask) {
3027         case UINT8_MAX:
3028                 if (nfilter->proto == 17) /* IPPROTO_UDP */
3029                         bfilter->ip_protocol = 17;
3030                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3031                         bfilter->ip_protocol = 6;
3032                 else
3033                         return -EINVAL;
3034                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3035                 break;
3036         default:
3037                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3038                 return -EINVAL;
3039         }
3040
3041         switch (nfilter->dst_ip_mask) {
3042         case UINT32_MAX:
3043                 bfilter->dst_ipaddr_mask[0] = -1;
3044                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3045                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3046                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3047                 break;
3048         default:
3049                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3050                 return -EINVAL;
3051         }
3052
3053         switch (nfilter->src_ip_mask) {
3054         case UINT32_MAX:
3055                 bfilter->src_ipaddr_mask[0] = -1;
3056                 bfilter->src_ipaddr[0] = nfilter->src_ip;
3057                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3058                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3059                 break;
3060         default:
3061                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3062                 return -EINVAL;
3063         }
3064
3065         switch (nfilter->src_port_mask) {
3066         case UINT16_MAX:
3067                 bfilter->src_port_mask = -1;
3068                 bfilter->src_port = nfilter->src_port;
3069                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3070                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3071                 break;
3072         default:
3073                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3074                 return -EINVAL;
3075         }
3076
3077         bfilter->enables = en;
3078         return 0;
3079 }
3080
3081 static struct bnxt_filter_info*
3082 bnxt_match_ntuple_filter(struct bnxt *bp,
3083                          struct bnxt_filter_info *bfilter,
3084                          struct bnxt_vnic_info **mvnic)
3085 {
3086         struct bnxt_filter_info *mfilter = NULL;
3087         int i;
3088
3089         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3090                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3091                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3092                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3093                             bfilter->src_ipaddr_mask[0] ==
3094                             mfilter->src_ipaddr_mask[0] &&
3095                             bfilter->src_port == mfilter->src_port &&
3096                             bfilter->src_port_mask == mfilter->src_port_mask &&
3097                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3098                             bfilter->dst_ipaddr_mask[0] ==
3099                             mfilter->dst_ipaddr_mask[0] &&
3100                             bfilter->dst_port == mfilter->dst_port &&
3101                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
3102                             bfilter->flags == mfilter->flags &&
3103                             bfilter->enables == mfilter->enables) {
3104                                 if (mvnic)
3105                                         *mvnic = vnic;
3106                                 return mfilter;
3107                         }
3108                 }
3109         }
3110         return NULL;
3111 }
3112
3113 static int
3114 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3115                        struct rte_eth_ntuple_filter *nfilter,
3116                        enum rte_filter_op filter_op)
3117 {
3118         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3119         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3120         int ret;
3121
3122         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3123                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3124                 return -EINVAL;
3125         }
3126
3127         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3128                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3129                 return -EINVAL;
3130         }
3131
3132         bfilter = bnxt_get_unused_filter(bp);
3133         if (bfilter == NULL) {
3134                 PMD_DRV_LOG(ERR,
3135                         "Not enough resources for a new filter.\n");
3136                 return -ENOMEM;
3137         }
3138         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3139         if (ret < 0)
3140                 goto free_filter;
3141
3142         vnic = &bp->vnic_info[nfilter->queue];
3143         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3144         filter1 = STAILQ_FIRST(&vnic0->filter);
3145         if (filter1 == NULL) {
3146                 ret = -EINVAL;
3147                 goto free_filter;
3148         }
3149
3150         bfilter->dst_id = vnic->fw_vnic_id;
3151         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3152         bfilter->enables |=
3153                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3154         bfilter->ethertype = 0x800;
3155         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3156
3157         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3158
3159         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3160             bfilter->dst_id == mfilter->dst_id) {
3161                 PMD_DRV_LOG(ERR, "filter exists.\n");
3162                 ret = -EEXIST;
3163                 goto free_filter;
3164         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3165                    bfilter->dst_id != mfilter->dst_id) {
3166                 mfilter->dst_id = vnic->fw_vnic_id;
3167                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3168                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3169                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3170                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3171                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3172                 goto free_filter;
3173         }
3174         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3175                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3176                 ret = -ENOENT;
3177                 goto free_filter;
3178         }
3179
3180         if (filter_op == RTE_ETH_FILTER_ADD) {
3181                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3182                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3183                 if (ret)
3184                         goto free_filter;
3185                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3186         } else {
3187                 if (mfilter == NULL) {
3188                         /* This should not happen. But for Coverity! */
3189                         ret = -ENOENT;
3190                         goto free_filter;
3191                 }
3192                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3193
3194                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3195                 bnxt_free_filter(bp, mfilter);
3196                 bnxt_free_filter(bp, bfilter);
3197         }
3198
3199         return 0;
3200 free_filter:
3201         bnxt_free_filter(bp, bfilter);
3202         return ret;
3203 }
3204
3205 static int
3206 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3207                         enum rte_filter_op filter_op,
3208                         void *arg)
3209 {
3210         struct bnxt *bp = dev->data->dev_private;
3211         int ret;
3212
3213         if (filter_op == RTE_ETH_FILTER_NOP)
3214                 return 0;
3215
3216         if (arg == NULL) {
3217                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3218                             filter_op);
3219                 return -EINVAL;
3220         }
3221
3222         switch (filter_op) {
3223         case RTE_ETH_FILTER_ADD:
3224                 ret = bnxt_cfg_ntuple_filter(bp,
3225                         (struct rte_eth_ntuple_filter *)arg,
3226                         filter_op);
3227                 break;
3228         case RTE_ETH_FILTER_DELETE:
3229                 ret = bnxt_cfg_ntuple_filter(bp,
3230                         (struct rte_eth_ntuple_filter *)arg,
3231                         filter_op);
3232                 break;
3233         default:
3234                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3235                 ret = -EINVAL;
3236                 break;
3237         }
3238         return ret;
3239 }
3240
3241 static int
3242 bnxt_parse_fdir_filter(struct bnxt *bp,
3243                        struct rte_eth_fdir_filter *fdir,
3244                        struct bnxt_filter_info *filter)
3245 {
3246         enum rte_fdir_mode fdir_mode =
3247                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3248         struct bnxt_vnic_info *vnic0, *vnic;
3249         struct bnxt_filter_info *filter1;
3250         uint32_t en = 0;
3251         int i;
3252
3253         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3254                 return -EINVAL;
3255
3256         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3257         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3258
3259         switch (fdir->input.flow_type) {
3260         case RTE_ETH_FLOW_IPV4:
3261         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3262                 /* FALLTHROUGH */
3263                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3264                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3265                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3266                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3267                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3268                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3269                 filter->ip_addr_type =
3270                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3271                 filter->src_ipaddr_mask[0] = 0xffffffff;
3272                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3273                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3274                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3275                 filter->ethertype = 0x800;
3276                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3277                 break;
3278         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3279                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3280                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3281                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3282                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3283                 filter->dst_port_mask = 0xffff;
3284                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3285                 filter->src_port_mask = 0xffff;
3286                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3287                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3288                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3289                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3290                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3291                 filter->ip_protocol = 6;
3292                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3293                 filter->ip_addr_type =
3294                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3295                 filter->src_ipaddr_mask[0] = 0xffffffff;
3296                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3297                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3298                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3299                 filter->ethertype = 0x800;
3300                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3301                 break;
3302         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3303                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3304                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3305                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3306                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3307                 filter->dst_port_mask = 0xffff;
3308                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3309                 filter->src_port_mask = 0xffff;
3310                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3311                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3312                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3313                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3314                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3315                 filter->ip_protocol = 17;
3316                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3317                 filter->ip_addr_type =
3318                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3319                 filter->src_ipaddr_mask[0] = 0xffffffff;
3320                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3321                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3322                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3323                 filter->ethertype = 0x800;
3324                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3325                 break;
3326         case RTE_ETH_FLOW_IPV6:
3327         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3328                 /* FALLTHROUGH */
3329                 filter->ip_addr_type =
3330                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3331                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3332                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3333                 rte_memcpy(filter->src_ipaddr,
3334                            fdir->input.flow.ipv6_flow.src_ip, 16);
3335                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3336                 rte_memcpy(filter->dst_ipaddr,
3337                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3338                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3339                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3340                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3341                 memset(filter->src_ipaddr_mask, 0xff, 16);
3342                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3343                 filter->ethertype = 0x86dd;
3344                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3345                 break;
3346         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3347                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3348                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3349                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3350                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3351                 filter->dst_port_mask = 0xffff;
3352                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3353                 filter->src_port_mask = 0xffff;
3354                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3355                 filter->ip_addr_type =
3356                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3357                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3358                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3359                 rte_memcpy(filter->src_ipaddr,
3360                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3361                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3362                 rte_memcpy(filter->dst_ipaddr,
3363                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3364                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3365                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3366                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3367                 memset(filter->src_ipaddr_mask, 0xff, 16);
3368                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3369                 filter->ethertype = 0x86dd;
3370                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3371                 break;
3372         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3373                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3374                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3375                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3376                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3377                 filter->dst_port_mask = 0xffff;
3378                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3379                 filter->src_port_mask = 0xffff;
3380                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3381                 filter->ip_addr_type =
3382                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3383                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3384                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3385                 rte_memcpy(filter->src_ipaddr,
3386                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3387                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3388                 rte_memcpy(filter->dst_ipaddr,
3389                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3390                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3391                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3392                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3393                 memset(filter->src_ipaddr_mask, 0xff, 16);
3394                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3395                 filter->ethertype = 0x86dd;
3396                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3397                 break;
3398         case RTE_ETH_FLOW_L2_PAYLOAD:
3399                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3400                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3401                 break;
3402         case RTE_ETH_FLOW_VXLAN:
3403                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3404                         return -EINVAL;
3405                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3406                 filter->tunnel_type =
3407                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3408                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3409                 break;
3410         case RTE_ETH_FLOW_NVGRE:
3411                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3412                         return -EINVAL;
3413                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3414                 filter->tunnel_type =
3415                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3416                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3417                 break;
3418         case RTE_ETH_FLOW_UNKNOWN:
3419         case RTE_ETH_FLOW_RAW:
3420         case RTE_ETH_FLOW_FRAG_IPV4:
3421         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3422         case RTE_ETH_FLOW_FRAG_IPV6:
3423         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3424         case RTE_ETH_FLOW_IPV6_EX:
3425         case RTE_ETH_FLOW_IPV6_TCP_EX:
3426         case RTE_ETH_FLOW_IPV6_UDP_EX:
3427         case RTE_ETH_FLOW_GENEVE:
3428                 /* FALLTHROUGH */
3429         default:
3430                 return -EINVAL;
3431         }
3432
3433         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3434         vnic = &bp->vnic_info[fdir->action.rx_queue];
3435         if (vnic == NULL) {
3436                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3437                 return -EINVAL;
3438         }
3439
3440         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3441                 rte_memcpy(filter->dst_macaddr,
3442                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3443                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3444         }
3445
3446         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3447                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3448                 filter1 = STAILQ_FIRST(&vnic0->filter);
3449                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3450         } else {
3451                 filter->dst_id = vnic->fw_vnic_id;
3452                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3453                         if (filter->dst_macaddr[i] == 0x00)
3454                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3455                         else
3456                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3457         }
3458
3459         if (filter1 == NULL)
3460                 return -EINVAL;
3461
3462         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3463         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3464
3465         filter->enables = en;
3466
3467         return 0;
3468 }
3469
3470 static struct bnxt_filter_info *
3471 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3472                 struct bnxt_vnic_info **mvnic)
3473 {
3474         struct bnxt_filter_info *mf = NULL;
3475         int i;
3476
3477         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3478                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3479
3480                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3481                         if (mf->filter_type == nf->filter_type &&
3482                             mf->flags == nf->flags &&
3483                             mf->src_port == nf->src_port &&
3484                             mf->src_port_mask == nf->src_port_mask &&
3485                             mf->dst_port == nf->dst_port &&
3486                             mf->dst_port_mask == nf->dst_port_mask &&
3487                             mf->ip_protocol == nf->ip_protocol &&
3488                             mf->ip_addr_type == nf->ip_addr_type &&
3489                             mf->ethertype == nf->ethertype &&
3490                             mf->vni == nf->vni &&
3491                             mf->tunnel_type == nf->tunnel_type &&
3492                             mf->l2_ovlan == nf->l2_ovlan &&
3493                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3494                             mf->l2_ivlan == nf->l2_ivlan &&
3495                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3496                             !memcmp(mf->l2_addr, nf->l2_addr,
3497                                     RTE_ETHER_ADDR_LEN) &&
3498                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3499                                     RTE_ETHER_ADDR_LEN) &&
3500                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3501                                     RTE_ETHER_ADDR_LEN) &&
3502                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3503                                     RTE_ETHER_ADDR_LEN) &&
3504                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3505                                     sizeof(nf->src_ipaddr)) &&
3506                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3507                                     sizeof(nf->src_ipaddr_mask)) &&
3508                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3509                                     sizeof(nf->dst_ipaddr)) &&
3510                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3511                                     sizeof(nf->dst_ipaddr_mask))) {
3512                                 if (mvnic)
3513                                         *mvnic = vnic;
3514                                 return mf;
3515                         }
3516                 }
3517         }
3518         return NULL;
3519 }
3520
3521 static int
3522 bnxt_fdir_filter(struct rte_eth_dev *dev,
3523                  enum rte_filter_op filter_op,
3524                  void *arg)
3525 {
3526         struct bnxt *bp = dev->data->dev_private;
3527         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3528         struct bnxt_filter_info *filter, *match;
3529         struct bnxt_vnic_info *vnic, *mvnic;
3530         int ret = 0, i;
3531
3532         if (filter_op == RTE_ETH_FILTER_NOP)
3533                 return 0;
3534
3535         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3536                 return -EINVAL;
3537
3538         switch (filter_op) {
3539         case RTE_ETH_FILTER_ADD:
3540         case RTE_ETH_FILTER_DELETE:
3541                 /* FALLTHROUGH */
3542                 filter = bnxt_get_unused_filter(bp);
3543                 if (filter == NULL) {
3544                         PMD_DRV_LOG(ERR,
3545                                 "Not enough resources for a new flow.\n");
3546                         return -ENOMEM;
3547                 }
3548
3549                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3550                 if (ret != 0)
3551                         goto free_filter;
3552                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3553
3554                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3555                         vnic = &bp->vnic_info[0];
3556                 else
3557                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3558
3559                 match = bnxt_match_fdir(bp, filter, &mvnic);
3560                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3561                         if (match->dst_id == vnic->fw_vnic_id) {
3562                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3563                                 ret = -EEXIST;
3564                                 goto free_filter;
3565                         } else {
3566                                 match->dst_id = vnic->fw_vnic_id;
3567                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3568                                                                   match->dst_id,
3569                                                                   match);
3570                                 STAILQ_REMOVE(&mvnic->filter, match,
3571                                               bnxt_filter_info, next);
3572                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3573                                 PMD_DRV_LOG(ERR,
3574                                         "Filter with matching pattern exist\n");
3575                                 PMD_DRV_LOG(ERR,
3576                                         "Updated it to new destination q\n");
3577                                 goto free_filter;
3578                         }
3579                 }
3580                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3581                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3582                         ret = -ENOENT;
3583                         goto free_filter;
3584                 }
3585
3586                 if (filter_op == RTE_ETH_FILTER_ADD) {
3587                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3588                                                           filter->dst_id,
3589                                                           filter);
3590                         if (ret)
3591                                 goto free_filter;
3592                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3593                 } else {
3594                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3595                         STAILQ_REMOVE(&vnic->filter, match,
3596                                       bnxt_filter_info, next);
3597                         bnxt_free_filter(bp, match);
3598                         bnxt_free_filter(bp, filter);
3599                 }
3600                 break;
3601         case RTE_ETH_FILTER_FLUSH:
3602                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3603                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3604
3605                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3606                                 if (filter->filter_type ==
3607                                     HWRM_CFA_NTUPLE_FILTER) {
3608                                         ret =
3609                                         bnxt_hwrm_clear_ntuple_filter(bp,
3610                                                                       filter);
3611                                         STAILQ_REMOVE(&vnic->filter, filter,
3612                                                       bnxt_filter_info, next);
3613                                 }
3614                         }
3615                 }
3616                 return ret;
3617         case RTE_ETH_FILTER_UPDATE:
3618         case RTE_ETH_FILTER_STATS:
3619         case RTE_ETH_FILTER_INFO:
3620                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3621                 break;
3622         default:
3623                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3624                 ret = -EINVAL;
3625                 break;
3626         }
3627         return ret;
3628
3629 free_filter:
3630         bnxt_free_filter(bp, filter);
3631         return ret;
3632 }
3633
3634 static int
3635 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3636                     enum rte_filter_type filter_type,
3637                     enum rte_filter_op filter_op, void *arg)
3638 {
3639         struct bnxt *bp = dev->data->dev_private;
3640         int ret = 0;
3641
3642         ret = is_bnxt_in_error(dev->data->dev_private);
3643         if (ret)
3644                 return ret;
3645
3646         switch (filter_type) {
3647         case RTE_ETH_FILTER_TUNNEL:
3648                 PMD_DRV_LOG(ERR,
3649                         "filter type: %d: To be implemented\n", filter_type);
3650                 break;
3651         case RTE_ETH_FILTER_FDIR:
3652                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3653                 break;
3654         case RTE_ETH_FILTER_NTUPLE:
3655                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3656                 break;
3657         case RTE_ETH_FILTER_ETHERTYPE:
3658                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3659                 break;
3660         case RTE_ETH_FILTER_GENERIC:
3661                 if (filter_op != RTE_ETH_FILTER_GET)
3662                         return -EINVAL;
3663                 if (BNXT_TRUFLOW_EN(bp))
3664                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3665                 else
3666                         *(const void **)arg = &bnxt_flow_ops;
3667                 break;
3668         default:
3669                 PMD_DRV_LOG(ERR,
3670                         "Filter type (%d) not supported", filter_type);
3671                 ret = -EINVAL;
3672                 break;
3673         }
3674         return ret;
3675 }
3676
3677 static const uint32_t *
3678 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3679 {
3680         static const uint32_t ptypes[] = {
3681                 RTE_PTYPE_L2_ETHER_VLAN,
3682                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3683                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3684                 RTE_PTYPE_L4_ICMP,
3685                 RTE_PTYPE_L4_TCP,
3686                 RTE_PTYPE_L4_UDP,
3687                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3688                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3689                 RTE_PTYPE_INNER_L4_ICMP,
3690                 RTE_PTYPE_INNER_L4_TCP,
3691                 RTE_PTYPE_INNER_L4_UDP,
3692                 RTE_PTYPE_UNKNOWN
3693         };
3694
3695         if (!dev->rx_pkt_burst)
3696                 return NULL;
3697
3698         return ptypes;
3699 }
3700
3701 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3702                          int reg_win)
3703 {
3704         uint32_t reg_base = *reg_arr & 0xfffff000;
3705         uint32_t win_off;
3706         int i;
3707
3708         for (i = 0; i < count; i++) {
3709                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3710                         return -ERANGE;
3711         }
3712         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3713         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3714         return 0;
3715 }
3716
3717 static int bnxt_map_ptp_regs(struct bnxt *bp)
3718 {
3719         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3720         uint32_t *reg_arr;
3721         int rc, i;
3722
3723         reg_arr = ptp->rx_regs;
3724         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3725         if (rc)
3726                 return rc;
3727
3728         reg_arr = ptp->tx_regs;
3729         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3730         if (rc)
3731                 return rc;
3732
3733         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3734                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3735
3736         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3737                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3738
3739         return 0;
3740 }
3741
3742 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3743 {
3744         rte_write32(0, (uint8_t *)bp->bar0 +
3745                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3746         rte_write32(0, (uint8_t *)bp->bar0 +
3747                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3748 }
3749
3750 static uint64_t bnxt_cc_read(struct bnxt *bp)
3751 {
3752         uint64_t ns;
3753
3754         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3755                               BNXT_GRCPF_REG_SYNC_TIME));
3756         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3757                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3758         return ns;
3759 }
3760
3761 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3762 {
3763         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3764         uint32_t fifo;
3765
3766         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3767                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3768         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3769                 return -EAGAIN;
3770
3771         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3772                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3773         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3774                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3775         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3776                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3777
3778         return 0;
3779 }
3780
3781 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3782 {
3783         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3784         struct bnxt_pf_info *pf = bp->pf;
3785         uint16_t port_id;
3786         uint32_t fifo;
3787
3788         if (!ptp)
3789                 return -ENODEV;
3790
3791         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3792                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3793         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3794                 return -EAGAIN;
3795
3796         port_id = pf->port_id;
3797         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3798                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3799
3800         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3801                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3802         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3803 /*              bnxt_clr_rx_ts(bp);       TBD  */
3804                 return -EBUSY;
3805         }
3806
3807         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3808                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3809         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3810                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3811
3812         return 0;
3813 }
3814
3815 static int
3816 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3817 {
3818         uint64_t ns;
3819         struct bnxt *bp = dev->data->dev_private;
3820         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3821
3822         if (!ptp)
3823                 return 0;
3824
3825         ns = rte_timespec_to_ns(ts);
3826         /* Set the timecounters to a new value. */
3827         ptp->tc.nsec = ns;
3828
3829         return 0;
3830 }
3831
3832 static int
3833 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3834 {
3835         struct bnxt *bp = dev->data->dev_private;
3836         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3837         uint64_t ns, systime_cycles = 0;
3838         int rc = 0;
3839
3840         if (!ptp)
3841                 return 0;
3842
3843         if (BNXT_CHIP_THOR(bp))
3844                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3845                                              &systime_cycles);
3846         else
3847                 systime_cycles = bnxt_cc_read(bp);
3848
3849         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3850         *ts = rte_ns_to_timespec(ns);
3851
3852         return rc;
3853 }
3854 static int
3855 bnxt_timesync_enable(struct rte_eth_dev *dev)
3856 {
3857         struct bnxt *bp = dev->data->dev_private;
3858         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3859         uint32_t shift = 0;
3860         int rc;
3861
3862         if (!ptp)
3863                 return 0;
3864
3865         ptp->rx_filter = 1;
3866         ptp->tx_tstamp_en = 1;
3867         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3868
3869         rc = bnxt_hwrm_ptp_cfg(bp);
3870         if (rc)
3871                 return rc;
3872
3873         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3874         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3875         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3876
3877         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3878         ptp->tc.cc_shift = shift;
3879         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3880
3881         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3882         ptp->rx_tstamp_tc.cc_shift = shift;
3883         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3884
3885         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3886         ptp->tx_tstamp_tc.cc_shift = shift;
3887         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3888
3889         if (!BNXT_CHIP_THOR(bp))
3890                 bnxt_map_ptp_regs(bp);
3891
3892         return 0;
3893 }
3894
3895 static int
3896 bnxt_timesync_disable(struct rte_eth_dev *dev)
3897 {
3898         struct bnxt *bp = dev->data->dev_private;
3899         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3900
3901         if (!ptp)
3902                 return 0;
3903
3904         ptp->rx_filter = 0;
3905         ptp->tx_tstamp_en = 0;
3906         ptp->rxctl = 0;
3907
3908         bnxt_hwrm_ptp_cfg(bp);
3909
3910         if (!BNXT_CHIP_THOR(bp))
3911                 bnxt_unmap_ptp_regs(bp);
3912
3913         return 0;
3914 }
3915
3916 static int
3917 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3918                                  struct timespec *timestamp,
3919                                  uint32_t flags __rte_unused)
3920 {
3921         struct bnxt *bp = dev->data->dev_private;
3922         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3923         uint64_t rx_tstamp_cycles = 0;
3924         uint64_t ns;
3925
3926         if (!ptp)
3927                 return 0;
3928
3929         if (BNXT_CHIP_THOR(bp))
3930                 rx_tstamp_cycles = ptp->rx_timestamp;
3931         else
3932                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3933
3934         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3935         *timestamp = rte_ns_to_timespec(ns);
3936         return  0;
3937 }
3938
3939 static int
3940 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3941                                  struct timespec *timestamp)
3942 {
3943         struct bnxt *bp = dev->data->dev_private;
3944         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3945         uint64_t tx_tstamp_cycles = 0;
3946         uint64_t ns;
3947         int rc = 0;
3948
3949         if (!ptp)
3950                 return 0;
3951
3952         if (BNXT_CHIP_THOR(bp))
3953                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3954                                              &tx_tstamp_cycles);
3955         else
3956                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3957
3958         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3959         *timestamp = rte_ns_to_timespec(ns);
3960
3961         return rc;
3962 }
3963
3964 static int
3965 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3966 {
3967         struct bnxt *bp = dev->data->dev_private;
3968         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3969
3970         if (!ptp)
3971                 return 0;
3972
3973         ptp->tc.nsec += delta;
3974
3975         return 0;
3976 }
3977
3978 static int
3979 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3980 {
3981         struct bnxt *bp = dev->data->dev_private;
3982         int rc;
3983         uint32_t dir_entries;
3984         uint32_t entry_length;
3985
3986         rc = is_bnxt_in_error(bp);
3987         if (rc)
3988                 return rc;
3989
3990         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3991                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3992                     bp->pdev->addr.devid, bp->pdev->addr.function);
3993
3994         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3995         if (rc != 0)
3996                 return rc;
3997
3998         return dir_entries * entry_length;
3999 }
4000
4001 static int
4002 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4003                 struct rte_dev_eeprom_info *in_eeprom)
4004 {
4005         struct bnxt *bp = dev->data->dev_private;
4006         uint32_t index;
4007         uint32_t offset;
4008         int rc;
4009
4010         rc = is_bnxt_in_error(bp);
4011         if (rc)
4012                 return rc;
4013
4014         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4015                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4016                     bp->pdev->addr.devid, bp->pdev->addr.function,
4017                     in_eeprom->offset, in_eeprom->length);
4018
4019         if (in_eeprom->offset == 0) /* special offset value to get directory */
4020                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4021                                                 in_eeprom->data);
4022
4023         index = in_eeprom->offset >> 24;
4024         offset = in_eeprom->offset & 0xffffff;
4025
4026         if (index != 0)
4027                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4028                                            in_eeprom->length, in_eeprom->data);
4029
4030         return 0;
4031 }
4032
4033 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4034 {
4035         switch (dir_type) {
4036         case BNX_DIR_TYPE_CHIMP_PATCH:
4037         case BNX_DIR_TYPE_BOOTCODE:
4038         case BNX_DIR_TYPE_BOOTCODE_2:
4039         case BNX_DIR_TYPE_APE_FW:
4040         case BNX_DIR_TYPE_APE_PATCH:
4041         case BNX_DIR_TYPE_KONG_FW:
4042         case BNX_DIR_TYPE_KONG_PATCH:
4043         case BNX_DIR_TYPE_BONO_FW:
4044         case BNX_DIR_TYPE_BONO_PATCH:
4045                 /* FALLTHROUGH */
4046                 return true;
4047         }
4048
4049         return false;
4050 }
4051
4052 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4053 {
4054         switch (dir_type) {
4055         case BNX_DIR_TYPE_AVS:
4056         case BNX_DIR_TYPE_EXP_ROM_MBA:
4057         case BNX_DIR_TYPE_PCIE:
4058         case BNX_DIR_TYPE_TSCF_UCODE:
4059         case BNX_DIR_TYPE_EXT_PHY:
4060         case BNX_DIR_TYPE_CCM:
4061         case BNX_DIR_TYPE_ISCSI_BOOT:
4062         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4063         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4064                 /* FALLTHROUGH */
4065                 return true;
4066         }
4067
4068         return false;
4069 }
4070
4071 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4072 {
4073         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4074                 bnxt_dir_type_is_other_exec_format(dir_type);
4075 }
4076
4077 static int
4078 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4079                 struct rte_dev_eeprom_info *in_eeprom)
4080 {
4081         struct bnxt *bp = dev->data->dev_private;
4082         uint8_t index, dir_op;
4083         uint16_t type, ext, ordinal, attr;
4084         int rc;
4085
4086         rc = is_bnxt_in_error(bp);
4087         if (rc)
4088                 return rc;
4089
4090         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4091                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4092                     bp->pdev->addr.devid, bp->pdev->addr.function,
4093                     in_eeprom->offset, in_eeprom->length);
4094
4095         if (!BNXT_PF(bp)) {
4096                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4097                 return -EINVAL;
4098         }
4099
4100         type = in_eeprom->magic >> 16;
4101
4102         if (type == 0xffff) { /* special value for directory operations */
4103                 index = in_eeprom->magic & 0xff;
4104                 dir_op = in_eeprom->magic >> 8;
4105                 if (index == 0)
4106                         return -EINVAL;
4107                 switch (dir_op) {
4108                 case 0x0e: /* erase */
4109                         if (in_eeprom->offset != ~in_eeprom->magic)
4110                                 return -EINVAL;
4111                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4112                 default:
4113                         return -EINVAL;
4114                 }
4115         }
4116
4117         /* Create or re-write an NVM item: */
4118         if (bnxt_dir_type_is_executable(type) == true)
4119                 return -EOPNOTSUPP;
4120         ext = in_eeprom->magic & 0xffff;
4121         ordinal = in_eeprom->offset >> 16;
4122         attr = in_eeprom->offset & 0xffff;
4123
4124         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4125                                      in_eeprom->data, in_eeprom->length);
4126 }
4127
4128 /*
4129  * Initialization
4130  */
4131
4132 static const struct eth_dev_ops bnxt_dev_ops = {
4133         .dev_infos_get = bnxt_dev_info_get_op,
4134         .dev_close = bnxt_dev_close_op,
4135         .dev_configure = bnxt_dev_configure_op,
4136         .dev_start = bnxt_dev_start_op,
4137         .dev_stop = bnxt_dev_stop_op,
4138         .dev_set_link_up = bnxt_dev_set_link_up_op,
4139         .dev_set_link_down = bnxt_dev_set_link_down_op,
4140         .stats_get = bnxt_stats_get_op,
4141         .stats_reset = bnxt_stats_reset_op,
4142         .rx_queue_setup = bnxt_rx_queue_setup_op,
4143         .rx_queue_release = bnxt_rx_queue_release_op,
4144         .tx_queue_setup = bnxt_tx_queue_setup_op,
4145         .tx_queue_release = bnxt_tx_queue_release_op,
4146         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4147         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4148         .reta_update = bnxt_reta_update_op,
4149         .reta_query = bnxt_reta_query_op,
4150         .rss_hash_update = bnxt_rss_hash_update_op,
4151         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4152         .link_update = bnxt_link_update_op,
4153         .promiscuous_enable = bnxt_promiscuous_enable_op,
4154         .promiscuous_disable = bnxt_promiscuous_disable_op,
4155         .allmulticast_enable = bnxt_allmulticast_enable_op,
4156         .allmulticast_disable = bnxt_allmulticast_disable_op,
4157         .mac_addr_add = bnxt_mac_addr_add_op,
4158         .mac_addr_remove = bnxt_mac_addr_remove_op,
4159         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4160         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4161         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4162         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4163         .vlan_filter_set = bnxt_vlan_filter_set_op,
4164         .vlan_offload_set = bnxt_vlan_offload_set_op,
4165         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4166         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4167         .mtu_set = bnxt_mtu_set_op,
4168         .mac_addr_set = bnxt_set_default_mac_addr_op,
4169         .xstats_get = bnxt_dev_xstats_get_op,
4170         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4171         .xstats_reset = bnxt_dev_xstats_reset_op,
4172         .fw_version_get = bnxt_fw_version_get,
4173         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4174         .rxq_info_get = bnxt_rxq_info_get_op,
4175         .txq_info_get = bnxt_txq_info_get_op,
4176         .dev_led_on = bnxt_dev_led_on_op,
4177         .dev_led_off = bnxt_dev_led_off_op,
4178         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4179         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4180         .rx_queue_count = bnxt_rx_queue_count_op,
4181         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
4182         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
4183         .rx_queue_start = bnxt_rx_queue_start,
4184         .rx_queue_stop = bnxt_rx_queue_stop,
4185         .tx_queue_start = bnxt_tx_queue_start,
4186         .tx_queue_stop = bnxt_tx_queue_stop,
4187         .filter_ctrl = bnxt_filter_ctrl_op,
4188         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4189         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4190         .get_eeprom           = bnxt_get_eeprom_op,
4191         .set_eeprom           = bnxt_set_eeprom_op,
4192         .timesync_enable      = bnxt_timesync_enable,
4193         .timesync_disable     = bnxt_timesync_disable,
4194         .timesync_read_time   = bnxt_timesync_read_time,
4195         .timesync_write_time   = bnxt_timesync_write_time,
4196         .timesync_adjust_time = bnxt_timesync_adjust_time,
4197         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4198         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4199 };
4200
4201 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4202 {
4203         uint32_t offset;
4204
4205         /* Only pre-map the reset GRC registers using window 3 */
4206         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4207                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4208
4209         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4210
4211         return offset;
4212 }
4213
4214 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4215 {
4216         struct bnxt_error_recovery_info *info = bp->recovery_info;
4217         uint32_t reg_base = 0xffffffff;
4218         int i;
4219
4220         /* Only pre-map the monitoring GRC registers using window 2 */
4221         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4222                 uint32_t reg = info->status_regs[i];
4223
4224                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4225                         continue;
4226
4227                 if (reg_base == 0xffffffff)
4228                         reg_base = reg & 0xfffff000;
4229                 if ((reg & 0xfffff000) != reg_base)
4230                         return -ERANGE;
4231
4232                 /* Use mask 0xffc as the Lower 2 bits indicates
4233                  * address space location
4234                  */
4235                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4236                                                 (reg & 0xffc);
4237         }
4238
4239         if (reg_base == 0xffffffff)
4240                 return 0;
4241
4242         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4243                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4244
4245         return 0;
4246 }
4247
4248 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4249 {
4250         struct bnxt_error_recovery_info *info = bp->recovery_info;
4251         uint32_t delay = info->delay_after_reset[index];
4252         uint32_t val = info->reset_reg_val[index];
4253         uint32_t reg = info->reset_reg[index];
4254         uint32_t type, offset;
4255
4256         type = BNXT_FW_STATUS_REG_TYPE(reg);
4257         offset = BNXT_FW_STATUS_REG_OFF(reg);
4258
4259         switch (type) {
4260         case BNXT_FW_STATUS_REG_TYPE_CFG:
4261                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4262                 break;
4263         case BNXT_FW_STATUS_REG_TYPE_GRC:
4264                 offset = bnxt_map_reset_regs(bp, offset);
4265                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4266                 break;
4267         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4268                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4269                 break;
4270         }
4271         /* wait on a specific interval of time until core reset is complete */
4272         if (delay)
4273                 rte_delay_ms(delay);
4274 }
4275
4276 static void bnxt_dev_cleanup(struct bnxt *bp)
4277 {
4278         bnxt_set_hwrm_link_config(bp, false);
4279         bp->link_info->link_up = 0;
4280         if (bp->eth_dev->data->dev_started)
4281                 bnxt_dev_stop_op(bp->eth_dev);
4282
4283         bnxt_uninit_resources(bp, true);
4284 }
4285
4286 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4287 {
4288         struct rte_eth_dev *dev = bp->eth_dev;
4289         struct rte_vlan_filter_conf *vfc;
4290         int vidx, vbit, rc;
4291         uint16_t vlan_id;
4292
4293         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4294                 vfc = &dev->data->vlan_filter_conf;
4295                 vidx = vlan_id / 64;
4296                 vbit = vlan_id % 64;
4297
4298                 /* Each bit corresponds to a VLAN id */
4299                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4300                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4301                         if (rc)
4302                                 return rc;
4303                 }
4304         }
4305
4306         return 0;
4307 }
4308
4309 static int bnxt_restore_mac_filters(struct bnxt *bp)
4310 {
4311         struct rte_eth_dev *dev = bp->eth_dev;
4312         struct rte_eth_dev_info dev_info;
4313         struct rte_ether_addr *addr;
4314         uint64_t pool_mask;
4315         uint32_t pool = 0;
4316         uint16_t i;
4317         int rc;
4318
4319         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
4320                 return 0;
4321
4322         rc = bnxt_dev_info_get_op(dev, &dev_info);
4323         if (rc)
4324                 return rc;
4325
4326         /* replay MAC address configuration */
4327         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4328                 addr = &dev->data->mac_addrs[i];
4329
4330                 /* skip zero address */
4331                 if (rte_is_zero_ether_addr(addr))
4332                         continue;
4333
4334                 pool = 0;
4335                 pool_mask = dev->data->mac_pool_sel[i];
4336
4337                 do {
4338                         if (pool_mask & 1ULL) {
4339                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4340                                 if (rc)
4341                                         return rc;
4342                         }
4343                         pool_mask >>= 1;
4344                         pool++;
4345                 } while (pool_mask);
4346         }
4347
4348         return 0;
4349 }
4350
4351 static int bnxt_restore_filters(struct bnxt *bp)
4352 {
4353         struct rte_eth_dev *dev = bp->eth_dev;
4354         int ret = 0;
4355
4356         if (dev->data->all_multicast) {
4357                 ret = bnxt_allmulticast_enable_op(dev);
4358                 if (ret)
4359                         return ret;
4360         }
4361         if (dev->data->promiscuous) {
4362                 ret = bnxt_promiscuous_enable_op(dev);
4363                 if (ret)
4364                         return ret;
4365         }
4366
4367         ret = bnxt_restore_mac_filters(bp);
4368         if (ret)
4369                 return ret;
4370
4371         ret = bnxt_restore_vlan_filters(bp);
4372         /* TODO restore other filters as well */
4373         return ret;
4374 }
4375
4376 static void bnxt_dev_recover(void *arg)
4377 {
4378         struct bnxt *bp = arg;
4379         int timeout = bp->fw_reset_max_msecs;
4380         int rc = 0;
4381
4382         /* Clear Error flag so that device re-init should happen */
4383         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4384
4385         do {
4386                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4387                 if (rc == 0)
4388                         break;
4389                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4390                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4391         } while (rc && timeout);
4392
4393         if (rc) {
4394                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4395                 goto err;
4396         }
4397
4398         rc = bnxt_init_resources(bp, true);
4399         if (rc) {
4400                 PMD_DRV_LOG(ERR,
4401                             "Failed to initialize resources after reset\n");
4402                 goto err;
4403         }
4404         /* clear reset flag as the device is initialized now */
4405         bp->flags &= ~BNXT_FLAG_FW_RESET;
4406
4407         rc = bnxt_dev_start_op(bp->eth_dev);
4408         if (rc) {
4409                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4410                 goto err_start;
4411         }
4412
4413         rc = bnxt_restore_filters(bp);
4414         if (rc)
4415                 goto err_start;
4416
4417         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4418         return;
4419 err_start:
4420         bnxt_dev_stop_op(bp->eth_dev);
4421 err:
4422         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4423         bnxt_uninit_resources(bp, false);
4424         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4425 }
4426
4427 void bnxt_dev_reset_and_resume(void *arg)
4428 {
4429         struct bnxt *bp = arg;
4430         int rc;
4431
4432         bnxt_dev_cleanup(bp);
4433
4434         bnxt_wait_for_device_shutdown(bp);
4435
4436         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4437                                bnxt_dev_recover, (void *)bp);
4438         if (rc)
4439                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4440 }
4441
4442 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4443 {
4444         struct bnxt_error_recovery_info *info = bp->recovery_info;
4445         uint32_t reg = info->status_regs[index];
4446         uint32_t type, offset, val = 0;
4447
4448         type = BNXT_FW_STATUS_REG_TYPE(reg);
4449         offset = BNXT_FW_STATUS_REG_OFF(reg);
4450
4451         switch (type) {
4452         case BNXT_FW_STATUS_REG_TYPE_CFG:
4453                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4454                 break;
4455         case BNXT_FW_STATUS_REG_TYPE_GRC:
4456                 offset = info->mapped_status_regs[index];
4457                 /* FALLTHROUGH */
4458         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4459                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4460                                        offset));
4461                 break;
4462         }
4463
4464         return val;
4465 }
4466
4467 static int bnxt_fw_reset_all(struct bnxt *bp)
4468 {
4469         struct bnxt_error_recovery_info *info = bp->recovery_info;
4470         uint32_t i;
4471         int rc = 0;
4472
4473         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4474                 /* Reset through master function driver */
4475                 for (i = 0; i < info->reg_array_cnt; i++)
4476                         bnxt_write_fw_reset_reg(bp, i);
4477                 /* Wait for time specified by FW after triggering reset */
4478                 rte_delay_ms(info->master_func_wait_period_after_reset);
4479         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4480                 /* Reset with the help of Kong processor */
4481                 rc = bnxt_hwrm_fw_reset(bp);
4482                 if (rc)
4483                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4484         }
4485
4486         return rc;
4487 }
4488
4489 static void bnxt_fw_reset_cb(void *arg)
4490 {
4491         struct bnxt *bp = arg;
4492         struct bnxt_error_recovery_info *info = bp->recovery_info;
4493         int rc = 0;
4494
4495         /* Only Master function can do FW reset */
4496         if (bnxt_is_master_func(bp) &&
4497             bnxt_is_recovery_enabled(bp)) {
4498                 rc = bnxt_fw_reset_all(bp);
4499                 if (rc) {
4500                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4501                         return;
4502                 }
4503         }
4504
4505         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4506          * EXCEPTION_FATAL_ASYNC event to all the functions
4507          * (including MASTER FUNC). After receiving this Async, all the active
4508          * drivers should treat this case as FW initiated recovery
4509          */
4510         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4511                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4512                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4513
4514                 /* To recover from error */
4515                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4516                                   (void *)bp);
4517         }
4518 }
4519
4520 /* Driver should poll FW heartbeat, reset_counter with the frequency
4521  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4522  * When the driver detects heartbeat stop or change in reset_counter,
4523  * it has to trigger a reset to recover from the error condition.
4524  * A “master PF” is the function who will have the privilege to
4525  * initiate the chimp reset. The master PF will be elected by the
4526  * firmware and will be notified through async message.
4527  */
4528 static void bnxt_check_fw_health(void *arg)
4529 {
4530         struct bnxt *bp = arg;
4531         struct bnxt_error_recovery_info *info = bp->recovery_info;
4532         uint32_t val = 0, wait_msec;
4533
4534         if (!info || !bnxt_is_recovery_enabled(bp) ||
4535             is_bnxt_in_error(bp))
4536                 return;
4537
4538         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4539         if (val == info->last_heart_beat)
4540                 goto reset;
4541
4542         info->last_heart_beat = val;
4543
4544         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4545         if (val != info->last_reset_counter)
4546                 goto reset;
4547
4548         info->last_reset_counter = val;
4549
4550         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4551                           bnxt_check_fw_health, (void *)bp);
4552
4553         return;
4554 reset:
4555         /* Stop DMA to/from device */
4556         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4557         bp->flags |= BNXT_FLAG_FW_RESET;
4558
4559         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4560
4561         if (bnxt_is_master_func(bp))
4562                 wait_msec = info->master_func_wait_period;
4563         else
4564                 wait_msec = info->normal_func_wait_period;
4565
4566         rte_eal_alarm_set(US_PER_MS * wait_msec,
4567                           bnxt_fw_reset_cb, (void *)bp);
4568 }
4569
4570 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4571 {
4572         uint32_t polling_freq;
4573
4574         if (!bnxt_is_recovery_enabled(bp))
4575                 return;
4576
4577         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4578                 return;
4579
4580         polling_freq = bp->recovery_info->driver_polling_freq;
4581
4582         rte_eal_alarm_set(US_PER_MS * polling_freq,
4583                           bnxt_check_fw_health, (void *)bp);
4584         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4585 }
4586
4587 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4588 {
4589         if (!bnxt_is_recovery_enabled(bp))
4590                 return;
4591
4592         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4593         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4594 }
4595
4596 static bool bnxt_vf_pciid(uint16_t device_id)
4597 {
4598         switch (device_id) {
4599         case BROADCOM_DEV_ID_57304_VF:
4600         case BROADCOM_DEV_ID_57406_VF:
4601         case BROADCOM_DEV_ID_5731X_VF:
4602         case BROADCOM_DEV_ID_5741X_VF:
4603         case BROADCOM_DEV_ID_57414_VF:
4604         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4605         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4606         case BROADCOM_DEV_ID_58802_VF:
4607         case BROADCOM_DEV_ID_57500_VF1:
4608         case BROADCOM_DEV_ID_57500_VF2:
4609                 /* FALLTHROUGH */
4610                 return true;
4611         default:
4612                 return false;
4613         }
4614 }
4615
4616 static bool bnxt_thor_device(uint16_t device_id)
4617 {
4618         switch (device_id) {
4619         case BROADCOM_DEV_ID_57508:
4620         case BROADCOM_DEV_ID_57504:
4621         case BROADCOM_DEV_ID_57502:
4622         case BROADCOM_DEV_ID_57508_MF1:
4623         case BROADCOM_DEV_ID_57504_MF1:
4624         case BROADCOM_DEV_ID_57502_MF1:
4625         case BROADCOM_DEV_ID_57508_MF2:
4626         case BROADCOM_DEV_ID_57504_MF2:
4627         case BROADCOM_DEV_ID_57502_MF2:
4628         case BROADCOM_DEV_ID_57500_VF1:
4629         case BROADCOM_DEV_ID_57500_VF2:
4630                 /* FALLTHROUGH */
4631                 return true;
4632         default:
4633                 return false;
4634         }
4635 }
4636
4637 bool bnxt_stratus_device(struct bnxt *bp)
4638 {
4639         uint16_t device_id = bp->pdev->id.device_id;
4640
4641         switch (device_id) {
4642         case BROADCOM_DEV_ID_STRATUS_NIC:
4643         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4644         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4645                 /* FALLTHROUGH */
4646                 return true;
4647         default:
4648                 return false;
4649         }
4650 }
4651
4652 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4653 {
4654         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4655         struct bnxt *bp = eth_dev->data->dev_private;
4656
4657         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4658         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4659         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4660         if (!bp->bar0 || !bp->doorbell_base) {
4661                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4662                 return -ENODEV;
4663         }
4664
4665         bp->eth_dev = eth_dev;
4666         bp->pdev = pci_dev;
4667
4668         return 0;
4669 }
4670
4671 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4672                                   struct bnxt_ctx_pg_info *ctx_pg,
4673                                   uint32_t mem_size,
4674                                   const char *suffix,
4675                                   uint16_t idx)
4676 {
4677         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4678         const struct rte_memzone *mz = NULL;
4679         char mz_name[RTE_MEMZONE_NAMESIZE];
4680         rte_iova_t mz_phys_addr;
4681         uint64_t valid_bits = 0;
4682         uint32_t sz;
4683         int i;
4684
4685         if (!mem_size)
4686                 return 0;
4687
4688         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4689                          BNXT_PAGE_SIZE;
4690         rmem->page_size = BNXT_PAGE_SIZE;
4691         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4692         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4693         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4694
4695         valid_bits = PTU_PTE_VALID;
4696
4697         if (rmem->nr_pages > 1) {
4698                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4699                          "bnxt_ctx_pg_tbl%s_%x_%d",
4700                          suffix, idx, bp->eth_dev->data->port_id);
4701                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4702                 mz = rte_memzone_lookup(mz_name);
4703                 if (!mz) {
4704                         mz = rte_memzone_reserve_aligned(mz_name,
4705                                                 rmem->nr_pages * 8,
4706                                                 SOCKET_ID_ANY,
4707                                                 RTE_MEMZONE_2MB |
4708                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4709                                                 RTE_MEMZONE_IOVA_CONTIG,
4710                                                 BNXT_PAGE_SIZE);
4711                         if (mz == NULL)
4712                                 return -ENOMEM;
4713                 }
4714
4715                 memset(mz->addr, 0, mz->len);
4716                 mz_phys_addr = mz->iova;
4717
4718                 rmem->pg_tbl = mz->addr;
4719                 rmem->pg_tbl_map = mz_phys_addr;
4720                 rmem->pg_tbl_mz = mz;
4721         }
4722
4723         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4724                  suffix, idx, bp->eth_dev->data->port_id);
4725         mz = rte_memzone_lookup(mz_name);
4726         if (!mz) {
4727                 mz = rte_memzone_reserve_aligned(mz_name,
4728                                                  mem_size,
4729                                                  SOCKET_ID_ANY,
4730                                                  RTE_MEMZONE_1GB |
4731                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4732                                                  RTE_MEMZONE_IOVA_CONTIG,
4733                                                  BNXT_PAGE_SIZE);
4734                 if (mz == NULL)
4735                         return -ENOMEM;
4736         }
4737
4738         memset(mz->addr, 0, mz->len);
4739         mz_phys_addr = mz->iova;
4740
4741         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4742                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4743                 rmem->dma_arr[i] = mz_phys_addr + sz;
4744
4745                 if (rmem->nr_pages > 1) {
4746                         if (i == rmem->nr_pages - 2 &&
4747                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4748                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4749                         else if (i == rmem->nr_pages - 1 &&
4750                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4751                                 valid_bits |= PTU_PTE_LAST;
4752
4753                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4754                                                            valid_bits);
4755                 }
4756         }
4757
4758         rmem->mz = mz;
4759         if (rmem->vmem_size)
4760                 rmem->vmem = (void **)mz->addr;
4761         rmem->dma_arr[0] = mz_phys_addr;
4762         return 0;
4763 }
4764
4765 static void bnxt_free_ctx_mem(struct bnxt *bp)
4766 {
4767         int i;
4768
4769         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4770                 return;
4771
4772         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4773         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4774         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4775         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4776         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4777         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4778         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4779         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4780         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4781         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4782         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4783
4784         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4785                 if (bp->ctx->tqm_mem[i])
4786                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4787         }
4788
4789         rte_free(bp->ctx);
4790         bp->ctx = NULL;
4791 }
4792
4793 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4794
4795 #define min_t(type, x, y) ({                    \
4796         type __min1 = (x);                      \
4797         type __min2 = (y);                      \
4798         __min1 < __min2 ? __min1 : __min2; })
4799
4800 #define max_t(type, x, y) ({                    \
4801         type __max1 = (x);                      \
4802         type __max2 = (y);                      \
4803         __max1 > __max2 ? __max1 : __max2; })
4804
4805 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4806
4807 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4808 {
4809         struct bnxt_ctx_pg_info *ctx_pg;
4810         struct bnxt_ctx_mem_info *ctx;
4811         uint32_t mem_size, ena, entries;
4812         uint32_t entries_sp, min;
4813         int i, rc;
4814
4815         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4816         if (rc) {
4817                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4818                 return rc;
4819         }
4820         ctx = bp->ctx;
4821         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4822                 return 0;
4823
4824         ctx_pg = &ctx->qp_mem;
4825         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4826         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4827         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4828         if (rc)
4829                 return rc;
4830
4831         ctx_pg = &ctx->srq_mem;
4832         ctx_pg->entries = ctx->srq_max_l2_entries;
4833         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4834         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4835         if (rc)
4836                 return rc;
4837
4838         ctx_pg = &ctx->cq_mem;
4839         ctx_pg->entries = ctx->cq_max_l2_entries;
4840         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4841         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4842         if (rc)
4843                 return rc;
4844
4845         ctx_pg = &ctx->vnic_mem;
4846         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4847                 ctx->vnic_max_ring_table_entries;
4848         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4849         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4850         if (rc)
4851                 return rc;
4852
4853         ctx_pg = &ctx->stat_mem;
4854         ctx_pg->entries = ctx->stat_max_entries;
4855         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4856         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4857         if (rc)
4858                 return rc;
4859
4860         min = ctx->tqm_min_entries_per_ring;
4861
4862         entries_sp = ctx->qp_max_l2_entries +
4863                      ctx->vnic_max_vnic_entries +
4864                      2 * ctx->qp_min_qp1_entries + min;
4865         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4866
4867         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4868         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4869         entries = clamp_t(uint32_t, entries, min,
4870                           ctx->tqm_max_entries_per_ring);
4871         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4872                 ctx_pg = ctx->tqm_mem[i];
4873                 ctx_pg->entries = i ? entries : entries_sp;
4874                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4875                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4876                 if (rc)
4877                         return rc;
4878                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4879         }
4880
4881         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4882         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4883         if (rc)
4884                 PMD_DRV_LOG(ERR,
4885                             "Failed to configure context mem: rc = %d\n", rc);
4886         else
4887                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4888
4889         return rc;
4890 }
4891
4892 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4893 {
4894         struct rte_pci_device *pci_dev = bp->pdev;
4895         char mz_name[RTE_MEMZONE_NAMESIZE];
4896         const struct rte_memzone *mz = NULL;
4897         uint32_t total_alloc_len;
4898         rte_iova_t mz_phys_addr;
4899
4900         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4901                 return 0;
4902
4903         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4904                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4905                  pci_dev->addr.bus, pci_dev->addr.devid,
4906                  pci_dev->addr.function, "rx_port_stats");
4907         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4908         mz = rte_memzone_lookup(mz_name);
4909         total_alloc_len =
4910                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4911                                        sizeof(struct rx_port_stats_ext) + 512);
4912         if (!mz) {
4913                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4914                                          SOCKET_ID_ANY,
4915                                          RTE_MEMZONE_2MB |
4916                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4917                                          RTE_MEMZONE_IOVA_CONTIG);
4918                 if (mz == NULL)
4919                         return -ENOMEM;
4920         }
4921         memset(mz->addr, 0, mz->len);
4922         mz_phys_addr = mz->iova;
4923
4924         bp->rx_mem_zone = (const void *)mz;
4925         bp->hw_rx_port_stats = mz->addr;
4926         bp->hw_rx_port_stats_map = mz_phys_addr;
4927
4928         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4929                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4930                  pci_dev->addr.bus, pci_dev->addr.devid,
4931                  pci_dev->addr.function, "tx_port_stats");
4932         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4933         mz = rte_memzone_lookup(mz_name);
4934         total_alloc_len =
4935                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4936                                        sizeof(struct tx_port_stats_ext) + 512);
4937         if (!mz) {
4938                 mz = rte_memzone_reserve(mz_name,
4939                                          total_alloc_len,
4940                                          SOCKET_ID_ANY,
4941                                          RTE_MEMZONE_2MB |
4942                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4943                                          RTE_MEMZONE_IOVA_CONTIG);
4944                 if (mz == NULL)
4945                         return -ENOMEM;
4946         }
4947         memset(mz->addr, 0, mz->len);
4948         mz_phys_addr = mz->iova;
4949
4950         bp->tx_mem_zone = (const void *)mz;
4951         bp->hw_tx_port_stats = mz->addr;
4952         bp->hw_tx_port_stats_map = mz_phys_addr;
4953         bp->flags |= BNXT_FLAG_PORT_STATS;
4954
4955         /* Display extended statistics if FW supports it */
4956         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4957             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4958             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4959                 return 0;
4960
4961         bp->hw_rx_port_stats_ext = (void *)
4962                 ((uint8_t *)bp->hw_rx_port_stats +
4963                  sizeof(struct rx_port_stats));
4964         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4965                 sizeof(struct rx_port_stats);
4966         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4967
4968         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4969             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4970                 bp->hw_tx_port_stats_ext = (void *)
4971                         ((uint8_t *)bp->hw_tx_port_stats +
4972                          sizeof(struct tx_port_stats));
4973                 bp->hw_tx_port_stats_ext_map =
4974                         bp->hw_tx_port_stats_map +
4975                         sizeof(struct tx_port_stats);
4976                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4977         }
4978
4979         return 0;
4980 }
4981
4982 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4983 {
4984         struct bnxt *bp = eth_dev->data->dev_private;
4985         int rc = 0;
4986
4987         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4988                                                RTE_ETHER_ADDR_LEN *
4989                                                bp->max_l2_ctx,
4990                                                0);
4991         if (eth_dev->data->mac_addrs == NULL) {
4992                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4993                 return -ENOMEM;
4994         }
4995
4996         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4997                 if (BNXT_PF(bp))
4998                         return -EINVAL;
4999
5000                 /* Generate a random MAC address, if none was assigned by PF */
5001                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5002                 bnxt_eth_hw_addr_random(bp->mac_addr);
5003                 PMD_DRV_LOG(INFO,
5004                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5005                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5006                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5007
5008                 rc = bnxt_hwrm_set_mac(bp);
5009                 if (rc)
5010                         return rc;
5011         }
5012
5013         /* Copy the permanent MAC from the FUNC_QCAPS response */
5014         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5015
5016         return rc;
5017 }
5018
5019 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5020 {
5021         int rc = 0;
5022
5023         /* MAC is already configured in FW */
5024         if (BNXT_HAS_DFLT_MAC_SET(bp))
5025                 return 0;
5026
5027         /* Restore the old MAC configured */
5028         rc = bnxt_hwrm_set_mac(bp);
5029         if (rc)
5030                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5031
5032         return rc;
5033 }
5034
5035 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5036 {
5037         if (!BNXT_PF(bp))
5038                 return;
5039
5040 #define ALLOW_FUNC(x)   \
5041         { \
5042                 uint32_t arg = (x); \
5043                 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5044                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5045         }
5046
5047         /* Forward all requests if firmware is new enough */
5048         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5049              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5050             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5051                 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5052         } else {
5053                 PMD_DRV_LOG(WARNING,
5054                             "Firmware too old for VF mailbox functionality\n");
5055                 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5056         }
5057
5058         /*
5059          * The following are used for driver cleanup. If we disallow these,
5060          * VF drivers can't clean up cleanly.
5061          */
5062         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5063         ALLOW_FUNC(HWRM_VNIC_FREE);
5064         ALLOW_FUNC(HWRM_RING_FREE);
5065         ALLOW_FUNC(HWRM_RING_GRP_FREE);
5066         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5067         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5068         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5069         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5070         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5071 }
5072
5073 uint16_t
5074 bnxt_get_svif(uint16_t port_id, bool func_svif)
5075 {
5076         struct rte_eth_dev *eth_dev;
5077         struct bnxt *bp;
5078
5079         eth_dev = &rte_eth_devices[port_id];
5080         bp = eth_dev->data->dev_private;
5081
5082         return func_svif ? bp->func_svif : bp->port_svif;
5083 }
5084
5085 uint16_t
5086 bnxt_get_vnic_id(uint16_t port)
5087 {
5088         struct rte_eth_dev *eth_dev;
5089         struct bnxt_vnic_info *vnic;
5090         struct bnxt *bp;
5091
5092         eth_dev = &rte_eth_devices[port];
5093         bp = eth_dev->data->dev_private;
5094
5095         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5096
5097         return vnic->fw_vnic_id;
5098 }
5099
5100 uint16_t
5101 bnxt_get_fw_func_id(uint16_t port)
5102 {
5103         struct rte_eth_dev *eth_dev;
5104         struct bnxt *bp;
5105
5106         eth_dev = &rte_eth_devices[port];
5107         bp = eth_dev->data->dev_private;
5108
5109         return bp->fw_fid;
5110 }
5111
5112 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5113 {
5114         struct bnxt_error_recovery_info *info = bp->recovery_info;
5115
5116         if (info) {
5117                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5118                         memset(info, 0, sizeof(*info));
5119                 return;
5120         }
5121
5122         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5123                 return;
5124
5125         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5126                            sizeof(*info), 0);
5127         if (!info)
5128                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5129
5130         bp->recovery_info = info;
5131 }
5132
5133 static void bnxt_check_fw_status(struct bnxt *bp)
5134 {
5135         uint32_t fw_status;
5136
5137         if (!(bp->recovery_info &&
5138               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5139                 return;
5140
5141         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5142         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5143                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5144                             fw_status);
5145 }
5146
5147 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5148 {
5149         struct bnxt_error_recovery_info *info = bp->recovery_info;
5150         uint32_t status_loc;
5151         uint32_t sig_ver;
5152
5153         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5154                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5155         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5156                                    BNXT_GRCP_WINDOW_2_BASE +
5157                                    offsetof(struct hcomm_status,
5158                                             sig_ver)));
5159         /* If the signature is absent, then FW does not support this feature */
5160         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5161             HCOMM_STATUS_SIGNATURE_VAL)
5162                 return 0;
5163
5164         if (!info) {
5165                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5166                                    sizeof(*info), 0);
5167                 if (!info)
5168                         return -ENOMEM;
5169                 bp->recovery_info = info;
5170         } else {
5171                 memset(info, 0, sizeof(*info));
5172         }
5173
5174         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5175                                       BNXT_GRCP_WINDOW_2_BASE +
5176                                       offsetof(struct hcomm_status,
5177                                                fw_status_loc)));
5178
5179         /* Only pre-map the FW health status GRC register */
5180         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5181                 return 0;
5182
5183         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5184         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5185                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5186
5187         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5188                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5189
5190         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5191
5192         return 0;
5193 }
5194
5195 static int bnxt_init_fw(struct bnxt *bp)
5196 {
5197         uint16_t mtu;
5198         int rc = 0;
5199
5200         bp->fw_cap = 0;
5201
5202         rc = bnxt_map_hcomm_fw_status_reg(bp);
5203         if (rc)
5204                 return rc;
5205
5206         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5207         if (rc) {
5208                 bnxt_check_fw_status(bp);
5209                 return rc;
5210         }
5211
5212         rc = bnxt_hwrm_func_reset(bp);
5213         if (rc)
5214                 return -EIO;
5215
5216         rc = bnxt_hwrm_vnic_qcaps(bp);
5217         if (rc)
5218                 return rc;
5219
5220         rc = bnxt_hwrm_queue_qportcfg(bp);
5221         if (rc)
5222                 return rc;
5223
5224         /* Get the MAX capabilities for this function.
5225          * This function also allocates context memory for TQM rings and
5226          * informs the firmware about this allocated backing store memory.
5227          */
5228         rc = bnxt_hwrm_func_qcaps(bp);
5229         if (rc)
5230                 return rc;
5231
5232         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5233         if (rc)
5234                 return rc;
5235
5236         bnxt_hwrm_port_mac_qcfg(bp);
5237
5238         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5239         if (rc)
5240                 return rc;
5241
5242         bnxt_alloc_error_recovery_info(bp);
5243         /* Get the adapter error recovery support info */
5244         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5245         if (rc)
5246                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5247
5248         bnxt_hwrm_port_led_qcaps(bp);
5249
5250         return 0;
5251 }
5252
5253 static int
5254 bnxt_init_locks(struct bnxt *bp)
5255 {
5256         int err;
5257
5258         err = pthread_mutex_init(&bp->flow_lock, NULL);
5259         if (err) {
5260                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5261                 return err;
5262         }
5263
5264         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5265         if (err)
5266                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5267         return err;
5268 }
5269
5270 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5271 {
5272         int rc;
5273
5274         rc = bnxt_init_fw(bp);
5275         if (rc)
5276                 return rc;
5277
5278         if (!reconfig_dev) {
5279                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5280                 if (rc)
5281                         return rc;
5282         } else {
5283                 rc = bnxt_restore_dflt_mac(bp);
5284                 if (rc)
5285                         return rc;
5286         }
5287
5288         bnxt_config_vf_req_fwd(bp);
5289
5290         rc = bnxt_hwrm_func_driver_register(bp);
5291         if (rc) {
5292                 PMD_DRV_LOG(ERR, "Failed to register driver");
5293                 return -EBUSY;
5294         }
5295
5296         if (BNXT_PF(bp)) {
5297                 if (bp->pdev->max_vfs) {
5298                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5299                         if (rc) {
5300                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5301                                 return rc;
5302                         }
5303                 } else {
5304                         rc = bnxt_hwrm_allocate_pf_only(bp);
5305                         if (rc) {
5306                                 PMD_DRV_LOG(ERR,
5307                                             "Failed to allocate PF resources");
5308                                 return rc;
5309                         }
5310                 }
5311         }
5312
5313         rc = bnxt_alloc_mem(bp, reconfig_dev);
5314         if (rc)
5315                 return rc;
5316
5317         rc = bnxt_setup_int(bp);
5318         if (rc)
5319                 return rc;
5320
5321         rc = bnxt_request_int(bp);
5322         if (rc)
5323                 return rc;
5324
5325         rc = bnxt_init_ctx_mem(bp);
5326         if (rc) {
5327                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5328                 return rc;
5329         }
5330
5331         rc = bnxt_init_locks(bp);
5332         if (rc)
5333                 return rc;
5334
5335         return 0;
5336 }
5337
5338 static int
5339 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5340                           const char *value, void *opaque_arg)
5341 {
5342         struct bnxt *bp = opaque_arg;
5343         unsigned long truflow;
5344         char *end = NULL;
5345
5346         if (!value || !opaque_arg) {
5347                 PMD_DRV_LOG(ERR,
5348                             "Invalid parameter passed to truflow devargs.\n");
5349                 return -EINVAL;
5350         }
5351
5352         truflow = strtoul(value, &end, 10);
5353         if (end == NULL || *end != '\0' ||
5354             (truflow == ULONG_MAX && errno == ERANGE)) {
5355                 PMD_DRV_LOG(ERR,
5356                             "Invalid parameter passed to truflow devargs.\n");
5357                 return -EINVAL;
5358         }
5359
5360         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5361                 PMD_DRV_LOG(ERR,
5362                             "Invalid value passed to truflow devargs.\n");
5363                 return -EINVAL;
5364         }
5365
5366         bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5367         if (BNXT_TRUFLOW_EN(bp))
5368                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5369
5370         return 0;
5371 }
5372
5373 static int
5374 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5375                              const char *value, void *opaque_arg)
5376 {
5377         struct bnxt *bp = opaque_arg;
5378         unsigned long flow_xstat;
5379         char *end = NULL;
5380
5381         if (!value || !opaque_arg) {
5382                 PMD_DRV_LOG(ERR,
5383                             "Invalid parameter passed to flow_xstat devarg.\n");
5384                 return -EINVAL;
5385         }
5386
5387         flow_xstat = strtoul(value, &end, 10);
5388         if (end == NULL || *end != '\0' ||
5389             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5390                 PMD_DRV_LOG(ERR,
5391                             "Invalid parameter passed to flow_xstat devarg.\n");
5392                 return -EINVAL;
5393         }
5394
5395         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5396                 PMD_DRV_LOG(ERR,
5397                             "Invalid value passed to flow_xstat devarg.\n");
5398                 return -EINVAL;
5399         }
5400
5401         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5402         if (BNXT_FLOW_XSTATS_EN(bp))
5403                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5404
5405         return 0;
5406 }
5407
5408 static int
5409 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5410                                         const char *value, void *opaque_arg)
5411 {
5412         struct bnxt *bp = opaque_arg;
5413         unsigned long max_num_kflows;
5414         char *end = NULL;
5415
5416         if (!value || !opaque_arg) {
5417                 PMD_DRV_LOG(ERR,
5418                         "Invalid parameter passed to max_num_kflows devarg.\n");
5419                 return -EINVAL;
5420         }
5421
5422         max_num_kflows = strtoul(value, &end, 10);
5423         if (end == NULL || *end != '\0' ||
5424                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5425                 PMD_DRV_LOG(ERR,
5426                         "Invalid parameter passed to max_num_kflows devarg.\n");
5427                 return -EINVAL;
5428         }
5429
5430         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5431                 PMD_DRV_LOG(ERR,
5432                         "Invalid value passed to max_num_kflows devarg.\n");
5433                 return -EINVAL;
5434         }
5435
5436         bp->max_num_kflows = max_num_kflows;
5437         if (bp->max_num_kflows)
5438                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5439                                 max_num_kflows);
5440
5441         return 0;
5442 }
5443
5444 static void
5445 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5446 {
5447         struct rte_kvargs *kvlist;
5448
5449         if (devargs == NULL)
5450                 return;
5451
5452         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5453         if (kvlist == NULL)
5454                 return;
5455
5456         /*
5457          * Handler for "truflow" devarg.
5458          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5459          */
5460         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5461                            bnxt_parse_devarg_truflow, bp);
5462
5463         /*
5464          * Handler for "flow_xstat" devarg.
5465          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5466          */
5467         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5468                            bnxt_parse_devarg_flow_xstat, bp);
5469
5470         /*
5471          * Handler for "max_num_kflows" devarg.
5472          * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5473          */
5474         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5475                            bnxt_parse_devarg_max_num_kflows, bp);
5476
5477         rte_kvargs_free(kvlist);
5478 }
5479
5480 static int
5481 bnxt_dev_init(struct rte_eth_dev *eth_dev)
5482 {
5483         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5484         static int version_printed;
5485         struct bnxt *bp;
5486         int rc;
5487
5488         if (version_printed++ == 0)
5489                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5490
5491         eth_dev->dev_ops = &bnxt_dev_ops;
5492         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5493         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5494
5495         /*
5496          * For secondary processes, we don't initialise any further
5497          * as primary has already done this work.
5498          */
5499         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5500                 return 0;
5501
5502         rte_eth_copy_pci_info(eth_dev, pci_dev);
5503
5504         bp = eth_dev->data->dev_private;
5505
5506         /* Parse dev arguments passed on when starting the DPDK application. */
5507         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5508
5509         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5510
5511         if (bnxt_vf_pciid(pci_dev->id.device_id))
5512                 bp->flags |= BNXT_FLAG_VF;
5513
5514         if (bnxt_thor_device(pci_dev->id.device_id))
5515                 bp->flags |= BNXT_FLAG_THOR_CHIP;
5516
5517         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5518             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5519             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5520             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5521                 bp->flags |= BNXT_FLAG_STINGRAY;
5522
5523         rc = bnxt_init_board(eth_dev);
5524         if (rc) {
5525                 PMD_DRV_LOG(ERR,
5526                             "Failed to initialize board rc: %x\n", rc);
5527                 return rc;
5528         }
5529
5530         rc = bnxt_alloc_pf_info(bp);
5531         if (rc)
5532                 goto error_free;
5533
5534         rc = bnxt_alloc_link_info(bp);
5535         if (rc)
5536                 goto error_free;
5537
5538         rc = bnxt_alloc_hwrm_resources(bp);
5539         if (rc) {
5540                 PMD_DRV_LOG(ERR,
5541                             "Failed to allocate hwrm resource rc: %x\n", rc);
5542                 goto error_free;
5543         }
5544         rc = bnxt_alloc_leds_info(bp);
5545         if (rc)
5546                 goto error_free;
5547
5548         rc = bnxt_alloc_cos_queues(bp);
5549         if (rc)
5550                 goto error_free;
5551
5552         rc = bnxt_init_resources(bp, false);
5553         if (rc)
5554                 goto error_free;
5555
5556         rc = bnxt_alloc_stats_mem(bp);
5557         if (rc)
5558                 goto error_free;
5559
5560         /* Pass the information to the rte_eth_dev_close() that it should also
5561          * release the private port resources.
5562          */
5563         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5564
5565         PMD_DRV_LOG(INFO,
5566                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5567                     pci_dev->mem_resource[0].phys_addr,
5568                     pci_dev->mem_resource[0].addr);
5569
5570         return 0;
5571
5572 error_free:
5573         bnxt_dev_uninit(eth_dev);
5574         return rc;
5575 }
5576
5577
5578 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5579 {
5580         if (!ctx)
5581                 return;
5582
5583         if (ctx->va)
5584                 rte_free(ctx->va);
5585
5586         ctx->va = NULL;
5587         ctx->dma = RTE_BAD_IOVA;
5588         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5589 }
5590
5591 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5592 {
5593         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5594                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5595                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5596                                   bp->flow_stat->max_fc,
5597                                   false);
5598
5599         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5600                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5601                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5602                                   bp->flow_stat->max_fc,
5603                                   false);
5604
5605         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5606                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5607         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5608
5609         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5610                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5611         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5612
5613         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5614                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5615         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5616
5617         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5618                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5619         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5620 }
5621
5622 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5623 {
5624         bnxt_unregister_fc_ctx_mem(bp);
5625
5626         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5627         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5628         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5629         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5630 }
5631
5632 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5633 {
5634         if (BNXT_FLOW_XSTATS_EN(bp))
5635                 bnxt_uninit_fc_ctx_mem(bp);
5636 }
5637
5638 static void
5639 bnxt_free_error_recovery_info(struct bnxt *bp)
5640 {
5641         rte_free(bp->recovery_info);
5642         bp->recovery_info = NULL;
5643         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5644 }
5645
5646 static void
5647 bnxt_uninit_locks(struct bnxt *bp)
5648 {
5649         pthread_mutex_destroy(&bp->flow_lock);
5650         pthread_mutex_destroy(&bp->def_cp_lock);
5651 }
5652
5653 static int
5654 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5655 {
5656         int rc;
5657
5658         bnxt_free_int(bp);
5659         bnxt_free_mem(bp, reconfig_dev);
5660         bnxt_hwrm_func_buf_unrgtr(bp);
5661         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5662         bp->flags &= ~BNXT_FLAG_REGISTERED;
5663         bnxt_free_ctx_mem(bp);
5664         if (!reconfig_dev) {
5665                 bnxt_free_hwrm_resources(bp);
5666                 bnxt_free_error_recovery_info(bp);
5667         }
5668
5669         bnxt_uninit_ctx_mem(bp);
5670
5671         bnxt_uninit_locks(bp);
5672         bnxt_free_flow_stats_info(bp);
5673         rte_free(bp->ptp_cfg);
5674         bp->ptp_cfg = NULL;
5675         return rc;
5676 }
5677
5678 static int
5679 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5680 {
5681         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5682                 return -EPERM;
5683
5684         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5685
5686         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5687                 bnxt_dev_close_op(eth_dev);
5688
5689         return 0;
5690 }
5691
5692 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5693         struct rte_pci_device *pci_dev)
5694 {
5695         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
5696                 bnxt_dev_init);
5697 }
5698
5699 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5700 {
5701         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
5702                 return rte_eth_dev_pci_generic_remove(pci_dev,
5703                                 bnxt_dev_uninit);
5704         else
5705                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5706 }
5707
5708 static struct rte_pci_driver bnxt_rte_pmd = {
5709         .id_table = bnxt_pci_id_map,
5710         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5711         .probe = bnxt_pci_probe,
5712         .remove = bnxt_pci_remove,
5713 };
5714
5715 static bool
5716 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5717 {
5718         if (strcmp(dev->device->driver->name, drv->driver.name))
5719                 return false;
5720
5721         return true;
5722 }
5723
5724 bool is_bnxt_supported(struct rte_eth_dev *dev)
5725 {
5726         return is_device_supported(dev, &bnxt_rte_pmd);
5727 }
5728
5729 RTE_INIT(bnxt_init_log)
5730 {
5731         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
5732         if (bnxt_logtype_driver >= 0)
5733                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
5734 }
5735
5736 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5737 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5738 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");