1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
18 #include "bnxt_filter.h"
19 #include "bnxt_hwrm.h"
21 #include "bnxt_reps.h"
22 #include "bnxt_ring.h"
25 #include "bnxt_stats.h"
28 #include "bnxt_vnic.h"
29 #include "hsi_struct_def_dpdk.h"
30 #include "bnxt_nvm_defs.h"
31 #include "bnxt_tf_common.h"
32 #include "ulp_flow_db.h"
34 #define DRV_MODULE_NAME "bnxt"
35 static const char bnxt_version[] =
36 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
39 * The set of PCI devices this driver supports
41 static const struct rte_pci_id bnxt_pci_id_map[] = {
42 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
43 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
95 { .vendor_id = 0, /* sentinel */ },
98 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
99 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
100 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
101 #define BNXT_DEVARG_REPRESENTOR "representor"
103 static const char *const bnxt_dev_args[] = {
104 BNXT_DEVARG_REPRESENTOR,
106 BNXT_DEVARG_FLOW_XSTAT,
107 BNXT_DEVARG_MAX_NUM_KFLOWS,
112 * truflow == false to disable the feature
113 * truflow == true to enable the feature
115 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
118 * flow_xstat == false to disable the feature
119 * flow_xstat == true to enable the feature
121 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
124 * max_num_kflows must be >= 32
125 * and must be a power-of-2 supported value
126 * return: 1 -> invalid
129 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
131 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
136 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
137 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
138 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
139 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
140 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
141 static int bnxt_restore_vlan_filters(struct bnxt *bp);
142 static void bnxt_dev_recover(void *arg);
143 static void bnxt_free_error_recovery_info(struct bnxt *bp);
144 static void bnxt_free_rep_info(struct bnxt *bp);
146 int is_bnxt_in_error(struct bnxt *bp)
148 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
150 if (bp->flags & BNXT_FLAG_FW_RESET)
156 /***********************/
159 * High level utility functions
162 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
164 if (!BNXT_CHIP_THOR(bp))
167 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
168 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
169 BNXT_RSS_ENTRIES_PER_CTX_THOR;
172 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
174 if (!BNXT_CHIP_THOR(bp))
175 return HW_HASH_INDEX_SIZE;
177 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
180 static void bnxt_free_parent_info(struct bnxt *bp)
182 rte_free(bp->parent);
185 static void bnxt_free_pf_info(struct bnxt *bp)
190 static void bnxt_free_link_info(struct bnxt *bp)
192 rte_free(bp->link_info);
195 static void bnxt_free_leds_info(struct bnxt *bp)
204 static void bnxt_free_flow_stats_info(struct bnxt *bp)
206 rte_free(bp->flow_stat);
207 bp->flow_stat = NULL;
210 static void bnxt_free_cos_queues(struct bnxt *bp)
212 rte_free(bp->rx_cos_queue);
213 rte_free(bp->tx_cos_queue);
216 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
218 bnxt_free_filter_mem(bp);
219 bnxt_free_vnic_attributes(bp);
220 bnxt_free_vnic_mem(bp);
222 /* tx/rx rings are configured as part of *_queue_setup callbacks.
223 * If the number of rings change across fw update,
224 * we don't have much choice except to warn the user.
228 bnxt_free_tx_rings(bp);
229 bnxt_free_rx_rings(bp);
231 bnxt_free_async_cp_ring(bp);
232 bnxt_free_rxtx_nq_ring(bp);
234 rte_free(bp->grp_info);
238 static int bnxt_alloc_parent_info(struct bnxt *bp)
240 bp->parent = rte_zmalloc("bnxt_parent_info",
241 sizeof(struct bnxt_parent_info), 0);
242 if (bp->parent == NULL)
248 static int bnxt_alloc_pf_info(struct bnxt *bp)
250 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
257 static int bnxt_alloc_link_info(struct bnxt *bp)
260 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
261 if (bp->link_info == NULL)
267 static int bnxt_alloc_leds_info(struct bnxt *bp)
272 bp->leds = rte_zmalloc("bnxt_leds",
273 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
275 if (bp->leds == NULL)
281 static int bnxt_alloc_cos_queues(struct bnxt *bp)
284 rte_zmalloc("bnxt_rx_cosq",
285 BNXT_COS_QUEUE_COUNT *
286 sizeof(struct bnxt_cos_queue_info),
288 if (bp->rx_cos_queue == NULL)
292 rte_zmalloc("bnxt_tx_cosq",
293 BNXT_COS_QUEUE_COUNT *
294 sizeof(struct bnxt_cos_queue_info),
296 if (bp->tx_cos_queue == NULL)
302 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
304 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
305 sizeof(struct bnxt_flow_stat_info), 0);
306 if (bp->flow_stat == NULL)
312 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
316 rc = bnxt_alloc_ring_grps(bp);
320 rc = bnxt_alloc_async_ring_struct(bp);
324 rc = bnxt_alloc_vnic_mem(bp);
328 rc = bnxt_alloc_vnic_attributes(bp);
332 rc = bnxt_alloc_filter_mem(bp);
336 rc = bnxt_alloc_async_cp_ring(bp);
340 rc = bnxt_alloc_rxtx_nq_ring(bp);
344 if (BNXT_FLOW_XSTATS_EN(bp)) {
345 rc = bnxt_alloc_flow_stats_info(bp);
353 bnxt_free_mem(bp, reconfig);
357 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
359 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
360 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
361 uint64_t rx_offloads = dev_conf->rxmode.offloads;
362 struct bnxt_rx_queue *rxq;
366 rc = bnxt_vnic_grp_alloc(bp, vnic);
370 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
371 vnic_id, vnic, vnic->fw_grp_ids);
373 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
377 /* Alloc RSS context only if RSS mode is enabled */
378 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
379 int j, nr_ctxs = bnxt_rss_ctxts(bp);
382 for (j = 0; j < nr_ctxs; j++) {
383 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
389 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
393 vnic->num_lb_ctxts = nr_ctxs;
397 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
398 * setting is not available at this time, it will not be
399 * configured correctly in the CFA.
401 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
402 vnic->vlan_strip = true;
404 vnic->vlan_strip = false;
406 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
410 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
414 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
415 rxq = bp->eth_dev->data->rx_queues[j];
418 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
419 j, rxq->vnic, rxq->vnic->fw_grp_ids);
421 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
422 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
424 vnic->rx_queue_cnt++;
427 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
429 rc = bnxt_vnic_rss_configure(bp, vnic);
433 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
435 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
436 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
438 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
442 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
447 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
451 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
452 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
457 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
458 " rx_fc_in_tbl.ctx_id = %d\n",
459 bp->flow_stat->rx_fc_in_tbl.va,
460 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
461 bp->flow_stat->rx_fc_in_tbl.ctx_id);
463 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
464 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
469 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
470 " rx_fc_out_tbl.ctx_id = %d\n",
471 bp->flow_stat->rx_fc_out_tbl.va,
472 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
473 bp->flow_stat->rx_fc_out_tbl.ctx_id);
475 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
476 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
481 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
482 " tx_fc_in_tbl.ctx_id = %d\n",
483 bp->flow_stat->tx_fc_in_tbl.va,
484 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
485 bp->flow_stat->tx_fc_in_tbl.ctx_id);
487 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
488 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
493 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
494 " tx_fc_out_tbl.ctx_id = %d\n",
495 bp->flow_stat->tx_fc_out_tbl.va,
496 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
497 bp->flow_stat->tx_fc_out_tbl.ctx_id);
499 memset(bp->flow_stat->rx_fc_out_tbl.va,
501 bp->flow_stat->rx_fc_out_tbl.size);
502 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
503 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
504 bp->flow_stat->rx_fc_out_tbl.ctx_id,
505 bp->flow_stat->max_fc,
510 memset(bp->flow_stat->tx_fc_out_tbl.va,
512 bp->flow_stat->tx_fc_out_tbl.size);
513 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
514 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
515 bp->flow_stat->tx_fc_out_tbl.ctx_id,
516 bp->flow_stat->max_fc,
522 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
523 struct bnxt_ctx_mem_buf_info *ctx)
528 ctx->va = rte_zmalloc(type, size, 0);
531 rte_mem_lock_page(ctx->va);
533 ctx->dma = rte_mem_virt2iova(ctx->va);
534 if (ctx->dma == RTE_BAD_IOVA)
540 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
542 struct rte_pci_device *pdev = bp->pdev;
543 char type[RTE_MEMZONE_NAMESIZE];
547 max_fc = bp->flow_stat->max_fc;
549 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
550 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
551 /* 4 bytes for each counter-id */
552 rc = bnxt_alloc_ctx_mem_buf(type,
554 &bp->flow_stat->rx_fc_in_tbl);
558 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
559 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
560 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
561 rc = bnxt_alloc_ctx_mem_buf(type,
563 &bp->flow_stat->rx_fc_out_tbl);
567 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
568 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
569 /* 4 bytes for each counter-id */
570 rc = bnxt_alloc_ctx_mem_buf(type,
572 &bp->flow_stat->tx_fc_in_tbl);
576 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
577 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
578 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
579 rc = bnxt_alloc_ctx_mem_buf(type,
581 &bp->flow_stat->tx_fc_out_tbl);
585 rc = bnxt_register_fc_ctx_mem(bp);
590 static int bnxt_init_ctx_mem(struct bnxt *bp)
594 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
595 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
596 !BNXT_FLOW_XSTATS_EN(bp))
599 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
603 rc = bnxt_init_fc_ctx_mem(bp);
608 static int bnxt_init_chip(struct bnxt *bp)
610 struct rte_eth_link new;
611 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
612 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
613 uint32_t intr_vector = 0;
614 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
615 uint32_t vec = BNXT_MISC_VEC_ID;
619 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
620 bp->eth_dev->data->dev_conf.rxmode.offloads |=
621 DEV_RX_OFFLOAD_JUMBO_FRAME;
622 bp->flags |= BNXT_FLAG_JUMBO;
624 bp->eth_dev->data->dev_conf.rxmode.offloads &=
625 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
626 bp->flags &= ~BNXT_FLAG_JUMBO;
629 /* THOR does not support ring groups.
630 * But we will use the array to save RSS context IDs.
632 if (BNXT_CHIP_THOR(bp))
633 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
635 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
637 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
641 rc = bnxt_alloc_hwrm_rings(bp);
643 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
647 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
649 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
653 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
656 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
657 if (bp->rx_cos_queue[i].id != 0xff) {
658 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
662 "Num pools more than FW profile\n");
666 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
672 rc = bnxt_mq_rx_configure(bp);
674 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
678 /* VNIC configuration */
679 for (i = 0; i < bp->nr_vnics; i++) {
680 rc = bnxt_setup_one_vnic(bp, i);
685 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
688 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
692 /* check and configure queue intr-vector mapping */
693 if ((rte_intr_cap_multiple(intr_handle) ||
694 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
695 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
696 intr_vector = bp->eth_dev->data->nb_rx_queues;
697 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
698 if (intr_vector > bp->rx_cp_nr_rings) {
699 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
703 rc = rte_intr_efd_enable(intr_handle, intr_vector);
708 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
709 intr_handle->intr_vec =
710 rte_zmalloc("intr_vec",
711 bp->eth_dev->data->nb_rx_queues *
713 if (intr_handle->intr_vec == NULL) {
714 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
715 " intr_vec", bp->eth_dev->data->nb_rx_queues);
719 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
720 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
721 intr_handle->intr_vec, intr_handle->nb_efd,
722 intr_handle->max_intr);
723 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
725 intr_handle->intr_vec[queue_id] =
726 vec + BNXT_RX_VEC_START;
727 if (vec < base + intr_handle->nb_efd - 1)
732 /* enable uio/vfio intr/eventfd mapping */
733 rc = rte_intr_enable(intr_handle);
734 #ifndef RTE_EXEC_ENV_FREEBSD
735 /* In FreeBSD OS, nic_uio driver does not support interrupts */
740 rc = bnxt_get_hwrm_link_config(bp, &new);
742 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
746 if (!bp->link_info->link_up) {
747 rc = bnxt_set_hwrm_link_config(bp, true);
750 "HWRM link config failure rc: %x\n", rc);
754 bnxt_print_link_info(bp->eth_dev);
756 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
758 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
763 rte_free(intr_handle->intr_vec);
765 rte_intr_efd_disable(intr_handle);
767 /* Some of the error status returned by FW may not be from errno.h */
774 static int bnxt_shutdown_nic(struct bnxt *bp)
776 bnxt_free_all_hwrm_resources(bp);
777 bnxt_free_all_filters(bp);
778 bnxt_free_all_vnics(bp);
783 * Device configuration and status function
786 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
788 uint32_t link_speed = bp->link_info->support_speeds;
789 uint32_t speed_capa = 0;
791 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
792 speed_capa |= ETH_LINK_SPEED_100M;
793 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
794 speed_capa |= ETH_LINK_SPEED_100M_HD;
795 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
796 speed_capa |= ETH_LINK_SPEED_1G;
797 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
798 speed_capa |= ETH_LINK_SPEED_2_5G;
799 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
800 speed_capa |= ETH_LINK_SPEED_10G;
801 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
802 speed_capa |= ETH_LINK_SPEED_20G;
803 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
804 speed_capa |= ETH_LINK_SPEED_25G;
805 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
806 speed_capa |= ETH_LINK_SPEED_40G;
807 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
808 speed_capa |= ETH_LINK_SPEED_50G;
809 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
810 speed_capa |= ETH_LINK_SPEED_100G;
811 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
812 speed_capa |= ETH_LINK_SPEED_200G;
814 if (bp->link_info->auto_mode ==
815 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
816 speed_capa |= ETH_LINK_SPEED_FIXED;
818 speed_capa |= ETH_LINK_SPEED_AUTONEG;
823 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
824 struct rte_eth_dev_info *dev_info)
826 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
827 struct bnxt *bp = eth_dev->data->dev_private;
828 uint16_t max_vnics, i, j, vpool, vrxq;
829 unsigned int max_rx_rings;
832 rc = is_bnxt_in_error(bp);
837 dev_info->max_mac_addrs = bp->max_l2_ctx;
838 dev_info->max_hash_mac_addrs = 0;
840 /* PF/VF specifics */
842 dev_info->max_vfs = pdev->max_vfs;
844 max_rx_rings = BNXT_MAX_RINGS(bp);
845 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
846 dev_info->max_rx_queues = max_rx_rings;
847 dev_info->max_tx_queues = max_rx_rings;
848 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
849 dev_info->hash_key_size = 40;
850 max_vnics = bp->max_vnics;
853 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
854 dev_info->max_mtu = BNXT_MAX_MTU;
856 /* Fast path specifics */
857 dev_info->min_rx_bufsize = 1;
858 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
860 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
861 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
862 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
863 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
864 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
866 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
869 dev_info->default_rxconf = (struct rte_eth_rxconf) {
875 .rx_free_thresh = 32,
876 /* If no descriptors available, pkts are dropped by default */
880 dev_info->default_txconf = (struct rte_eth_txconf) {
886 .tx_free_thresh = 32,
889 eth_dev->data->dev_conf.intr_conf.lsc = 1;
891 eth_dev->data->dev_conf.intr_conf.rxq = 1;
892 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
893 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
894 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
895 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
900 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
901 * need further investigation.
905 vpool = 64; /* ETH_64_POOLS */
906 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
907 for (i = 0; i < 4; vpool >>= 1, i++) {
908 if (max_vnics > vpool) {
909 for (j = 0; j < 5; vrxq >>= 1, j++) {
910 if (dev_info->max_rx_queues > vrxq) {
916 /* Not enough resources to support VMDq */
920 /* Not enough resources to support VMDq */
924 dev_info->max_vmdq_pools = vpool;
925 dev_info->vmdq_queue_num = vrxq;
927 dev_info->vmdq_pool_base = 0;
928 dev_info->vmdq_queue_base = 0;
933 /* Configure the device based on the configuration provided */
934 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
936 struct bnxt *bp = eth_dev->data->dev_private;
937 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
940 bp->rx_queues = (void *)eth_dev->data->rx_queues;
941 bp->tx_queues = (void *)eth_dev->data->tx_queues;
942 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
943 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
945 rc = is_bnxt_in_error(bp);
949 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
950 rc = bnxt_hwrm_check_vf_rings(bp);
952 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
956 /* If a resource has already been allocated - in this case
957 * it is the async completion ring, free it. Reallocate it after
958 * resource reservation. This will ensure the resource counts
959 * are calculated correctly.
962 pthread_mutex_lock(&bp->def_cp_lock);
964 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
965 bnxt_disable_int(bp);
966 bnxt_free_cp_ring(bp, bp->async_cp_ring);
969 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
971 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
972 pthread_mutex_unlock(&bp->def_cp_lock);
976 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
977 rc = bnxt_alloc_async_cp_ring(bp);
979 pthread_mutex_unlock(&bp->def_cp_lock);
985 pthread_mutex_unlock(&bp->def_cp_lock);
987 /* legacy driver needs to get updated values */
988 rc = bnxt_hwrm_func_qcaps(bp);
990 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
995 /* Inherit new configurations */
996 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
997 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
998 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
999 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1000 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1002 goto resource_error;
1004 if (BNXT_HAS_RING_GRPS(bp) &&
1005 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1006 goto resource_error;
1008 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1009 bp->max_vnics < eth_dev->data->nb_rx_queues)
1010 goto resource_error;
1012 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1013 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1015 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1016 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1017 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1019 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1020 eth_dev->data->mtu =
1021 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1022 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1024 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1030 "Insufficient resources to support requested config\n");
1032 "Num Queues Requested: Tx %d, Rx %d\n",
1033 eth_dev->data->nb_tx_queues,
1034 eth_dev->data->nb_rx_queues);
1036 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1037 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1038 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1042 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1044 struct rte_eth_link *link = ð_dev->data->dev_link;
1046 if (link->link_status)
1047 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1048 eth_dev->data->port_id,
1049 (uint32_t)link->link_speed,
1050 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1051 ("full-duplex") : ("half-duplex\n"));
1053 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1054 eth_dev->data->port_id);
1058 * Determine whether the current configuration requires support for scattered
1059 * receive; return 1 if scattered receive is required and 0 if not.
1061 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1066 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1069 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1070 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1072 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1073 RTE_PKTMBUF_HEADROOM);
1074 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1080 static eth_rx_burst_t
1081 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1083 struct bnxt *bp = eth_dev->data->dev_private;
1085 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1086 #ifndef RTE_LIBRTE_IEEE1588
1088 * Vector mode receive can be enabled only if scatter rx is not
1089 * in use and rx offloads are limited to VLAN stripping and
1092 if (!eth_dev->data->scattered_rx &&
1093 !(eth_dev->data->dev_conf.rxmode.offloads &
1094 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1095 DEV_RX_OFFLOAD_KEEP_CRC |
1096 DEV_RX_OFFLOAD_JUMBO_FRAME |
1097 DEV_RX_OFFLOAD_IPV4_CKSUM |
1098 DEV_RX_OFFLOAD_UDP_CKSUM |
1099 DEV_RX_OFFLOAD_TCP_CKSUM |
1100 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1101 DEV_RX_OFFLOAD_RSS_HASH |
1102 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1103 !BNXT_TRUFLOW_EN(bp)) {
1104 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1105 eth_dev->data->port_id);
1106 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1107 return bnxt_recv_pkts_vec;
1109 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1110 eth_dev->data->port_id);
1112 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1113 eth_dev->data->port_id,
1114 eth_dev->data->scattered_rx,
1115 eth_dev->data->dev_conf.rxmode.offloads);
1118 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1119 return bnxt_recv_pkts;
1122 static eth_tx_burst_t
1123 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1125 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1126 #ifndef RTE_LIBRTE_IEEE1588
1127 struct bnxt *bp = eth_dev->data->dev_private;
1130 * Vector mode transmit can be enabled only if not using scatter rx
1133 if (!eth_dev->data->scattered_rx &&
1134 !eth_dev->data->dev_conf.txmode.offloads &&
1135 !BNXT_TRUFLOW_EN(bp)) {
1136 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1137 eth_dev->data->port_id);
1138 return bnxt_xmit_pkts_vec;
1140 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1141 eth_dev->data->port_id);
1143 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1144 eth_dev->data->port_id,
1145 eth_dev->data->scattered_rx,
1146 eth_dev->data->dev_conf.txmode.offloads);
1149 return bnxt_xmit_pkts;
1152 static int bnxt_handle_if_change_status(struct bnxt *bp)
1156 /* Since fw has undergone a reset and lost all contexts,
1157 * set fatal flag to not issue hwrm during cleanup
1159 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1160 bnxt_uninit_resources(bp, true);
1162 /* clear fatal flag so that re-init happens */
1163 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1164 rc = bnxt_init_resources(bp, true);
1166 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1172 bnxt_create_port_app_df_rule(struct bnxt *bp, uint8_t flow_type,
1175 uint16_t port_id = bp->eth_dev->data->port_id;
1176 struct ulp_tlv_param param_list[] = {
1178 .type = BNXT_ULP_DF_PARAM_TYPE_DEV_PORT_ID,
1180 .value = {(port_id >> 8) & 0xff, port_id & 0xff}
1183 .type = BNXT_ULP_DF_PARAM_TYPE_LAST,
1189 return ulp_default_flow_create(bp->eth_dev, param_list, flow_type,
1194 bnxt_create_df_rules(struct bnxt *bp)
1196 struct bnxt_ulp_data *cfg_data;
1199 cfg_data = bp->ulp_ctx->cfg_data;
1200 rc = bnxt_create_port_app_df_rule(bp, BNXT_ULP_DF_TPL_PORT_TO_VS,
1201 &cfg_data->port_to_app_flow_id);
1204 "Failed to create port to app default rule\n");
1208 BNXT_TF_DBG(DEBUG, "***** created port to app default rule ******\n");
1209 rc = bnxt_create_port_app_df_rule(bp, BNXT_ULP_DF_TPL_VS_TO_PORT,
1210 &cfg_data->app_to_port_flow_id);
1212 rc = ulp_default_flow_db_cfa_action_get(bp->ulp_ctx,
1213 cfg_data->app_to_port_flow_id,
1214 &cfg_data->tx_cfa_action);
1219 "***** created app to port default rule *****\n");
1224 BNXT_TF_DBG(DEBUG, "Failed to create app to port default rule\n");
1229 bnxt_destroy_df_rules(struct bnxt *bp)
1231 struct bnxt_ulp_data *cfg_data;
1233 cfg_data = bp->ulp_ctx->cfg_data;
1234 ulp_default_flow_destroy(bp->eth_dev, cfg_data->port_to_app_flow_id);
1235 ulp_default_flow_destroy(bp->eth_dev, cfg_data->app_to_port_flow_id);
1238 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1240 struct bnxt *bp = eth_dev->data->dev_private;
1241 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1243 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1245 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1246 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1250 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1252 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1253 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1257 rc = bnxt_hwrm_if_change(bp, true);
1258 if (rc == 0 || rc != -EAGAIN)
1261 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1262 } while (retry_cnt--);
1267 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1268 rc = bnxt_handle_if_change_status(bp);
1273 bnxt_enable_int(bp);
1275 rc = bnxt_init_chip(bp);
1279 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1280 eth_dev->data->dev_started = 1;
1282 bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1284 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1285 vlan_mask |= ETH_VLAN_FILTER_MASK;
1286 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1287 vlan_mask |= ETH_VLAN_STRIP_MASK;
1288 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1292 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1293 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1295 pthread_mutex_lock(&bp->def_cp_lock);
1296 bnxt_schedule_fw_health_check(bp);
1297 pthread_mutex_unlock(&bp->def_cp_lock);
1299 if (BNXT_TRUFLOW_EN(bp))
1305 bnxt_shutdown_nic(bp);
1306 bnxt_free_tx_mbufs(bp);
1307 bnxt_free_rx_mbufs(bp);
1308 bnxt_hwrm_if_change(bp, false);
1309 eth_dev->data->dev_started = 0;
1313 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1315 struct bnxt *bp = eth_dev->data->dev_private;
1318 if (!bp->link_info->link_up)
1319 rc = bnxt_set_hwrm_link_config(bp, true);
1321 eth_dev->data->dev_link.link_status = 1;
1323 bnxt_print_link_info(eth_dev);
1327 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1329 struct bnxt *bp = eth_dev->data->dev_private;
1331 eth_dev->data->dev_link.link_status = 0;
1332 bnxt_set_hwrm_link_config(bp, false);
1333 bp->link_info->link_up = 0;
1338 static void bnxt_free_switch_domain(struct bnxt *bp)
1340 if (bp->switch_domain_id)
1341 rte_eth_switch_domain_free(bp->switch_domain_id);
1344 /* Unload the driver, release resources */
1345 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1347 struct bnxt *bp = eth_dev->data->dev_private;
1348 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1349 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1351 eth_dev->data->dev_started = 0;
1352 /* Prevent crashes when queues are still in use */
1353 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1354 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1356 bnxt_disable_int(bp);
1358 /* disable uio/vfio intr/eventfd mapping */
1359 rte_intr_disable(intr_handle);
1361 bnxt_cancel_fw_health_check(bp);
1363 bnxt_dev_set_link_down_op(eth_dev);
1365 /* Wait for link to be reset and the async notification to process.
1366 * During reset recovery, there is no need to wait and
1367 * VF/NPAR functions do not have privilege to change PHY config.
1369 if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1370 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1372 /* Clean queue intr-vector mapping */
1373 rte_intr_efd_disable(intr_handle);
1374 if (intr_handle->intr_vec != NULL) {
1375 rte_free(intr_handle->intr_vec);
1376 intr_handle->intr_vec = NULL;
1379 bnxt_hwrm_port_clr_stats(bp);
1380 bnxt_free_tx_mbufs(bp);
1381 bnxt_free_rx_mbufs(bp);
1382 /* Process any remaining notifications in default completion queue */
1383 bnxt_int_handler(eth_dev);
1384 bnxt_shutdown_nic(bp);
1385 bnxt_hwrm_if_change(bp, false);
1387 rte_free(bp->mark_table);
1388 bp->mark_table = NULL;
1390 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1391 bp->rx_cosq_cnt = 0;
1392 /* All filters are deleted on a port stop. */
1393 if (BNXT_FLOW_XSTATS_EN(bp))
1394 bp->flow_stat->flow_count = 0;
1397 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1399 struct bnxt *bp = eth_dev->data->dev_private;
1401 /* cancel the recovery handler before remove dev */
1402 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1403 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1404 bnxt_cancel_fc_thread(bp);
1406 if (BNXT_TRUFLOW_EN(bp)) {
1407 if (bp->rep_info != NULL)
1408 bnxt_destroy_df_rules(bp);
1409 bnxt_ulp_deinit(bp);
1412 if (eth_dev->data->dev_started)
1413 bnxt_dev_stop_op(eth_dev);
1415 bnxt_free_switch_domain(bp);
1417 bnxt_uninit_resources(bp, false);
1419 bnxt_free_leds_info(bp);
1420 bnxt_free_cos_queues(bp);
1421 bnxt_free_link_info(bp);
1422 bnxt_free_pf_info(bp);
1423 bnxt_free_parent_info(bp);
1425 eth_dev->dev_ops = NULL;
1426 eth_dev->rx_pkt_burst = NULL;
1427 eth_dev->tx_pkt_burst = NULL;
1429 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1430 bp->tx_mem_zone = NULL;
1431 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1432 bp->rx_mem_zone = NULL;
1434 rte_free(bp->pf->vf_info);
1435 bp->pf->vf_info = NULL;
1437 rte_free(bp->grp_info);
1438 bp->grp_info = NULL;
1441 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1444 struct bnxt *bp = eth_dev->data->dev_private;
1445 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1446 struct bnxt_vnic_info *vnic;
1447 struct bnxt_filter_info *filter, *temp_filter;
1450 if (is_bnxt_in_error(bp))
1454 * Loop through all VNICs from the specified filter flow pools to
1455 * remove the corresponding MAC addr filter
1457 for (i = 0; i < bp->nr_vnics; i++) {
1458 if (!(pool_mask & (1ULL << i)))
1461 vnic = &bp->vnic_info[i];
1462 filter = STAILQ_FIRST(&vnic->filter);
1464 temp_filter = STAILQ_NEXT(filter, next);
1465 if (filter->mac_index == index) {
1466 STAILQ_REMOVE(&vnic->filter, filter,
1467 bnxt_filter_info, next);
1468 bnxt_hwrm_clear_l2_filter(bp, filter);
1469 bnxt_free_filter(bp, filter);
1471 filter = temp_filter;
1476 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1477 struct rte_ether_addr *mac_addr, uint32_t index,
1480 struct bnxt_filter_info *filter;
1483 /* Attach requested MAC address to the new l2_filter */
1484 STAILQ_FOREACH(filter, &vnic->filter, next) {
1485 if (filter->mac_index == index) {
1487 "MAC addr already existed for pool %d\n",
1493 filter = bnxt_alloc_filter(bp);
1495 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1499 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1500 * if the MAC that's been programmed now is a different one, then,
1501 * copy that addr to filter->l2_addr
1504 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1505 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1507 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1509 filter->mac_index = index;
1510 if (filter->mac_index == 0)
1511 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1513 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1515 bnxt_free_filter(bp, filter);
1521 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1522 struct rte_ether_addr *mac_addr,
1523 uint32_t index, uint32_t pool)
1525 struct bnxt *bp = eth_dev->data->dev_private;
1526 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1529 rc = is_bnxt_in_error(bp);
1533 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1534 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1539 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1543 /* Filter settings will get applied when port is started */
1544 if (!eth_dev->data->dev_started)
1547 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1552 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1553 bool exp_link_status)
1556 struct bnxt *bp = eth_dev->data->dev_private;
1557 struct rte_eth_link new;
1558 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1559 BNXT_LINK_DOWN_WAIT_CNT;
1561 rc = is_bnxt_in_error(bp);
1565 memset(&new, 0, sizeof(new));
1567 /* Retrieve link info from hardware */
1568 rc = bnxt_get_hwrm_link_config(bp, &new);
1570 new.link_speed = ETH_LINK_SPEED_100M;
1571 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1573 "Failed to retrieve link rc = 0x%x!\n", rc);
1577 if (!wait_to_complete || new.link_status == exp_link_status)
1580 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1584 /* Timed out or success */
1585 if (new.link_status != eth_dev->data->dev_link.link_status ||
1586 new.link_speed != eth_dev->data->dev_link.link_speed) {
1587 rte_eth_linkstatus_set(eth_dev, &new);
1589 _rte_eth_dev_callback_process(eth_dev,
1590 RTE_ETH_EVENT_INTR_LSC,
1593 bnxt_print_link_info(eth_dev);
1599 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1600 int wait_to_complete)
1602 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1605 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1607 struct bnxt *bp = eth_dev->data->dev_private;
1608 struct bnxt_vnic_info *vnic;
1612 rc = is_bnxt_in_error(bp);
1616 /* Filter settings will get applied when port is started */
1617 if (!eth_dev->data->dev_started)
1620 if (bp->vnic_info == NULL)
1623 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1625 old_flags = vnic->flags;
1626 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1627 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1629 vnic->flags = old_flags;
1634 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1636 struct bnxt *bp = eth_dev->data->dev_private;
1637 struct bnxt_vnic_info *vnic;
1641 rc = is_bnxt_in_error(bp);
1645 /* Filter settings will get applied when port is started */
1646 if (!eth_dev->data->dev_started)
1649 if (bp->vnic_info == NULL)
1652 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1654 old_flags = vnic->flags;
1655 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1656 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1658 vnic->flags = old_flags;
1660 if (BNXT_TRUFLOW_EN(bp) && bp->rep_info != NULL)
1661 bnxt_create_df_rules(bp);
1666 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1668 struct bnxt *bp = eth_dev->data->dev_private;
1669 struct bnxt_vnic_info *vnic;
1673 rc = is_bnxt_in_error(bp);
1677 /* Filter settings will get applied when port is started */
1678 if (!eth_dev->data->dev_started)
1681 if (bp->vnic_info == NULL)
1684 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1686 old_flags = vnic->flags;
1687 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1688 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1690 vnic->flags = old_flags;
1695 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1697 struct bnxt *bp = eth_dev->data->dev_private;
1698 struct bnxt_vnic_info *vnic;
1702 rc = is_bnxt_in_error(bp);
1706 /* Filter settings will get applied when port is started */
1707 if (!eth_dev->data->dev_started)
1710 if (bp->vnic_info == NULL)
1713 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1715 old_flags = vnic->flags;
1716 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1717 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1719 vnic->flags = old_flags;
1724 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1725 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1727 if (qid >= bp->rx_nr_rings)
1730 return bp->eth_dev->data->rx_queues[qid];
1733 /* Return rxq corresponding to a given rss table ring/group ID. */
1734 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1736 struct bnxt_rx_queue *rxq;
1739 if (!BNXT_HAS_RING_GRPS(bp)) {
1740 for (i = 0; i < bp->rx_nr_rings; i++) {
1741 rxq = bp->eth_dev->data->rx_queues[i];
1742 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1746 for (i = 0; i < bp->rx_nr_rings; i++) {
1747 if (bp->grp_info[i].fw_grp_id == fwr)
1752 return INVALID_HW_RING_ID;
1755 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1756 struct rte_eth_rss_reta_entry64 *reta_conf,
1759 struct bnxt *bp = eth_dev->data->dev_private;
1760 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1761 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1762 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1766 rc = is_bnxt_in_error(bp);
1770 if (!vnic->rss_table)
1773 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1776 if (reta_size != tbl_size) {
1777 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1778 "(%d) must equal the size supported by the hardware "
1779 "(%d)\n", reta_size, tbl_size);
1783 for (i = 0; i < reta_size; i++) {
1784 struct bnxt_rx_queue *rxq;
1786 idx = i / RTE_RETA_GROUP_SIZE;
1787 sft = i % RTE_RETA_GROUP_SIZE;
1789 if (!(reta_conf[idx].mask & (1ULL << sft)))
1792 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1794 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1798 if (BNXT_CHIP_THOR(bp)) {
1799 vnic->rss_table[i * 2] =
1800 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1801 vnic->rss_table[i * 2 + 1] =
1802 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1804 vnic->rss_table[i] =
1805 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1809 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1813 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1814 struct rte_eth_rss_reta_entry64 *reta_conf,
1817 struct bnxt *bp = eth_dev->data->dev_private;
1818 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1819 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1820 uint16_t idx, sft, i;
1823 rc = is_bnxt_in_error(bp);
1827 /* Retrieve from the default VNIC */
1830 if (!vnic->rss_table)
1833 if (reta_size != tbl_size) {
1834 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1835 "(%d) must equal the size supported by the hardware "
1836 "(%d)\n", reta_size, tbl_size);
1840 for (idx = 0, i = 0; i < reta_size; i++) {
1841 idx = i / RTE_RETA_GROUP_SIZE;
1842 sft = i % RTE_RETA_GROUP_SIZE;
1844 if (reta_conf[idx].mask & (1ULL << sft)) {
1847 if (BNXT_CHIP_THOR(bp))
1848 qid = bnxt_rss_to_qid(bp,
1849 vnic->rss_table[i * 2]);
1851 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1853 if (qid == INVALID_HW_RING_ID) {
1854 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1857 reta_conf[idx].reta[sft] = qid;
1864 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1865 struct rte_eth_rss_conf *rss_conf)
1867 struct bnxt *bp = eth_dev->data->dev_private;
1868 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1869 struct bnxt_vnic_info *vnic;
1872 rc = is_bnxt_in_error(bp);
1877 * If RSS enablement were different than dev_configure,
1878 * then return -EINVAL
1880 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1881 if (!rss_conf->rss_hf)
1882 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1884 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1888 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1889 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
1893 /* Update the default RSS VNIC(s) */
1894 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1895 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1898 * If hashkey is not specified, use the previously configured
1901 if (!rss_conf->rss_key)
1904 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1906 "Invalid hashkey length, should be 16 bytes\n");
1909 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1912 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1916 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1917 struct rte_eth_rss_conf *rss_conf)
1919 struct bnxt *bp = eth_dev->data->dev_private;
1920 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1922 uint32_t hash_types;
1924 rc = is_bnxt_in_error(bp);
1928 /* RSS configuration is the same for all VNICs */
1929 if (vnic && vnic->rss_hash_key) {
1930 if (rss_conf->rss_key) {
1931 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1932 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1933 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1936 hash_types = vnic->hash_type;
1937 rss_conf->rss_hf = 0;
1938 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1939 rss_conf->rss_hf |= ETH_RSS_IPV4;
1940 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1942 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1943 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1945 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1947 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1948 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1950 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1952 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1953 rss_conf->rss_hf |= ETH_RSS_IPV6;
1954 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1956 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1957 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1959 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1961 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1962 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1964 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1968 "Unknown RSS config from firmware (%08x), RSS disabled",
1973 rss_conf->rss_hf = 0;
1978 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1979 struct rte_eth_fc_conf *fc_conf)
1981 struct bnxt *bp = dev->data->dev_private;
1982 struct rte_eth_link link_info;
1985 rc = is_bnxt_in_error(bp);
1989 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1993 memset(fc_conf, 0, sizeof(*fc_conf));
1994 if (bp->link_info->auto_pause)
1995 fc_conf->autoneg = 1;
1996 switch (bp->link_info->pause) {
1998 fc_conf->mode = RTE_FC_NONE;
2000 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2001 fc_conf->mode = RTE_FC_TX_PAUSE;
2003 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2004 fc_conf->mode = RTE_FC_RX_PAUSE;
2006 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2007 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2008 fc_conf->mode = RTE_FC_FULL;
2014 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2015 struct rte_eth_fc_conf *fc_conf)
2017 struct bnxt *bp = dev->data->dev_private;
2020 rc = is_bnxt_in_error(bp);
2024 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2025 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2029 switch (fc_conf->mode) {
2031 bp->link_info->auto_pause = 0;
2032 bp->link_info->force_pause = 0;
2034 case RTE_FC_RX_PAUSE:
2035 if (fc_conf->autoneg) {
2036 bp->link_info->auto_pause =
2037 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2038 bp->link_info->force_pause = 0;
2040 bp->link_info->auto_pause = 0;
2041 bp->link_info->force_pause =
2042 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2045 case RTE_FC_TX_PAUSE:
2046 if (fc_conf->autoneg) {
2047 bp->link_info->auto_pause =
2048 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2049 bp->link_info->force_pause = 0;
2051 bp->link_info->auto_pause = 0;
2052 bp->link_info->force_pause =
2053 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2057 if (fc_conf->autoneg) {
2058 bp->link_info->auto_pause =
2059 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2060 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2061 bp->link_info->force_pause = 0;
2063 bp->link_info->auto_pause = 0;
2064 bp->link_info->force_pause =
2065 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2066 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2070 return bnxt_set_hwrm_link_config(bp, true);
2073 /* Add UDP tunneling port */
2075 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2076 struct rte_eth_udp_tunnel *udp_tunnel)
2078 struct bnxt *bp = eth_dev->data->dev_private;
2079 uint16_t tunnel_type = 0;
2082 rc = is_bnxt_in_error(bp);
2086 switch (udp_tunnel->prot_type) {
2087 case RTE_TUNNEL_TYPE_VXLAN:
2088 if (bp->vxlan_port_cnt) {
2089 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2090 udp_tunnel->udp_port);
2091 if (bp->vxlan_port != udp_tunnel->udp_port) {
2092 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2095 bp->vxlan_port_cnt++;
2099 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2100 bp->vxlan_port_cnt++;
2102 case RTE_TUNNEL_TYPE_GENEVE:
2103 if (bp->geneve_port_cnt) {
2104 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2105 udp_tunnel->udp_port);
2106 if (bp->geneve_port != udp_tunnel->udp_port) {
2107 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2110 bp->geneve_port_cnt++;
2114 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2115 bp->geneve_port_cnt++;
2118 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2121 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2127 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2128 struct rte_eth_udp_tunnel *udp_tunnel)
2130 struct bnxt *bp = eth_dev->data->dev_private;
2131 uint16_t tunnel_type = 0;
2135 rc = is_bnxt_in_error(bp);
2139 switch (udp_tunnel->prot_type) {
2140 case RTE_TUNNEL_TYPE_VXLAN:
2141 if (!bp->vxlan_port_cnt) {
2142 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2145 if (bp->vxlan_port != udp_tunnel->udp_port) {
2146 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2147 udp_tunnel->udp_port, bp->vxlan_port);
2150 if (--bp->vxlan_port_cnt)
2154 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2155 port = bp->vxlan_fw_dst_port_id;
2157 case RTE_TUNNEL_TYPE_GENEVE:
2158 if (!bp->geneve_port_cnt) {
2159 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2162 if (bp->geneve_port != udp_tunnel->udp_port) {
2163 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2164 udp_tunnel->udp_port, bp->geneve_port);
2167 if (--bp->geneve_port_cnt)
2171 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2172 port = bp->geneve_fw_dst_port_id;
2175 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2179 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2182 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2185 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2186 bp->geneve_port = 0;
2191 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2193 struct bnxt_filter_info *filter;
2194 struct bnxt_vnic_info *vnic;
2196 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2198 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2199 filter = STAILQ_FIRST(&vnic->filter);
2201 /* Search for this matching MAC+VLAN filter */
2202 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2203 /* Delete the filter */
2204 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2207 STAILQ_REMOVE(&vnic->filter, filter,
2208 bnxt_filter_info, next);
2209 bnxt_free_filter(bp, filter);
2211 "Deleted vlan filter for %d\n",
2215 filter = STAILQ_NEXT(filter, next);
2220 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2222 struct bnxt_filter_info *filter;
2223 struct bnxt_vnic_info *vnic;
2225 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2226 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2227 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2229 /* Implementation notes on the use of VNIC in this command:
2231 * By default, these filters belong to default vnic for the function.
2232 * Once these filters are set up, only destination VNIC can be modified.
2233 * If the destination VNIC is not specified in this command,
2234 * then the HWRM shall only create an l2 context id.
2237 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2238 filter = STAILQ_FIRST(&vnic->filter);
2239 /* Check if the VLAN has already been added */
2241 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2244 filter = STAILQ_NEXT(filter, next);
2247 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2248 * command to create MAC+VLAN filter with the right flags, enables set.
2250 filter = bnxt_alloc_filter(bp);
2253 "MAC/VLAN filter alloc failed\n");
2256 /* MAC + VLAN ID filter */
2257 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2258 * untagged packets are received
2260 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2261 * packets and only the programmed vlan's packets are received
2263 filter->l2_ivlan = vlan_id;
2264 filter->l2_ivlan_mask = 0x0FFF;
2265 filter->enables |= en;
2266 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2268 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2270 /* Free the newly allocated filter as we were
2271 * not able to create the filter in hardware.
2273 bnxt_free_filter(bp, filter);
2277 filter->mac_index = 0;
2278 /* Add this new filter to the list */
2280 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2282 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2285 "Added Vlan filter for %d\n", vlan_id);
2289 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2290 uint16_t vlan_id, int on)
2292 struct bnxt *bp = eth_dev->data->dev_private;
2295 rc = is_bnxt_in_error(bp);
2299 if (!eth_dev->data->dev_started) {
2300 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2304 /* These operations apply to ALL existing MAC/VLAN filters */
2306 return bnxt_add_vlan_filter(bp, vlan_id);
2308 return bnxt_del_vlan_filter(bp, vlan_id);
2311 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2312 struct bnxt_vnic_info *vnic)
2314 struct bnxt_filter_info *filter;
2317 filter = STAILQ_FIRST(&vnic->filter);
2319 if (filter->mac_index == 0 &&
2320 !memcmp(filter->l2_addr, bp->mac_addr,
2321 RTE_ETHER_ADDR_LEN)) {
2322 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2324 STAILQ_REMOVE(&vnic->filter, filter,
2325 bnxt_filter_info, next);
2326 bnxt_free_filter(bp, filter);
2330 filter = STAILQ_NEXT(filter, next);
2336 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2338 struct bnxt_vnic_info *vnic;
2342 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2343 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2344 /* Remove any VLAN filters programmed */
2345 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2346 bnxt_del_vlan_filter(bp, i);
2348 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2352 /* Default filter will allow packets that match the
2353 * dest mac. So, it has to be deleted, otherwise, we
2354 * will endup receiving vlan packets for which the
2355 * filter is not programmed, when hw-vlan-filter
2356 * configuration is ON
2358 bnxt_del_dflt_mac_filter(bp, vnic);
2359 /* This filter will allow only untagged packets */
2360 bnxt_add_vlan_filter(bp, 0);
2362 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2363 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2368 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2370 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2374 /* Destroy vnic filters and vnic */
2375 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2376 DEV_RX_OFFLOAD_VLAN_FILTER) {
2377 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2378 bnxt_del_vlan_filter(bp, i);
2380 bnxt_del_dflt_mac_filter(bp, vnic);
2382 rc = bnxt_hwrm_vnic_free(bp, vnic);
2386 rte_free(vnic->fw_grp_ids);
2387 vnic->fw_grp_ids = NULL;
2389 vnic->rx_queue_cnt = 0;
2395 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2397 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2400 /* Destroy, recreate and reconfigure the default vnic */
2401 rc = bnxt_free_one_vnic(bp, 0);
2405 /* default vnic 0 */
2406 rc = bnxt_setup_one_vnic(bp, 0);
2410 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2411 DEV_RX_OFFLOAD_VLAN_FILTER) {
2412 rc = bnxt_add_vlan_filter(bp, 0);
2415 rc = bnxt_restore_vlan_filters(bp);
2419 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2424 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2428 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2429 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2435 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2437 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2438 struct bnxt *bp = dev->data->dev_private;
2441 rc = is_bnxt_in_error(bp);
2445 /* Filter settings will get applied when port is started */
2446 if (!dev->data->dev_started)
2449 if (mask & ETH_VLAN_FILTER_MASK) {
2450 /* Enable or disable VLAN filtering */
2451 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2456 if (mask & ETH_VLAN_STRIP_MASK) {
2457 /* Enable or disable VLAN stripping */
2458 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2463 if (mask & ETH_VLAN_EXTEND_MASK) {
2464 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2465 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2467 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2474 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2477 struct bnxt *bp = dev->data->dev_private;
2478 int qinq = dev->data->dev_conf.rxmode.offloads &
2479 DEV_RX_OFFLOAD_VLAN_EXTEND;
2481 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2482 vlan_type != ETH_VLAN_TYPE_OUTER) {
2484 "Unsupported vlan type.");
2489 "QinQ not enabled. Needs to be ON as we can "
2490 "accelerate only outer vlan\n");
2494 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2496 case RTE_ETHER_TYPE_QINQ:
2498 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2500 case RTE_ETHER_TYPE_VLAN:
2502 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2504 case RTE_ETHER_TYPE_QINQ1:
2506 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2508 case RTE_ETHER_TYPE_QINQ2:
2510 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2512 case RTE_ETHER_TYPE_QINQ3:
2514 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2517 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2520 bp->outer_tpid_bd |= tpid;
2521 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2522 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2524 "Can accelerate only outer vlan in QinQ\n");
2532 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2533 struct rte_ether_addr *addr)
2535 struct bnxt *bp = dev->data->dev_private;
2536 /* Default Filter is tied to VNIC 0 */
2537 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2540 rc = is_bnxt_in_error(bp);
2544 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2547 if (rte_is_zero_ether_addr(addr))
2550 /* Filter settings will get applied when port is started */
2551 if (!dev->data->dev_started)
2554 /* Check if the requested MAC is already added */
2555 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2558 /* Destroy filter and re-create it */
2559 bnxt_del_dflt_mac_filter(bp, vnic);
2561 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2562 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2563 /* This filter will allow only untagged packets */
2564 rc = bnxt_add_vlan_filter(bp, 0);
2566 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2569 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2574 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2575 struct rte_ether_addr *mc_addr_set,
2576 uint32_t nb_mc_addr)
2578 struct bnxt *bp = eth_dev->data->dev_private;
2579 char *mc_addr_list = (char *)mc_addr_set;
2580 struct bnxt_vnic_info *vnic;
2581 uint32_t off = 0, i = 0;
2584 rc = is_bnxt_in_error(bp);
2588 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2590 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2591 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2595 /* TODO Check for Duplicate mcast addresses */
2596 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2597 for (i = 0; i < nb_mc_addr; i++) {
2598 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2599 RTE_ETHER_ADDR_LEN);
2600 off += RTE_ETHER_ADDR_LEN;
2603 vnic->mc_addr_cnt = i;
2604 if (vnic->mc_addr_cnt)
2605 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2607 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2610 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2614 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2616 struct bnxt *bp = dev->data->dev_private;
2617 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2618 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2619 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2620 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2623 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2624 fw_major, fw_minor, fw_updt, fw_rsvd);
2626 ret += 1; /* add the size of '\0' */
2627 if (fw_size < (uint32_t)ret)
2634 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2635 struct rte_eth_rxq_info *qinfo)
2637 struct bnxt *bp = dev->data->dev_private;
2638 struct bnxt_rx_queue *rxq;
2640 if (is_bnxt_in_error(bp))
2643 rxq = dev->data->rx_queues[queue_id];
2645 qinfo->mp = rxq->mb_pool;
2646 qinfo->scattered_rx = dev->data->scattered_rx;
2647 qinfo->nb_desc = rxq->nb_rx_desc;
2649 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2650 qinfo->conf.rx_drop_en = 0;
2651 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2655 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2656 struct rte_eth_txq_info *qinfo)
2658 struct bnxt *bp = dev->data->dev_private;
2659 struct bnxt_tx_queue *txq;
2661 if (is_bnxt_in_error(bp))
2664 txq = dev->data->tx_queues[queue_id];
2666 qinfo->nb_desc = txq->nb_tx_desc;
2668 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2669 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2670 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2672 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2673 qinfo->conf.tx_rs_thresh = 0;
2674 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2678 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2679 struct rte_eth_burst_mode *mode)
2681 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2683 if (pkt_burst == bnxt_recv_pkts) {
2684 snprintf(mode->info, sizeof(mode->info), "%s",
2688 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
2689 if (pkt_burst == bnxt_recv_pkts_vec) {
2690 snprintf(mode->info, sizeof(mode->info), "%s",
2700 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2701 struct rte_eth_burst_mode *mode)
2703 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2705 if (pkt_burst == bnxt_xmit_pkts) {
2706 snprintf(mode->info, sizeof(mode->info), "%s",
2710 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
2711 if (pkt_burst == bnxt_xmit_pkts_vec) {
2712 snprintf(mode->info, sizeof(mode->info), "%s",
2721 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2723 struct bnxt *bp = eth_dev->data->dev_private;
2724 uint32_t new_pkt_size;
2728 rc = is_bnxt_in_error(bp);
2732 /* Exit if receive queues are not configured yet */
2733 if (!eth_dev->data->nb_rx_queues)
2736 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2737 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2739 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
2741 * If vector-mode tx/rx is active, disallow any MTU change that would
2742 * require scattered receive support.
2744 if (eth_dev->data->dev_started &&
2745 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2746 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2748 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2750 "MTU change would require scattered rx support. ");
2751 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2756 if (new_mtu > RTE_ETHER_MTU) {
2757 bp->flags |= BNXT_FLAG_JUMBO;
2758 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2759 DEV_RX_OFFLOAD_JUMBO_FRAME;
2761 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2762 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2763 bp->flags &= ~BNXT_FLAG_JUMBO;
2766 /* Is there a change in mtu setting? */
2767 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2770 for (i = 0; i < bp->nr_vnics; i++) {
2771 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2774 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2775 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2779 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2780 size -= RTE_PKTMBUF_HEADROOM;
2782 if (size < new_mtu) {
2783 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2790 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2792 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2798 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2800 struct bnxt *bp = dev->data->dev_private;
2801 uint16_t vlan = bp->vlan;
2804 rc = is_bnxt_in_error(bp);
2808 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2810 "PVID cannot be modified for this function\n");
2813 bp->vlan = on ? pvid : 0;
2815 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2822 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2824 struct bnxt *bp = dev->data->dev_private;
2827 rc = is_bnxt_in_error(bp);
2831 return bnxt_hwrm_port_led_cfg(bp, true);
2835 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2837 struct bnxt *bp = dev->data->dev_private;
2840 rc = is_bnxt_in_error(bp);
2844 return bnxt_hwrm_port_led_cfg(bp, false);
2848 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2850 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2851 uint32_t desc = 0, raw_cons = 0, cons;
2852 struct bnxt_cp_ring_info *cpr;
2853 struct bnxt_rx_queue *rxq;
2854 struct rx_pkt_cmpl *rxcmp;
2857 rc = is_bnxt_in_error(bp);
2861 rxq = dev->data->rx_queues[rx_queue_id];
2863 raw_cons = cpr->cp_raw_cons;
2866 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2867 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2868 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2870 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2882 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2884 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2885 struct bnxt_rx_ring_info *rxr;
2886 struct bnxt_cp_ring_info *cpr;
2887 struct bnxt_sw_rx_bd *rx_buf;
2888 struct rx_pkt_cmpl *rxcmp;
2889 uint32_t cons, cp_cons;
2895 rc = is_bnxt_in_error(rxq->bp);
2902 if (offset >= rxq->nb_rx_desc)
2905 cons = RING_CMP(cpr->cp_ring_struct, offset);
2906 cp_cons = cpr->cp_raw_cons;
2907 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2909 if (cons > cp_cons) {
2910 if (CMPL_VALID(rxcmp, cpr->valid))
2911 return RTE_ETH_RX_DESC_DONE;
2913 if (CMPL_VALID(rxcmp, !cpr->valid))
2914 return RTE_ETH_RX_DESC_DONE;
2916 rx_buf = &rxr->rx_buf_ring[cons];
2917 if (rx_buf->mbuf == NULL)
2918 return RTE_ETH_RX_DESC_UNAVAIL;
2921 return RTE_ETH_RX_DESC_AVAIL;
2925 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2927 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2928 struct bnxt_tx_ring_info *txr;
2929 struct bnxt_cp_ring_info *cpr;
2930 struct bnxt_sw_tx_bd *tx_buf;
2931 struct tx_pkt_cmpl *txcmp;
2932 uint32_t cons, cp_cons;
2938 rc = is_bnxt_in_error(txq->bp);
2945 if (offset >= txq->nb_tx_desc)
2948 cons = RING_CMP(cpr->cp_ring_struct, offset);
2949 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2950 cp_cons = cpr->cp_raw_cons;
2952 if (cons > cp_cons) {
2953 if (CMPL_VALID(txcmp, cpr->valid))
2954 return RTE_ETH_TX_DESC_UNAVAIL;
2956 if (CMPL_VALID(txcmp, !cpr->valid))
2957 return RTE_ETH_TX_DESC_UNAVAIL;
2959 tx_buf = &txr->tx_buf_ring[cons];
2960 if (tx_buf->mbuf == NULL)
2961 return RTE_ETH_TX_DESC_DONE;
2963 return RTE_ETH_TX_DESC_FULL;
2966 static struct bnxt_filter_info *
2967 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2968 struct rte_eth_ethertype_filter *efilter,
2969 struct bnxt_vnic_info *vnic0,
2970 struct bnxt_vnic_info *vnic,
2973 struct bnxt_filter_info *mfilter = NULL;
2977 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2978 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2979 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2980 " ethertype filter.", efilter->ether_type);
2984 if (efilter->queue >= bp->rx_nr_rings) {
2985 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2990 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2991 vnic = &bp->vnic_info[efilter->queue];
2993 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2998 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2999 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
3000 if ((!memcmp(efilter->mac_addr.addr_bytes,
3001 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3003 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
3004 mfilter->ethertype == efilter->ether_type)) {
3010 STAILQ_FOREACH(mfilter, &vnic->filter, next)
3011 if ((!memcmp(efilter->mac_addr.addr_bytes,
3012 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
3013 mfilter->ethertype == efilter->ether_type &&
3015 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
3029 bnxt_ethertype_filter(struct rte_eth_dev *dev,
3030 enum rte_filter_op filter_op,
3033 struct bnxt *bp = dev->data->dev_private;
3034 struct rte_eth_ethertype_filter *efilter =
3035 (struct rte_eth_ethertype_filter *)arg;
3036 struct bnxt_filter_info *bfilter, *filter1;
3037 struct bnxt_vnic_info *vnic, *vnic0;
3040 if (filter_op == RTE_ETH_FILTER_NOP)
3044 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3049 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3050 vnic = &bp->vnic_info[efilter->queue];
3052 switch (filter_op) {
3053 case RTE_ETH_FILTER_ADD:
3054 bnxt_match_and_validate_ether_filter(bp, efilter,
3059 bfilter = bnxt_get_unused_filter(bp);
3060 if (bfilter == NULL) {
3062 "Not enough resources for a new filter.\n");
3065 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3066 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
3067 RTE_ETHER_ADDR_LEN);
3068 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
3069 RTE_ETHER_ADDR_LEN);
3070 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3071 bfilter->ethertype = efilter->ether_type;
3072 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3074 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3075 if (filter1 == NULL) {
3080 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3081 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3083 bfilter->dst_id = vnic->fw_vnic_id;
3085 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3087 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3090 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3093 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3095 case RTE_ETH_FILTER_DELETE:
3096 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3098 if (ret == -EEXIST) {
3099 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3101 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3103 bnxt_free_filter(bp, filter1);
3104 } else if (ret == 0) {
3105 PMD_DRV_LOG(ERR, "No matching filter found\n");
3109 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3115 bnxt_free_filter(bp, bfilter);
3121 parse_ntuple_filter(struct bnxt *bp,
3122 struct rte_eth_ntuple_filter *nfilter,
3123 struct bnxt_filter_info *bfilter)
3127 if (nfilter->queue >= bp->rx_nr_rings) {
3128 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3132 switch (nfilter->dst_port_mask) {
3134 bfilter->dst_port_mask = -1;
3135 bfilter->dst_port = nfilter->dst_port;
3136 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3137 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3140 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3144 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3145 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3147 switch (nfilter->proto_mask) {
3149 if (nfilter->proto == 17) /* IPPROTO_UDP */
3150 bfilter->ip_protocol = 17;
3151 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3152 bfilter->ip_protocol = 6;
3155 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3158 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3162 switch (nfilter->dst_ip_mask) {
3164 bfilter->dst_ipaddr_mask[0] = -1;
3165 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3166 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3167 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3170 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3174 switch (nfilter->src_ip_mask) {
3176 bfilter->src_ipaddr_mask[0] = -1;
3177 bfilter->src_ipaddr[0] = nfilter->src_ip;
3178 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3179 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3182 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3186 switch (nfilter->src_port_mask) {
3188 bfilter->src_port_mask = -1;
3189 bfilter->src_port = nfilter->src_port;
3190 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3191 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3194 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3198 bfilter->enables = en;
3202 static struct bnxt_filter_info*
3203 bnxt_match_ntuple_filter(struct bnxt *bp,
3204 struct bnxt_filter_info *bfilter,
3205 struct bnxt_vnic_info **mvnic)
3207 struct bnxt_filter_info *mfilter = NULL;
3210 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3211 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3212 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3213 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3214 bfilter->src_ipaddr_mask[0] ==
3215 mfilter->src_ipaddr_mask[0] &&
3216 bfilter->src_port == mfilter->src_port &&
3217 bfilter->src_port_mask == mfilter->src_port_mask &&
3218 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3219 bfilter->dst_ipaddr_mask[0] ==
3220 mfilter->dst_ipaddr_mask[0] &&
3221 bfilter->dst_port == mfilter->dst_port &&
3222 bfilter->dst_port_mask == mfilter->dst_port_mask &&
3223 bfilter->flags == mfilter->flags &&
3224 bfilter->enables == mfilter->enables) {
3235 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3236 struct rte_eth_ntuple_filter *nfilter,
3237 enum rte_filter_op filter_op)
3239 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3240 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3243 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3244 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3248 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3249 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3253 bfilter = bnxt_get_unused_filter(bp);
3254 if (bfilter == NULL) {
3256 "Not enough resources for a new filter.\n");
3259 ret = parse_ntuple_filter(bp, nfilter, bfilter);
3263 vnic = &bp->vnic_info[nfilter->queue];
3264 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3265 filter1 = STAILQ_FIRST(&vnic0->filter);
3266 if (filter1 == NULL) {
3271 bfilter->dst_id = vnic->fw_vnic_id;
3272 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3274 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3275 bfilter->ethertype = 0x800;
3276 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3278 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3280 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3281 bfilter->dst_id == mfilter->dst_id) {
3282 PMD_DRV_LOG(ERR, "filter exists.\n");
3285 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3286 bfilter->dst_id != mfilter->dst_id) {
3287 mfilter->dst_id = vnic->fw_vnic_id;
3288 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3289 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3290 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3291 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3292 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3295 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3296 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3301 if (filter_op == RTE_ETH_FILTER_ADD) {
3302 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3303 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3306 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3308 if (mfilter == NULL) {
3309 /* This should not happen. But for Coverity! */
3313 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3315 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3316 bnxt_free_filter(bp, mfilter);
3317 bnxt_free_filter(bp, bfilter);
3322 bnxt_free_filter(bp, bfilter);
3327 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3328 enum rte_filter_op filter_op,
3331 struct bnxt *bp = dev->data->dev_private;
3334 if (filter_op == RTE_ETH_FILTER_NOP)
3338 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3343 switch (filter_op) {
3344 case RTE_ETH_FILTER_ADD:
3345 ret = bnxt_cfg_ntuple_filter(bp,
3346 (struct rte_eth_ntuple_filter *)arg,
3349 case RTE_ETH_FILTER_DELETE:
3350 ret = bnxt_cfg_ntuple_filter(bp,
3351 (struct rte_eth_ntuple_filter *)arg,
3355 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3363 bnxt_parse_fdir_filter(struct bnxt *bp,
3364 struct rte_eth_fdir_filter *fdir,
3365 struct bnxt_filter_info *filter)
3367 enum rte_fdir_mode fdir_mode =
3368 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3369 struct bnxt_vnic_info *vnic0, *vnic;
3370 struct bnxt_filter_info *filter1;
3374 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3377 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3378 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3380 switch (fdir->input.flow_type) {
3381 case RTE_ETH_FLOW_IPV4:
3382 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3384 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3385 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3386 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3387 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3388 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3389 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3390 filter->ip_addr_type =
3391 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3392 filter->src_ipaddr_mask[0] = 0xffffffff;
3393 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3394 filter->dst_ipaddr_mask[0] = 0xffffffff;
3395 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3396 filter->ethertype = 0x800;
3397 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3399 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3400 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3401 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3402 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3403 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3404 filter->dst_port_mask = 0xffff;
3405 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3406 filter->src_port_mask = 0xffff;
3407 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3408 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3409 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3410 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3411 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3412 filter->ip_protocol = 6;
3413 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3414 filter->ip_addr_type =
3415 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3416 filter->src_ipaddr_mask[0] = 0xffffffff;
3417 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3418 filter->dst_ipaddr_mask[0] = 0xffffffff;
3419 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3420 filter->ethertype = 0x800;
3421 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3423 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3424 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3425 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3426 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3427 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3428 filter->dst_port_mask = 0xffff;
3429 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3430 filter->src_port_mask = 0xffff;
3431 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3432 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3433 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3434 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3435 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3436 filter->ip_protocol = 17;
3437 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3438 filter->ip_addr_type =
3439 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3440 filter->src_ipaddr_mask[0] = 0xffffffff;
3441 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3442 filter->dst_ipaddr_mask[0] = 0xffffffff;
3443 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3444 filter->ethertype = 0x800;
3445 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3447 case RTE_ETH_FLOW_IPV6:
3448 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3450 filter->ip_addr_type =
3451 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3452 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3453 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3454 rte_memcpy(filter->src_ipaddr,
3455 fdir->input.flow.ipv6_flow.src_ip, 16);
3456 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3457 rte_memcpy(filter->dst_ipaddr,
3458 fdir->input.flow.ipv6_flow.dst_ip, 16);
3459 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3460 memset(filter->dst_ipaddr_mask, 0xff, 16);
3461 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3462 memset(filter->src_ipaddr_mask, 0xff, 16);
3463 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3464 filter->ethertype = 0x86dd;
3465 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3467 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3468 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3469 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3470 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3471 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3472 filter->dst_port_mask = 0xffff;
3473 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3474 filter->src_port_mask = 0xffff;
3475 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3476 filter->ip_addr_type =
3477 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3478 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3479 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3480 rte_memcpy(filter->src_ipaddr,
3481 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3482 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3483 rte_memcpy(filter->dst_ipaddr,
3484 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3485 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3486 memset(filter->dst_ipaddr_mask, 0xff, 16);
3487 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3488 memset(filter->src_ipaddr_mask, 0xff, 16);
3489 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3490 filter->ethertype = 0x86dd;
3491 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3493 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3494 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3495 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3496 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3497 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3498 filter->dst_port_mask = 0xffff;
3499 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3500 filter->src_port_mask = 0xffff;
3501 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3502 filter->ip_addr_type =
3503 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3504 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3505 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3506 rte_memcpy(filter->src_ipaddr,
3507 fdir->input.flow.udp6_flow.ip.src_ip, 16);
3508 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3509 rte_memcpy(filter->dst_ipaddr,
3510 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3511 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3512 memset(filter->dst_ipaddr_mask, 0xff, 16);
3513 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3514 memset(filter->src_ipaddr_mask, 0xff, 16);
3515 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3516 filter->ethertype = 0x86dd;
3517 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3519 case RTE_ETH_FLOW_L2_PAYLOAD:
3520 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3521 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3523 case RTE_ETH_FLOW_VXLAN:
3524 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3526 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3527 filter->tunnel_type =
3528 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3529 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3531 case RTE_ETH_FLOW_NVGRE:
3532 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3534 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3535 filter->tunnel_type =
3536 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3537 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3539 case RTE_ETH_FLOW_UNKNOWN:
3540 case RTE_ETH_FLOW_RAW:
3541 case RTE_ETH_FLOW_FRAG_IPV4:
3542 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3543 case RTE_ETH_FLOW_FRAG_IPV6:
3544 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3545 case RTE_ETH_FLOW_IPV6_EX:
3546 case RTE_ETH_FLOW_IPV6_TCP_EX:
3547 case RTE_ETH_FLOW_IPV6_UDP_EX:
3548 case RTE_ETH_FLOW_GENEVE:
3554 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3555 vnic = &bp->vnic_info[fdir->action.rx_queue];
3557 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3561 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3562 rte_memcpy(filter->dst_macaddr,
3563 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3564 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3567 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3568 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3569 filter1 = STAILQ_FIRST(&vnic0->filter);
3570 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3572 filter->dst_id = vnic->fw_vnic_id;
3573 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3574 if (filter->dst_macaddr[i] == 0x00)
3575 filter1 = STAILQ_FIRST(&vnic0->filter);
3577 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3580 if (filter1 == NULL)
3583 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3584 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3586 filter->enables = en;
3591 static struct bnxt_filter_info *
3592 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3593 struct bnxt_vnic_info **mvnic)
3595 struct bnxt_filter_info *mf = NULL;
3598 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3599 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3601 STAILQ_FOREACH(mf, &vnic->filter, next) {
3602 if (mf->filter_type == nf->filter_type &&
3603 mf->flags == nf->flags &&
3604 mf->src_port == nf->src_port &&
3605 mf->src_port_mask == nf->src_port_mask &&
3606 mf->dst_port == nf->dst_port &&
3607 mf->dst_port_mask == nf->dst_port_mask &&
3608 mf->ip_protocol == nf->ip_protocol &&
3609 mf->ip_addr_type == nf->ip_addr_type &&
3610 mf->ethertype == nf->ethertype &&
3611 mf->vni == nf->vni &&
3612 mf->tunnel_type == nf->tunnel_type &&
3613 mf->l2_ovlan == nf->l2_ovlan &&
3614 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3615 mf->l2_ivlan == nf->l2_ivlan &&
3616 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3617 !memcmp(mf->l2_addr, nf->l2_addr,
3618 RTE_ETHER_ADDR_LEN) &&
3619 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3620 RTE_ETHER_ADDR_LEN) &&
3621 !memcmp(mf->src_macaddr, nf->src_macaddr,
3622 RTE_ETHER_ADDR_LEN) &&
3623 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3624 RTE_ETHER_ADDR_LEN) &&
3625 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3626 sizeof(nf->src_ipaddr)) &&
3627 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3628 sizeof(nf->src_ipaddr_mask)) &&
3629 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3630 sizeof(nf->dst_ipaddr)) &&
3631 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3632 sizeof(nf->dst_ipaddr_mask))) {
3643 bnxt_fdir_filter(struct rte_eth_dev *dev,
3644 enum rte_filter_op filter_op,
3647 struct bnxt *bp = dev->data->dev_private;
3648 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3649 struct bnxt_filter_info *filter, *match;
3650 struct bnxt_vnic_info *vnic, *mvnic;
3653 if (filter_op == RTE_ETH_FILTER_NOP)
3656 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3659 switch (filter_op) {
3660 case RTE_ETH_FILTER_ADD:
3661 case RTE_ETH_FILTER_DELETE:
3663 filter = bnxt_get_unused_filter(bp);
3664 if (filter == NULL) {
3666 "Not enough resources for a new flow.\n");
3670 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3673 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3675 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3676 vnic = &bp->vnic_info[0];
3678 vnic = &bp->vnic_info[fdir->action.rx_queue];
3680 match = bnxt_match_fdir(bp, filter, &mvnic);
3681 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3682 if (match->dst_id == vnic->fw_vnic_id) {
3683 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3687 match->dst_id = vnic->fw_vnic_id;
3688 ret = bnxt_hwrm_set_ntuple_filter(bp,
3691 STAILQ_REMOVE(&mvnic->filter, match,
3692 bnxt_filter_info, next);
3693 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3695 "Filter with matching pattern exist\n");
3697 "Updated it to new destination q\n");
3701 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3702 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3707 if (filter_op == RTE_ETH_FILTER_ADD) {
3708 ret = bnxt_hwrm_set_ntuple_filter(bp,
3713 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3715 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3716 STAILQ_REMOVE(&vnic->filter, match,
3717 bnxt_filter_info, next);
3718 bnxt_free_filter(bp, match);
3719 bnxt_free_filter(bp, filter);
3722 case RTE_ETH_FILTER_FLUSH:
3723 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3724 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3726 STAILQ_FOREACH(filter, &vnic->filter, next) {
3727 if (filter->filter_type ==
3728 HWRM_CFA_NTUPLE_FILTER) {
3730 bnxt_hwrm_clear_ntuple_filter(bp,
3732 STAILQ_REMOVE(&vnic->filter, filter,
3733 bnxt_filter_info, next);
3738 case RTE_ETH_FILTER_UPDATE:
3739 case RTE_ETH_FILTER_STATS:
3740 case RTE_ETH_FILTER_INFO:
3741 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3744 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3751 bnxt_free_filter(bp, filter);
3756 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3757 enum rte_filter_type filter_type,
3758 enum rte_filter_op filter_op, void *arg)
3760 struct bnxt *bp = dev->data->dev_private;
3763 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3764 struct bnxt_vf_representor *vfr = dev->data->dev_private;
3765 bp = vfr->parent_dev->data->dev_private;
3768 ret = is_bnxt_in_error(bp);
3772 switch (filter_type) {
3773 case RTE_ETH_FILTER_TUNNEL:
3775 "filter type: %d: To be implemented\n", filter_type);
3777 case RTE_ETH_FILTER_FDIR:
3778 ret = bnxt_fdir_filter(dev, filter_op, arg);
3780 case RTE_ETH_FILTER_NTUPLE:
3781 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3783 case RTE_ETH_FILTER_ETHERTYPE:
3784 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3786 case RTE_ETH_FILTER_GENERIC:
3787 if (filter_op != RTE_ETH_FILTER_GET)
3789 if (BNXT_TRUFLOW_EN(bp))
3790 *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3792 *(const void **)arg = &bnxt_flow_ops;
3796 "Filter type (%d) not supported", filter_type);
3803 static const uint32_t *
3804 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3806 static const uint32_t ptypes[] = {
3807 RTE_PTYPE_L2_ETHER_VLAN,
3808 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3809 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3813 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3814 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3815 RTE_PTYPE_INNER_L4_ICMP,
3816 RTE_PTYPE_INNER_L4_TCP,
3817 RTE_PTYPE_INNER_L4_UDP,
3821 if (!dev->rx_pkt_burst)
3827 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3830 uint32_t reg_base = *reg_arr & 0xfffff000;
3834 for (i = 0; i < count; i++) {
3835 if ((reg_arr[i] & 0xfffff000) != reg_base)
3838 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3839 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3843 static int bnxt_map_ptp_regs(struct bnxt *bp)
3845 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3849 reg_arr = ptp->rx_regs;
3850 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3854 reg_arr = ptp->tx_regs;
3855 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3859 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3860 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3862 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3863 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3868 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3870 rte_write32(0, (uint8_t *)bp->bar0 +
3871 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3872 rte_write32(0, (uint8_t *)bp->bar0 +
3873 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3876 static uint64_t bnxt_cc_read(struct bnxt *bp)
3880 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3881 BNXT_GRCPF_REG_SYNC_TIME));
3882 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3883 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3887 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3889 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3892 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3893 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3894 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3897 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3898 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3899 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3900 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3901 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3902 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3907 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3909 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3910 struct bnxt_pf_info *pf = bp->pf;
3917 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3918 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3919 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3922 port_id = pf->port_id;
3923 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3924 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3926 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3927 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3928 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3929 /* bnxt_clr_rx_ts(bp); TBD */
3933 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3934 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3935 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3936 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3942 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3945 struct bnxt *bp = dev->data->dev_private;
3946 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3951 ns = rte_timespec_to_ns(ts);
3952 /* Set the timecounters to a new value. */
3959 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3961 struct bnxt *bp = dev->data->dev_private;
3962 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3963 uint64_t ns, systime_cycles = 0;
3969 if (BNXT_CHIP_THOR(bp))
3970 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3973 systime_cycles = bnxt_cc_read(bp);
3975 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3976 *ts = rte_ns_to_timespec(ns);
3981 bnxt_timesync_enable(struct rte_eth_dev *dev)
3983 struct bnxt *bp = dev->data->dev_private;
3984 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3992 ptp->tx_tstamp_en = 1;
3993 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3995 rc = bnxt_hwrm_ptp_cfg(bp);
3999 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
4000 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4001 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4003 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4004 ptp->tc.cc_shift = shift;
4005 ptp->tc.nsec_mask = (1ULL << shift) - 1;
4007 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4008 ptp->rx_tstamp_tc.cc_shift = shift;
4009 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4011 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
4012 ptp->tx_tstamp_tc.cc_shift = shift;
4013 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4015 if (!BNXT_CHIP_THOR(bp))
4016 bnxt_map_ptp_regs(bp);
4022 bnxt_timesync_disable(struct rte_eth_dev *dev)
4024 struct bnxt *bp = dev->data->dev_private;
4025 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4031 ptp->tx_tstamp_en = 0;
4034 bnxt_hwrm_ptp_cfg(bp);
4036 if (!BNXT_CHIP_THOR(bp))
4037 bnxt_unmap_ptp_regs(bp);
4043 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4044 struct timespec *timestamp,
4045 uint32_t flags __rte_unused)
4047 struct bnxt *bp = dev->data->dev_private;
4048 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4049 uint64_t rx_tstamp_cycles = 0;
4055 if (BNXT_CHIP_THOR(bp))
4056 rx_tstamp_cycles = ptp->rx_timestamp;
4058 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
4060 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
4061 *timestamp = rte_ns_to_timespec(ns);
4066 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4067 struct timespec *timestamp)
4069 struct bnxt *bp = dev->data->dev_private;
4070 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4071 uint64_t tx_tstamp_cycles = 0;
4078 if (BNXT_CHIP_THOR(bp))
4079 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4082 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4084 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4085 *timestamp = rte_ns_to_timespec(ns);
4091 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4093 struct bnxt *bp = dev->data->dev_private;
4094 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4099 ptp->tc.nsec += delta;
4105 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4107 struct bnxt *bp = dev->data->dev_private;
4109 uint32_t dir_entries;
4110 uint32_t entry_length;
4112 rc = is_bnxt_in_error(bp);
4116 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4117 bp->pdev->addr.domain, bp->pdev->addr.bus,
4118 bp->pdev->addr.devid, bp->pdev->addr.function);
4120 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4124 return dir_entries * entry_length;
4128 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4129 struct rte_dev_eeprom_info *in_eeprom)
4131 struct bnxt *bp = dev->data->dev_private;
4136 rc = is_bnxt_in_error(bp);
4140 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4141 bp->pdev->addr.domain, bp->pdev->addr.bus,
4142 bp->pdev->addr.devid, bp->pdev->addr.function,
4143 in_eeprom->offset, in_eeprom->length);
4145 if (in_eeprom->offset == 0) /* special offset value to get directory */
4146 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4149 index = in_eeprom->offset >> 24;
4150 offset = in_eeprom->offset & 0xffffff;
4153 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4154 in_eeprom->length, in_eeprom->data);
4159 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4162 case BNX_DIR_TYPE_CHIMP_PATCH:
4163 case BNX_DIR_TYPE_BOOTCODE:
4164 case BNX_DIR_TYPE_BOOTCODE_2:
4165 case BNX_DIR_TYPE_APE_FW:
4166 case BNX_DIR_TYPE_APE_PATCH:
4167 case BNX_DIR_TYPE_KONG_FW:
4168 case BNX_DIR_TYPE_KONG_PATCH:
4169 case BNX_DIR_TYPE_BONO_FW:
4170 case BNX_DIR_TYPE_BONO_PATCH:
4178 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4181 case BNX_DIR_TYPE_AVS:
4182 case BNX_DIR_TYPE_EXP_ROM_MBA:
4183 case BNX_DIR_TYPE_PCIE:
4184 case BNX_DIR_TYPE_TSCF_UCODE:
4185 case BNX_DIR_TYPE_EXT_PHY:
4186 case BNX_DIR_TYPE_CCM:
4187 case BNX_DIR_TYPE_ISCSI_BOOT:
4188 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4189 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4197 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4199 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4200 bnxt_dir_type_is_other_exec_format(dir_type);
4204 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4205 struct rte_dev_eeprom_info *in_eeprom)
4207 struct bnxt *bp = dev->data->dev_private;
4208 uint8_t index, dir_op;
4209 uint16_t type, ext, ordinal, attr;
4212 rc = is_bnxt_in_error(bp);
4216 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4217 bp->pdev->addr.domain, bp->pdev->addr.bus,
4218 bp->pdev->addr.devid, bp->pdev->addr.function,
4219 in_eeprom->offset, in_eeprom->length);
4222 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4226 type = in_eeprom->magic >> 16;
4228 if (type == 0xffff) { /* special value for directory operations */
4229 index = in_eeprom->magic & 0xff;
4230 dir_op = in_eeprom->magic >> 8;
4234 case 0x0e: /* erase */
4235 if (in_eeprom->offset != ~in_eeprom->magic)
4237 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4243 /* Create or re-write an NVM item: */
4244 if (bnxt_dir_type_is_executable(type) == true)
4246 ext = in_eeprom->magic & 0xffff;
4247 ordinal = in_eeprom->offset >> 16;
4248 attr = in_eeprom->offset & 0xffff;
4250 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4251 in_eeprom->data, in_eeprom->length);
4258 static const struct eth_dev_ops bnxt_dev_ops = {
4259 .dev_infos_get = bnxt_dev_info_get_op,
4260 .dev_close = bnxt_dev_close_op,
4261 .dev_configure = bnxt_dev_configure_op,
4262 .dev_start = bnxt_dev_start_op,
4263 .dev_stop = bnxt_dev_stop_op,
4264 .dev_set_link_up = bnxt_dev_set_link_up_op,
4265 .dev_set_link_down = bnxt_dev_set_link_down_op,
4266 .stats_get = bnxt_stats_get_op,
4267 .stats_reset = bnxt_stats_reset_op,
4268 .rx_queue_setup = bnxt_rx_queue_setup_op,
4269 .rx_queue_release = bnxt_rx_queue_release_op,
4270 .tx_queue_setup = bnxt_tx_queue_setup_op,
4271 .tx_queue_release = bnxt_tx_queue_release_op,
4272 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4273 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4274 .reta_update = bnxt_reta_update_op,
4275 .reta_query = bnxt_reta_query_op,
4276 .rss_hash_update = bnxt_rss_hash_update_op,
4277 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4278 .link_update = bnxt_link_update_op,
4279 .promiscuous_enable = bnxt_promiscuous_enable_op,
4280 .promiscuous_disable = bnxt_promiscuous_disable_op,
4281 .allmulticast_enable = bnxt_allmulticast_enable_op,
4282 .allmulticast_disable = bnxt_allmulticast_disable_op,
4283 .mac_addr_add = bnxt_mac_addr_add_op,
4284 .mac_addr_remove = bnxt_mac_addr_remove_op,
4285 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4286 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4287 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
4288 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
4289 .vlan_filter_set = bnxt_vlan_filter_set_op,
4290 .vlan_offload_set = bnxt_vlan_offload_set_op,
4291 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4292 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4293 .mtu_set = bnxt_mtu_set_op,
4294 .mac_addr_set = bnxt_set_default_mac_addr_op,
4295 .xstats_get = bnxt_dev_xstats_get_op,
4296 .xstats_get_names = bnxt_dev_xstats_get_names_op,
4297 .xstats_reset = bnxt_dev_xstats_reset_op,
4298 .fw_version_get = bnxt_fw_version_get,
4299 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4300 .rxq_info_get = bnxt_rxq_info_get_op,
4301 .txq_info_get = bnxt_txq_info_get_op,
4302 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4303 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4304 .dev_led_on = bnxt_dev_led_on_op,
4305 .dev_led_off = bnxt_dev_led_off_op,
4306 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4307 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4308 .rx_queue_count = bnxt_rx_queue_count_op,
4309 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
4310 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
4311 .rx_queue_start = bnxt_rx_queue_start,
4312 .rx_queue_stop = bnxt_rx_queue_stop,
4313 .tx_queue_start = bnxt_tx_queue_start,
4314 .tx_queue_stop = bnxt_tx_queue_stop,
4315 .filter_ctrl = bnxt_filter_ctrl_op,
4316 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4317 .get_eeprom_length = bnxt_get_eeprom_length_op,
4318 .get_eeprom = bnxt_get_eeprom_op,
4319 .set_eeprom = bnxt_set_eeprom_op,
4320 .timesync_enable = bnxt_timesync_enable,
4321 .timesync_disable = bnxt_timesync_disable,
4322 .timesync_read_time = bnxt_timesync_read_time,
4323 .timesync_write_time = bnxt_timesync_write_time,
4324 .timesync_adjust_time = bnxt_timesync_adjust_time,
4325 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4326 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4329 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4333 /* Only pre-map the reset GRC registers using window 3 */
4334 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4335 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4337 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4342 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4344 struct bnxt_error_recovery_info *info = bp->recovery_info;
4345 uint32_t reg_base = 0xffffffff;
4348 /* Only pre-map the monitoring GRC registers using window 2 */
4349 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4350 uint32_t reg = info->status_regs[i];
4352 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4355 if (reg_base == 0xffffffff)
4356 reg_base = reg & 0xfffff000;
4357 if ((reg & 0xfffff000) != reg_base)
4360 /* Use mask 0xffc as the Lower 2 bits indicates
4361 * address space location
4363 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4367 if (reg_base == 0xffffffff)
4370 rte_write32(reg_base, (uint8_t *)bp->bar0 +
4371 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4376 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4378 struct bnxt_error_recovery_info *info = bp->recovery_info;
4379 uint32_t delay = info->delay_after_reset[index];
4380 uint32_t val = info->reset_reg_val[index];
4381 uint32_t reg = info->reset_reg[index];
4382 uint32_t type, offset;
4384 type = BNXT_FW_STATUS_REG_TYPE(reg);
4385 offset = BNXT_FW_STATUS_REG_OFF(reg);
4388 case BNXT_FW_STATUS_REG_TYPE_CFG:
4389 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4391 case BNXT_FW_STATUS_REG_TYPE_GRC:
4392 offset = bnxt_map_reset_regs(bp, offset);
4393 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4395 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4396 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4399 /* wait on a specific interval of time until core reset is complete */
4401 rte_delay_ms(delay);
4404 static void bnxt_dev_cleanup(struct bnxt *bp)
4406 bnxt_set_hwrm_link_config(bp, false);
4407 bp->link_info->link_up = 0;
4408 if (bp->eth_dev->data->dev_started)
4409 bnxt_dev_stop_op(bp->eth_dev);
4411 bnxt_uninit_resources(bp, true);
4414 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4416 struct rte_eth_dev *dev = bp->eth_dev;
4417 struct rte_vlan_filter_conf *vfc;
4421 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4422 vfc = &dev->data->vlan_filter_conf;
4423 vidx = vlan_id / 64;
4424 vbit = vlan_id % 64;
4426 /* Each bit corresponds to a VLAN id */
4427 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4428 rc = bnxt_add_vlan_filter(bp, vlan_id);
4437 static int bnxt_restore_mac_filters(struct bnxt *bp)
4439 struct rte_eth_dev *dev = bp->eth_dev;
4440 struct rte_eth_dev_info dev_info;
4441 struct rte_ether_addr *addr;
4447 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
4450 rc = bnxt_dev_info_get_op(dev, &dev_info);
4454 /* replay MAC address configuration */
4455 for (i = 1; i < dev_info.max_mac_addrs; i++) {
4456 addr = &dev->data->mac_addrs[i];
4458 /* skip zero address */
4459 if (rte_is_zero_ether_addr(addr))
4463 pool_mask = dev->data->mac_pool_sel[i];
4466 if (pool_mask & 1ULL) {
4467 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4473 } while (pool_mask);
4479 static int bnxt_restore_filters(struct bnxt *bp)
4481 struct rte_eth_dev *dev = bp->eth_dev;
4484 if (dev->data->all_multicast) {
4485 ret = bnxt_allmulticast_enable_op(dev);
4489 if (dev->data->promiscuous) {
4490 ret = bnxt_promiscuous_enable_op(dev);
4495 ret = bnxt_restore_mac_filters(bp);
4499 ret = bnxt_restore_vlan_filters(bp);
4500 /* TODO restore other filters as well */
4504 static void bnxt_dev_recover(void *arg)
4506 struct bnxt *bp = arg;
4507 int timeout = bp->fw_reset_max_msecs;
4510 /* Clear Error flag so that device re-init should happen */
4511 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4514 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4517 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4518 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4519 } while (rc && timeout);
4522 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4526 rc = bnxt_init_resources(bp, true);
4529 "Failed to initialize resources after reset\n");
4532 /* clear reset flag as the device is initialized now */
4533 bp->flags &= ~BNXT_FLAG_FW_RESET;
4535 rc = bnxt_dev_start_op(bp->eth_dev);
4537 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4541 rc = bnxt_restore_filters(bp);
4545 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4548 bnxt_dev_stop_op(bp->eth_dev);
4550 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4551 bnxt_uninit_resources(bp, false);
4552 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4555 void bnxt_dev_reset_and_resume(void *arg)
4557 struct bnxt *bp = arg;
4560 bnxt_dev_cleanup(bp);
4562 bnxt_wait_for_device_shutdown(bp);
4564 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4565 bnxt_dev_recover, (void *)bp);
4567 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4570 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4572 struct bnxt_error_recovery_info *info = bp->recovery_info;
4573 uint32_t reg = info->status_regs[index];
4574 uint32_t type, offset, val = 0;
4576 type = BNXT_FW_STATUS_REG_TYPE(reg);
4577 offset = BNXT_FW_STATUS_REG_OFF(reg);
4580 case BNXT_FW_STATUS_REG_TYPE_CFG:
4581 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4583 case BNXT_FW_STATUS_REG_TYPE_GRC:
4584 offset = info->mapped_status_regs[index];
4586 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4587 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4595 static int bnxt_fw_reset_all(struct bnxt *bp)
4597 struct bnxt_error_recovery_info *info = bp->recovery_info;
4601 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4602 /* Reset through master function driver */
4603 for (i = 0; i < info->reg_array_cnt; i++)
4604 bnxt_write_fw_reset_reg(bp, i);
4605 /* Wait for time specified by FW after triggering reset */
4606 rte_delay_ms(info->master_func_wait_period_after_reset);
4607 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4608 /* Reset with the help of Kong processor */
4609 rc = bnxt_hwrm_fw_reset(bp);
4611 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4617 static void bnxt_fw_reset_cb(void *arg)
4619 struct bnxt *bp = arg;
4620 struct bnxt_error_recovery_info *info = bp->recovery_info;
4623 /* Only Master function can do FW reset */
4624 if (bnxt_is_master_func(bp) &&
4625 bnxt_is_recovery_enabled(bp)) {
4626 rc = bnxt_fw_reset_all(bp);
4628 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4633 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4634 * EXCEPTION_FATAL_ASYNC event to all the functions
4635 * (including MASTER FUNC). After receiving this Async, all the active
4636 * drivers should treat this case as FW initiated recovery
4638 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4639 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4640 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4642 /* To recover from error */
4643 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4648 /* Driver should poll FW heartbeat, reset_counter with the frequency
4649 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4650 * When the driver detects heartbeat stop or change in reset_counter,
4651 * it has to trigger a reset to recover from the error condition.
4652 * A “master PF” is the function who will have the privilege to
4653 * initiate the chimp reset. The master PF will be elected by the
4654 * firmware and will be notified through async message.
4656 static void bnxt_check_fw_health(void *arg)
4658 struct bnxt *bp = arg;
4659 struct bnxt_error_recovery_info *info = bp->recovery_info;
4660 uint32_t val = 0, wait_msec;
4662 if (!info || !bnxt_is_recovery_enabled(bp) ||
4663 is_bnxt_in_error(bp))
4666 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4667 if (val == info->last_heart_beat)
4670 info->last_heart_beat = val;
4672 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4673 if (val != info->last_reset_counter)
4676 info->last_reset_counter = val;
4678 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4679 bnxt_check_fw_health, (void *)bp);
4683 /* Stop DMA to/from device */
4684 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4685 bp->flags |= BNXT_FLAG_FW_RESET;
4687 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4689 if (bnxt_is_master_func(bp))
4690 wait_msec = info->master_func_wait_period;
4692 wait_msec = info->normal_func_wait_period;
4694 rte_eal_alarm_set(US_PER_MS * wait_msec,
4695 bnxt_fw_reset_cb, (void *)bp);
4698 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4700 uint32_t polling_freq;
4702 if (!bnxt_is_recovery_enabled(bp))
4705 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4708 polling_freq = bp->recovery_info->driver_polling_freq;
4710 rte_eal_alarm_set(US_PER_MS * polling_freq,
4711 bnxt_check_fw_health, (void *)bp);
4712 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4715 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4717 if (!bnxt_is_recovery_enabled(bp))
4720 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4721 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4724 static bool bnxt_vf_pciid(uint16_t device_id)
4726 switch (device_id) {
4727 case BROADCOM_DEV_ID_57304_VF:
4728 case BROADCOM_DEV_ID_57406_VF:
4729 case BROADCOM_DEV_ID_5731X_VF:
4730 case BROADCOM_DEV_ID_5741X_VF:
4731 case BROADCOM_DEV_ID_57414_VF:
4732 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4733 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4734 case BROADCOM_DEV_ID_58802_VF:
4735 case BROADCOM_DEV_ID_57500_VF1:
4736 case BROADCOM_DEV_ID_57500_VF2:
4744 static bool bnxt_thor_device(uint16_t device_id)
4746 switch (device_id) {
4747 case BROADCOM_DEV_ID_57508:
4748 case BROADCOM_DEV_ID_57504:
4749 case BROADCOM_DEV_ID_57502:
4750 case BROADCOM_DEV_ID_57508_MF1:
4751 case BROADCOM_DEV_ID_57504_MF1:
4752 case BROADCOM_DEV_ID_57502_MF1:
4753 case BROADCOM_DEV_ID_57508_MF2:
4754 case BROADCOM_DEV_ID_57504_MF2:
4755 case BROADCOM_DEV_ID_57502_MF2:
4756 case BROADCOM_DEV_ID_57500_VF1:
4757 case BROADCOM_DEV_ID_57500_VF2:
4765 bool bnxt_stratus_device(struct bnxt *bp)
4767 uint16_t device_id = bp->pdev->id.device_id;
4769 switch (device_id) {
4770 case BROADCOM_DEV_ID_STRATUS_NIC:
4771 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4772 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4780 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4782 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4783 struct bnxt *bp = eth_dev->data->dev_private;
4785 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4786 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4787 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4788 if (!bp->bar0 || !bp->doorbell_base) {
4789 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4793 bp->eth_dev = eth_dev;
4799 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4800 struct bnxt_ctx_pg_info *ctx_pg,
4805 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4806 const struct rte_memzone *mz = NULL;
4807 char mz_name[RTE_MEMZONE_NAMESIZE];
4808 rte_iova_t mz_phys_addr;
4809 uint64_t valid_bits = 0;
4816 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4818 rmem->page_size = BNXT_PAGE_SIZE;
4819 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4820 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4821 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4823 valid_bits = PTU_PTE_VALID;
4825 if (rmem->nr_pages > 1) {
4826 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4827 "bnxt_ctx_pg_tbl%s_%x_%d",
4828 suffix, idx, bp->eth_dev->data->port_id);
4829 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4830 mz = rte_memzone_lookup(mz_name);
4832 mz = rte_memzone_reserve_aligned(mz_name,
4836 RTE_MEMZONE_SIZE_HINT_ONLY |
4837 RTE_MEMZONE_IOVA_CONTIG,
4843 memset(mz->addr, 0, mz->len);
4844 mz_phys_addr = mz->iova;
4846 rmem->pg_tbl = mz->addr;
4847 rmem->pg_tbl_map = mz_phys_addr;
4848 rmem->pg_tbl_mz = mz;
4851 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4852 suffix, idx, bp->eth_dev->data->port_id);
4853 mz = rte_memzone_lookup(mz_name);
4855 mz = rte_memzone_reserve_aligned(mz_name,
4859 RTE_MEMZONE_SIZE_HINT_ONLY |
4860 RTE_MEMZONE_IOVA_CONTIG,
4866 memset(mz->addr, 0, mz->len);
4867 mz_phys_addr = mz->iova;
4869 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4870 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4871 rmem->dma_arr[i] = mz_phys_addr + sz;
4873 if (rmem->nr_pages > 1) {
4874 if (i == rmem->nr_pages - 2 &&
4875 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4876 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4877 else if (i == rmem->nr_pages - 1 &&
4878 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4879 valid_bits |= PTU_PTE_LAST;
4881 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4887 if (rmem->vmem_size)
4888 rmem->vmem = (void **)mz->addr;
4889 rmem->dma_arr[0] = mz_phys_addr;
4893 static void bnxt_free_ctx_mem(struct bnxt *bp)
4897 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4900 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4901 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4902 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4903 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4904 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4905 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4906 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4907 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4908 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4909 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4910 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4912 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4913 if (bp->ctx->tqm_mem[i])
4914 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4921 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4923 #define min_t(type, x, y) ({ \
4924 type __min1 = (x); \
4925 type __min2 = (y); \
4926 __min1 < __min2 ? __min1 : __min2; })
4928 #define max_t(type, x, y) ({ \
4929 type __max1 = (x); \
4930 type __max2 = (y); \
4931 __max1 > __max2 ? __max1 : __max2; })
4933 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4935 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4937 struct bnxt_ctx_pg_info *ctx_pg;
4938 struct bnxt_ctx_mem_info *ctx;
4939 uint32_t mem_size, ena, entries;
4940 uint32_t entries_sp, min;
4943 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4945 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4949 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4952 ctx_pg = &ctx->qp_mem;
4953 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4954 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4955 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4959 ctx_pg = &ctx->srq_mem;
4960 ctx_pg->entries = ctx->srq_max_l2_entries;
4961 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4962 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4966 ctx_pg = &ctx->cq_mem;
4967 ctx_pg->entries = ctx->cq_max_l2_entries;
4968 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4969 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4973 ctx_pg = &ctx->vnic_mem;
4974 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4975 ctx->vnic_max_ring_table_entries;
4976 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4977 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4981 ctx_pg = &ctx->stat_mem;
4982 ctx_pg->entries = ctx->stat_max_entries;
4983 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4984 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4988 min = ctx->tqm_min_entries_per_ring;
4990 entries_sp = ctx->qp_max_l2_entries +
4991 ctx->vnic_max_vnic_entries +
4992 2 * ctx->qp_min_qp1_entries + min;
4993 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4995 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4996 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4997 entries = clamp_t(uint32_t, entries, min,
4998 ctx->tqm_max_entries_per_ring);
4999 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
5000 ctx_pg = ctx->tqm_mem[i];
5001 ctx_pg->entries = i ? entries : entries_sp;
5002 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
5003 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
5006 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
5009 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
5010 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
5013 "Failed to configure context mem: rc = %d\n", rc);
5015 ctx->flags |= BNXT_CTX_FLAG_INITED;
5020 static int bnxt_alloc_stats_mem(struct bnxt *bp)
5022 struct rte_pci_device *pci_dev = bp->pdev;
5023 char mz_name[RTE_MEMZONE_NAMESIZE];
5024 const struct rte_memzone *mz = NULL;
5025 uint32_t total_alloc_len;
5026 rte_iova_t mz_phys_addr;
5028 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
5031 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5032 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5033 pci_dev->addr.bus, pci_dev->addr.devid,
5034 pci_dev->addr.function, "rx_port_stats");
5035 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5036 mz = rte_memzone_lookup(mz_name);
5038 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
5039 sizeof(struct rx_port_stats_ext) + 512);
5041 mz = rte_memzone_reserve(mz_name, total_alloc_len,
5044 RTE_MEMZONE_SIZE_HINT_ONLY |
5045 RTE_MEMZONE_IOVA_CONTIG);
5049 memset(mz->addr, 0, mz->len);
5050 mz_phys_addr = mz->iova;
5052 bp->rx_mem_zone = (const void *)mz;
5053 bp->hw_rx_port_stats = mz->addr;
5054 bp->hw_rx_port_stats_map = mz_phys_addr;
5056 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5057 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5058 pci_dev->addr.bus, pci_dev->addr.devid,
5059 pci_dev->addr.function, "tx_port_stats");
5060 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5061 mz = rte_memzone_lookup(mz_name);
5063 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
5064 sizeof(struct tx_port_stats_ext) + 512);
5066 mz = rte_memzone_reserve(mz_name,
5070 RTE_MEMZONE_SIZE_HINT_ONLY |
5071 RTE_MEMZONE_IOVA_CONTIG);
5075 memset(mz->addr, 0, mz->len);
5076 mz_phys_addr = mz->iova;
5078 bp->tx_mem_zone = (const void *)mz;
5079 bp->hw_tx_port_stats = mz->addr;
5080 bp->hw_tx_port_stats_map = mz_phys_addr;
5081 bp->flags |= BNXT_FLAG_PORT_STATS;
5083 /* Display extended statistics if FW supports it */
5084 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5085 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5086 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5089 bp->hw_rx_port_stats_ext = (void *)
5090 ((uint8_t *)bp->hw_rx_port_stats +
5091 sizeof(struct rx_port_stats));
5092 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5093 sizeof(struct rx_port_stats);
5094 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5096 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5097 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5098 bp->hw_tx_port_stats_ext = (void *)
5099 ((uint8_t *)bp->hw_tx_port_stats +
5100 sizeof(struct tx_port_stats));
5101 bp->hw_tx_port_stats_ext_map =
5102 bp->hw_tx_port_stats_map +
5103 sizeof(struct tx_port_stats);
5104 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5110 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5112 struct bnxt *bp = eth_dev->data->dev_private;
5115 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5116 RTE_ETHER_ADDR_LEN *
5119 if (eth_dev->data->mac_addrs == NULL) {
5120 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5124 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5128 /* Generate a random MAC address, if none was assigned by PF */
5129 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5130 bnxt_eth_hw_addr_random(bp->mac_addr);
5132 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5133 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5134 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5136 rc = bnxt_hwrm_set_mac(bp);
5141 /* Copy the permanent MAC from the FUNC_QCAPS response */
5142 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5147 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5151 /* MAC is already configured in FW */
5152 if (BNXT_HAS_DFLT_MAC_SET(bp))
5155 /* Restore the old MAC configured */
5156 rc = bnxt_hwrm_set_mac(bp);
5158 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5163 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5168 #define ALLOW_FUNC(x) \
5170 uint32_t arg = (x); \
5171 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5172 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5175 /* Forward all requests if firmware is new enough */
5176 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5177 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5178 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5179 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5181 PMD_DRV_LOG(WARNING,
5182 "Firmware too old for VF mailbox functionality\n");
5183 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5187 * The following are used for driver cleanup. If we disallow these,
5188 * VF drivers can't clean up cleanly.
5190 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5191 ALLOW_FUNC(HWRM_VNIC_FREE);
5192 ALLOW_FUNC(HWRM_RING_FREE);
5193 ALLOW_FUNC(HWRM_RING_GRP_FREE);
5194 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5195 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5196 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5197 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5198 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5202 bnxt_get_svif(uint16_t port_id, bool func_svif,
5203 enum bnxt_ulp_intf_type type)
5205 struct rte_eth_dev *eth_dev;
5208 eth_dev = &rte_eth_devices[port_id];
5209 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5210 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5214 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5217 eth_dev = vfr->parent_dev;
5220 bp = eth_dev->data->dev_private;
5222 return func_svif ? bp->func_svif : bp->port_svif;
5226 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5228 struct rte_eth_dev *eth_dev;
5229 struct bnxt_vnic_info *vnic;
5232 eth_dev = &rte_eth_devices[port];
5233 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5234 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5238 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5239 return vfr->dflt_vnic_id;
5241 eth_dev = vfr->parent_dev;
5244 bp = eth_dev->data->dev_private;
5246 vnic = BNXT_GET_DEFAULT_VNIC(bp);
5248 return vnic->fw_vnic_id;
5252 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5254 struct rte_eth_dev *eth_dev;
5257 eth_dev = &rte_eth_devices[port];
5258 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5259 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5263 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5266 eth_dev = vfr->parent_dev;
5269 bp = eth_dev->data->dev_private;
5274 enum bnxt_ulp_intf_type
5275 bnxt_get_interface_type(uint16_t port)
5277 struct rte_eth_dev *eth_dev;
5280 eth_dev = &rte_eth_devices[port];
5281 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5282 return BNXT_ULP_INTF_TYPE_VF_REP;
5284 bp = eth_dev->data->dev_private;
5286 return BNXT_ULP_INTF_TYPE_PF;
5287 else if (BNXT_VF_IS_TRUSTED(bp))
5288 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5289 else if (BNXT_VF(bp))
5290 return BNXT_ULP_INTF_TYPE_VF;
5292 return BNXT_ULP_INTF_TYPE_INVALID;
5296 bnxt_get_phy_port_id(uint16_t port_id)
5298 struct bnxt_vf_representor *vfr;
5299 struct rte_eth_dev *eth_dev;
5302 eth_dev = &rte_eth_devices[port_id];
5303 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5304 vfr = eth_dev->data->dev_private;
5308 eth_dev = vfr->parent_dev;
5311 bp = eth_dev->data->dev_private;
5313 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5317 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5319 struct rte_eth_dev *eth_dev;
5322 eth_dev = &rte_eth_devices[port_id];
5323 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5324 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5328 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5329 return vfr->fw_fid - 1;
5331 eth_dev = vfr->parent_dev;
5334 bp = eth_dev->data->dev_private;
5336 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5340 bnxt_get_vport(uint16_t port_id)
5342 return (1 << bnxt_get_phy_port_id(port_id));
5345 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5347 struct bnxt_error_recovery_info *info = bp->recovery_info;
5350 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5351 memset(info, 0, sizeof(*info));
5355 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5358 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5361 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5363 bp->recovery_info = info;
5366 static void bnxt_check_fw_status(struct bnxt *bp)
5370 if (!(bp->recovery_info &&
5371 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5374 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5375 if (fw_status != BNXT_FW_STATUS_HEALTHY)
5376 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5380 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5382 struct bnxt_error_recovery_info *info = bp->recovery_info;
5383 uint32_t status_loc;
5386 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5387 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5388 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5389 BNXT_GRCP_WINDOW_2_BASE +
5390 offsetof(struct hcomm_status,
5392 /* If the signature is absent, then FW does not support this feature */
5393 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5394 HCOMM_STATUS_SIGNATURE_VAL)
5398 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5402 bp->recovery_info = info;
5404 memset(info, 0, sizeof(*info));
5407 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5408 BNXT_GRCP_WINDOW_2_BASE +
5409 offsetof(struct hcomm_status,
5412 /* Only pre-map the FW health status GRC register */
5413 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5416 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5417 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5418 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5420 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5421 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5423 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5428 static int bnxt_init_fw(struct bnxt *bp)
5435 rc = bnxt_map_hcomm_fw_status_reg(bp);
5439 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5441 bnxt_check_fw_status(bp);
5445 rc = bnxt_hwrm_func_reset(bp);
5449 rc = bnxt_hwrm_vnic_qcaps(bp);
5453 rc = bnxt_hwrm_queue_qportcfg(bp);
5457 /* Get the MAX capabilities for this function.
5458 * This function also allocates context memory for TQM rings and
5459 * informs the firmware about this allocated backing store memory.
5461 rc = bnxt_hwrm_func_qcaps(bp);
5465 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5469 bnxt_hwrm_port_mac_qcfg(bp);
5471 bnxt_hwrm_parent_pf_qcfg(bp);
5473 bnxt_hwrm_port_phy_qcaps(bp);
5475 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5479 bnxt_alloc_error_recovery_info(bp);
5480 /* Get the adapter error recovery support info */
5481 rc = bnxt_hwrm_error_recovery_qcfg(bp);
5483 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5485 bnxt_hwrm_port_led_qcaps(bp);
5491 bnxt_init_locks(struct bnxt *bp)
5495 err = pthread_mutex_init(&bp->flow_lock, NULL);
5497 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5501 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5503 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5507 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5511 rc = bnxt_init_fw(bp);
5515 if (!reconfig_dev) {
5516 rc = bnxt_setup_mac_addr(bp->eth_dev);
5520 rc = bnxt_restore_dflt_mac(bp);
5525 bnxt_config_vf_req_fwd(bp);
5527 rc = bnxt_hwrm_func_driver_register(bp);
5529 PMD_DRV_LOG(ERR, "Failed to register driver");
5534 if (bp->pdev->max_vfs) {
5535 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5537 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5541 rc = bnxt_hwrm_allocate_pf_only(bp);
5544 "Failed to allocate PF resources");
5550 rc = bnxt_alloc_mem(bp, reconfig_dev);
5554 rc = bnxt_setup_int(bp);
5558 rc = bnxt_request_int(bp);
5562 rc = bnxt_init_ctx_mem(bp);
5564 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5568 rc = bnxt_init_locks(bp);
5576 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5577 const char *value, void *opaque_arg)
5579 struct bnxt *bp = opaque_arg;
5580 unsigned long truflow;
5583 if (!value || !opaque_arg) {
5585 "Invalid parameter passed to truflow devargs.\n");
5589 truflow = strtoul(value, &end, 10);
5590 if (end == NULL || *end != '\0' ||
5591 (truflow == ULONG_MAX && errno == ERANGE)) {
5593 "Invalid parameter passed to truflow devargs.\n");
5597 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5599 "Invalid value passed to truflow devargs.\n");
5603 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5604 if (BNXT_TRUFLOW_EN(bp))
5605 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5611 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5612 const char *value, void *opaque_arg)
5614 struct bnxt *bp = opaque_arg;
5615 unsigned long flow_xstat;
5618 if (!value || !opaque_arg) {
5620 "Invalid parameter passed to flow_xstat devarg.\n");
5624 flow_xstat = strtoul(value, &end, 10);
5625 if (end == NULL || *end != '\0' ||
5626 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5628 "Invalid parameter passed to flow_xstat devarg.\n");
5632 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5634 "Invalid value passed to flow_xstat devarg.\n");
5638 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5639 if (BNXT_FLOW_XSTATS_EN(bp))
5640 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5646 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5647 const char *value, void *opaque_arg)
5649 struct bnxt *bp = opaque_arg;
5650 unsigned long max_num_kflows;
5653 if (!value || !opaque_arg) {
5655 "Invalid parameter passed to max_num_kflows devarg.\n");
5659 max_num_kflows = strtoul(value, &end, 10);
5660 if (end == NULL || *end != '\0' ||
5661 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5663 "Invalid parameter passed to max_num_kflows devarg.\n");
5667 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5669 "Invalid value passed to max_num_kflows devarg.\n");
5673 bp->max_num_kflows = max_num_kflows;
5674 if (bp->max_num_kflows)
5675 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5682 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5684 struct rte_kvargs *kvlist;
5686 if (devargs == NULL)
5689 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5694 * Handler for "truflow" devarg.
5695 * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5697 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5698 bnxt_parse_devarg_truflow, bp);
5701 * Handler for "flow_xstat" devarg.
5702 * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5704 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5705 bnxt_parse_devarg_flow_xstat, bp);
5708 * Handler for "max_num_kflows" devarg.
5709 * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5711 rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5712 bnxt_parse_devarg_max_num_kflows, bp);
5714 rte_kvargs_free(kvlist);
5717 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5721 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5722 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5725 "Failed to alloc switch domain: %d\n", rc);
5728 "Switch domain allocated %d\n",
5729 bp->switch_domain_id);
5736 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5738 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5739 static int version_printed;
5743 if (version_printed++ == 0)
5744 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5746 eth_dev->dev_ops = &bnxt_dev_ops;
5747 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5748 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5751 * For secondary processes, we don't initialise any further
5752 * as primary has already done this work.
5754 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5757 rte_eth_copy_pci_info(eth_dev, pci_dev);
5759 bp = eth_dev->data->dev_private;
5761 /* Parse dev arguments passed on when starting the DPDK application. */
5762 bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5764 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5766 if (bnxt_vf_pciid(pci_dev->id.device_id))
5767 bp->flags |= BNXT_FLAG_VF;
5769 if (bnxt_thor_device(pci_dev->id.device_id))
5770 bp->flags |= BNXT_FLAG_THOR_CHIP;
5772 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5773 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5774 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5775 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5776 bp->flags |= BNXT_FLAG_STINGRAY;
5778 rc = bnxt_init_board(eth_dev);
5781 "Failed to initialize board rc: %x\n", rc);
5785 rc = bnxt_alloc_pf_info(bp);
5789 rc = bnxt_alloc_link_info(bp);
5793 rc = bnxt_alloc_parent_info(bp);
5797 rc = bnxt_alloc_hwrm_resources(bp);
5800 "Failed to allocate hwrm resource rc: %x\n", rc);
5803 rc = bnxt_alloc_leds_info(bp);
5807 rc = bnxt_alloc_cos_queues(bp);
5811 rc = bnxt_init_resources(bp, false);
5815 rc = bnxt_alloc_stats_mem(bp);
5819 bnxt_alloc_switch_domain(bp);
5821 /* Pass the information to the rte_eth_dev_close() that it should also
5822 * release the private port resources.
5824 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5827 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5828 pci_dev->mem_resource[0].phys_addr,
5829 pci_dev->mem_resource[0].addr);
5834 bnxt_dev_uninit(eth_dev);
5839 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5848 ctx->dma = RTE_BAD_IOVA;
5849 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5852 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5854 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5855 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5856 bp->flow_stat->rx_fc_out_tbl.ctx_id,
5857 bp->flow_stat->max_fc,
5860 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5861 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5862 bp->flow_stat->tx_fc_out_tbl.ctx_id,
5863 bp->flow_stat->max_fc,
5866 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5867 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5868 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5870 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5871 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5872 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5874 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5875 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5876 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5878 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5879 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5880 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5883 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5885 bnxt_unregister_fc_ctx_mem(bp);
5887 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5888 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5889 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5890 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5893 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5895 if (BNXT_FLOW_XSTATS_EN(bp))
5896 bnxt_uninit_fc_ctx_mem(bp);
5900 bnxt_free_error_recovery_info(struct bnxt *bp)
5902 rte_free(bp->recovery_info);
5903 bp->recovery_info = NULL;
5904 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5908 bnxt_uninit_locks(struct bnxt *bp)
5910 pthread_mutex_destroy(&bp->flow_lock);
5911 pthread_mutex_destroy(&bp->def_cp_lock);
5913 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5917 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5922 bnxt_free_mem(bp, reconfig_dev);
5923 bnxt_hwrm_func_buf_unrgtr(bp);
5924 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5925 bp->flags &= ~BNXT_FLAG_REGISTERED;
5926 bnxt_free_ctx_mem(bp);
5927 if (!reconfig_dev) {
5928 bnxt_free_hwrm_resources(bp);
5929 bnxt_free_error_recovery_info(bp);
5932 bnxt_uninit_ctx_mem(bp);
5934 bnxt_uninit_locks(bp);
5935 bnxt_free_flow_stats_info(bp);
5936 bnxt_free_rep_info(bp);
5937 rte_free(bp->ptp_cfg);
5943 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5945 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5948 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5950 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5951 bnxt_dev_close_op(eth_dev);
5956 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5958 struct bnxt *bp = eth_dev->data->dev_private;
5959 struct rte_eth_dev *vf_rep_eth_dev;
5965 for (i = 0; i < bp->num_reps; i++) {
5966 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5967 if (!vf_rep_eth_dev)
5969 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_vf_representor_uninit);
5971 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5976 static void bnxt_free_rep_info(struct bnxt *bp)
5978 rte_free(bp->rep_info);
5979 bp->rep_info = NULL;
5980 rte_free(bp->cfa_code_map);
5981 bp->cfa_code_map = NULL;
5984 static int bnxt_init_rep_info(struct bnxt *bp)
5991 bp->rep_info = rte_zmalloc("bnxt_rep_info",
5992 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5994 if (!bp->rep_info) {
5995 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5998 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5999 sizeof(*bp->cfa_code_map) *
6000 BNXT_MAX_CFA_CODE, 0);
6001 if (!bp->cfa_code_map) {
6002 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6003 bnxt_free_rep_info(bp);
6007 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6008 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6010 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6012 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6013 bnxt_free_rep_info(bp);
6019 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6020 struct rte_eth_devargs eth_da,
6021 struct rte_eth_dev *backing_eth_dev)
6023 struct rte_eth_dev *vf_rep_eth_dev;
6024 char name[RTE_ETH_NAME_MAX_LEN];
6025 struct bnxt *backing_bp;
6029 num_rep = eth_da.nb_representor_ports;
6030 if (num_rep > BNXT_MAX_VF_REPS) {
6031 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6032 num_rep, BNXT_MAX_VF_REPS);
6036 if (num_rep > RTE_MAX_ETHPORTS) {
6038 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6039 num_rep, RTE_MAX_ETHPORTS);
6043 backing_bp = backing_eth_dev->data->dev_private;
6045 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6047 "Not a PF or trusted VF. No Representor support\n");
6048 /* Returning an error is not an option.
6049 * Applications are not handling this correctly
6054 if (bnxt_init_rep_info(backing_bp))
6057 for (i = 0; i < num_rep; i++) {
6058 struct bnxt_vf_representor representor = {
6059 .vf_id = eth_da.representor_ports[i],
6060 .switch_domain_id = backing_bp->switch_domain_id,
6061 .parent_dev = backing_eth_dev
6064 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6065 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6066 representor.vf_id, BNXT_MAX_VF_REPS);
6070 /* representor port net_bdf_port */
6071 snprintf(name, sizeof(name), "net_%s_representor_%d",
6072 pci_dev->device.name, eth_da.representor_ports[i]);
6074 ret = rte_eth_dev_create(&pci_dev->device, name,
6075 sizeof(struct bnxt_vf_representor),
6077 bnxt_vf_representor_init,
6081 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6082 if (!vf_rep_eth_dev) {
6083 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6084 " for VF-Rep: %s.", name);
6085 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6089 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6091 backing_bp->num_reps++;
6093 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6094 "representor %s.", name);
6095 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6102 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6103 struct rte_pci_device *pci_dev)
6105 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6106 struct rte_eth_dev *backing_eth_dev;
6110 if (pci_dev->device.devargs) {
6111 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6117 num_rep = eth_da.nb_representor_ports;
6118 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6121 /* We could come here after first level of probe is already invoked
6122 * as part of an application bringup(OVS-DPDK vswitchd), so first check
6123 * for already allocated eth_dev for the backing device (PF/Trusted VF)
6125 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6126 if (backing_eth_dev == NULL) {
6127 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6128 sizeof(struct bnxt),
6129 eth_dev_pci_specific_init, pci_dev,
6130 bnxt_dev_init, NULL);
6132 if (ret || !num_rep)
6135 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6138 /* probe representor ports now */
6139 ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev);
6144 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6146 struct rte_eth_dev *eth_dev;
6148 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6150 return 0; /* Invoked typically only by OVS-DPDK, by the
6151 * time it comes here the eth_dev is already
6152 * deleted by rte_eth_dev_close(), so returning
6153 * +ve value will at least help in proper cleanup
6156 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6157 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6158 return rte_eth_dev_destroy(eth_dev,
6159 bnxt_vf_representor_uninit);
6161 return rte_eth_dev_destroy(eth_dev,
6164 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6168 static struct rte_pci_driver bnxt_rte_pmd = {
6169 .id_table = bnxt_pci_id_map,
6170 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6171 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6174 .probe = bnxt_pci_probe,
6175 .remove = bnxt_pci_remove,
6179 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6181 if (strcmp(dev->device->driver->name, drv->driver.name))
6187 bool is_bnxt_supported(struct rte_eth_dev *dev)
6189 return is_device_supported(dev, &bnxt_rte_pmd);
6192 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6193 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6194 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6195 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");