1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
30 #define DRV_MODULE_NAME "bnxt"
31 static const char bnxt_version[] =
32 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
33 int bnxt_logtype_driver;
36 * The set of PCI devices this driver supports
38 static const struct rte_pci_id bnxt_pci_id_map[] = {
39 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
40 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
41 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
42 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
43 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
45 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
92 { .vendor_id = 0, /* sentinel */ },
95 #define BNXT_ETH_RSS_SUPPORT ( \
97 ETH_RSS_NONFRAG_IPV4_TCP | \
98 ETH_RSS_NONFRAG_IPV4_UDP | \
100 ETH_RSS_NONFRAG_IPV6_TCP | \
101 ETH_RSS_NONFRAG_IPV6_UDP)
103 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
104 DEV_TX_OFFLOAD_IPV4_CKSUM | \
105 DEV_TX_OFFLOAD_TCP_CKSUM | \
106 DEV_TX_OFFLOAD_UDP_CKSUM | \
107 DEV_TX_OFFLOAD_TCP_TSO | \
108 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
109 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
110 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
111 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
112 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
113 DEV_TX_OFFLOAD_QINQ_INSERT | \
114 DEV_TX_OFFLOAD_MULTI_SEGS)
116 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
117 DEV_RX_OFFLOAD_VLAN_STRIP | \
118 DEV_RX_OFFLOAD_IPV4_CKSUM | \
119 DEV_RX_OFFLOAD_UDP_CKSUM | \
120 DEV_RX_OFFLOAD_TCP_CKSUM | \
121 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
122 DEV_RX_OFFLOAD_JUMBO_FRAME | \
123 DEV_RX_OFFLOAD_KEEP_CRC | \
124 DEV_RX_OFFLOAD_VLAN_EXTEND | \
125 DEV_RX_OFFLOAD_TCP_LRO | \
126 DEV_RX_OFFLOAD_SCATTER)
128 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
129 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
130 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
131 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
132 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
133 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
135 int is_bnxt_in_error(struct bnxt *bp)
137 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
139 if (bp->flags & BNXT_FLAG_FW_RESET)
145 /***********************/
148 * High level utility functions
151 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
153 if (!BNXT_CHIP_THOR(bp))
156 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
157 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
158 BNXT_RSS_ENTRIES_PER_CTX_THOR;
161 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
163 if (!BNXT_CHIP_THOR(bp))
164 return HW_HASH_INDEX_SIZE;
166 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
169 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
171 bnxt_free_filter_mem(bp);
172 bnxt_free_vnic_attributes(bp);
173 bnxt_free_vnic_mem(bp);
175 /* tx/rx rings are configured as part of *_queue_setup callbacks.
176 * If the number of rings change across fw update,
177 * we don't have much choice except to warn the user.
181 bnxt_free_tx_rings(bp);
182 bnxt_free_rx_rings(bp);
184 bnxt_free_async_cp_ring(bp);
185 bnxt_free_rxtx_nq_ring(bp);
187 rte_free(bp->grp_info);
191 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
195 rc = bnxt_alloc_ring_grps(bp);
199 rc = bnxt_alloc_async_ring_struct(bp);
203 rc = bnxt_alloc_vnic_mem(bp);
207 rc = bnxt_alloc_vnic_attributes(bp);
211 rc = bnxt_alloc_filter_mem(bp);
215 rc = bnxt_alloc_async_cp_ring(bp);
219 rc = bnxt_alloc_rxtx_nq_ring(bp);
226 bnxt_free_mem(bp, reconfig);
230 static int bnxt_init_chip(struct bnxt *bp)
232 struct bnxt_rx_queue *rxq;
233 struct rte_eth_link new;
234 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
235 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
236 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
237 uint64_t rx_offloads = dev_conf->rxmode.offloads;
238 uint32_t intr_vector = 0;
239 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
240 uint32_t vec = BNXT_MISC_VEC_ID;
244 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
245 bp->eth_dev->data->dev_conf.rxmode.offloads |=
246 DEV_RX_OFFLOAD_JUMBO_FRAME;
247 bp->flags |= BNXT_FLAG_JUMBO;
249 bp->eth_dev->data->dev_conf.rxmode.offloads &=
250 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
251 bp->flags &= ~BNXT_FLAG_JUMBO;
254 /* THOR does not support ring groups.
255 * But we will use the array to save RSS context IDs.
257 if (BNXT_CHIP_THOR(bp))
258 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
260 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
262 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
266 rc = bnxt_alloc_hwrm_rings(bp);
268 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
272 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
274 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
278 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
281 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
282 if (bp->rx_cos_queue[i].id != 0xff) {
283 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
287 "Num pools more than FW profile\n");
291 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
297 rc = bnxt_mq_rx_configure(bp);
299 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
303 /* VNIC configuration */
304 for (i = 0; i < bp->nr_vnics; i++) {
305 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
306 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
308 rc = bnxt_vnic_grp_alloc(bp, vnic);
312 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
313 i, vnic, vnic->fw_grp_ids);
315 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
317 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
322 /* Alloc RSS context only if RSS mode is enabled */
323 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
324 int j, nr_ctxs = bnxt_rss_ctxts(bp);
327 for (j = 0; j < nr_ctxs; j++) {
328 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
334 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
338 vnic->num_lb_ctxts = nr_ctxs;
342 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
343 * setting is not available at this time, it will not be
344 * configured correctly in the CFA.
346 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
347 vnic->vlan_strip = true;
349 vnic->vlan_strip = false;
351 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
353 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
358 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
361 "HWRM vnic %d filter failure rc: %x\n",
366 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
367 rxq = bp->eth_dev->data->rx_queues[j];
370 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
371 j, rxq->vnic, rxq->vnic->fw_grp_ids);
373 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
374 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
377 rc = bnxt_vnic_rss_configure(bp, vnic);
380 "HWRM vnic set RSS failure rc: %x\n", rc);
384 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
386 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
387 DEV_RX_OFFLOAD_TCP_LRO)
388 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
390 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
392 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
395 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
399 /* check and configure queue intr-vector mapping */
400 if ((rte_intr_cap_multiple(intr_handle) ||
401 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
402 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
403 intr_vector = bp->eth_dev->data->nb_rx_queues;
404 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
405 if (intr_vector > bp->rx_cp_nr_rings) {
406 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
410 rc = rte_intr_efd_enable(intr_handle, intr_vector);
415 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
416 intr_handle->intr_vec =
417 rte_zmalloc("intr_vec",
418 bp->eth_dev->data->nb_rx_queues *
420 if (intr_handle->intr_vec == NULL) {
421 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
422 " intr_vec", bp->eth_dev->data->nb_rx_queues);
426 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
427 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
428 intr_handle->intr_vec, intr_handle->nb_efd,
429 intr_handle->max_intr);
430 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
432 intr_handle->intr_vec[queue_id] =
433 vec + BNXT_RX_VEC_START;
434 if (vec < base + intr_handle->nb_efd - 1)
439 /* enable uio/vfio intr/eventfd mapping */
440 rc = rte_intr_enable(intr_handle);
444 rc = bnxt_get_hwrm_link_config(bp, &new);
446 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
450 if (!bp->link_info.link_up) {
451 rc = bnxt_set_hwrm_link_config(bp, true);
454 "HWRM link config failure rc: %x\n", rc);
458 bnxt_print_link_info(bp->eth_dev);
463 rte_free(intr_handle->intr_vec);
465 rte_intr_efd_disable(intr_handle);
467 /* Some of the error status returned by FW may not be from errno.h */
474 static int bnxt_shutdown_nic(struct bnxt *bp)
476 bnxt_free_all_hwrm_resources(bp);
477 bnxt_free_all_filters(bp);
478 bnxt_free_all_vnics(bp);
483 * Device configuration and status function
486 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
487 struct rte_eth_dev_info *dev_info)
489 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
490 struct bnxt *bp = eth_dev->data->dev_private;
491 uint16_t max_vnics, i, j, vpool, vrxq;
492 unsigned int max_rx_rings;
495 rc = is_bnxt_in_error(bp);
500 dev_info->max_mac_addrs = bp->max_l2_ctx;
501 dev_info->max_hash_mac_addrs = 0;
503 /* PF/VF specifics */
505 dev_info->max_vfs = pdev->max_vfs;
507 max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
508 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
509 dev_info->max_rx_queues = max_rx_rings;
510 dev_info->max_tx_queues = max_rx_rings;
511 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
512 dev_info->hash_key_size = 40;
513 max_vnics = bp->max_vnics;
516 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
517 dev_info->max_mtu = BNXT_MAX_MTU;
519 /* Fast path specifics */
520 dev_info->min_rx_bufsize = 1;
521 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
523 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
524 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
525 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
526 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
527 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
530 dev_info->default_rxconf = (struct rte_eth_rxconf) {
536 .rx_free_thresh = 32,
537 /* If no descriptors available, pkts are dropped by default */
541 dev_info->default_txconf = (struct rte_eth_txconf) {
547 .tx_free_thresh = 32,
550 eth_dev->data->dev_conf.intr_conf.lsc = 1;
552 eth_dev->data->dev_conf.intr_conf.rxq = 1;
553 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
554 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
555 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
556 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
561 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
562 * need further investigation.
566 vpool = 64; /* ETH_64_POOLS */
567 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
568 for (i = 0; i < 4; vpool >>= 1, i++) {
569 if (max_vnics > vpool) {
570 for (j = 0; j < 5; vrxq >>= 1, j++) {
571 if (dev_info->max_rx_queues > vrxq) {
577 /* Not enough resources to support VMDq */
581 /* Not enough resources to support VMDq */
585 dev_info->max_vmdq_pools = vpool;
586 dev_info->vmdq_queue_num = vrxq;
588 dev_info->vmdq_pool_base = 0;
589 dev_info->vmdq_queue_base = 0;
594 /* Configure the device based on the configuration provided */
595 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
597 struct bnxt *bp = eth_dev->data->dev_private;
598 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
601 bp->rx_queues = (void *)eth_dev->data->rx_queues;
602 bp->tx_queues = (void *)eth_dev->data->tx_queues;
603 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
604 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
606 rc = is_bnxt_in_error(bp);
610 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
611 rc = bnxt_hwrm_check_vf_rings(bp);
613 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
617 /* If a resource has already been allocated - in this case
618 * it is the async completion ring, free it. Reallocate it after
619 * resource reservation. This will ensure the resource counts
620 * are calculated correctly.
623 pthread_mutex_lock(&bp->def_cp_lock);
625 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
626 bnxt_disable_int(bp);
627 bnxt_free_cp_ring(bp, bp->async_cp_ring);
630 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
632 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
633 pthread_mutex_unlock(&bp->def_cp_lock);
637 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
638 rc = bnxt_alloc_async_cp_ring(bp);
640 pthread_mutex_unlock(&bp->def_cp_lock);
646 pthread_mutex_unlock(&bp->def_cp_lock);
648 /* legacy driver needs to get updated values */
649 rc = bnxt_hwrm_func_qcaps(bp);
651 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
656 /* Inherit new configurations */
657 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
658 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
659 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
660 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
661 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
665 if (BNXT_HAS_RING_GRPS(bp) &&
666 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
669 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
670 bp->max_vnics < eth_dev->data->nb_rx_queues)
673 bp->rx_cp_nr_rings = bp->rx_nr_rings;
674 bp->tx_cp_nr_rings = bp->tx_nr_rings;
676 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
678 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
679 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
681 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
687 "Insufficient resources to support requested config\n");
689 "Num Queues Requested: Tx %d, Rx %d\n",
690 eth_dev->data->nb_tx_queues,
691 eth_dev->data->nb_rx_queues);
693 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
694 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
695 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
699 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
701 struct rte_eth_link *link = ð_dev->data->dev_link;
703 if (link->link_status)
704 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
705 eth_dev->data->port_id,
706 (uint32_t)link->link_speed,
707 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
708 ("full-duplex") : ("half-duplex\n"));
710 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
711 eth_dev->data->port_id);
715 * Determine whether the current configuration requires support for scattered
716 * receive; return 1 if scattered receive is required and 0 if not.
718 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
723 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
726 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
727 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
729 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
730 RTE_PKTMBUF_HEADROOM);
731 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
737 static eth_rx_burst_t
738 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
741 #ifndef RTE_LIBRTE_IEEE1588
743 * Vector mode receive can be enabled only if scatter rx is not
744 * in use and rx offloads are limited to VLAN stripping and
747 if (!eth_dev->data->scattered_rx &&
748 !(eth_dev->data->dev_conf.rxmode.offloads &
749 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
750 DEV_RX_OFFLOAD_KEEP_CRC |
751 DEV_RX_OFFLOAD_JUMBO_FRAME |
752 DEV_RX_OFFLOAD_IPV4_CKSUM |
753 DEV_RX_OFFLOAD_UDP_CKSUM |
754 DEV_RX_OFFLOAD_TCP_CKSUM |
755 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
756 DEV_RX_OFFLOAD_VLAN_FILTER))) {
757 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
758 eth_dev->data->port_id);
759 return bnxt_recv_pkts_vec;
761 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
762 eth_dev->data->port_id);
764 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
765 eth_dev->data->port_id,
766 eth_dev->data->scattered_rx,
767 eth_dev->data->dev_conf.rxmode.offloads);
770 return bnxt_recv_pkts;
773 static eth_tx_burst_t
774 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
777 #ifndef RTE_LIBRTE_IEEE1588
779 * Vector mode transmit can be enabled only if not using scatter rx
782 if (!eth_dev->data->scattered_rx &&
783 !eth_dev->data->dev_conf.txmode.offloads) {
784 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
785 eth_dev->data->port_id);
786 return bnxt_xmit_pkts_vec;
788 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
789 eth_dev->data->port_id);
791 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
792 eth_dev->data->port_id,
793 eth_dev->data->scattered_rx,
794 eth_dev->data->dev_conf.txmode.offloads);
797 return bnxt_xmit_pkts;
800 static int bnxt_handle_if_change_status(struct bnxt *bp)
804 /* Since fw has undergone a reset and lost all contexts,
805 * set fatal flag to not issue hwrm during cleanup
807 bp->flags |= BNXT_FLAG_FATAL_ERROR;
808 bnxt_uninit_resources(bp, true);
810 /* clear fatal flag so that re-init happens */
811 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
812 rc = bnxt_init_resources(bp, true);
814 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
819 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
821 struct bnxt *bp = eth_dev->data->dev_private;
822 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
826 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
827 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
831 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
833 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
834 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
837 rc = bnxt_hwrm_if_change(bp, 1);
839 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
840 rc = bnxt_handle_if_change_status(bp);
847 rc = bnxt_init_chip(bp);
851 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
853 bnxt_link_update_op(eth_dev, 1);
855 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
856 vlan_mask |= ETH_VLAN_FILTER_MASK;
857 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
858 vlan_mask |= ETH_VLAN_STRIP_MASK;
859 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
863 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
864 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
866 bp->flags |= BNXT_FLAG_INIT_DONE;
867 eth_dev->data->dev_started = 1;
869 pthread_mutex_lock(&bp->def_cp_lock);
870 bnxt_schedule_fw_health_check(bp);
871 pthread_mutex_unlock(&bp->def_cp_lock);
875 bnxt_hwrm_if_change(bp, 0);
876 bnxt_shutdown_nic(bp);
877 bnxt_free_tx_mbufs(bp);
878 bnxt_free_rx_mbufs(bp);
882 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
884 struct bnxt *bp = eth_dev->data->dev_private;
887 if (!bp->link_info.link_up)
888 rc = bnxt_set_hwrm_link_config(bp, true);
890 eth_dev->data->dev_link.link_status = 1;
892 bnxt_print_link_info(eth_dev);
896 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
898 struct bnxt *bp = eth_dev->data->dev_private;
900 eth_dev->data->dev_link.link_status = 0;
901 bnxt_set_hwrm_link_config(bp, false);
902 bp->link_info.link_up = 0;
907 /* Unload the driver, release resources */
908 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
910 struct bnxt *bp = eth_dev->data->dev_private;
911 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
912 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
914 eth_dev->data->dev_started = 0;
915 /* Prevent crashes when queues are still in use */
916 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
917 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
919 bnxt_disable_int(bp);
921 /* disable uio/vfio intr/eventfd mapping */
922 rte_intr_disable(intr_handle);
924 bnxt_cancel_fw_health_check(bp);
926 bp->flags &= ~BNXT_FLAG_INIT_DONE;
927 if (bp->eth_dev->data->dev_started) {
928 /* TBD: STOP HW queues DMA */
929 eth_dev->data->dev_link.link_status = 0;
931 bnxt_dev_set_link_down_op(eth_dev);
933 /* Wait for link to be reset and the async notification to process.
934 * During reset recovery, there is no need to wait
936 if (!is_bnxt_in_error(bp))
937 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
939 /* Clean queue intr-vector mapping */
940 rte_intr_efd_disable(intr_handle);
941 if (intr_handle->intr_vec != NULL) {
942 rte_free(intr_handle->intr_vec);
943 intr_handle->intr_vec = NULL;
946 bnxt_hwrm_port_clr_stats(bp);
947 bnxt_free_tx_mbufs(bp);
948 bnxt_free_rx_mbufs(bp);
949 /* Process any remaining notifications in default completion queue */
950 bnxt_int_handler(eth_dev);
951 bnxt_shutdown_nic(bp);
952 bnxt_hwrm_if_change(bp, 0);
957 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
959 struct bnxt *bp = eth_dev->data->dev_private;
961 if (bp->dev_stopped == 0)
962 bnxt_dev_stop_op(eth_dev);
964 if (eth_dev->data->mac_addrs != NULL) {
965 rte_free(eth_dev->data->mac_addrs);
966 eth_dev->data->mac_addrs = NULL;
968 if (bp->grp_info != NULL) {
969 rte_free(bp->grp_info);
973 bnxt_dev_uninit(eth_dev);
976 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
979 struct bnxt *bp = eth_dev->data->dev_private;
980 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
981 struct bnxt_vnic_info *vnic;
982 struct bnxt_filter_info *filter, *temp_filter;
985 if (is_bnxt_in_error(bp))
989 * Loop through all VNICs from the specified filter flow pools to
990 * remove the corresponding MAC addr filter
992 for (i = 0; i < bp->nr_vnics; i++) {
993 if (!(pool_mask & (1ULL << i)))
996 vnic = &bp->vnic_info[i];
997 filter = STAILQ_FIRST(&vnic->filter);
999 temp_filter = STAILQ_NEXT(filter, next);
1000 if (filter->mac_index == index) {
1001 STAILQ_REMOVE(&vnic->filter, filter,
1002 bnxt_filter_info, next);
1003 bnxt_hwrm_clear_l2_filter(bp, filter);
1004 filter->mac_index = INVALID_MAC_INDEX;
1005 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1006 bnxt_free_filter(bp, filter);
1008 filter = temp_filter;
1013 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1014 struct rte_ether_addr *mac_addr, uint32_t index,
1017 struct bnxt_filter_info *filter;
1020 /* Attach requested MAC address to the new l2_filter */
1021 STAILQ_FOREACH(filter, &vnic->filter, next) {
1022 if (filter->mac_index == index) {
1024 "MAC addr already existed for pool %d\n",
1030 filter = bnxt_alloc_filter(bp);
1032 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1036 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1037 * if the MAC that's been programmed now is a different one, then,
1038 * copy that addr to filter->l2_addr
1041 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1042 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1044 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1046 filter->mac_index = index;
1047 if (filter->mac_index == 0)
1048 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1050 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1052 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1053 bnxt_free_filter(bp, filter);
1059 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1060 struct rte_ether_addr *mac_addr,
1061 uint32_t index, uint32_t pool)
1063 struct bnxt *bp = eth_dev->data->dev_private;
1064 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1067 rc = is_bnxt_in_error(bp);
1071 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1072 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1077 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1081 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1086 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1089 struct bnxt *bp = eth_dev->data->dev_private;
1090 struct rte_eth_link new;
1091 unsigned int cnt = BNXT_LINK_WAIT_CNT;
1093 rc = is_bnxt_in_error(bp);
1097 memset(&new, 0, sizeof(new));
1099 /* Retrieve link info from hardware */
1100 rc = bnxt_get_hwrm_link_config(bp, &new);
1102 new.link_speed = ETH_LINK_SPEED_100M;
1103 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1105 "Failed to retrieve link rc = 0x%x!\n", rc);
1109 if (!wait_to_complete || new.link_status)
1112 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1116 /* Timed out or success */
1117 if (new.link_status != eth_dev->data->dev_link.link_status ||
1118 new.link_speed != eth_dev->data->dev_link.link_speed) {
1119 rte_eth_linkstatus_set(eth_dev, &new);
1121 _rte_eth_dev_callback_process(eth_dev,
1122 RTE_ETH_EVENT_INTR_LSC,
1125 bnxt_print_link_info(eth_dev);
1131 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1133 struct bnxt *bp = eth_dev->data->dev_private;
1134 struct bnxt_vnic_info *vnic;
1138 rc = is_bnxt_in_error(bp);
1142 if (bp->vnic_info == NULL)
1145 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1147 old_flags = vnic->flags;
1148 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1149 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1151 vnic->flags = old_flags;
1156 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1158 struct bnxt *bp = eth_dev->data->dev_private;
1159 struct bnxt_vnic_info *vnic;
1163 rc = is_bnxt_in_error(bp);
1167 if (bp->vnic_info == NULL)
1170 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1172 old_flags = vnic->flags;
1173 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1174 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1176 vnic->flags = old_flags;
1181 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1183 struct bnxt *bp = eth_dev->data->dev_private;
1184 struct bnxt_vnic_info *vnic;
1188 rc = is_bnxt_in_error(bp);
1192 if (bp->vnic_info == NULL)
1195 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1197 old_flags = vnic->flags;
1198 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1199 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1201 vnic->flags = old_flags;
1206 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1208 struct bnxt *bp = eth_dev->data->dev_private;
1209 struct bnxt_vnic_info *vnic;
1213 rc = is_bnxt_in_error(bp);
1217 if (bp->vnic_info == NULL)
1220 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1222 old_flags = vnic->flags;
1223 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1224 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1226 vnic->flags = old_flags;
1231 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1232 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1234 if (qid >= bp->rx_nr_rings)
1237 return bp->eth_dev->data->rx_queues[qid];
1240 /* Return rxq corresponding to a given rss table ring/group ID. */
1241 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1243 struct bnxt_rx_queue *rxq;
1246 if (!BNXT_HAS_RING_GRPS(bp)) {
1247 for (i = 0; i < bp->rx_nr_rings; i++) {
1248 rxq = bp->eth_dev->data->rx_queues[i];
1249 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1253 for (i = 0; i < bp->rx_nr_rings; i++) {
1254 if (bp->grp_info[i].fw_grp_id == fwr)
1259 return INVALID_HW_RING_ID;
1262 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1263 struct rte_eth_rss_reta_entry64 *reta_conf,
1266 struct bnxt *bp = eth_dev->data->dev_private;
1267 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1268 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1269 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1273 rc = is_bnxt_in_error(bp);
1277 if (!vnic->rss_table)
1280 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1283 if (reta_size != tbl_size) {
1284 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1285 "(%d) must equal the size supported by the hardware "
1286 "(%d)\n", reta_size, tbl_size);
1290 for (i = 0; i < reta_size; i++) {
1291 struct bnxt_rx_queue *rxq;
1293 idx = i / RTE_RETA_GROUP_SIZE;
1294 sft = i % RTE_RETA_GROUP_SIZE;
1296 if (!(reta_conf[idx].mask & (1ULL << sft)))
1299 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1301 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1305 if (BNXT_CHIP_THOR(bp)) {
1306 vnic->rss_table[i * 2] =
1307 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1308 vnic->rss_table[i * 2 + 1] =
1309 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1311 vnic->rss_table[i] =
1312 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1316 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1320 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1321 struct rte_eth_rss_reta_entry64 *reta_conf,
1324 struct bnxt *bp = eth_dev->data->dev_private;
1325 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1326 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1327 uint16_t idx, sft, i;
1330 rc = is_bnxt_in_error(bp);
1334 /* Retrieve from the default VNIC */
1337 if (!vnic->rss_table)
1340 if (reta_size != tbl_size) {
1341 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1342 "(%d) must equal the size supported by the hardware "
1343 "(%d)\n", reta_size, tbl_size);
1347 for (idx = 0, i = 0; i < reta_size; i++) {
1348 idx = i / RTE_RETA_GROUP_SIZE;
1349 sft = i % RTE_RETA_GROUP_SIZE;
1351 if (reta_conf[idx].mask & (1ULL << sft)) {
1354 if (BNXT_CHIP_THOR(bp))
1355 qid = bnxt_rss_to_qid(bp,
1356 vnic->rss_table[i * 2]);
1358 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1360 if (qid == INVALID_HW_RING_ID) {
1361 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1364 reta_conf[idx].reta[sft] = qid;
1371 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1372 struct rte_eth_rss_conf *rss_conf)
1374 struct bnxt *bp = eth_dev->data->dev_private;
1375 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1376 struct bnxt_vnic_info *vnic;
1379 rc = is_bnxt_in_error(bp);
1384 * If RSS enablement were different than dev_configure,
1385 * then return -EINVAL
1387 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1388 if (!rss_conf->rss_hf)
1389 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1391 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1395 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1396 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1398 /* Update the default RSS VNIC(s) */
1399 vnic = &bp->vnic_info[0];
1400 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1403 * If hashkey is not specified, use the previously configured
1406 if (!rss_conf->rss_key)
1409 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1411 "Invalid hashkey length, should be 16 bytes\n");
1414 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1417 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1421 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1422 struct rte_eth_rss_conf *rss_conf)
1424 struct bnxt *bp = eth_dev->data->dev_private;
1425 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1427 uint32_t hash_types;
1429 rc = is_bnxt_in_error(bp);
1433 /* RSS configuration is the same for all VNICs */
1434 if (vnic && vnic->rss_hash_key) {
1435 if (rss_conf->rss_key) {
1436 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1437 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1438 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1441 hash_types = vnic->hash_type;
1442 rss_conf->rss_hf = 0;
1443 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1444 rss_conf->rss_hf |= ETH_RSS_IPV4;
1445 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1447 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1448 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1450 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1452 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1453 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1455 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1457 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1458 rss_conf->rss_hf |= ETH_RSS_IPV6;
1459 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1461 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1462 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1464 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1466 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1467 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1469 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1473 "Unknwon RSS config from firmware (%08x), RSS disabled",
1478 rss_conf->rss_hf = 0;
1483 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1484 struct rte_eth_fc_conf *fc_conf)
1486 struct bnxt *bp = dev->data->dev_private;
1487 struct rte_eth_link link_info;
1490 rc = is_bnxt_in_error(bp);
1494 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1498 memset(fc_conf, 0, sizeof(*fc_conf));
1499 if (bp->link_info.auto_pause)
1500 fc_conf->autoneg = 1;
1501 switch (bp->link_info.pause) {
1503 fc_conf->mode = RTE_FC_NONE;
1505 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1506 fc_conf->mode = RTE_FC_TX_PAUSE;
1508 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1509 fc_conf->mode = RTE_FC_RX_PAUSE;
1511 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1512 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1513 fc_conf->mode = RTE_FC_FULL;
1519 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1520 struct rte_eth_fc_conf *fc_conf)
1522 struct bnxt *bp = dev->data->dev_private;
1525 rc = is_bnxt_in_error(bp);
1529 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1530 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1534 switch (fc_conf->mode) {
1536 bp->link_info.auto_pause = 0;
1537 bp->link_info.force_pause = 0;
1539 case RTE_FC_RX_PAUSE:
1540 if (fc_conf->autoneg) {
1541 bp->link_info.auto_pause =
1542 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1543 bp->link_info.force_pause = 0;
1545 bp->link_info.auto_pause = 0;
1546 bp->link_info.force_pause =
1547 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1550 case RTE_FC_TX_PAUSE:
1551 if (fc_conf->autoneg) {
1552 bp->link_info.auto_pause =
1553 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1554 bp->link_info.force_pause = 0;
1556 bp->link_info.auto_pause = 0;
1557 bp->link_info.force_pause =
1558 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1562 if (fc_conf->autoneg) {
1563 bp->link_info.auto_pause =
1564 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1565 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1566 bp->link_info.force_pause = 0;
1568 bp->link_info.auto_pause = 0;
1569 bp->link_info.force_pause =
1570 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1571 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1575 return bnxt_set_hwrm_link_config(bp, true);
1578 /* Add UDP tunneling port */
1580 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1581 struct rte_eth_udp_tunnel *udp_tunnel)
1583 struct bnxt *bp = eth_dev->data->dev_private;
1584 uint16_t tunnel_type = 0;
1587 rc = is_bnxt_in_error(bp);
1591 switch (udp_tunnel->prot_type) {
1592 case RTE_TUNNEL_TYPE_VXLAN:
1593 if (bp->vxlan_port_cnt) {
1594 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1595 udp_tunnel->udp_port);
1596 if (bp->vxlan_port != udp_tunnel->udp_port) {
1597 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1600 bp->vxlan_port_cnt++;
1604 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1605 bp->vxlan_port_cnt++;
1607 case RTE_TUNNEL_TYPE_GENEVE:
1608 if (bp->geneve_port_cnt) {
1609 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1610 udp_tunnel->udp_port);
1611 if (bp->geneve_port != udp_tunnel->udp_port) {
1612 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1615 bp->geneve_port_cnt++;
1619 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1620 bp->geneve_port_cnt++;
1623 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1626 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1632 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1633 struct rte_eth_udp_tunnel *udp_tunnel)
1635 struct bnxt *bp = eth_dev->data->dev_private;
1636 uint16_t tunnel_type = 0;
1640 rc = is_bnxt_in_error(bp);
1644 switch (udp_tunnel->prot_type) {
1645 case RTE_TUNNEL_TYPE_VXLAN:
1646 if (!bp->vxlan_port_cnt) {
1647 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1650 if (bp->vxlan_port != udp_tunnel->udp_port) {
1651 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1652 udp_tunnel->udp_port, bp->vxlan_port);
1655 if (--bp->vxlan_port_cnt)
1659 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1660 port = bp->vxlan_fw_dst_port_id;
1662 case RTE_TUNNEL_TYPE_GENEVE:
1663 if (!bp->geneve_port_cnt) {
1664 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1667 if (bp->geneve_port != udp_tunnel->udp_port) {
1668 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1669 udp_tunnel->udp_port, bp->geneve_port);
1672 if (--bp->geneve_port_cnt)
1676 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1677 port = bp->geneve_fw_dst_port_id;
1680 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1684 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1687 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1690 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1691 bp->geneve_port = 0;
1696 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1698 struct bnxt_filter_info *filter;
1699 struct bnxt_vnic_info *vnic;
1701 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1703 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1704 filter = STAILQ_FIRST(&vnic->filter);
1706 /* Search for this matching MAC+VLAN filter */
1707 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1708 /* Delete the filter */
1709 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1712 STAILQ_REMOVE(&vnic->filter, filter,
1713 bnxt_filter_info, next);
1714 bnxt_free_filter(bp, filter);
1716 "Deleted vlan filter for %d\n",
1720 filter = STAILQ_NEXT(filter, next);
1725 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1727 struct bnxt_filter_info *filter;
1728 struct bnxt_vnic_info *vnic;
1730 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1731 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1732 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1734 /* Implementation notes on the use of VNIC in this command:
1736 * By default, these filters belong to default vnic for the function.
1737 * Once these filters are set up, only destination VNIC can be modified.
1738 * If the destination VNIC is not specified in this command,
1739 * then the HWRM shall only create an l2 context id.
1742 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1743 filter = STAILQ_FIRST(&vnic->filter);
1744 /* Check if the VLAN has already been added */
1746 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
1749 filter = STAILQ_NEXT(filter, next);
1752 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1753 * command to create MAC+VLAN filter with the right flags, enables set.
1755 filter = bnxt_alloc_filter(bp);
1758 "MAC/VLAN filter alloc failed\n");
1761 /* MAC + VLAN ID filter */
1762 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1763 * untagged packets are received
1765 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1766 * packets and only the programmed vlan's packets are received
1768 filter->l2_ivlan = vlan_id;
1769 filter->l2_ivlan_mask = 0x0FFF;
1770 filter->enables |= en;
1771 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1773 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1775 /* Free the newly allocated filter as we were
1776 * not able to create the filter in hardware.
1778 filter->fw_l2_filter_id = UINT64_MAX;
1779 bnxt_free_filter(bp, filter);
1783 filter->mac_index = 0;
1784 /* Add this new filter to the list */
1786 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1788 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1791 "Added Vlan filter for %d\n", vlan_id);
1795 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1796 uint16_t vlan_id, int on)
1798 struct bnxt *bp = eth_dev->data->dev_private;
1801 rc = is_bnxt_in_error(bp);
1805 /* These operations apply to ALL existing MAC/VLAN filters */
1807 return bnxt_add_vlan_filter(bp, vlan_id);
1809 return bnxt_del_vlan_filter(bp, vlan_id);
1812 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1813 struct bnxt_vnic_info *vnic)
1815 struct bnxt_filter_info *filter;
1818 filter = STAILQ_FIRST(&vnic->filter);
1820 if (filter->mac_index == 0 &&
1821 !memcmp(filter->l2_addr, bp->mac_addr,
1822 RTE_ETHER_ADDR_LEN)) {
1823 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1825 STAILQ_REMOVE(&vnic->filter, filter,
1826 bnxt_filter_info, next);
1827 bnxt_free_filter(bp, filter);
1828 filter->fw_l2_filter_id = UINT64_MAX;
1832 filter = STAILQ_NEXT(filter, next);
1838 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1840 struct bnxt *bp = dev->data->dev_private;
1841 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1842 struct bnxt_vnic_info *vnic;
1846 rc = is_bnxt_in_error(bp);
1850 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1851 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1852 /* Remove any VLAN filters programmed */
1853 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1854 bnxt_del_vlan_filter(bp, i);
1856 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1860 /* Default filter will allow packets that match the
1861 * dest mac. So, it has to be deleted, otherwise, we
1862 * will endup receiving vlan packets for which the
1863 * filter is not programmed, when hw-vlan-filter
1864 * configuration is ON
1866 bnxt_del_dflt_mac_filter(bp, vnic);
1867 /* This filter will allow only untagged packets */
1868 bnxt_add_vlan_filter(bp, 0);
1870 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1871 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1873 if (mask & ETH_VLAN_STRIP_MASK) {
1874 /* Enable or disable VLAN stripping */
1875 for (i = 0; i < bp->nr_vnics; i++) {
1876 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1877 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1878 vnic->vlan_strip = true;
1880 vnic->vlan_strip = false;
1881 bnxt_hwrm_vnic_cfg(bp, vnic);
1883 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1884 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1887 if (mask & ETH_VLAN_EXTEND_MASK) {
1888 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1889 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1891 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1898 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1901 struct bnxt *bp = dev->data->dev_private;
1902 int qinq = dev->data->dev_conf.rxmode.offloads &
1903 DEV_RX_OFFLOAD_VLAN_EXTEND;
1905 if (vlan_type != ETH_VLAN_TYPE_INNER &&
1906 vlan_type != ETH_VLAN_TYPE_OUTER) {
1908 "Unsupported vlan type.");
1913 "QinQ not enabled. Needs to be ON as we can "
1914 "accelerate only outer vlan\n");
1918 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1920 case RTE_ETHER_TYPE_QINQ:
1922 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1924 case RTE_ETHER_TYPE_VLAN:
1926 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1930 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1934 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
1938 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
1941 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
1944 bp->outer_tpid_bd |= tpid;
1945 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
1946 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
1948 "Can accelerate only outer vlan in QinQ\n");
1956 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1957 struct rte_ether_addr *addr)
1959 struct bnxt *bp = dev->data->dev_private;
1960 /* Default Filter is tied to VNIC 0 */
1961 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1962 struct bnxt_filter_info *filter;
1965 rc = is_bnxt_in_error(bp);
1969 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1972 if (rte_is_zero_ether_addr(addr))
1975 STAILQ_FOREACH(filter, &vnic->filter, next) {
1976 /* Default Filter is at Index 0 */
1977 if (filter->mac_index != 0)
1980 memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN);
1981 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1982 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX |
1983 HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1985 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1986 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1988 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1990 memcpy(filter->l2_addr, bp->mac_addr,
1991 RTE_ETHER_ADDR_LEN);
1995 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1996 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2004 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2005 struct rte_ether_addr *mc_addr_set,
2006 uint32_t nb_mc_addr)
2008 struct bnxt *bp = eth_dev->data->dev_private;
2009 char *mc_addr_list = (char *)mc_addr_set;
2010 struct bnxt_vnic_info *vnic;
2011 uint32_t off = 0, i = 0;
2014 rc = is_bnxt_in_error(bp);
2018 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2020 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2021 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2025 /* TODO Check for Duplicate mcast addresses */
2026 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2027 for (i = 0; i < nb_mc_addr; i++) {
2028 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2029 RTE_ETHER_ADDR_LEN);
2030 off += RTE_ETHER_ADDR_LEN;
2033 vnic->mc_addr_cnt = i;
2034 if (vnic->mc_addr_cnt)
2035 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2037 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2040 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2044 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2046 struct bnxt *bp = dev->data->dev_private;
2047 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2048 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2049 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2052 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2053 fw_major, fw_minor, fw_updt);
2055 ret += 1; /* add the size of '\0' */
2056 if (fw_size < (uint32_t)ret)
2063 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2064 struct rte_eth_rxq_info *qinfo)
2066 struct bnxt_rx_queue *rxq;
2068 rxq = dev->data->rx_queues[queue_id];
2070 qinfo->mp = rxq->mb_pool;
2071 qinfo->scattered_rx = dev->data->scattered_rx;
2072 qinfo->nb_desc = rxq->nb_rx_desc;
2074 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2075 qinfo->conf.rx_drop_en = 0;
2076 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2080 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2081 struct rte_eth_txq_info *qinfo)
2083 struct bnxt_tx_queue *txq;
2085 txq = dev->data->tx_queues[queue_id];
2087 qinfo->nb_desc = txq->nb_tx_desc;
2089 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2090 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2091 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2093 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2094 qinfo->conf.tx_rs_thresh = 0;
2095 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2098 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2100 struct bnxt *bp = eth_dev->data->dev_private;
2101 uint32_t new_pkt_size;
2105 rc = is_bnxt_in_error(bp);
2109 /* Exit if receive queues are not configured yet */
2110 if (!eth_dev->data->nb_rx_queues)
2113 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2114 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2118 * If vector-mode tx/rx is active, disallow any MTU change that would
2119 * require scattered receive support.
2121 if (eth_dev->data->dev_started &&
2122 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2123 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2125 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2127 "MTU change would require scattered rx support. ");
2128 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2133 if (new_mtu > RTE_ETHER_MTU) {
2134 bp->flags |= BNXT_FLAG_JUMBO;
2135 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2136 DEV_RX_OFFLOAD_JUMBO_FRAME;
2138 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2139 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2140 bp->flags &= ~BNXT_FLAG_JUMBO;
2143 /* Is there a change in mtu setting? */
2144 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2147 for (i = 0; i < bp->nr_vnics; i++) {
2148 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2151 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2152 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2156 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2157 size -= RTE_PKTMBUF_HEADROOM;
2159 if (size < new_mtu) {
2160 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2167 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2169 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2175 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2177 struct bnxt *bp = dev->data->dev_private;
2178 uint16_t vlan = bp->vlan;
2181 rc = is_bnxt_in_error(bp);
2185 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2187 "PVID cannot be modified for this function\n");
2190 bp->vlan = on ? pvid : 0;
2192 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2199 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2201 struct bnxt *bp = dev->data->dev_private;
2204 rc = is_bnxt_in_error(bp);
2208 return bnxt_hwrm_port_led_cfg(bp, true);
2212 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2214 struct bnxt *bp = dev->data->dev_private;
2217 rc = is_bnxt_in_error(bp);
2221 return bnxt_hwrm_port_led_cfg(bp, false);
2225 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2227 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2228 uint32_t desc = 0, raw_cons = 0, cons;
2229 struct bnxt_cp_ring_info *cpr;
2230 struct bnxt_rx_queue *rxq;
2231 struct rx_pkt_cmpl *rxcmp;
2234 rc = is_bnxt_in_error(bp);
2238 rxq = dev->data->rx_queues[rx_queue_id];
2240 raw_cons = cpr->cp_raw_cons;
2243 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2244 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2245 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2247 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2259 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2261 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2262 struct bnxt_rx_ring_info *rxr;
2263 struct bnxt_cp_ring_info *cpr;
2264 struct bnxt_sw_rx_bd *rx_buf;
2265 struct rx_pkt_cmpl *rxcmp;
2266 uint32_t cons, cp_cons;
2272 rc = is_bnxt_in_error(rxq->bp);
2279 if (offset >= rxq->nb_rx_desc)
2282 cons = RING_CMP(cpr->cp_ring_struct, offset);
2283 cp_cons = cpr->cp_raw_cons;
2284 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2286 if (cons > cp_cons) {
2287 if (CMPL_VALID(rxcmp, cpr->valid))
2288 return RTE_ETH_RX_DESC_DONE;
2290 if (CMPL_VALID(rxcmp, !cpr->valid))
2291 return RTE_ETH_RX_DESC_DONE;
2293 rx_buf = &rxr->rx_buf_ring[cons];
2294 if (rx_buf->mbuf == NULL)
2295 return RTE_ETH_RX_DESC_UNAVAIL;
2298 return RTE_ETH_RX_DESC_AVAIL;
2302 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2304 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2305 struct bnxt_tx_ring_info *txr;
2306 struct bnxt_cp_ring_info *cpr;
2307 struct bnxt_sw_tx_bd *tx_buf;
2308 struct tx_pkt_cmpl *txcmp;
2309 uint32_t cons, cp_cons;
2315 rc = is_bnxt_in_error(txq->bp);
2322 if (offset >= txq->nb_tx_desc)
2325 cons = RING_CMP(cpr->cp_ring_struct, offset);
2326 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2327 cp_cons = cpr->cp_raw_cons;
2329 if (cons > cp_cons) {
2330 if (CMPL_VALID(txcmp, cpr->valid))
2331 return RTE_ETH_TX_DESC_UNAVAIL;
2333 if (CMPL_VALID(txcmp, !cpr->valid))
2334 return RTE_ETH_TX_DESC_UNAVAIL;
2336 tx_buf = &txr->tx_buf_ring[cons];
2337 if (tx_buf->mbuf == NULL)
2338 return RTE_ETH_TX_DESC_DONE;
2340 return RTE_ETH_TX_DESC_FULL;
2343 static struct bnxt_filter_info *
2344 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2345 struct rte_eth_ethertype_filter *efilter,
2346 struct bnxt_vnic_info *vnic0,
2347 struct bnxt_vnic_info *vnic,
2350 struct bnxt_filter_info *mfilter = NULL;
2354 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2355 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2356 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2357 " ethertype filter.", efilter->ether_type);
2361 if (efilter->queue >= bp->rx_nr_rings) {
2362 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2367 vnic0 = &bp->vnic_info[0];
2368 vnic = &bp->vnic_info[efilter->queue];
2370 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2375 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2376 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2377 if ((!memcmp(efilter->mac_addr.addr_bytes,
2378 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2380 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2381 mfilter->ethertype == efilter->ether_type)) {
2387 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2388 if ((!memcmp(efilter->mac_addr.addr_bytes,
2389 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2390 mfilter->ethertype == efilter->ether_type &&
2392 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2406 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2407 enum rte_filter_op filter_op,
2410 struct bnxt *bp = dev->data->dev_private;
2411 struct rte_eth_ethertype_filter *efilter =
2412 (struct rte_eth_ethertype_filter *)arg;
2413 struct bnxt_filter_info *bfilter, *filter1;
2414 struct bnxt_vnic_info *vnic, *vnic0;
2417 if (filter_op == RTE_ETH_FILTER_NOP)
2421 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2426 vnic0 = &bp->vnic_info[0];
2427 vnic = &bp->vnic_info[efilter->queue];
2429 switch (filter_op) {
2430 case RTE_ETH_FILTER_ADD:
2431 bnxt_match_and_validate_ether_filter(bp, efilter,
2436 bfilter = bnxt_get_unused_filter(bp);
2437 if (bfilter == NULL) {
2439 "Not enough resources for a new filter.\n");
2442 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2443 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2444 RTE_ETHER_ADDR_LEN);
2445 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2446 RTE_ETHER_ADDR_LEN);
2447 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2448 bfilter->ethertype = efilter->ether_type;
2449 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2451 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2452 if (filter1 == NULL) {
2457 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2458 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2460 bfilter->dst_id = vnic->fw_vnic_id;
2462 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2464 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2467 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2470 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2472 case RTE_ETH_FILTER_DELETE:
2473 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2475 if (ret == -EEXIST) {
2476 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2478 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2480 bnxt_free_filter(bp, filter1);
2481 } else if (ret == 0) {
2482 PMD_DRV_LOG(ERR, "No matching filter found\n");
2486 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2492 bnxt_free_filter(bp, bfilter);
2498 parse_ntuple_filter(struct bnxt *bp,
2499 struct rte_eth_ntuple_filter *nfilter,
2500 struct bnxt_filter_info *bfilter)
2504 if (nfilter->queue >= bp->rx_nr_rings) {
2505 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2509 switch (nfilter->dst_port_mask) {
2511 bfilter->dst_port_mask = -1;
2512 bfilter->dst_port = nfilter->dst_port;
2513 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2514 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2517 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2521 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2522 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2524 switch (nfilter->proto_mask) {
2526 if (nfilter->proto == 17) /* IPPROTO_UDP */
2527 bfilter->ip_protocol = 17;
2528 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2529 bfilter->ip_protocol = 6;
2532 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2535 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2539 switch (nfilter->dst_ip_mask) {
2541 bfilter->dst_ipaddr_mask[0] = -1;
2542 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2543 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2544 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2547 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2551 switch (nfilter->src_ip_mask) {
2553 bfilter->src_ipaddr_mask[0] = -1;
2554 bfilter->src_ipaddr[0] = nfilter->src_ip;
2555 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2556 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2559 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2563 switch (nfilter->src_port_mask) {
2565 bfilter->src_port_mask = -1;
2566 bfilter->src_port = nfilter->src_port;
2567 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2568 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2571 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2575 bfilter->enables = en;
2579 static struct bnxt_filter_info*
2580 bnxt_match_ntuple_filter(struct bnxt *bp,
2581 struct bnxt_filter_info *bfilter,
2582 struct bnxt_vnic_info **mvnic)
2584 struct bnxt_filter_info *mfilter = NULL;
2587 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2588 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2589 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2590 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2591 bfilter->src_ipaddr_mask[0] ==
2592 mfilter->src_ipaddr_mask[0] &&
2593 bfilter->src_port == mfilter->src_port &&
2594 bfilter->src_port_mask == mfilter->src_port_mask &&
2595 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2596 bfilter->dst_ipaddr_mask[0] ==
2597 mfilter->dst_ipaddr_mask[0] &&
2598 bfilter->dst_port == mfilter->dst_port &&
2599 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2600 bfilter->flags == mfilter->flags &&
2601 bfilter->enables == mfilter->enables) {
2612 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2613 struct rte_eth_ntuple_filter *nfilter,
2614 enum rte_filter_op filter_op)
2616 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2617 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2620 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2621 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2625 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2626 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2630 bfilter = bnxt_get_unused_filter(bp);
2631 if (bfilter == NULL) {
2633 "Not enough resources for a new filter.\n");
2636 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2640 vnic = &bp->vnic_info[nfilter->queue];
2641 vnic0 = &bp->vnic_info[0];
2642 filter1 = STAILQ_FIRST(&vnic0->filter);
2643 if (filter1 == NULL) {
2648 bfilter->dst_id = vnic->fw_vnic_id;
2649 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2651 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2652 bfilter->ethertype = 0x800;
2653 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2655 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2657 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2658 bfilter->dst_id == mfilter->dst_id) {
2659 PMD_DRV_LOG(ERR, "filter exists.\n");
2662 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2663 bfilter->dst_id != mfilter->dst_id) {
2664 mfilter->dst_id = vnic->fw_vnic_id;
2665 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2666 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2667 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2668 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2669 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2672 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2673 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2678 if (filter_op == RTE_ETH_FILTER_ADD) {
2679 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2680 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2683 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2685 if (mfilter == NULL) {
2686 /* This should not happen. But for Coverity! */
2690 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2692 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2693 bnxt_free_filter(bp, mfilter);
2694 mfilter->fw_l2_filter_id = -1;
2695 bnxt_free_filter(bp, bfilter);
2696 bfilter->fw_l2_filter_id = -1;
2701 bfilter->fw_l2_filter_id = -1;
2702 bnxt_free_filter(bp, bfilter);
2707 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2708 enum rte_filter_op filter_op,
2711 struct bnxt *bp = dev->data->dev_private;
2714 if (filter_op == RTE_ETH_FILTER_NOP)
2718 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2723 switch (filter_op) {
2724 case RTE_ETH_FILTER_ADD:
2725 ret = bnxt_cfg_ntuple_filter(bp,
2726 (struct rte_eth_ntuple_filter *)arg,
2729 case RTE_ETH_FILTER_DELETE:
2730 ret = bnxt_cfg_ntuple_filter(bp,
2731 (struct rte_eth_ntuple_filter *)arg,
2735 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2743 bnxt_parse_fdir_filter(struct bnxt *bp,
2744 struct rte_eth_fdir_filter *fdir,
2745 struct bnxt_filter_info *filter)
2747 enum rte_fdir_mode fdir_mode =
2748 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2749 struct bnxt_vnic_info *vnic0, *vnic;
2750 struct bnxt_filter_info *filter1;
2754 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2757 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2758 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2760 switch (fdir->input.flow_type) {
2761 case RTE_ETH_FLOW_IPV4:
2762 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2764 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2765 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2766 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2767 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2768 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2769 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2770 filter->ip_addr_type =
2771 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2772 filter->src_ipaddr_mask[0] = 0xffffffff;
2773 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2774 filter->dst_ipaddr_mask[0] = 0xffffffff;
2775 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2776 filter->ethertype = 0x800;
2777 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2779 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2780 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2781 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2782 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2783 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2784 filter->dst_port_mask = 0xffff;
2785 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2786 filter->src_port_mask = 0xffff;
2787 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2788 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2789 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2790 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2791 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2792 filter->ip_protocol = 6;
2793 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2794 filter->ip_addr_type =
2795 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2796 filter->src_ipaddr_mask[0] = 0xffffffff;
2797 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2798 filter->dst_ipaddr_mask[0] = 0xffffffff;
2799 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2800 filter->ethertype = 0x800;
2801 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2803 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2804 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2805 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2806 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2807 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2808 filter->dst_port_mask = 0xffff;
2809 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2810 filter->src_port_mask = 0xffff;
2811 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2812 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2813 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2814 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2815 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2816 filter->ip_protocol = 17;
2817 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2818 filter->ip_addr_type =
2819 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2820 filter->src_ipaddr_mask[0] = 0xffffffff;
2821 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2822 filter->dst_ipaddr_mask[0] = 0xffffffff;
2823 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2824 filter->ethertype = 0x800;
2825 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2827 case RTE_ETH_FLOW_IPV6:
2828 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2830 filter->ip_addr_type =
2831 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2832 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2833 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2834 rte_memcpy(filter->src_ipaddr,
2835 fdir->input.flow.ipv6_flow.src_ip, 16);
2836 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2837 rte_memcpy(filter->dst_ipaddr,
2838 fdir->input.flow.ipv6_flow.dst_ip, 16);
2839 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2840 memset(filter->dst_ipaddr_mask, 0xff, 16);
2841 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2842 memset(filter->src_ipaddr_mask, 0xff, 16);
2843 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2844 filter->ethertype = 0x86dd;
2845 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2847 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2848 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2849 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2850 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2851 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2852 filter->dst_port_mask = 0xffff;
2853 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2854 filter->src_port_mask = 0xffff;
2855 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2856 filter->ip_addr_type =
2857 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2858 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2859 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2860 rte_memcpy(filter->src_ipaddr,
2861 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2862 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2863 rte_memcpy(filter->dst_ipaddr,
2864 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2865 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2866 memset(filter->dst_ipaddr_mask, 0xff, 16);
2867 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2868 memset(filter->src_ipaddr_mask, 0xff, 16);
2869 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2870 filter->ethertype = 0x86dd;
2871 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2873 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2874 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2875 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2876 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2877 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2878 filter->dst_port_mask = 0xffff;
2879 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2880 filter->src_port_mask = 0xffff;
2881 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2882 filter->ip_addr_type =
2883 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2884 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2885 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2886 rte_memcpy(filter->src_ipaddr,
2887 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2888 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2889 rte_memcpy(filter->dst_ipaddr,
2890 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2891 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2892 memset(filter->dst_ipaddr_mask, 0xff, 16);
2893 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2894 memset(filter->src_ipaddr_mask, 0xff, 16);
2895 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2896 filter->ethertype = 0x86dd;
2897 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2899 case RTE_ETH_FLOW_L2_PAYLOAD:
2900 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2901 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2903 case RTE_ETH_FLOW_VXLAN:
2904 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2906 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2907 filter->tunnel_type =
2908 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2909 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2911 case RTE_ETH_FLOW_NVGRE:
2912 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2914 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2915 filter->tunnel_type =
2916 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2917 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2919 case RTE_ETH_FLOW_UNKNOWN:
2920 case RTE_ETH_FLOW_RAW:
2921 case RTE_ETH_FLOW_FRAG_IPV4:
2922 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2923 case RTE_ETH_FLOW_FRAG_IPV6:
2924 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2925 case RTE_ETH_FLOW_IPV6_EX:
2926 case RTE_ETH_FLOW_IPV6_TCP_EX:
2927 case RTE_ETH_FLOW_IPV6_UDP_EX:
2928 case RTE_ETH_FLOW_GENEVE:
2934 vnic0 = &bp->vnic_info[0];
2935 vnic = &bp->vnic_info[fdir->action.rx_queue];
2937 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2941 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2942 rte_memcpy(filter->dst_macaddr,
2943 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2944 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2947 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2948 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2949 filter1 = STAILQ_FIRST(&vnic0->filter);
2950 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2952 filter->dst_id = vnic->fw_vnic_id;
2953 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2954 if (filter->dst_macaddr[i] == 0x00)
2955 filter1 = STAILQ_FIRST(&vnic0->filter);
2957 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2960 if (filter1 == NULL)
2963 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2964 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2966 filter->enables = en;
2971 static struct bnxt_filter_info *
2972 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2973 struct bnxt_vnic_info **mvnic)
2975 struct bnxt_filter_info *mf = NULL;
2978 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2979 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2981 STAILQ_FOREACH(mf, &vnic->filter, next) {
2982 if (mf->filter_type == nf->filter_type &&
2983 mf->flags == nf->flags &&
2984 mf->src_port == nf->src_port &&
2985 mf->src_port_mask == nf->src_port_mask &&
2986 mf->dst_port == nf->dst_port &&
2987 mf->dst_port_mask == nf->dst_port_mask &&
2988 mf->ip_protocol == nf->ip_protocol &&
2989 mf->ip_addr_type == nf->ip_addr_type &&
2990 mf->ethertype == nf->ethertype &&
2991 mf->vni == nf->vni &&
2992 mf->tunnel_type == nf->tunnel_type &&
2993 mf->l2_ovlan == nf->l2_ovlan &&
2994 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2995 mf->l2_ivlan == nf->l2_ivlan &&
2996 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2997 !memcmp(mf->l2_addr, nf->l2_addr,
2998 RTE_ETHER_ADDR_LEN) &&
2999 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3000 RTE_ETHER_ADDR_LEN) &&
3001 !memcmp(mf->src_macaddr, nf->src_macaddr,
3002 RTE_ETHER_ADDR_LEN) &&
3003 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3004 RTE_ETHER_ADDR_LEN) &&
3005 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3006 sizeof(nf->src_ipaddr)) &&
3007 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3008 sizeof(nf->src_ipaddr_mask)) &&
3009 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3010 sizeof(nf->dst_ipaddr)) &&
3011 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3012 sizeof(nf->dst_ipaddr_mask))) {
3023 bnxt_fdir_filter(struct rte_eth_dev *dev,
3024 enum rte_filter_op filter_op,
3027 struct bnxt *bp = dev->data->dev_private;
3028 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3029 struct bnxt_filter_info *filter, *match;
3030 struct bnxt_vnic_info *vnic, *mvnic;
3033 if (filter_op == RTE_ETH_FILTER_NOP)
3036 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3039 switch (filter_op) {
3040 case RTE_ETH_FILTER_ADD:
3041 case RTE_ETH_FILTER_DELETE:
3043 filter = bnxt_get_unused_filter(bp);
3044 if (filter == NULL) {
3046 "Not enough resources for a new flow.\n");
3050 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3053 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3055 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3056 vnic = &bp->vnic_info[0];
3058 vnic = &bp->vnic_info[fdir->action.rx_queue];
3060 match = bnxt_match_fdir(bp, filter, &mvnic);
3061 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3062 if (match->dst_id == vnic->fw_vnic_id) {
3063 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3067 match->dst_id = vnic->fw_vnic_id;
3068 ret = bnxt_hwrm_set_ntuple_filter(bp,
3071 STAILQ_REMOVE(&mvnic->filter, match,
3072 bnxt_filter_info, next);
3073 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3075 "Filter with matching pattern exist\n");
3077 "Updated it to new destination q\n");
3081 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3082 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3087 if (filter_op == RTE_ETH_FILTER_ADD) {
3088 ret = bnxt_hwrm_set_ntuple_filter(bp,
3093 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3095 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3096 STAILQ_REMOVE(&vnic->filter, match,
3097 bnxt_filter_info, next);
3098 bnxt_free_filter(bp, match);
3099 filter->fw_l2_filter_id = -1;
3100 bnxt_free_filter(bp, filter);
3103 case RTE_ETH_FILTER_FLUSH:
3104 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3105 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3107 STAILQ_FOREACH(filter, &vnic->filter, next) {
3108 if (filter->filter_type ==
3109 HWRM_CFA_NTUPLE_FILTER) {
3111 bnxt_hwrm_clear_ntuple_filter(bp,
3113 STAILQ_REMOVE(&vnic->filter, filter,
3114 bnxt_filter_info, next);
3119 case RTE_ETH_FILTER_UPDATE:
3120 case RTE_ETH_FILTER_STATS:
3121 case RTE_ETH_FILTER_INFO:
3122 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3125 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3132 filter->fw_l2_filter_id = -1;
3133 bnxt_free_filter(bp, filter);
3138 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3139 enum rte_filter_type filter_type,
3140 enum rte_filter_op filter_op, void *arg)
3144 ret = is_bnxt_in_error(dev->data->dev_private);
3148 switch (filter_type) {
3149 case RTE_ETH_FILTER_TUNNEL:
3151 "filter type: %d: To be implemented\n", filter_type);
3153 case RTE_ETH_FILTER_FDIR:
3154 ret = bnxt_fdir_filter(dev, filter_op, arg);
3156 case RTE_ETH_FILTER_NTUPLE:
3157 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3159 case RTE_ETH_FILTER_ETHERTYPE:
3160 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3162 case RTE_ETH_FILTER_GENERIC:
3163 if (filter_op != RTE_ETH_FILTER_GET)
3165 *(const void **)arg = &bnxt_flow_ops;
3169 "Filter type (%d) not supported", filter_type);
3176 static const uint32_t *
3177 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3179 static const uint32_t ptypes[] = {
3180 RTE_PTYPE_L2_ETHER_VLAN,
3181 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3182 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3186 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3187 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3188 RTE_PTYPE_INNER_L4_ICMP,
3189 RTE_PTYPE_INNER_L4_TCP,
3190 RTE_PTYPE_INNER_L4_UDP,
3194 if (!dev->rx_pkt_burst)
3200 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3203 uint32_t reg_base = *reg_arr & 0xfffff000;
3207 for (i = 0; i < count; i++) {
3208 if ((reg_arr[i] & 0xfffff000) != reg_base)
3211 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3212 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3216 static int bnxt_map_ptp_regs(struct bnxt *bp)
3218 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3222 reg_arr = ptp->rx_regs;
3223 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3227 reg_arr = ptp->tx_regs;
3228 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3232 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3233 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3235 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3236 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3241 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3243 rte_write32(0, (uint8_t *)bp->bar0 +
3244 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3245 rte_write32(0, (uint8_t *)bp->bar0 +
3246 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3249 static uint64_t bnxt_cc_read(struct bnxt *bp)
3253 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3254 BNXT_GRCPF_REG_SYNC_TIME));
3255 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3256 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3260 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3262 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3265 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3266 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3267 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3270 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3271 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3272 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3273 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3274 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3275 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3280 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3282 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3283 struct bnxt_pf_info *pf = &bp->pf;
3290 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3291 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3292 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3295 port_id = pf->port_id;
3296 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3297 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3299 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3300 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3301 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3302 /* bnxt_clr_rx_ts(bp); TBD */
3306 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3307 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3308 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3309 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3315 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3318 struct bnxt *bp = dev->data->dev_private;
3319 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3324 ns = rte_timespec_to_ns(ts);
3325 /* Set the timecounters to a new value. */
3332 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3334 struct bnxt *bp = dev->data->dev_private;
3335 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3336 uint64_t ns, systime_cycles = 0;
3342 if (BNXT_CHIP_THOR(bp))
3343 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3346 systime_cycles = bnxt_cc_read(bp);
3348 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3349 *ts = rte_ns_to_timespec(ns);
3354 bnxt_timesync_enable(struct rte_eth_dev *dev)
3356 struct bnxt *bp = dev->data->dev_private;
3357 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3365 ptp->tx_tstamp_en = 1;
3366 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3368 rc = bnxt_hwrm_ptp_cfg(bp);
3372 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3373 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3374 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3376 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3377 ptp->tc.cc_shift = shift;
3378 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3380 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3381 ptp->rx_tstamp_tc.cc_shift = shift;
3382 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3384 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3385 ptp->tx_tstamp_tc.cc_shift = shift;
3386 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3388 if (!BNXT_CHIP_THOR(bp))
3389 bnxt_map_ptp_regs(bp);
3395 bnxt_timesync_disable(struct rte_eth_dev *dev)
3397 struct bnxt *bp = dev->data->dev_private;
3398 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3404 ptp->tx_tstamp_en = 0;
3407 bnxt_hwrm_ptp_cfg(bp);
3409 if (!BNXT_CHIP_THOR(bp))
3410 bnxt_unmap_ptp_regs(bp);
3416 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3417 struct timespec *timestamp,
3418 uint32_t flags __rte_unused)
3420 struct bnxt *bp = dev->data->dev_private;
3421 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3422 uint64_t rx_tstamp_cycles = 0;
3428 if (BNXT_CHIP_THOR(bp))
3429 rx_tstamp_cycles = ptp->rx_timestamp;
3431 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3433 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3434 *timestamp = rte_ns_to_timespec(ns);
3439 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3440 struct timespec *timestamp)
3442 struct bnxt *bp = dev->data->dev_private;
3443 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3444 uint64_t tx_tstamp_cycles = 0;
3451 if (BNXT_CHIP_THOR(bp))
3452 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3455 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3457 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3458 *timestamp = rte_ns_to_timespec(ns);
3464 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3466 struct bnxt *bp = dev->data->dev_private;
3467 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3472 ptp->tc.nsec += delta;
3478 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3480 struct bnxt *bp = dev->data->dev_private;
3482 uint32_t dir_entries;
3483 uint32_t entry_length;
3485 rc = is_bnxt_in_error(bp);
3489 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3490 bp->pdev->addr.domain, bp->pdev->addr.bus,
3491 bp->pdev->addr.devid, bp->pdev->addr.function);
3493 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3497 return dir_entries * entry_length;
3501 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3502 struct rte_dev_eeprom_info *in_eeprom)
3504 struct bnxt *bp = dev->data->dev_private;
3509 rc = is_bnxt_in_error(bp);
3513 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3514 "len = %d\n", bp->pdev->addr.domain,
3515 bp->pdev->addr.bus, bp->pdev->addr.devid,
3516 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3518 if (in_eeprom->offset == 0) /* special offset value to get directory */
3519 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3522 index = in_eeprom->offset >> 24;
3523 offset = in_eeprom->offset & 0xffffff;
3526 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3527 in_eeprom->length, in_eeprom->data);
3532 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3535 case BNX_DIR_TYPE_CHIMP_PATCH:
3536 case BNX_DIR_TYPE_BOOTCODE:
3537 case BNX_DIR_TYPE_BOOTCODE_2:
3538 case BNX_DIR_TYPE_APE_FW:
3539 case BNX_DIR_TYPE_APE_PATCH:
3540 case BNX_DIR_TYPE_KONG_FW:
3541 case BNX_DIR_TYPE_KONG_PATCH:
3542 case BNX_DIR_TYPE_BONO_FW:
3543 case BNX_DIR_TYPE_BONO_PATCH:
3551 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3554 case BNX_DIR_TYPE_AVS:
3555 case BNX_DIR_TYPE_EXP_ROM_MBA:
3556 case BNX_DIR_TYPE_PCIE:
3557 case BNX_DIR_TYPE_TSCF_UCODE:
3558 case BNX_DIR_TYPE_EXT_PHY:
3559 case BNX_DIR_TYPE_CCM:
3560 case BNX_DIR_TYPE_ISCSI_BOOT:
3561 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3562 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3570 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3572 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3573 bnxt_dir_type_is_other_exec_format(dir_type);
3577 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3578 struct rte_dev_eeprom_info *in_eeprom)
3580 struct bnxt *bp = dev->data->dev_private;
3581 uint8_t index, dir_op;
3582 uint16_t type, ext, ordinal, attr;
3585 rc = is_bnxt_in_error(bp);
3589 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3590 "len = %d\n", bp->pdev->addr.domain,
3591 bp->pdev->addr.bus, bp->pdev->addr.devid,
3592 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3595 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3599 type = in_eeprom->magic >> 16;
3601 if (type == 0xffff) { /* special value for directory operations */
3602 index = in_eeprom->magic & 0xff;
3603 dir_op = in_eeprom->magic >> 8;
3607 case 0x0e: /* erase */
3608 if (in_eeprom->offset != ~in_eeprom->magic)
3610 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3616 /* Create or re-write an NVM item: */
3617 if (bnxt_dir_type_is_executable(type) == true)
3619 ext = in_eeprom->magic & 0xffff;
3620 ordinal = in_eeprom->offset >> 16;
3621 attr = in_eeprom->offset & 0xffff;
3623 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3624 in_eeprom->data, in_eeprom->length);
3631 static const struct eth_dev_ops bnxt_dev_ops = {
3632 .dev_infos_get = bnxt_dev_info_get_op,
3633 .dev_close = bnxt_dev_close_op,
3634 .dev_configure = bnxt_dev_configure_op,
3635 .dev_start = bnxt_dev_start_op,
3636 .dev_stop = bnxt_dev_stop_op,
3637 .dev_set_link_up = bnxt_dev_set_link_up_op,
3638 .dev_set_link_down = bnxt_dev_set_link_down_op,
3639 .stats_get = bnxt_stats_get_op,
3640 .stats_reset = bnxt_stats_reset_op,
3641 .rx_queue_setup = bnxt_rx_queue_setup_op,
3642 .rx_queue_release = bnxt_rx_queue_release_op,
3643 .tx_queue_setup = bnxt_tx_queue_setup_op,
3644 .tx_queue_release = bnxt_tx_queue_release_op,
3645 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3646 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3647 .reta_update = bnxt_reta_update_op,
3648 .reta_query = bnxt_reta_query_op,
3649 .rss_hash_update = bnxt_rss_hash_update_op,
3650 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3651 .link_update = bnxt_link_update_op,
3652 .promiscuous_enable = bnxt_promiscuous_enable_op,
3653 .promiscuous_disable = bnxt_promiscuous_disable_op,
3654 .allmulticast_enable = bnxt_allmulticast_enable_op,
3655 .allmulticast_disable = bnxt_allmulticast_disable_op,
3656 .mac_addr_add = bnxt_mac_addr_add_op,
3657 .mac_addr_remove = bnxt_mac_addr_remove_op,
3658 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3659 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3660 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3661 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3662 .vlan_filter_set = bnxt_vlan_filter_set_op,
3663 .vlan_offload_set = bnxt_vlan_offload_set_op,
3664 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3665 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3666 .mtu_set = bnxt_mtu_set_op,
3667 .mac_addr_set = bnxt_set_default_mac_addr_op,
3668 .xstats_get = bnxt_dev_xstats_get_op,
3669 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3670 .xstats_reset = bnxt_dev_xstats_reset_op,
3671 .fw_version_get = bnxt_fw_version_get,
3672 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3673 .rxq_info_get = bnxt_rxq_info_get_op,
3674 .txq_info_get = bnxt_txq_info_get_op,
3675 .dev_led_on = bnxt_dev_led_on_op,
3676 .dev_led_off = bnxt_dev_led_off_op,
3677 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3678 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3679 .rx_queue_count = bnxt_rx_queue_count_op,
3680 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3681 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3682 .rx_queue_start = bnxt_rx_queue_start,
3683 .rx_queue_stop = bnxt_rx_queue_stop,
3684 .tx_queue_start = bnxt_tx_queue_start,
3685 .tx_queue_stop = bnxt_tx_queue_stop,
3686 .filter_ctrl = bnxt_filter_ctrl_op,
3687 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3688 .get_eeprom_length = bnxt_get_eeprom_length_op,
3689 .get_eeprom = bnxt_get_eeprom_op,
3690 .set_eeprom = bnxt_set_eeprom_op,
3691 .timesync_enable = bnxt_timesync_enable,
3692 .timesync_disable = bnxt_timesync_disable,
3693 .timesync_read_time = bnxt_timesync_read_time,
3694 .timesync_write_time = bnxt_timesync_write_time,
3695 .timesync_adjust_time = bnxt_timesync_adjust_time,
3696 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3697 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3700 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3704 /* Only pre-map the reset GRC registers using window 3 */
3705 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3706 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3708 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3713 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3715 struct bnxt_error_recovery_info *info = bp->recovery_info;
3716 uint32_t reg_base = 0xffffffff;
3719 /* Only pre-map the monitoring GRC registers using window 2 */
3720 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3721 uint32_t reg = info->status_regs[i];
3723 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3726 if (reg_base == 0xffffffff)
3727 reg_base = reg & 0xfffff000;
3728 if ((reg & 0xfffff000) != reg_base)
3731 /* Use mask 0xffc as the Lower 2 bits indicates
3732 * address space location
3734 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3738 if (reg_base == 0xffffffff)
3741 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3742 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3747 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3749 struct bnxt_error_recovery_info *info = bp->recovery_info;
3750 uint32_t delay = info->delay_after_reset[index];
3751 uint32_t val = info->reset_reg_val[index];
3752 uint32_t reg = info->reset_reg[index];
3753 uint32_t type, offset;
3755 type = BNXT_FW_STATUS_REG_TYPE(reg);
3756 offset = BNXT_FW_STATUS_REG_OFF(reg);
3759 case BNXT_FW_STATUS_REG_TYPE_CFG:
3760 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3762 case BNXT_FW_STATUS_REG_TYPE_GRC:
3763 offset = bnxt_map_reset_regs(bp, offset);
3764 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3766 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3767 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3770 /* wait on a specific interval of time until core reset is complete */
3772 rte_delay_ms(delay);
3775 static void bnxt_dev_cleanup(struct bnxt *bp)
3777 bnxt_set_hwrm_link_config(bp, false);
3778 bp->link_info.link_up = 0;
3779 if (bp->dev_stopped == 0)
3780 bnxt_dev_stop_op(bp->eth_dev);
3782 bnxt_uninit_resources(bp, true);
3785 static int bnxt_restore_filters(struct bnxt *bp)
3787 struct rte_eth_dev *dev = bp->eth_dev;
3790 if (dev->data->all_multicast)
3791 ret = bnxt_allmulticast_enable_op(dev);
3792 if (dev->data->promiscuous)
3793 ret = bnxt_promiscuous_enable_op(dev);
3795 /* TODO restore other filters as well */
3799 static void bnxt_dev_recover(void *arg)
3801 struct bnxt *bp = arg;
3802 int timeout = bp->fw_reset_max_msecs;
3805 /* Clear Error flag so that device re-init should happen */
3806 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3809 rc = bnxt_hwrm_ver_get(bp);
3812 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3813 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3814 } while (rc && timeout);
3817 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3821 rc = bnxt_init_resources(bp, true);
3824 "Failed to initialize resources after reset\n");
3827 /* clear reset flag as the device is initialized now */
3828 bp->flags &= ~BNXT_FLAG_FW_RESET;
3830 rc = bnxt_dev_start_op(bp->eth_dev);
3832 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3836 rc = bnxt_restore_filters(bp);
3840 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3843 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3844 bnxt_uninit_resources(bp, false);
3845 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3848 void bnxt_dev_reset_and_resume(void *arg)
3850 struct bnxt *bp = arg;
3853 bnxt_dev_cleanup(bp);
3855 bnxt_wait_for_device_shutdown(bp);
3857 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3858 bnxt_dev_recover, (void *)bp);
3860 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3863 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3865 struct bnxt_error_recovery_info *info = bp->recovery_info;
3866 uint32_t reg = info->status_regs[index];
3867 uint32_t type, offset, val = 0;
3869 type = BNXT_FW_STATUS_REG_TYPE(reg);
3870 offset = BNXT_FW_STATUS_REG_OFF(reg);
3873 case BNXT_FW_STATUS_REG_TYPE_CFG:
3874 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3876 case BNXT_FW_STATUS_REG_TYPE_GRC:
3877 offset = info->mapped_status_regs[index];
3879 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3880 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3888 static int bnxt_fw_reset_all(struct bnxt *bp)
3890 struct bnxt_error_recovery_info *info = bp->recovery_info;
3894 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3895 /* Reset through master function driver */
3896 for (i = 0; i < info->reg_array_cnt; i++)
3897 bnxt_write_fw_reset_reg(bp, i);
3898 /* Wait for time specified by FW after triggering reset */
3899 rte_delay_ms(info->master_func_wait_period_after_reset);
3900 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3901 /* Reset with the help of Kong processor */
3902 rc = bnxt_hwrm_fw_reset(bp);
3904 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3910 static void bnxt_fw_reset_cb(void *arg)
3912 struct bnxt *bp = arg;
3913 struct bnxt_error_recovery_info *info = bp->recovery_info;
3916 /* Only Master function can do FW reset */
3917 if (bnxt_is_master_func(bp) &&
3918 bnxt_is_recovery_enabled(bp)) {
3919 rc = bnxt_fw_reset_all(bp);
3921 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3926 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3927 * EXCEPTION_FATAL_ASYNC event to all the functions
3928 * (including MASTER FUNC). After receiving this Async, all the active
3929 * drivers should treat this case as FW initiated recovery
3931 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3932 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3933 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3935 /* To recover from error */
3936 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3941 /* Driver should poll FW heartbeat, reset_counter with the frequency
3942 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3943 * When the driver detects heartbeat stop or change in reset_counter,
3944 * it has to trigger a reset to recover from the error condition.
3945 * A “master PF” is the function who will have the privilege to
3946 * initiate the chimp reset. The master PF will be elected by the
3947 * firmware and will be notified through async message.
3949 static void bnxt_check_fw_health(void *arg)
3951 struct bnxt *bp = arg;
3952 struct bnxt_error_recovery_info *info = bp->recovery_info;
3953 uint32_t val = 0, wait_msec;
3955 if (!info || !bnxt_is_recovery_enabled(bp) ||
3956 is_bnxt_in_error(bp))
3959 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3960 if (val == info->last_heart_beat)
3963 info->last_heart_beat = val;
3965 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3966 if (val != info->last_reset_counter)
3969 info->last_reset_counter = val;
3971 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3972 bnxt_check_fw_health, (void *)bp);
3976 /* Stop DMA to/from device */
3977 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3978 bp->flags |= BNXT_FLAG_FW_RESET;
3980 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3982 if (bnxt_is_master_func(bp))
3983 wait_msec = info->master_func_wait_period;
3985 wait_msec = info->normal_func_wait_period;
3987 rte_eal_alarm_set(US_PER_MS * wait_msec,
3988 bnxt_fw_reset_cb, (void *)bp);
3991 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3993 uint32_t polling_freq;
3995 if (!bnxt_is_recovery_enabled(bp))
3998 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4001 polling_freq = bp->recovery_info->driver_polling_freq;
4003 rte_eal_alarm_set(US_PER_MS * polling_freq,
4004 bnxt_check_fw_health, (void *)bp);
4005 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4008 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4010 if (!bnxt_is_recovery_enabled(bp))
4013 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4014 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4017 static bool bnxt_vf_pciid(uint16_t id)
4019 if (id == BROADCOM_DEV_ID_57304_VF ||
4020 id == BROADCOM_DEV_ID_57406_VF ||
4021 id == BROADCOM_DEV_ID_5731X_VF ||
4022 id == BROADCOM_DEV_ID_5741X_VF ||
4023 id == BROADCOM_DEV_ID_57414_VF ||
4024 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4025 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
4026 id == BROADCOM_DEV_ID_58802_VF ||
4027 id == BROADCOM_DEV_ID_57500_VF1 ||
4028 id == BROADCOM_DEV_ID_57500_VF2)
4033 static bool bnxt_thor_device(uint16_t id)
4035 if (id == BROADCOM_DEV_ID_57508 ||
4036 id == BROADCOM_DEV_ID_57504 ||
4037 id == BROADCOM_DEV_ID_57502 ||
4038 id == BROADCOM_DEV_ID_57508_MF1 ||
4039 id == BROADCOM_DEV_ID_57504_MF1 ||
4040 id == BROADCOM_DEV_ID_57502_MF1 ||
4041 id == BROADCOM_DEV_ID_57508_MF2 ||
4042 id == BROADCOM_DEV_ID_57504_MF2 ||
4043 id == BROADCOM_DEV_ID_57502_MF2 ||
4044 id == BROADCOM_DEV_ID_57500_VF1 ||
4045 id == BROADCOM_DEV_ID_57500_VF2)
4051 bool bnxt_stratus_device(struct bnxt *bp)
4053 uint16_t id = bp->pdev->id.device_id;
4055 if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
4056 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4057 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
4062 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4064 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4065 struct bnxt *bp = eth_dev->data->dev_private;
4067 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4068 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4069 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4070 if (!bp->bar0 || !bp->doorbell_base) {
4071 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4075 bp->eth_dev = eth_dev;
4081 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
4082 struct bnxt_ctx_pg_info *ctx_pg,
4087 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4088 const struct rte_memzone *mz = NULL;
4089 char mz_name[RTE_MEMZONE_NAMESIZE];
4090 rte_iova_t mz_phys_addr;
4091 uint64_t valid_bits = 0;
4098 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4100 rmem->page_size = BNXT_PAGE_SIZE;
4101 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4102 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4103 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4105 valid_bits = PTU_PTE_VALID;
4107 if (rmem->nr_pages > 1) {
4108 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4109 "bnxt_ctx_pg_tbl%s_%x_%d",
4110 suffix, idx, bp->eth_dev->data->port_id);
4111 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4112 mz = rte_memzone_lookup(mz_name);
4114 mz = rte_memzone_reserve_aligned(mz_name,
4118 RTE_MEMZONE_SIZE_HINT_ONLY |
4119 RTE_MEMZONE_IOVA_CONTIG,
4125 memset(mz->addr, 0, mz->len);
4126 mz_phys_addr = mz->iova;
4127 if ((unsigned long)mz->addr == mz_phys_addr) {
4129 "physical address same as virtual\n");
4130 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4131 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4132 if (mz_phys_addr == RTE_BAD_IOVA) {
4134 "unable to map addr to phys memory\n");
4138 rte_mem_lock_page(((char *)mz->addr));
4140 rmem->pg_tbl = mz->addr;
4141 rmem->pg_tbl_map = mz_phys_addr;
4142 rmem->pg_tbl_mz = mz;
4145 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4146 suffix, idx, bp->eth_dev->data->port_id);
4147 mz = rte_memzone_lookup(mz_name);
4149 mz = rte_memzone_reserve_aligned(mz_name,
4153 RTE_MEMZONE_SIZE_HINT_ONLY |
4154 RTE_MEMZONE_IOVA_CONTIG,
4160 memset(mz->addr, 0, mz->len);
4161 mz_phys_addr = mz->iova;
4162 if ((unsigned long)mz->addr == mz_phys_addr) {
4164 "Memzone physical address same as virtual.\n");
4165 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4166 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4167 rte_mem_lock_page(((char *)mz->addr) + sz);
4168 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4169 if (mz_phys_addr == RTE_BAD_IOVA) {
4171 "unable to map addr to phys memory\n");
4176 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4177 rte_mem_lock_page(((char *)mz->addr) + sz);
4178 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4179 rmem->dma_arr[i] = mz_phys_addr + sz;
4181 if (rmem->nr_pages > 1) {
4182 if (i == rmem->nr_pages - 2 &&
4183 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4184 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4185 else if (i == rmem->nr_pages - 1 &&
4186 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4187 valid_bits |= PTU_PTE_LAST;
4189 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4195 if (rmem->vmem_size)
4196 rmem->vmem = (void **)mz->addr;
4197 rmem->dma_arr[0] = mz_phys_addr;
4201 static void bnxt_free_ctx_mem(struct bnxt *bp)
4205 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4208 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4209 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4210 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4211 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4212 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4213 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4214 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4215 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4216 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4217 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4218 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4220 for (i = 0; i < BNXT_MAX_Q; i++) {
4221 if (bp->ctx->tqm_mem[i])
4222 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4229 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4231 #define min_t(type, x, y) ({ \
4232 type __min1 = (x); \
4233 type __min2 = (y); \
4234 __min1 < __min2 ? __min1 : __min2; })
4236 #define max_t(type, x, y) ({ \
4237 type __max1 = (x); \
4238 type __max2 = (y); \
4239 __max1 > __max2 ? __max1 : __max2; })
4241 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4243 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4245 struct bnxt_ctx_pg_info *ctx_pg;
4246 struct bnxt_ctx_mem_info *ctx;
4247 uint32_t mem_size, ena, entries;
4250 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4252 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4256 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4259 ctx_pg = &ctx->qp_mem;
4260 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4261 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4262 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4266 ctx_pg = &ctx->srq_mem;
4267 ctx_pg->entries = ctx->srq_max_l2_entries;
4268 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4269 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4273 ctx_pg = &ctx->cq_mem;
4274 ctx_pg->entries = ctx->cq_max_l2_entries;
4275 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4276 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4280 ctx_pg = &ctx->vnic_mem;
4281 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4282 ctx->vnic_max_ring_table_entries;
4283 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4284 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4288 ctx_pg = &ctx->stat_mem;
4289 ctx_pg->entries = ctx->stat_max_entries;
4290 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4291 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4295 entries = ctx->qp_max_l2_entries +
4296 ctx->vnic_max_vnic_entries +
4297 ctx->tqm_min_entries_per_ring;
4298 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4299 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4300 ctx->tqm_max_entries_per_ring);
4301 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4302 ctx_pg = ctx->tqm_mem[i];
4303 /* use min tqm entries for now. */
4304 ctx_pg->entries = entries;
4305 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4306 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4309 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4312 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4313 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4316 "Failed to configure context mem: rc = %d\n", rc);
4318 ctx->flags |= BNXT_CTX_FLAG_INITED;
4323 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4325 struct rte_pci_device *pci_dev = bp->pdev;
4326 char mz_name[RTE_MEMZONE_NAMESIZE];
4327 const struct rte_memzone *mz = NULL;
4328 uint32_t total_alloc_len;
4329 rte_iova_t mz_phys_addr;
4331 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4334 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4335 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4336 pci_dev->addr.bus, pci_dev->addr.devid,
4337 pci_dev->addr.function, "rx_port_stats");
4338 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4339 mz = rte_memzone_lookup(mz_name);
4341 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4342 sizeof(struct rx_port_stats_ext) + 512);
4344 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4347 RTE_MEMZONE_SIZE_HINT_ONLY |
4348 RTE_MEMZONE_IOVA_CONTIG);
4352 memset(mz->addr, 0, mz->len);
4353 mz_phys_addr = mz->iova;
4354 if ((unsigned long)mz->addr == mz_phys_addr) {
4356 "Memzone physical address same as virtual.\n");
4358 "Using rte_mem_virt2iova()\n");
4359 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4360 if (mz_phys_addr == RTE_BAD_IOVA) {
4362 "Can't map address to physical memory\n");
4367 bp->rx_mem_zone = (const void *)mz;
4368 bp->hw_rx_port_stats = mz->addr;
4369 bp->hw_rx_port_stats_map = mz_phys_addr;
4371 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4372 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4373 pci_dev->addr.bus, pci_dev->addr.devid,
4374 pci_dev->addr.function, "tx_port_stats");
4375 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4376 mz = rte_memzone_lookup(mz_name);
4378 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4379 sizeof(struct tx_port_stats_ext) + 512);
4381 mz = rte_memzone_reserve(mz_name,
4385 RTE_MEMZONE_SIZE_HINT_ONLY |
4386 RTE_MEMZONE_IOVA_CONTIG);
4390 memset(mz->addr, 0, mz->len);
4391 mz_phys_addr = mz->iova;
4392 if ((unsigned long)mz->addr == mz_phys_addr) {
4394 "Memzone physical address same as virtual\n");
4395 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4396 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4397 if (mz_phys_addr == RTE_BAD_IOVA) {
4399 "Can't map address to physical memory\n");
4404 bp->tx_mem_zone = (const void *)mz;
4405 bp->hw_tx_port_stats = mz->addr;
4406 bp->hw_tx_port_stats_map = mz_phys_addr;
4407 bp->flags |= BNXT_FLAG_PORT_STATS;
4409 /* Display extended statistics if FW supports it */
4410 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4411 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4412 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4415 bp->hw_rx_port_stats_ext = (void *)
4416 ((uint8_t *)bp->hw_rx_port_stats +
4417 sizeof(struct rx_port_stats));
4418 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4419 sizeof(struct rx_port_stats);
4420 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4422 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4423 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4424 bp->hw_tx_port_stats_ext = (void *)
4425 ((uint8_t *)bp->hw_tx_port_stats +
4426 sizeof(struct tx_port_stats));
4427 bp->hw_tx_port_stats_ext_map =
4428 bp->hw_tx_port_stats_map +
4429 sizeof(struct tx_port_stats);
4430 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4436 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4438 struct bnxt *bp = eth_dev->data->dev_private;
4441 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4442 RTE_ETHER_ADDR_LEN *
4445 if (eth_dev->data->mac_addrs == NULL) {
4446 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4450 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4454 /* Generate a random MAC address, if none was assigned by PF */
4455 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4456 bnxt_eth_hw_addr_random(bp->mac_addr);
4458 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4459 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4460 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4462 rc = bnxt_hwrm_set_mac(bp);
4464 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4465 RTE_ETHER_ADDR_LEN);
4469 /* Copy the permanent MAC from the FUNC_QCAPS response */
4470 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4471 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4476 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4480 /* MAC is already configured in FW */
4481 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4484 /* Restore the old MAC configured */
4485 rc = bnxt_hwrm_set_mac(bp);
4487 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4492 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4497 #define ALLOW_FUNC(x) \
4499 uint32_t arg = (x); \
4500 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4501 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4504 /* Forward all requests if firmware is new enough */
4505 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4506 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4507 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4508 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4510 PMD_DRV_LOG(WARNING,
4511 "Firmware too old for VF mailbox functionality\n");
4512 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4516 * The following are used for driver cleanup. If we disallow these,
4517 * VF drivers can't clean up cleanly.
4519 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4520 ALLOW_FUNC(HWRM_VNIC_FREE);
4521 ALLOW_FUNC(HWRM_RING_FREE);
4522 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4523 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4524 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4525 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4526 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4527 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4530 static int bnxt_init_fw(struct bnxt *bp)
4535 rc = bnxt_hwrm_ver_get(bp);
4539 rc = bnxt_hwrm_func_reset(bp);
4543 rc = bnxt_hwrm_vnic_qcaps(bp);
4547 rc = bnxt_hwrm_queue_qportcfg(bp);
4551 /* Get the MAX capabilities for this function.
4552 * This function also allocates context memory for TQM rings and
4553 * informs the firmware about this allocated backing store memory.
4555 rc = bnxt_hwrm_func_qcaps(bp);
4559 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4563 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4567 /* Get the adapter error recovery support info */
4568 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4570 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4572 if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4573 mtu != bp->eth_dev->data->mtu)
4574 bp->eth_dev->data->mtu = mtu;
4576 bnxt_hwrm_port_led_qcaps(bp);
4582 bnxt_init_locks(struct bnxt *bp)
4586 err = pthread_mutex_init(&bp->flow_lock, NULL);
4588 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4592 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4594 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4598 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4602 rc = bnxt_init_fw(bp);
4606 if (!reconfig_dev) {
4607 rc = bnxt_setup_mac_addr(bp->eth_dev);
4611 rc = bnxt_restore_dflt_mac(bp);
4616 bnxt_config_vf_req_fwd(bp);
4618 rc = bnxt_hwrm_func_driver_register(bp);
4620 PMD_DRV_LOG(ERR, "Failed to register driver");
4625 if (bp->pdev->max_vfs) {
4626 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4628 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4632 rc = bnxt_hwrm_allocate_pf_only(bp);
4635 "Failed to allocate PF resources");
4641 rc = bnxt_alloc_mem(bp, reconfig_dev);
4645 rc = bnxt_setup_int(bp);
4649 rc = bnxt_request_int(bp);
4653 rc = bnxt_init_locks(bp);
4661 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4663 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4664 static int version_printed;
4668 if (version_printed++ == 0)
4669 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4671 eth_dev->dev_ops = &bnxt_dev_ops;
4672 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4673 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4676 * For secondary processes, we don't initialise any further
4677 * as primary has already done this work.
4679 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4682 rte_eth_copy_pci_info(eth_dev, pci_dev);
4684 bp = eth_dev->data->dev_private;
4686 bp->dev_stopped = 1;
4688 if (bnxt_vf_pciid(pci_dev->id.device_id))
4689 bp->flags |= BNXT_FLAG_VF;
4691 if (bnxt_thor_device(pci_dev->id.device_id))
4692 bp->flags |= BNXT_FLAG_THOR_CHIP;
4694 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4695 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4696 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4697 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4698 bp->flags |= BNXT_FLAG_STINGRAY;
4700 rc = bnxt_init_board(eth_dev);
4703 "Failed to initialize board rc: %x\n", rc);
4707 rc = bnxt_alloc_hwrm_resources(bp);
4710 "Failed to allocate hwrm resource rc: %x\n", rc);
4713 rc = bnxt_init_resources(bp, false);
4717 rc = bnxt_alloc_stats_mem(bp);
4722 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4723 pci_dev->mem_resource[0].phys_addr,
4724 pci_dev->mem_resource[0].addr);
4729 bnxt_dev_uninit(eth_dev);
4734 bnxt_uninit_locks(struct bnxt *bp)
4736 pthread_mutex_destroy(&bp->flow_lock);
4737 pthread_mutex_destroy(&bp->def_cp_lock);
4741 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4746 bnxt_free_mem(bp, reconfig_dev);
4747 bnxt_hwrm_func_buf_unrgtr(bp);
4748 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4749 bp->flags &= ~BNXT_FLAG_REGISTERED;
4750 bnxt_free_ctx_mem(bp);
4751 if (!reconfig_dev) {
4752 bnxt_free_hwrm_resources(bp);
4754 if (bp->recovery_info != NULL) {
4755 rte_free(bp->recovery_info);
4756 bp->recovery_info = NULL;
4760 bnxt_uninit_locks(bp);
4761 rte_free(bp->ptp_cfg);
4767 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4769 struct bnxt *bp = eth_dev->data->dev_private;
4772 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4775 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4777 rc = bnxt_uninit_resources(bp, false);
4779 if (bp->tx_mem_zone) {
4780 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4781 bp->tx_mem_zone = NULL;
4784 if (bp->rx_mem_zone) {
4785 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4786 bp->rx_mem_zone = NULL;
4789 if (bp->dev_stopped == 0)
4790 bnxt_dev_close_op(eth_dev);
4792 rte_free(bp->pf.vf_info);
4793 eth_dev->dev_ops = NULL;
4794 eth_dev->rx_pkt_burst = NULL;
4795 eth_dev->tx_pkt_burst = NULL;
4800 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4801 struct rte_pci_device *pci_dev)
4803 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4807 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4809 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4810 return rte_eth_dev_pci_generic_remove(pci_dev,
4813 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4816 static struct rte_pci_driver bnxt_rte_pmd = {
4817 .id_table = bnxt_pci_id_map,
4818 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4819 .probe = bnxt_pci_probe,
4820 .remove = bnxt_pci_remove,
4824 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4826 if (strcmp(dev->device->driver->name, drv->driver.name))
4832 bool is_bnxt_supported(struct rte_eth_dev *dev)
4834 return is_device_supported(dev, &bnxt_rte_pmd);
4837 RTE_INIT(bnxt_init_log)
4839 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4840 if (bnxt_logtype_driver >= 0)
4841 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4844 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4845 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4846 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");