1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
18 #include "bnxt_filter.h"
19 #include "bnxt_hwrm.h"
21 #include "bnxt_ring.h"
24 #include "bnxt_stats.h"
27 #include "bnxt_vnic.h"
28 #include "hsi_struct_def_dpdk.h"
29 #include "bnxt_nvm_defs.h"
30 #include "bnxt_util.h"
32 #define DRV_MODULE_NAME "bnxt"
33 static const char bnxt_version[] =
34 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
35 int bnxt_logtype_driver;
37 #define PCI_VENDOR_ID_BROADCOM 0x14E4
39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
40 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
41 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
42 #define BROADCOM_DEV_ID_57414_VF 0x16c1
43 #define BROADCOM_DEV_ID_57301 0x16c8
44 #define BROADCOM_DEV_ID_57302 0x16c9
45 #define BROADCOM_DEV_ID_57304_PF 0x16ca
46 #define BROADCOM_DEV_ID_57304_VF 0x16cb
47 #define BROADCOM_DEV_ID_57417_MF 0x16cc
48 #define BROADCOM_DEV_ID_NS2 0x16cd
49 #define BROADCOM_DEV_ID_57311 0x16ce
50 #define BROADCOM_DEV_ID_57312 0x16cf
51 #define BROADCOM_DEV_ID_57402 0x16d0
52 #define BROADCOM_DEV_ID_57404 0x16d1
53 #define BROADCOM_DEV_ID_57406_PF 0x16d2
54 #define BROADCOM_DEV_ID_57406_VF 0x16d3
55 #define BROADCOM_DEV_ID_57402_MF 0x16d4
56 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
57 #define BROADCOM_DEV_ID_57412 0x16d6
58 #define BROADCOM_DEV_ID_57414 0x16d7
59 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
60 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
61 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
62 #define BROADCOM_DEV_ID_57412_MF 0x16de
63 #define BROADCOM_DEV_ID_57314 0x16df
64 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
65 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
66 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
67 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
68 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
69 #define BROADCOM_DEV_ID_57404_MF 0x16e7
70 #define BROADCOM_DEV_ID_57406_MF 0x16e8
71 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
72 #define BROADCOM_DEV_ID_57407_MF 0x16ea
73 #define BROADCOM_DEV_ID_57414_MF 0x16ec
74 #define BROADCOM_DEV_ID_57416_MF 0x16ee
75 #define BROADCOM_DEV_ID_57508 0x1750
76 #define BROADCOM_DEV_ID_57504 0x1751
77 #define BROADCOM_DEV_ID_57502 0x1752
78 #define BROADCOM_DEV_ID_57500_VF1 0x1806
79 #define BROADCOM_DEV_ID_57500_VF2 0x1807
80 #define BROADCOM_DEV_ID_58802 0xd802
81 #define BROADCOM_DEV_ID_58804 0xd804
82 #define BROADCOM_DEV_ID_58808 0x16f0
83 #define BROADCOM_DEV_ID_58802_VF 0xd800
85 static const struct rte_pci_id bnxt_pci_id_map[] = {
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
87 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
89 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
130 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
131 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
132 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
133 { .vendor_id = 0, /* sentinel */ },
136 #define BNXT_ETH_RSS_SUPPORT ( \
138 ETH_RSS_NONFRAG_IPV4_TCP | \
139 ETH_RSS_NONFRAG_IPV4_UDP | \
141 ETH_RSS_NONFRAG_IPV6_TCP | \
142 ETH_RSS_NONFRAG_IPV6_UDP)
144 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
145 DEV_TX_OFFLOAD_IPV4_CKSUM | \
146 DEV_TX_OFFLOAD_TCP_CKSUM | \
147 DEV_TX_OFFLOAD_UDP_CKSUM | \
148 DEV_TX_OFFLOAD_TCP_TSO | \
149 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
150 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
151 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
152 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
153 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
154 DEV_TX_OFFLOAD_MULTI_SEGS)
156 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
157 DEV_RX_OFFLOAD_VLAN_STRIP | \
158 DEV_RX_OFFLOAD_IPV4_CKSUM | \
159 DEV_RX_OFFLOAD_UDP_CKSUM | \
160 DEV_RX_OFFLOAD_TCP_CKSUM | \
161 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
162 DEV_RX_OFFLOAD_JUMBO_FRAME | \
163 DEV_RX_OFFLOAD_KEEP_CRC | \
164 DEV_RX_OFFLOAD_TCP_LRO)
166 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
167 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
168 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
169 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
170 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
171 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
172 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
174 int is_bnxt_in_error(struct bnxt *bp)
176 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
178 if (bp->flags & BNXT_FLAG_FW_RESET)
184 /***********************/
187 * High level utility functions
190 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
192 if (!BNXT_CHIP_THOR(bp))
195 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
196 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
197 BNXT_RSS_ENTRIES_PER_CTX_THOR;
200 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
202 if (!BNXT_CHIP_THOR(bp))
203 return HW_HASH_INDEX_SIZE;
205 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
208 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
210 bnxt_free_filter_mem(bp);
211 bnxt_free_vnic_attributes(bp);
212 bnxt_free_vnic_mem(bp);
214 /* tx/rx rings are configured as part of *_queue_setup callbacks.
215 * If the number of rings change across fw update,
216 * we don't have much choice except to warn the user.
220 bnxt_free_tx_rings(bp);
221 bnxt_free_rx_rings(bp);
223 bnxt_free_async_cp_ring(bp);
226 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
230 rc = bnxt_alloc_ring_grps(bp);
234 rc = bnxt_alloc_async_ring_struct(bp);
238 rc = bnxt_alloc_vnic_mem(bp);
242 rc = bnxt_alloc_vnic_attributes(bp);
246 rc = bnxt_alloc_filter_mem(bp);
250 rc = bnxt_alloc_async_cp_ring(bp);
257 bnxt_free_mem(bp, reconfig);
261 static int bnxt_init_chip(struct bnxt *bp)
263 struct bnxt_rx_queue *rxq;
264 struct rte_eth_link new;
265 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
266 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
267 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
268 uint64_t rx_offloads = dev_conf->rxmode.offloads;
269 uint32_t intr_vector = 0;
270 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
271 uint32_t vec = BNXT_MISC_VEC_ID;
275 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
276 bp->eth_dev->data->dev_conf.rxmode.offloads |=
277 DEV_RX_OFFLOAD_JUMBO_FRAME;
278 bp->flags |= BNXT_FLAG_JUMBO;
280 bp->eth_dev->data->dev_conf.rxmode.offloads &=
281 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
282 bp->flags &= ~BNXT_FLAG_JUMBO;
285 /* THOR does not support ring groups.
286 * But we will use the array to save RSS context IDs.
288 if (BNXT_CHIP_THOR(bp))
289 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
291 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
293 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
297 rc = bnxt_alloc_hwrm_rings(bp);
299 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
303 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
305 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
309 rc = bnxt_mq_rx_configure(bp);
311 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
315 /* VNIC configuration */
316 for (i = 0; i < bp->nr_vnics; i++) {
317 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
318 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
319 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
321 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
322 if (!vnic->fw_grp_ids) {
324 "Failed to alloc %d bytes for group ids\n",
329 memset(vnic->fw_grp_ids, -1, size);
331 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
332 i, vnic, vnic->fw_grp_ids);
334 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
336 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
341 /* Alloc RSS context only if RSS mode is enabled */
342 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
343 int j, nr_ctxs = bnxt_rss_ctxts(bp);
346 for (j = 0; j < nr_ctxs; j++) {
347 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
353 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
357 vnic->num_lb_ctxts = nr_ctxs;
361 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
362 * setting is not available at this time, it will not be
363 * configured correctly in the CFA.
365 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
366 vnic->vlan_strip = true;
368 vnic->vlan_strip = false;
370 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
372 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
377 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
380 "HWRM vnic %d filter failure rc: %x\n",
385 for (j = 0; j < bp->rx_nr_rings; j++) {
386 rxq = bp->eth_dev->data->rx_queues[j];
389 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
390 j, rxq->vnic, rxq->vnic->fw_grp_ids);
392 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
393 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
396 rc = bnxt_vnic_rss_configure(bp, vnic);
399 "HWRM vnic set RSS failure rc: %x\n", rc);
403 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
405 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
406 DEV_RX_OFFLOAD_TCP_LRO)
407 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
409 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
411 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
414 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
418 /* check and configure queue intr-vector mapping */
419 if ((rte_intr_cap_multiple(intr_handle) ||
420 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
421 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
422 intr_vector = bp->eth_dev->data->nb_rx_queues;
423 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
424 if (intr_vector > bp->rx_cp_nr_rings) {
425 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
429 rc = rte_intr_efd_enable(intr_handle, intr_vector);
434 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
435 intr_handle->intr_vec =
436 rte_zmalloc("intr_vec",
437 bp->eth_dev->data->nb_rx_queues *
439 if (intr_handle->intr_vec == NULL) {
440 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
441 " intr_vec", bp->eth_dev->data->nb_rx_queues);
445 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
446 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
447 intr_handle->intr_vec, intr_handle->nb_efd,
448 intr_handle->max_intr);
449 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
451 intr_handle->intr_vec[queue_id] =
452 vec + BNXT_RX_VEC_START;
453 if (vec < base + intr_handle->nb_efd - 1)
458 /* enable uio/vfio intr/eventfd mapping */
459 rc = rte_intr_enable(intr_handle);
463 rc = bnxt_get_hwrm_link_config(bp, &new);
465 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
469 if (!bp->link_info.link_up) {
470 rc = bnxt_set_hwrm_link_config(bp, true);
473 "HWRM link config failure rc: %x\n", rc);
477 bnxt_print_link_info(bp->eth_dev);
482 rte_free(intr_handle->intr_vec);
484 rte_intr_efd_disable(intr_handle);
486 /* Some of the error status returned by FW may not be from errno.h */
493 static int bnxt_shutdown_nic(struct bnxt *bp)
495 bnxt_free_all_hwrm_resources(bp);
496 bnxt_free_all_filters(bp);
497 bnxt_free_all_vnics(bp);
501 static int bnxt_init_nic(struct bnxt *bp)
505 if (BNXT_HAS_RING_GRPS(bp)) {
506 rc = bnxt_init_ring_grps(bp);
512 bnxt_init_filters(bp);
518 * Device configuration and status function
521 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
522 struct rte_eth_dev_info *dev_info)
524 struct bnxt *bp = eth_dev->data->dev_private;
525 uint16_t max_vnics, i, j, vpool, vrxq;
526 unsigned int max_rx_rings;
529 rc = is_bnxt_in_error(bp);
534 dev_info->max_mac_addrs = bp->max_l2_ctx;
535 dev_info->max_hash_mac_addrs = 0;
537 /* PF/VF specifics */
539 dev_info->max_vfs = bp->pdev->max_vfs;
540 max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
541 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
542 dev_info->max_rx_queues = max_rx_rings;
543 dev_info->max_tx_queues = max_rx_rings;
544 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
545 dev_info->hash_key_size = 40;
546 max_vnics = bp->max_vnics;
549 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
550 dev_info->max_mtu = BNXT_MAX_MTU;
552 /* Fast path specifics */
553 dev_info->min_rx_bufsize = 1;
554 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
556 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
557 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
558 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
559 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
560 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
563 dev_info->default_rxconf = (struct rte_eth_rxconf) {
569 .rx_free_thresh = 32,
570 /* If no descriptors available, pkts are dropped by default */
574 dev_info->default_txconf = (struct rte_eth_txconf) {
580 .tx_free_thresh = 32,
583 eth_dev->data->dev_conf.intr_conf.lsc = 1;
585 eth_dev->data->dev_conf.intr_conf.rxq = 1;
586 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
587 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
588 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
589 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
594 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
595 * need further investigation.
599 vpool = 64; /* ETH_64_POOLS */
600 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
601 for (i = 0; i < 4; vpool >>= 1, i++) {
602 if (max_vnics > vpool) {
603 for (j = 0; j < 5; vrxq >>= 1, j++) {
604 if (dev_info->max_rx_queues > vrxq) {
610 /* Not enough resources to support VMDq */
614 /* Not enough resources to support VMDq */
618 dev_info->max_vmdq_pools = vpool;
619 dev_info->vmdq_queue_num = vrxq;
621 dev_info->vmdq_pool_base = 0;
622 dev_info->vmdq_queue_base = 0;
627 /* Configure the device based on the configuration provided */
628 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
630 struct bnxt *bp = eth_dev->data->dev_private;
631 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
634 bp->rx_queues = (void *)eth_dev->data->rx_queues;
635 bp->tx_queues = (void *)eth_dev->data->tx_queues;
636 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
637 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
639 rc = is_bnxt_in_error(bp);
643 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
644 rc = bnxt_hwrm_check_vf_rings(bp);
646 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
650 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
652 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
656 /* legacy driver needs to get updated values */
657 rc = bnxt_hwrm_func_qcaps(bp);
659 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
664 /* Inherit new configurations */
665 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
666 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
667 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
668 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
669 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
673 if (BNXT_HAS_RING_GRPS(bp) &&
674 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
677 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
678 bp->max_vnics < eth_dev->data->nb_rx_queues)
681 bp->rx_cp_nr_rings = bp->rx_nr_rings;
682 bp->tx_cp_nr_rings = bp->tx_nr_rings;
684 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
686 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
687 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
689 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
695 "Insufficient resources to support requested config\n");
697 "Num Queues Requested: Tx %d, Rx %d\n",
698 eth_dev->data->nb_tx_queues,
699 eth_dev->data->nb_rx_queues);
701 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
702 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
703 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
707 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
709 struct rte_eth_link *link = ð_dev->data->dev_link;
711 if (link->link_status)
712 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
713 eth_dev->data->port_id,
714 (uint32_t)link->link_speed,
715 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
716 ("full-duplex") : ("half-duplex\n"));
718 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
719 eth_dev->data->port_id);
723 * Determine whether the current configuration requires support for scattered
724 * receive; return 1 if scattered receive is required and 0 if not.
726 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
731 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
732 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
734 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
735 RTE_PKTMBUF_HEADROOM);
736 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
742 static eth_rx_burst_t
743 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
746 #ifndef RTE_LIBRTE_IEEE1588
748 * Vector mode receive can be enabled only if scatter rx is not
749 * in use and rx offloads are limited to VLAN stripping and
752 if (!eth_dev->data->scattered_rx &&
753 !(eth_dev->data->dev_conf.rxmode.offloads &
754 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
755 DEV_RX_OFFLOAD_KEEP_CRC |
756 DEV_RX_OFFLOAD_JUMBO_FRAME |
757 DEV_RX_OFFLOAD_IPV4_CKSUM |
758 DEV_RX_OFFLOAD_UDP_CKSUM |
759 DEV_RX_OFFLOAD_TCP_CKSUM |
760 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
761 DEV_RX_OFFLOAD_VLAN_FILTER))) {
762 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
763 eth_dev->data->port_id);
764 return bnxt_recv_pkts_vec;
766 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
767 eth_dev->data->port_id);
769 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
770 eth_dev->data->port_id,
771 eth_dev->data->scattered_rx,
772 eth_dev->data->dev_conf.rxmode.offloads);
775 return bnxt_recv_pkts;
778 static eth_tx_burst_t
779 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
782 #ifndef RTE_LIBRTE_IEEE1588
784 * Vector mode transmit can be enabled only if not using scatter rx
787 if (!eth_dev->data->scattered_rx &&
788 !eth_dev->data->dev_conf.txmode.offloads) {
789 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
790 eth_dev->data->port_id);
791 return bnxt_xmit_pkts_vec;
793 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
794 eth_dev->data->port_id);
796 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
797 eth_dev->data->port_id,
798 eth_dev->data->scattered_rx,
799 eth_dev->data->dev_conf.txmode.offloads);
802 return bnxt_xmit_pkts;
805 static int bnxt_handle_if_change_status(struct bnxt *bp)
809 /* Since fw has undergone a reset and lost all contexts,
810 * set fatal flag to not issue hwrm during cleanup
812 bp->flags |= BNXT_FLAG_FATAL_ERROR;
813 bnxt_uninit_resources(bp, true);
815 /* clear fatal flag so that re-init happens */
816 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
817 rc = bnxt_init_resources(bp, true);
819 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
824 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
826 struct bnxt *bp = eth_dev->data->dev_private;
827 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
831 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
833 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
834 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
838 rc = bnxt_hwrm_if_change(bp, 1);
840 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
841 rc = bnxt_handle_if_change_status(bp);
847 rc = bnxt_init_chip(bp);
851 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
853 bnxt_link_update_op(eth_dev, 1);
855 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
856 vlan_mask |= ETH_VLAN_FILTER_MASK;
857 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
858 vlan_mask |= ETH_VLAN_STRIP_MASK;
859 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
863 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
864 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
866 bp->flags |= BNXT_FLAG_INIT_DONE;
867 eth_dev->data->dev_started = 1;
869 bnxt_schedule_fw_health_check(bp);
873 bnxt_hwrm_if_change(bp, 0);
874 bnxt_shutdown_nic(bp);
875 bnxt_free_tx_mbufs(bp);
876 bnxt_free_rx_mbufs(bp);
880 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
882 struct bnxt *bp = eth_dev->data->dev_private;
885 if (!bp->link_info.link_up)
886 rc = bnxt_set_hwrm_link_config(bp, true);
888 eth_dev->data->dev_link.link_status = 1;
890 bnxt_print_link_info(eth_dev);
894 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
896 struct bnxt *bp = eth_dev->data->dev_private;
898 eth_dev->data->dev_link.link_status = 0;
899 bnxt_set_hwrm_link_config(bp, false);
900 bp->link_info.link_up = 0;
905 /* Unload the driver, release resources */
906 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
908 struct bnxt *bp = eth_dev->data->dev_private;
909 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
910 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
912 eth_dev->data->dev_started = 0;
913 /* Prevent crashes when queues are still in use */
914 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
915 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
917 bnxt_disable_int(bp);
919 /* disable uio/vfio intr/eventfd mapping */
920 rte_intr_disable(intr_handle);
922 bnxt_cancel_fw_health_check(bp);
924 bp->flags &= ~BNXT_FLAG_INIT_DONE;
925 if (bp->eth_dev->data->dev_started) {
926 /* TBD: STOP HW queues DMA */
927 eth_dev->data->dev_link.link_status = 0;
929 bnxt_dev_set_link_down_op(eth_dev);
930 /* Wait for link to be reset and the async notification to process. */
931 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
933 /* Clean queue intr-vector mapping */
934 rte_intr_efd_disable(intr_handle);
935 if (intr_handle->intr_vec != NULL) {
936 rte_free(intr_handle->intr_vec);
937 intr_handle->intr_vec = NULL;
940 bnxt_hwrm_port_clr_stats(bp);
941 bnxt_free_tx_mbufs(bp);
942 bnxt_free_rx_mbufs(bp);
943 /* Process any remaining notifications in default completion queue */
944 bnxt_int_handler(eth_dev);
945 bnxt_shutdown_nic(bp);
946 bnxt_hwrm_if_change(bp, 0);
950 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
952 struct bnxt *bp = eth_dev->data->dev_private;
954 if (bp->dev_stopped == 0)
955 bnxt_dev_stop_op(eth_dev);
957 if (eth_dev->data->mac_addrs != NULL) {
958 rte_free(eth_dev->data->mac_addrs);
959 eth_dev->data->mac_addrs = NULL;
961 if (bp->grp_info != NULL) {
962 rte_free(bp->grp_info);
966 bnxt_dev_uninit(eth_dev);
969 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
972 struct bnxt *bp = eth_dev->data->dev_private;
973 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
974 struct bnxt_vnic_info *vnic;
975 struct bnxt_filter_info *filter, *temp_filter;
978 if (is_bnxt_in_error(bp))
982 * Loop through all VNICs from the specified filter flow pools to
983 * remove the corresponding MAC addr filter
985 for (i = 0; i < bp->nr_vnics; i++) {
986 if (!(pool_mask & (1ULL << i)))
989 vnic = &bp->vnic_info[i];
990 filter = STAILQ_FIRST(&vnic->filter);
992 temp_filter = STAILQ_NEXT(filter, next);
993 if (filter->mac_index == index) {
994 STAILQ_REMOVE(&vnic->filter, filter,
995 bnxt_filter_info, next);
996 bnxt_hwrm_clear_l2_filter(bp, filter);
997 filter->mac_index = INVALID_MAC_INDEX;
998 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
999 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1002 filter = temp_filter;
1007 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1008 struct rte_ether_addr *mac_addr,
1009 uint32_t index, uint32_t pool)
1011 struct bnxt *bp = eth_dev->data->dev_private;
1012 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1013 struct bnxt_filter_info *filter;
1016 rc = is_bnxt_in_error(bp);
1020 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1021 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1026 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1029 /* Attach requested MAC address to the new l2_filter */
1030 STAILQ_FOREACH(filter, &vnic->filter, next) {
1031 if (filter->mac_index == index) {
1033 "MAC addr already existed for pool %d\n", pool);
1037 filter = bnxt_alloc_filter(bp);
1039 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1043 filter->mac_index = index;
1044 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1046 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1048 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1050 filter->mac_index = INVALID_MAC_INDEX;
1051 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1052 bnxt_free_filter(bp, filter);
1058 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1061 struct bnxt *bp = eth_dev->data->dev_private;
1062 struct rte_eth_link new;
1063 unsigned int cnt = BNXT_LINK_WAIT_CNT;
1065 rc = is_bnxt_in_error(bp);
1069 memset(&new, 0, sizeof(new));
1071 /* Retrieve link info from hardware */
1072 rc = bnxt_get_hwrm_link_config(bp, &new);
1074 new.link_speed = ETH_LINK_SPEED_100M;
1075 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1077 "Failed to retrieve link rc = 0x%x!\n", rc);
1081 if (!wait_to_complete || new.link_status)
1084 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1088 /* Timed out or success */
1089 if (new.link_status != eth_dev->data->dev_link.link_status ||
1090 new.link_speed != eth_dev->data->dev_link.link_speed) {
1091 rte_eth_linkstatus_set(eth_dev, &new);
1093 _rte_eth_dev_callback_process(eth_dev,
1094 RTE_ETH_EVENT_INTR_LSC,
1097 bnxt_print_link_info(eth_dev);
1103 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1105 struct bnxt *bp = eth_dev->data->dev_private;
1106 struct bnxt_vnic_info *vnic;
1110 rc = is_bnxt_in_error(bp);
1114 if (bp->vnic_info == NULL)
1117 vnic = &bp->vnic_info[0];
1119 old_flags = vnic->flags;
1120 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1121 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1123 vnic->flags = old_flags;
1128 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1130 struct bnxt *bp = eth_dev->data->dev_private;
1131 struct bnxt_vnic_info *vnic;
1135 rc = is_bnxt_in_error(bp);
1139 if (bp->vnic_info == NULL)
1142 vnic = &bp->vnic_info[0];
1144 old_flags = vnic->flags;
1145 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1146 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1148 vnic->flags = old_flags;
1153 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1155 struct bnxt *bp = eth_dev->data->dev_private;
1156 struct bnxt_vnic_info *vnic;
1160 rc = is_bnxt_in_error(bp);
1164 if (bp->vnic_info == NULL)
1167 vnic = &bp->vnic_info[0];
1169 old_flags = vnic->flags;
1170 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1171 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1173 vnic->flags = old_flags;
1178 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1180 struct bnxt *bp = eth_dev->data->dev_private;
1181 struct bnxt_vnic_info *vnic;
1185 rc = is_bnxt_in_error(bp);
1189 if (bp->vnic_info == NULL)
1192 vnic = &bp->vnic_info[0];
1194 old_flags = vnic->flags;
1195 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1196 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1198 vnic->flags = old_flags;
1203 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1204 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1206 if (qid >= bp->rx_nr_rings)
1209 return bp->eth_dev->data->rx_queues[qid];
1212 /* Return rxq corresponding to a given rss table ring/group ID. */
1213 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1215 struct bnxt_rx_queue *rxq;
1218 if (!BNXT_HAS_RING_GRPS(bp)) {
1219 for (i = 0; i < bp->rx_nr_rings; i++) {
1220 rxq = bp->eth_dev->data->rx_queues[i];
1221 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1225 for (i = 0; i < bp->rx_nr_rings; i++) {
1226 if (bp->grp_info[i].fw_grp_id == fwr)
1231 return INVALID_HW_RING_ID;
1234 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1235 struct rte_eth_rss_reta_entry64 *reta_conf,
1238 struct bnxt *bp = eth_dev->data->dev_private;
1239 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1240 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1241 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1245 rc = is_bnxt_in_error(bp);
1249 if (!vnic->rss_table)
1252 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1255 if (reta_size != tbl_size) {
1256 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1257 "(%d) must equal the size supported by the hardware "
1258 "(%d)\n", reta_size, tbl_size);
1262 for (i = 0; i < reta_size; i++) {
1263 struct bnxt_rx_queue *rxq;
1265 idx = i / RTE_RETA_GROUP_SIZE;
1266 sft = i % RTE_RETA_GROUP_SIZE;
1268 if (!(reta_conf[idx].mask & (1ULL << sft)))
1271 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1273 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1277 if (BNXT_CHIP_THOR(bp)) {
1278 vnic->rss_table[i * 2] =
1279 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1280 vnic->rss_table[i * 2 + 1] =
1281 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1283 vnic->rss_table[i] =
1284 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1287 vnic->rss_table[i] =
1288 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1291 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1295 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1296 struct rte_eth_rss_reta_entry64 *reta_conf,
1299 struct bnxt *bp = eth_dev->data->dev_private;
1300 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1301 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1302 uint16_t idx, sft, i;
1305 rc = is_bnxt_in_error(bp);
1309 /* Retrieve from the default VNIC */
1312 if (!vnic->rss_table)
1315 if (reta_size != tbl_size) {
1316 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1317 "(%d) must equal the size supported by the hardware "
1318 "(%d)\n", reta_size, tbl_size);
1322 for (idx = 0, i = 0; i < reta_size; i++) {
1323 idx = i / RTE_RETA_GROUP_SIZE;
1324 sft = i % RTE_RETA_GROUP_SIZE;
1326 if (reta_conf[idx].mask & (1ULL << sft)) {
1329 if (BNXT_CHIP_THOR(bp))
1330 qid = bnxt_rss_to_qid(bp,
1331 vnic->rss_table[i * 2]);
1333 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1335 if (qid == INVALID_HW_RING_ID) {
1336 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1339 reta_conf[idx].reta[sft] = qid;
1346 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1347 struct rte_eth_rss_conf *rss_conf)
1349 struct bnxt *bp = eth_dev->data->dev_private;
1350 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1351 struct bnxt_vnic_info *vnic;
1352 uint16_t hash_type = 0;
1356 rc = is_bnxt_in_error(bp);
1361 * If RSS enablement were different than dev_configure,
1362 * then return -EINVAL
1364 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1365 if (!rss_conf->rss_hf)
1366 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1368 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1372 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1373 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1375 if (rss_conf->rss_hf & ETH_RSS_IPV4)
1376 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1377 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1378 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1379 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1380 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1381 if (rss_conf->rss_hf & ETH_RSS_IPV6)
1382 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1383 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1384 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1385 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1386 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1388 /* Update the RSS VNIC(s) */
1389 for (i = 0; i < bp->nr_vnics; i++) {
1390 vnic = &bp->vnic_info[i];
1391 vnic->hash_type = hash_type;
1394 * Use the supplied key if the key length is
1395 * acceptable and the rss_key is not NULL
1397 if (rss_conf->rss_key &&
1398 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
1399 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
1400 rss_conf->rss_key_len);
1402 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1407 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1408 struct rte_eth_rss_conf *rss_conf)
1410 struct bnxt *bp = eth_dev->data->dev_private;
1411 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1413 uint32_t hash_types;
1415 rc = is_bnxt_in_error(bp);
1419 /* RSS configuration is the same for all VNICs */
1420 if (vnic && vnic->rss_hash_key) {
1421 if (rss_conf->rss_key) {
1422 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1423 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1424 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1427 hash_types = vnic->hash_type;
1428 rss_conf->rss_hf = 0;
1429 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1430 rss_conf->rss_hf |= ETH_RSS_IPV4;
1431 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1433 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1434 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1436 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1438 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1439 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1441 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1443 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1444 rss_conf->rss_hf |= ETH_RSS_IPV6;
1445 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1447 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1448 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1450 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1452 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1453 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1455 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1459 "Unknwon RSS config from firmware (%08x), RSS disabled",
1464 rss_conf->rss_hf = 0;
1469 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1470 struct rte_eth_fc_conf *fc_conf)
1472 struct bnxt *bp = dev->data->dev_private;
1473 struct rte_eth_link link_info;
1476 rc = is_bnxt_in_error(bp);
1480 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1484 memset(fc_conf, 0, sizeof(*fc_conf));
1485 if (bp->link_info.auto_pause)
1486 fc_conf->autoneg = 1;
1487 switch (bp->link_info.pause) {
1489 fc_conf->mode = RTE_FC_NONE;
1491 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1492 fc_conf->mode = RTE_FC_TX_PAUSE;
1494 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1495 fc_conf->mode = RTE_FC_RX_PAUSE;
1497 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1498 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1499 fc_conf->mode = RTE_FC_FULL;
1505 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1506 struct rte_eth_fc_conf *fc_conf)
1508 struct bnxt *bp = dev->data->dev_private;
1511 rc = is_bnxt_in_error(bp);
1515 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1516 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1520 switch (fc_conf->mode) {
1522 bp->link_info.auto_pause = 0;
1523 bp->link_info.force_pause = 0;
1525 case RTE_FC_RX_PAUSE:
1526 if (fc_conf->autoneg) {
1527 bp->link_info.auto_pause =
1528 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1529 bp->link_info.force_pause = 0;
1531 bp->link_info.auto_pause = 0;
1532 bp->link_info.force_pause =
1533 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1536 case RTE_FC_TX_PAUSE:
1537 if (fc_conf->autoneg) {
1538 bp->link_info.auto_pause =
1539 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1540 bp->link_info.force_pause = 0;
1542 bp->link_info.auto_pause = 0;
1543 bp->link_info.force_pause =
1544 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1548 if (fc_conf->autoneg) {
1549 bp->link_info.auto_pause =
1550 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1551 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1552 bp->link_info.force_pause = 0;
1554 bp->link_info.auto_pause = 0;
1555 bp->link_info.force_pause =
1556 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1557 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1561 return bnxt_set_hwrm_link_config(bp, true);
1564 /* Add UDP tunneling port */
1566 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1567 struct rte_eth_udp_tunnel *udp_tunnel)
1569 struct bnxt *bp = eth_dev->data->dev_private;
1570 uint16_t tunnel_type = 0;
1573 rc = is_bnxt_in_error(bp);
1577 switch (udp_tunnel->prot_type) {
1578 case RTE_TUNNEL_TYPE_VXLAN:
1579 if (bp->vxlan_port_cnt) {
1580 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1581 udp_tunnel->udp_port);
1582 if (bp->vxlan_port != udp_tunnel->udp_port) {
1583 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1586 bp->vxlan_port_cnt++;
1590 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1591 bp->vxlan_port_cnt++;
1593 case RTE_TUNNEL_TYPE_GENEVE:
1594 if (bp->geneve_port_cnt) {
1595 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1596 udp_tunnel->udp_port);
1597 if (bp->geneve_port != udp_tunnel->udp_port) {
1598 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1601 bp->geneve_port_cnt++;
1605 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1606 bp->geneve_port_cnt++;
1609 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1612 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1618 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1619 struct rte_eth_udp_tunnel *udp_tunnel)
1621 struct bnxt *bp = eth_dev->data->dev_private;
1622 uint16_t tunnel_type = 0;
1626 rc = is_bnxt_in_error(bp);
1630 switch (udp_tunnel->prot_type) {
1631 case RTE_TUNNEL_TYPE_VXLAN:
1632 if (!bp->vxlan_port_cnt) {
1633 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1636 if (bp->vxlan_port != udp_tunnel->udp_port) {
1637 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1638 udp_tunnel->udp_port, bp->vxlan_port);
1641 if (--bp->vxlan_port_cnt)
1645 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1646 port = bp->vxlan_fw_dst_port_id;
1648 case RTE_TUNNEL_TYPE_GENEVE:
1649 if (!bp->geneve_port_cnt) {
1650 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1653 if (bp->geneve_port != udp_tunnel->udp_port) {
1654 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1655 udp_tunnel->udp_port, bp->geneve_port);
1658 if (--bp->geneve_port_cnt)
1662 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1663 port = bp->geneve_fw_dst_port_id;
1666 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1670 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1673 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1676 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1677 bp->geneve_port = 0;
1682 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1684 struct bnxt_filter_info *filter;
1685 struct bnxt_vnic_info *vnic;
1687 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1689 /* if VLAN exists && VLAN matches vlan_id
1690 * remove the MAC+VLAN filter
1691 * add a new MAC only filter
1693 * VLAN filter doesn't exist, just skip and continue
1695 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1696 filter = STAILQ_FIRST(&vnic->filter);
1698 /* Search for this matching MAC+VLAN filter */
1699 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1700 !memcmp(filter->l2_addr,
1702 RTE_ETHER_ADDR_LEN)) {
1703 /* Delete the filter */
1704 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1707 STAILQ_REMOVE(&vnic->filter, filter,
1708 bnxt_filter_info, next);
1709 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1712 "Del Vlan filter for %d\n",
1716 filter = STAILQ_NEXT(filter, next);
1721 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1723 struct bnxt_filter_info *filter;
1724 struct bnxt_vnic_info *vnic;
1726 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1727 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1728 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1730 /* Implementation notes on the use of VNIC in this command:
1732 * By default, these filters belong to default vnic for the function.
1733 * Once these filters are set up, only destination VNIC can be modified.
1734 * If the destination VNIC is not specified in this command,
1735 * then the HWRM shall only create an l2 context id.
1738 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1739 filter = STAILQ_FIRST(&vnic->filter);
1740 /* Check if the VLAN has already been added */
1742 if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
1743 !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN))
1746 filter = STAILQ_NEXT(filter, next);
1749 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1750 * command to create MAC+VLAN filter with the right flags, enables set.
1752 filter = bnxt_alloc_filter(bp);
1755 "MAC/VLAN filter alloc failed\n");
1758 /* MAC + VLAN ID filter */
1759 filter->l2_ivlan = vlan_id;
1760 filter->l2_ivlan_mask = 0x0FFF;
1761 filter->enables |= en;
1762 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1764 /* Free the newly allocated filter as we were
1765 * not able to create the filter in hardware.
1767 filter->fw_l2_filter_id = UINT64_MAX;
1768 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1772 /* Add this new filter to the list */
1773 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1775 "Added Vlan filter for %d\n", vlan_id);
1779 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1780 uint16_t vlan_id, int on)
1782 struct bnxt *bp = eth_dev->data->dev_private;
1785 rc = is_bnxt_in_error(bp);
1789 /* These operations apply to ALL existing MAC/VLAN filters */
1791 return bnxt_add_vlan_filter(bp, vlan_id);
1793 return bnxt_del_vlan_filter(bp, vlan_id);
1797 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1799 struct bnxt *bp = dev->data->dev_private;
1800 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1804 rc = is_bnxt_in_error(bp);
1808 if (mask & ETH_VLAN_FILTER_MASK) {
1809 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1810 /* Remove any VLAN filters programmed */
1811 for (i = 0; i < 4095; i++)
1812 bnxt_del_vlan_filter(bp, i);
1814 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1815 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1818 if (mask & ETH_VLAN_STRIP_MASK) {
1819 /* Enable or disable VLAN stripping */
1820 for (i = 0; i < bp->nr_vnics; i++) {
1821 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1822 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1823 vnic->vlan_strip = true;
1825 vnic->vlan_strip = false;
1826 bnxt_hwrm_vnic_cfg(bp, vnic);
1828 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1829 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1832 if (mask & ETH_VLAN_EXTEND_MASK)
1833 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1839 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1840 struct rte_ether_addr *addr)
1842 struct bnxt *bp = dev->data->dev_private;
1843 /* Default Filter is tied to VNIC 0 */
1844 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1845 struct bnxt_filter_info *filter;
1848 rc = is_bnxt_in_error(bp);
1852 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
1855 if (rte_is_zero_ether_addr(addr))
1858 STAILQ_FOREACH(filter, &vnic->filter, next) {
1859 /* Default Filter is at Index 0 */
1860 if (filter->mac_index != 0)
1863 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
1864 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
1865 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1867 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1868 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1870 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1874 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
1875 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1883 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1884 struct rte_ether_addr *mc_addr_set,
1885 uint32_t nb_mc_addr)
1887 struct bnxt *bp = eth_dev->data->dev_private;
1888 char *mc_addr_list = (char *)mc_addr_set;
1889 struct bnxt_vnic_info *vnic;
1890 uint32_t off = 0, i = 0;
1893 rc = is_bnxt_in_error(bp);
1897 vnic = &bp->vnic_info[0];
1899 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1900 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1904 /* TODO Check for Duplicate mcast addresses */
1905 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1906 for (i = 0; i < nb_mc_addr; i++) {
1907 memcpy(vnic->mc_list + off, &mc_addr_list[i],
1908 RTE_ETHER_ADDR_LEN);
1909 off += RTE_ETHER_ADDR_LEN;
1912 vnic->mc_addr_cnt = i;
1915 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1919 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1921 struct bnxt *bp = dev->data->dev_private;
1922 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1923 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1924 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1927 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1928 fw_major, fw_minor, fw_updt);
1930 ret += 1; /* add the size of '\0' */
1931 if (fw_size < (uint32_t)ret)
1938 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1939 struct rte_eth_rxq_info *qinfo)
1941 struct bnxt_rx_queue *rxq;
1943 rxq = dev->data->rx_queues[queue_id];
1945 qinfo->mp = rxq->mb_pool;
1946 qinfo->scattered_rx = dev->data->scattered_rx;
1947 qinfo->nb_desc = rxq->nb_rx_desc;
1949 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1950 qinfo->conf.rx_drop_en = 0;
1951 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1955 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1956 struct rte_eth_txq_info *qinfo)
1958 struct bnxt_tx_queue *txq;
1960 txq = dev->data->tx_queues[queue_id];
1962 qinfo->nb_desc = txq->nb_tx_desc;
1964 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1965 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1966 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1968 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1969 qinfo->conf.tx_rs_thresh = 0;
1970 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1973 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1975 struct bnxt *bp = eth_dev->data->dev_private;
1976 uint32_t new_pkt_size;
1980 rc = is_bnxt_in_error(bp);
1984 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
1985 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
1989 * If vector-mode tx/rx is active, disallow any MTU change that would
1990 * require scattered receive support.
1992 if (eth_dev->data->dev_started &&
1993 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
1994 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
1996 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
1998 "MTU change would require scattered rx support. ");
1999 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2004 if (new_mtu > RTE_ETHER_MTU) {
2005 bp->flags |= BNXT_FLAG_JUMBO;
2006 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2007 DEV_RX_OFFLOAD_JUMBO_FRAME;
2009 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2010 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2011 bp->flags &= ~BNXT_FLAG_JUMBO;
2014 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2016 for (i = 0; i < bp->nr_vnics; i++) {
2017 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2020 vnic->mru = new_mtu + RTE_ETHER_HDR_LEN +
2021 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
2022 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2026 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2027 size -= RTE_PKTMBUF_HEADROOM;
2029 if (size < new_mtu) {
2030 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2036 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2042 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2044 struct bnxt *bp = dev->data->dev_private;
2045 uint16_t vlan = bp->vlan;
2048 rc = is_bnxt_in_error(bp);
2052 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2054 "PVID cannot be modified for this function\n");
2057 bp->vlan = on ? pvid : 0;
2059 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2066 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2068 struct bnxt *bp = dev->data->dev_private;
2071 rc = is_bnxt_in_error(bp);
2075 return bnxt_hwrm_port_led_cfg(bp, true);
2079 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2081 struct bnxt *bp = dev->data->dev_private;
2084 rc = is_bnxt_in_error(bp);
2088 return bnxt_hwrm_port_led_cfg(bp, false);
2092 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2094 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2095 uint32_t desc = 0, raw_cons = 0, cons;
2096 struct bnxt_cp_ring_info *cpr;
2097 struct bnxt_rx_queue *rxq;
2098 struct rx_pkt_cmpl *rxcmp;
2104 rc = is_bnxt_in_error(bp);
2108 rxq = dev->data->rx_queues[rx_queue_id];
2112 while (raw_cons < rxq->nb_rx_desc) {
2113 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2114 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2116 if (!CMPL_VALID(rxcmp, valid))
2118 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
2119 cmp_type = CMP_TYPE(rxcmp);
2120 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
2121 cmp = (rte_le_to_cpu_32(
2122 ((struct rx_tpa_end_cmpl *)
2123 (rxcmp))->agg_bufs_v1) &
2124 RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
2125 RX_TPA_END_CMPL_AGG_BUFS_SFT;
2127 } else if (cmp_type == 0x11) {
2129 cmp = (rxcmp->agg_bufs_v1 &
2130 RX_PKT_CMPL_AGG_BUFS_MASK) >>
2131 RX_PKT_CMPL_AGG_BUFS_SFT;
2136 raw_cons += cmp ? cmp : 2;
2143 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2145 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2146 struct bnxt_rx_ring_info *rxr;
2147 struct bnxt_cp_ring_info *cpr;
2148 struct bnxt_sw_rx_bd *rx_buf;
2149 struct rx_pkt_cmpl *rxcmp;
2150 uint32_t cons, cp_cons;
2156 rc = is_bnxt_in_error(rxq->bp);
2163 if (offset >= rxq->nb_rx_desc)
2166 cons = RING_CMP(cpr->cp_ring_struct, offset);
2167 cp_cons = cpr->cp_raw_cons;
2168 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2170 if (cons > cp_cons) {
2171 if (CMPL_VALID(rxcmp, cpr->valid))
2172 return RTE_ETH_RX_DESC_DONE;
2174 if (CMPL_VALID(rxcmp, !cpr->valid))
2175 return RTE_ETH_RX_DESC_DONE;
2177 rx_buf = &rxr->rx_buf_ring[cons];
2178 if (rx_buf->mbuf == NULL)
2179 return RTE_ETH_RX_DESC_UNAVAIL;
2182 return RTE_ETH_RX_DESC_AVAIL;
2186 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2188 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2189 struct bnxt_tx_ring_info *txr;
2190 struct bnxt_cp_ring_info *cpr;
2191 struct bnxt_sw_tx_bd *tx_buf;
2192 struct tx_pkt_cmpl *txcmp;
2193 uint32_t cons, cp_cons;
2199 rc = is_bnxt_in_error(txq->bp);
2206 if (offset >= txq->nb_tx_desc)
2209 cons = RING_CMP(cpr->cp_ring_struct, offset);
2210 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2211 cp_cons = cpr->cp_raw_cons;
2213 if (cons > cp_cons) {
2214 if (CMPL_VALID(txcmp, cpr->valid))
2215 return RTE_ETH_TX_DESC_UNAVAIL;
2217 if (CMPL_VALID(txcmp, !cpr->valid))
2218 return RTE_ETH_TX_DESC_UNAVAIL;
2220 tx_buf = &txr->tx_buf_ring[cons];
2221 if (tx_buf->mbuf == NULL)
2222 return RTE_ETH_TX_DESC_DONE;
2224 return RTE_ETH_TX_DESC_FULL;
2227 static struct bnxt_filter_info *
2228 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2229 struct rte_eth_ethertype_filter *efilter,
2230 struct bnxt_vnic_info *vnic0,
2231 struct bnxt_vnic_info *vnic,
2234 struct bnxt_filter_info *mfilter = NULL;
2238 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2239 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2240 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2241 " ethertype filter.", efilter->ether_type);
2245 if (efilter->queue >= bp->rx_nr_rings) {
2246 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2251 vnic0 = &bp->vnic_info[0];
2252 vnic = &bp->vnic_info[efilter->queue];
2254 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2259 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2260 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2261 if ((!memcmp(efilter->mac_addr.addr_bytes,
2262 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2264 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2265 mfilter->ethertype == efilter->ether_type)) {
2271 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2272 if ((!memcmp(efilter->mac_addr.addr_bytes,
2273 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2274 mfilter->ethertype == efilter->ether_type &&
2276 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2290 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2291 enum rte_filter_op filter_op,
2294 struct bnxt *bp = dev->data->dev_private;
2295 struct rte_eth_ethertype_filter *efilter =
2296 (struct rte_eth_ethertype_filter *)arg;
2297 struct bnxt_filter_info *bfilter, *filter1;
2298 struct bnxt_vnic_info *vnic, *vnic0;
2301 if (filter_op == RTE_ETH_FILTER_NOP)
2305 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2310 vnic0 = &bp->vnic_info[0];
2311 vnic = &bp->vnic_info[efilter->queue];
2313 switch (filter_op) {
2314 case RTE_ETH_FILTER_ADD:
2315 bnxt_match_and_validate_ether_filter(bp, efilter,
2320 bfilter = bnxt_get_unused_filter(bp);
2321 if (bfilter == NULL) {
2323 "Not enough resources for a new filter.\n");
2326 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2327 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2328 RTE_ETHER_ADDR_LEN);
2329 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2330 RTE_ETHER_ADDR_LEN);
2331 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2332 bfilter->ethertype = efilter->ether_type;
2333 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2335 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2336 if (filter1 == NULL) {
2341 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2342 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2344 bfilter->dst_id = vnic->fw_vnic_id;
2346 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2348 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2351 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2354 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2356 case RTE_ETH_FILTER_DELETE:
2357 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2359 if (ret == -EEXIST) {
2360 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2362 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2364 bnxt_free_filter(bp, filter1);
2365 } else if (ret == 0) {
2366 PMD_DRV_LOG(ERR, "No matching filter found\n");
2370 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2376 bnxt_free_filter(bp, bfilter);
2382 parse_ntuple_filter(struct bnxt *bp,
2383 struct rte_eth_ntuple_filter *nfilter,
2384 struct bnxt_filter_info *bfilter)
2388 if (nfilter->queue >= bp->rx_nr_rings) {
2389 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2393 switch (nfilter->dst_port_mask) {
2395 bfilter->dst_port_mask = -1;
2396 bfilter->dst_port = nfilter->dst_port;
2397 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2398 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2401 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2405 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2406 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2408 switch (nfilter->proto_mask) {
2410 if (nfilter->proto == 17) /* IPPROTO_UDP */
2411 bfilter->ip_protocol = 17;
2412 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2413 bfilter->ip_protocol = 6;
2416 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2419 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2423 switch (nfilter->dst_ip_mask) {
2425 bfilter->dst_ipaddr_mask[0] = -1;
2426 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2427 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2428 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2431 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2435 switch (nfilter->src_ip_mask) {
2437 bfilter->src_ipaddr_mask[0] = -1;
2438 bfilter->src_ipaddr[0] = nfilter->src_ip;
2439 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2440 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2443 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2447 switch (nfilter->src_port_mask) {
2449 bfilter->src_port_mask = -1;
2450 bfilter->src_port = nfilter->src_port;
2451 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2452 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2455 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2460 //nfilter->priority = (uint8_t)filter->priority;
2462 bfilter->enables = en;
2466 static struct bnxt_filter_info*
2467 bnxt_match_ntuple_filter(struct bnxt *bp,
2468 struct bnxt_filter_info *bfilter,
2469 struct bnxt_vnic_info **mvnic)
2471 struct bnxt_filter_info *mfilter = NULL;
2474 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2475 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2476 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2477 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2478 bfilter->src_ipaddr_mask[0] ==
2479 mfilter->src_ipaddr_mask[0] &&
2480 bfilter->src_port == mfilter->src_port &&
2481 bfilter->src_port_mask == mfilter->src_port_mask &&
2482 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2483 bfilter->dst_ipaddr_mask[0] ==
2484 mfilter->dst_ipaddr_mask[0] &&
2485 bfilter->dst_port == mfilter->dst_port &&
2486 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2487 bfilter->flags == mfilter->flags &&
2488 bfilter->enables == mfilter->enables) {
2499 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2500 struct rte_eth_ntuple_filter *nfilter,
2501 enum rte_filter_op filter_op)
2503 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2504 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2507 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2508 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2512 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2513 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2517 bfilter = bnxt_get_unused_filter(bp);
2518 if (bfilter == NULL) {
2520 "Not enough resources for a new filter.\n");
2523 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2527 vnic = &bp->vnic_info[nfilter->queue];
2528 vnic0 = &bp->vnic_info[0];
2529 filter1 = STAILQ_FIRST(&vnic0->filter);
2530 if (filter1 == NULL) {
2535 bfilter->dst_id = vnic->fw_vnic_id;
2536 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2538 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2539 bfilter->ethertype = 0x800;
2540 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2542 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2544 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2545 bfilter->dst_id == mfilter->dst_id) {
2546 PMD_DRV_LOG(ERR, "filter exists.\n");
2549 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2550 bfilter->dst_id != mfilter->dst_id) {
2551 mfilter->dst_id = vnic->fw_vnic_id;
2552 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2553 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2554 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2555 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2556 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2559 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2560 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2565 if (filter_op == RTE_ETH_FILTER_ADD) {
2566 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2567 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2570 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2572 if (mfilter == NULL) {
2573 /* This should not happen. But for Coverity! */
2577 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2579 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2580 bnxt_free_filter(bp, mfilter);
2581 mfilter->fw_l2_filter_id = -1;
2582 bnxt_free_filter(bp, bfilter);
2583 bfilter->fw_l2_filter_id = -1;
2588 bfilter->fw_l2_filter_id = -1;
2589 bnxt_free_filter(bp, bfilter);
2594 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2595 enum rte_filter_op filter_op,
2598 struct bnxt *bp = dev->data->dev_private;
2601 if (filter_op == RTE_ETH_FILTER_NOP)
2605 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2610 switch (filter_op) {
2611 case RTE_ETH_FILTER_ADD:
2612 ret = bnxt_cfg_ntuple_filter(bp,
2613 (struct rte_eth_ntuple_filter *)arg,
2616 case RTE_ETH_FILTER_DELETE:
2617 ret = bnxt_cfg_ntuple_filter(bp,
2618 (struct rte_eth_ntuple_filter *)arg,
2622 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2630 bnxt_parse_fdir_filter(struct bnxt *bp,
2631 struct rte_eth_fdir_filter *fdir,
2632 struct bnxt_filter_info *filter)
2634 enum rte_fdir_mode fdir_mode =
2635 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2636 struct bnxt_vnic_info *vnic0, *vnic;
2637 struct bnxt_filter_info *filter1;
2641 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2644 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2645 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2647 switch (fdir->input.flow_type) {
2648 case RTE_ETH_FLOW_IPV4:
2649 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2651 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2652 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2653 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2654 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2655 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2656 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2657 filter->ip_addr_type =
2658 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2659 filter->src_ipaddr_mask[0] = 0xffffffff;
2660 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2661 filter->dst_ipaddr_mask[0] = 0xffffffff;
2662 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2663 filter->ethertype = 0x800;
2664 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2666 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2667 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2668 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2669 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2670 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2671 filter->dst_port_mask = 0xffff;
2672 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2673 filter->src_port_mask = 0xffff;
2674 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2675 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2676 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2677 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2678 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2679 filter->ip_protocol = 6;
2680 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2681 filter->ip_addr_type =
2682 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2683 filter->src_ipaddr_mask[0] = 0xffffffff;
2684 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2685 filter->dst_ipaddr_mask[0] = 0xffffffff;
2686 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2687 filter->ethertype = 0x800;
2688 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2690 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2691 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2692 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2693 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2694 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2695 filter->dst_port_mask = 0xffff;
2696 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2697 filter->src_port_mask = 0xffff;
2698 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2699 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2700 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2701 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2702 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2703 filter->ip_protocol = 17;
2704 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2705 filter->ip_addr_type =
2706 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2707 filter->src_ipaddr_mask[0] = 0xffffffff;
2708 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2709 filter->dst_ipaddr_mask[0] = 0xffffffff;
2710 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2711 filter->ethertype = 0x800;
2712 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2714 case RTE_ETH_FLOW_IPV6:
2715 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2717 filter->ip_addr_type =
2718 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2719 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2720 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2721 rte_memcpy(filter->src_ipaddr,
2722 fdir->input.flow.ipv6_flow.src_ip, 16);
2723 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2724 rte_memcpy(filter->dst_ipaddr,
2725 fdir->input.flow.ipv6_flow.dst_ip, 16);
2726 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2727 memset(filter->dst_ipaddr_mask, 0xff, 16);
2728 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2729 memset(filter->src_ipaddr_mask, 0xff, 16);
2730 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2731 filter->ethertype = 0x86dd;
2732 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2734 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2735 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2736 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2737 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2738 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2739 filter->dst_port_mask = 0xffff;
2740 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2741 filter->src_port_mask = 0xffff;
2742 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2743 filter->ip_addr_type =
2744 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2745 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2746 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2747 rte_memcpy(filter->src_ipaddr,
2748 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2749 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2750 rte_memcpy(filter->dst_ipaddr,
2751 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2752 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2753 memset(filter->dst_ipaddr_mask, 0xff, 16);
2754 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2755 memset(filter->src_ipaddr_mask, 0xff, 16);
2756 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2757 filter->ethertype = 0x86dd;
2758 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2760 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2761 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2762 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2763 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2764 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2765 filter->dst_port_mask = 0xffff;
2766 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2767 filter->src_port_mask = 0xffff;
2768 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2769 filter->ip_addr_type =
2770 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2771 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2772 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2773 rte_memcpy(filter->src_ipaddr,
2774 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2775 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2776 rte_memcpy(filter->dst_ipaddr,
2777 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2778 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2779 memset(filter->dst_ipaddr_mask, 0xff, 16);
2780 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2781 memset(filter->src_ipaddr_mask, 0xff, 16);
2782 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2783 filter->ethertype = 0x86dd;
2784 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2786 case RTE_ETH_FLOW_L2_PAYLOAD:
2787 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2788 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2790 case RTE_ETH_FLOW_VXLAN:
2791 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2793 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2794 filter->tunnel_type =
2795 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2796 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2798 case RTE_ETH_FLOW_NVGRE:
2799 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2801 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2802 filter->tunnel_type =
2803 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2804 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2806 case RTE_ETH_FLOW_UNKNOWN:
2807 case RTE_ETH_FLOW_RAW:
2808 case RTE_ETH_FLOW_FRAG_IPV4:
2809 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2810 case RTE_ETH_FLOW_FRAG_IPV6:
2811 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2812 case RTE_ETH_FLOW_IPV6_EX:
2813 case RTE_ETH_FLOW_IPV6_TCP_EX:
2814 case RTE_ETH_FLOW_IPV6_UDP_EX:
2815 case RTE_ETH_FLOW_GENEVE:
2821 vnic0 = &bp->vnic_info[0];
2822 vnic = &bp->vnic_info[fdir->action.rx_queue];
2824 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2829 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2830 rte_memcpy(filter->dst_macaddr,
2831 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2832 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2835 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2836 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2837 filter1 = STAILQ_FIRST(&vnic0->filter);
2838 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2840 filter->dst_id = vnic->fw_vnic_id;
2841 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2842 if (filter->dst_macaddr[i] == 0x00)
2843 filter1 = STAILQ_FIRST(&vnic0->filter);
2845 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2848 if (filter1 == NULL)
2851 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2852 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2854 filter->enables = en;
2859 static struct bnxt_filter_info *
2860 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2861 struct bnxt_vnic_info **mvnic)
2863 struct bnxt_filter_info *mf = NULL;
2866 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2867 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2869 STAILQ_FOREACH(mf, &vnic->filter, next) {
2870 if (mf->filter_type == nf->filter_type &&
2871 mf->flags == nf->flags &&
2872 mf->src_port == nf->src_port &&
2873 mf->src_port_mask == nf->src_port_mask &&
2874 mf->dst_port == nf->dst_port &&
2875 mf->dst_port_mask == nf->dst_port_mask &&
2876 mf->ip_protocol == nf->ip_protocol &&
2877 mf->ip_addr_type == nf->ip_addr_type &&
2878 mf->ethertype == nf->ethertype &&
2879 mf->vni == nf->vni &&
2880 mf->tunnel_type == nf->tunnel_type &&
2881 mf->l2_ovlan == nf->l2_ovlan &&
2882 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2883 mf->l2_ivlan == nf->l2_ivlan &&
2884 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2885 !memcmp(mf->l2_addr, nf->l2_addr,
2886 RTE_ETHER_ADDR_LEN) &&
2887 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2888 RTE_ETHER_ADDR_LEN) &&
2889 !memcmp(mf->src_macaddr, nf->src_macaddr,
2890 RTE_ETHER_ADDR_LEN) &&
2891 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2892 RTE_ETHER_ADDR_LEN) &&
2893 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2894 sizeof(nf->src_ipaddr)) &&
2895 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2896 sizeof(nf->src_ipaddr_mask)) &&
2897 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2898 sizeof(nf->dst_ipaddr)) &&
2899 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2900 sizeof(nf->dst_ipaddr_mask))) {
2911 bnxt_fdir_filter(struct rte_eth_dev *dev,
2912 enum rte_filter_op filter_op,
2915 struct bnxt *bp = dev->data->dev_private;
2916 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2917 struct bnxt_filter_info *filter, *match;
2918 struct bnxt_vnic_info *vnic, *mvnic;
2921 if (filter_op == RTE_ETH_FILTER_NOP)
2924 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2927 switch (filter_op) {
2928 case RTE_ETH_FILTER_ADD:
2929 case RTE_ETH_FILTER_DELETE:
2931 filter = bnxt_get_unused_filter(bp);
2932 if (filter == NULL) {
2934 "Not enough resources for a new flow.\n");
2938 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2941 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2943 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2944 vnic = &bp->vnic_info[0];
2946 vnic = &bp->vnic_info[fdir->action.rx_queue];
2948 match = bnxt_match_fdir(bp, filter, &mvnic);
2949 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2950 if (match->dst_id == vnic->fw_vnic_id) {
2951 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2955 match->dst_id = vnic->fw_vnic_id;
2956 ret = bnxt_hwrm_set_ntuple_filter(bp,
2959 STAILQ_REMOVE(&mvnic->filter, match,
2960 bnxt_filter_info, next);
2961 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2963 "Filter with matching pattern exist\n");
2965 "Updated it to new destination q\n");
2969 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2970 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2975 if (filter_op == RTE_ETH_FILTER_ADD) {
2976 ret = bnxt_hwrm_set_ntuple_filter(bp,
2981 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2983 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2984 STAILQ_REMOVE(&vnic->filter, match,
2985 bnxt_filter_info, next);
2986 bnxt_free_filter(bp, match);
2987 filter->fw_l2_filter_id = -1;
2988 bnxt_free_filter(bp, filter);
2991 case RTE_ETH_FILTER_FLUSH:
2992 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2993 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2995 STAILQ_FOREACH(filter, &vnic->filter, next) {
2996 if (filter->filter_type ==
2997 HWRM_CFA_NTUPLE_FILTER) {
2999 bnxt_hwrm_clear_ntuple_filter(bp,
3001 STAILQ_REMOVE(&vnic->filter, filter,
3002 bnxt_filter_info, next);
3007 case RTE_ETH_FILTER_UPDATE:
3008 case RTE_ETH_FILTER_STATS:
3009 case RTE_ETH_FILTER_INFO:
3010 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3013 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3020 filter->fw_l2_filter_id = -1;
3021 bnxt_free_filter(bp, filter);
3026 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3027 enum rte_filter_type filter_type,
3028 enum rte_filter_op filter_op, void *arg)
3032 ret = is_bnxt_in_error(dev->data->dev_private);
3036 switch (filter_type) {
3037 case RTE_ETH_FILTER_TUNNEL:
3039 "filter type: %d: To be implemented\n", filter_type);
3041 case RTE_ETH_FILTER_FDIR:
3042 ret = bnxt_fdir_filter(dev, filter_op, arg);
3044 case RTE_ETH_FILTER_NTUPLE:
3045 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3047 case RTE_ETH_FILTER_ETHERTYPE:
3048 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3050 case RTE_ETH_FILTER_GENERIC:
3051 if (filter_op != RTE_ETH_FILTER_GET)
3053 *(const void **)arg = &bnxt_flow_ops;
3057 "Filter type (%d) not supported", filter_type);
3064 static const uint32_t *
3065 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3067 static const uint32_t ptypes[] = {
3068 RTE_PTYPE_L2_ETHER_VLAN,
3069 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3070 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3074 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3075 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3076 RTE_PTYPE_INNER_L4_ICMP,
3077 RTE_PTYPE_INNER_L4_TCP,
3078 RTE_PTYPE_INNER_L4_UDP,
3082 if (!dev->rx_pkt_burst)
3088 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3091 uint32_t reg_base = *reg_arr & 0xfffff000;
3095 for (i = 0; i < count; i++) {
3096 if ((reg_arr[i] & 0xfffff000) != reg_base)
3099 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3100 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3104 static int bnxt_map_ptp_regs(struct bnxt *bp)
3106 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3110 reg_arr = ptp->rx_regs;
3111 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3115 reg_arr = ptp->tx_regs;
3116 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3120 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3121 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3123 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3124 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3129 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3131 rte_write32(0, (uint8_t *)bp->bar0 +
3132 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3133 rte_write32(0, (uint8_t *)bp->bar0 +
3134 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3137 static uint64_t bnxt_cc_read(struct bnxt *bp)
3141 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3142 BNXT_GRCPF_REG_SYNC_TIME));
3143 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3144 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3148 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3150 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3153 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3154 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3155 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3158 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3159 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3160 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3161 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3162 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3163 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3168 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3170 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3171 struct bnxt_pf_info *pf = &bp->pf;
3178 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3179 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3180 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3183 port_id = pf->port_id;
3184 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3185 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3187 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3188 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3189 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3190 /* bnxt_clr_rx_ts(bp); TBD */
3194 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3195 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3196 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3197 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3203 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3206 struct bnxt *bp = dev->data->dev_private;
3207 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3212 ns = rte_timespec_to_ns(ts);
3213 /* Set the timecounters to a new value. */
3220 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3222 struct bnxt *bp = dev->data->dev_private;
3223 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3224 uint64_t ns, systime_cycles = 0;
3230 if (BNXT_CHIP_THOR(bp))
3231 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3234 systime_cycles = bnxt_cc_read(bp);
3236 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3237 *ts = rte_ns_to_timespec(ns);
3242 bnxt_timesync_enable(struct rte_eth_dev *dev)
3244 struct bnxt *bp = dev->data->dev_private;
3245 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3253 ptp->tx_tstamp_en = 1;
3254 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3256 rc = bnxt_hwrm_ptp_cfg(bp);
3260 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3261 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3262 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3264 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3265 ptp->tc.cc_shift = shift;
3266 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3268 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3269 ptp->rx_tstamp_tc.cc_shift = shift;
3270 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3272 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3273 ptp->tx_tstamp_tc.cc_shift = shift;
3274 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3276 if (!BNXT_CHIP_THOR(bp))
3277 bnxt_map_ptp_regs(bp);
3283 bnxt_timesync_disable(struct rte_eth_dev *dev)
3285 struct bnxt *bp = dev->data->dev_private;
3286 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3292 ptp->tx_tstamp_en = 0;
3295 bnxt_hwrm_ptp_cfg(bp);
3297 if (!BNXT_CHIP_THOR(bp))
3298 bnxt_unmap_ptp_regs(bp);
3304 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3305 struct timespec *timestamp,
3306 uint32_t flags __rte_unused)
3308 struct bnxt *bp = dev->data->dev_private;
3309 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3310 uint64_t rx_tstamp_cycles = 0;
3316 if (BNXT_CHIP_THOR(bp))
3317 rx_tstamp_cycles = ptp->rx_timestamp;
3319 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3321 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3322 *timestamp = rte_ns_to_timespec(ns);
3327 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3328 struct timespec *timestamp)
3330 struct bnxt *bp = dev->data->dev_private;
3331 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3332 uint64_t tx_tstamp_cycles = 0;
3339 if (BNXT_CHIP_THOR(bp))
3340 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3343 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3345 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3346 *timestamp = rte_ns_to_timespec(ns);
3352 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3354 struct bnxt *bp = dev->data->dev_private;
3355 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3360 ptp->tc.nsec += delta;
3366 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3368 struct bnxt *bp = dev->data->dev_private;
3370 uint32_t dir_entries;
3371 uint32_t entry_length;
3373 rc = is_bnxt_in_error(bp);
3377 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3378 bp->pdev->addr.domain, bp->pdev->addr.bus,
3379 bp->pdev->addr.devid, bp->pdev->addr.function);
3381 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3385 return dir_entries * entry_length;
3389 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3390 struct rte_dev_eeprom_info *in_eeprom)
3392 struct bnxt *bp = dev->data->dev_private;
3397 rc = is_bnxt_in_error(bp);
3401 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3402 "len = %d\n", bp->pdev->addr.domain,
3403 bp->pdev->addr.bus, bp->pdev->addr.devid,
3404 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3406 if (in_eeprom->offset == 0) /* special offset value to get directory */
3407 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3410 index = in_eeprom->offset >> 24;
3411 offset = in_eeprom->offset & 0xffffff;
3414 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3415 in_eeprom->length, in_eeprom->data);
3420 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3423 case BNX_DIR_TYPE_CHIMP_PATCH:
3424 case BNX_DIR_TYPE_BOOTCODE:
3425 case BNX_DIR_TYPE_BOOTCODE_2:
3426 case BNX_DIR_TYPE_APE_FW:
3427 case BNX_DIR_TYPE_APE_PATCH:
3428 case BNX_DIR_TYPE_KONG_FW:
3429 case BNX_DIR_TYPE_KONG_PATCH:
3430 case BNX_DIR_TYPE_BONO_FW:
3431 case BNX_DIR_TYPE_BONO_PATCH:
3439 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3442 case BNX_DIR_TYPE_AVS:
3443 case BNX_DIR_TYPE_EXP_ROM_MBA:
3444 case BNX_DIR_TYPE_PCIE:
3445 case BNX_DIR_TYPE_TSCF_UCODE:
3446 case BNX_DIR_TYPE_EXT_PHY:
3447 case BNX_DIR_TYPE_CCM:
3448 case BNX_DIR_TYPE_ISCSI_BOOT:
3449 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3450 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3458 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3460 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3461 bnxt_dir_type_is_other_exec_format(dir_type);
3465 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3466 struct rte_dev_eeprom_info *in_eeprom)
3468 struct bnxt *bp = dev->data->dev_private;
3469 uint8_t index, dir_op;
3470 uint16_t type, ext, ordinal, attr;
3473 rc = is_bnxt_in_error(bp);
3477 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3478 "len = %d\n", bp->pdev->addr.domain,
3479 bp->pdev->addr.bus, bp->pdev->addr.devid,
3480 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3483 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3487 type = in_eeprom->magic >> 16;
3489 if (type == 0xffff) { /* special value for directory operations */
3490 index = in_eeprom->magic & 0xff;
3491 dir_op = in_eeprom->magic >> 8;
3495 case 0x0e: /* erase */
3496 if (in_eeprom->offset != ~in_eeprom->magic)
3498 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3504 /* Create or re-write an NVM item: */
3505 if (bnxt_dir_type_is_executable(type) == true)
3507 ext = in_eeprom->magic & 0xffff;
3508 ordinal = in_eeprom->offset >> 16;
3509 attr = in_eeprom->offset & 0xffff;
3511 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3512 in_eeprom->data, in_eeprom->length);
3519 static const struct eth_dev_ops bnxt_dev_ops = {
3520 .dev_infos_get = bnxt_dev_info_get_op,
3521 .dev_close = bnxt_dev_close_op,
3522 .dev_configure = bnxt_dev_configure_op,
3523 .dev_start = bnxt_dev_start_op,
3524 .dev_stop = bnxt_dev_stop_op,
3525 .dev_set_link_up = bnxt_dev_set_link_up_op,
3526 .dev_set_link_down = bnxt_dev_set_link_down_op,
3527 .stats_get = bnxt_stats_get_op,
3528 .stats_reset = bnxt_stats_reset_op,
3529 .rx_queue_setup = bnxt_rx_queue_setup_op,
3530 .rx_queue_release = bnxt_rx_queue_release_op,
3531 .tx_queue_setup = bnxt_tx_queue_setup_op,
3532 .tx_queue_release = bnxt_tx_queue_release_op,
3533 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3534 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3535 .reta_update = bnxt_reta_update_op,
3536 .reta_query = bnxt_reta_query_op,
3537 .rss_hash_update = bnxt_rss_hash_update_op,
3538 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3539 .link_update = bnxt_link_update_op,
3540 .promiscuous_enable = bnxt_promiscuous_enable_op,
3541 .promiscuous_disable = bnxt_promiscuous_disable_op,
3542 .allmulticast_enable = bnxt_allmulticast_enable_op,
3543 .allmulticast_disable = bnxt_allmulticast_disable_op,
3544 .mac_addr_add = bnxt_mac_addr_add_op,
3545 .mac_addr_remove = bnxt_mac_addr_remove_op,
3546 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3547 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3548 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3549 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3550 .vlan_filter_set = bnxt_vlan_filter_set_op,
3551 .vlan_offload_set = bnxt_vlan_offload_set_op,
3552 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3553 .mtu_set = bnxt_mtu_set_op,
3554 .mac_addr_set = bnxt_set_default_mac_addr_op,
3555 .xstats_get = bnxt_dev_xstats_get_op,
3556 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3557 .xstats_reset = bnxt_dev_xstats_reset_op,
3558 .fw_version_get = bnxt_fw_version_get,
3559 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3560 .rxq_info_get = bnxt_rxq_info_get_op,
3561 .txq_info_get = bnxt_txq_info_get_op,
3562 .dev_led_on = bnxt_dev_led_on_op,
3563 .dev_led_off = bnxt_dev_led_off_op,
3564 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3565 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3566 .rx_queue_count = bnxt_rx_queue_count_op,
3567 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3568 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3569 .rx_queue_start = bnxt_rx_queue_start,
3570 .rx_queue_stop = bnxt_rx_queue_stop,
3571 .tx_queue_start = bnxt_tx_queue_start,
3572 .tx_queue_stop = bnxt_tx_queue_stop,
3573 .filter_ctrl = bnxt_filter_ctrl_op,
3574 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3575 .get_eeprom_length = bnxt_get_eeprom_length_op,
3576 .get_eeprom = bnxt_get_eeprom_op,
3577 .set_eeprom = bnxt_set_eeprom_op,
3578 .timesync_enable = bnxt_timesync_enable,
3579 .timesync_disable = bnxt_timesync_disable,
3580 .timesync_read_time = bnxt_timesync_read_time,
3581 .timesync_write_time = bnxt_timesync_write_time,
3582 .timesync_adjust_time = bnxt_timesync_adjust_time,
3583 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3584 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3587 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3591 /* Only pre-map the reset GRC registers using window 3 */
3592 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3593 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3595 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3600 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3602 struct bnxt_error_recovery_info *info = bp->recovery_info;
3603 uint32_t reg_base = 0xffffffff;
3606 /* Only pre-map the monitoring GRC registers using window 2 */
3607 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3608 uint32_t reg = info->status_regs[i];
3610 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3613 if (reg_base == 0xffffffff)
3614 reg_base = reg & 0xfffff000;
3615 if ((reg & 0xfffff000) != reg_base)
3618 /* Use mask 0xffc as the Lower 2 bits indicates
3619 * address space location
3621 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3625 if (reg_base == 0xffffffff)
3628 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3629 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3634 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3636 struct bnxt_error_recovery_info *info = bp->recovery_info;
3637 uint32_t delay = info->delay_after_reset[index];
3638 uint32_t val = info->reset_reg_val[index];
3639 uint32_t reg = info->reset_reg[index];
3640 uint32_t type, offset;
3642 type = BNXT_FW_STATUS_REG_TYPE(reg);
3643 offset = BNXT_FW_STATUS_REG_OFF(reg);
3646 case BNXT_FW_STATUS_REG_TYPE_CFG:
3647 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3649 case BNXT_FW_STATUS_REG_TYPE_GRC:
3650 offset = bnxt_map_reset_regs(bp, offset);
3651 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3653 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3654 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3657 /* wait on a specific interval of time until core reset is complete */
3659 rte_delay_ms(delay);
3662 static void bnxt_dev_cleanup(struct bnxt *bp)
3664 bnxt_set_hwrm_link_config(bp, false);
3665 bp->link_info.link_up = 0;
3666 if (bp->dev_stopped == 0)
3667 bnxt_dev_stop_op(bp->eth_dev);
3669 bnxt_uninit_resources(bp, true);
3672 static int bnxt_restore_filters(struct bnxt *bp)
3674 struct rte_eth_dev *dev = bp->eth_dev;
3677 if (dev->data->all_multicast)
3678 ret = bnxt_allmulticast_enable_op(dev);
3679 if (dev->data->promiscuous)
3680 ret = bnxt_promiscuous_enable_op(dev);
3682 /* TODO restore other filters as well */
3686 static void bnxt_dev_recover(void *arg)
3688 struct bnxt *bp = arg;
3689 int timeout = bp->fw_reset_max_msecs;
3692 /* Clear Error flag so that device re-init should happen */
3693 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3696 rc = bnxt_hwrm_ver_get(bp);
3699 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3700 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3701 } while (rc && timeout);
3704 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3708 rc = bnxt_init_resources(bp, true);
3711 "Failed to initialize resources after reset\n");
3714 /* clear reset flag as the device is initialized now */
3715 bp->flags &= ~BNXT_FLAG_FW_RESET;
3717 rc = bnxt_dev_start_op(bp->eth_dev);
3719 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3723 rc = bnxt_restore_filters(bp);
3727 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3730 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3731 bnxt_uninit_resources(bp, false);
3732 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3735 void bnxt_dev_reset_and_resume(void *arg)
3737 struct bnxt *bp = arg;
3740 bnxt_dev_cleanup(bp);
3742 bnxt_wait_for_device_shutdown(bp);
3744 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3745 bnxt_dev_recover, (void *)bp);
3747 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3750 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3752 struct bnxt_error_recovery_info *info = bp->recovery_info;
3753 uint32_t reg = info->status_regs[index];
3754 uint32_t type, offset, val = 0;
3756 type = BNXT_FW_STATUS_REG_TYPE(reg);
3757 offset = BNXT_FW_STATUS_REG_OFF(reg);
3760 case BNXT_FW_STATUS_REG_TYPE_CFG:
3761 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3763 case BNXT_FW_STATUS_REG_TYPE_GRC:
3764 offset = info->mapped_status_regs[index];
3766 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3767 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3775 static int bnxt_fw_reset_all(struct bnxt *bp)
3777 struct bnxt_error_recovery_info *info = bp->recovery_info;
3781 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3782 /* Reset through master function driver */
3783 for (i = 0; i < info->reg_array_cnt; i++)
3784 bnxt_write_fw_reset_reg(bp, i);
3785 /* Wait for time specified by FW after triggering reset */
3786 rte_delay_ms(info->master_func_wait_period_after_reset);
3787 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3788 /* Reset with the help of Kong processor */
3789 rc = bnxt_hwrm_fw_reset(bp);
3791 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3797 static void bnxt_fw_reset_cb(void *arg)
3799 struct bnxt *bp = arg;
3800 struct bnxt_error_recovery_info *info = bp->recovery_info;
3803 /* Only Master function can do FW reset */
3804 if (bnxt_is_master_func(bp) &&
3805 bnxt_is_recovery_enabled(bp)) {
3806 rc = bnxt_fw_reset_all(bp);
3808 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3813 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3814 * EXCEPTION_FATAL_ASYNC event to all the functions
3815 * (including MASTER FUNC). After receiving this Async, all the active
3816 * drivers should treat this case as FW initiated recovery
3818 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3819 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3820 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3822 /* To recover from error */
3823 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3828 /* Driver should poll FW heartbeat, reset_counter with the frequency
3829 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3830 * When the driver detects heartbeat stop or change in reset_counter,
3831 * it has to trigger a reset to recover from the error condition.
3832 * A “master PF” is the function who will have the privilege to
3833 * initiate the chimp reset. The master PF will be elected by the
3834 * firmware and will be notified through async message.
3836 static void bnxt_check_fw_health(void *arg)
3838 struct bnxt *bp = arg;
3839 struct bnxt_error_recovery_info *info = bp->recovery_info;
3840 uint32_t val = 0, wait_msec;
3842 if (!info || !bnxt_is_recovery_enabled(bp) ||
3843 is_bnxt_in_error(bp))
3846 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3847 if (val == info->last_heart_beat)
3850 info->last_heart_beat = val;
3852 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3853 if (val != info->last_reset_counter)
3856 info->last_reset_counter = val;
3858 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3859 bnxt_check_fw_health, (void *)bp);
3863 /* Stop DMA to/from device */
3864 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3865 bp->flags |= BNXT_FLAG_FW_RESET;
3867 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3869 if (bnxt_is_master_func(bp))
3870 wait_msec = info->master_func_wait_period;
3872 wait_msec = info->normal_func_wait_period;
3874 rte_eal_alarm_set(US_PER_MS * wait_msec,
3875 bnxt_fw_reset_cb, (void *)bp);
3878 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3880 uint32_t polling_freq;
3882 if (!bnxt_is_recovery_enabled(bp))
3885 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
3888 polling_freq = bp->recovery_info->driver_polling_freq;
3890 rte_eal_alarm_set(US_PER_MS * polling_freq,
3891 bnxt_check_fw_health, (void *)bp);
3892 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3895 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
3897 if (!bnxt_is_recovery_enabled(bp))
3900 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
3901 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3904 static bool bnxt_vf_pciid(uint16_t id)
3906 if (id == BROADCOM_DEV_ID_57304_VF ||
3907 id == BROADCOM_DEV_ID_57406_VF ||
3908 id == BROADCOM_DEV_ID_5731X_VF ||
3909 id == BROADCOM_DEV_ID_5741X_VF ||
3910 id == BROADCOM_DEV_ID_57414_VF ||
3911 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3912 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3913 id == BROADCOM_DEV_ID_58802_VF ||
3914 id == BROADCOM_DEV_ID_57500_VF1 ||
3915 id == BROADCOM_DEV_ID_57500_VF2)
3920 bool bnxt_stratus_device(struct bnxt *bp)
3922 uint16_t id = bp->pdev->id.device_id;
3924 if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3925 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3926 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3931 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3933 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3934 struct bnxt *bp = eth_dev->data->dev_private;
3936 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3937 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3938 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3939 if (!bp->bar0 || !bp->doorbell_base) {
3940 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
3944 bp->eth_dev = eth_dev;
3950 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
3951 struct bnxt_ctx_pg_info *ctx_pg,
3956 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
3957 const struct rte_memzone *mz = NULL;
3958 char mz_name[RTE_MEMZONE_NAMESIZE];
3959 rte_iova_t mz_phys_addr;
3960 uint64_t valid_bits = 0;
3967 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
3969 rmem->page_size = BNXT_PAGE_SIZE;
3970 rmem->pg_arr = ctx_pg->ctx_pg_arr;
3971 rmem->dma_arr = ctx_pg->ctx_dma_arr;
3972 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
3974 valid_bits = PTU_PTE_VALID;
3976 if (rmem->nr_pages > 1) {
3977 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3978 "bnxt_ctx_pg_tbl%s_%x_%d",
3979 suffix, idx, bp->eth_dev->data->port_id);
3980 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3981 mz = rte_memzone_lookup(mz_name);
3983 mz = rte_memzone_reserve_aligned(mz_name,
3987 RTE_MEMZONE_SIZE_HINT_ONLY |
3988 RTE_MEMZONE_IOVA_CONTIG,
3994 memset(mz->addr, 0, mz->len);
3995 mz_phys_addr = mz->iova;
3996 if ((unsigned long)mz->addr == mz_phys_addr) {
3998 "physical address same as virtual\n");
3999 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4000 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4001 if (mz_phys_addr == RTE_BAD_IOVA) {
4003 "unable to map addr to phys memory\n");
4007 rte_mem_lock_page(((char *)mz->addr));
4009 rmem->pg_tbl = mz->addr;
4010 rmem->pg_tbl_map = mz_phys_addr;
4011 rmem->pg_tbl_mz = mz;
4014 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4015 suffix, idx, bp->eth_dev->data->port_id);
4016 mz = rte_memzone_lookup(mz_name);
4018 mz = rte_memzone_reserve_aligned(mz_name,
4022 RTE_MEMZONE_SIZE_HINT_ONLY |
4023 RTE_MEMZONE_IOVA_CONTIG,
4029 memset(mz->addr, 0, mz->len);
4030 mz_phys_addr = mz->iova;
4031 if ((unsigned long)mz->addr == mz_phys_addr) {
4033 "Memzone physical address same as virtual.\n");
4034 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4035 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4036 rte_mem_lock_page(((char *)mz->addr) + sz);
4037 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4038 if (mz_phys_addr == RTE_BAD_IOVA) {
4040 "unable to map addr to phys memory\n");
4045 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4046 rte_mem_lock_page(((char *)mz->addr) + sz);
4047 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4048 rmem->dma_arr[i] = mz_phys_addr + sz;
4050 if (rmem->nr_pages > 1) {
4051 if (i == rmem->nr_pages - 2 &&
4052 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4053 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4054 else if (i == rmem->nr_pages - 1 &&
4055 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4056 valid_bits |= PTU_PTE_LAST;
4058 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4064 if (rmem->vmem_size)
4065 rmem->vmem = (void **)mz->addr;
4066 rmem->dma_arr[0] = mz_phys_addr;
4070 static void bnxt_free_ctx_mem(struct bnxt *bp)
4074 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4077 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4078 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4079 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4080 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4081 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4082 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4083 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4084 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4085 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4086 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4087 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4089 for (i = 0; i < BNXT_MAX_Q; i++) {
4090 if (bp->ctx->tqm_mem[i])
4091 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4098 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4100 #define min_t(type, x, y) ({ \
4101 type __min1 = (x); \
4102 type __min2 = (y); \
4103 __min1 < __min2 ? __min1 : __min2; })
4105 #define max_t(type, x, y) ({ \
4106 type __max1 = (x); \
4107 type __max2 = (y); \
4108 __max1 > __max2 ? __max1 : __max2; })
4110 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4112 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4114 struct bnxt_ctx_pg_info *ctx_pg;
4115 struct bnxt_ctx_mem_info *ctx;
4116 uint32_t mem_size, ena, entries;
4119 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4121 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4125 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4128 ctx_pg = &ctx->qp_mem;
4129 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4130 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4131 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4135 ctx_pg = &ctx->srq_mem;
4136 ctx_pg->entries = ctx->srq_max_l2_entries;
4137 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4138 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4142 ctx_pg = &ctx->cq_mem;
4143 ctx_pg->entries = ctx->cq_max_l2_entries;
4144 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4145 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4149 ctx_pg = &ctx->vnic_mem;
4150 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4151 ctx->vnic_max_ring_table_entries;
4152 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4153 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4157 ctx_pg = &ctx->stat_mem;
4158 ctx_pg->entries = ctx->stat_max_entries;
4159 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4160 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4164 entries = ctx->qp_max_l2_entries;
4165 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4166 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4167 ctx->tqm_max_entries_per_ring);
4168 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4169 ctx_pg = ctx->tqm_mem[i];
4170 /* use min tqm entries for now. */
4171 ctx_pg->entries = entries;
4172 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4173 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4176 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4179 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4180 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4183 "Failed to configure context mem: rc = %d\n", rc);
4185 ctx->flags |= BNXT_CTX_FLAG_INITED;
4190 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4192 struct rte_pci_device *pci_dev = bp->pdev;
4193 char mz_name[RTE_MEMZONE_NAMESIZE];
4194 const struct rte_memzone *mz = NULL;
4195 uint32_t total_alloc_len;
4196 rte_iova_t mz_phys_addr;
4198 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4201 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4202 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4203 pci_dev->addr.bus, pci_dev->addr.devid,
4204 pci_dev->addr.function, "rx_port_stats");
4205 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4206 mz = rte_memzone_lookup(mz_name);
4208 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4209 sizeof(struct rx_port_stats_ext) + 512);
4211 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4214 RTE_MEMZONE_SIZE_HINT_ONLY |
4215 RTE_MEMZONE_IOVA_CONTIG);
4219 memset(mz->addr, 0, mz->len);
4220 mz_phys_addr = mz->iova;
4221 if ((unsigned long)mz->addr == mz_phys_addr) {
4223 "Memzone physical address same as virtual.\n");
4225 "Using rte_mem_virt2iova()\n");
4226 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4227 if (mz_phys_addr == RTE_BAD_IOVA) {
4229 "Can't map address to physical memory\n");
4234 bp->rx_mem_zone = (const void *)mz;
4235 bp->hw_rx_port_stats = mz->addr;
4236 bp->hw_rx_port_stats_map = mz_phys_addr;
4238 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4239 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4240 pci_dev->addr.bus, pci_dev->addr.devid,
4241 pci_dev->addr.function, "tx_port_stats");
4242 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4243 mz = rte_memzone_lookup(mz_name);
4245 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4246 sizeof(struct tx_port_stats_ext) + 512);
4248 mz = rte_memzone_reserve(mz_name,
4252 RTE_MEMZONE_SIZE_HINT_ONLY |
4253 RTE_MEMZONE_IOVA_CONTIG);
4257 memset(mz->addr, 0, mz->len);
4258 mz_phys_addr = mz->iova;
4259 if ((unsigned long)mz->addr == mz_phys_addr) {
4261 "Memzone physical address same as virtual\n");
4262 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4263 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4264 if (mz_phys_addr == RTE_BAD_IOVA) {
4266 "Can't map address to physical memory\n");
4271 bp->tx_mem_zone = (const void *)mz;
4272 bp->hw_tx_port_stats = mz->addr;
4273 bp->hw_tx_port_stats_map = mz_phys_addr;
4274 bp->flags |= BNXT_FLAG_PORT_STATS;
4276 /* Display extended statistics if FW supports it */
4277 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4278 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4279 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4282 bp->hw_rx_port_stats_ext = (void *)
4283 ((uint8_t *)bp->hw_rx_port_stats +
4284 sizeof(struct rx_port_stats));
4285 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4286 sizeof(struct rx_port_stats);
4287 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4289 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4290 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4291 bp->hw_tx_port_stats_ext = (void *)
4292 ((uint8_t *)bp->hw_tx_port_stats +
4293 sizeof(struct tx_port_stats));
4294 bp->hw_tx_port_stats_ext_map =
4295 bp->hw_tx_port_stats_map +
4296 sizeof(struct tx_port_stats);
4297 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4303 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4305 struct bnxt *bp = eth_dev->data->dev_private;
4308 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4309 RTE_ETHER_ADDR_LEN *
4312 if (eth_dev->data->mac_addrs == NULL) {
4313 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4317 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4321 /* Generate a random MAC address, if none was assigned by PF */
4322 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4323 bnxt_eth_hw_addr_random(bp->mac_addr);
4325 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4326 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4327 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4329 rc = bnxt_hwrm_set_mac(bp);
4331 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4332 RTE_ETHER_ADDR_LEN);
4336 /* Copy the permanent MAC from the FUNC_QCAPS response */
4337 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4338 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4343 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4347 /* MAC is already configured in FW */
4348 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4351 /* Restore the old MAC configured */
4352 rc = bnxt_hwrm_set_mac(bp);
4354 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4359 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4364 #define ALLOW_FUNC(x) \
4366 uint32_t arg = (x); \
4367 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4368 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4371 /* Forward all requests if firmware is new enough */
4372 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4373 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4374 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4375 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4377 PMD_DRV_LOG(WARNING,
4378 "Firmware too old for VF mailbox functionality\n");
4379 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4383 * The following are used for driver cleanup. If we disallow these,
4384 * VF drivers can't clean up cleanly.
4386 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4387 ALLOW_FUNC(HWRM_VNIC_FREE);
4388 ALLOW_FUNC(HWRM_RING_FREE);
4389 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4390 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4391 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4392 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4393 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4394 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4397 static int bnxt_init_fw(struct bnxt *bp)
4402 rc = bnxt_hwrm_ver_get(bp);
4406 rc = bnxt_hwrm_func_reset(bp);
4410 rc = bnxt_hwrm_queue_qportcfg(bp);
4414 /* Get the MAX capabilities for this function */
4415 rc = bnxt_hwrm_func_qcaps(bp);
4419 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4423 /* Get the adapter error recovery support info */
4424 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4426 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4428 if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4429 mtu != bp->eth_dev->data->mtu)
4430 bp->eth_dev->data->mtu = mtu;
4432 bnxt_hwrm_port_led_qcaps(bp);
4437 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4441 rc = bnxt_init_fw(bp);
4445 if (!reconfig_dev) {
4446 rc = bnxt_setup_mac_addr(bp->eth_dev);
4450 rc = bnxt_restore_dflt_mac(bp);
4455 bnxt_config_vf_req_fwd(bp);
4457 rc = bnxt_hwrm_func_driver_register(bp);
4459 PMD_DRV_LOG(ERR, "Failed to register driver");
4464 if (bp->pdev->max_vfs) {
4465 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4467 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4471 rc = bnxt_hwrm_allocate_pf_only(bp);
4474 "Failed to allocate PF resources");
4480 rc = bnxt_alloc_mem(bp, reconfig_dev);
4484 rc = bnxt_setup_int(bp);
4490 rc = bnxt_request_int(bp);
4498 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4500 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4501 static int version_printed;
4505 if (version_printed++ == 0)
4506 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4508 rte_eth_copy_pci_info(eth_dev, pci_dev);
4510 bp = eth_dev->data->dev_private;
4512 bp->dev_stopped = 1;
4514 eth_dev->dev_ops = &bnxt_dev_ops;
4515 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4516 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4519 * For secondary processes, we don't initialise any further
4520 * as primary has already done this work.
4522 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4525 if (bnxt_vf_pciid(pci_dev->id.device_id))
4526 bp->flags |= BNXT_FLAG_VF;
4528 if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4529 pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4530 pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4531 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4532 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4533 bp->flags |= BNXT_FLAG_THOR_CHIP;
4535 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4536 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4537 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4538 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4539 bp->flags |= BNXT_FLAG_STINGRAY;
4541 rc = bnxt_init_board(eth_dev);
4544 "Failed to initialize board rc: %x\n", rc);
4548 rc = bnxt_alloc_hwrm_resources(bp);
4551 "Failed to allocate hwrm resource rc: %x\n", rc);
4554 rc = bnxt_init_resources(bp, false);
4558 rc = bnxt_alloc_stats_mem(bp);
4563 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4564 pci_dev->mem_resource[0].phys_addr,
4565 pci_dev->mem_resource[0].addr);
4570 bnxt_dev_uninit(eth_dev);
4575 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4580 bnxt_free_mem(bp, reconfig_dev);
4581 bnxt_hwrm_func_buf_unrgtr(bp);
4582 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4583 bp->flags &= ~BNXT_FLAG_REGISTERED;
4584 bnxt_free_ctx_mem(bp);
4585 if (!reconfig_dev) {
4586 bnxt_free_hwrm_resources(bp);
4588 if (bp->recovery_info != NULL) {
4589 rte_free(bp->recovery_info);
4590 bp->recovery_info = NULL;
4594 rte_free(bp->ptp_cfg);
4600 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4602 struct bnxt *bp = eth_dev->data->dev_private;
4605 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4608 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4610 rc = bnxt_uninit_resources(bp, false);
4612 if (bp->grp_info != NULL) {
4613 rte_free(bp->grp_info);
4614 bp->grp_info = NULL;
4617 if (bp->tx_mem_zone) {
4618 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4619 bp->tx_mem_zone = NULL;
4622 if (bp->rx_mem_zone) {
4623 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4624 bp->rx_mem_zone = NULL;
4627 if (bp->dev_stopped == 0)
4628 bnxt_dev_close_op(eth_dev);
4630 rte_free(bp->pf.vf_info);
4631 eth_dev->dev_ops = NULL;
4632 eth_dev->rx_pkt_burst = NULL;
4633 eth_dev->tx_pkt_burst = NULL;
4638 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4639 struct rte_pci_device *pci_dev)
4641 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4645 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4647 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4648 return rte_eth_dev_pci_generic_remove(pci_dev,
4651 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4654 static struct rte_pci_driver bnxt_rte_pmd = {
4655 .id_table = bnxt_pci_id_map,
4656 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4657 .probe = bnxt_pci_probe,
4658 .remove = bnxt_pci_remove,
4662 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4664 if (strcmp(dev->device->driver->name, drv->driver.name))
4670 bool is_bnxt_supported(struct rte_eth_dev *dev)
4672 return is_device_supported(dev, &bnxt_rte_pmd);
4675 RTE_INIT(bnxt_init_log)
4677 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4678 if (bnxt_logtype_driver >= 0)
4679 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4682 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4683 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4684 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");