1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
30 #define DRV_MODULE_NAME "bnxt"
31 static const char bnxt_version[] =
32 "Broadcom NetXtreme driver " DRV_MODULE_NAME "\n";
33 int bnxt_logtype_driver;
35 #define PCI_VENDOR_ID_BROADCOM 0x14E4
37 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
39 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
40 #define BROADCOM_DEV_ID_57414_VF 0x16c1
41 #define BROADCOM_DEV_ID_57301 0x16c8
42 #define BROADCOM_DEV_ID_57302 0x16c9
43 #define BROADCOM_DEV_ID_57304_PF 0x16ca
44 #define BROADCOM_DEV_ID_57304_VF 0x16cb
45 #define BROADCOM_DEV_ID_57417_MF 0x16cc
46 #define BROADCOM_DEV_ID_NS2 0x16cd
47 #define BROADCOM_DEV_ID_57311 0x16ce
48 #define BROADCOM_DEV_ID_57312 0x16cf
49 #define BROADCOM_DEV_ID_57402 0x16d0
50 #define BROADCOM_DEV_ID_57404 0x16d1
51 #define BROADCOM_DEV_ID_57406_PF 0x16d2
52 #define BROADCOM_DEV_ID_57406_VF 0x16d3
53 #define BROADCOM_DEV_ID_57402_MF 0x16d4
54 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
55 #define BROADCOM_DEV_ID_57412 0x16d6
56 #define BROADCOM_DEV_ID_57414 0x16d7
57 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
58 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
59 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
60 #define BROADCOM_DEV_ID_57412_MF 0x16de
61 #define BROADCOM_DEV_ID_57314 0x16df
62 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
63 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
64 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
65 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
66 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
67 #define BROADCOM_DEV_ID_57404_MF 0x16e7
68 #define BROADCOM_DEV_ID_57406_MF 0x16e8
69 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
70 #define BROADCOM_DEV_ID_57407_MF 0x16ea
71 #define BROADCOM_DEV_ID_57414_MF 0x16ec
72 #define BROADCOM_DEV_ID_57416_MF 0x16ee
73 #define BROADCOM_DEV_ID_58802 0xd802
74 #define BROADCOM_DEV_ID_58804 0xd804
75 #define BROADCOM_DEV_ID_58808 0x16f0
77 static const struct rte_pci_id bnxt_pci_id_map[] = {
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
79 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
81 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
119 { .vendor_id = 0, /* sentinel */ },
122 #define BNXT_ETH_RSS_SUPPORT ( \
124 ETH_RSS_NONFRAG_IPV4_TCP | \
125 ETH_RSS_NONFRAG_IPV4_UDP | \
127 ETH_RSS_NONFRAG_IPV6_TCP | \
128 ETH_RSS_NONFRAG_IPV6_UDP)
130 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
131 DEV_TX_OFFLOAD_IPV4_CKSUM | \
132 DEV_TX_OFFLOAD_TCP_CKSUM | \
133 DEV_TX_OFFLOAD_UDP_CKSUM | \
134 DEV_TX_OFFLOAD_TCP_TSO | \
135 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
136 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
137 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
138 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
139 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
140 DEV_TX_OFFLOAD_MULTI_SEGS)
142 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
143 DEV_RX_OFFLOAD_VLAN_STRIP | \
144 DEV_RX_OFFLOAD_IPV4_CKSUM | \
145 DEV_RX_OFFLOAD_UDP_CKSUM | \
146 DEV_RX_OFFLOAD_TCP_CKSUM | \
147 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
148 DEV_RX_OFFLOAD_JUMBO_FRAME | \
149 DEV_RX_OFFLOAD_CRC_STRIP | \
150 DEV_RX_OFFLOAD_KEEP_CRC | \
151 DEV_RX_OFFLOAD_TCP_LRO)
153 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
154 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
155 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
157 /***********************/
160 * High level utility functions
163 static void bnxt_free_mem(struct bnxt *bp)
165 bnxt_free_filter_mem(bp);
166 bnxt_free_vnic_attributes(bp);
167 bnxt_free_vnic_mem(bp);
170 bnxt_free_tx_rings(bp);
171 bnxt_free_rx_rings(bp);
174 static int bnxt_alloc_mem(struct bnxt *bp)
178 rc = bnxt_alloc_vnic_mem(bp);
182 rc = bnxt_alloc_vnic_attributes(bp);
186 rc = bnxt_alloc_filter_mem(bp);
197 static int bnxt_init_chip(struct bnxt *bp)
200 struct rte_eth_link new;
201 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
202 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
203 uint32_t intr_vector = 0;
204 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
205 uint32_t vec = BNXT_MISC_VEC_ID;
208 /* disable uio/vfio intr/eventfd mapping */
209 rte_intr_disable(intr_handle);
211 if (bp->eth_dev->data->mtu > ETHER_MTU) {
212 bp->eth_dev->data->dev_conf.rxmode.offloads |=
213 DEV_RX_OFFLOAD_JUMBO_FRAME;
214 bp->flags |= BNXT_FLAG_JUMBO;
216 bp->eth_dev->data->dev_conf.rxmode.offloads &=
217 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
218 bp->flags &= ~BNXT_FLAG_JUMBO;
221 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
223 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
227 rc = bnxt_alloc_hwrm_rings(bp);
229 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
233 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
235 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
239 rc = bnxt_mq_rx_configure(bp);
241 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
245 /* VNIC configuration */
246 for (i = 0; i < bp->nr_vnics; i++) {
247 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
249 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
251 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
256 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
259 "HWRM vnic %d ctx alloc failure rc: %x\n",
264 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
266 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
271 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
274 "HWRM vnic %d filter failure rc: %x\n",
279 rc = bnxt_vnic_rss_configure(bp, vnic);
282 "HWRM vnic set RSS failure rc: %x\n", rc);
286 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
288 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
289 DEV_RX_OFFLOAD_TCP_LRO)
290 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
292 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
294 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
297 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
301 /* check and configure queue intr-vector mapping */
302 if ((rte_intr_cap_multiple(intr_handle) ||
303 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
304 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
305 intr_vector = bp->eth_dev->data->nb_rx_queues;
306 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
307 if (intr_vector > bp->rx_cp_nr_rings) {
308 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
312 if (rte_intr_efd_enable(intr_handle, intr_vector))
316 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
317 intr_handle->intr_vec =
318 rte_zmalloc("intr_vec",
319 bp->eth_dev->data->nb_rx_queues *
321 if (intr_handle->intr_vec == NULL) {
322 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
323 " intr_vec", bp->eth_dev->data->nb_rx_queues);
326 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
327 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
328 intr_handle->intr_vec, intr_handle->nb_efd,
329 intr_handle->max_intr);
332 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
334 intr_handle->intr_vec[queue_id] = vec;
335 if (vec < base + intr_handle->nb_efd - 1)
339 /* enable uio/vfio intr/eventfd mapping */
340 rte_intr_enable(intr_handle);
342 rc = bnxt_get_hwrm_link_config(bp, &new);
344 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
348 if (!bp->link_info.link_up) {
349 rc = bnxt_set_hwrm_link_config(bp, true);
352 "HWRM link config failure rc: %x\n", rc);
356 bnxt_print_link_info(bp->eth_dev);
361 bnxt_free_all_hwrm_resources(bp);
363 /* Some of the error status returned by FW may not be from errno.h */
370 static int bnxt_shutdown_nic(struct bnxt *bp)
372 bnxt_free_all_hwrm_resources(bp);
373 bnxt_free_all_filters(bp);
374 bnxt_free_all_vnics(bp);
378 static int bnxt_init_nic(struct bnxt *bp)
382 rc = bnxt_init_ring_grps(bp);
387 bnxt_init_filters(bp);
393 * Device configuration and status function
396 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
397 struct rte_eth_dev_info *dev_info)
399 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
400 uint16_t max_vnics, i, j, vpool, vrxq;
401 unsigned int max_rx_rings;
404 dev_info->max_mac_addrs = bp->max_l2_ctx;
405 dev_info->max_hash_mac_addrs = 0;
407 /* PF/VF specifics */
409 dev_info->max_vfs = bp->pdev->max_vfs;
410 max_rx_rings = RTE_MIN(bp->max_vnics, bp->max_stat_ctx);
411 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
412 dev_info->max_rx_queues = max_rx_rings;
413 dev_info->max_tx_queues = max_rx_rings;
414 dev_info->reta_size = bp->max_rsscos_ctx;
415 dev_info->hash_key_size = 40;
416 max_vnics = bp->max_vnics;
418 /* Fast path specifics */
419 dev_info->min_rx_bufsize = 1;
420 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
423 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
424 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
425 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
426 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
427 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
430 dev_info->default_rxconf = (struct rte_eth_rxconf) {
436 .rx_free_thresh = 32,
437 /* If no descriptors available, pkts are dropped by default */
441 dev_info->default_txconf = (struct rte_eth_txconf) {
447 .tx_free_thresh = 32,
450 eth_dev->data->dev_conf.intr_conf.lsc = 1;
452 eth_dev->data->dev_conf.intr_conf.rxq = 1;
453 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
454 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
455 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
456 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
461 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
462 * need further investigation.
466 vpool = 64; /* ETH_64_POOLS */
467 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
468 for (i = 0; i < 4; vpool >>= 1, i++) {
469 if (max_vnics > vpool) {
470 for (j = 0; j < 5; vrxq >>= 1, j++) {
471 if (dev_info->max_rx_queues > vrxq) {
477 /* Not enough resources to support VMDq */
481 /* Not enough resources to support VMDq */
485 dev_info->max_vmdq_pools = vpool;
486 dev_info->vmdq_queue_num = vrxq;
488 dev_info->vmdq_pool_base = 0;
489 dev_info->vmdq_queue_base = 0;
492 /* Configure the device based on the configuration provided */
493 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
495 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
496 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
498 bp->rx_queues = (void *)eth_dev->data->rx_queues;
499 bp->tx_queues = (void *)eth_dev->data->tx_queues;
500 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
501 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
503 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
506 rc = bnxt_hwrm_func_reserve_vf_resc(bp);
508 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
512 /* legacy driver needs to get updated values */
513 rc = bnxt_hwrm_func_qcaps(bp);
515 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
520 /* Inherit new configurations */
521 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
522 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
523 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
525 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
527 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) {
529 "Insufficient resources to support requested config\n");
531 "Num Queues Requested: Tx %d, Rx %d\n",
532 eth_dev->data->nb_tx_queues,
533 eth_dev->data->nb_rx_queues);
535 "Res available: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d\n",
536 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
537 bp->max_stat_ctx, bp->max_ring_grps);
541 bp->rx_cp_nr_rings = bp->rx_nr_rings;
542 bp->tx_cp_nr_rings = bp->tx_nr_rings;
544 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
546 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
547 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE *
549 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
554 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
556 struct rte_eth_link *link = ð_dev->data->dev_link;
558 if (link->link_status)
559 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
560 eth_dev->data->port_id,
561 (uint32_t)link->link_speed,
562 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
563 ("full-duplex") : ("half-duplex\n"));
565 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
566 eth_dev->data->port_id);
569 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
571 bnxt_print_link_info(eth_dev);
575 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
577 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
578 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
582 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
584 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
585 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
589 rc = bnxt_init_chip(bp);
593 bnxt_link_update_op(eth_dev, 1);
595 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
596 vlan_mask |= ETH_VLAN_FILTER_MASK;
597 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
598 vlan_mask |= ETH_VLAN_STRIP_MASK;
599 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
603 bp->flags |= BNXT_FLAG_INIT_DONE;
607 bnxt_shutdown_nic(bp);
608 bnxt_free_tx_mbufs(bp);
609 bnxt_free_rx_mbufs(bp);
613 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
615 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
618 if (!bp->link_info.link_up)
619 rc = bnxt_set_hwrm_link_config(bp, true);
621 eth_dev->data->dev_link.link_status = 1;
623 bnxt_print_link_info(eth_dev);
627 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
629 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
631 eth_dev->data->dev_link.link_status = 0;
632 bnxt_set_hwrm_link_config(bp, false);
633 bp->link_info.link_up = 0;
638 /* Unload the driver, release resources */
639 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
641 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
643 bp->flags &= ~BNXT_FLAG_INIT_DONE;
644 if (bp->eth_dev->data->dev_started) {
645 /* TBD: STOP HW queues DMA */
646 eth_dev->data->dev_link.link_status = 0;
648 bnxt_set_hwrm_link_config(bp, false);
649 bnxt_hwrm_port_clr_stats(bp);
650 bnxt_free_tx_mbufs(bp);
651 bnxt_free_rx_mbufs(bp);
652 bnxt_shutdown_nic(bp);
656 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
658 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
660 if (bp->dev_stopped == 0)
661 bnxt_dev_stop_op(eth_dev);
664 if (eth_dev->data->mac_addrs != NULL) {
665 rte_free(eth_dev->data->mac_addrs);
666 eth_dev->data->mac_addrs = NULL;
668 if (bp->grp_info != NULL) {
669 rte_free(bp->grp_info);
674 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
677 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
678 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
679 struct bnxt_vnic_info *vnic;
680 struct bnxt_filter_info *filter, *temp_filter;
681 uint32_t pool = RTE_MIN(MAX_FF_POOLS, ETH_64_POOLS);
685 * Loop through all VNICs from the specified filter flow pools to
686 * remove the corresponding MAC addr filter
688 for (i = 0; i < pool; i++) {
689 if (!(pool_mask & (1ULL << i)))
692 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
693 filter = STAILQ_FIRST(&vnic->filter);
695 temp_filter = STAILQ_NEXT(filter, next);
696 if (filter->mac_index == index) {
697 STAILQ_REMOVE(&vnic->filter, filter,
698 bnxt_filter_info, next);
699 bnxt_hwrm_clear_l2_filter(bp, filter);
700 filter->mac_index = INVALID_MAC_INDEX;
701 memset(&filter->l2_addr, 0,
704 &bp->free_filter_list,
707 filter = temp_filter;
713 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
714 struct ether_addr *mac_addr,
715 uint32_t index, uint32_t pool)
717 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
718 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
719 struct bnxt_filter_info *filter;
722 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
727 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
730 /* Attach requested MAC address to the new l2_filter */
731 STAILQ_FOREACH(filter, &vnic->filter, next) {
732 if (filter->mac_index == index) {
734 "MAC addr already existed for pool %d\n", pool);
738 filter = bnxt_alloc_filter(bp);
740 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
743 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
744 filter->mac_index = index;
745 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
746 return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
749 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
752 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
753 struct rte_eth_link new;
754 unsigned int cnt = BNXT_LINK_WAIT_CNT;
756 memset(&new, 0, sizeof(new));
758 /* Retrieve link info from hardware */
759 rc = bnxt_get_hwrm_link_config(bp, &new);
761 new.link_speed = ETH_LINK_SPEED_100M;
762 new.link_duplex = ETH_LINK_FULL_DUPLEX;
764 "Failed to retrieve link rc = 0x%x!\n", rc);
767 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
769 if (!wait_to_complete)
771 } while (!new.link_status && cnt--);
774 /* Timed out or success */
775 if (new.link_status != eth_dev->data->dev_link.link_status ||
776 new.link_speed != eth_dev->data->dev_link.link_speed) {
777 memcpy(ð_dev->data->dev_link, &new,
778 sizeof(struct rte_eth_link));
780 _rte_eth_dev_callback_process(eth_dev,
781 RTE_ETH_EVENT_INTR_LSC,
784 bnxt_print_link_info(eth_dev);
790 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
792 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
793 struct bnxt_vnic_info *vnic;
795 if (bp->vnic_info == NULL)
798 vnic = &bp->vnic_info[0];
800 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
801 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
804 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
806 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
807 struct bnxt_vnic_info *vnic;
809 if (bp->vnic_info == NULL)
812 vnic = &bp->vnic_info[0];
814 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
815 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
818 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
820 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
821 struct bnxt_vnic_info *vnic;
823 if (bp->vnic_info == NULL)
826 vnic = &bp->vnic_info[0];
828 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
829 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
832 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
834 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
835 struct bnxt_vnic_info *vnic;
837 if (bp->vnic_info == NULL)
840 vnic = &bp->vnic_info[0];
842 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
843 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
846 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
847 struct rte_eth_rss_reta_entry64 *reta_conf,
850 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
851 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
852 struct bnxt_vnic_info *vnic;
855 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
858 if (reta_size != HW_HASH_INDEX_SIZE) {
859 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
860 "(%d) must equal the size supported by the hardware "
861 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
864 /* Update the RSS VNIC(s) */
865 for (i = 0; i < MAX_FF_POOLS; i++) {
866 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
867 memcpy(vnic->rss_table, reta_conf, reta_size);
869 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
875 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
876 struct rte_eth_rss_reta_entry64 *reta_conf,
879 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
880 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
881 struct rte_intr_handle *intr_handle
882 = &bp->pdev->intr_handle;
884 /* Retrieve from the default VNIC */
887 if (!vnic->rss_table)
890 if (reta_size != HW_HASH_INDEX_SIZE) {
891 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
892 "(%d) must equal the size supported by the hardware "
893 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
896 /* EW - need to revisit here copying from uint64_t to uint16_t */
897 memcpy(reta_conf, vnic->rss_table, reta_size);
899 if (rte_intr_allow_others(intr_handle)) {
900 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
901 bnxt_dev_lsc_intr_setup(eth_dev);
907 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
908 struct rte_eth_rss_conf *rss_conf)
910 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
911 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
912 struct bnxt_vnic_info *vnic;
913 uint16_t hash_type = 0;
917 * If RSS enablement were different than dev_configure,
918 * then return -EINVAL
920 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
921 if (!rss_conf->rss_hf)
922 PMD_DRV_LOG(ERR, "Hash type NONE\n");
924 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
928 bp->flags |= BNXT_FLAG_UPDATE_HASH;
929 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
931 if (rss_conf->rss_hf & ETH_RSS_IPV4)
932 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
933 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
934 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
935 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
936 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
937 if (rss_conf->rss_hf & ETH_RSS_IPV6)
938 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
939 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
940 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
941 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
942 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
944 /* Update the RSS VNIC(s) */
945 for (i = 0; i < MAX_FF_POOLS; i++) {
946 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
947 vnic->hash_type = hash_type;
950 * Use the supplied key if the key length is
951 * acceptable and the rss_key is not NULL
953 if (rss_conf->rss_key &&
954 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
955 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
956 rss_conf->rss_key_len);
958 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
964 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
965 struct rte_eth_rss_conf *rss_conf)
967 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
968 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
972 /* RSS configuration is the same for all VNICs */
973 if (vnic && vnic->rss_hash_key) {
974 if (rss_conf->rss_key) {
975 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
976 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
977 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
980 hash_types = vnic->hash_type;
981 rss_conf->rss_hf = 0;
982 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
983 rss_conf->rss_hf |= ETH_RSS_IPV4;
984 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
986 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
987 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
989 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
991 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
992 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
994 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
996 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
997 rss_conf->rss_hf |= ETH_RSS_IPV6;
998 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1000 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1001 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1003 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1005 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1006 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1008 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1012 "Unknwon RSS config from firmware (%08x), RSS disabled",
1017 rss_conf->rss_hf = 0;
1022 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1023 struct rte_eth_fc_conf *fc_conf)
1025 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1026 struct rte_eth_link link_info;
1029 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1033 memset(fc_conf, 0, sizeof(*fc_conf));
1034 if (bp->link_info.auto_pause)
1035 fc_conf->autoneg = 1;
1036 switch (bp->link_info.pause) {
1038 fc_conf->mode = RTE_FC_NONE;
1040 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1041 fc_conf->mode = RTE_FC_TX_PAUSE;
1043 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1044 fc_conf->mode = RTE_FC_RX_PAUSE;
1046 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1047 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1048 fc_conf->mode = RTE_FC_FULL;
1054 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1055 struct rte_eth_fc_conf *fc_conf)
1057 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1059 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1060 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1064 switch (fc_conf->mode) {
1066 bp->link_info.auto_pause = 0;
1067 bp->link_info.force_pause = 0;
1069 case RTE_FC_RX_PAUSE:
1070 if (fc_conf->autoneg) {
1071 bp->link_info.auto_pause =
1072 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1073 bp->link_info.force_pause = 0;
1075 bp->link_info.auto_pause = 0;
1076 bp->link_info.force_pause =
1077 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1080 case RTE_FC_TX_PAUSE:
1081 if (fc_conf->autoneg) {
1082 bp->link_info.auto_pause =
1083 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1084 bp->link_info.force_pause = 0;
1086 bp->link_info.auto_pause = 0;
1087 bp->link_info.force_pause =
1088 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1092 if (fc_conf->autoneg) {
1093 bp->link_info.auto_pause =
1094 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1095 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1096 bp->link_info.force_pause = 0;
1098 bp->link_info.auto_pause = 0;
1099 bp->link_info.force_pause =
1100 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1101 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1105 return bnxt_set_hwrm_link_config(bp, true);
1108 /* Add UDP tunneling port */
1110 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1111 struct rte_eth_udp_tunnel *udp_tunnel)
1113 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1114 uint16_t tunnel_type = 0;
1117 switch (udp_tunnel->prot_type) {
1118 case RTE_TUNNEL_TYPE_VXLAN:
1119 if (bp->vxlan_port_cnt) {
1120 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1121 udp_tunnel->udp_port);
1122 if (bp->vxlan_port != udp_tunnel->udp_port) {
1123 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1126 bp->vxlan_port_cnt++;
1130 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1131 bp->vxlan_port_cnt++;
1133 case RTE_TUNNEL_TYPE_GENEVE:
1134 if (bp->geneve_port_cnt) {
1135 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1136 udp_tunnel->udp_port);
1137 if (bp->geneve_port != udp_tunnel->udp_port) {
1138 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1141 bp->geneve_port_cnt++;
1145 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1146 bp->geneve_port_cnt++;
1149 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1152 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1158 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1159 struct rte_eth_udp_tunnel *udp_tunnel)
1161 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1162 uint16_t tunnel_type = 0;
1166 switch (udp_tunnel->prot_type) {
1167 case RTE_TUNNEL_TYPE_VXLAN:
1168 if (!bp->vxlan_port_cnt) {
1169 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1172 if (bp->vxlan_port != udp_tunnel->udp_port) {
1173 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1174 udp_tunnel->udp_port, bp->vxlan_port);
1177 if (--bp->vxlan_port_cnt)
1181 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1182 port = bp->vxlan_fw_dst_port_id;
1184 case RTE_TUNNEL_TYPE_GENEVE:
1185 if (!bp->geneve_port_cnt) {
1186 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1189 if (bp->geneve_port != udp_tunnel->udp_port) {
1190 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1191 udp_tunnel->udp_port, bp->geneve_port);
1194 if (--bp->geneve_port_cnt)
1198 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1199 port = bp->geneve_fw_dst_port_id;
1202 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1206 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1209 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1212 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1213 bp->geneve_port = 0;
1218 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1220 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1221 struct bnxt_vnic_info *vnic;
1224 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1226 /* Cycle through all VNICs */
1227 for (i = 0; i < bp->nr_vnics; i++) {
1229 * For each VNIC and each associated filter(s)
1230 * if VLAN exists && VLAN matches vlan_id
1231 * remove the MAC+VLAN filter
1232 * add a new MAC only filter
1234 * VLAN filter doesn't exist, just skip and continue
1236 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1237 filter = STAILQ_FIRST(&vnic->filter);
1239 temp_filter = STAILQ_NEXT(filter, next);
1241 if (filter->enables & chk &&
1242 filter->l2_ovlan == vlan_id) {
1243 /* Must delete the filter */
1244 STAILQ_REMOVE(&vnic->filter, filter,
1245 bnxt_filter_info, next);
1246 bnxt_hwrm_clear_l2_filter(bp, filter);
1248 &bp->free_filter_list,
1252 * Need to examine to see if the MAC
1253 * filter already existed or not before
1254 * allocating a new one
1257 new_filter = bnxt_alloc_filter(bp);
1260 "MAC/VLAN filter alloc failed\n");
1264 STAILQ_INSERT_TAIL(&vnic->filter,
1266 /* Inherit MAC from previous filter */
1267 new_filter->mac_index =
1269 memcpy(new_filter->l2_addr,
1270 filter->l2_addr, ETHER_ADDR_LEN);
1271 /* MAC only filter */
1272 rc = bnxt_hwrm_set_l2_filter(bp,
1278 "Del Vlan filter for %d\n",
1281 filter = temp_filter;
1289 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1291 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1292 struct bnxt_vnic_info *vnic;
1295 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN |
1296 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK;
1297 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1299 /* Cycle through all VNICs */
1300 for (i = 0; i < bp->nr_vnics; i++) {
1302 * For each VNIC and each associated filter(s)
1304 * if VLAN matches vlan_id
1305 * VLAN filter already exists, just skip and continue
1307 * add a new MAC+VLAN filter
1309 * Remove the old MAC only filter
1310 * Add a new MAC+VLAN filter
1312 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1313 filter = STAILQ_FIRST(&vnic->filter);
1315 temp_filter = STAILQ_NEXT(filter, next);
1317 if (filter->enables & chk) {
1318 if (filter->l2_ovlan == vlan_id)
1321 /* Must delete the MAC filter */
1322 STAILQ_REMOVE(&vnic->filter, filter,
1323 bnxt_filter_info, next);
1324 bnxt_hwrm_clear_l2_filter(bp, filter);
1325 filter->l2_ovlan = 0;
1327 &bp->free_filter_list,
1330 new_filter = bnxt_alloc_filter(bp);
1333 "MAC/VLAN filter alloc failed\n");
1337 STAILQ_INSERT_TAIL(&vnic->filter, new_filter,
1339 /* Inherit MAC from the previous filter */
1340 new_filter->mac_index = filter->mac_index;
1341 memcpy(new_filter->l2_addr, filter->l2_addr,
1343 /* MAC + VLAN ID filter */
1344 new_filter->l2_ovlan = vlan_id;
1345 new_filter->l2_ovlan_mask = 0xF000;
1346 new_filter->enables |= en;
1347 rc = bnxt_hwrm_set_l2_filter(bp,
1353 "Added Vlan filter for %d\n", vlan_id);
1355 filter = temp_filter;
1363 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1364 uint16_t vlan_id, int on)
1366 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1368 /* These operations apply to ALL existing MAC/VLAN filters */
1370 return bnxt_add_vlan_filter(bp, vlan_id);
1372 return bnxt_del_vlan_filter(bp, vlan_id);
1376 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1378 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1379 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1382 if (mask & ETH_VLAN_FILTER_MASK) {
1383 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1384 /* Remove any VLAN filters programmed */
1385 for (i = 0; i < 4095; i++)
1386 bnxt_del_vlan_filter(bp, i);
1388 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1389 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1392 if (mask & ETH_VLAN_STRIP_MASK) {
1393 /* Enable or disable VLAN stripping */
1394 for (i = 0; i < bp->nr_vnics; i++) {
1395 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1396 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1397 vnic->vlan_strip = true;
1399 vnic->vlan_strip = false;
1400 bnxt_hwrm_vnic_cfg(bp, vnic);
1402 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1403 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1406 if (mask & ETH_VLAN_EXTEND_MASK)
1407 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1413 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr)
1415 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1416 /* Default Filter is tied to VNIC 0 */
1417 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1418 struct bnxt_filter_info *filter;
1424 memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1426 STAILQ_FOREACH(filter, &vnic->filter, next) {
1427 /* Default Filter is at Index 0 */
1428 if (filter->mac_index != 0)
1430 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1433 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN);
1434 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN);
1435 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1437 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1438 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1439 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1442 filter->mac_index = 0;
1443 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1450 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1451 struct ether_addr *mc_addr_set,
1452 uint32_t nb_mc_addr)
1454 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1455 char *mc_addr_list = (char *)mc_addr_set;
1456 struct bnxt_vnic_info *vnic;
1457 uint32_t off = 0, i = 0;
1459 vnic = &bp->vnic_info[0];
1461 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1462 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1466 /* TODO Check for Duplicate mcast addresses */
1467 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1468 for (i = 0; i < nb_mc_addr; i++) {
1469 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN);
1470 off += ETHER_ADDR_LEN;
1473 vnic->mc_addr_cnt = i;
1476 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1480 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1482 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1483 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1484 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1485 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1488 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1489 fw_major, fw_minor, fw_updt);
1491 ret += 1; /* add the size of '\0' */
1492 if (fw_size < (uint32_t)ret)
1499 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1500 struct rte_eth_rxq_info *qinfo)
1502 struct bnxt_rx_queue *rxq;
1504 rxq = dev->data->rx_queues[queue_id];
1506 qinfo->mp = rxq->mb_pool;
1507 qinfo->scattered_rx = dev->data->scattered_rx;
1508 qinfo->nb_desc = rxq->nb_rx_desc;
1510 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1511 qinfo->conf.rx_drop_en = 0;
1512 qinfo->conf.rx_deferred_start = 0;
1516 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1517 struct rte_eth_txq_info *qinfo)
1519 struct bnxt_tx_queue *txq;
1521 txq = dev->data->tx_queues[queue_id];
1523 qinfo->nb_desc = txq->nb_tx_desc;
1525 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1526 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1527 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1529 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1530 qinfo->conf.tx_rs_thresh = 0;
1531 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1534 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1536 struct bnxt *bp = eth_dev->data->dev_private;
1537 struct rte_eth_dev_info dev_info;
1538 uint32_t max_dev_mtu;
1542 bnxt_dev_info_get_op(eth_dev, &dev_info);
1543 max_dev_mtu = dev_info.max_rx_pktlen -
1544 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2;
1546 if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) {
1547 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1548 ETHER_MIN_MTU, max_dev_mtu);
1553 if (new_mtu > ETHER_MTU) {
1554 bp->flags |= BNXT_FLAG_JUMBO;
1555 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1556 DEV_RX_OFFLOAD_JUMBO_FRAME;
1558 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1559 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1560 bp->flags &= ~BNXT_FLAG_JUMBO;
1563 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
1564 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1566 eth_dev->data->mtu = new_mtu;
1567 PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1569 for (i = 0; i < bp->nr_vnics; i++) {
1570 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1572 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1573 ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1574 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1578 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1587 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1589 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1590 uint16_t vlan = bp->vlan;
1593 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1595 "PVID cannot be modified for this function\n");
1598 bp->vlan = on ? pvid : 0;
1600 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1607 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1609 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1611 return bnxt_hwrm_port_led_cfg(bp, true);
1615 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1617 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1619 return bnxt_hwrm_port_led_cfg(bp, false);
1623 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1625 uint32_t desc = 0, raw_cons = 0, cons;
1626 struct bnxt_cp_ring_info *cpr;
1627 struct bnxt_rx_queue *rxq;
1628 struct rx_pkt_cmpl *rxcmp;
1633 rxq = dev->data->rx_queues[rx_queue_id];
1637 while (raw_cons < rxq->nb_rx_desc) {
1638 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1639 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1641 if (!CMPL_VALID(rxcmp, valid))
1643 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1644 cmp_type = CMP_TYPE(rxcmp);
1645 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1646 cmp = (rte_le_to_cpu_32(
1647 ((struct rx_tpa_end_cmpl *)
1648 (rxcmp))->agg_bufs_v1) &
1649 RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1650 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1652 } else if (cmp_type == 0x11) {
1654 cmp = (rxcmp->agg_bufs_v1 &
1655 RX_PKT_CMPL_AGG_BUFS_MASK) >>
1656 RX_PKT_CMPL_AGG_BUFS_SFT;
1661 raw_cons += cmp ? cmp : 2;
1668 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1670 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1671 struct bnxt_rx_ring_info *rxr;
1672 struct bnxt_cp_ring_info *cpr;
1673 struct bnxt_sw_rx_bd *rx_buf;
1674 struct rx_pkt_cmpl *rxcmp;
1675 uint32_t cons, cp_cons;
1683 if (offset >= rxq->nb_rx_desc)
1686 cons = RING_CMP(cpr->cp_ring_struct, offset);
1687 cp_cons = cpr->cp_raw_cons;
1688 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1690 if (cons > cp_cons) {
1691 if (CMPL_VALID(rxcmp, cpr->valid))
1692 return RTE_ETH_RX_DESC_DONE;
1694 if (CMPL_VALID(rxcmp, !cpr->valid))
1695 return RTE_ETH_RX_DESC_DONE;
1697 rx_buf = &rxr->rx_buf_ring[cons];
1698 if (rx_buf->mbuf == NULL)
1699 return RTE_ETH_RX_DESC_UNAVAIL;
1702 return RTE_ETH_RX_DESC_AVAIL;
1706 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1708 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1709 struct bnxt_tx_ring_info *txr;
1710 struct bnxt_cp_ring_info *cpr;
1711 struct bnxt_sw_tx_bd *tx_buf;
1712 struct tx_pkt_cmpl *txcmp;
1713 uint32_t cons, cp_cons;
1721 if (offset >= txq->nb_tx_desc)
1724 cons = RING_CMP(cpr->cp_ring_struct, offset);
1725 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1726 cp_cons = cpr->cp_raw_cons;
1728 if (cons > cp_cons) {
1729 if (CMPL_VALID(txcmp, cpr->valid))
1730 return RTE_ETH_TX_DESC_UNAVAIL;
1732 if (CMPL_VALID(txcmp, !cpr->valid))
1733 return RTE_ETH_TX_DESC_UNAVAIL;
1735 tx_buf = &txr->tx_buf_ring[cons];
1736 if (tx_buf->mbuf == NULL)
1737 return RTE_ETH_TX_DESC_DONE;
1739 return RTE_ETH_TX_DESC_FULL;
1742 static struct bnxt_filter_info *
1743 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1744 struct rte_eth_ethertype_filter *efilter,
1745 struct bnxt_vnic_info *vnic0,
1746 struct bnxt_vnic_info *vnic,
1749 struct bnxt_filter_info *mfilter = NULL;
1753 if (efilter->ether_type == ETHER_TYPE_IPv4 ||
1754 efilter->ether_type == ETHER_TYPE_IPv6) {
1755 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
1756 " ethertype filter.", efilter->ether_type);
1760 if (efilter->queue >= bp->rx_nr_rings) {
1761 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1766 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1767 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1769 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1774 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1775 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1776 if ((!memcmp(efilter->mac_addr.addr_bytes,
1777 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1779 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1780 mfilter->ethertype == efilter->ether_type)) {
1786 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1787 if ((!memcmp(efilter->mac_addr.addr_bytes,
1788 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1789 mfilter->ethertype == efilter->ether_type &&
1791 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
1805 bnxt_ethertype_filter(struct rte_eth_dev *dev,
1806 enum rte_filter_op filter_op,
1809 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1810 struct rte_eth_ethertype_filter *efilter =
1811 (struct rte_eth_ethertype_filter *)arg;
1812 struct bnxt_filter_info *bfilter, *filter1;
1813 struct bnxt_vnic_info *vnic, *vnic0;
1816 if (filter_op == RTE_ETH_FILTER_NOP)
1820 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
1825 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1826 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1828 switch (filter_op) {
1829 case RTE_ETH_FILTER_ADD:
1830 bnxt_match_and_validate_ether_filter(bp, efilter,
1835 bfilter = bnxt_get_unused_filter(bp);
1836 if (bfilter == NULL) {
1838 "Not enough resources for a new filter.\n");
1841 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
1842 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
1844 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
1846 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
1847 bfilter->ethertype = efilter->ether_type;
1848 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
1850 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
1851 if (filter1 == NULL) {
1856 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
1857 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
1859 bfilter->dst_id = vnic->fw_vnic_id;
1861 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1863 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
1866 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
1869 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
1871 case RTE_ETH_FILTER_DELETE:
1872 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
1874 if (ret == -EEXIST) {
1875 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
1877 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
1879 bnxt_free_filter(bp, filter1);
1880 } else if (ret == 0) {
1881 PMD_DRV_LOG(ERR, "No matching filter found\n");
1885 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
1891 bnxt_free_filter(bp, bfilter);
1897 parse_ntuple_filter(struct bnxt *bp,
1898 struct rte_eth_ntuple_filter *nfilter,
1899 struct bnxt_filter_info *bfilter)
1903 if (nfilter->queue >= bp->rx_nr_rings) {
1904 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
1908 switch (nfilter->dst_port_mask) {
1910 bfilter->dst_port_mask = -1;
1911 bfilter->dst_port = nfilter->dst_port;
1912 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
1913 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
1916 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
1920 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
1921 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1923 switch (nfilter->proto_mask) {
1925 if (nfilter->proto == 17) /* IPPROTO_UDP */
1926 bfilter->ip_protocol = 17;
1927 else if (nfilter->proto == 6) /* IPPROTO_TCP */
1928 bfilter->ip_protocol = 6;
1931 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1934 PMD_DRV_LOG(ERR, "invalid protocol mask.");
1938 switch (nfilter->dst_ip_mask) {
1940 bfilter->dst_ipaddr_mask[0] = -1;
1941 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
1942 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
1943 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
1946 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
1950 switch (nfilter->src_ip_mask) {
1952 bfilter->src_ipaddr_mask[0] = -1;
1953 bfilter->src_ipaddr[0] = nfilter->src_ip;
1954 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
1955 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
1958 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
1962 switch (nfilter->src_port_mask) {
1964 bfilter->src_port_mask = -1;
1965 bfilter->src_port = nfilter->src_port;
1966 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
1967 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
1970 PMD_DRV_LOG(ERR, "invalid src_port mask.");
1975 //nfilter->priority = (uint8_t)filter->priority;
1977 bfilter->enables = en;
1981 static struct bnxt_filter_info*
1982 bnxt_match_ntuple_filter(struct bnxt *bp,
1983 struct bnxt_filter_info *bfilter,
1984 struct bnxt_vnic_info **mvnic)
1986 struct bnxt_filter_info *mfilter = NULL;
1989 for (i = bp->nr_vnics - 1; i >= 0; i--) {
1990 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1991 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
1992 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
1993 bfilter->src_ipaddr_mask[0] ==
1994 mfilter->src_ipaddr_mask[0] &&
1995 bfilter->src_port == mfilter->src_port &&
1996 bfilter->src_port_mask == mfilter->src_port_mask &&
1997 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
1998 bfilter->dst_ipaddr_mask[0] ==
1999 mfilter->dst_ipaddr_mask[0] &&
2000 bfilter->dst_port == mfilter->dst_port &&
2001 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2002 bfilter->flags == mfilter->flags &&
2003 bfilter->enables == mfilter->enables) {
2014 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2015 struct rte_eth_ntuple_filter *nfilter,
2016 enum rte_filter_op filter_op)
2018 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2019 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2022 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2023 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2027 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2028 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2032 bfilter = bnxt_get_unused_filter(bp);
2033 if (bfilter == NULL) {
2035 "Not enough resources for a new filter.\n");
2038 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2042 vnic = STAILQ_FIRST(&bp->ff_pool[nfilter->queue]);
2043 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2044 filter1 = STAILQ_FIRST(&vnic0->filter);
2045 if (filter1 == NULL) {
2050 bfilter->dst_id = vnic->fw_vnic_id;
2051 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2053 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2054 bfilter->ethertype = 0x800;
2055 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2057 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2059 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2060 bfilter->dst_id == mfilter->dst_id) {
2061 PMD_DRV_LOG(ERR, "filter exists.\n");
2064 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2065 bfilter->dst_id != mfilter->dst_id) {
2066 mfilter->dst_id = vnic->fw_vnic_id;
2067 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2068 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2069 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2070 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2071 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2074 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2075 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2080 if (filter_op == RTE_ETH_FILTER_ADD) {
2081 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2082 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2085 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2087 if (mfilter == NULL) {
2088 /* This should not happen. But for Coverity! */
2092 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2094 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2095 bnxt_free_filter(bp, mfilter);
2096 mfilter->fw_l2_filter_id = -1;
2097 bnxt_free_filter(bp, bfilter);
2098 bfilter->fw_l2_filter_id = -1;
2103 bfilter->fw_l2_filter_id = -1;
2104 bnxt_free_filter(bp, bfilter);
2109 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2110 enum rte_filter_op filter_op,
2113 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2116 if (filter_op == RTE_ETH_FILTER_NOP)
2120 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2125 switch (filter_op) {
2126 case RTE_ETH_FILTER_ADD:
2127 ret = bnxt_cfg_ntuple_filter(bp,
2128 (struct rte_eth_ntuple_filter *)arg,
2131 case RTE_ETH_FILTER_DELETE:
2132 ret = bnxt_cfg_ntuple_filter(bp,
2133 (struct rte_eth_ntuple_filter *)arg,
2137 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2145 bnxt_parse_fdir_filter(struct bnxt *bp,
2146 struct rte_eth_fdir_filter *fdir,
2147 struct bnxt_filter_info *filter)
2149 enum rte_fdir_mode fdir_mode =
2150 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2151 struct bnxt_vnic_info *vnic0, *vnic;
2152 struct bnxt_filter_info *filter1;
2156 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2159 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2160 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2162 switch (fdir->input.flow_type) {
2163 case RTE_ETH_FLOW_IPV4:
2164 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2166 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2167 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2168 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2169 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2170 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2171 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2172 filter->ip_addr_type =
2173 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2174 filter->src_ipaddr_mask[0] = 0xffffffff;
2175 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2176 filter->dst_ipaddr_mask[0] = 0xffffffff;
2177 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2178 filter->ethertype = 0x800;
2179 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2181 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2182 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2183 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2184 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2185 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2186 filter->dst_port_mask = 0xffff;
2187 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2188 filter->src_port_mask = 0xffff;
2189 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2190 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2191 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2192 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2193 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2194 filter->ip_protocol = 6;
2195 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2196 filter->ip_addr_type =
2197 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2198 filter->src_ipaddr_mask[0] = 0xffffffff;
2199 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2200 filter->dst_ipaddr_mask[0] = 0xffffffff;
2201 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2202 filter->ethertype = 0x800;
2203 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2205 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2206 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2207 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2208 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2209 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2210 filter->dst_port_mask = 0xffff;
2211 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2212 filter->src_port_mask = 0xffff;
2213 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2214 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2215 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2216 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2217 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2218 filter->ip_protocol = 17;
2219 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2220 filter->ip_addr_type =
2221 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2222 filter->src_ipaddr_mask[0] = 0xffffffff;
2223 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2224 filter->dst_ipaddr_mask[0] = 0xffffffff;
2225 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2226 filter->ethertype = 0x800;
2227 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2229 case RTE_ETH_FLOW_IPV6:
2230 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2232 filter->ip_addr_type =
2233 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2234 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2235 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2236 rte_memcpy(filter->src_ipaddr,
2237 fdir->input.flow.ipv6_flow.src_ip, 16);
2238 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2239 rte_memcpy(filter->dst_ipaddr,
2240 fdir->input.flow.ipv6_flow.dst_ip, 16);
2241 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2242 memset(filter->dst_ipaddr_mask, 0xff, 16);
2243 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2244 memset(filter->src_ipaddr_mask, 0xff, 16);
2245 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2246 filter->ethertype = 0x86dd;
2247 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2249 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2250 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2251 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2252 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2253 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2254 filter->dst_port_mask = 0xffff;
2255 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2256 filter->src_port_mask = 0xffff;
2257 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2258 filter->ip_addr_type =
2259 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2260 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2261 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2262 rte_memcpy(filter->src_ipaddr,
2263 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2264 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2265 rte_memcpy(filter->dst_ipaddr,
2266 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2267 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2268 memset(filter->dst_ipaddr_mask, 0xff, 16);
2269 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2270 memset(filter->src_ipaddr_mask, 0xff, 16);
2271 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2272 filter->ethertype = 0x86dd;
2273 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2275 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2276 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2277 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2278 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2279 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2280 filter->dst_port_mask = 0xffff;
2281 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2282 filter->src_port_mask = 0xffff;
2283 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2284 filter->ip_addr_type =
2285 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2286 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2287 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2288 rte_memcpy(filter->src_ipaddr,
2289 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2290 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2291 rte_memcpy(filter->dst_ipaddr,
2292 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2293 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2294 memset(filter->dst_ipaddr_mask, 0xff, 16);
2295 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2296 memset(filter->src_ipaddr_mask, 0xff, 16);
2297 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2298 filter->ethertype = 0x86dd;
2299 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2301 case RTE_ETH_FLOW_L2_PAYLOAD:
2302 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2303 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2305 case RTE_ETH_FLOW_VXLAN:
2306 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2308 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2309 filter->tunnel_type =
2310 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2311 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2313 case RTE_ETH_FLOW_NVGRE:
2314 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2316 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2317 filter->tunnel_type =
2318 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2319 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2321 case RTE_ETH_FLOW_UNKNOWN:
2322 case RTE_ETH_FLOW_RAW:
2323 case RTE_ETH_FLOW_FRAG_IPV4:
2324 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2325 case RTE_ETH_FLOW_FRAG_IPV6:
2326 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2327 case RTE_ETH_FLOW_IPV6_EX:
2328 case RTE_ETH_FLOW_IPV6_TCP_EX:
2329 case RTE_ETH_FLOW_IPV6_UDP_EX:
2330 case RTE_ETH_FLOW_GENEVE:
2336 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2337 vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2339 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2344 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2345 rte_memcpy(filter->dst_macaddr,
2346 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2347 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2350 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2351 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2352 filter1 = STAILQ_FIRST(&vnic0->filter);
2353 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2355 filter->dst_id = vnic->fw_vnic_id;
2356 for (i = 0; i < ETHER_ADDR_LEN; i++)
2357 if (filter->dst_macaddr[i] == 0x00)
2358 filter1 = STAILQ_FIRST(&vnic0->filter);
2360 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2363 if (filter1 == NULL)
2366 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2367 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2369 filter->enables = en;
2374 static struct bnxt_filter_info *
2375 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2376 struct bnxt_vnic_info **mvnic)
2378 struct bnxt_filter_info *mf = NULL;
2381 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2382 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2384 STAILQ_FOREACH(mf, &vnic->filter, next) {
2385 if (mf->filter_type == nf->filter_type &&
2386 mf->flags == nf->flags &&
2387 mf->src_port == nf->src_port &&
2388 mf->src_port_mask == nf->src_port_mask &&
2389 mf->dst_port == nf->dst_port &&
2390 mf->dst_port_mask == nf->dst_port_mask &&
2391 mf->ip_protocol == nf->ip_protocol &&
2392 mf->ip_addr_type == nf->ip_addr_type &&
2393 mf->ethertype == nf->ethertype &&
2394 mf->vni == nf->vni &&
2395 mf->tunnel_type == nf->tunnel_type &&
2396 mf->l2_ovlan == nf->l2_ovlan &&
2397 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2398 mf->l2_ivlan == nf->l2_ivlan &&
2399 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2400 !memcmp(mf->l2_addr, nf->l2_addr, ETHER_ADDR_LEN) &&
2401 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2403 !memcmp(mf->src_macaddr, nf->src_macaddr,
2405 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2407 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2408 sizeof(nf->src_ipaddr)) &&
2409 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2410 sizeof(nf->src_ipaddr_mask)) &&
2411 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2412 sizeof(nf->dst_ipaddr)) &&
2413 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2414 sizeof(nf->dst_ipaddr_mask))) {
2425 bnxt_fdir_filter(struct rte_eth_dev *dev,
2426 enum rte_filter_op filter_op,
2429 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2430 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2431 struct bnxt_filter_info *filter, *match;
2432 struct bnxt_vnic_info *vnic, *mvnic;
2435 if (filter_op == RTE_ETH_FILTER_NOP)
2438 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2441 switch (filter_op) {
2442 case RTE_ETH_FILTER_ADD:
2443 case RTE_ETH_FILTER_DELETE:
2445 filter = bnxt_get_unused_filter(bp);
2446 if (filter == NULL) {
2448 "Not enough resources for a new flow.\n");
2452 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2455 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2457 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2458 vnic = STAILQ_FIRST(&bp->ff_pool[0]);
2460 vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2462 match = bnxt_match_fdir(bp, filter, &mvnic);
2463 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2464 if (match->dst_id == vnic->fw_vnic_id) {
2465 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2469 match->dst_id = vnic->fw_vnic_id;
2470 ret = bnxt_hwrm_set_ntuple_filter(bp,
2473 STAILQ_REMOVE(&mvnic->filter, match,
2474 bnxt_filter_info, next);
2475 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2477 "Filter with matching pattern exist\n");
2479 "Updated it to new destination q\n");
2483 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2484 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2489 if (filter_op == RTE_ETH_FILTER_ADD) {
2490 ret = bnxt_hwrm_set_ntuple_filter(bp,
2495 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2497 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2498 STAILQ_REMOVE(&vnic->filter, match,
2499 bnxt_filter_info, next);
2500 bnxt_free_filter(bp, match);
2501 filter->fw_l2_filter_id = -1;
2502 bnxt_free_filter(bp, filter);
2505 case RTE_ETH_FILTER_FLUSH:
2506 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2507 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2509 STAILQ_FOREACH(filter, &vnic->filter, next) {
2510 if (filter->filter_type ==
2511 HWRM_CFA_NTUPLE_FILTER) {
2513 bnxt_hwrm_clear_ntuple_filter(bp,
2515 STAILQ_REMOVE(&vnic->filter, filter,
2516 bnxt_filter_info, next);
2521 case RTE_ETH_FILTER_UPDATE:
2522 case RTE_ETH_FILTER_STATS:
2523 case RTE_ETH_FILTER_INFO:
2524 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2527 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2534 filter->fw_l2_filter_id = -1;
2535 bnxt_free_filter(bp, filter);
2540 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2541 enum rte_filter_type filter_type,
2542 enum rte_filter_op filter_op, void *arg)
2546 switch (filter_type) {
2547 case RTE_ETH_FILTER_TUNNEL:
2549 "filter type: %d: To be implemented\n", filter_type);
2551 case RTE_ETH_FILTER_FDIR:
2552 ret = bnxt_fdir_filter(dev, filter_op, arg);
2554 case RTE_ETH_FILTER_NTUPLE:
2555 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2557 case RTE_ETH_FILTER_ETHERTYPE:
2558 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2560 case RTE_ETH_FILTER_GENERIC:
2561 if (filter_op != RTE_ETH_FILTER_GET)
2563 *(const void **)arg = &bnxt_flow_ops;
2567 "Filter type (%d) not supported", filter_type);
2574 static const uint32_t *
2575 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2577 static const uint32_t ptypes[] = {
2578 RTE_PTYPE_L2_ETHER_VLAN,
2579 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2580 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2584 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2585 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2586 RTE_PTYPE_INNER_L4_ICMP,
2587 RTE_PTYPE_INNER_L4_TCP,
2588 RTE_PTYPE_INNER_L4_UDP,
2592 if (dev->rx_pkt_burst == bnxt_recv_pkts)
2597 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2600 uint32_t reg_base = *reg_arr & 0xfffff000;
2604 for (i = 0; i < count; i++) {
2605 if ((reg_arr[i] & 0xfffff000) != reg_base)
2608 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2609 rte_cpu_to_le_32(rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off));
2613 static int bnxt_map_ptp_regs(struct bnxt *bp)
2615 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2619 reg_arr = ptp->rx_regs;
2620 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2624 reg_arr = ptp->tx_regs;
2625 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2629 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2630 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2632 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2633 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2638 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2640 rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2641 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16));
2642 rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2643 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20));
2646 static uint64_t bnxt_cc_read(struct bnxt *bp)
2650 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2651 BNXT_GRCPF_REG_SYNC_TIME));
2652 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2653 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2657 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2659 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2662 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2663 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2664 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2667 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2668 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2669 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2670 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2671 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2672 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2677 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2679 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2680 struct bnxt_pf_info *pf = &bp->pf;
2687 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2688 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2689 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2692 port_id = pf->port_id;
2693 rte_cpu_to_le_32(rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2694 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]));
2696 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2697 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2698 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2699 /* bnxt_clr_rx_ts(bp); TBD */
2703 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2704 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2705 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2706 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2712 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2715 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2716 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2721 ns = rte_timespec_to_ns(ts);
2722 /* Set the timecounters to a new value. */
2729 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2731 uint64_t ns, systime_cycles;
2732 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2733 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2738 systime_cycles = bnxt_cc_read(bp);
2739 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
2740 *ts = rte_ns_to_timespec(ns);
2745 bnxt_timesync_enable(struct rte_eth_dev *dev)
2747 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2748 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2755 ptp->tx_tstamp_en = 1;
2756 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
2758 if (!bnxt_hwrm_ptp_cfg(bp))
2759 bnxt_map_ptp_regs(bp);
2761 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
2762 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2763 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2765 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2766 ptp->tc.cc_shift = shift;
2767 ptp->tc.nsec_mask = (1ULL << shift) - 1;
2769 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2770 ptp->rx_tstamp_tc.cc_shift = shift;
2771 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2773 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2774 ptp->tx_tstamp_tc.cc_shift = shift;
2775 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2781 bnxt_timesync_disable(struct rte_eth_dev *dev)
2783 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2784 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2790 ptp->tx_tstamp_en = 0;
2793 bnxt_hwrm_ptp_cfg(bp);
2795 bnxt_unmap_ptp_regs(bp);
2801 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
2802 struct timespec *timestamp,
2803 uint32_t flags __rte_unused)
2805 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2806 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2807 uint64_t rx_tstamp_cycles = 0;
2813 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
2814 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
2815 *timestamp = rte_ns_to_timespec(ns);
2820 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
2821 struct timespec *timestamp)
2823 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2824 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2825 uint64_t tx_tstamp_cycles = 0;
2831 bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
2832 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
2833 *timestamp = rte_ns_to_timespec(ns);
2839 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
2841 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2842 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2847 ptp->tc.nsec += delta;
2853 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
2855 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2857 uint32_t dir_entries;
2858 uint32_t entry_length;
2860 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
2861 bp->pdev->addr.domain, bp->pdev->addr.bus,
2862 bp->pdev->addr.devid, bp->pdev->addr.function);
2864 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
2868 return dir_entries * entry_length;
2872 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
2873 struct rte_dev_eeprom_info *in_eeprom)
2875 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2879 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2880 "len = %d\n", bp->pdev->addr.domain,
2881 bp->pdev->addr.bus, bp->pdev->addr.devid,
2882 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2884 if (in_eeprom->offset == 0) /* special offset value to get directory */
2885 return bnxt_get_nvram_directory(bp, in_eeprom->length,
2888 index = in_eeprom->offset >> 24;
2889 offset = in_eeprom->offset & 0xffffff;
2892 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
2893 in_eeprom->length, in_eeprom->data);
2898 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
2901 case BNX_DIR_TYPE_CHIMP_PATCH:
2902 case BNX_DIR_TYPE_BOOTCODE:
2903 case BNX_DIR_TYPE_BOOTCODE_2:
2904 case BNX_DIR_TYPE_APE_FW:
2905 case BNX_DIR_TYPE_APE_PATCH:
2906 case BNX_DIR_TYPE_KONG_FW:
2907 case BNX_DIR_TYPE_KONG_PATCH:
2908 case BNX_DIR_TYPE_BONO_FW:
2909 case BNX_DIR_TYPE_BONO_PATCH:
2917 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
2920 case BNX_DIR_TYPE_AVS:
2921 case BNX_DIR_TYPE_EXP_ROM_MBA:
2922 case BNX_DIR_TYPE_PCIE:
2923 case BNX_DIR_TYPE_TSCF_UCODE:
2924 case BNX_DIR_TYPE_EXT_PHY:
2925 case BNX_DIR_TYPE_CCM:
2926 case BNX_DIR_TYPE_ISCSI_BOOT:
2927 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2928 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2936 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
2938 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2939 bnxt_dir_type_is_other_exec_format(dir_type);
2943 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
2944 struct rte_dev_eeprom_info *in_eeprom)
2946 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2947 uint8_t index, dir_op;
2948 uint16_t type, ext, ordinal, attr;
2950 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2951 "len = %d\n", bp->pdev->addr.domain,
2952 bp->pdev->addr.bus, bp->pdev->addr.devid,
2953 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2956 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
2960 type = in_eeprom->magic >> 16;
2962 if (type == 0xffff) { /* special value for directory operations */
2963 index = in_eeprom->magic & 0xff;
2964 dir_op = in_eeprom->magic >> 8;
2968 case 0x0e: /* erase */
2969 if (in_eeprom->offset != ~in_eeprom->magic)
2971 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
2977 /* Create or re-write an NVM item: */
2978 if (bnxt_dir_type_is_executable(type) == true)
2980 ext = in_eeprom->magic & 0xffff;
2981 ordinal = in_eeprom->offset >> 16;
2982 attr = in_eeprom->offset & 0xffff;
2984 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
2985 in_eeprom->data, in_eeprom->length);
2993 static const struct eth_dev_ops bnxt_dev_ops = {
2994 .dev_infos_get = bnxt_dev_info_get_op,
2995 .dev_close = bnxt_dev_close_op,
2996 .dev_configure = bnxt_dev_configure_op,
2997 .dev_start = bnxt_dev_start_op,
2998 .dev_stop = bnxt_dev_stop_op,
2999 .dev_set_link_up = bnxt_dev_set_link_up_op,
3000 .dev_set_link_down = bnxt_dev_set_link_down_op,
3001 .stats_get = bnxt_stats_get_op,
3002 .stats_reset = bnxt_stats_reset_op,
3003 .rx_queue_setup = bnxt_rx_queue_setup_op,
3004 .rx_queue_release = bnxt_rx_queue_release_op,
3005 .tx_queue_setup = bnxt_tx_queue_setup_op,
3006 .tx_queue_release = bnxt_tx_queue_release_op,
3007 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3008 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3009 .reta_update = bnxt_reta_update_op,
3010 .reta_query = bnxt_reta_query_op,
3011 .rss_hash_update = bnxt_rss_hash_update_op,
3012 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3013 .link_update = bnxt_link_update_op,
3014 .promiscuous_enable = bnxt_promiscuous_enable_op,
3015 .promiscuous_disable = bnxt_promiscuous_disable_op,
3016 .allmulticast_enable = bnxt_allmulticast_enable_op,
3017 .allmulticast_disable = bnxt_allmulticast_disable_op,
3018 .mac_addr_add = bnxt_mac_addr_add_op,
3019 .mac_addr_remove = bnxt_mac_addr_remove_op,
3020 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3021 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3022 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3023 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3024 .vlan_filter_set = bnxt_vlan_filter_set_op,
3025 .vlan_offload_set = bnxt_vlan_offload_set_op,
3026 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3027 .mtu_set = bnxt_mtu_set_op,
3028 .mac_addr_set = bnxt_set_default_mac_addr_op,
3029 .xstats_get = bnxt_dev_xstats_get_op,
3030 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3031 .xstats_reset = bnxt_dev_xstats_reset_op,
3032 .fw_version_get = bnxt_fw_version_get,
3033 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3034 .rxq_info_get = bnxt_rxq_info_get_op,
3035 .txq_info_get = bnxt_txq_info_get_op,
3036 .dev_led_on = bnxt_dev_led_on_op,
3037 .dev_led_off = bnxt_dev_led_off_op,
3038 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3039 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3040 .rx_queue_count = bnxt_rx_queue_count_op,
3041 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3042 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3043 .rx_queue_start = bnxt_rx_queue_start,
3044 .rx_queue_stop = bnxt_rx_queue_stop,
3045 .tx_queue_start = bnxt_tx_queue_start,
3046 .tx_queue_stop = bnxt_tx_queue_stop,
3047 .filter_ctrl = bnxt_filter_ctrl_op,
3048 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3049 .get_eeprom_length = bnxt_get_eeprom_length_op,
3050 .get_eeprom = bnxt_get_eeprom_op,
3051 .set_eeprom = bnxt_set_eeprom_op,
3052 .timesync_enable = bnxt_timesync_enable,
3053 .timesync_disable = bnxt_timesync_disable,
3054 .timesync_read_time = bnxt_timesync_read_time,
3055 .timesync_write_time = bnxt_timesync_write_time,
3056 .timesync_adjust_time = bnxt_timesync_adjust_time,
3057 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3058 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3061 static bool bnxt_vf_pciid(uint16_t id)
3063 if (id == BROADCOM_DEV_ID_57304_VF ||
3064 id == BROADCOM_DEV_ID_57406_VF ||
3065 id == BROADCOM_DEV_ID_5731X_VF ||
3066 id == BROADCOM_DEV_ID_5741X_VF ||
3067 id == BROADCOM_DEV_ID_57414_VF ||
3068 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3069 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3074 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3076 struct bnxt *bp = eth_dev->data->dev_private;
3077 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3080 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3081 if (!pci_dev->mem_resource[0].addr) {
3083 "Cannot find PCI device base address, aborting\n");
3085 goto init_err_disable;
3088 bp->eth_dev = eth_dev;
3091 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3093 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3095 goto init_err_release;
3098 if (!pci_dev->mem_resource[2].addr) {
3100 "Cannot find PCI device BAR 2 address, aborting\n");
3102 goto init_err_release;
3104 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3112 if (bp->doorbell_base)
3113 bp->doorbell_base = NULL;
3120 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
3122 #define ALLOW_FUNC(x) \
3124 typeof(x) arg = (x); \
3125 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3126 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3129 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3131 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3132 char mz_name[RTE_MEMZONE_NAMESIZE];
3133 const struct rte_memzone *mz = NULL;
3134 static int version_printed;
3135 uint32_t total_alloc_len;
3136 rte_iova_t mz_phys_addr;
3140 if (version_printed++ == 0)
3141 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3143 rte_eth_copy_pci_info(eth_dev, pci_dev);
3145 bp = eth_dev->data->dev_private;
3147 bp->dev_stopped = 1;
3149 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3152 if (bnxt_vf_pciid(pci_dev->id.device_id))
3153 bp->flags |= BNXT_FLAG_VF;
3155 rc = bnxt_init_board(eth_dev);
3158 "Board initialization failed rc: %x\n", rc);
3162 eth_dev->dev_ops = &bnxt_dev_ops;
3163 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3164 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3165 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3168 if (pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3169 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3170 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3171 pci_dev->addr.bus, pci_dev->addr.devid,
3172 pci_dev->addr.function, "rx_port_stats");
3173 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3174 mz = rte_memzone_lookup(mz_name);
3175 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3176 sizeof(struct rx_port_stats) + 512);
3178 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3181 RTE_MEMZONE_SIZE_HINT_ONLY |
3182 RTE_MEMZONE_IOVA_CONTIG);
3186 memset(mz->addr, 0, mz->len);
3187 mz_phys_addr = mz->iova;
3188 if ((unsigned long)mz->addr == mz_phys_addr) {
3189 PMD_DRV_LOG(WARNING,
3190 "Memzone physical address same as virtual.\n");
3191 PMD_DRV_LOG(WARNING,
3192 "Using rte_mem_virt2iova()\n");
3193 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3194 if (mz_phys_addr == 0) {
3196 "unable to map address to physical memory\n");
3201 bp->rx_mem_zone = (const void *)mz;
3202 bp->hw_rx_port_stats = mz->addr;
3203 bp->hw_rx_port_stats_map = mz_phys_addr;
3205 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3206 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3207 pci_dev->addr.bus, pci_dev->addr.devid,
3208 pci_dev->addr.function, "tx_port_stats");
3209 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3210 mz = rte_memzone_lookup(mz_name);
3211 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3212 sizeof(struct tx_port_stats) + 512);
3214 mz = rte_memzone_reserve(mz_name,
3218 RTE_MEMZONE_SIZE_HINT_ONLY |
3219 RTE_MEMZONE_IOVA_CONTIG);
3223 memset(mz->addr, 0, mz->len);
3224 mz_phys_addr = mz->iova;
3225 if ((unsigned long)mz->addr == mz_phys_addr) {
3226 PMD_DRV_LOG(WARNING,
3227 "Memzone physical address same as virtual.\n");
3228 PMD_DRV_LOG(WARNING,
3229 "Using rte_mem_virt2iova()\n");
3230 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3231 if (mz_phys_addr == 0) {
3233 "unable to map address to physical memory\n");
3238 bp->tx_mem_zone = (const void *)mz;
3239 bp->hw_tx_port_stats = mz->addr;
3240 bp->hw_tx_port_stats_map = mz_phys_addr;
3242 bp->flags |= BNXT_FLAG_PORT_STATS;
3245 rc = bnxt_alloc_hwrm_resources(bp);
3248 "hwrm resource allocation failure rc: %x\n", rc);
3251 rc = bnxt_hwrm_ver_get(bp);
3254 rc = bnxt_hwrm_queue_qportcfg(bp);
3256 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3260 rc = bnxt_hwrm_func_qcfg(bp);
3262 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3266 /* Get the MAX capabilities for this function */
3267 rc = bnxt_hwrm_func_qcaps(bp);
3269 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3272 if (bp->max_tx_rings == 0) {
3273 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3277 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3278 ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3279 if (eth_dev->data->mac_addrs == NULL) {
3281 "Failed to alloc %u bytes needed to store MAC addr tbl",
3282 ETHER_ADDR_LEN * bp->max_l2_ctx);
3287 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, ETHER_ADDR_LEN)) {
3289 "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
3290 bp->dflt_mac_addr[0], bp->dflt_mac_addr[1],
3291 bp->dflt_mac_addr[2], bp->dflt_mac_addr[3],
3292 bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]);
3296 /* Copy the permanent MAC from the qcap response address now. */
3297 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3298 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
3300 if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3301 /* 1 ring is for default completion ring */
3302 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3307 bp->grp_info = rte_zmalloc("bnxt_grp_info",
3308 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3309 if (!bp->grp_info) {
3311 "Failed to alloc %zu bytes to store group info table\n",
3312 sizeof(*bp->grp_info) * bp->max_ring_grps);
3317 /* Forward all requests if firmware is new enough */
3318 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3319 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3320 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3321 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3323 PMD_DRV_LOG(WARNING,
3324 "Firmware too old for VF mailbox functionality\n");
3325 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3329 * The following are used for driver cleanup. If we disallow these,
3330 * VF drivers can't clean up cleanly.
3332 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3333 ALLOW_FUNC(HWRM_VNIC_FREE);
3334 ALLOW_FUNC(HWRM_RING_FREE);
3335 ALLOW_FUNC(HWRM_RING_GRP_FREE);
3336 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3337 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3338 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3339 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3340 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3341 rc = bnxt_hwrm_func_driver_register(bp);
3344 "Failed to register driver");
3350 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3351 pci_dev->mem_resource[0].phys_addr,
3352 pci_dev->mem_resource[0].addr);
3354 rc = bnxt_hwrm_func_reset(bp);
3356 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3362 //if (bp->pf.active_vfs) {
3363 // TODO: Deallocate VF resources?
3365 if (bp->pdev->max_vfs) {
3366 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3368 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3372 rc = bnxt_hwrm_allocate_pf_only(bp);
3375 "Failed to allocate PF resources\n");
3381 bnxt_hwrm_port_led_qcaps(bp);
3383 rc = bnxt_setup_int(bp);
3387 rc = bnxt_alloc_mem(bp);
3389 goto error_free_int;
3391 rc = bnxt_request_int(bp);
3393 goto error_free_int;
3395 bnxt_enable_int(bp);
3401 bnxt_disable_int(bp);
3402 bnxt_hwrm_func_buf_unrgtr(bp);
3406 bnxt_dev_uninit(eth_dev);
3412 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
3413 struct bnxt *bp = eth_dev->data->dev_private;
3416 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3419 bnxt_disable_int(bp);
3422 if (eth_dev->data->mac_addrs != NULL) {
3423 rte_free(eth_dev->data->mac_addrs);
3424 eth_dev->data->mac_addrs = NULL;
3426 if (bp->grp_info != NULL) {
3427 rte_free(bp->grp_info);
3428 bp->grp_info = NULL;
3430 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3431 bnxt_free_hwrm_resources(bp);
3432 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3433 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3434 if (bp->dev_stopped == 0)
3435 bnxt_dev_close_op(eth_dev);
3437 rte_free(bp->pf.vf_info);
3438 eth_dev->dev_ops = NULL;
3439 eth_dev->rx_pkt_burst = NULL;
3440 eth_dev->tx_pkt_burst = NULL;
3445 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3446 struct rte_pci_device *pci_dev)
3448 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
3452 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
3454 return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
3457 static struct rte_pci_driver bnxt_rte_pmd = {
3458 .id_table = bnxt_pci_id_map,
3459 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
3460 RTE_PCI_DRV_INTR_LSC,
3461 .probe = bnxt_pci_probe,
3462 .remove = bnxt_pci_remove,
3466 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
3468 if (strcmp(dev->device->driver->name, drv->driver.name))
3474 bool is_bnxt_supported(struct rte_eth_dev *dev)
3476 return is_device_supported(dev, &bnxt_rte_pmd);
3479 RTE_INIT(bnxt_init_log);
3483 bnxt_logtype_driver = rte_log_register("pmd.bnxt.driver");
3484 if (bnxt_logtype_driver >= 0)
3485 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_INFO);
3488 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
3489 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
3490 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");