1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
18 #include "bnxt_filter.h"
19 #include "bnxt_hwrm.h"
21 #include "bnxt_reps.h"
22 #include "bnxt_ring.h"
25 #include "bnxt_stats.h"
28 #include "bnxt_vnic.h"
29 #include "hsi_struct_def_dpdk.h"
30 #include "bnxt_nvm_defs.h"
31 #include "bnxt_tf_common.h"
32 #include "ulp_flow_db.h"
34 #define DRV_MODULE_NAME "bnxt"
35 static const char bnxt_version[] =
36 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
39 * The set of PCI devices this driver supports
41 static const struct rte_pci_id bnxt_pci_id_map[] = {
42 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
43 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
95 { .vendor_id = 0, /* sentinel */ },
98 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
99 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
100 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
101 #define BNXT_DEVARG_REPRESENTOR "representor"
103 static const char *const bnxt_dev_args[] = {
104 BNXT_DEVARG_REPRESENTOR,
106 BNXT_DEVARG_FLOW_XSTAT,
107 BNXT_DEVARG_MAX_NUM_KFLOWS,
112 * truflow == false to disable the feature
113 * truflow == true to enable the feature
115 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
118 * flow_xstat == false to disable the feature
119 * flow_xstat == true to enable the feature
121 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
124 * max_num_kflows must be >= 32
125 * and must be a power-of-2 supported value
126 * return: 1 -> invalid
129 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
131 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
136 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
137 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
138 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
139 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
140 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
141 static int bnxt_restore_vlan_filters(struct bnxt *bp);
142 static void bnxt_dev_recover(void *arg);
143 static void bnxt_free_error_recovery_info(struct bnxt *bp);
144 static void bnxt_free_rep_info(struct bnxt *bp);
146 int is_bnxt_in_error(struct bnxt *bp)
148 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
150 if (bp->flags & BNXT_FLAG_FW_RESET)
156 /***********************/
159 * High level utility functions
162 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
164 if (!BNXT_CHIP_THOR(bp))
167 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
168 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
169 BNXT_RSS_ENTRIES_PER_CTX_THOR;
172 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
174 if (!BNXT_CHIP_THOR(bp))
175 return HW_HASH_INDEX_SIZE;
177 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
180 static void bnxt_free_parent_info(struct bnxt *bp)
182 rte_free(bp->parent);
185 static void bnxt_free_pf_info(struct bnxt *bp)
190 static void bnxt_free_link_info(struct bnxt *bp)
192 rte_free(bp->link_info);
195 static void bnxt_free_leds_info(struct bnxt *bp)
204 static void bnxt_free_flow_stats_info(struct bnxt *bp)
206 rte_free(bp->flow_stat);
207 bp->flow_stat = NULL;
210 static void bnxt_free_cos_queues(struct bnxt *bp)
212 rte_free(bp->rx_cos_queue);
213 rte_free(bp->tx_cos_queue);
216 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
218 bnxt_free_filter_mem(bp);
219 bnxt_free_vnic_attributes(bp);
220 bnxt_free_vnic_mem(bp);
222 /* tx/rx rings are configured as part of *_queue_setup callbacks.
223 * If the number of rings change across fw update,
224 * we don't have much choice except to warn the user.
228 bnxt_free_tx_rings(bp);
229 bnxt_free_rx_rings(bp);
231 bnxt_free_async_cp_ring(bp);
232 bnxt_free_rxtx_nq_ring(bp);
234 rte_free(bp->grp_info);
238 static int bnxt_alloc_parent_info(struct bnxt *bp)
240 bp->parent = rte_zmalloc("bnxt_parent_info",
241 sizeof(struct bnxt_parent_info), 0);
242 if (bp->parent == NULL)
248 static int bnxt_alloc_pf_info(struct bnxt *bp)
250 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
257 static int bnxt_alloc_link_info(struct bnxt *bp)
260 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
261 if (bp->link_info == NULL)
267 static int bnxt_alloc_leds_info(struct bnxt *bp)
272 bp->leds = rte_zmalloc("bnxt_leds",
273 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
275 if (bp->leds == NULL)
281 static int bnxt_alloc_cos_queues(struct bnxt *bp)
284 rte_zmalloc("bnxt_rx_cosq",
285 BNXT_COS_QUEUE_COUNT *
286 sizeof(struct bnxt_cos_queue_info),
288 if (bp->rx_cos_queue == NULL)
292 rte_zmalloc("bnxt_tx_cosq",
293 BNXT_COS_QUEUE_COUNT *
294 sizeof(struct bnxt_cos_queue_info),
296 if (bp->tx_cos_queue == NULL)
302 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
304 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
305 sizeof(struct bnxt_flow_stat_info), 0);
306 if (bp->flow_stat == NULL)
312 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
316 rc = bnxt_alloc_ring_grps(bp);
320 rc = bnxt_alloc_async_ring_struct(bp);
324 rc = bnxt_alloc_vnic_mem(bp);
328 rc = bnxt_alloc_vnic_attributes(bp);
332 rc = bnxt_alloc_filter_mem(bp);
336 rc = bnxt_alloc_async_cp_ring(bp);
340 rc = bnxt_alloc_rxtx_nq_ring(bp);
344 if (BNXT_FLOW_XSTATS_EN(bp)) {
345 rc = bnxt_alloc_flow_stats_info(bp);
353 bnxt_free_mem(bp, reconfig);
357 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
359 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
360 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
361 uint64_t rx_offloads = dev_conf->rxmode.offloads;
362 struct bnxt_rx_queue *rxq;
366 rc = bnxt_vnic_grp_alloc(bp, vnic);
370 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
371 vnic_id, vnic, vnic->fw_grp_ids);
373 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
377 /* Alloc RSS context only if RSS mode is enabled */
378 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
379 int j, nr_ctxs = bnxt_rss_ctxts(bp);
382 for (j = 0; j < nr_ctxs; j++) {
383 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
389 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
393 vnic->num_lb_ctxts = nr_ctxs;
397 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
398 * setting is not available at this time, it will not be
399 * configured correctly in the CFA.
401 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
402 vnic->vlan_strip = true;
404 vnic->vlan_strip = false;
406 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
410 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
414 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
415 rxq = bp->eth_dev->data->rx_queues[j];
418 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
419 j, rxq->vnic, rxq->vnic->fw_grp_ids);
421 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
422 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
424 vnic->rx_queue_cnt++;
427 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
429 rc = bnxt_vnic_rss_configure(bp, vnic);
433 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
435 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
436 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
438 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
442 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
447 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
451 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
452 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
457 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
458 " rx_fc_in_tbl.ctx_id = %d\n",
459 bp->flow_stat->rx_fc_in_tbl.va,
460 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
461 bp->flow_stat->rx_fc_in_tbl.ctx_id);
463 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
464 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
469 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
470 " rx_fc_out_tbl.ctx_id = %d\n",
471 bp->flow_stat->rx_fc_out_tbl.va,
472 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
473 bp->flow_stat->rx_fc_out_tbl.ctx_id);
475 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
476 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
481 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
482 " tx_fc_in_tbl.ctx_id = %d\n",
483 bp->flow_stat->tx_fc_in_tbl.va,
484 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
485 bp->flow_stat->tx_fc_in_tbl.ctx_id);
487 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
488 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
493 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
494 " tx_fc_out_tbl.ctx_id = %d\n",
495 bp->flow_stat->tx_fc_out_tbl.va,
496 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
497 bp->flow_stat->tx_fc_out_tbl.ctx_id);
499 memset(bp->flow_stat->rx_fc_out_tbl.va,
501 bp->flow_stat->rx_fc_out_tbl.size);
502 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
503 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
504 bp->flow_stat->rx_fc_out_tbl.ctx_id,
505 bp->flow_stat->max_fc,
510 memset(bp->flow_stat->tx_fc_out_tbl.va,
512 bp->flow_stat->tx_fc_out_tbl.size);
513 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
514 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
515 bp->flow_stat->tx_fc_out_tbl.ctx_id,
516 bp->flow_stat->max_fc,
522 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
523 struct bnxt_ctx_mem_buf_info *ctx)
528 ctx->va = rte_zmalloc(type, size, 0);
531 rte_mem_lock_page(ctx->va);
533 ctx->dma = rte_mem_virt2iova(ctx->va);
534 if (ctx->dma == RTE_BAD_IOVA)
540 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
542 struct rte_pci_device *pdev = bp->pdev;
543 char type[RTE_MEMZONE_NAMESIZE];
547 max_fc = bp->flow_stat->max_fc;
549 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
550 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
551 /* 4 bytes for each counter-id */
552 rc = bnxt_alloc_ctx_mem_buf(type,
554 &bp->flow_stat->rx_fc_in_tbl);
558 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
559 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
560 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
561 rc = bnxt_alloc_ctx_mem_buf(type,
563 &bp->flow_stat->rx_fc_out_tbl);
567 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
568 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
569 /* 4 bytes for each counter-id */
570 rc = bnxt_alloc_ctx_mem_buf(type,
572 &bp->flow_stat->tx_fc_in_tbl);
576 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
577 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
578 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
579 rc = bnxt_alloc_ctx_mem_buf(type,
581 &bp->flow_stat->tx_fc_out_tbl);
585 rc = bnxt_register_fc_ctx_mem(bp);
590 static int bnxt_init_ctx_mem(struct bnxt *bp)
594 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
595 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
596 !BNXT_FLOW_XSTATS_EN(bp))
599 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
603 rc = bnxt_init_fc_ctx_mem(bp);
608 static int bnxt_update_phy_setting(struct bnxt *bp)
610 struct rte_eth_link new;
613 rc = bnxt_get_hwrm_link_config(bp, &new);
615 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
620 * On BCM957508-N2100 adapters, FW will not allow any user other
621 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
622 * always returns link up. Force phy update always in that case.
624 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
625 rc = bnxt_set_hwrm_link_config(bp, true);
627 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
635 static int bnxt_init_chip(struct bnxt *bp)
637 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
638 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
639 uint32_t intr_vector = 0;
640 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
641 uint32_t vec = BNXT_MISC_VEC_ID;
645 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
646 bp->eth_dev->data->dev_conf.rxmode.offloads |=
647 DEV_RX_OFFLOAD_JUMBO_FRAME;
648 bp->flags |= BNXT_FLAG_JUMBO;
650 bp->eth_dev->data->dev_conf.rxmode.offloads &=
651 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
652 bp->flags &= ~BNXT_FLAG_JUMBO;
655 /* THOR does not support ring groups.
656 * But we will use the array to save RSS context IDs.
658 if (BNXT_CHIP_THOR(bp))
659 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
661 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
663 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
667 rc = bnxt_alloc_hwrm_rings(bp);
669 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
673 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
675 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
679 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
682 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
683 if (bp->rx_cos_queue[i].id != 0xff) {
684 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
688 "Num pools more than FW profile\n");
692 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
698 rc = bnxt_mq_rx_configure(bp);
700 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
704 /* VNIC configuration */
705 for (i = 0; i < bp->nr_vnics; i++) {
706 rc = bnxt_setup_one_vnic(bp, i);
711 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
714 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
718 /* check and configure queue intr-vector mapping */
719 if ((rte_intr_cap_multiple(intr_handle) ||
720 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
721 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
722 intr_vector = bp->eth_dev->data->nb_rx_queues;
723 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
724 if (intr_vector > bp->rx_cp_nr_rings) {
725 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
729 rc = rte_intr_efd_enable(intr_handle, intr_vector);
734 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
735 intr_handle->intr_vec =
736 rte_zmalloc("intr_vec",
737 bp->eth_dev->data->nb_rx_queues *
739 if (intr_handle->intr_vec == NULL) {
740 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
741 " intr_vec", bp->eth_dev->data->nb_rx_queues);
745 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
746 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
747 intr_handle->intr_vec, intr_handle->nb_efd,
748 intr_handle->max_intr);
749 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
751 intr_handle->intr_vec[queue_id] =
752 vec + BNXT_RX_VEC_START;
753 if (vec < base + intr_handle->nb_efd - 1)
758 /* enable uio/vfio intr/eventfd mapping */
759 rc = rte_intr_enable(intr_handle);
760 #ifndef RTE_EXEC_ENV_FREEBSD
761 /* In FreeBSD OS, nic_uio driver does not support interrupts */
766 rc = bnxt_update_phy_setting(bp);
770 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
772 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
777 rte_free(intr_handle->intr_vec);
779 rte_intr_efd_disable(intr_handle);
781 /* Some of the error status returned by FW may not be from errno.h */
788 static int bnxt_shutdown_nic(struct bnxt *bp)
790 bnxt_free_all_hwrm_resources(bp);
791 bnxt_free_all_filters(bp);
792 bnxt_free_all_vnics(bp);
797 * Device configuration and status function
800 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
802 uint32_t link_speed = bp->link_info->support_speeds;
803 uint32_t speed_capa = 0;
805 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
806 speed_capa |= ETH_LINK_SPEED_100M;
807 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
808 speed_capa |= ETH_LINK_SPEED_100M_HD;
809 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
810 speed_capa |= ETH_LINK_SPEED_1G;
811 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
812 speed_capa |= ETH_LINK_SPEED_2_5G;
813 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
814 speed_capa |= ETH_LINK_SPEED_10G;
815 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
816 speed_capa |= ETH_LINK_SPEED_20G;
817 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
818 speed_capa |= ETH_LINK_SPEED_25G;
819 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
820 speed_capa |= ETH_LINK_SPEED_40G;
821 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
822 speed_capa |= ETH_LINK_SPEED_50G;
823 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
824 speed_capa |= ETH_LINK_SPEED_100G;
825 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
826 speed_capa |= ETH_LINK_SPEED_200G;
828 if (bp->link_info->auto_mode ==
829 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
830 speed_capa |= ETH_LINK_SPEED_FIXED;
832 speed_capa |= ETH_LINK_SPEED_AUTONEG;
837 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
838 struct rte_eth_dev_info *dev_info)
840 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
841 struct bnxt *bp = eth_dev->data->dev_private;
842 uint16_t max_vnics, i, j, vpool, vrxq;
843 unsigned int max_rx_rings;
846 rc = is_bnxt_in_error(bp);
851 dev_info->max_mac_addrs = bp->max_l2_ctx;
852 dev_info->max_hash_mac_addrs = 0;
854 /* PF/VF specifics */
856 dev_info->max_vfs = pdev->max_vfs;
858 max_rx_rings = BNXT_MAX_RINGS(bp);
859 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
860 dev_info->max_rx_queues = max_rx_rings;
861 dev_info->max_tx_queues = max_rx_rings;
862 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
863 dev_info->hash_key_size = 40;
864 max_vnics = bp->max_vnics;
867 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
868 dev_info->max_mtu = BNXT_MAX_MTU;
870 /* Fast path specifics */
871 dev_info->min_rx_bufsize = 1;
872 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
874 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
875 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
876 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
877 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
878 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
880 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
883 dev_info->default_rxconf = (struct rte_eth_rxconf) {
889 .rx_free_thresh = 32,
890 /* If no descriptors available, pkts are dropped by default */
894 dev_info->default_txconf = (struct rte_eth_txconf) {
900 .tx_free_thresh = 32,
903 eth_dev->data->dev_conf.intr_conf.lsc = 1;
905 eth_dev->data->dev_conf.intr_conf.rxq = 1;
906 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
907 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
908 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
909 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
911 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
912 dev_info->switch_info.name = eth_dev->device->name;
913 dev_info->switch_info.domain_id = bp->switch_domain_id;
914 dev_info->switch_info.port_id =
915 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
916 BNXT_SWITCH_PORT_ID_TRUSTED_VF;
922 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
923 * need further investigation.
927 vpool = 64; /* ETH_64_POOLS */
928 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
929 for (i = 0; i < 4; vpool >>= 1, i++) {
930 if (max_vnics > vpool) {
931 for (j = 0; j < 5; vrxq >>= 1, j++) {
932 if (dev_info->max_rx_queues > vrxq) {
938 /* Not enough resources to support VMDq */
942 /* Not enough resources to support VMDq */
946 dev_info->max_vmdq_pools = vpool;
947 dev_info->vmdq_queue_num = vrxq;
949 dev_info->vmdq_pool_base = 0;
950 dev_info->vmdq_queue_base = 0;
955 /* Configure the device based on the configuration provided */
956 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
958 struct bnxt *bp = eth_dev->data->dev_private;
959 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
962 bp->rx_queues = (void *)eth_dev->data->rx_queues;
963 bp->tx_queues = (void *)eth_dev->data->tx_queues;
964 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
965 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
967 rc = is_bnxt_in_error(bp);
971 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
972 rc = bnxt_hwrm_check_vf_rings(bp);
974 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
978 /* If a resource has already been allocated - in this case
979 * it is the async completion ring, free it. Reallocate it after
980 * resource reservation. This will ensure the resource counts
981 * are calculated correctly.
984 pthread_mutex_lock(&bp->def_cp_lock);
986 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
987 bnxt_disable_int(bp);
988 bnxt_free_cp_ring(bp, bp->async_cp_ring);
991 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
993 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
994 pthread_mutex_unlock(&bp->def_cp_lock);
998 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
999 rc = bnxt_alloc_async_cp_ring(bp);
1001 pthread_mutex_unlock(&bp->def_cp_lock);
1004 bnxt_enable_int(bp);
1007 pthread_mutex_unlock(&bp->def_cp_lock);
1009 /* legacy driver needs to get updated values */
1010 rc = bnxt_hwrm_func_qcaps(bp);
1012 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
1017 /* Inherit new configurations */
1018 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1019 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1020 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1021 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1022 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1024 goto resource_error;
1026 if (BNXT_HAS_RING_GRPS(bp) &&
1027 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1028 goto resource_error;
1030 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1031 bp->max_vnics < eth_dev->data->nb_rx_queues)
1032 goto resource_error;
1034 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1035 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1037 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1038 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1039 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1041 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1042 eth_dev->data->mtu =
1043 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1044 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1046 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1052 "Insufficient resources to support requested config\n");
1054 "Num Queues Requested: Tx %d, Rx %d\n",
1055 eth_dev->data->nb_tx_queues,
1056 eth_dev->data->nb_rx_queues);
1058 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1059 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1060 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1064 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1066 struct rte_eth_link *link = ð_dev->data->dev_link;
1068 if (link->link_status)
1069 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1070 eth_dev->data->port_id,
1071 (uint32_t)link->link_speed,
1072 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1073 ("full-duplex") : ("half-duplex\n"));
1075 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1076 eth_dev->data->port_id);
1080 * Determine whether the current configuration requires support for scattered
1081 * receive; return 1 if scattered receive is required and 0 if not.
1083 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1088 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1091 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1092 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1094 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1095 RTE_PKTMBUF_HEADROOM);
1096 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1102 static eth_rx_burst_t
1103 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1105 struct bnxt *bp = eth_dev->data->dev_private;
1107 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1108 #ifndef RTE_LIBRTE_IEEE1588
1110 * Vector mode receive can be enabled only if scatter rx is not
1111 * in use and rx offloads are limited to VLAN stripping and
1114 if (!eth_dev->data->scattered_rx &&
1115 !(eth_dev->data->dev_conf.rxmode.offloads &
1116 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1117 DEV_RX_OFFLOAD_KEEP_CRC |
1118 DEV_RX_OFFLOAD_JUMBO_FRAME |
1119 DEV_RX_OFFLOAD_IPV4_CKSUM |
1120 DEV_RX_OFFLOAD_UDP_CKSUM |
1121 DEV_RX_OFFLOAD_TCP_CKSUM |
1122 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1123 DEV_RX_OFFLOAD_RSS_HASH |
1124 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1125 !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp)) {
1126 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1127 eth_dev->data->port_id);
1128 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1129 return bnxt_recv_pkts_vec;
1131 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1132 eth_dev->data->port_id);
1134 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1135 eth_dev->data->port_id,
1136 eth_dev->data->scattered_rx,
1137 eth_dev->data->dev_conf.rxmode.offloads);
1140 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1141 return bnxt_recv_pkts;
1144 static eth_tx_burst_t
1145 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1147 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1148 #ifndef RTE_LIBRTE_IEEE1588
1149 struct bnxt *bp = eth_dev->data->dev_private;
1152 * Vector mode transmit can be enabled only if not using scatter rx
1155 if (!eth_dev->data->scattered_rx &&
1156 !eth_dev->data->dev_conf.txmode.offloads &&
1157 !BNXT_TRUFLOW_EN(bp)) {
1158 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1159 eth_dev->data->port_id);
1160 return bnxt_xmit_pkts_vec;
1162 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1163 eth_dev->data->port_id);
1165 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1166 eth_dev->data->port_id,
1167 eth_dev->data->scattered_rx,
1168 eth_dev->data->dev_conf.txmode.offloads);
1171 return bnxt_xmit_pkts;
1174 static int bnxt_handle_if_change_status(struct bnxt *bp)
1178 /* Since fw has undergone a reset and lost all contexts,
1179 * set fatal flag to not issue hwrm during cleanup
1181 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1182 bnxt_uninit_resources(bp, true);
1184 /* clear fatal flag so that re-init happens */
1185 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1186 rc = bnxt_init_resources(bp, true);
1188 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1193 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1195 struct bnxt *bp = eth_dev->data->dev_private;
1196 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1198 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1200 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1201 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1205 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1207 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1208 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1212 rc = bnxt_hwrm_if_change(bp, true);
1213 if (rc == 0 || rc != -EAGAIN)
1216 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1217 } while (retry_cnt--);
1222 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1223 rc = bnxt_handle_if_change_status(bp);
1228 bnxt_enable_int(bp);
1230 rc = bnxt_init_chip(bp);
1234 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1235 eth_dev->data->dev_started = 1;
1237 bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1239 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1240 vlan_mask |= ETH_VLAN_FILTER_MASK;
1241 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1242 vlan_mask |= ETH_VLAN_STRIP_MASK;
1243 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1247 /* Initialize bnxt ULP port details */
1248 rc = bnxt_ulp_port_init(bp);
1252 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1253 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1255 pthread_mutex_lock(&bp->def_cp_lock);
1256 bnxt_schedule_fw_health_check(bp);
1257 pthread_mutex_unlock(&bp->def_cp_lock);
1262 bnxt_shutdown_nic(bp);
1263 bnxt_free_tx_mbufs(bp);
1264 bnxt_free_rx_mbufs(bp);
1265 bnxt_hwrm_if_change(bp, false);
1266 eth_dev->data->dev_started = 0;
1270 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1272 struct bnxt *bp = eth_dev->data->dev_private;
1275 if (!bp->link_info->link_up)
1276 rc = bnxt_set_hwrm_link_config(bp, true);
1278 eth_dev->data->dev_link.link_status = 1;
1280 bnxt_print_link_info(eth_dev);
1284 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1286 struct bnxt *bp = eth_dev->data->dev_private;
1288 eth_dev->data->dev_link.link_status = 0;
1289 bnxt_set_hwrm_link_config(bp, false);
1290 bp->link_info->link_up = 0;
1295 static void bnxt_free_switch_domain(struct bnxt *bp)
1297 if (bp->switch_domain_id)
1298 rte_eth_switch_domain_free(bp->switch_domain_id);
1301 /* Unload the driver, release resources */
1302 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1304 struct bnxt *bp = eth_dev->data->dev_private;
1305 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1306 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1308 eth_dev->data->dev_started = 0;
1309 eth_dev->data->scattered_rx = 0;
1311 /* Prevent crashes when queues are still in use */
1312 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1313 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1315 bnxt_disable_int(bp);
1317 /* disable uio/vfio intr/eventfd mapping */
1318 rte_intr_disable(intr_handle);
1320 /* Stop the child representors for this device */
1321 bnxt_vf_rep_stop_all(bp);
1323 /* delete the bnxt ULP port details */
1324 bnxt_ulp_port_deinit(bp);
1326 bnxt_cancel_fw_health_check(bp);
1328 bnxt_dev_set_link_down_op(eth_dev);
1330 /* Wait for link to be reset and the async notification to process.
1331 * During reset recovery, there is no need to wait and
1332 * VF/NPAR functions do not have privilege to change PHY config.
1334 if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1335 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1337 /* Clean queue intr-vector mapping */
1338 rte_intr_efd_disable(intr_handle);
1339 if (intr_handle->intr_vec != NULL) {
1340 rte_free(intr_handle->intr_vec);
1341 intr_handle->intr_vec = NULL;
1344 bnxt_hwrm_port_clr_stats(bp);
1345 bnxt_free_tx_mbufs(bp);
1346 bnxt_free_rx_mbufs(bp);
1347 /* Process any remaining notifications in default completion queue */
1348 bnxt_int_handler(eth_dev);
1349 bnxt_shutdown_nic(bp);
1350 bnxt_hwrm_if_change(bp, false);
1352 rte_free(bp->mark_table);
1353 bp->mark_table = NULL;
1355 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1356 bp->rx_cosq_cnt = 0;
1357 /* All filters are deleted on a port stop. */
1358 if (BNXT_FLOW_XSTATS_EN(bp))
1359 bp->flow_stat->flow_count = 0;
1362 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1364 struct bnxt *bp = eth_dev->data->dev_private;
1366 /* cancel the recovery handler before remove dev */
1367 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1368 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1369 bnxt_cancel_fc_thread(bp);
1371 if (eth_dev->data->dev_started)
1372 bnxt_dev_stop_op(eth_dev);
1374 bnxt_free_switch_domain(bp);
1376 bnxt_uninit_resources(bp, false);
1378 bnxt_free_leds_info(bp);
1379 bnxt_free_cos_queues(bp);
1380 bnxt_free_link_info(bp);
1381 bnxt_free_pf_info(bp);
1382 bnxt_free_parent_info(bp);
1384 eth_dev->dev_ops = NULL;
1385 eth_dev->rx_pkt_burst = NULL;
1386 eth_dev->tx_pkt_burst = NULL;
1388 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1389 bp->tx_mem_zone = NULL;
1390 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1391 bp->rx_mem_zone = NULL;
1393 bnxt_hwrm_free_vf_info(bp);
1395 rte_free(bp->grp_info);
1396 bp->grp_info = NULL;
1399 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1402 struct bnxt *bp = eth_dev->data->dev_private;
1403 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1404 struct bnxt_vnic_info *vnic;
1405 struct bnxt_filter_info *filter, *temp_filter;
1408 if (is_bnxt_in_error(bp))
1412 * Loop through all VNICs from the specified filter flow pools to
1413 * remove the corresponding MAC addr filter
1415 for (i = 0; i < bp->nr_vnics; i++) {
1416 if (!(pool_mask & (1ULL << i)))
1419 vnic = &bp->vnic_info[i];
1420 filter = STAILQ_FIRST(&vnic->filter);
1422 temp_filter = STAILQ_NEXT(filter, next);
1423 if (filter->mac_index == index) {
1424 STAILQ_REMOVE(&vnic->filter, filter,
1425 bnxt_filter_info, next);
1426 bnxt_hwrm_clear_l2_filter(bp, filter);
1427 bnxt_free_filter(bp, filter);
1429 filter = temp_filter;
1434 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1435 struct rte_ether_addr *mac_addr, uint32_t index,
1438 struct bnxt_filter_info *filter;
1441 /* Attach requested MAC address to the new l2_filter */
1442 STAILQ_FOREACH(filter, &vnic->filter, next) {
1443 if (filter->mac_index == index) {
1445 "MAC addr already existed for pool %d\n",
1451 filter = bnxt_alloc_filter(bp);
1453 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1457 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1458 * if the MAC that's been programmed now is a different one, then,
1459 * copy that addr to filter->l2_addr
1462 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1463 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1465 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1467 filter->mac_index = index;
1468 if (filter->mac_index == 0)
1469 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1471 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1473 bnxt_free_filter(bp, filter);
1479 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1480 struct rte_ether_addr *mac_addr,
1481 uint32_t index, uint32_t pool)
1483 struct bnxt *bp = eth_dev->data->dev_private;
1484 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1487 rc = is_bnxt_in_error(bp);
1491 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1492 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1497 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1501 /* Filter settings will get applied when port is started */
1502 if (!eth_dev->data->dev_started)
1505 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1510 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1511 bool exp_link_status)
1514 struct bnxt *bp = eth_dev->data->dev_private;
1515 struct rte_eth_link new;
1516 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1517 BNXT_LINK_DOWN_WAIT_CNT;
1519 rc = is_bnxt_in_error(bp);
1523 memset(&new, 0, sizeof(new));
1525 /* Retrieve link info from hardware */
1526 rc = bnxt_get_hwrm_link_config(bp, &new);
1528 new.link_speed = ETH_LINK_SPEED_100M;
1529 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1531 "Failed to retrieve link rc = 0x%x!\n", rc);
1535 if (!wait_to_complete || new.link_status == exp_link_status)
1538 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1542 /* Timed out or success */
1543 if (new.link_status != eth_dev->data->dev_link.link_status ||
1544 new.link_speed != eth_dev->data->dev_link.link_speed) {
1545 rte_eth_linkstatus_set(eth_dev, &new);
1547 rte_eth_dev_callback_process(eth_dev,
1548 RTE_ETH_EVENT_INTR_LSC,
1551 bnxt_print_link_info(eth_dev);
1557 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1558 int wait_to_complete)
1560 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1563 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1565 struct bnxt *bp = eth_dev->data->dev_private;
1566 struct bnxt_vnic_info *vnic;
1570 rc = is_bnxt_in_error(bp);
1574 /* Filter settings will get applied when port is started */
1575 if (!eth_dev->data->dev_started)
1578 if (bp->vnic_info == NULL)
1581 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1583 old_flags = vnic->flags;
1584 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1585 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1587 vnic->flags = old_flags;
1592 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1594 struct bnxt *bp = eth_dev->data->dev_private;
1595 struct bnxt_vnic_info *vnic;
1599 rc = is_bnxt_in_error(bp);
1603 /* Filter settings will get applied when port is started */
1604 if (!eth_dev->data->dev_started)
1607 if (bp->vnic_info == NULL)
1610 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1612 old_flags = vnic->flags;
1613 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1614 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1616 vnic->flags = old_flags;
1621 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1623 struct bnxt *bp = eth_dev->data->dev_private;
1624 struct bnxt_vnic_info *vnic;
1628 rc = is_bnxt_in_error(bp);
1632 /* Filter settings will get applied when port is started */
1633 if (!eth_dev->data->dev_started)
1636 if (bp->vnic_info == NULL)
1639 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1641 old_flags = vnic->flags;
1642 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1643 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1645 vnic->flags = old_flags;
1650 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1652 struct bnxt *bp = eth_dev->data->dev_private;
1653 struct bnxt_vnic_info *vnic;
1657 rc = is_bnxt_in_error(bp);
1661 /* Filter settings will get applied when port is started */
1662 if (!eth_dev->data->dev_started)
1665 if (bp->vnic_info == NULL)
1668 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1670 old_flags = vnic->flags;
1671 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1672 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1674 vnic->flags = old_flags;
1679 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1680 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1682 if (qid >= bp->rx_nr_rings)
1685 return bp->eth_dev->data->rx_queues[qid];
1688 /* Return rxq corresponding to a given rss table ring/group ID. */
1689 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1691 struct bnxt_rx_queue *rxq;
1694 if (!BNXT_HAS_RING_GRPS(bp)) {
1695 for (i = 0; i < bp->rx_nr_rings; i++) {
1696 rxq = bp->eth_dev->data->rx_queues[i];
1697 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1701 for (i = 0; i < bp->rx_nr_rings; i++) {
1702 if (bp->grp_info[i].fw_grp_id == fwr)
1707 return INVALID_HW_RING_ID;
1710 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1711 struct rte_eth_rss_reta_entry64 *reta_conf,
1714 struct bnxt *bp = eth_dev->data->dev_private;
1715 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1716 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1717 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1721 rc = is_bnxt_in_error(bp);
1725 if (!vnic->rss_table)
1728 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1731 if (reta_size != tbl_size) {
1732 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1733 "(%d) must equal the size supported by the hardware "
1734 "(%d)\n", reta_size, tbl_size);
1738 for (i = 0; i < reta_size; i++) {
1739 struct bnxt_rx_queue *rxq;
1741 idx = i / RTE_RETA_GROUP_SIZE;
1742 sft = i % RTE_RETA_GROUP_SIZE;
1744 if (!(reta_conf[idx].mask & (1ULL << sft)))
1747 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1749 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1753 if (BNXT_CHIP_THOR(bp)) {
1754 vnic->rss_table[i * 2] =
1755 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1756 vnic->rss_table[i * 2 + 1] =
1757 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1759 vnic->rss_table[i] =
1760 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1764 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1768 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1769 struct rte_eth_rss_reta_entry64 *reta_conf,
1772 struct bnxt *bp = eth_dev->data->dev_private;
1773 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1774 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1775 uint16_t idx, sft, i;
1778 rc = is_bnxt_in_error(bp);
1782 /* Retrieve from the default VNIC */
1785 if (!vnic->rss_table)
1788 if (reta_size != tbl_size) {
1789 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1790 "(%d) must equal the size supported by the hardware "
1791 "(%d)\n", reta_size, tbl_size);
1795 for (idx = 0, i = 0; i < reta_size; i++) {
1796 idx = i / RTE_RETA_GROUP_SIZE;
1797 sft = i % RTE_RETA_GROUP_SIZE;
1799 if (reta_conf[idx].mask & (1ULL << sft)) {
1802 if (BNXT_CHIP_THOR(bp))
1803 qid = bnxt_rss_to_qid(bp,
1804 vnic->rss_table[i * 2]);
1806 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1808 if (qid == INVALID_HW_RING_ID) {
1809 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1812 reta_conf[idx].reta[sft] = qid;
1819 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1820 struct rte_eth_rss_conf *rss_conf)
1822 struct bnxt *bp = eth_dev->data->dev_private;
1823 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1824 struct bnxt_vnic_info *vnic;
1827 rc = is_bnxt_in_error(bp);
1832 * If RSS enablement were different than dev_configure,
1833 * then return -EINVAL
1835 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1836 if (!rss_conf->rss_hf)
1837 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1839 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1843 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1844 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
1848 /* Update the default RSS VNIC(s) */
1849 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1850 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1853 * If hashkey is not specified, use the previously configured
1856 if (!rss_conf->rss_key)
1859 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1861 "Invalid hashkey length, should be 16 bytes\n");
1864 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1867 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1871 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1872 struct rte_eth_rss_conf *rss_conf)
1874 struct bnxt *bp = eth_dev->data->dev_private;
1875 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1877 uint32_t hash_types;
1879 rc = is_bnxt_in_error(bp);
1883 /* RSS configuration is the same for all VNICs */
1884 if (vnic && vnic->rss_hash_key) {
1885 if (rss_conf->rss_key) {
1886 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1887 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1888 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1891 hash_types = vnic->hash_type;
1892 rss_conf->rss_hf = 0;
1893 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1894 rss_conf->rss_hf |= ETH_RSS_IPV4;
1895 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1897 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1898 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1900 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1902 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1903 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1905 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1907 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1908 rss_conf->rss_hf |= ETH_RSS_IPV6;
1909 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1911 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1912 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1914 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1916 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1917 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1919 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1923 "Unknown RSS config from firmware (%08x), RSS disabled",
1928 rss_conf->rss_hf = 0;
1933 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1934 struct rte_eth_fc_conf *fc_conf)
1936 struct bnxt *bp = dev->data->dev_private;
1937 struct rte_eth_link link_info;
1940 rc = is_bnxt_in_error(bp);
1944 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1948 memset(fc_conf, 0, sizeof(*fc_conf));
1949 if (bp->link_info->auto_pause)
1950 fc_conf->autoneg = 1;
1951 switch (bp->link_info->pause) {
1953 fc_conf->mode = RTE_FC_NONE;
1955 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1956 fc_conf->mode = RTE_FC_TX_PAUSE;
1958 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1959 fc_conf->mode = RTE_FC_RX_PAUSE;
1961 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1962 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1963 fc_conf->mode = RTE_FC_FULL;
1969 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1970 struct rte_eth_fc_conf *fc_conf)
1972 struct bnxt *bp = dev->data->dev_private;
1975 rc = is_bnxt_in_error(bp);
1979 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1980 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1984 switch (fc_conf->mode) {
1986 bp->link_info->auto_pause = 0;
1987 bp->link_info->force_pause = 0;
1989 case RTE_FC_RX_PAUSE:
1990 if (fc_conf->autoneg) {
1991 bp->link_info->auto_pause =
1992 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1993 bp->link_info->force_pause = 0;
1995 bp->link_info->auto_pause = 0;
1996 bp->link_info->force_pause =
1997 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2000 case RTE_FC_TX_PAUSE:
2001 if (fc_conf->autoneg) {
2002 bp->link_info->auto_pause =
2003 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2004 bp->link_info->force_pause = 0;
2006 bp->link_info->auto_pause = 0;
2007 bp->link_info->force_pause =
2008 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2012 if (fc_conf->autoneg) {
2013 bp->link_info->auto_pause =
2014 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2015 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2016 bp->link_info->force_pause = 0;
2018 bp->link_info->auto_pause = 0;
2019 bp->link_info->force_pause =
2020 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2021 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2025 return bnxt_set_hwrm_link_config(bp, true);
2028 /* Add UDP tunneling port */
2030 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2031 struct rte_eth_udp_tunnel *udp_tunnel)
2033 struct bnxt *bp = eth_dev->data->dev_private;
2034 uint16_t tunnel_type = 0;
2037 rc = is_bnxt_in_error(bp);
2041 switch (udp_tunnel->prot_type) {
2042 case RTE_TUNNEL_TYPE_VXLAN:
2043 if (bp->vxlan_port_cnt) {
2044 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2045 udp_tunnel->udp_port);
2046 if (bp->vxlan_port != udp_tunnel->udp_port) {
2047 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2050 bp->vxlan_port_cnt++;
2054 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2055 bp->vxlan_port_cnt++;
2057 case RTE_TUNNEL_TYPE_GENEVE:
2058 if (bp->geneve_port_cnt) {
2059 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2060 udp_tunnel->udp_port);
2061 if (bp->geneve_port != udp_tunnel->udp_port) {
2062 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2065 bp->geneve_port_cnt++;
2069 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2070 bp->geneve_port_cnt++;
2073 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2076 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2082 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2083 struct rte_eth_udp_tunnel *udp_tunnel)
2085 struct bnxt *bp = eth_dev->data->dev_private;
2086 uint16_t tunnel_type = 0;
2090 rc = is_bnxt_in_error(bp);
2094 switch (udp_tunnel->prot_type) {
2095 case RTE_TUNNEL_TYPE_VXLAN:
2096 if (!bp->vxlan_port_cnt) {
2097 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2100 if (bp->vxlan_port != udp_tunnel->udp_port) {
2101 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2102 udp_tunnel->udp_port, bp->vxlan_port);
2105 if (--bp->vxlan_port_cnt)
2109 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2110 port = bp->vxlan_fw_dst_port_id;
2112 case RTE_TUNNEL_TYPE_GENEVE:
2113 if (!bp->geneve_port_cnt) {
2114 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2117 if (bp->geneve_port != udp_tunnel->udp_port) {
2118 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2119 udp_tunnel->udp_port, bp->geneve_port);
2122 if (--bp->geneve_port_cnt)
2126 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2127 port = bp->geneve_fw_dst_port_id;
2130 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2134 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2137 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2140 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2141 bp->geneve_port = 0;
2146 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2148 struct bnxt_filter_info *filter;
2149 struct bnxt_vnic_info *vnic;
2151 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2153 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2154 filter = STAILQ_FIRST(&vnic->filter);
2156 /* Search for this matching MAC+VLAN filter */
2157 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2158 /* Delete the filter */
2159 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2162 STAILQ_REMOVE(&vnic->filter, filter,
2163 bnxt_filter_info, next);
2164 bnxt_free_filter(bp, filter);
2166 "Deleted vlan filter for %d\n",
2170 filter = STAILQ_NEXT(filter, next);
2175 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2177 struct bnxt_filter_info *filter;
2178 struct bnxt_vnic_info *vnic;
2180 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2181 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2182 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2184 /* Implementation notes on the use of VNIC in this command:
2186 * By default, these filters belong to default vnic for the function.
2187 * Once these filters are set up, only destination VNIC can be modified.
2188 * If the destination VNIC is not specified in this command,
2189 * then the HWRM shall only create an l2 context id.
2192 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2193 filter = STAILQ_FIRST(&vnic->filter);
2194 /* Check if the VLAN has already been added */
2196 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2199 filter = STAILQ_NEXT(filter, next);
2202 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2203 * command to create MAC+VLAN filter with the right flags, enables set.
2205 filter = bnxt_alloc_filter(bp);
2208 "MAC/VLAN filter alloc failed\n");
2211 /* MAC + VLAN ID filter */
2212 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2213 * untagged packets are received
2215 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2216 * packets and only the programmed vlan's packets are received
2218 filter->l2_ivlan = vlan_id;
2219 filter->l2_ivlan_mask = 0x0FFF;
2220 filter->enables |= en;
2221 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2223 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2225 /* Free the newly allocated filter as we were
2226 * not able to create the filter in hardware.
2228 bnxt_free_filter(bp, filter);
2232 filter->mac_index = 0;
2233 /* Add this new filter to the list */
2235 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2237 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2240 "Added Vlan filter for %d\n", vlan_id);
2244 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2245 uint16_t vlan_id, int on)
2247 struct bnxt *bp = eth_dev->data->dev_private;
2250 rc = is_bnxt_in_error(bp);
2254 if (!eth_dev->data->dev_started) {
2255 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2259 /* These operations apply to ALL existing MAC/VLAN filters */
2261 return bnxt_add_vlan_filter(bp, vlan_id);
2263 return bnxt_del_vlan_filter(bp, vlan_id);
2266 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2267 struct bnxt_vnic_info *vnic)
2269 struct bnxt_filter_info *filter;
2272 filter = STAILQ_FIRST(&vnic->filter);
2274 if (filter->mac_index == 0 &&
2275 !memcmp(filter->l2_addr, bp->mac_addr,
2276 RTE_ETHER_ADDR_LEN)) {
2277 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2279 STAILQ_REMOVE(&vnic->filter, filter,
2280 bnxt_filter_info, next);
2281 bnxt_free_filter(bp, filter);
2285 filter = STAILQ_NEXT(filter, next);
2291 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2293 struct bnxt_vnic_info *vnic;
2297 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2298 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2299 /* Remove any VLAN filters programmed */
2300 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2301 bnxt_del_vlan_filter(bp, i);
2303 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2307 /* Default filter will allow packets that match the
2308 * dest mac. So, it has to be deleted, otherwise, we
2309 * will endup receiving vlan packets for which the
2310 * filter is not programmed, when hw-vlan-filter
2311 * configuration is ON
2313 bnxt_del_dflt_mac_filter(bp, vnic);
2314 /* This filter will allow only untagged packets */
2315 bnxt_add_vlan_filter(bp, 0);
2317 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2318 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2323 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2325 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2329 /* Destroy vnic filters and vnic */
2330 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2331 DEV_RX_OFFLOAD_VLAN_FILTER) {
2332 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2333 bnxt_del_vlan_filter(bp, i);
2335 bnxt_del_dflt_mac_filter(bp, vnic);
2337 rc = bnxt_hwrm_vnic_free(bp, vnic);
2341 rte_free(vnic->fw_grp_ids);
2342 vnic->fw_grp_ids = NULL;
2344 vnic->rx_queue_cnt = 0;
2350 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2352 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2355 /* Destroy, recreate and reconfigure the default vnic */
2356 rc = bnxt_free_one_vnic(bp, 0);
2360 /* default vnic 0 */
2361 rc = bnxt_setup_one_vnic(bp, 0);
2365 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2366 DEV_RX_OFFLOAD_VLAN_FILTER) {
2367 rc = bnxt_add_vlan_filter(bp, 0);
2370 rc = bnxt_restore_vlan_filters(bp);
2374 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2379 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2383 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2384 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2390 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2392 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2393 struct bnxt *bp = dev->data->dev_private;
2396 rc = is_bnxt_in_error(bp);
2400 /* Filter settings will get applied when port is started */
2401 if (!dev->data->dev_started)
2404 if (mask & ETH_VLAN_FILTER_MASK) {
2405 /* Enable or disable VLAN filtering */
2406 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2411 if (mask & ETH_VLAN_STRIP_MASK) {
2412 /* Enable or disable VLAN stripping */
2413 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2418 if (mask & ETH_VLAN_EXTEND_MASK) {
2419 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2420 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2422 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2429 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2432 struct bnxt *bp = dev->data->dev_private;
2433 int qinq = dev->data->dev_conf.rxmode.offloads &
2434 DEV_RX_OFFLOAD_VLAN_EXTEND;
2436 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2437 vlan_type != ETH_VLAN_TYPE_OUTER) {
2439 "Unsupported vlan type.");
2444 "QinQ not enabled. Needs to be ON as we can "
2445 "accelerate only outer vlan\n");
2449 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2451 case RTE_ETHER_TYPE_QINQ:
2453 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2455 case RTE_ETHER_TYPE_VLAN:
2457 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2459 case RTE_ETHER_TYPE_QINQ1:
2461 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2463 case RTE_ETHER_TYPE_QINQ2:
2465 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2467 case RTE_ETHER_TYPE_QINQ3:
2469 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2472 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2475 bp->outer_tpid_bd |= tpid;
2476 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2477 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2479 "Can accelerate only outer vlan in QinQ\n");
2487 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2488 struct rte_ether_addr *addr)
2490 struct bnxt *bp = dev->data->dev_private;
2491 /* Default Filter is tied to VNIC 0 */
2492 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2495 rc = is_bnxt_in_error(bp);
2499 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2502 if (rte_is_zero_ether_addr(addr))
2505 /* Filter settings will get applied when port is started */
2506 if (!dev->data->dev_started)
2509 /* Check if the requested MAC is already added */
2510 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2513 /* Destroy filter and re-create it */
2514 bnxt_del_dflt_mac_filter(bp, vnic);
2516 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2517 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2518 /* This filter will allow only untagged packets */
2519 rc = bnxt_add_vlan_filter(bp, 0);
2521 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2524 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2529 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2530 struct rte_ether_addr *mc_addr_set,
2531 uint32_t nb_mc_addr)
2533 struct bnxt *bp = eth_dev->data->dev_private;
2534 char *mc_addr_list = (char *)mc_addr_set;
2535 struct bnxt_vnic_info *vnic;
2536 uint32_t off = 0, i = 0;
2539 rc = is_bnxt_in_error(bp);
2543 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2545 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2546 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2550 /* TODO Check for Duplicate mcast addresses */
2551 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2552 for (i = 0; i < nb_mc_addr; i++) {
2553 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2554 RTE_ETHER_ADDR_LEN);
2555 off += RTE_ETHER_ADDR_LEN;
2558 vnic->mc_addr_cnt = i;
2559 if (vnic->mc_addr_cnt)
2560 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2562 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2565 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2569 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2571 struct bnxt *bp = dev->data->dev_private;
2572 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2573 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2574 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2575 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2578 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2579 fw_major, fw_minor, fw_updt, fw_rsvd);
2581 ret += 1; /* add the size of '\0' */
2582 if (fw_size < (uint32_t)ret)
2589 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2590 struct rte_eth_rxq_info *qinfo)
2592 struct bnxt *bp = dev->data->dev_private;
2593 struct bnxt_rx_queue *rxq;
2595 if (is_bnxt_in_error(bp))
2598 rxq = dev->data->rx_queues[queue_id];
2600 qinfo->mp = rxq->mb_pool;
2601 qinfo->scattered_rx = dev->data->scattered_rx;
2602 qinfo->nb_desc = rxq->nb_rx_desc;
2604 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2605 qinfo->conf.rx_drop_en = 0;
2606 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2610 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2611 struct rte_eth_txq_info *qinfo)
2613 struct bnxt *bp = dev->data->dev_private;
2614 struct bnxt_tx_queue *txq;
2616 if (is_bnxt_in_error(bp))
2619 txq = dev->data->tx_queues[queue_id];
2621 qinfo->nb_desc = txq->nb_tx_desc;
2623 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2624 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2625 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2627 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2628 qinfo->conf.tx_rs_thresh = 0;
2629 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2632 static const struct {
2633 eth_rx_burst_t pkt_burst;
2635 } bnxt_rx_burst_info[] = {
2636 {bnxt_recv_pkts, "Scalar"},
2637 #if defined(RTE_ARCH_X86)
2638 {bnxt_recv_pkts_vec, "Vector SSE"},
2639 #elif defined(RTE_ARCH_ARM64)
2640 {bnxt_recv_pkts_vec, "Vector Neon"},
2645 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2646 struct rte_eth_burst_mode *mode)
2648 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2651 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2652 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2653 snprintf(mode->info, sizeof(mode->info), "%s",
2654 bnxt_rx_burst_info[i].info);
2662 static const struct {
2663 eth_tx_burst_t pkt_burst;
2665 } bnxt_tx_burst_info[] = {
2666 {bnxt_xmit_pkts, "Scalar"},
2667 #if defined(RTE_ARCH_X86)
2668 {bnxt_xmit_pkts_vec, "Vector SSE"},
2669 #elif defined(RTE_ARCH_ARM64)
2670 {bnxt_xmit_pkts_vec, "Vector Neon"},
2675 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2676 struct rte_eth_burst_mode *mode)
2678 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2681 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2682 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2683 snprintf(mode->info, sizeof(mode->info), "%s",
2684 bnxt_tx_burst_info[i].info);
2692 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2694 struct bnxt *bp = eth_dev->data->dev_private;
2695 uint32_t new_pkt_size;
2699 rc = is_bnxt_in_error(bp);
2703 /* Exit if receive queues are not configured yet */
2704 if (!eth_dev->data->nb_rx_queues)
2707 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2708 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2711 * Disallow any MTU change that would require scattered receive support
2712 * if it is not already enabled.
2714 if (eth_dev->data->dev_started &&
2715 !eth_dev->data->scattered_rx &&
2717 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2719 "MTU change would require scattered rx support. ");
2720 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2724 if (new_mtu > RTE_ETHER_MTU) {
2725 bp->flags |= BNXT_FLAG_JUMBO;
2726 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2727 DEV_RX_OFFLOAD_JUMBO_FRAME;
2729 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2730 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2731 bp->flags &= ~BNXT_FLAG_JUMBO;
2734 /* Is there a change in mtu setting? */
2735 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2738 for (i = 0; i < bp->nr_vnics; i++) {
2739 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2742 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2743 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2747 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2748 size -= RTE_PKTMBUF_HEADROOM;
2750 if (size < new_mtu) {
2751 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2758 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2760 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2766 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2768 struct bnxt *bp = dev->data->dev_private;
2769 uint16_t vlan = bp->vlan;
2772 rc = is_bnxt_in_error(bp);
2776 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2778 "PVID cannot be modified for this function\n");
2781 bp->vlan = on ? pvid : 0;
2783 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2790 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2792 struct bnxt *bp = dev->data->dev_private;
2795 rc = is_bnxt_in_error(bp);
2799 return bnxt_hwrm_port_led_cfg(bp, true);
2803 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2805 struct bnxt *bp = dev->data->dev_private;
2808 rc = is_bnxt_in_error(bp);
2812 return bnxt_hwrm_port_led_cfg(bp, false);
2816 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2818 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2819 uint32_t desc = 0, raw_cons = 0, cons;
2820 struct bnxt_cp_ring_info *cpr;
2821 struct bnxt_rx_queue *rxq;
2822 struct rx_pkt_cmpl *rxcmp;
2825 rc = is_bnxt_in_error(bp);
2829 rxq = dev->data->rx_queues[rx_queue_id];
2831 raw_cons = cpr->cp_raw_cons;
2834 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2835 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2836 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2838 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2850 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2852 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2853 struct bnxt_rx_ring_info *rxr;
2854 struct bnxt_cp_ring_info *cpr;
2855 struct rte_mbuf *rx_buf;
2856 struct rx_pkt_cmpl *rxcmp;
2857 uint32_t cons, cp_cons;
2863 rc = is_bnxt_in_error(rxq->bp);
2870 if (offset >= rxq->nb_rx_desc)
2873 cons = RING_CMP(cpr->cp_ring_struct, offset);
2874 cp_cons = cpr->cp_raw_cons;
2875 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2877 if (cons > cp_cons) {
2878 if (CMPL_VALID(rxcmp, cpr->valid))
2879 return RTE_ETH_RX_DESC_DONE;
2881 if (CMPL_VALID(rxcmp, !cpr->valid))
2882 return RTE_ETH_RX_DESC_DONE;
2884 rx_buf = rxr->rx_buf_ring[cons];
2885 if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2886 return RTE_ETH_RX_DESC_UNAVAIL;
2889 return RTE_ETH_RX_DESC_AVAIL;
2893 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2895 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2896 struct bnxt_tx_ring_info *txr;
2897 struct bnxt_cp_ring_info *cpr;
2898 struct bnxt_sw_tx_bd *tx_buf;
2899 struct tx_pkt_cmpl *txcmp;
2900 uint32_t cons, cp_cons;
2906 rc = is_bnxt_in_error(txq->bp);
2913 if (offset >= txq->nb_tx_desc)
2916 cons = RING_CMP(cpr->cp_ring_struct, offset);
2917 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2918 cp_cons = cpr->cp_raw_cons;
2920 if (cons > cp_cons) {
2921 if (CMPL_VALID(txcmp, cpr->valid))
2922 return RTE_ETH_TX_DESC_UNAVAIL;
2924 if (CMPL_VALID(txcmp, !cpr->valid))
2925 return RTE_ETH_TX_DESC_UNAVAIL;
2927 tx_buf = &txr->tx_buf_ring[cons];
2928 if (tx_buf->mbuf == NULL)
2929 return RTE_ETH_TX_DESC_DONE;
2931 return RTE_ETH_TX_DESC_FULL;
2934 static struct bnxt_filter_info *
2935 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2936 struct rte_eth_ethertype_filter *efilter,
2937 struct bnxt_vnic_info *vnic0,
2938 struct bnxt_vnic_info *vnic,
2941 struct bnxt_filter_info *mfilter = NULL;
2945 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2946 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2947 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2948 " ethertype filter.", efilter->ether_type);
2952 if (efilter->queue >= bp->rx_nr_rings) {
2953 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2958 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2959 vnic = &bp->vnic_info[efilter->queue];
2961 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2966 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2967 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2968 if ((!memcmp(efilter->mac_addr.addr_bytes,
2969 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2971 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2972 mfilter->ethertype == efilter->ether_type)) {
2978 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2979 if ((!memcmp(efilter->mac_addr.addr_bytes,
2980 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2981 mfilter->ethertype == efilter->ether_type &&
2983 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2997 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2998 enum rte_filter_op filter_op,
3001 struct bnxt *bp = dev->data->dev_private;
3002 struct rte_eth_ethertype_filter *efilter =
3003 (struct rte_eth_ethertype_filter *)arg;
3004 struct bnxt_filter_info *bfilter, *filter1;
3005 struct bnxt_vnic_info *vnic, *vnic0;
3008 if (filter_op == RTE_ETH_FILTER_NOP)
3012 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3017 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3018 vnic = &bp->vnic_info[efilter->queue];
3020 switch (filter_op) {
3021 case RTE_ETH_FILTER_ADD:
3022 bnxt_match_and_validate_ether_filter(bp, efilter,
3027 bfilter = bnxt_get_unused_filter(bp);
3028 if (bfilter == NULL) {
3030 "Not enough resources for a new filter.\n");
3033 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3034 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
3035 RTE_ETHER_ADDR_LEN);
3036 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
3037 RTE_ETHER_ADDR_LEN);
3038 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3039 bfilter->ethertype = efilter->ether_type;
3040 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3042 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3043 if (filter1 == NULL) {
3048 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3049 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3051 bfilter->dst_id = vnic->fw_vnic_id;
3053 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3055 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3058 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3061 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3063 case RTE_ETH_FILTER_DELETE:
3064 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3066 if (ret == -EEXIST) {
3067 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3069 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3071 bnxt_free_filter(bp, filter1);
3072 } else if (ret == 0) {
3073 PMD_DRV_LOG(ERR, "No matching filter found\n");
3077 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3083 bnxt_free_filter(bp, bfilter);
3089 parse_ntuple_filter(struct bnxt *bp,
3090 struct rte_eth_ntuple_filter *nfilter,
3091 struct bnxt_filter_info *bfilter)
3095 if (nfilter->queue >= bp->rx_nr_rings) {
3096 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3100 switch (nfilter->dst_port_mask) {
3102 bfilter->dst_port_mask = -1;
3103 bfilter->dst_port = nfilter->dst_port;
3104 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3105 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3108 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3112 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3113 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3115 switch (nfilter->proto_mask) {
3117 if (nfilter->proto == 17) /* IPPROTO_UDP */
3118 bfilter->ip_protocol = 17;
3119 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3120 bfilter->ip_protocol = 6;
3123 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3126 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3130 switch (nfilter->dst_ip_mask) {
3132 bfilter->dst_ipaddr_mask[0] = -1;
3133 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3134 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3135 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3138 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3142 switch (nfilter->src_ip_mask) {
3144 bfilter->src_ipaddr_mask[0] = -1;
3145 bfilter->src_ipaddr[0] = nfilter->src_ip;
3146 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3147 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3150 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3154 switch (nfilter->src_port_mask) {
3156 bfilter->src_port_mask = -1;
3157 bfilter->src_port = nfilter->src_port;
3158 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3159 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3162 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3166 bfilter->enables = en;
3170 static struct bnxt_filter_info*
3171 bnxt_match_ntuple_filter(struct bnxt *bp,
3172 struct bnxt_filter_info *bfilter,
3173 struct bnxt_vnic_info **mvnic)
3175 struct bnxt_filter_info *mfilter = NULL;
3178 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3179 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3180 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3181 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3182 bfilter->src_ipaddr_mask[0] ==
3183 mfilter->src_ipaddr_mask[0] &&
3184 bfilter->src_port == mfilter->src_port &&
3185 bfilter->src_port_mask == mfilter->src_port_mask &&
3186 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3187 bfilter->dst_ipaddr_mask[0] ==
3188 mfilter->dst_ipaddr_mask[0] &&
3189 bfilter->dst_port == mfilter->dst_port &&
3190 bfilter->dst_port_mask == mfilter->dst_port_mask &&
3191 bfilter->flags == mfilter->flags &&
3192 bfilter->enables == mfilter->enables) {
3203 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3204 struct rte_eth_ntuple_filter *nfilter,
3205 enum rte_filter_op filter_op)
3207 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3208 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3211 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3212 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3216 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3217 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3221 bfilter = bnxt_get_unused_filter(bp);
3222 if (bfilter == NULL) {
3224 "Not enough resources for a new filter.\n");
3227 ret = parse_ntuple_filter(bp, nfilter, bfilter);
3231 vnic = &bp->vnic_info[nfilter->queue];
3232 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3233 filter1 = STAILQ_FIRST(&vnic0->filter);
3234 if (filter1 == NULL) {
3239 bfilter->dst_id = vnic->fw_vnic_id;
3240 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3242 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3243 bfilter->ethertype = 0x800;
3244 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3246 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3248 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3249 bfilter->dst_id == mfilter->dst_id) {
3250 PMD_DRV_LOG(ERR, "filter exists.\n");
3253 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3254 bfilter->dst_id != mfilter->dst_id) {
3255 mfilter->dst_id = vnic->fw_vnic_id;
3256 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3257 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3258 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3259 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3260 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3263 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3264 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3269 if (filter_op == RTE_ETH_FILTER_ADD) {
3270 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3271 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3274 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3276 if (mfilter == NULL) {
3277 /* This should not happen. But for Coverity! */
3281 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3283 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3284 bnxt_free_filter(bp, mfilter);
3285 bnxt_free_filter(bp, bfilter);
3290 bnxt_free_filter(bp, bfilter);
3295 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3296 enum rte_filter_op filter_op,
3299 struct bnxt *bp = dev->data->dev_private;
3302 if (filter_op == RTE_ETH_FILTER_NOP)
3306 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3311 switch (filter_op) {
3312 case RTE_ETH_FILTER_ADD:
3313 ret = bnxt_cfg_ntuple_filter(bp,
3314 (struct rte_eth_ntuple_filter *)arg,
3317 case RTE_ETH_FILTER_DELETE:
3318 ret = bnxt_cfg_ntuple_filter(bp,
3319 (struct rte_eth_ntuple_filter *)arg,
3323 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3331 bnxt_parse_fdir_filter(struct bnxt *bp,
3332 struct rte_eth_fdir_filter *fdir,
3333 struct bnxt_filter_info *filter)
3335 enum rte_fdir_mode fdir_mode =
3336 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3337 struct bnxt_vnic_info *vnic0, *vnic;
3338 struct bnxt_filter_info *filter1;
3342 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3345 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3346 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3348 switch (fdir->input.flow_type) {
3349 case RTE_ETH_FLOW_IPV4:
3350 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3352 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3353 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3354 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3355 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3356 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3357 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3358 filter->ip_addr_type =
3359 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3360 filter->src_ipaddr_mask[0] = 0xffffffff;
3361 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3362 filter->dst_ipaddr_mask[0] = 0xffffffff;
3363 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3364 filter->ethertype = 0x800;
3365 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3367 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3368 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3369 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3370 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3371 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3372 filter->dst_port_mask = 0xffff;
3373 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3374 filter->src_port_mask = 0xffff;
3375 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3376 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3377 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3378 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3379 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3380 filter->ip_protocol = 6;
3381 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3382 filter->ip_addr_type =
3383 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3384 filter->src_ipaddr_mask[0] = 0xffffffff;
3385 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3386 filter->dst_ipaddr_mask[0] = 0xffffffff;
3387 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3388 filter->ethertype = 0x800;
3389 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3391 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3392 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3393 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3394 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3395 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3396 filter->dst_port_mask = 0xffff;
3397 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3398 filter->src_port_mask = 0xffff;
3399 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3400 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3401 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3402 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3403 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3404 filter->ip_protocol = 17;
3405 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3406 filter->ip_addr_type =
3407 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3408 filter->src_ipaddr_mask[0] = 0xffffffff;
3409 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3410 filter->dst_ipaddr_mask[0] = 0xffffffff;
3411 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3412 filter->ethertype = 0x800;
3413 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3415 case RTE_ETH_FLOW_IPV6:
3416 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3418 filter->ip_addr_type =
3419 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3420 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3421 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3422 rte_memcpy(filter->src_ipaddr,
3423 fdir->input.flow.ipv6_flow.src_ip, 16);
3424 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3425 rte_memcpy(filter->dst_ipaddr,
3426 fdir->input.flow.ipv6_flow.dst_ip, 16);
3427 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3428 memset(filter->dst_ipaddr_mask, 0xff, 16);
3429 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3430 memset(filter->src_ipaddr_mask, 0xff, 16);
3431 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3432 filter->ethertype = 0x86dd;
3433 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3435 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3436 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3437 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3438 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3439 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3440 filter->dst_port_mask = 0xffff;
3441 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3442 filter->src_port_mask = 0xffff;
3443 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3444 filter->ip_addr_type =
3445 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3446 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3447 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3448 rte_memcpy(filter->src_ipaddr,
3449 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3450 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3451 rte_memcpy(filter->dst_ipaddr,
3452 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3453 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3454 memset(filter->dst_ipaddr_mask, 0xff, 16);
3455 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3456 memset(filter->src_ipaddr_mask, 0xff, 16);
3457 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3458 filter->ethertype = 0x86dd;
3459 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3461 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3462 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3463 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3464 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3465 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3466 filter->dst_port_mask = 0xffff;
3467 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3468 filter->src_port_mask = 0xffff;
3469 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3470 filter->ip_addr_type =
3471 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3472 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3473 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3474 rte_memcpy(filter->src_ipaddr,
3475 fdir->input.flow.udp6_flow.ip.src_ip, 16);
3476 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3477 rte_memcpy(filter->dst_ipaddr,
3478 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3479 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3480 memset(filter->dst_ipaddr_mask, 0xff, 16);
3481 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3482 memset(filter->src_ipaddr_mask, 0xff, 16);
3483 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3484 filter->ethertype = 0x86dd;
3485 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3487 case RTE_ETH_FLOW_L2_PAYLOAD:
3488 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3489 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3491 case RTE_ETH_FLOW_VXLAN:
3492 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3494 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3495 filter->tunnel_type =
3496 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3497 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3499 case RTE_ETH_FLOW_NVGRE:
3500 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3502 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3503 filter->tunnel_type =
3504 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3505 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3507 case RTE_ETH_FLOW_UNKNOWN:
3508 case RTE_ETH_FLOW_RAW:
3509 case RTE_ETH_FLOW_FRAG_IPV4:
3510 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3511 case RTE_ETH_FLOW_FRAG_IPV6:
3512 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3513 case RTE_ETH_FLOW_IPV6_EX:
3514 case RTE_ETH_FLOW_IPV6_TCP_EX:
3515 case RTE_ETH_FLOW_IPV6_UDP_EX:
3516 case RTE_ETH_FLOW_GENEVE:
3522 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3523 vnic = &bp->vnic_info[fdir->action.rx_queue];
3525 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3529 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3530 rte_memcpy(filter->dst_macaddr,
3531 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3532 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3535 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3536 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3537 filter1 = STAILQ_FIRST(&vnic0->filter);
3538 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3540 filter->dst_id = vnic->fw_vnic_id;
3541 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3542 if (filter->dst_macaddr[i] == 0x00)
3543 filter1 = STAILQ_FIRST(&vnic0->filter);
3545 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3548 if (filter1 == NULL)
3551 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3552 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3554 filter->enables = en;
3559 static struct bnxt_filter_info *
3560 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3561 struct bnxt_vnic_info **mvnic)
3563 struct bnxt_filter_info *mf = NULL;
3566 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3567 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3569 STAILQ_FOREACH(mf, &vnic->filter, next) {
3570 if (mf->filter_type == nf->filter_type &&
3571 mf->flags == nf->flags &&
3572 mf->src_port == nf->src_port &&
3573 mf->src_port_mask == nf->src_port_mask &&
3574 mf->dst_port == nf->dst_port &&
3575 mf->dst_port_mask == nf->dst_port_mask &&
3576 mf->ip_protocol == nf->ip_protocol &&
3577 mf->ip_addr_type == nf->ip_addr_type &&
3578 mf->ethertype == nf->ethertype &&
3579 mf->vni == nf->vni &&
3580 mf->tunnel_type == nf->tunnel_type &&
3581 mf->l2_ovlan == nf->l2_ovlan &&
3582 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3583 mf->l2_ivlan == nf->l2_ivlan &&
3584 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3585 !memcmp(mf->l2_addr, nf->l2_addr,
3586 RTE_ETHER_ADDR_LEN) &&
3587 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3588 RTE_ETHER_ADDR_LEN) &&
3589 !memcmp(mf->src_macaddr, nf->src_macaddr,
3590 RTE_ETHER_ADDR_LEN) &&
3591 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3592 RTE_ETHER_ADDR_LEN) &&
3593 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3594 sizeof(nf->src_ipaddr)) &&
3595 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3596 sizeof(nf->src_ipaddr_mask)) &&
3597 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3598 sizeof(nf->dst_ipaddr)) &&
3599 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3600 sizeof(nf->dst_ipaddr_mask))) {
3611 bnxt_fdir_filter(struct rte_eth_dev *dev,
3612 enum rte_filter_op filter_op,
3615 struct bnxt *bp = dev->data->dev_private;
3616 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3617 struct bnxt_filter_info *filter, *match;
3618 struct bnxt_vnic_info *vnic, *mvnic;
3621 if (filter_op == RTE_ETH_FILTER_NOP)
3624 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3627 switch (filter_op) {
3628 case RTE_ETH_FILTER_ADD:
3629 case RTE_ETH_FILTER_DELETE:
3631 filter = bnxt_get_unused_filter(bp);
3632 if (filter == NULL) {
3634 "Not enough resources for a new flow.\n");
3638 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3641 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3643 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3644 vnic = &bp->vnic_info[0];
3646 vnic = &bp->vnic_info[fdir->action.rx_queue];
3648 match = bnxt_match_fdir(bp, filter, &mvnic);
3649 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3650 if (match->dst_id == vnic->fw_vnic_id) {
3651 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3655 match->dst_id = vnic->fw_vnic_id;
3656 ret = bnxt_hwrm_set_ntuple_filter(bp,
3659 STAILQ_REMOVE(&mvnic->filter, match,
3660 bnxt_filter_info, next);
3661 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3663 "Filter with matching pattern exist\n");
3665 "Updated it to new destination q\n");
3669 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3670 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3675 if (filter_op == RTE_ETH_FILTER_ADD) {
3676 ret = bnxt_hwrm_set_ntuple_filter(bp,
3681 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3683 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3684 STAILQ_REMOVE(&vnic->filter, match,
3685 bnxt_filter_info, next);
3686 bnxt_free_filter(bp, match);
3687 bnxt_free_filter(bp, filter);
3690 case RTE_ETH_FILTER_FLUSH:
3691 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3692 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3694 STAILQ_FOREACH(filter, &vnic->filter, next) {
3695 if (filter->filter_type ==
3696 HWRM_CFA_NTUPLE_FILTER) {
3698 bnxt_hwrm_clear_ntuple_filter(bp,
3700 STAILQ_REMOVE(&vnic->filter, filter,
3701 bnxt_filter_info, next);
3706 case RTE_ETH_FILTER_UPDATE:
3707 case RTE_ETH_FILTER_STATS:
3708 case RTE_ETH_FILTER_INFO:
3709 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3712 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3719 bnxt_free_filter(bp, filter);
3724 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3725 enum rte_filter_type filter_type,
3726 enum rte_filter_op filter_op, void *arg)
3728 struct bnxt *bp = dev->data->dev_private;
3734 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3735 struct bnxt_vf_representor *vfr = dev->data->dev_private;
3736 bp = vfr->parent_dev->data->dev_private;
3737 /* parent is deleted while children are still valid */
3739 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3747 ret = is_bnxt_in_error(bp);
3751 switch (filter_type) {
3752 case RTE_ETH_FILTER_TUNNEL:
3754 "filter type: %d: To be implemented\n", filter_type);
3756 case RTE_ETH_FILTER_FDIR:
3757 ret = bnxt_fdir_filter(dev, filter_op, arg);
3759 case RTE_ETH_FILTER_NTUPLE:
3760 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3762 case RTE_ETH_FILTER_ETHERTYPE:
3763 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3765 case RTE_ETH_FILTER_GENERIC:
3766 if (filter_op != RTE_ETH_FILTER_GET)
3768 if (BNXT_TRUFLOW_EN(bp))
3769 *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3771 *(const void **)arg = &bnxt_flow_ops;
3775 "Filter type (%d) not supported", filter_type);
3782 static const uint32_t *
3783 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3785 static const uint32_t ptypes[] = {
3786 RTE_PTYPE_L2_ETHER_VLAN,
3787 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3788 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3792 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3793 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3794 RTE_PTYPE_INNER_L4_ICMP,
3795 RTE_PTYPE_INNER_L4_TCP,
3796 RTE_PTYPE_INNER_L4_UDP,
3800 if (!dev->rx_pkt_burst)
3806 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3809 uint32_t reg_base = *reg_arr & 0xfffff000;
3813 for (i = 0; i < count; i++) {
3814 if ((reg_arr[i] & 0xfffff000) != reg_base)
3817 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3818 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3822 static int bnxt_map_ptp_regs(struct bnxt *bp)
3824 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3828 reg_arr = ptp->rx_regs;
3829 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3833 reg_arr = ptp->tx_regs;
3834 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3838 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3839 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3841 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3842 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3847 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3849 rte_write32(0, (uint8_t *)bp->bar0 +
3850 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3851 rte_write32(0, (uint8_t *)bp->bar0 +
3852 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3855 static uint64_t bnxt_cc_read(struct bnxt *bp)
3859 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3860 BNXT_GRCPF_REG_SYNC_TIME));
3861 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3862 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3866 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3868 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3871 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3872 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3873 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3876 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3877 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3878 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3879 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3880 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3881 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3886 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3888 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3889 struct bnxt_pf_info *pf = bp->pf;
3896 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3897 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3898 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3901 port_id = pf->port_id;
3902 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3903 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3905 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3906 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3907 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3908 /* bnxt_clr_rx_ts(bp); TBD */
3912 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3913 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3914 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3915 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3921 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3924 struct bnxt *bp = dev->data->dev_private;
3925 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3930 ns = rte_timespec_to_ns(ts);
3931 /* Set the timecounters to a new value. */
3938 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3940 struct bnxt *bp = dev->data->dev_private;
3941 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3942 uint64_t ns, systime_cycles = 0;
3948 if (BNXT_CHIP_THOR(bp))
3949 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3952 systime_cycles = bnxt_cc_read(bp);
3954 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3955 *ts = rte_ns_to_timespec(ns);
3960 bnxt_timesync_enable(struct rte_eth_dev *dev)
3962 struct bnxt *bp = dev->data->dev_private;
3963 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3971 ptp->tx_tstamp_en = 1;
3972 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3974 rc = bnxt_hwrm_ptp_cfg(bp);
3978 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3979 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3980 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3982 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3983 ptp->tc.cc_shift = shift;
3984 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3986 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3987 ptp->rx_tstamp_tc.cc_shift = shift;
3988 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3990 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3991 ptp->tx_tstamp_tc.cc_shift = shift;
3992 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3994 if (!BNXT_CHIP_THOR(bp))
3995 bnxt_map_ptp_regs(bp);
4001 bnxt_timesync_disable(struct rte_eth_dev *dev)
4003 struct bnxt *bp = dev->data->dev_private;
4004 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4010 ptp->tx_tstamp_en = 0;
4013 bnxt_hwrm_ptp_cfg(bp);
4015 if (!BNXT_CHIP_THOR(bp))
4016 bnxt_unmap_ptp_regs(bp);
4022 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4023 struct timespec *timestamp,
4024 uint32_t flags __rte_unused)
4026 struct bnxt *bp = dev->data->dev_private;
4027 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4028 uint64_t rx_tstamp_cycles = 0;
4034 if (BNXT_CHIP_THOR(bp))
4035 rx_tstamp_cycles = ptp->rx_timestamp;
4037 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
4039 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
4040 *timestamp = rte_ns_to_timespec(ns);
4045 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4046 struct timespec *timestamp)
4048 struct bnxt *bp = dev->data->dev_private;
4049 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4050 uint64_t tx_tstamp_cycles = 0;
4057 if (BNXT_CHIP_THOR(bp))
4058 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4061 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4063 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4064 *timestamp = rte_ns_to_timespec(ns);
4070 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4072 struct bnxt *bp = dev->data->dev_private;
4073 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4078 ptp->tc.nsec += delta;
4084 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4086 struct bnxt *bp = dev->data->dev_private;
4088 uint32_t dir_entries;
4089 uint32_t entry_length;
4091 rc = is_bnxt_in_error(bp);
4095 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4096 bp->pdev->addr.domain, bp->pdev->addr.bus,
4097 bp->pdev->addr.devid, bp->pdev->addr.function);
4099 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4103 return dir_entries * entry_length;
4107 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4108 struct rte_dev_eeprom_info *in_eeprom)
4110 struct bnxt *bp = dev->data->dev_private;
4115 rc = is_bnxt_in_error(bp);
4119 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4120 bp->pdev->addr.domain, bp->pdev->addr.bus,
4121 bp->pdev->addr.devid, bp->pdev->addr.function,
4122 in_eeprom->offset, in_eeprom->length);
4124 if (in_eeprom->offset == 0) /* special offset value to get directory */
4125 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4128 index = in_eeprom->offset >> 24;
4129 offset = in_eeprom->offset & 0xffffff;
4132 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4133 in_eeprom->length, in_eeprom->data);
4138 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4141 case BNX_DIR_TYPE_CHIMP_PATCH:
4142 case BNX_DIR_TYPE_BOOTCODE:
4143 case BNX_DIR_TYPE_BOOTCODE_2:
4144 case BNX_DIR_TYPE_APE_FW:
4145 case BNX_DIR_TYPE_APE_PATCH:
4146 case BNX_DIR_TYPE_KONG_FW:
4147 case BNX_DIR_TYPE_KONG_PATCH:
4148 case BNX_DIR_TYPE_BONO_FW:
4149 case BNX_DIR_TYPE_BONO_PATCH:
4157 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4160 case BNX_DIR_TYPE_AVS:
4161 case BNX_DIR_TYPE_EXP_ROM_MBA:
4162 case BNX_DIR_TYPE_PCIE:
4163 case BNX_DIR_TYPE_TSCF_UCODE:
4164 case BNX_DIR_TYPE_EXT_PHY:
4165 case BNX_DIR_TYPE_CCM:
4166 case BNX_DIR_TYPE_ISCSI_BOOT:
4167 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4168 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4176 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4178 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4179 bnxt_dir_type_is_other_exec_format(dir_type);
4183 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4184 struct rte_dev_eeprom_info *in_eeprom)
4186 struct bnxt *bp = dev->data->dev_private;
4187 uint8_t index, dir_op;
4188 uint16_t type, ext, ordinal, attr;
4191 rc = is_bnxt_in_error(bp);
4195 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4196 bp->pdev->addr.domain, bp->pdev->addr.bus,
4197 bp->pdev->addr.devid, bp->pdev->addr.function,
4198 in_eeprom->offset, in_eeprom->length);
4201 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4205 type = in_eeprom->magic >> 16;
4207 if (type == 0xffff) { /* special value for directory operations */
4208 index = in_eeprom->magic & 0xff;
4209 dir_op = in_eeprom->magic >> 8;
4213 case 0x0e: /* erase */
4214 if (in_eeprom->offset != ~in_eeprom->magic)
4216 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4222 /* Create or re-write an NVM item: */
4223 if (bnxt_dir_type_is_executable(type) == true)
4225 ext = in_eeprom->magic & 0xffff;
4226 ordinal = in_eeprom->offset >> 16;
4227 attr = in_eeprom->offset & 0xffff;
4229 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4230 in_eeprom->data, in_eeprom->length);
4237 static const struct eth_dev_ops bnxt_dev_ops = {
4238 .dev_infos_get = bnxt_dev_info_get_op,
4239 .dev_close = bnxt_dev_close_op,
4240 .dev_configure = bnxt_dev_configure_op,
4241 .dev_start = bnxt_dev_start_op,
4242 .dev_stop = bnxt_dev_stop_op,
4243 .dev_set_link_up = bnxt_dev_set_link_up_op,
4244 .dev_set_link_down = bnxt_dev_set_link_down_op,
4245 .stats_get = bnxt_stats_get_op,
4246 .stats_reset = bnxt_stats_reset_op,
4247 .rx_queue_setup = bnxt_rx_queue_setup_op,
4248 .rx_queue_release = bnxt_rx_queue_release_op,
4249 .tx_queue_setup = bnxt_tx_queue_setup_op,
4250 .tx_queue_release = bnxt_tx_queue_release_op,
4251 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4252 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4253 .reta_update = bnxt_reta_update_op,
4254 .reta_query = bnxt_reta_query_op,
4255 .rss_hash_update = bnxt_rss_hash_update_op,
4256 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4257 .link_update = bnxt_link_update_op,
4258 .promiscuous_enable = bnxt_promiscuous_enable_op,
4259 .promiscuous_disable = bnxt_promiscuous_disable_op,
4260 .allmulticast_enable = bnxt_allmulticast_enable_op,
4261 .allmulticast_disable = bnxt_allmulticast_disable_op,
4262 .mac_addr_add = bnxt_mac_addr_add_op,
4263 .mac_addr_remove = bnxt_mac_addr_remove_op,
4264 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4265 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4266 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
4267 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
4268 .vlan_filter_set = bnxt_vlan_filter_set_op,
4269 .vlan_offload_set = bnxt_vlan_offload_set_op,
4270 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4271 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4272 .mtu_set = bnxt_mtu_set_op,
4273 .mac_addr_set = bnxt_set_default_mac_addr_op,
4274 .xstats_get = bnxt_dev_xstats_get_op,
4275 .xstats_get_names = bnxt_dev_xstats_get_names_op,
4276 .xstats_reset = bnxt_dev_xstats_reset_op,
4277 .fw_version_get = bnxt_fw_version_get,
4278 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4279 .rxq_info_get = bnxt_rxq_info_get_op,
4280 .txq_info_get = bnxt_txq_info_get_op,
4281 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4282 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4283 .dev_led_on = bnxt_dev_led_on_op,
4284 .dev_led_off = bnxt_dev_led_off_op,
4285 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4286 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4287 .rx_queue_start = bnxt_rx_queue_start,
4288 .rx_queue_stop = bnxt_rx_queue_stop,
4289 .tx_queue_start = bnxt_tx_queue_start,
4290 .tx_queue_stop = bnxt_tx_queue_stop,
4291 .filter_ctrl = bnxt_filter_ctrl_op,
4292 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4293 .get_eeprom_length = bnxt_get_eeprom_length_op,
4294 .get_eeprom = bnxt_get_eeprom_op,
4295 .set_eeprom = bnxt_set_eeprom_op,
4296 .timesync_enable = bnxt_timesync_enable,
4297 .timesync_disable = bnxt_timesync_disable,
4298 .timesync_read_time = bnxt_timesync_read_time,
4299 .timesync_write_time = bnxt_timesync_write_time,
4300 .timesync_adjust_time = bnxt_timesync_adjust_time,
4301 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4302 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4305 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4309 /* Only pre-map the reset GRC registers using window 3 */
4310 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4311 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4313 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4318 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4320 struct bnxt_error_recovery_info *info = bp->recovery_info;
4321 uint32_t reg_base = 0xffffffff;
4324 /* Only pre-map the monitoring GRC registers using window 2 */
4325 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4326 uint32_t reg = info->status_regs[i];
4328 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4331 if (reg_base == 0xffffffff)
4332 reg_base = reg & 0xfffff000;
4333 if ((reg & 0xfffff000) != reg_base)
4336 /* Use mask 0xffc as the Lower 2 bits indicates
4337 * address space location
4339 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4343 if (reg_base == 0xffffffff)
4346 rte_write32(reg_base, (uint8_t *)bp->bar0 +
4347 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4352 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4354 struct bnxt_error_recovery_info *info = bp->recovery_info;
4355 uint32_t delay = info->delay_after_reset[index];
4356 uint32_t val = info->reset_reg_val[index];
4357 uint32_t reg = info->reset_reg[index];
4358 uint32_t type, offset;
4360 type = BNXT_FW_STATUS_REG_TYPE(reg);
4361 offset = BNXT_FW_STATUS_REG_OFF(reg);
4364 case BNXT_FW_STATUS_REG_TYPE_CFG:
4365 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4367 case BNXT_FW_STATUS_REG_TYPE_GRC:
4368 offset = bnxt_map_reset_regs(bp, offset);
4369 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4371 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4372 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4375 /* wait on a specific interval of time until core reset is complete */
4377 rte_delay_ms(delay);
4380 static void bnxt_dev_cleanup(struct bnxt *bp)
4382 bnxt_set_hwrm_link_config(bp, false);
4383 bp->link_info->link_up = 0;
4384 if (bp->eth_dev->data->dev_started)
4385 bnxt_dev_stop_op(bp->eth_dev);
4387 bnxt_uninit_resources(bp, true);
4390 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4392 struct rte_eth_dev *dev = bp->eth_dev;
4393 struct rte_vlan_filter_conf *vfc;
4397 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4398 vfc = &dev->data->vlan_filter_conf;
4399 vidx = vlan_id / 64;
4400 vbit = vlan_id % 64;
4402 /* Each bit corresponds to a VLAN id */
4403 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4404 rc = bnxt_add_vlan_filter(bp, vlan_id);
4413 static int bnxt_restore_mac_filters(struct bnxt *bp)
4415 struct rte_eth_dev *dev = bp->eth_dev;
4416 struct rte_eth_dev_info dev_info;
4417 struct rte_ether_addr *addr;
4423 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4426 rc = bnxt_dev_info_get_op(dev, &dev_info);
4430 /* replay MAC address configuration */
4431 for (i = 1; i < dev_info.max_mac_addrs; i++) {
4432 addr = &dev->data->mac_addrs[i];
4434 /* skip zero address */
4435 if (rte_is_zero_ether_addr(addr))
4439 pool_mask = dev->data->mac_pool_sel[i];
4442 if (pool_mask & 1ULL) {
4443 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4449 } while (pool_mask);
4455 static int bnxt_restore_filters(struct bnxt *bp)
4457 struct rte_eth_dev *dev = bp->eth_dev;
4460 if (dev->data->all_multicast) {
4461 ret = bnxt_allmulticast_enable_op(dev);
4465 if (dev->data->promiscuous) {
4466 ret = bnxt_promiscuous_enable_op(dev);
4471 ret = bnxt_restore_mac_filters(bp);
4475 ret = bnxt_restore_vlan_filters(bp);
4476 /* TODO restore other filters as well */
4480 static void bnxt_dev_recover(void *arg)
4482 struct bnxt *bp = arg;
4483 int timeout = bp->fw_reset_max_msecs;
4486 /* Clear Error flag so that device re-init should happen */
4487 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4490 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4493 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4494 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4495 } while (rc && timeout);
4498 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4502 rc = bnxt_init_resources(bp, true);
4505 "Failed to initialize resources after reset\n");
4508 /* clear reset flag as the device is initialized now */
4509 bp->flags &= ~BNXT_FLAG_FW_RESET;
4511 rc = bnxt_dev_start_op(bp->eth_dev);
4513 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4517 rc = bnxt_restore_filters(bp);
4521 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4524 bnxt_dev_stop_op(bp->eth_dev);
4526 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4527 bnxt_uninit_resources(bp, false);
4528 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4531 void bnxt_dev_reset_and_resume(void *arg)
4533 struct bnxt *bp = arg;
4536 bnxt_dev_cleanup(bp);
4538 bnxt_wait_for_device_shutdown(bp);
4540 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4541 bnxt_dev_recover, (void *)bp);
4543 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4546 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4548 struct bnxt_error_recovery_info *info = bp->recovery_info;
4549 uint32_t reg = info->status_regs[index];
4550 uint32_t type, offset, val = 0;
4552 type = BNXT_FW_STATUS_REG_TYPE(reg);
4553 offset = BNXT_FW_STATUS_REG_OFF(reg);
4556 case BNXT_FW_STATUS_REG_TYPE_CFG:
4557 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4559 case BNXT_FW_STATUS_REG_TYPE_GRC:
4560 offset = info->mapped_status_regs[index];
4562 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4563 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4571 static int bnxt_fw_reset_all(struct bnxt *bp)
4573 struct bnxt_error_recovery_info *info = bp->recovery_info;
4577 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4578 /* Reset through master function driver */
4579 for (i = 0; i < info->reg_array_cnt; i++)
4580 bnxt_write_fw_reset_reg(bp, i);
4581 /* Wait for time specified by FW after triggering reset */
4582 rte_delay_ms(info->master_func_wait_period_after_reset);
4583 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4584 /* Reset with the help of Kong processor */
4585 rc = bnxt_hwrm_fw_reset(bp);
4587 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4593 static void bnxt_fw_reset_cb(void *arg)
4595 struct bnxt *bp = arg;
4596 struct bnxt_error_recovery_info *info = bp->recovery_info;
4599 /* Only Master function can do FW reset */
4600 if (bnxt_is_master_func(bp) &&
4601 bnxt_is_recovery_enabled(bp)) {
4602 rc = bnxt_fw_reset_all(bp);
4604 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4609 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4610 * EXCEPTION_FATAL_ASYNC event to all the functions
4611 * (including MASTER FUNC). After receiving this Async, all the active
4612 * drivers should treat this case as FW initiated recovery
4614 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4615 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4616 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4618 /* To recover from error */
4619 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4624 /* Driver should poll FW heartbeat, reset_counter with the frequency
4625 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4626 * When the driver detects heartbeat stop or change in reset_counter,
4627 * it has to trigger a reset to recover from the error condition.
4628 * A “master PF” is the function who will have the privilege to
4629 * initiate the chimp reset. The master PF will be elected by the
4630 * firmware and will be notified through async message.
4632 static void bnxt_check_fw_health(void *arg)
4634 struct bnxt *bp = arg;
4635 struct bnxt_error_recovery_info *info = bp->recovery_info;
4636 uint32_t val = 0, wait_msec;
4638 if (!info || !bnxt_is_recovery_enabled(bp) ||
4639 is_bnxt_in_error(bp))
4642 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4643 if (val == info->last_heart_beat)
4646 info->last_heart_beat = val;
4648 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4649 if (val != info->last_reset_counter)
4652 info->last_reset_counter = val;
4654 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4655 bnxt_check_fw_health, (void *)bp);
4659 /* Stop DMA to/from device */
4660 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4661 bp->flags |= BNXT_FLAG_FW_RESET;
4663 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4665 if (bnxt_is_master_func(bp))
4666 wait_msec = info->master_func_wait_period;
4668 wait_msec = info->normal_func_wait_period;
4670 rte_eal_alarm_set(US_PER_MS * wait_msec,
4671 bnxt_fw_reset_cb, (void *)bp);
4674 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4676 uint32_t polling_freq;
4678 if (!bnxt_is_recovery_enabled(bp))
4681 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4684 polling_freq = bp->recovery_info->driver_polling_freq;
4686 rte_eal_alarm_set(US_PER_MS * polling_freq,
4687 bnxt_check_fw_health, (void *)bp);
4688 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4691 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4693 if (!bnxt_is_recovery_enabled(bp))
4696 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4697 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4700 static bool bnxt_vf_pciid(uint16_t device_id)
4702 switch (device_id) {
4703 case BROADCOM_DEV_ID_57304_VF:
4704 case BROADCOM_DEV_ID_57406_VF:
4705 case BROADCOM_DEV_ID_5731X_VF:
4706 case BROADCOM_DEV_ID_5741X_VF:
4707 case BROADCOM_DEV_ID_57414_VF:
4708 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4709 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4710 case BROADCOM_DEV_ID_58802_VF:
4711 case BROADCOM_DEV_ID_57500_VF1:
4712 case BROADCOM_DEV_ID_57500_VF2:
4720 static bool bnxt_thor_device(uint16_t device_id)
4722 switch (device_id) {
4723 case BROADCOM_DEV_ID_57508:
4724 case BROADCOM_DEV_ID_57504:
4725 case BROADCOM_DEV_ID_57502:
4726 case BROADCOM_DEV_ID_57508_MF1:
4727 case BROADCOM_DEV_ID_57504_MF1:
4728 case BROADCOM_DEV_ID_57502_MF1:
4729 case BROADCOM_DEV_ID_57508_MF2:
4730 case BROADCOM_DEV_ID_57504_MF2:
4731 case BROADCOM_DEV_ID_57502_MF2:
4732 case BROADCOM_DEV_ID_57500_VF1:
4733 case BROADCOM_DEV_ID_57500_VF2:
4741 bool bnxt_stratus_device(struct bnxt *bp)
4743 uint16_t device_id = bp->pdev->id.device_id;
4745 switch (device_id) {
4746 case BROADCOM_DEV_ID_STRATUS_NIC:
4747 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4748 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4756 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4758 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4759 struct bnxt *bp = eth_dev->data->dev_private;
4761 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4762 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4763 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4764 if (!bp->bar0 || !bp->doorbell_base) {
4765 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4769 bp->eth_dev = eth_dev;
4775 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4776 struct bnxt_ctx_pg_info *ctx_pg,
4781 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4782 const struct rte_memzone *mz = NULL;
4783 char mz_name[RTE_MEMZONE_NAMESIZE];
4784 rte_iova_t mz_phys_addr;
4785 uint64_t valid_bits = 0;
4792 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4794 rmem->page_size = BNXT_PAGE_SIZE;
4795 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4796 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4797 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4799 valid_bits = PTU_PTE_VALID;
4801 if (rmem->nr_pages > 1) {
4802 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4803 "bnxt_ctx_pg_tbl%s_%x_%d",
4804 suffix, idx, bp->eth_dev->data->port_id);
4805 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4806 mz = rte_memzone_lookup(mz_name);
4808 mz = rte_memzone_reserve_aligned(mz_name,
4812 RTE_MEMZONE_SIZE_HINT_ONLY |
4813 RTE_MEMZONE_IOVA_CONTIG,
4819 memset(mz->addr, 0, mz->len);
4820 mz_phys_addr = mz->iova;
4822 rmem->pg_tbl = mz->addr;
4823 rmem->pg_tbl_map = mz_phys_addr;
4824 rmem->pg_tbl_mz = mz;
4827 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4828 suffix, idx, bp->eth_dev->data->port_id);
4829 mz = rte_memzone_lookup(mz_name);
4831 mz = rte_memzone_reserve_aligned(mz_name,
4835 RTE_MEMZONE_SIZE_HINT_ONLY |
4836 RTE_MEMZONE_IOVA_CONTIG,
4842 memset(mz->addr, 0, mz->len);
4843 mz_phys_addr = mz->iova;
4845 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4846 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4847 rmem->dma_arr[i] = mz_phys_addr + sz;
4849 if (rmem->nr_pages > 1) {
4850 if (i == rmem->nr_pages - 2 &&
4851 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4852 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4853 else if (i == rmem->nr_pages - 1 &&
4854 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4855 valid_bits |= PTU_PTE_LAST;
4857 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4863 if (rmem->vmem_size)
4864 rmem->vmem = (void **)mz->addr;
4865 rmem->dma_arr[0] = mz_phys_addr;
4869 static void bnxt_free_ctx_mem(struct bnxt *bp)
4873 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4876 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4877 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4878 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4879 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4880 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4881 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4882 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4883 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4884 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4885 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4886 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4888 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4889 if (bp->ctx->tqm_mem[i])
4890 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4897 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4899 #define min_t(type, x, y) ({ \
4900 type __min1 = (x); \
4901 type __min2 = (y); \
4902 __min1 < __min2 ? __min1 : __min2; })
4904 #define max_t(type, x, y) ({ \
4905 type __max1 = (x); \
4906 type __max2 = (y); \
4907 __max1 > __max2 ? __max1 : __max2; })
4909 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4911 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4913 struct bnxt_ctx_pg_info *ctx_pg;
4914 struct bnxt_ctx_mem_info *ctx;
4915 uint32_t mem_size, ena, entries;
4916 uint32_t entries_sp, min;
4919 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4921 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4925 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4928 ctx_pg = &ctx->qp_mem;
4929 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4930 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4931 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4935 ctx_pg = &ctx->srq_mem;
4936 ctx_pg->entries = ctx->srq_max_l2_entries;
4937 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4938 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4942 ctx_pg = &ctx->cq_mem;
4943 ctx_pg->entries = ctx->cq_max_l2_entries;
4944 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4945 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4949 ctx_pg = &ctx->vnic_mem;
4950 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4951 ctx->vnic_max_ring_table_entries;
4952 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4953 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4957 ctx_pg = &ctx->stat_mem;
4958 ctx_pg->entries = ctx->stat_max_entries;
4959 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4960 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4964 min = ctx->tqm_min_entries_per_ring;
4966 entries_sp = ctx->qp_max_l2_entries +
4967 ctx->vnic_max_vnic_entries +
4968 2 * ctx->qp_min_qp1_entries + min;
4969 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4971 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4972 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4973 entries = clamp_t(uint32_t, entries, min,
4974 ctx->tqm_max_entries_per_ring);
4975 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4976 ctx_pg = ctx->tqm_mem[i];
4977 ctx_pg->entries = i ? entries : entries_sp;
4978 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4979 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4982 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4985 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4986 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4989 "Failed to configure context mem: rc = %d\n", rc);
4991 ctx->flags |= BNXT_CTX_FLAG_INITED;
4996 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4998 struct rte_pci_device *pci_dev = bp->pdev;
4999 char mz_name[RTE_MEMZONE_NAMESIZE];
5000 const struct rte_memzone *mz = NULL;
5001 uint32_t total_alloc_len;
5002 rte_iova_t mz_phys_addr;
5004 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
5007 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5008 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5009 pci_dev->addr.bus, pci_dev->addr.devid,
5010 pci_dev->addr.function, "rx_port_stats");
5011 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5012 mz = rte_memzone_lookup(mz_name);
5014 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
5015 sizeof(struct rx_port_stats_ext) + 512);
5017 mz = rte_memzone_reserve(mz_name, total_alloc_len,
5020 RTE_MEMZONE_SIZE_HINT_ONLY |
5021 RTE_MEMZONE_IOVA_CONTIG);
5025 memset(mz->addr, 0, mz->len);
5026 mz_phys_addr = mz->iova;
5028 bp->rx_mem_zone = (const void *)mz;
5029 bp->hw_rx_port_stats = mz->addr;
5030 bp->hw_rx_port_stats_map = mz_phys_addr;
5032 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5033 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5034 pci_dev->addr.bus, pci_dev->addr.devid,
5035 pci_dev->addr.function, "tx_port_stats");
5036 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5037 mz = rte_memzone_lookup(mz_name);
5039 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
5040 sizeof(struct tx_port_stats_ext) + 512);
5042 mz = rte_memzone_reserve(mz_name,
5046 RTE_MEMZONE_SIZE_HINT_ONLY |
5047 RTE_MEMZONE_IOVA_CONTIG);
5051 memset(mz->addr, 0, mz->len);
5052 mz_phys_addr = mz->iova;
5054 bp->tx_mem_zone = (const void *)mz;
5055 bp->hw_tx_port_stats = mz->addr;
5056 bp->hw_tx_port_stats_map = mz_phys_addr;
5057 bp->flags |= BNXT_FLAG_PORT_STATS;
5059 /* Display extended statistics if FW supports it */
5060 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5061 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5062 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5065 bp->hw_rx_port_stats_ext = (void *)
5066 ((uint8_t *)bp->hw_rx_port_stats +
5067 sizeof(struct rx_port_stats));
5068 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5069 sizeof(struct rx_port_stats);
5070 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5072 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5073 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5074 bp->hw_tx_port_stats_ext = (void *)
5075 ((uint8_t *)bp->hw_tx_port_stats +
5076 sizeof(struct tx_port_stats));
5077 bp->hw_tx_port_stats_ext_map =
5078 bp->hw_tx_port_stats_map +
5079 sizeof(struct tx_port_stats);
5080 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5086 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5088 struct bnxt *bp = eth_dev->data->dev_private;
5091 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5092 RTE_ETHER_ADDR_LEN *
5095 if (eth_dev->data->mac_addrs == NULL) {
5096 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5100 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5104 /* Generate a random MAC address, if none was assigned by PF */
5105 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5106 bnxt_eth_hw_addr_random(bp->mac_addr);
5108 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5109 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5110 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5112 rc = bnxt_hwrm_set_mac(bp);
5117 /* Copy the permanent MAC from the FUNC_QCAPS response */
5118 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5123 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5127 /* MAC is already configured in FW */
5128 if (BNXT_HAS_DFLT_MAC_SET(bp))
5131 /* Restore the old MAC configured */
5132 rc = bnxt_hwrm_set_mac(bp);
5134 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5139 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5144 #define ALLOW_FUNC(x) \
5146 uint32_t arg = (x); \
5147 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5148 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5151 /* Forward all requests if firmware is new enough */
5152 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5153 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5154 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5155 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5157 PMD_DRV_LOG(WARNING,
5158 "Firmware too old for VF mailbox functionality\n");
5159 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5163 * The following are used for driver cleanup. If we disallow these,
5164 * VF drivers can't clean up cleanly.
5166 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5167 ALLOW_FUNC(HWRM_VNIC_FREE);
5168 ALLOW_FUNC(HWRM_RING_FREE);
5169 ALLOW_FUNC(HWRM_RING_GRP_FREE);
5170 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5171 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5172 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5173 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5174 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5178 bnxt_get_svif(uint16_t port_id, bool func_svif,
5179 enum bnxt_ulp_intf_type type)
5181 struct rte_eth_dev *eth_dev;
5184 eth_dev = &rte_eth_devices[port_id];
5185 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5186 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5190 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5193 eth_dev = vfr->parent_dev;
5196 bp = eth_dev->data->dev_private;
5198 return func_svif ? bp->func_svif : bp->port_svif;
5202 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5204 struct rte_eth_dev *eth_dev;
5205 struct bnxt_vnic_info *vnic;
5208 eth_dev = &rte_eth_devices[port];
5209 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5210 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5214 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5215 return vfr->dflt_vnic_id;
5217 eth_dev = vfr->parent_dev;
5220 bp = eth_dev->data->dev_private;
5222 vnic = BNXT_GET_DEFAULT_VNIC(bp);
5224 return vnic->fw_vnic_id;
5228 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5230 struct rte_eth_dev *eth_dev;
5233 eth_dev = &rte_eth_devices[port];
5234 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5235 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5239 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5242 eth_dev = vfr->parent_dev;
5245 bp = eth_dev->data->dev_private;
5250 enum bnxt_ulp_intf_type
5251 bnxt_get_interface_type(uint16_t port)
5253 struct rte_eth_dev *eth_dev;
5256 eth_dev = &rte_eth_devices[port];
5257 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5258 return BNXT_ULP_INTF_TYPE_VF_REP;
5260 bp = eth_dev->data->dev_private;
5262 return BNXT_ULP_INTF_TYPE_PF;
5263 else if (BNXT_VF_IS_TRUSTED(bp))
5264 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5265 else if (BNXT_VF(bp))
5266 return BNXT_ULP_INTF_TYPE_VF;
5268 return BNXT_ULP_INTF_TYPE_INVALID;
5272 bnxt_get_phy_port_id(uint16_t port_id)
5274 struct bnxt_vf_representor *vfr;
5275 struct rte_eth_dev *eth_dev;
5278 eth_dev = &rte_eth_devices[port_id];
5279 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5280 vfr = eth_dev->data->dev_private;
5284 eth_dev = vfr->parent_dev;
5287 bp = eth_dev->data->dev_private;
5289 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5293 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5295 struct rte_eth_dev *eth_dev;
5298 eth_dev = &rte_eth_devices[port_id];
5299 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5300 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5304 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5305 return vfr->fw_fid - 1;
5307 eth_dev = vfr->parent_dev;
5310 bp = eth_dev->data->dev_private;
5312 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5316 bnxt_get_vport(uint16_t port_id)
5318 return (1 << bnxt_get_phy_port_id(port_id));
5321 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5323 struct bnxt_error_recovery_info *info = bp->recovery_info;
5326 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5327 memset(info, 0, sizeof(*info));
5331 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5334 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5337 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5339 bp->recovery_info = info;
5342 static void bnxt_check_fw_status(struct bnxt *bp)
5346 if (!(bp->recovery_info &&
5347 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5350 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5351 if (fw_status != BNXT_FW_STATUS_HEALTHY)
5352 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5356 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5358 struct bnxt_error_recovery_info *info = bp->recovery_info;
5359 uint32_t status_loc;
5362 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5363 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5364 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5365 BNXT_GRCP_WINDOW_2_BASE +
5366 offsetof(struct hcomm_status,
5368 /* If the signature is absent, then FW does not support this feature */
5369 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5370 HCOMM_STATUS_SIGNATURE_VAL)
5374 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5378 bp->recovery_info = info;
5380 memset(info, 0, sizeof(*info));
5383 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5384 BNXT_GRCP_WINDOW_2_BASE +
5385 offsetof(struct hcomm_status,
5388 /* Only pre-map the FW health status GRC register */
5389 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5392 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5393 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5394 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5396 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5397 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5399 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5404 static int bnxt_init_fw(struct bnxt *bp)
5411 rc = bnxt_map_hcomm_fw_status_reg(bp);
5415 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5417 bnxt_check_fw_status(bp);
5421 rc = bnxt_hwrm_func_reset(bp);
5425 rc = bnxt_hwrm_vnic_qcaps(bp);
5429 rc = bnxt_hwrm_queue_qportcfg(bp);
5433 /* Get the MAX capabilities for this function.
5434 * This function also allocates context memory for TQM rings and
5435 * informs the firmware about this allocated backing store memory.
5437 rc = bnxt_hwrm_func_qcaps(bp);
5441 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5445 bnxt_hwrm_port_mac_qcfg(bp);
5447 bnxt_hwrm_parent_pf_qcfg(bp);
5449 bnxt_hwrm_port_phy_qcaps(bp);
5451 bnxt_alloc_error_recovery_info(bp);
5452 /* Get the adapter error recovery support info */
5453 rc = bnxt_hwrm_error_recovery_qcfg(bp);
5455 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5457 bnxt_hwrm_port_led_qcaps(bp);
5463 bnxt_init_locks(struct bnxt *bp)
5467 err = pthread_mutex_init(&bp->flow_lock, NULL);
5469 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5473 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5475 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5479 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5483 rc = bnxt_init_fw(bp);
5487 if (!reconfig_dev) {
5488 rc = bnxt_setup_mac_addr(bp->eth_dev);
5492 rc = bnxt_restore_dflt_mac(bp);
5497 bnxt_config_vf_req_fwd(bp);
5499 rc = bnxt_hwrm_func_driver_register(bp);
5501 PMD_DRV_LOG(ERR, "Failed to register driver");
5506 if (bp->pdev->max_vfs) {
5507 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5509 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5513 rc = bnxt_hwrm_allocate_pf_only(bp);
5516 "Failed to allocate PF resources");
5522 rc = bnxt_alloc_mem(bp, reconfig_dev);
5526 rc = bnxt_setup_int(bp);
5530 rc = bnxt_request_int(bp);
5534 rc = bnxt_init_ctx_mem(bp);
5536 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5540 rc = bnxt_init_locks(bp);
5548 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5549 const char *value, void *opaque_arg)
5551 struct bnxt *bp = opaque_arg;
5552 unsigned long truflow;
5555 if (!value || !opaque_arg) {
5557 "Invalid parameter passed to truflow devargs.\n");
5561 truflow = strtoul(value, &end, 10);
5562 if (end == NULL || *end != '\0' ||
5563 (truflow == ULONG_MAX && errno == ERANGE)) {
5565 "Invalid parameter passed to truflow devargs.\n");
5569 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5571 "Invalid value passed to truflow devargs.\n");
5575 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5576 if (BNXT_TRUFLOW_EN(bp))
5577 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5583 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5584 const char *value, void *opaque_arg)
5586 struct bnxt *bp = opaque_arg;
5587 unsigned long flow_xstat;
5590 if (!value || !opaque_arg) {
5592 "Invalid parameter passed to flow_xstat devarg.\n");
5596 flow_xstat = strtoul(value, &end, 10);
5597 if (end == NULL || *end != '\0' ||
5598 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5600 "Invalid parameter passed to flow_xstat devarg.\n");
5604 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5606 "Invalid value passed to flow_xstat devarg.\n");
5610 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5611 if (BNXT_FLOW_XSTATS_EN(bp))
5612 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5618 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5619 const char *value, void *opaque_arg)
5621 struct bnxt *bp = opaque_arg;
5622 unsigned long max_num_kflows;
5625 if (!value || !opaque_arg) {
5627 "Invalid parameter passed to max_num_kflows devarg.\n");
5631 max_num_kflows = strtoul(value, &end, 10);
5632 if (end == NULL || *end != '\0' ||
5633 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5635 "Invalid parameter passed to max_num_kflows devarg.\n");
5639 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5641 "Invalid value passed to max_num_kflows devarg.\n");
5645 bp->max_num_kflows = max_num_kflows;
5646 if (bp->max_num_kflows)
5647 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5654 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5656 struct rte_kvargs *kvlist;
5658 if (devargs == NULL)
5661 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5666 * Handler for "truflow" devarg.
5667 * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5669 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5670 bnxt_parse_devarg_truflow, bp);
5673 * Handler for "flow_xstat" devarg.
5674 * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5676 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5677 bnxt_parse_devarg_flow_xstat, bp);
5680 * Handler for "max_num_kflows" devarg.
5681 * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5683 rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5684 bnxt_parse_devarg_max_num_kflows, bp);
5686 rte_kvargs_free(kvlist);
5689 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5693 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5694 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5697 "Failed to alloc switch domain: %d\n", rc);
5700 "Switch domain allocated %d\n",
5701 bp->switch_domain_id);
5708 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5710 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5711 static int version_printed;
5715 if (version_printed++ == 0)
5716 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5718 eth_dev->dev_ops = &bnxt_dev_ops;
5719 eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5720 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5721 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5722 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5723 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5726 * For secondary processes, we don't initialise any further
5727 * as primary has already done this work.
5729 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5732 rte_eth_copy_pci_info(eth_dev, pci_dev);
5734 bp = eth_dev->data->dev_private;
5736 /* Parse dev arguments passed on when starting the DPDK application. */
5737 bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5739 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5741 if (bnxt_vf_pciid(pci_dev->id.device_id))
5742 bp->flags |= BNXT_FLAG_VF;
5744 if (bnxt_thor_device(pci_dev->id.device_id))
5745 bp->flags |= BNXT_FLAG_THOR_CHIP;
5747 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5748 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5749 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5750 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5751 bp->flags |= BNXT_FLAG_STINGRAY;
5753 rc = bnxt_init_board(eth_dev);
5756 "Failed to initialize board rc: %x\n", rc);
5760 rc = bnxt_alloc_pf_info(bp);
5764 rc = bnxt_alloc_link_info(bp);
5768 rc = bnxt_alloc_parent_info(bp);
5772 rc = bnxt_alloc_hwrm_resources(bp);
5775 "Failed to allocate hwrm resource rc: %x\n", rc);
5778 rc = bnxt_alloc_leds_info(bp);
5782 rc = bnxt_alloc_cos_queues(bp);
5786 rc = bnxt_init_resources(bp, false);
5790 rc = bnxt_alloc_stats_mem(bp);
5794 bnxt_alloc_switch_domain(bp);
5796 /* Pass the information to the rte_eth_dev_close() that it should also
5797 * release the private port resources.
5799 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5802 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5803 pci_dev->mem_resource[0].phys_addr,
5804 pci_dev->mem_resource[0].addr);
5809 bnxt_dev_uninit(eth_dev);
5814 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5823 ctx->dma = RTE_BAD_IOVA;
5824 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5827 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5829 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5830 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5831 bp->flow_stat->rx_fc_out_tbl.ctx_id,
5832 bp->flow_stat->max_fc,
5835 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5836 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5837 bp->flow_stat->tx_fc_out_tbl.ctx_id,
5838 bp->flow_stat->max_fc,
5841 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5842 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5843 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5845 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5846 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5847 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5849 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5850 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5851 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5853 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5854 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5855 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5858 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5860 bnxt_unregister_fc_ctx_mem(bp);
5862 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5863 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5864 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5865 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5868 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5870 if (BNXT_FLOW_XSTATS_EN(bp))
5871 bnxt_uninit_fc_ctx_mem(bp);
5875 bnxt_free_error_recovery_info(struct bnxt *bp)
5877 rte_free(bp->recovery_info);
5878 bp->recovery_info = NULL;
5879 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5883 bnxt_uninit_locks(struct bnxt *bp)
5885 pthread_mutex_destroy(&bp->flow_lock);
5886 pthread_mutex_destroy(&bp->def_cp_lock);
5888 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5889 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
5894 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5899 bnxt_free_mem(bp, reconfig_dev);
5900 bnxt_hwrm_func_buf_unrgtr(bp);
5901 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5902 bp->flags &= ~BNXT_FLAG_REGISTERED;
5903 bnxt_free_ctx_mem(bp);
5904 if (!reconfig_dev) {
5905 bnxt_free_hwrm_resources(bp);
5906 bnxt_free_error_recovery_info(bp);
5909 bnxt_uninit_ctx_mem(bp);
5911 bnxt_uninit_locks(bp);
5912 bnxt_free_flow_stats_info(bp);
5913 bnxt_free_rep_info(bp);
5914 rte_free(bp->ptp_cfg);
5920 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5922 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5925 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5927 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5928 bnxt_dev_close_op(eth_dev);
5933 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5935 struct bnxt *bp = eth_dev->data->dev_private;
5936 struct rte_eth_dev *vf_rep_eth_dev;
5942 for (i = 0; i < bp->num_reps; i++) {
5943 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5944 if (!vf_rep_eth_dev)
5946 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5947 vf_rep_eth_dev->data->port_id);
5948 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_vf_representor_uninit);
5950 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5951 eth_dev->data->port_id);
5952 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5957 static void bnxt_free_rep_info(struct bnxt *bp)
5959 rte_free(bp->rep_info);
5960 bp->rep_info = NULL;
5961 rte_free(bp->cfa_code_map);
5962 bp->cfa_code_map = NULL;
5965 static int bnxt_init_rep_info(struct bnxt *bp)
5972 bp->rep_info = rte_zmalloc("bnxt_rep_info",
5973 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5975 if (!bp->rep_info) {
5976 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5979 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5980 sizeof(*bp->cfa_code_map) *
5981 BNXT_MAX_CFA_CODE, 0);
5982 if (!bp->cfa_code_map) {
5983 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5984 bnxt_free_rep_info(bp);
5988 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5989 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5991 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5993 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5994 bnxt_free_rep_info(bp);
5998 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6000 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6001 bnxt_free_rep_info(bp);
6008 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6009 struct rte_eth_devargs eth_da,
6010 struct rte_eth_dev *backing_eth_dev)
6012 struct rte_eth_dev *vf_rep_eth_dev;
6013 char name[RTE_ETH_NAME_MAX_LEN];
6014 struct bnxt *backing_bp;
6018 num_rep = eth_da.nb_representor_ports;
6019 if (num_rep > BNXT_MAX_VF_REPS) {
6020 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6021 num_rep, BNXT_MAX_VF_REPS);
6025 if (num_rep >= RTE_MAX_ETHPORTS) {
6027 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6028 num_rep, RTE_MAX_ETHPORTS);
6032 backing_bp = backing_eth_dev->data->dev_private;
6034 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6036 "Not a PF or trusted VF. No Representor support\n");
6037 /* Returning an error is not an option.
6038 * Applications are not handling this correctly
6043 if (bnxt_init_rep_info(backing_bp))
6046 for (i = 0; i < num_rep; i++) {
6047 struct bnxt_vf_representor representor = {
6048 .vf_id = eth_da.representor_ports[i],
6049 .switch_domain_id = backing_bp->switch_domain_id,
6050 .parent_dev = backing_eth_dev
6053 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6054 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6055 representor.vf_id, BNXT_MAX_VF_REPS);
6059 /* representor port net_bdf_port */
6060 snprintf(name, sizeof(name), "net_%s_representor_%d",
6061 pci_dev->device.name, eth_da.representor_ports[i]);
6063 ret = rte_eth_dev_create(&pci_dev->device, name,
6064 sizeof(struct bnxt_vf_representor),
6066 bnxt_vf_representor_init,
6069 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6070 "representor %s.", name);
6074 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6075 if (!vf_rep_eth_dev) {
6076 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6077 " for VF-Rep: %s.", name);
6082 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6083 backing_eth_dev->data->port_id);
6084 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6086 backing_bp->num_reps++;
6092 /* If num_rep > 1, then rollback already created
6093 * ports, since we'll be failing the probe anyway
6096 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6101 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6102 struct rte_pci_device *pci_dev)
6104 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6105 struct rte_eth_dev *backing_eth_dev;
6109 if (pci_dev->device.devargs) {
6110 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6116 num_rep = eth_da.nb_representor_ports;
6117 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6120 /* We could come here after first level of probe is already invoked
6121 * as part of an application bringup(OVS-DPDK vswitchd), so first check
6122 * for already allocated eth_dev for the backing device (PF/Trusted VF)
6124 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6125 if (backing_eth_dev == NULL) {
6126 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6127 sizeof(struct bnxt),
6128 eth_dev_pci_specific_init, pci_dev,
6129 bnxt_dev_init, NULL);
6131 if (ret || !num_rep)
6134 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6136 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6137 backing_eth_dev->data->port_id);
6138 /* probe representor ports now */
6139 ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev);
6144 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6146 struct rte_eth_dev *eth_dev;
6148 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6150 return 0; /* Invoked typically only by OVS-DPDK, by the
6151 * time it comes here the eth_dev is already
6152 * deleted by rte_eth_dev_close(), so returning
6153 * +ve value will at least help in proper cleanup
6156 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6157 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6158 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6159 return rte_eth_dev_destroy(eth_dev,
6160 bnxt_vf_representor_uninit);
6162 return rte_eth_dev_destroy(eth_dev,
6165 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6169 static struct rte_pci_driver bnxt_rte_pmd = {
6170 .id_table = bnxt_pci_id_map,
6171 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6172 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6175 .probe = bnxt_pci_probe,
6176 .remove = bnxt_pci_remove,
6180 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6182 if (strcmp(dev->device->driver->name, drv->driver.name))
6188 bool is_bnxt_supported(struct rte_eth_dev *dev)
6190 return is_device_supported(dev, &bnxt_rte_pmd);
6193 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6194 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6195 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6196 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");