1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
29 #include "bnxt_util.h"
31 #define DRV_MODULE_NAME "bnxt"
32 static const char bnxt_version[] =
33 "Broadcom NetXtreme driver " DRV_MODULE_NAME "\n";
34 int bnxt_logtype_driver;
36 #define PCI_VENDOR_ID_BROADCOM 0x14E4
38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
41 #define BROADCOM_DEV_ID_57414_VF 0x16c1
42 #define BROADCOM_DEV_ID_57301 0x16c8
43 #define BROADCOM_DEV_ID_57302 0x16c9
44 #define BROADCOM_DEV_ID_57304_PF 0x16ca
45 #define BROADCOM_DEV_ID_57304_VF 0x16cb
46 #define BROADCOM_DEV_ID_57417_MF 0x16cc
47 #define BROADCOM_DEV_ID_NS2 0x16cd
48 #define BROADCOM_DEV_ID_57311 0x16ce
49 #define BROADCOM_DEV_ID_57312 0x16cf
50 #define BROADCOM_DEV_ID_57402 0x16d0
51 #define BROADCOM_DEV_ID_57404 0x16d1
52 #define BROADCOM_DEV_ID_57406_PF 0x16d2
53 #define BROADCOM_DEV_ID_57406_VF 0x16d3
54 #define BROADCOM_DEV_ID_57402_MF 0x16d4
55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
56 #define BROADCOM_DEV_ID_57412 0x16d6
57 #define BROADCOM_DEV_ID_57414 0x16d7
58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
61 #define BROADCOM_DEV_ID_57412_MF 0x16de
62 #define BROADCOM_DEV_ID_57314 0x16df
63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
68 #define BROADCOM_DEV_ID_57404_MF 0x16e7
69 #define BROADCOM_DEV_ID_57406_MF 0x16e8
70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
71 #define BROADCOM_DEV_ID_57407_MF 0x16ea
72 #define BROADCOM_DEV_ID_57414_MF 0x16ec
73 #define BROADCOM_DEV_ID_57416_MF 0x16ee
74 #define BROADCOM_DEV_ID_58802 0xd802
75 #define BROADCOM_DEV_ID_58804 0xd804
76 #define BROADCOM_DEV_ID_58808 0x16f0
77 #define BROADCOM_DEV_ID_58802_VF 0xd800
79 static const struct rte_pci_id bnxt_pci_id_map[] = {
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
81 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
83 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
122 { .vendor_id = 0, /* sentinel */ },
125 #define BNXT_ETH_RSS_SUPPORT ( \
127 ETH_RSS_NONFRAG_IPV4_TCP | \
128 ETH_RSS_NONFRAG_IPV4_UDP | \
130 ETH_RSS_NONFRAG_IPV6_TCP | \
131 ETH_RSS_NONFRAG_IPV6_UDP)
133 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
134 DEV_TX_OFFLOAD_IPV4_CKSUM | \
135 DEV_TX_OFFLOAD_TCP_CKSUM | \
136 DEV_TX_OFFLOAD_UDP_CKSUM | \
137 DEV_TX_OFFLOAD_TCP_TSO | \
138 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
139 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
140 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
141 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
142 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
143 DEV_TX_OFFLOAD_MULTI_SEGS)
145 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
146 DEV_RX_OFFLOAD_VLAN_STRIP | \
147 DEV_RX_OFFLOAD_IPV4_CKSUM | \
148 DEV_RX_OFFLOAD_UDP_CKSUM | \
149 DEV_RX_OFFLOAD_TCP_CKSUM | \
150 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
151 DEV_RX_OFFLOAD_JUMBO_FRAME | \
152 DEV_RX_OFFLOAD_CRC_STRIP | \
153 DEV_RX_OFFLOAD_KEEP_CRC | \
154 DEV_RX_OFFLOAD_TCP_LRO)
156 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
157 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
158 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
159 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
161 /***********************/
164 * High level utility functions
167 static void bnxt_free_mem(struct bnxt *bp)
169 bnxt_free_filter_mem(bp);
170 bnxt_free_vnic_attributes(bp);
171 bnxt_free_vnic_mem(bp);
174 bnxt_free_tx_rings(bp);
175 bnxt_free_rx_rings(bp);
178 static int bnxt_alloc_mem(struct bnxt *bp)
182 rc = bnxt_alloc_vnic_mem(bp);
186 rc = bnxt_alloc_vnic_attributes(bp);
190 rc = bnxt_alloc_filter_mem(bp);
201 static int bnxt_init_chip(struct bnxt *bp)
203 struct bnxt_rx_queue *rxq;
204 struct rte_eth_link new;
205 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
206 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
207 uint32_t intr_vector = 0;
208 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
209 uint32_t vec = BNXT_MISC_VEC_ID;
213 /* disable uio/vfio intr/eventfd mapping */
214 rte_intr_disable(intr_handle);
216 if (bp->eth_dev->data->mtu > ETHER_MTU) {
217 bp->eth_dev->data->dev_conf.rxmode.offloads |=
218 DEV_RX_OFFLOAD_JUMBO_FRAME;
219 bp->flags |= BNXT_FLAG_JUMBO;
221 bp->eth_dev->data->dev_conf.rxmode.offloads &=
222 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
223 bp->flags &= ~BNXT_FLAG_JUMBO;
226 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
228 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
232 rc = bnxt_alloc_hwrm_rings(bp);
234 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
238 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
240 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
244 rc = bnxt_mq_rx_configure(bp);
246 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
250 /* VNIC configuration */
251 for (i = 0; i < bp->nr_vnics; i++) {
252 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
254 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
256 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
261 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
264 "HWRM vnic %d ctx alloc failure rc: %x\n",
269 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
271 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
276 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
279 "HWRM vnic %d filter failure rc: %x\n",
284 for (j = 0; j < bp->rx_nr_rings; j++) {
285 rxq = bp->eth_dev->data->rx_queues[j];
287 if (rxq->rx_deferred_start)
288 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
291 rc = bnxt_vnic_rss_configure(bp, vnic);
294 "HWRM vnic set RSS failure rc: %x\n", rc);
298 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
300 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
301 DEV_RX_OFFLOAD_TCP_LRO)
302 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
304 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
306 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
309 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
313 /* check and configure queue intr-vector mapping */
314 if ((rte_intr_cap_multiple(intr_handle) ||
315 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
316 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
317 intr_vector = bp->eth_dev->data->nb_rx_queues;
318 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
319 if (intr_vector > bp->rx_cp_nr_rings) {
320 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
324 if (rte_intr_efd_enable(intr_handle, intr_vector))
328 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
329 intr_handle->intr_vec =
330 rte_zmalloc("intr_vec",
331 bp->eth_dev->data->nb_rx_queues *
333 if (intr_handle->intr_vec == NULL) {
334 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
335 " intr_vec", bp->eth_dev->data->nb_rx_queues);
338 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
339 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
340 intr_handle->intr_vec, intr_handle->nb_efd,
341 intr_handle->max_intr);
344 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
346 intr_handle->intr_vec[queue_id] = vec;
347 if (vec < base + intr_handle->nb_efd - 1)
351 /* enable uio/vfio intr/eventfd mapping */
352 rte_intr_enable(intr_handle);
354 rc = bnxt_get_hwrm_link_config(bp, &new);
356 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
360 if (!bp->link_info.link_up) {
361 rc = bnxt_set_hwrm_link_config(bp, true);
364 "HWRM link config failure rc: %x\n", rc);
368 bnxt_print_link_info(bp->eth_dev);
373 bnxt_free_all_hwrm_resources(bp);
375 /* Some of the error status returned by FW may not be from errno.h */
382 static int bnxt_shutdown_nic(struct bnxt *bp)
384 bnxt_free_all_hwrm_resources(bp);
385 bnxt_free_all_filters(bp);
386 bnxt_free_all_vnics(bp);
390 static int bnxt_init_nic(struct bnxt *bp)
394 rc = bnxt_init_ring_grps(bp);
399 bnxt_init_filters(bp);
405 * Device configuration and status function
408 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
409 struct rte_eth_dev_info *dev_info)
411 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
412 uint16_t max_vnics, i, j, vpool, vrxq;
413 unsigned int max_rx_rings;
416 dev_info->max_mac_addrs = bp->max_l2_ctx;
417 dev_info->max_hash_mac_addrs = 0;
419 /* PF/VF specifics */
421 dev_info->max_vfs = bp->pdev->max_vfs;
422 max_rx_rings = RTE_MIN(bp->max_vnics, bp->max_stat_ctx);
423 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
424 dev_info->max_rx_queues = max_rx_rings;
425 dev_info->max_tx_queues = max_rx_rings;
426 dev_info->reta_size = bp->max_rsscos_ctx;
427 dev_info->hash_key_size = 40;
428 max_vnics = bp->max_vnics;
430 /* Fast path specifics */
431 dev_info->min_rx_bufsize = 1;
432 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
435 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
436 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
437 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
438 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
439 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
442 dev_info->default_rxconf = (struct rte_eth_rxconf) {
448 .rx_free_thresh = 32,
449 /* If no descriptors available, pkts are dropped by default */
453 dev_info->default_txconf = (struct rte_eth_txconf) {
459 .tx_free_thresh = 32,
462 eth_dev->data->dev_conf.intr_conf.lsc = 1;
464 eth_dev->data->dev_conf.intr_conf.rxq = 1;
465 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
466 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
467 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
468 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
473 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
474 * need further investigation.
478 vpool = 64; /* ETH_64_POOLS */
479 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
480 for (i = 0; i < 4; vpool >>= 1, i++) {
481 if (max_vnics > vpool) {
482 for (j = 0; j < 5; vrxq >>= 1, j++) {
483 if (dev_info->max_rx_queues > vrxq) {
489 /* Not enough resources to support VMDq */
493 /* Not enough resources to support VMDq */
497 dev_info->max_vmdq_pools = vpool;
498 dev_info->vmdq_queue_num = vrxq;
500 dev_info->vmdq_pool_base = 0;
501 dev_info->vmdq_queue_base = 0;
504 /* Configure the device based on the configuration provided */
505 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
507 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
508 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
510 bp->rx_queues = (void *)eth_dev->data->rx_queues;
511 bp->tx_queues = (void *)eth_dev->data->tx_queues;
512 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
513 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
515 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
518 rc = bnxt_hwrm_func_reserve_vf_resc(bp);
520 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
524 /* legacy driver needs to get updated values */
525 rc = bnxt_hwrm_func_qcaps(bp);
527 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
532 /* Inherit new configurations */
533 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
534 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
535 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
537 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
539 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) {
541 "Insufficient resources to support requested config\n");
543 "Num Queues Requested: Tx %d, Rx %d\n",
544 eth_dev->data->nb_tx_queues,
545 eth_dev->data->nb_rx_queues);
547 "Res available: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d\n",
548 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
549 bp->max_stat_ctx, bp->max_ring_grps);
553 bp->rx_cp_nr_rings = bp->rx_nr_rings;
554 bp->tx_cp_nr_rings = bp->tx_nr_rings;
556 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
558 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
559 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE *
561 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
566 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
568 struct rte_eth_link *link = ð_dev->data->dev_link;
570 if (link->link_status)
571 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
572 eth_dev->data->port_id,
573 (uint32_t)link->link_speed,
574 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
575 ("full-duplex") : ("half-duplex\n"));
577 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
578 eth_dev->data->port_id);
581 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
583 bnxt_print_link_info(eth_dev);
587 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
589 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
590 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
594 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
596 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
597 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
601 rc = bnxt_init_chip(bp);
605 bnxt_link_update_op(eth_dev, 1);
607 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
608 vlan_mask |= ETH_VLAN_FILTER_MASK;
609 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
610 vlan_mask |= ETH_VLAN_STRIP_MASK;
611 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
615 bp->flags |= BNXT_FLAG_INIT_DONE;
619 bnxt_shutdown_nic(bp);
620 bnxt_free_tx_mbufs(bp);
621 bnxt_free_rx_mbufs(bp);
625 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
627 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
630 if (!bp->link_info.link_up)
631 rc = bnxt_set_hwrm_link_config(bp, true);
633 eth_dev->data->dev_link.link_status = 1;
635 bnxt_print_link_info(eth_dev);
639 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
641 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
643 eth_dev->data->dev_link.link_status = 0;
644 bnxt_set_hwrm_link_config(bp, false);
645 bp->link_info.link_up = 0;
650 /* Unload the driver, release resources */
651 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
653 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
655 bp->flags &= ~BNXT_FLAG_INIT_DONE;
656 if (bp->eth_dev->data->dev_started) {
657 /* TBD: STOP HW queues DMA */
658 eth_dev->data->dev_link.link_status = 0;
660 bnxt_set_hwrm_link_config(bp, false);
661 bnxt_hwrm_port_clr_stats(bp);
662 bnxt_free_tx_mbufs(bp);
663 bnxt_free_rx_mbufs(bp);
664 bnxt_shutdown_nic(bp);
668 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
670 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
672 if (bp->dev_stopped == 0)
673 bnxt_dev_stop_op(eth_dev);
676 if (eth_dev->data->mac_addrs != NULL) {
677 rte_free(eth_dev->data->mac_addrs);
678 eth_dev->data->mac_addrs = NULL;
680 if (bp->grp_info != NULL) {
681 rte_free(bp->grp_info);
685 bnxt_dev_uninit(eth_dev);
688 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
691 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
692 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
693 struct bnxt_vnic_info *vnic;
694 struct bnxt_filter_info *filter, *temp_filter;
695 uint32_t pool = RTE_MIN(MAX_FF_POOLS, ETH_64_POOLS);
699 * Loop through all VNICs from the specified filter flow pools to
700 * remove the corresponding MAC addr filter
702 for (i = 0; i < pool; i++) {
703 if (!(pool_mask & (1ULL << i)))
706 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
707 filter = STAILQ_FIRST(&vnic->filter);
709 temp_filter = STAILQ_NEXT(filter, next);
710 if (filter->mac_index == index) {
711 STAILQ_REMOVE(&vnic->filter, filter,
712 bnxt_filter_info, next);
713 bnxt_hwrm_clear_l2_filter(bp, filter);
714 filter->mac_index = INVALID_MAC_INDEX;
715 memset(&filter->l2_addr, 0,
718 &bp->free_filter_list,
721 filter = temp_filter;
727 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
728 struct ether_addr *mac_addr,
729 uint32_t index, uint32_t pool)
731 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
732 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
733 struct bnxt_filter_info *filter;
736 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
741 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
744 /* Attach requested MAC address to the new l2_filter */
745 STAILQ_FOREACH(filter, &vnic->filter, next) {
746 if (filter->mac_index == index) {
748 "MAC addr already existed for pool %d\n", pool);
752 filter = bnxt_alloc_filter(bp);
754 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
757 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
758 filter->mac_index = index;
759 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
760 return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
763 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
766 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
767 struct rte_eth_link new;
768 unsigned int cnt = BNXT_LINK_WAIT_CNT;
770 memset(&new, 0, sizeof(new));
772 /* Retrieve link info from hardware */
773 rc = bnxt_get_hwrm_link_config(bp, &new);
775 new.link_speed = ETH_LINK_SPEED_100M;
776 new.link_duplex = ETH_LINK_FULL_DUPLEX;
778 "Failed to retrieve link rc = 0x%x!\n", rc);
781 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
783 if (!wait_to_complete)
785 } while (!new.link_status && cnt--);
788 /* Timed out or success */
789 if (new.link_status != eth_dev->data->dev_link.link_status ||
790 new.link_speed != eth_dev->data->dev_link.link_speed) {
791 memcpy(ð_dev->data->dev_link, &new,
792 sizeof(struct rte_eth_link));
794 _rte_eth_dev_callback_process(eth_dev,
795 RTE_ETH_EVENT_INTR_LSC,
798 bnxt_print_link_info(eth_dev);
804 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
806 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
807 struct bnxt_vnic_info *vnic;
809 if (bp->vnic_info == NULL)
812 vnic = &bp->vnic_info[0];
814 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
815 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
818 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
820 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
821 struct bnxt_vnic_info *vnic;
823 if (bp->vnic_info == NULL)
826 vnic = &bp->vnic_info[0];
828 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
829 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
832 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
834 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
835 struct bnxt_vnic_info *vnic;
837 if (bp->vnic_info == NULL)
840 vnic = &bp->vnic_info[0];
842 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
843 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
846 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
848 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
849 struct bnxt_vnic_info *vnic;
851 if (bp->vnic_info == NULL)
854 vnic = &bp->vnic_info[0];
856 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
857 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
860 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
861 struct rte_eth_rss_reta_entry64 *reta_conf,
864 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
865 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
866 struct bnxt_vnic_info *vnic;
869 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
872 if (reta_size != HW_HASH_INDEX_SIZE) {
873 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
874 "(%d) must equal the size supported by the hardware "
875 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
878 /* Update the RSS VNIC(s) */
879 for (i = 0; i < MAX_FF_POOLS; i++) {
880 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
881 memcpy(vnic->rss_table, reta_conf, reta_size);
883 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
889 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
890 struct rte_eth_rss_reta_entry64 *reta_conf,
893 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
894 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
895 struct rte_intr_handle *intr_handle
896 = &bp->pdev->intr_handle;
898 /* Retrieve from the default VNIC */
901 if (!vnic->rss_table)
904 if (reta_size != HW_HASH_INDEX_SIZE) {
905 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
906 "(%d) must equal the size supported by the hardware "
907 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
910 /* EW - need to revisit here copying from uint64_t to uint16_t */
911 memcpy(reta_conf, vnic->rss_table, reta_size);
913 if (rte_intr_allow_others(intr_handle)) {
914 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
915 bnxt_dev_lsc_intr_setup(eth_dev);
921 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
922 struct rte_eth_rss_conf *rss_conf)
924 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
925 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
926 struct bnxt_vnic_info *vnic;
927 uint16_t hash_type = 0;
931 * If RSS enablement were different than dev_configure,
932 * then return -EINVAL
934 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
935 if (!rss_conf->rss_hf)
936 PMD_DRV_LOG(ERR, "Hash type NONE\n");
938 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
942 bp->flags |= BNXT_FLAG_UPDATE_HASH;
943 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
945 if (rss_conf->rss_hf & ETH_RSS_IPV4)
946 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
947 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
948 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
949 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
950 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
951 if (rss_conf->rss_hf & ETH_RSS_IPV6)
952 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
953 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
954 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
955 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
956 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
958 /* Update the RSS VNIC(s) */
959 for (i = 0; i < MAX_FF_POOLS; i++) {
960 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
961 vnic->hash_type = hash_type;
964 * Use the supplied key if the key length is
965 * acceptable and the rss_key is not NULL
967 if (rss_conf->rss_key &&
968 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
969 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
970 rss_conf->rss_key_len);
972 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
978 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
979 struct rte_eth_rss_conf *rss_conf)
981 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
982 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
986 /* RSS configuration is the same for all VNICs */
987 if (vnic && vnic->rss_hash_key) {
988 if (rss_conf->rss_key) {
989 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
990 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
991 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
994 hash_types = vnic->hash_type;
995 rss_conf->rss_hf = 0;
996 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
997 rss_conf->rss_hf |= ETH_RSS_IPV4;
998 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1000 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1001 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1003 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1005 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1006 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1008 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1010 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1011 rss_conf->rss_hf |= ETH_RSS_IPV6;
1012 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1014 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1015 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1017 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1019 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1020 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1022 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1026 "Unknwon RSS config from firmware (%08x), RSS disabled",
1031 rss_conf->rss_hf = 0;
1036 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1037 struct rte_eth_fc_conf *fc_conf)
1039 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1040 struct rte_eth_link link_info;
1043 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1047 memset(fc_conf, 0, sizeof(*fc_conf));
1048 if (bp->link_info.auto_pause)
1049 fc_conf->autoneg = 1;
1050 switch (bp->link_info.pause) {
1052 fc_conf->mode = RTE_FC_NONE;
1054 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1055 fc_conf->mode = RTE_FC_TX_PAUSE;
1057 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1058 fc_conf->mode = RTE_FC_RX_PAUSE;
1060 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1061 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1062 fc_conf->mode = RTE_FC_FULL;
1068 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1069 struct rte_eth_fc_conf *fc_conf)
1071 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1073 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1074 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1078 switch (fc_conf->mode) {
1080 bp->link_info.auto_pause = 0;
1081 bp->link_info.force_pause = 0;
1083 case RTE_FC_RX_PAUSE:
1084 if (fc_conf->autoneg) {
1085 bp->link_info.auto_pause =
1086 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1087 bp->link_info.force_pause = 0;
1089 bp->link_info.auto_pause = 0;
1090 bp->link_info.force_pause =
1091 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1094 case RTE_FC_TX_PAUSE:
1095 if (fc_conf->autoneg) {
1096 bp->link_info.auto_pause =
1097 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1098 bp->link_info.force_pause = 0;
1100 bp->link_info.auto_pause = 0;
1101 bp->link_info.force_pause =
1102 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1106 if (fc_conf->autoneg) {
1107 bp->link_info.auto_pause =
1108 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1109 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1110 bp->link_info.force_pause = 0;
1112 bp->link_info.auto_pause = 0;
1113 bp->link_info.force_pause =
1114 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1115 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1119 return bnxt_set_hwrm_link_config(bp, true);
1122 /* Add UDP tunneling port */
1124 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1125 struct rte_eth_udp_tunnel *udp_tunnel)
1127 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1128 uint16_t tunnel_type = 0;
1131 switch (udp_tunnel->prot_type) {
1132 case RTE_TUNNEL_TYPE_VXLAN:
1133 if (bp->vxlan_port_cnt) {
1134 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1135 udp_tunnel->udp_port);
1136 if (bp->vxlan_port != udp_tunnel->udp_port) {
1137 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1140 bp->vxlan_port_cnt++;
1144 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1145 bp->vxlan_port_cnt++;
1147 case RTE_TUNNEL_TYPE_GENEVE:
1148 if (bp->geneve_port_cnt) {
1149 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1150 udp_tunnel->udp_port);
1151 if (bp->geneve_port != udp_tunnel->udp_port) {
1152 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1155 bp->geneve_port_cnt++;
1159 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1160 bp->geneve_port_cnt++;
1163 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1166 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1172 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1173 struct rte_eth_udp_tunnel *udp_tunnel)
1175 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1176 uint16_t tunnel_type = 0;
1180 switch (udp_tunnel->prot_type) {
1181 case RTE_TUNNEL_TYPE_VXLAN:
1182 if (!bp->vxlan_port_cnt) {
1183 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1186 if (bp->vxlan_port != udp_tunnel->udp_port) {
1187 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1188 udp_tunnel->udp_port, bp->vxlan_port);
1191 if (--bp->vxlan_port_cnt)
1195 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1196 port = bp->vxlan_fw_dst_port_id;
1198 case RTE_TUNNEL_TYPE_GENEVE:
1199 if (!bp->geneve_port_cnt) {
1200 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1203 if (bp->geneve_port != udp_tunnel->udp_port) {
1204 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1205 udp_tunnel->udp_port, bp->geneve_port);
1208 if (--bp->geneve_port_cnt)
1212 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1213 port = bp->geneve_fw_dst_port_id;
1216 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1220 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1223 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1226 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1227 bp->geneve_port = 0;
1232 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1234 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1235 struct bnxt_vnic_info *vnic;
1238 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1240 /* Cycle through all VNICs */
1241 for (i = 0; i < bp->nr_vnics; i++) {
1243 * For each VNIC and each associated filter(s)
1244 * if VLAN exists && VLAN matches vlan_id
1245 * remove the MAC+VLAN filter
1246 * add a new MAC only filter
1248 * VLAN filter doesn't exist, just skip and continue
1250 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1251 filter = STAILQ_FIRST(&vnic->filter);
1253 temp_filter = STAILQ_NEXT(filter, next);
1255 if (filter->enables & chk &&
1256 filter->l2_ovlan == vlan_id) {
1257 /* Must delete the filter */
1258 STAILQ_REMOVE(&vnic->filter, filter,
1259 bnxt_filter_info, next);
1260 bnxt_hwrm_clear_l2_filter(bp, filter);
1262 &bp->free_filter_list,
1266 * Need to examine to see if the MAC
1267 * filter already existed or not before
1268 * allocating a new one
1271 new_filter = bnxt_alloc_filter(bp);
1274 "MAC/VLAN filter alloc failed\n");
1278 STAILQ_INSERT_TAIL(&vnic->filter,
1280 /* Inherit MAC from previous filter */
1281 new_filter->mac_index =
1283 memcpy(new_filter->l2_addr,
1284 filter->l2_addr, ETHER_ADDR_LEN);
1285 /* MAC only filter */
1286 rc = bnxt_hwrm_set_l2_filter(bp,
1292 "Del Vlan filter for %d\n",
1295 filter = temp_filter;
1303 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1305 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1306 struct bnxt_vnic_info *vnic;
1309 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN |
1310 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK;
1311 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1313 /* Cycle through all VNICs */
1314 for (i = 0; i < bp->nr_vnics; i++) {
1316 * For each VNIC and each associated filter(s)
1318 * if VLAN matches vlan_id
1319 * VLAN filter already exists, just skip and continue
1321 * add a new MAC+VLAN filter
1323 * Remove the old MAC only filter
1324 * Add a new MAC+VLAN filter
1326 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1327 filter = STAILQ_FIRST(&vnic->filter);
1329 temp_filter = STAILQ_NEXT(filter, next);
1331 if (filter->enables & chk) {
1332 if (filter->l2_ovlan == vlan_id)
1335 /* Must delete the MAC filter */
1336 STAILQ_REMOVE(&vnic->filter, filter,
1337 bnxt_filter_info, next);
1338 bnxt_hwrm_clear_l2_filter(bp, filter);
1339 filter->l2_ovlan = 0;
1341 &bp->free_filter_list,
1344 new_filter = bnxt_alloc_filter(bp);
1347 "MAC/VLAN filter alloc failed\n");
1351 STAILQ_INSERT_TAIL(&vnic->filter, new_filter,
1353 /* Inherit MAC from the previous filter */
1354 new_filter->mac_index = filter->mac_index;
1355 memcpy(new_filter->l2_addr, filter->l2_addr,
1357 /* MAC + VLAN ID filter */
1358 new_filter->l2_ovlan = vlan_id;
1359 new_filter->l2_ovlan_mask = 0xF000;
1360 new_filter->enables |= en;
1361 rc = bnxt_hwrm_set_l2_filter(bp,
1367 "Added Vlan filter for %d\n", vlan_id);
1369 filter = temp_filter;
1377 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1378 uint16_t vlan_id, int on)
1380 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1382 /* These operations apply to ALL existing MAC/VLAN filters */
1384 return bnxt_add_vlan_filter(bp, vlan_id);
1386 return bnxt_del_vlan_filter(bp, vlan_id);
1390 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1392 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1393 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1396 if (mask & ETH_VLAN_FILTER_MASK) {
1397 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1398 /* Remove any VLAN filters programmed */
1399 for (i = 0; i < 4095; i++)
1400 bnxt_del_vlan_filter(bp, i);
1402 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1403 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1406 if (mask & ETH_VLAN_STRIP_MASK) {
1407 /* Enable or disable VLAN stripping */
1408 for (i = 0; i < bp->nr_vnics; i++) {
1409 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1410 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1411 vnic->vlan_strip = true;
1413 vnic->vlan_strip = false;
1414 bnxt_hwrm_vnic_cfg(bp, vnic);
1416 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1417 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1420 if (mask & ETH_VLAN_EXTEND_MASK)
1421 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1427 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr)
1429 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1430 /* Default Filter is tied to VNIC 0 */
1431 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1432 struct bnxt_filter_info *filter;
1438 memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1440 STAILQ_FOREACH(filter, &vnic->filter, next) {
1441 /* Default Filter is at Index 0 */
1442 if (filter->mac_index != 0)
1444 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1447 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN);
1448 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN);
1449 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1451 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1452 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1453 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1456 filter->mac_index = 0;
1457 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1464 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1465 struct ether_addr *mc_addr_set,
1466 uint32_t nb_mc_addr)
1468 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1469 char *mc_addr_list = (char *)mc_addr_set;
1470 struct bnxt_vnic_info *vnic;
1471 uint32_t off = 0, i = 0;
1473 vnic = &bp->vnic_info[0];
1475 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1476 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1480 /* TODO Check for Duplicate mcast addresses */
1481 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1482 for (i = 0; i < nb_mc_addr; i++) {
1483 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN);
1484 off += ETHER_ADDR_LEN;
1487 vnic->mc_addr_cnt = i;
1490 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1494 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1496 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1497 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1498 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1499 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1502 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1503 fw_major, fw_minor, fw_updt);
1505 ret += 1; /* add the size of '\0' */
1506 if (fw_size < (uint32_t)ret)
1513 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1514 struct rte_eth_rxq_info *qinfo)
1516 struct bnxt_rx_queue *rxq;
1518 rxq = dev->data->rx_queues[queue_id];
1520 qinfo->mp = rxq->mb_pool;
1521 qinfo->scattered_rx = dev->data->scattered_rx;
1522 qinfo->nb_desc = rxq->nb_rx_desc;
1524 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1525 qinfo->conf.rx_drop_en = 0;
1526 qinfo->conf.rx_deferred_start = 0;
1530 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1531 struct rte_eth_txq_info *qinfo)
1533 struct bnxt_tx_queue *txq;
1535 txq = dev->data->tx_queues[queue_id];
1537 qinfo->nb_desc = txq->nb_tx_desc;
1539 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1540 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1541 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1543 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1544 qinfo->conf.tx_rs_thresh = 0;
1545 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1548 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1550 struct bnxt *bp = eth_dev->data->dev_private;
1551 struct rte_eth_dev_info dev_info;
1552 uint32_t max_dev_mtu;
1556 bnxt_dev_info_get_op(eth_dev, &dev_info);
1557 max_dev_mtu = dev_info.max_rx_pktlen -
1558 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2;
1560 if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) {
1561 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1562 ETHER_MIN_MTU, max_dev_mtu);
1567 if (new_mtu > ETHER_MTU) {
1568 bp->flags |= BNXT_FLAG_JUMBO;
1569 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1570 DEV_RX_OFFLOAD_JUMBO_FRAME;
1572 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1573 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1574 bp->flags &= ~BNXT_FLAG_JUMBO;
1577 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
1578 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1580 eth_dev->data->mtu = new_mtu;
1581 PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1583 for (i = 0; i < bp->nr_vnics; i++) {
1584 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1586 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1587 ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1588 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1592 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1601 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1603 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1604 uint16_t vlan = bp->vlan;
1607 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1609 "PVID cannot be modified for this function\n");
1612 bp->vlan = on ? pvid : 0;
1614 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1621 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1623 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1625 return bnxt_hwrm_port_led_cfg(bp, true);
1629 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1631 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1633 return bnxt_hwrm_port_led_cfg(bp, false);
1637 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1639 uint32_t desc = 0, raw_cons = 0, cons;
1640 struct bnxt_cp_ring_info *cpr;
1641 struct bnxt_rx_queue *rxq;
1642 struct rx_pkt_cmpl *rxcmp;
1647 rxq = dev->data->rx_queues[rx_queue_id];
1651 while (raw_cons < rxq->nb_rx_desc) {
1652 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1653 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1655 if (!CMPL_VALID(rxcmp, valid))
1657 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1658 cmp_type = CMP_TYPE(rxcmp);
1659 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1660 cmp = (rte_le_to_cpu_32(
1661 ((struct rx_tpa_end_cmpl *)
1662 (rxcmp))->agg_bufs_v1) &
1663 RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1664 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1666 } else if (cmp_type == 0x11) {
1668 cmp = (rxcmp->agg_bufs_v1 &
1669 RX_PKT_CMPL_AGG_BUFS_MASK) >>
1670 RX_PKT_CMPL_AGG_BUFS_SFT;
1675 raw_cons += cmp ? cmp : 2;
1682 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1684 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1685 struct bnxt_rx_ring_info *rxr;
1686 struct bnxt_cp_ring_info *cpr;
1687 struct bnxt_sw_rx_bd *rx_buf;
1688 struct rx_pkt_cmpl *rxcmp;
1689 uint32_t cons, cp_cons;
1697 if (offset >= rxq->nb_rx_desc)
1700 cons = RING_CMP(cpr->cp_ring_struct, offset);
1701 cp_cons = cpr->cp_raw_cons;
1702 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1704 if (cons > cp_cons) {
1705 if (CMPL_VALID(rxcmp, cpr->valid))
1706 return RTE_ETH_RX_DESC_DONE;
1708 if (CMPL_VALID(rxcmp, !cpr->valid))
1709 return RTE_ETH_RX_DESC_DONE;
1711 rx_buf = &rxr->rx_buf_ring[cons];
1712 if (rx_buf->mbuf == NULL)
1713 return RTE_ETH_RX_DESC_UNAVAIL;
1716 return RTE_ETH_RX_DESC_AVAIL;
1720 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1722 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1723 struct bnxt_tx_ring_info *txr;
1724 struct bnxt_cp_ring_info *cpr;
1725 struct bnxt_sw_tx_bd *tx_buf;
1726 struct tx_pkt_cmpl *txcmp;
1727 uint32_t cons, cp_cons;
1735 if (offset >= txq->nb_tx_desc)
1738 cons = RING_CMP(cpr->cp_ring_struct, offset);
1739 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1740 cp_cons = cpr->cp_raw_cons;
1742 if (cons > cp_cons) {
1743 if (CMPL_VALID(txcmp, cpr->valid))
1744 return RTE_ETH_TX_DESC_UNAVAIL;
1746 if (CMPL_VALID(txcmp, !cpr->valid))
1747 return RTE_ETH_TX_DESC_UNAVAIL;
1749 tx_buf = &txr->tx_buf_ring[cons];
1750 if (tx_buf->mbuf == NULL)
1751 return RTE_ETH_TX_DESC_DONE;
1753 return RTE_ETH_TX_DESC_FULL;
1756 static struct bnxt_filter_info *
1757 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1758 struct rte_eth_ethertype_filter *efilter,
1759 struct bnxt_vnic_info *vnic0,
1760 struct bnxt_vnic_info *vnic,
1763 struct bnxt_filter_info *mfilter = NULL;
1767 if (efilter->ether_type == ETHER_TYPE_IPv4 ||
1768 efilter->ether_type == ETHER_TYPE_IPv6) {
1769 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
1770 " ethertype filter.", efilter->ether_type);
1774 if (efilter->queue >= bp->rx_nr_rings) {
1775 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1780 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1781 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1783 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1788 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1789 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1790 if ((!memcmp(efilter->mac_addr.addr_bytes,
1791 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1793 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1794 mfilter->ethertype == efilter->ether_type)) {
1800 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1801 if ((!memcmp(efilter->mac_addr.addr_bytes,
1802 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1803 mfilter->ethertype == efilter->ether_type &&
1805 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
1819 bnxt_ethertype_filter(struct rte_eth_dev *dev,
1820 enum rte_filter_op filter_op,
1823 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1824 struct rte_eth_ethertype_filter *efilter =
1825 (struct rte_eth_ethertype_filter *)arg;
1826 struct bnxt_filter_info *bfilter, *filter1;
1827 struct bnxt_vnic_info *vnic, *vnic0;
1830 if (filter_op == RTE_ETH_FILTER_NOP)
1834 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
1839 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1840 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1842 switch (filter_op) {
1843 case RTE_ETH_FILTER_ADD:
1844 bnxt_match_and_validate_ether_filter(bp, efilter,
1849 bfilter = bnxt_get_unused_filter(bp);
1850 if (bfilter == NULL) {
1852 "Not enough resources for a new filter.\n");
1855 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
1856 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
1858 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
1860 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
1861 bfilter->ethertype = efilter->ether_type;
1862 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
1864 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
1865 if (filter1 == NULL) {
1870 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
1871 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
1873 bfilter->dst_id = vnic->fw_vnic_id;
1875 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1877 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
1880 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
1883 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
1885 case RTE_ETH_FILTER_DELETE:
1886 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
1888 if (ret == -EEXIST) {
1889 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
1891 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
1893 bnxt_free_filter(bp, filter1);
1894 } else if (ret == 0) {
1895 PMD_DRV_LOG(ERR, "No matching filter found\n");
1899 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
1905 bnxt_free_filter(bp, bfilter);
1911 parse_ntuple_filter(struct bnxt *bp,
1912 struct rte_eth_ntuple_filter *nfilter,
1913 struct bnxt_filter_info *bfilter)
1917 if (nfilter->queue >= bp->rx_nr_rings) {
1918 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
1922 switch (nfilter->dst_port_mask) {
1924 bfilter->dst_port_mask = -1;
1925 bfilter->dst_port = nfilter->dst_port;
1926 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
1927 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
1930 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
1934 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
1935 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1937 switch (nfilter->proto_mask) {
1939 if (nfilter->proto == 17) /* IPPROTO_UDP */
1940 bfilter->ip_protocol = 17;
1941 else if (nfilter->proto == 6) /* IPPROTO_TCP */
1942 bfilter->ip_protocol = 6;
1945 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1948 PMD_DRV_LOG(ERR, "invalid protocol mask.");
1952 switch (nfilter->dst_ip_mask) {
1954 bfilter->dst_ipaddr_mask[0] = -1;
1955 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
1956 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
1957 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
1960 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
1964 switch (nfilter->src_ip_mask) {
1966 bfilter->src_ipaddr_mask[0] = -1;
1967 bfilter->src_ipaddr[0] = nfilter->src_ip;
1968 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
1969 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
1972 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
1976 switch (nfilter->src_port_mask) {
1978 bfilter->src_port_mask = -1;
1979 bfilter->src_port = nfilter->src_port;
1980 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
1981 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
1984 PMD_DRV_LOG(ERR, "invalid src_port mask.");
1989 //nfilter->priority = (uint8_t)filter->priority;
1991 bfilter->enables = en;
1995 static struct bnxt_filter_info*
1996 bnxt_match_ntuple_filter(struct bnxt *bp,
1997 struct bnxt_filter_info *bfilter,
1998 struct bnxt_vnic_info **mvnic)
2000 struct bnxt_filter_info *mfilter = NULL;
2003 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2004 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2005 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2006 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2007 bfilter->src_ipaddr_mask[0] ==
2008 mfilter->src_ipaddr_mask[0] &&
2009 bfilter->src_port == mfilter->src_port &&
2010 bfilter->src_port_mask == mfilter->src_port_mask &&
2011 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2012 bfilter->dst_ipaddr_mask[0] ==
2013 mfilter->dst_ipaddr_mask[0] &&
2014 bfilter->dst_port == mfilter->dst_port &&
2015 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2016 bfilter->flags == mfilter->flags &&
2017 bfilter->enables == mfilter->enables) {
2028 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2029 struct rte_eth_ntuple_filter *nfilter,
2030 enum rte_filter_op filter_op)
2032 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2033 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2036 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2037 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2041 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2042 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2046 bfilter = bnxt_get_unused_filter(bp);
2047 if (bfilter == NULL) {
2049 "Not enough resources for a new filter.\n");
2052 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2056 vnic = STAILQ_FIRST(&bp->ff_pool[nfilter->queue]);
2057 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2058 filter1 = STAILQ_FIRST(&vnic0->filter);
2059 if (filter1 == NULL) {
2064 bfilter->dst_id = vnic->fw_vnic_id;
2065 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2067 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2068 bfilter->ethertype = 0x800;
2069 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2071 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2073 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2074 bfilter->dst_id == mfilter->dst_id) {
2075 PMD_DRV_LOG(ERR, "filter exists.\n");
2078 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2079 bfilter->dst_id != mfilter->dst_id) {
2080 mfilter->dst_id = vnic->fw_vnic_id;
2081 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2082 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2083 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2084 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2085 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2088 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2089 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2094 if (filter_op == RTE_ETH_FILTER_ADD) {
2095 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2096 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2099 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2101 if (mfilter == NULL) {
2102 /* This should not happen. But for Coverity! */
2106 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2108 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2109 bnxt_free_filter(bp, mfilter);
2110 mfilter->fw_l2_filter_id = -1;
2111 bnxt_free_filter(bp, bfilter);
2112 bfilter->fw_l2_filter_id = -1;
2117 bfilter->fw_l2_filter_id = -1;
2118 bnxt_free_filter(bp, bfilter);
2123 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2124 enum rte_filter_op filter_op,
2127 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2130 if (filter_op == RTE_ETH_FILTER_NOP)
2134 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2139 switch (filter_op) {
2140 case RTE_ETH_FILTER_ADD:
2141 ret = bnxt_cfg_ntuple_filter(bp,
2142 (struct rte_eth_ntuple_filter *)arg,
2145 case RTE_ETH_FILTER_DELETE:
2146 ret = bnxt_cfg_ntuple_filter(bp,
2147 (struct rte_eth_ntuple_filter *)arg,
2151 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2159 bnxt_parse_fdir_filter(struct bnxt *bp,
2160 struct rte_eth_fdir_filter *fdir,
2161 struct bnxt_filter_info *filter)
2163 enum rte_fdir_mode fdir_mode =
2164 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2165 struct bnxt_vnic_info *vnic0, *vnic;
2166 struct bnxt_filter_info *filter1;
2170 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2173 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2174 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2176 switch (fdir->input.flow_type) {
2177 case RTE_ETH_FLOW_IPV4:
2178 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2180 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2181 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2182 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2183 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2184 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2185 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2186 filter->ip_addr_type =
2187 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2188 filter->src_ipaddr_mask[0] = 0xffffffff;
2189 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2190 filter->dst_ipaddr_mask[0] = 0xffffffff;
2191 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2192 filter->ethertype = 0x800;
2193 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2195 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2196 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2197 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2198 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2199 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2200 filter->dst_port_mask = 0xffff;
2201 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2202 filter->src_port_mask = 0xffff;
2203 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2204 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2205 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2206 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2207 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2208 filter->ip_protocol = 6;
2209 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2210 filter->ip_addr_type =
2211 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2212 filter->src_ipaddr_mask[0] = 0xffffffff;
2213 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2214 filter->dst_ipaddr_mask[0] = 0xffffffff;
2215 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2216 filter->ethertype = 0x800;
2217 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2219 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2220 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2221 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2222 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2223 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2224 filter->dst_port_mask = 0xffff;
2225 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2226 filter->src_port_mask = 0xffff;
2227 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2228 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2229 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2230 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2231 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2232 filter->ip_protocol = 17;
2233 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2234 filter->ip_addr_type =
2235 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2236 filter->src_ipaddr_mask[0] = 0xffffffff;
2237 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2238 filter->dst_ipaddr_mask[0] = 0xffffffff;
2239 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2240 filter->ethertype = 0x800;
2241 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2243 case RTE_ETH_FLOW_IPV6:
2244 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2246 filter->ip_addr_type =
2247 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2248 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2249 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2250 rte_memcpy(filter->src_ipaddr,
2251 fdir->input.flow.ipv6_flow.src_ip, 16);
2252 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2253 rte_memcpy(filter->dst_ipaddr,
2254 fdir->input.flow.ipv6_flow.dst_ip, 16);
2255 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2256 memset(filter->dst_ipaddr_mask, 0xff, 16);
2257 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2258 memset(filter->src_ipaddr_mask, 0xff, 16);
2259 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2260 filter->ethertype = 0x86dd;
2261 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2263 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2264 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2265 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2266 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2267 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2268 filter->dst_port_mask = 0xffff;
2269 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2270 filter->src_port_mask = 0xffff;
2271 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2272 filter->ip_addr_type =
2273 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2274 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2275 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2276 rte_memcpy(filter->src_ipaddr,
2277 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2278 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2279 rte_memcpy(filter->dst_ipaddr,
2280 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2281 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2282 memset(filter->dst_ipaddr_mask, 0xff, 16);
2283 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2284 memset(filter->src_ipaddr_mask, 0xff, 16);
2285 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2286 filter->ethertype = 0x86dd;
2287 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2289 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2290 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2291 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2292 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2293 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2294 filter->dst_port_mask = 0xffff;
2295 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2296 filter->src_port_mask = 0xffff;
2297 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2298 filter->ip_addr_type =
2299 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2300 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2301 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2302 rte_memcpy(filter->src_ipaddr,
2303 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2304 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2305 rte_memcpy(filter->dst_ipaddr,
2306 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2307 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2308 memset(filter->dst_ipaddr_mask, 0xff, 16);
2309 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2310 memset(filter->src_ipaddr_mask, 0xff, 16);
2311 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2312 filter->ethertype = 0x86dd;
2313 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2315 case RTE_ETH_FLOW_L2_PAYLOAD:
2316 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2317 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2319 case RTE_ETH_FLOW_VXLAN:
2320 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2322 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2323 filter->tunnel_type =
2324 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2325 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2327 case RTE_ETH_FLOW_NVGRE:
2328 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2330 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2331 filter->tunnel_type =
2332 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2333 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2335 case RTE_ETH_FLOW_UNKNOWN:
2336 case RTE_ETH_FLOW_RAW:
2337 case RTE_ETH_FLOW_FRAG_IPV4:
2338 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2339 case RTE_ETH_FLOW_FRAG_IPV6:
2340 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2341 case RTE_ETH_FLOW_IPV6_EX:
2342 case RTE_ETH_FLOW_IPV6_TCP_EX:
2343 case RTE_ETH_FLOW_IPV6_UDP_EX:
2344 case RTE_ETH_FLOW_GENEVE:
2350 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2351 vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2353 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2358 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2359 rte_memcpy(filter->dst_macaddr,
2360 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2361 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2364 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2365 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2366 filter1 = STAILQ_FIRST(&vnic0->filter);
2367 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2369 filter->dst_id = vnic->fw_vnic_id;
2370 for (i = 0; i < ETHER_ADDR_LEN; i++)
2371 if (filter->dst_macaddr[i] == 0x00)
2372 filter1 = STAILQ_FIRST(&vnic0->filter);
2374 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2377 if (filter1 == NULL)
2380 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2381 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2383 filter->enables = en;
2388 static struct bnxt_filter_info *
2389 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2390 struct bnxt_vnic_info **mvnic)
2392 struct bnxt_filter_info *mf = NULL;
2395 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2396 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2398 STAILQ_FOREACH(mf, &vnic->filter, next) {
2399 if (mf->filter_type == nf->filter_type &&
2400 mf->flags == nf->flags &&
2401 mf->src_port == nf->src_port &&
2402 mf->src_port_mask == nf->src_port_mask &&
2403 mf->dst_port == nf->dst_port &&
2404 mf->dst_port_mask == nf->dst_port_mask &&
2405 mf->ip_protocol == nf->ip_protocol &&
2406 mf->ip_addr_type == nf->ip_addr_type &&
2407 mf->ethertype == nf->ethertype &&
2408 mf->vni == nf->vni &&
2409 mf->tunnel_type == nf->tunnel_type &&
2410 mf->l2_ovlan == nf->l2_ovlan &&
2411 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2412 mf->l2_ivlan == nf->l2_ivlan &&
2413 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2414 !memcmp(mf->l2_addr, nf->l2_addr, ETHER_ADDR_LEN) &&
2415 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2417 !memcmp(mf->src_macaddr, nf->src_macaddr,
2419 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2421 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2422 sizeof(nf->src_ipaddr)) &&
2423 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2424 sizeof(nf->src_ipaddr_mask)) &&
2425 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2426 sizeof(nf->dst_ipaddr)) &&
2427 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2428 sizeof(nf->dst_ipaddr_mask))) {
2439 bnxt_fdir_filter(struct rte_eth_dev *dev,
2440 enum rte_filter_op filter_op,
2443 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2444 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2445 struct bnxt_filter_info *filter, *match;
2446 struct bnxt_vnic_info *vnic, *mvnic;
2449 if (filter_op == RTE_ETH_FILTER_NOP)
2452 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2455 switch (filter_op) {
2456 case RTE_ETH_FILTER_ADD:
2457 case RTE_ETH_FILTER_DELETE:
2459 filter = bnxt_get_unused_filter(bp);
2460 if (filter == NULL) {
2462 "Not enough resources for a new flow.\n");
2466 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2469 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2471 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2472 vnic = STAILQ_FIRST(&bp->ff_pool[0]);
2474 vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2476 match = bnxt_match_fdir(bp, filter, &mvnic);
2477 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2478 if (match->dst_id == vnic->fw_vnic_id) {
2479 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2483 match->dst_id = vnic->fw_vnic_id;
2484 ret = bnxt_hwrm_set_ntuple_filter(bp,
2487 STAILQ_REMOVE(&mvnic->filter, match,
2488 bnxt_filter_info, next);
2489 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2491 "Filter with matching pattern exist\n");
2493 "Updated it to new destination q\n");
2497 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2498 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2503 if (filter_op == RTE_ETH_FILTER_ADD) {
2504 ret = bnxt_hwrm_set_ntuple_filter(bp,
2509 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2511 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2512 STAILQ_REMOVE(&vnic->filter, match,
2513 bnxt_filter_info, next);
2514 bnxt_free_filter(bp, match);
2515 filter->fw_l2_filter_id = -1;
2516 bnxt_free_filter(bp, filter);
2519 case RTE_ETH_FILTER_FLUSH:
2520 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2521 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2523 STAILQ_FOREACH(filter, &vnic->filter, next) {
2524 if (filter->filter_type ==
2525 HWRM_CFA_NTUPLE_FILTER) {
2527 bnxt_hwrm_clear_ntuple_filter(bp,
2529 STAILQ_REMOVE(&vnic->filter, filter,
2530 bnxt_filter_info, next);
2535 case RTE_ETH_FILTER_UPDATE:
2536 case RTE_ETH_FILTER_STATS:
2537 case RTE_ETH_FILTER_INFO:
2538 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2541 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2548 filter->fw_l2_filter_id = -1;
2549 bnxt_free_filter(bp, filter);
2554 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2555 enum rte_filter_type filter_type,
2556 enum rte_filter_op filter_op, void *arg)
2560 switch (filter_type) {
2561 case RTE_ETH_FILTER_TUNNEL:
2563 "filter type: %d: To be implemented\n", filter_type);
2565 case RTE_ETH_FILTER_FDIR:
2566 ret = bnxt_fdir_filter(dev, filter_op, arg);
2568 case RTE_ETH_FILTER_NTUPLE:
2569 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2571 case RTE_ETH_FILTER_ETHERTYPE:
2572 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2574 case RTE_ETH_FILTER_GENERIC:
2575 if (filter_op != RTE_ETH_FILTER_GET)
2577 *(const void **)arg = &bnxt_flow_ops;
2581 "Filter type (%d) not supported", filter_type);
2588 static const uint32_t *
2589 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2591 static const uint32_t ptypes[] = {
2592 RTE_PTYPE_L2_ETHER_VLAN,
2593 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2594 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2598 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2599 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2600 RTE_PTYPE_INNER_L4_ICMP,
2601 RTE_PTYPE_INNER_L4_TCP,
2602 RTE_PTYPE_INNER_L4_UDP,
2606 if (dev->rx_pkt_burst == bnxt_recv_pkts)
2611 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2614 uint32_t reg_base = *reg_arr & 0xfffff000;
2618 for (i = 0; i < count; i++) {
2619 if ((reg_arr[i] & 0xfffff000) != reg_base)
2622 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2623 rte_cpu_to_le_32(rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off));
2627 static int bnxt_map_ptp_regs(struct bnxt *bp)
2629 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2633 reg_arr = ptp->rx_regs;
2634 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2638 reg_arr = ptp->tx_regs;
2639 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2643 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2644 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2646 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2647 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2652 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2654 rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2655 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16));
2656 rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2657 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20));
2660 static uint64_t bnxt_cc_read(struct bnxt *bp)
2664 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2665 BNXT_GRCPF_REG_SYNC_TIME));
2666 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2667 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2671 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2673 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2676 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2677 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2678 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2681 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2682 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2683 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2684 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2685 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2686 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2691 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2693 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2694 struct bnxt_pf_info *pf = &bp->pf;
2701 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2702 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2703 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2706 port_id = pf->port_id;
2707 rte_cpu_to_le_32(rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2708 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]));
2710 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2711 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2712 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2713 /* bnxt_clr_rx_ts(bp); TBD */
2717 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2718 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2719 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2720 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2726 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2729 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2730 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2735 ns = rte_timespec_to_ns(ts);
2736 /* Set the timecounters to a new value. */
2743 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2745 uint64_t ns, systime_cycles;
2746 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2747 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2752 systime_cycles = bnxt_cc_read(bp);
2753 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
2754 *ts = rte_ns_to_timespec(ns);
2759 bnxt_timesync_enable(struct rte_eth_dev *dev)
2761 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2762 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2769 ptp->tx_tstamp_en = 1;
2770 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
2772 if (!bnxt_hwrm_ptp_cfg(bp))
2773 bnxt_map_ptp_regs(bp);
2775 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
2776 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2777 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2779 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2780 ptp->tc.cc_shift = shift;
2781 ptp->tc.nsec_mask = (1ULL << shift) - 1;
2783 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2784 ptp->rx_tstamp_tc.cc_shift = shift;
2785 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2787 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2788 ptp->tx_tstamp_tc.cc_shift = shift;
2789 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2795 bnxt_timesync_disable(struct rte_eth_dev *dev)
2797 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2798 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2804 ptp->tx_tstamp_en = 0;
2807 bnxt_hwrm_ptp_cfg(bp);
2809 bnxt_unmap_ptp_regs(bp);
2815 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
2816 struct timespec *timestamp,
2817 uint32_t flags __rte_unused)
2819 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2820 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2821 uint64_t rx_tstamp_cycles = 0;
2827 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
2828 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
2829 *timestamp = rte_ns_to_timespec(ns);
2834 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
2835 struct timespec *timestamp)
2837 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2838 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2839 uint64_t tx_tstamp_cycles = 0;
2845 bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
2846 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
2847 *timestamp = rte_ns_to_timespec(ns);
2853 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
2855 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2856 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2861 ptp->tc.nsec += delta;
2867 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
2869 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2871 uint32_t dir_entries;
2872 uint32_t entry_length;
2874 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
2875 bp->pdev->addr.domain, bp->pdev->addr.bus,
2876 bp->pdev->addr.devid, bp->pdev->addr.function);
2878 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
2882 return dir_entries * entry_length;
2886 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
2887 struct rte_dev_eeprom_info *in_eeprom)
2889 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2893 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2894 "len = %d\n", bp->pdev->addr.domain,
2895 bp->pdev->addr.bus, bp->pdev->addr.devid,
2896 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2898 if (in_eeprom->offset == 0) /* special offset value to get directory */
2899 return bnxt_get_nvram_directory(bp, in_eeprom->length,
2902 index = in_eeprom->offset >> 24;
2903 offset = in_eeprom->offset & 0xffffff;
2906 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
2907 in_eeprom->length, in_eeprom->data);
2912 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
2915 case BNX_DIR_TYPE_CHIMP_PATCH:
2916 case BNX_DIR_TYPE_BOOTCODE:
2917 case BNX_DIR_TYPE_BOOTCODE_2:
2918 case BNX_DIR_TYPE_APE_FW:
2919 case BNX_DIR_TYPE_APE_PATCH:
2920 case BNX_DIR_TYPE_KONG_FW:
2921 case BNX_DIR_TYPE_KONG_PATCH:
2922 case BNX_DIR_TYPE_BONO_FW:
2923 case BNX_DIR_TYPE_BONO_PATCH:
2931 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
2934 case BNX_DIR_TYPE_AVS:
2935 case BNX_DIR_TYPE_EXP_ROM_MBA:
2936 case BNX_DIR_TYPE_PCIE:
2937 case BNX_DIR_TYPE_TSCF_UCODE:
2938 case BNX_DIR_TYPE_EXT_PHY:
2939 case BNX_DIR_TYPE_CCM:
2940 case BNX_DIR_TYPE_ISCSI_BOOT:
2941 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2942 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2950 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
2952 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2953 bnxt_dir_type_is_other_exec_format(dir_type);
2957 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
2958 struct rte_dev_eeprom_info *in_eeprom)
2960 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2961 uint8_t index, dir_op;
2962 uint16_t type, ext, ordinal, attr;
2964 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2965 "len = %d\n", bp->pdev->addr.domain,
2966 bp->pdev->addr.bus, bp->pdev->addr.devid,
2967 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2970 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
2974 type = in_eeprom->magic >> 16;
2976 if (type == 0xffff) { /* special value for directory operations */
2977 index = in_eeprom->magic & 0xff;
2978 dir_op = in_eeprom->magic >> 8;
2982 case 0x0e: /* erase */
2983 if (in_eeprom->offset != ~in_eeprom->magic)
2985 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
2991 /* Create or re-write an NVM item: */
2992 if (bnxt_dir_type_is_executable(type) == true)
2994 ext = in_eeprom->magic & 0xffff;
2995 ordinal = in_eeprom->offset >> 16;
2996 attr = in_eeprom->offset & 0xffff;
2998 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
2999 in_eeprom->data, in_eeprom->length);
3007 static const struct eth_dev_ops bnxt_dev_ops = {
3008 .dev_infos_get = bnxt_dev_info_get_op,
3009 .dev_close = bnxt_dev_close_op,
3010 .dev_configure = bnxt_dev_configure_op,
3011 .dev_start = bnxt_dev_start_op,
3012 .dev_stop = bnxt_dev_stop_op,
3013 .dev_set_link_up = bnxt_dev_set_link_up_op,
3014 .dev_set_link_down = bnxt_dev_set_link_down_op,
3015 .stats_get = bnxt_stats_get_op,
3016 .stats_reset = bnxt_stats_reset_op,
3017 .rx_queue_setup = bnxt_rx_queue_setup_op,
3018 .rx_queue_release = bnxt_rx_queue_release_op,
3019 .tx_queue_setup = bnxt_tx_queue_setup_op,
3020 .tx_queue_release = bnxt_tx_queue_release_op,
3021 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3022 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3023 .reta_update = bnxt_reta_update_op,
3024 .reta_query = bnxt_reta_query_op,
3025 .rss_hash_update = bnxt_rss_hash_update_op,
3026 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3027 .link_update = bnxt_link_update_op,
3028 .promiscuous_enable = bnxt_promiscuous_enable_op,
3029 .promiscuous_disable = bnxt_promiscuous_disable_op,
3030 .allmulticast_enable = bnxt_allmulticast_enable_op,
3031 .allmulticast_disable = bnxt_allmulticast_disable_op,
3032 .mac_addr_add = bnxt_mac_addr_add_op,
3033 .mac_addr_remove = bnxt_mac_addr_remove_op,
3034 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3035 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3036 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3037 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3038 .vlan_filter_set = bnxt_vlan_filter_set_op,
3039 .vlan_offload_set = bnxt_vlan_offload_set_op,
3040 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3041 .mtu_set = bnxt_mtu_set_op,
3042 .mac_addr_set = bnxt_set_default_mac_addr_op,
3043 .xstats_get = bnxt_dev_xstats_get_op,
3044 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3045 .xstats_reset = bnxt_dev_xstats_reset_op,
3046 .fw_version_get = bnxt_fw_version_get,
3047 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3048 .rxq_info_get = bnxt_rxq_info_get_op,
3049 .txq_info_get = bnxt_txq_info_get_op,
3050 .dev_led_on = bnxt_dev_led_on_op,
3051 .dev_led_off = bnxt_dev_led_off_op,
3052 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3053 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3054 .rx_queue_count = bnxt_rx_queue_count_op,
3055 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3056 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3057 .rx_queue_start = bnxt_rx_queue_start,
3058 .rx_queue_stop = bnxt_rx_queue_stop,
3059 .tx_queue_start = bnxt_tx_queue_start,
3060 .tx_queue_stop = bnxt_tx_queue_stop,
3061 .filter_ctrl = bnxt_filter_ctrl_op,
3062 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3063 .get_eeprom_length = bnxt_get_eeprom_length_op,
3064 .get_eeprom = bnxt_get_eeprom_op,
3065 .set_eeprom = bnxt_set_eeprom_op,
3066 .timesync_enable = bnxt_timesync_enable,
3067 .timesync_disable = bnxt_timesync_disable,
3068 .timesync_read_time = bnxt_timesync_read_time,
3069 .timesync_write_time = bnxt_timesync_write_time,
3070 .timesync_adjust_time = bnxt_timesync_adjust_time,
3071 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3072 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3075 static bool bnxt_vf_pciid(uint16_t id)
3077 if (id == BROADCOM_DEV_ID_57304_VF ||
3078 id == BROADCOM_DEV_ID_57406_VF ||
3079 id == BROADCOM_DEV_ID_5731X_VF ||
3080 id == BROADCOM_DEV_ID_5741X_VF ||
3081 id == BROADCOM_DEV_ID_57414_VF ||
3082 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3083 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
3084 id == BROADCOM_DEV_ID_58802_VF)
3089 bool bnxt_stratus_device(struct bnxt *bp)
3091 uint16_t id = bp->pdev->id.device_id;
3093 if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
3094 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3095 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3100 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3102 struct bnxt *bp = eth_dev->data->dev_private;
3103 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3106 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3107 if (!pci_dev->mem_resource[0].addr) {
3109 "Cannot find PCI device base address, aborting\n");
3111 goto init_err_disable;
3114 bp->eth_dev = eth_dev;
3117 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3119 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3121 goto init_err_release;
3124 if (!pci_dev->mem_resource[2].addr) {
3126 "Cannot find PCI device BAR 2 address, aborting\n");
3128 goto init_err_release;
3130 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3138 if (bp->doorbell_base)
3139 bp->doorbell_base = NULL;
3147 #define ALLOW_FUNC(x) \
3149 typeof(x) arg = (x); \
3150 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3151 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3154 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3156 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3157 char mz_name[RTE_MEMZONE_NAMESIZE];
3158 const struct rte_memzone *mz = NULL;
3159 static int version_printed;
3160 uint32_t total_alloc_len;
3161 rte_iova_t mz_phys_addr;
3165 if (version_printed++ == 0)
3166 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3168 rte_eth_copy_pci_info(eth_dev, pci_dev);
3170 bp = eth_dev->data->dev_private;
3172 bp->dev_stopped = 1;
3174 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3177 if (bnxt_vf_pciid(pci_dev->id.device_id))
3178 bp->flags |= BNXT_FLAG_VF;
3180 rc = bnxt_init_board(eth_dev);
3183 "Board initialization failed rc: %x\n", rc);
3187 eth_dev->dev_ops = &bnxt_dev_ops;
3188 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3189 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3190 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3193 if (pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3194 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3195 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3196 pci_dev->addr.bus, pci_dev->addr.devid,
3197 pci_dev->addr.function, "rx_port_stats");
3198 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3199 mz = rte_memzone_lookup(mz_name);
3200 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3201 sizeof(struct rx_port_stats) + 512);
3203 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3206 RTE_MEMZONE_SIZE_HINT_ONLY |
3207 RTE_MEMZONE_IOVA_CONTIG);
3211 memset(mz->addr, 0, mz->len);
3212 mz_phys_addr = mz->iova;
3213 if ((unsigned long)mz->addr == mz_phys_addr) {
3214 PMD_DRV_LOG(WARNING,
3215 "Memzone physical address same as virtual.\n");
3216 PMD_DRV_LOG(WARNING,
3217 "Using rte_mem_virt2iova()\n");
3218 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3219 if (mz_phys_addr == 0) {
3221 "unable to map address to physical memory\n");
3226 bp->rx_mem_zone = (const void *)mz;
3227 bp->hw_rx_port_stats = mz->addr;
3228 bp->hw_rx_port_stats_map = mz_phys_addr;
3230 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3231 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3232 pci_dev->addr.bus, pci_dev->addr.devid,
3233 pci_dev->addr.function, "tx_port_stats");
3234 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3235 mz = rte_memzone_lookup(mz_name);
3236 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3237 sizeof(struct tx_port_stats) + 512);
3239 mz = rte_memzone_reserve(mz_name,
3243 RTE_MEMZONE_SIZE_HINT_ONLY |
3244 RTE_MEMZONE_IOVA_CONTIG);
3248 memset(mz->addr, 0, mz->len);
3249 mz_phys_addr = mz->iova;
3250 if ((unsigned long)mz->addr == mz_phys_addr) {
3251 PMD_DRV_LOG(WARNING,
3252 "Memzone physical address same as virtual.\n");
3253 PMD_DRV_LOG(WARNING,
3254 "Using rte_mem_virt2iova()\n");
3255 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3256 if (mz_phys_addr == 0) {
3258 "unable to map address to physical memory\n");
3263 bp->tx_mem_zone = (const void *)mz;
3264 bp->hw_tx_port_stats = mz->addr;
3265 bp->hw_tx_port_stats_map = mz_phys_addr;
3267 bp->flags |= BNXT_FLAG_PORT_STATS;
3270 rc = bnxt_alloc_hwrm_resources(bp);
3273 "hwrm resource allocation failure rc: %x\n", rc);
3276 rc = bnxt_hwrm_ver_get(bp);
3279 rc = bnxt_hwrm_queue_qportcfg(bp);
3281 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3285 rc = bnxt_hwrm_func_qcfg(bp);
3287 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3291 /* Get the MAX capabilities for this function */
3292 rc = bnxt_hwrm_func_qcaps(bp);
3294 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3297 if (bp->max_tx_rings == 0) {
3298 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3302 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3303 ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3304 if (eth_dev->data->mac_addrs == NULL) {
3306 "Failed to alloc %u bytes needed to store MAC addr tbl",
3307 ETHER_ADDR_LEN * bp->max_l2_ctx);
3312 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, ETHER_ADDR_LEN)) {
3314 "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
3315 bp->dflt_mac_addr[0], bp->dflt_mac_addr[1],
3316 bp->dflt_mac_addr[2], bp->dflt_mac_addr[3],
3317 bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]);
3321 /* Copy the permanent MAC from the qcap response address now. */
3322 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3323 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
3325 if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3326 /* 1 ring is for default completion ring */
3327 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3332 bp->grp_info = rte_zmalloc("bnxt_grp_info",
3333 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3334 if (!bp->grp_info) {
3336 "Failed to alloc %zu bytes to store group info table\n",
3337 sizeof(*bp->grp_info) * bp->max_ring_grps);
3342 /* Forward all requests if firmware is new enough */
3343 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3344 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3345 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3346 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3348 PMD_DRV_LOG(WARNING,
3349 "Firmware too old for VF mailbox functionality\n");
3350 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3354 * The following are used for driver cleanup. If we disallow these,
3355 * VF drivers can't clean up cleanly.
3357 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3358 ALLOW_FUNC(HWRM_VNIC_FREE);
3359 ALLOW_FUNC(HWRM_RING_FREE);
3360 ALLOW_FUNC(HWRM_RING_GRP_FREE);
3361 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3362 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3363 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3364 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3365 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3366 rc = bnxt_hwrm_func_driver_register(bp);
3369 "Failed to register driver");
3375 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3376 pci_dev->mem_resource[0].phys_addr,
3377 pci_dev->mem_resource[0].addr);
3379 rc = bnxt_hwrm_func_reset(bp);
3381 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3387 //if (bp->pf.active_vfs) {
3388 // TODO: Deallocate VF resources?
3390 if (bp->pdev->max_vfs) {
3391 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3393 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3397 rc = bnxt_hwrm_allocate_pf_only(bp);
3400 "Failed to allocate PF resources\n");
3406 bnxt_hwrm_port_led_qcaps(bp);
3408 rc = bnxt_setup_int(bp);
3412 rc = bnxt_alloc_mem(bp);
3414 goto error_free_int;
3416 rc = bnxt_request_int(bp);
3418 goto error_free_int;
3420 bnxt_enable_int(bp);
3426 bnxt_disable_int(bp);
3427 bnxt_hwrm_func_buf_unrgtr(bp);
3431 bnxt_dev_uninit(eth_dev);
3437 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
3439 struct bnxt *bp = eth_dev->data->dev_private;
3442 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3445 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
3446 bnxt_disable_int(bp);
3449 if (eth_dev->data->mac_addrs != NULL) {
3450 rte_free(eth_dev->data->mac_addrs);
3451 eth_dev->data->mac_addrs = NULL;
3453 if (bp->grp_info != NULL) {
3454 rte_free(bp->grp_info);
3455 bp->grp_info = NULL;
3457 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3458 bnxt_free_hwrm_resources(bp);
3460 if (bp->tx_mem_zone) {
3461 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3462 bp->tx_mem_zone = NULL;
3465 if (bp->rx_mem_zone) {
3466 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3467 bp->rx_mem_zone = NULL;
3470 if (bp->dev_stopped == 0)
3471 bnxt_dev_close_op(eth_dev);
3473 rte_free(bp->pf.vf_info);
3474 eth_dev->dev_ops = NULL;
3475 eth_dev->rx_pkt_burst = NULL;
3476 eth_dev->tx_pkt_burst = NULL;
3481 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3482 struct rte_pci_device *pci_dev)
3484 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
3488 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
3490 return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
3493 static struct rte_pci_driver bnxt_rte_pmd = {
3494 .id_table = bnxt_pci_id_map,
3495 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
3496 RTE_PCI_DRV_INTR_LSC,
3497 .probe = bnxt_pci_probe,
3498 .remove = bnxt_pci_remove,
3502 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
3504 if (strcmp(dev->device->driver->name, drv->driver.name))
3510 bool is_bnxt_supported(struct rte_eth_dev *dev)
3512 return is_device_supported(dev, &bnxt_rte_pmd);
3515 RTE_INIT(bnxt_init_log);
3519 bnxt_logtype_driver = rte_log_register("pmd.bnxt.driver");
3520 if (bnxt_logtype_driver >= 0)
3521 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_INFO);
3524 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
3525 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
3526 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");