1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
30 #define DRV_MODULE_NAME "bnxt"
31 static const char bnxt_version[] =
32 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
33 int bnxt_logtype_driver;
36 * The set of PCI devices this driver supports
38 static const struct rte_pci_id bnxt_pci_id_map[] = {
39 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
40 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
41 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
42 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
43 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
45 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
92 { .vendor_id = 0, /* sentinel */ },
95 #define BNXT_ETH_RSS_SUPPORT ( \
97 ETH_RSS_NONFRAG_IPV4_TCP | \
98 ETH_RSS_NONFRAG_IPV4_UDP | \
100 ETH_RSS_NONFRAG_IPV6_TCP | \
101 ETH_RSS_NONFRAG_IPV6_UDP)
103 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
104 DEV_TX_OFFLOAD_IPV4_CKSUM | \
105 DEV_TX_OFFLOAD_TCP_CKSUM | \
106 DEV_TX_OFFLOAD_UDP_CKSUM | \
107 DEV_TX_OFFLOAD_TCP_TSO | \
108 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
109 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
110 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
111 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
112 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
113 DEV_TX_OFFLOAD_QINQ_INSERT | \
114 DEV_TX_OFFLOAD_MULTI_SEGS)
116 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
117 DEV_RX_OFFLOAD_VLAN_STRIP | \
118 DEV_RX_OFFLOAD_IPV4_CKSUM | \
119 DEV_RX_OFFLOAD_UDP_CKSUM | \
120 DEV_RX_OFFLOAD_TCP_CKSUM | \
121 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
122 DEV_RX_OFFLOAD_JUMBO_FRAME | \
123 DEV_RX_OFFLOAD_KEEP_CRC | \
124 DEV_RX_OFFLOAD_VLAN_EXTEND | \
125 DEV_RX_OFFLOAD_TCP_LRO | \
126 DEV_RX_OFFLOAD_SCATTER | \
127 DEV_RX_OFFLOAD_RSS_HASH)
129 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
130 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
131 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
132 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
133 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
134 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
136 int is_bnxt_in_error(struct bnxt *bp)
138 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
140 if (bp->flags & BNXT_FLAG_FW_RESET)
146 /***********************/
149 * High level utility functions
152 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
154 if (!BNXT_CHIP_THOR(bp))
157 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
158 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
159 BNXT_RSS_ENTRIES_PER_CTX_THOR;
162 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
164 if (!BNXT_CHIP_THOR(bp))
165 return HW_HASH_INDEX_SIZE;
167 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
170 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
172 bnxt_free_filter_mem(bp);
173 bnxt_free_vnic_attributes(bp);
174 bnxt_free_vnic_mem(bp);
176 /* tx/rx rings are configured as part of *_queue_setup callbacks.
177 * If the number of rings change across fw update,
178 * we don't have much choice except to warn the user.
182 bnxt_free_tx_rings(bp);
183 bnxt_free_rx_rings(bp);
185 bnxt_free_async_cp_ring(bp);
186 bnxt_free_rxtx_nq_ring(bp);
188 rte_free(bp->grp_info);
192 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
196 rc = bnxt_alloc_ring_grps(bp);
200 rc = bnxt_alloc_async_ring_struct(bp);
204 rc = bnxt_alloc_vnic_mem(bp);
208 rc = bnxt_alloc_vnic_attributes(bp);
212 rc = bnxt_alloc_filter_mem(bp);
216 rc = bnxt_alloc_async_cp_ring(bp);
220 rc = bnxt_alloc_rxtx_nq_ring(bp);
227 bnxt_free_mem(bp, reconfig);
231 static int bnxt_init_chip(struct bnxt *bp)
233 struct bnxt_rx_queue *rxq;
234 struct rte_eth_link new;
235 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
236 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
237 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
238 uint64_t rx_offloads = dev_conf->rxmode.offloads;
239 uint32_t intr_vector = 0;
240 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
241 uint32_t vec = BNXT_MISC_VEC_ID;
245 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
246 bp->eth_dev->data->dev_conf.rxmode.offloads |=
247 DEV_RX_OFFLOAD_JUMBO_FRAME;
248 bp->flags |= BNXT_FLAG_JUMBO;
250 bp->eth_dev->data->dev_conf.rxmode.offloads &=
251 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
252 bp->flags &= ~BNXT_FLAG_JUMBO;
255 /* THOR does not support ring groups.
256 * But we will use the array to save RSS context IDs.
258 if (BNXT_CHIP_THOR(bp))
259 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
261 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
263 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
267 rc = bnxt_alloc_hwrm_rings(bp);
269 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
273 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
275 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
279 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
282 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
283 if (bp->rx_cos_queue[i].id != 0xff) {
284 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
288 "Num pools more than FW profile\n");
292 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
298 rc = bnxt_mq_rx_configure(bp);
300 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
304 /* VNIC configuration */
305 for (i = 0; i < bp->nr_vnics; i++) {
306 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
307 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
309 rc = bnxt_vnic_grp_alloc(bp, vnic);
313 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
314 i, vnic, vnic->fw_grp_ids);
316 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
318 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
323 /* Alloc RSS context only if RSS mode is enabled */
324 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
325 int j, nr_ctxs = bnxt_rss_ctxts(bp);
328 for (j = 0; j < nr_ctxs; j++) {
329 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
335 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
339 vnic->num_lb_ctxts = nr_ctxs;
343 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
344 * setting is not available at this time, it will not be
345 * configured correctly in the CFA.
347 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
348 vnic->vlan_strip = true;
350 vnic->vlan_strip = false;
352 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
354 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
359 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
362 "HWRM vnic %d filter failure rc: %x\n",
367 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
368 rxq = bp->eth_dev->data->rx_queues[j];
371 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
372 j, rxq->vnic, rxq->vnic->fw_grp_ids);
374 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
375 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
378 rc = bnxt_vnic_rss_configure(bp, vnic);
381 "HWRM vnic set RSS failure rc: %x\n", rc);
385 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
387 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
388 DEV_RX_OFFLOAD_TCP_LRO)
389 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
391 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
393 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
396 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
400 /* check and configure queue intr-vector mapping */
401 if ((rte_intr_cap_multiple(intr_handle) ||
402 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
403 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
404 intr_vector = bp->eth_dev->data->nb_rx_queues;
405 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
406 if (intr_vector > bp->rx_cp_nr_rings) {
407 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
411 rc = rte_intr_efd_enable(intr_handle, intr_vector);
416 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
417 intr_handle->intr_vec =
418 rte_zmalloc("intr_vec",
419 bp->eth_dev->data->nb_rx_queues *
421 if (intr_handle->intr_vec == NULL) {
422 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
423 " intr_vec", bp->eth_dev->data->nb_rx_queues);
427 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
428 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
429 intr_handle->intr_vec, intr_handle->nb_efd,
430 intr_handle->max_intr);
431 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
433 intr_handle->intr_vec[queue_id] =
434 vec + BNXT_RX_VEC_START;
435 if (vec < base + intr_handle->nb_efd - 1)
440 /* enable uio/vfio intr/eventfd mapping */
441 rc = rte_intr_enable(intr_handle);
442 #ifndef RTE_EXEC_ENV_FREEBSD
443 /* In FreeBSD OS, nic_uio driver does not support interrupts */
448 rc = bnxt_get_hwrm_link_config(bp, &new);
450 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
454 if (!bp->link_info.link_up) {
455 rc = bnxt_set_hwrm_link_config(bp, true);
458 "HWRM link config failure rc: %x\n", rc);
462 bnxt_print_link_info(bp->eth_dev);
464 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
466 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
471 rte_free(intr_handle->intr_vec);
473 rte_intr_efd_disable(intr_handle);
475 /* Some of the error status returned by FW may not be from errno.h */
482 static int bnxt_shutdown_nic(struct bnxt *bp)
484 bnxt_free_all_hwrm_resources(bp);
485 bnxt_free_all_filters(bp);
486 bnxt_free_all_vnics(bp);
491 * Device configuration and status function
494 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
495 struct rte_eth_dev_info *dev_info)
497 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
498 struct bnxt *bp = eth_dev->data->dev_private;
499 uint16_t max_vnics, i, j, vpool, vrxq;
500 unsigned int max_rx_rings;
503 rc = is_bnxt_in_error(bp);
508 dev_info->max_mac_addrs = bp->max_l2_ctx;
509 dev_info->max_hash_mac_addrs = 0;
511 /* PF/VF specifics */
513 dev_info->max_vfs = pdev->max_vfs;
515 max_rx_rings = BNXT_MAX_RINGS(bp);
516 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
517 dev_info->max_rx_queues = max_rx_rings;
518 dev_info->max_tx_queues = max_rx_rings;
519 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
520 dev_info->hash_key_size = 40;
521 max_vnics = bp->max_vnics;
524 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
525 dev_info->max_mtu = BNXT_MAX_MTU;
527 /* Fast path specifics */
528 dev_info->min_rx_bufsize = 1;
529 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
531 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
532 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
533 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
534 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
535 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
538 dev_info->default_rxconf = (struct rte_eth_rxconf) {
544 .rx_free_thresh = 32,
545 /* If no descriptors available, pkts are dropped by default */
549 dev_info->default_txconf = (struct rte_eth_txconf) {
555 .tx_free_thresh = 32,
558 eth_dev->data->dev_conf.intr_conf.lsc = 1;
560 eth_dev->data->dev_conf.intr_conf.rxq = 1;
561 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
562 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
563 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
564 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
569 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
570 * need further investigation.
574 vpool = 64; /* ETH_64_POOLS */
575 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
576 for (i = 0; i < 4; vpool >>= 1, i++) {
577 if (max_vnics > vpool) {
578 for (j = 0; j < 5; vrxq >>= 1, j++) {
579 if (dev_info->max_rx_queues > vrxq) {
585 /* Not enough resources to support VMDq */
589 /* Not enough resources to support VMDq */
593 dev_info->max_vmdq_pools = vpool;
594 dev_info->vmdq_queue_num = vrxq;
596 dev_info->vmdq_pool_base = 0;
597 dev_info->vmdq_queue_base = 0;
602 /* Configure the device based on the configuration provided */
603 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
605 struct bnxt *bp = eth_dev->data->dev_private;
606 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
609 bp->rx_queues = (void *)eth_dev->data->rx_queues;
610 bp->tx_queues = (void *)eth_dev->data->tx_queues;
611 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
612 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
614 rc = is_bnxt_in_error(bp);
618 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
619 rc = bnxt_hwrm_check_vf_rings(bp);
621 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
625 /* If a resource has already been allocated - in this case
626 * it is the async completion ring, free it. Reallocate it after
627 * resource reservation. This will ensure the resource counts
628 * are calculated correctly.
631 pthread_mutex_lock(&bp->def_cp_lock);
633 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
634 bnxt_disable_int(bp);
635 bnxt_free_cp_ring(bp, bp->async_cp_ring);
638 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
640 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
641 pthread_mutex_unlock(&bp->def_cp_lock);
645 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
646 rc = bnxt_alloc_async_cp_ring(bp);
648 pthread_mutex_unlock(&bp->def_cp_lock);
654 pthread_mutex_unlock(&bp->def_cp_lock);
656 /* legacy driver needs to get updated values */
657 rc = bnxt_hwrm_func_qcaps(bp);
659 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
664 /* Inherit new configurations */
665 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
666 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
667 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
668 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
669 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
673 if (BNXT_HAS_RING_GRPS(bp) &&
674 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
677 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
678 bp->max_vnics < eth_dev->data->nb_rx_queues)
681 bp->rx_cp_nr_rings = bp->rx_nr_rings;
682 bp->tx_cp_nr_rings = bp->tx_nr_rings;
684 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
685 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
686 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
688 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
690 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
691 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
693 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
699 "Insufficient resources to support requested config\n");
701 "Num Queues Requested: Tx %d, Rx %d\n",
702 eth_dev->data->nb_tx_queues,
703 eth_dev->data->nb_rx_queues);
705 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
706 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
707 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
711 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
713 struct rte_eth_link *link = ð_dev->data->dev_link;
715 if (link->link_status)
716 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
717 eth_dev->data->port_id,
718 (uint32_t)link->link_speed,
719 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
720 ("full-duplex") : ("half-duplex\n"));
722 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
723 eth_dev->data->port_id);
727 * Determine whether the current configuration requires support for scattered
728 * receive; return 1 if scattered receive is required and 0 if not.
730 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
735 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
738 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
739 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
741 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
742 RTE_PKTMBUF_HEADROOM);
743 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
749 static eth_rx_burst_t
750 bnxt_receive_function(struct rte_eth_dev *eth_dev)
752 struct bnxt *bp = eth_dev->data->dev_private;
755 #ifndef RTE_LIBRTE_IEEE1588
757 * Vector mode receive can be enabled only if scatter rx is not
758 * in use and rx offloads are limited to VLAN stripping and
761 if (!eth_dev->data->scattered_rx &&
762 !(eth_dev->data->dev_conf.rxmode.offloads &
763 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
764 DEV_RX_OFFLOAD_KEEP_CRC |
765 DEV_RX_OFFLOAD_JUMBO_FRAME |
766 DEV_RX_OFFLOAD_IPV4_CKSUM |
767 DEV_RX_OFFLOAD_UDP_CKSUM |
768 DEV_RX_OFFLOAD_TCP_CKSUM |
769 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
770 DEV_RX_OFFLOAD_RSS_HASH |
771 DEV_RX_OFFLOAD_VLAN_FILTER))) {
772 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
773 eth_dev->data->port_id);
774 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
775 return bnxt_recv_pkts_vec;
777 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
778 eth_dev->data->port_id);
780 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
781 eth_dev->data->port_id,
782 eth_dev->data->scattered_rx,
783 eth_dev->data->dev_conf.rxmode.offloads);
786 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
787 return bnxt_recv_pkts;
790 static eth_tx_burst_t
791 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
794 #ifndef RTE_LIBRTE_IEEE1588
796 * Vector mode transmit can be enabled only if not using scatter rx
799 if (!eth_dev->data->scattered_rx &&
800 !eth_dev->data->dev_conf.txmode.offloads) {
801 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
802 eth_dev->data->port_id);
803 return bnxt_xmit_pkts_vec;
805 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
806 eth_dev->data->port_id);
808 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
809 eth_dev->data->port_id,
810 eth_dev->data->scattered_rx,
811 eth_dev->data->dev_conf.txmode.offloads);
814 return bnxt_xmit_pkts;
817 static int bnxt_handle_if_change_status(struct bnxt *bp)
821 /* Since fw has undergone a reset and lost all contexts,
822 * set fatal flag to not issue hwrm during cleanup
824 bp->flags |= BNXT_FLAG_FATAL_ERROR;
825 bnxt_uninit_resources(bp, true);
827 /* clear fatal flag so that re-init happens */
828 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
829 rc = bnxt_init_resources(bp, true);
831 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
836 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
838 struct bnxt *bp = eth_dev->data->dev_private;
839 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
843 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
844 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
848 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
850 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
851 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
854 rc = bnxt_hwrm_if_change(bp, 1);
856 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
857 rc = bnxt_handle_if_change_status(bp);
864 rc = bnxt_init_chip(bp);
868 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
870 bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
872 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
873 vlan_mask |= ETH_VLAN_FILTER_MASK;
874 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
875 vlan_mask |= ETH_VLAN_STRIP_MASK;
876 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
880 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
881 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
883 bp->flags |= BNXT_FLAG_INIT_DONE;
884 eth_dev->data->dev_started = 1;
886 pthread_mutex_lock(&bp->def_cp_lock);
887 bnxt_schedule_fw_health_check(bp);
888 pthread_mutex_unlock(&bp->def_cp_lock);
892 bnxt_hwrm_if_change(bp, 0);
893 bnxt_shutdown_nic(bp);
894 bnxt_free_tx_mbufs(bp);
895 bnxt_free_rx_mbufs(bp);
899 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
901 struct bnxt *bp = eth_dev->data->dev_private;
904 if (!bp->link_info.link_up)
905 rc = bnxt_set_hwrm_link_config(bp, true);
907 eth_dev->data->dev_link.link_status = 1;
909 bnxt_print_link_info(eth_dev);
913 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
915 struct bnxt *bp = eth_dev->data->dev_private;
917 eth_dev->data->dev_link.link_status = 0;
918 bnxt_set_hwrm_link_config(bp, false);
919 bp->link_info.link_up = 0;
924 /* Unload the driver, release resources */
925 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
927 struct bnxt *bp = eth_dev->data->dev_private;
928 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
929 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
931 eth_dev->data->dev_started = 0;
932 /* Prevent crashes when queues are still in use */
933 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
934 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
936 bnxt_disable_int(bp);
938 /* disable uio/vfio intr/eventfd mapping */
939 rte_intr_disable(intr_handle);
941 bnxt_cancel_fw_health_check(bp);
943 bp->flags &= ~BNXT_FLAG_INIT_DONE;
944 if (bp->eth_dev->data->dev_started) {
945 /* TBD: STOP HW queues DMA */
946 eth_dev->data->dev_link.link_status = 0;
948 bnxt_dev_set_link_down_op(eth_dev);
950 /* Wait for link to be reset and the async notification to process.
951 * During reset recovery, there is no need to wait
953 if (!is_bnxt_in_error(bp))
954 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
956 /* Clean queue intr-vector mapping */
957 rte_intr_efd_disable(intr_handle);
958 if (intr_handle->intr_vec != NULL) {
959 rte_free(intr_handle->intr_vec);
960 intr_handle->intr_vec = NULL;
963 bnxt_hwrm_port_clr_stats(bp);
964 bnxt_free_tx_mbufs(bp);
965 bnxt_free_rx_mbufs(bp);
966 /* Process any remaining notifications in default completion queue */
967 bnxt_int_handler(eth_dev);
968 bnxt_shutdown_nic(bp);
969 bnxt_hwrm_if_change(bp, 0);
970 memset(bp->mark_table, 0, BNXT_MARK_TABLE_SZ);
971 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
976 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
978 struct bnxt *bp = eth_dev->data->dev_private;
980 if (bp->dev_stopped == 0)
981 bnxt_dev_stop_op(eth_dev);
983 if (eth_dev->data->mac_addrs != NULL) {
984 rte_free(eth_dev->data->mac_addrs);
985 eth_dev->data->mac_addrs = NULL;
987 if (bp->grp_info != NULL) {
988 rte_free(bp->grp_info);
992 rte_free(bp->mark_table);
993 bp->mark_table = NULL;
995 bnxt_dev_uninit(eth_dev);
998 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1001 struct bnxt *bp = eth_dev->data->dev_private;
1002 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1003 struct bnxt_vnic_info *vnic;
1004 struct bnxt_filter_info *filter, *temp_filter;
1007 if (is_bnxt_in_error(bp))
1011 * Loop through all VNICs from the specified filter flow pools to
1012 * remove the corresponding MAC addr filter
1014 for (i = 0; i < bp->nr_vnics; i++) {
1015 if (!(pool_mask & (1ULL << i)))
1018 vnic = &bp->vnic_info[i];
1019 filter = STAILQ_FIRST(&vnic->filter);
1021 temp_filter = STAILQ_NEXT(filter, next);
1022 if (filter->mac_index == index) {
1023 STAILQ_REMOVE(&vnic->filter, filter,
1024 bnxt_filter_info, next);
1025 bnxt_hwrm_clear_l2_filter(bp, filter);
1026 bnxt_free_filter(bp, filter);
1028 filter = temp_filter;
1033 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1034 struct rte_ether_addr *mac_addr, uint32_t index,
1037 struct bnxt_filter_info *filter;
1040 /* Attach requested MAC address to the new l2_filter */
1041 STAILQ_FOREACH(filter, &vnic->filter, next) {
1042 if (filter->mac_index == index) {
1044 "MAC addr already existed for pool %d\n",
1050 filter = bnxt_alloc_filter(bp);
1052 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1056 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1057 * if the MAC that's been programmed now is a different one, then,
1058 * copy that addr to filter->l2_addr
1061 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1062 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1064 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1066 filter->mac_index = index;
1067 if (filter->mac_index == 0)
1068 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1070 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1072 bnxt_free_filter(bp, filter);
1078 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1079 struct rte_ether_addr *mac_addr,
1080 uint32_t index, uint32_t pool)
1082 struct bnxt *bp = eth_dev->data->dev_private;
1083 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1086 rc = is_bnxt_in_error(bp);
1090 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1091 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1096 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1100 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1105 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1106 bool exp_link_status)
1109 struct bnxt *bp = eth_dev->data->dev_private;
1110 struct rte_eth_link new;
1111 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1112 BNXT_LINK_DOWN_WAIT_CNT;
1114 rc = is_bnxt_in_error(bp);
1118 memset(&new, 0, sizeof(new));
1120 /* Retrieve link info from hardware */
1121 rc = bnxt_get_hwrm_link_config(bp, &new);
1123 new.link_speed = ETH_LINK_SPEED_100M;
1124 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1126 "Failed to retrieve link rc = 0x%x!\n", rc);
1130 if (!wait_to_complete || new.link_status == exp_link_status)
1133 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1137 /* Timed out or success */
1138 if (new.link_status != eth_dev->data->dev_link.link_status ||
1139 new.link_speed != eth_dev->data->dev_link.link_speed) {
1140 rte_eth_linkstatus_set(eth_dev, &new);
1142 _rte_eth_dev_callback_process(eth_dev,
1143 RTE_ETH_EVENT_INTR_LSC,
1146 bnxt_print_link_info(eth_dev);
1152 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1153 int wait_to_complete)
1155 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1158 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1160 struct bnxt *bp = eth_dev->data->dev_private;
1161 struct bnxt_vnic_info *vnic;
1165 rc = is_bnxt_in_error(bp);
1169 if (bp->vnic_info == NULL)
1172 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1174 old_flags = vnic->flags;
1175 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1176 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1178 vnic->flags = old_flags;
1183 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1185 struct bnxt *bp = eth_dev->data->dev_private;
1186 struct bnxt_vnic_info *vnic;
1190 rc = is_bnxt_in_error(bp);
1194 if (bp->vnic_info == NULL)
1197 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1199 old_flags = vnic->flags;
1200 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1201 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1203 vnic->flags = old_flags;
1208 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1210 struct bnxt *bp = eth_dev->data->dev_private;
1211 struct bnxt_vnic_info *vnic;
1215 rc = is_bnxt_in_error(bp);
1219 if (bp->vnic_info == NULL)
1222 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1224 old_flags = vnic->flags;
1225 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1226 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1228 vnic->flags = old_flags;
1233 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1235 struct bnxt *bp = eth_dev->data->dev_private;
1236 struct bnxt_vnic_info *vnic;
1240 rc = is_bnxt_in_error(bp);
1244 if (bp->vnic_info == NULL)
1247 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1249 old_flags = vnic->flags;
1250 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1251 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1253 vnic->flags = old_flags;
1258 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1259 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1261 if (qid >= bp->rx_nr_rings)
1264 return bp->eth_dev->data->rx_queues[qid];
1267 /* Return rxq corresponding to a given rss table ring/group ID. */
1268 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1270 struct bnxt_rx_queue *rxq;
1273 if (!BNXT_HAS_RING_GRPS(bp)) {
1274 for (i = 0; i < bp->rx_nr_rings; i++) {
1275 rxq = bp->eth_dev->data->rx_queues[i];
1276 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1280 for (i = 0; i < bp->rx_nr_rings; i++) {
1281 if (bp->grp_info[i].fw_grp_id == fwr)
1286 return INVALID_HW_RING_ID;
1289 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1290 struct rte_eth_rss_reta_entry64 *reta_conf,
1293 struct bnxt *bp = eth_dev->data->dev_private;
1294 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1295 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1296 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1300 rc = is_bnxt_in_error(bp);
1304 if (!vnic->rss_table)
1307 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1310 if (reta_size != tbl_size) {
1311 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1312 "(%d) must equal the size supported by the hardware "
1313 "(%d)\n", reta_size, tbl_size);
1317 for (i = 0; i < reta_size; i++) {
1318 struct bnxt_rx_queue *rxq;
1320 idx = i / RTE_RETA_GROUP_SIZE;
1321 sft = i % RTE_RETA_GROUP_SIZE;
1323 if (!(reta_conf[idx].mask & (1ULL << sft)))
1326 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1328 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1332 if (BNXT_CHIP_THOR(bp)) {
1333 vnic->rss_table[i * 2] =
1334 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1335 vnic->rss_table[i * 2 + 1] =
1336 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1338 vnic->rss_table[i] =
1339 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1343 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1347 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1348 struct rte_eth_rss_reta_entry64 *reta_conf,
1351 struct bnxt *bp = eth_dev->data->dev_private;
1352 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1353 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1354 uint16_t idx, sft, i;
1357 rc = is_bnxt_in_error(bp);
1361 /* Retrieve from the default VNIC */
1364 if (!vnic->rss_table)
1367 if (reta_size != tbl_size) {
1368 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1369 "(%d) must equal the size supported by the hardware "
1370 "(%d)\n", reta_size, tbl_size);
1374 for (idx = 0, i = 0; i < reta_size; i++) {
1375 idx = i / RTE_RETA_GROUP_SIZE;
1376 sft = i % RTE_RETA_GROUP_SIZE;
1378 if (reta_conf[idx].mask & (1ULL << sft)) {
1381 if (BNXT_CHIP_THOR(bp))
1382 qid = bnxt_rss_to_qid(bp,
1383 vnic->rss_table[i * 2]);
1385 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1387 if (qid == INVALID_HW_RING_ID) {
1388 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1391 reta_conf[idx].reta[sft] = qid;
1398 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1399 struct rte_eth_rss_conf *rss_conf)
1401 struct bnxt *bp = eth_dev->data->dev_private;
1402 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1403 struct bnxt_vnic_info *vnic;
1406 rc = is_bnxt_in_error(bp);
1411 * If RSS enablement were different than dev_configure,
1412 * then return -EINVAL
1414 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1415 if (!rss_conf->rss_hf)
1416 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1418 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1422 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1423 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1425 /* Update the default RSS VNIC(s) */
1426 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1427 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1430 * If hashkey is not specified, use the previously configured
1433 if (!rss_conf->rss_key)
1436 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1438 "Invalid hashkey length, should be 16 bytes\n");
1441 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1444 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1448 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1449 struct rte_eth_rss_conf *rss_conf)
1451 struct bnxt *bp = eth_dev->data->dev_private;
1452 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1454 uint32_t hash_types;
1456 rc = is_bnxt_in_error(bp);
1460 /* RSS configuration is the same for all VNICs */
1461 if (vnic && vnic->rss_hash_key) {
1462 if (rss_conf->rss_key) {
1463 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1464 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1465 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1468 hash_types = vnic->hash_type;
1469 rss_conf->rss_hf = 0;
1470 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1471 rss_conf->rss_hf |= ETH_RSS_IPV4;
1472 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1474 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1475 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1477 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1479 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1480 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1482 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1484 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1485 rss_conf->rss_hf |= ETH_RSS_IPV6;
1486 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1488 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1489 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1491 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1493 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1494 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1496 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1500 "Unknwon RSS config from firmware (%08x), RSS disabled",
1505 rss_conf->rss_hf = 0;
1510 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1511 struct rte_eth_fc_conf *fc_conf)
1513 struct bnxt *bp = dev->data->dev_private;
1514 struct rte_eth_link link_info;
1517 rc = is_bnxt_in_error(bp);
1521 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1525 memset(fc_conf, 0, sizeof(*fc_conf));
1526 if (bp->link_info.auto_pause)
1527 fc_conf->autoneg = 1;
1528 switch (bp->link_info.pause) {
1530 fc_conf->mode = RTE_FC_NONE;
1532 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1533 fc_conf->mode = RTE_FC_TX_PAUSE;
1535 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1536 fc_conf->mode = RTE_FC_RX_PAUSE;
1538 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1539 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1540 fc_conf->mode = RTE_FC_FULL;
1546 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1547 struct rte_eth_fc_conf *fc_conf)
1549 struct bnxt *bp = dev->data->dev_private;
1552 rc = is_bnxt_in_error(bp);
1556 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1557 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1561 switch (fc_conf->mode) {
1563 bp->link_info.auto_pause = 0;
1564 bp->link_info.force_pause = 0;
1566 case RTE_FC_RX_PAUSE:
1567 if (fc_conf->autoneg) {
1568 bp->link_info.auto_pause =
1569 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1570 bp->link_info.force_pause = 0;
1572 bp->link_info.auto_pause = 0;
1573 bp->link_info.force_pause =
1574 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1577 case RTE_FC_TX_PAUSE:
1578 if (fc_conf->autoneg) {
1579 bp->link_info.auto_pause =
1580 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1581 bp->link_info.force_pause = 0;
1583 bp->link_info.auto_pause = 0;
1584 bp->link_info.force_pause =
1585 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1589 if (fc_conf->autoneg) {
1590 bp->link_info.auto_pause =
1591 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1592 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1593 bp->link_info.force_pause = 0;
1595 bp->link_info.auto_pause = 0;
1596 bp->link_info.force_pause =
1597 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1598 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1602 return bnxt_set_hwrm_link_config(bp, true);
1605 /* Add UDP tunneling port */
1607 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1608 struct rte_eth_udp_tunnel *udp_tunnel)
1610 struct bnxt *bp = eth_dev->data->dev_private;
1611 uint16_t tunnel_type = 0;
1614 rc = is_bnxt_in_error(bp);
1618 switch (udp_tunnel->prot_type) {
1619 case RTE_TUNNEL_TYPE_VXLAN:
1620 if (bp->vxlan_port_cnt) {
1621 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1622 udp_tunnel->udp_port);
1623 if (bp->vxlan_port != udp_tunnel->udp_port) {
1624 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1627 bp->vxlan_port_cnt++;
1631 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1632 bp->vxlan_port_cnt++;
1634 case RTE_TUNNEL_TYPE_GENEVE:
1635 if (bp->geneve_port_cnt) {
1636 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1637 udp_tunnel->udp_port);
1638 if (bp->geneve_port != udp_tunnel->udp_port) {
1639 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1642 bp->geneve_port_cnt++;
1646 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1647 bp->geneve_port_cnt++;
1650 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1653 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1659 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1660 struct rte_eth_udp_tunnel *udp_tunnel)
1662 struct bnxt *bp = eth_dev->data->dev_private;
1663 uint16_t tunnel_type = 0;
1667 rc = is_bnxt_in_error(bp);
1671 switch (udp_tunnel->prot_type) {
1672 case RTE_TUNNEL_TYPE_VXLAN:
1673 if (!bp->vxlan_port_cnt) {
1674 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1677 if (bp->vxlan_port != udp_tunnel->udp_port) {
1678 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1679 udp_tunnel->udp_port, bp->vxlan_port);
1682 if (--bp->vxlan_port_cnt)
1686 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1687 port = bp->vxlan_fw_dst_port_id;
1689 case RTE_TUNNEL_TYPE_GENEVE:
1690 if (!bp->geneve_port_cnt) {
1691 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1694 if (bp->geneve_port != udp_tunnel->udp_port) {
1695 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1696 udp_tunnel->udp_port, bp->geneve_port);
1699 if (--bp->geneve_port_cnt)
1703 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1704 port = bp->geneve_fw_dst_port_id;
1707 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1711 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1714 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1717 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1718 bp->geneve_port = 0;
1723 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1725 struct bnxt_filter_info *filter;
1726 struct bnxt_vnic_info *vnic;
1728 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1730 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1731 filter = STAILQ_FIRST(&vnic->filter);
1733 /* Search for this matching MAC+VLAN filter */
1734 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1735 /* Delete the filter */
1736 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1739 STAILQ_REMOVE(&vnic->filter, filter,
1740 bnxt_filter_info, next);
1741 bnxt_free_filter(bp, filter);
1743 "Deleted vlan filter for %d\n",
1747 filter = STAILQ_NEXT(filter, next);
1752 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1754 struct bnxt_filter_info *filter;
1755 struct bnxt_vnic_info *vnic;
1757 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1758 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1759 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1761 /* Implementation notes on the use of VNIC in this command:
1763 * By default, these filters belong to default vnic for the function.
1764 * Once these filters are set up, only destination VNIC can be modified.
1765 * If the destination VNIC is not specified in this command,
1766 * then the HWRM shall only create an l2 context id.
1769 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1770 filter = STAILQ_FIRST(&vnic->filter);
1771 /* Check if the VLAN has already been added */
1773 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
1776 filter = STAILQ_NEXT(filter, next);
1779 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1780 * command to create MAC+VLAN filter with the right flags, enables set.
1782 filter = bnxt_alloc_filter(bp);
1785 "MAC/VLAN filter alloc failed\n");
1788 /* MAC + VLAN ID filter */
1789 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1790 * untagged packets are received
1792 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1793 * packets and only the programmed vlan's packets are received
1795 filter->l2_ivlan = vlan_id;
1796 filter->l2_ivlan_mask = 0x0FFF;
1797 filter->enables |= en;
1798 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1800 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1802 /* Free the newly allocated filter as we were
1803 * not able to create the filter in hardware.
1805 bnxt_free_filter(bp, filter);
1809 filter->mac_index = 0;
1810 /* Add this new filter to the list */
1812 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1814 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1817 "Added Vlan filter for %d\n", vlan_id);
1821 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1822 uint16_t vlan_id, int on)
1824 struct bnxt *bp = eth_dev->data->dev_private;
1827 rc = is_bnxt_in_error(bp);
1831 /* These operations apply to ALL existing MAC/VLAN filters */
1833 return bnxt_add_vlan_filter(bp, vlan_id);
1835 return bnxt_del_vlan_filter(bp, vlan_id);
1838 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1839 struct bnxt_vnic_info *vnic)
1841 struct bnxt_filter_info *filter;
1844 filter = STAILQ_FIRST(&vnic->filter);
1846 if (filter->mac_index == 0 &&
1847 !memcmp(filter->l2_addr, bp->mac_addr,
1848 RTE_ETHER_ADDR_LEN)) {
1849 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1851 STAILQ_REMOVE(&vnic->filter, filter,
1852 bnxt_filter_info, next);
1853 bnxt_free_filter(bp, filter);
1857 filter = STAILQ_NEXT(filter, next);
1863 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
1865 struct bnxt_vnic_info *vnic;
1869 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1870 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1871 /* Remove any VLAN filters programmed */
1872 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1873 bnxt_del_vlan_filter(bp, i);
1875 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1879 /* Default filter will allow packets that match the
1880 * dest mac. So, it has to be deleted, otherwise, we
1881 * will endup receiving vlan packets for which the
1882 * filter is not programmed, when hw-vlan-filter
1883 * configuration is ON
1885 bnxt_del_dflt_mac_filter(bp, vnic);
1886 /* This filter will allow only untagged packets */
1887 bnxt_add_vlan_filter(bp, 0);
1889 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1890 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1896 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1898 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1899 struct bnxt *bp = dev->data->dev_private;
1903 rc = is_bnxt_in_error(bp);
1907 if (mask & ETH_VLAN_FILTER_MASK) {
1908 /* Enable or disable VLAN filtering */
1909 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
1914 if (mask & ETH_VLAN_STRIP_MASK) {
1915 /* Enable or disable VLAN stripping */
1916 for (i = 0; i < bp->nr_vnics; i++) {
1917 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1918 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1919 vnic->vlan_strip = true;
1921 vnic->vlan_strip = false;
1922 bnxt_hwrm_vnic_cfg(bp, vnic);
1924 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1925 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1928 if (mask & ETH_VLAN_EXTEND_MASK) {
1929 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1930 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1932 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1939 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1942 struct bnxt *bp = dev->data->dev_private;
1943 int qinq = dev->data->dev_conf.rxmode.offloads &
1944 DEV_RX_OFFLOAD_VLAN_EXTEND;
1946 if (vlan_type != ETH_VLAN_TYPE_INNER &&
1947 vlan_type != ETH_VLAN_TYPE_OUTER) {
1949 "Unsupported vlan type.");
1954 "QinQ not enabled. Needs to be ON as we can "
1955 "accelerate only outer vlan\n");
1959 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1961 case RTE_ETHER_TYPE_QINQ:
1963 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1965 case RTE_ETHER_TYPE_VLAN:
1967 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1971 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1975 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
1979 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
1982 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
1985 bp->outer_tpid_bd |= tpid;
1986 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
1987 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
1989 "Can accelerate only outer vlan in QinQ\n");
1997 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
1998 struct rte_ether_addr *addr)
2000 struct bnxt *bp = dev->data->dev_private;
2001 /* Default Filter is tied to VNIC 0 */
2002 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2005 rc = is_bnxt_in_error(bp);
2009 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2012 if (rte_is_zero_ether_addr(addr))
2015 /* Check if the requested MAC is already added */
2016 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2019 /* Destroy filter and re-create it */
2020 bnxt_del_dflt_mac_filter(bp, vnic);
2022 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2023 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2024 /* This filter will allow only untagged packets */
2025 rc = bnxt_add_vlan_filter(bp, 0);
2027 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2030 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2035 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2036 struct rte_ether_addr *mc_addr_set,
2037 uint32_t nb_mc_addr)
2039 struct bnxt *bp = eth_dev->data->dev_private;
2040 char *mc_addr_list = (char *)mc_addr_set;
2041 struct bnxt_vnic_info *vnic;
2042 uint32_t off = 0, i = 0;
2045 rc = is_bnxt_in_error(bp);
2049 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2051 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2052 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2056 /* TODO Check for Duplicate mcast addresses */
2057 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2058 for (i = 0; i < nb_mc_addr; i++) {
2059 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2060 RTE_ETHER_ADDR_LEN);
2061 off += RTE_ETHER_ADDR_LEN;
2064 vnic->mc_addr_cnt = i;
2065 if (vnic->mc_addr_cnt)
2066 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2068 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2071 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2075 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2077 struct bnxt *bp = dev->data->dev_private;
2078 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2079 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2080 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2083 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2084 fw_major, fw_minor, fw_updt);
2086 ret += 1; /* add the size of '\0' */
2087 if (fw_size < (uint32_t)ret)
2094 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2095 struct rte_eth_rxq_info *qinfo)
2097 struct bnxt *bp = dev->data->dev_private;
2098 struct bnxt_rx_queue *rxq;
2100 if (is_bnxt_in_error(bp))
2103 rxq = dev->data->rx_queues[queue_id];
2105 qinfo->mp = rxq->mb_pool;
2106 qinfo->scattered_rx = dev->data->scattered_rx;
2107 qinfo->nb_desc = rxq->nb_rx_desc;
2109 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2110 qinfo->conf.rx_drop_en = 0;
2111 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2115 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2116 struct rte_eth_txq_info *qinfo)
2118 struct bnxt *bp = dev->data->dev_private;
2119 struct bnxt_tx_queue *txq;
2121 if (is_bnxt_in_error(bp))
2124 txq = dev->data->tx_queues[queue_id];
2126 qinfo->nb_desc = txq->nb_tx_desc;
2128 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2129 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2130 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2132 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2133 qinfo->conf.tx_rs_thresh = 0;
2134 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2137 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2139 struct bnxt *bp = eth_dev->data->dev_private;
2140 uint32_t new_pkt_size;
2144 rc = is_bnxt_in_error(bp);
2148 /* Exit if receive queues are not configured yet */
2149 if (!eth_dev->data->nb_rx_queues)
2152 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2153 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2157 * If vector-mode tx/rx is active, disallow any MTU change that would
2158 * require scattered receive support.
2160 if (eth_dev->data->dev_started &&
2161 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2162 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2164 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2166 "MTU change would require scattered rx support. ");
2167 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2172 if (new_mtu > RTE_ETHER_MTU) {
2173 bp->flags |= BNXT_FLAG_JUMBO;
2174 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2175 DEV_RX_OFFLOAD_JUMBO_FRAME;
2177 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2178 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2179 bp->flags &= ~BNXT_FLAG_JUMBO;
2182 /* Is there a change in mtu setting? */
2183 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2186 for (i = 0; i < bp->nr_vnics; i++) {
2187 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2190 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2191 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2195 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2196 size -= RTE_PKTMBUF_HEADROOM;
2198 if (size < new_mtu) {
2199 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2206 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2208 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2214 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2216 struct bnxt *bp = dev->data->dev_private;
2217 uint16_t vlan = bp->vlan;
2220 rc = is_bnxt_in_error(bp);
2224 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2226 "PVID cannot be modified for this function\n");
2229 bp->vlan = on ? pvid : 0;
2231 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2238 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2240 struct bnxt *bp = dev->data->dev_private;
2243 rc = is_bnxt_in_error(bp);
2247 return bnxt_hwrm_port_led_cfg(bp, true);
2251 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2253 struct bnxt *bp = dev->data->dev_private;
2256 rc = is_bnxt_in_error(bp);
2260 return bnxt_hwrm_port_led_cfg(bp, false);
2264 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2266 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2267 uint32_t desc = 0, raw_cons = 0, cons;
2268 struct bnxt_cp_ring_info *cpr;
2269 struct bnxt_rx_queue *rxq;
2270 struct rx_pkt_cmpl *rxcmp;
2273 rc = is_bnxt_in_error(bp);
2277 rxq = dev->data->rx_queues[rx_queue_id];
2279 raw_cons = cpr->cp_raw_cons;
2282 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2283 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2284 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2286 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2298 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2300 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2301 struct bnxt_rx_ring_info *rxr;
2302 struct bnxt_cp_ring_info *cpr;
2303 struct bnxt_sw_rx_bd *rx_buf;
2304 struct rx_pkt_cmpl *rxcmp;
2305 uint32_t cons, cp_cons;
2311 rc = is_bnxt_in_error(rxq->bp);
2318 if (offset >= rxq->nb_rx_desc)
2321 cons = RING_CMP(cpr->cp_ring_struct, offset);
2322 cp_cons = cpr->cp_raw_cons;
2323 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2325 if (cons > cp_cons) {
2326 if (CMPL_VALID(rxcmp, cpr->valid))
2327 return RTE_ETH_RX_DESC_DONE;
2329 if (CMPL_VALID(rxcmp, !cpr->valid))
2330 return RTE_ETH_RX_DESC_DONE;
2332 rx_buf = &rxr->rx_buf_ring[cons];
2333 if (rx_buf->mbuf == NULL)
2334 return RTE_ETH_RX_DESC_UNAVAIL;
2337 return RTE_ETH_RX_DESC_AVAIL;
2341 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2343 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2344 struct bnxt_tx_ring_info *txr;
2345 struct bnxt_cp_ring_info *cpr;
2346 struct bnxt_sw_tx_bd *tx_buf;
2347 struct tx_pkt_cmpl *txcmp;
2348 uint32_t cons, cp_cons;
2354 rc = is_bnxt_in_error(txq->bp);
2361 if (offset >= txq->nb_tx_desc)
2364 cons = RING_CMP(cpr->cp_ring_struct, offset);
2365 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2366 cp_cons = cpr->cp_raw_cons;
2368 if (cons > cp_cons) {
2369 if (CMPL_VALID(txcmp, cpr->valid))
2370 return RTE_ETH_TX_DESC_UNAVAIL;
2372 if (CMPL_VALID(txcmp, !cpr->valid))
2373 return RTE_ETH_TX_DESC_UNAVAIL;
2375 tx_buf = &txr->tx_buf_ring[cons];
2376 if (tx_buf->mbuf == NULL)
2377 return RTE_ETH_TX_DESC_DONE;
2379 return RTE_ETH_TX_DESC_FULL;
2382 static struct bnxt_filter_info *
2383 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2384 struct rte_eth_ethertype_filter *efilter,
2385 struct bnxt_vnic_info *vnic0,
2386 struct bnxt_vnic_info *vnic,
2389 struct bnxt_filter_info *mfilter = NULL;
2393 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2394 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2395 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2396 " ethertype filter.", efilter->ether_type);
2400 if (efilter->queue >= bp->rx_nr_rings) {
2401 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2406 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2407 vnic = &bp->vnic_info[efilter->queue];
2409 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2414 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2415 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2416 if ((!memcmp(efilter->mac_addr.addr_bytes,
2417 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2419 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2420 mfilter->ethertype == efilter->ether_type)) {
2426 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2427 if ((!memcmp(efilter->mac_addr.addr_bytes,
2428 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2429 mfilter->ethertype == efilter->ether_type &&
2431 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2445 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2446 enum rte_filter_op filter_op,
2449 struct bnxt *bp = dev->data->dev_private;
2450 struct rte_eth_ethertype_filter *efilter =
2451 (struct rte_eth_ethertype_filter *)arg;
2452 struct bnxt_filter_info *bfilter, *filter1;
2453 struct bnxt_vnic_info *vnic, *vnic0;
2456 if (filter_op == RTE_ETH_FILTER_NOP)
2460 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2465 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2466 vnic = &bp->vnic_info[efilter->queue];
2468 switch (filter_op) {
2469 case RTE_ETH_FILTER_ADD:
2470 bnxt_match_and_validate_ether_filter(bp, efilter,
2475 bfilter = bnxt_get_unused_filter(bp);
2476 if (bfilter == NULL) {
2478 "Not enough resources for a new filter.\n");
2481 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2482 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2483 RTE_ETHER_ADDR_LEN);
2484 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2485 RTE_ETHER_ADDR_LEN);
2486 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2487 bfilter->ethertype = efilter->ether_type;
2488 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2490 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2491 if (filter1 == NULL) {
2496 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2497 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2499 bfilter->dst_id = vnic->fw_vnic_id;
2501 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2503 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2506 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2509 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2511 case RTE_ETH_FILTER_DELETE:
2512 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2514 if (ret == -EEXIST) {
2515 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2517 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2519 bnxt_free_filter(bp, filter1);
2520 } else if (ret == 0) {
2521 PMD_DRV_LOG(ERR, "No matching filter found\n");
2525 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2531 bnxt_free_filter(bp, bfilter);
2537 parse_ntuple_filter(struct bnxt *bp,
2538 struct rte_eth_ntuple_filter *nfilter,
2539 struct bnxt_filter_info *bfilter)
2543 if (nfilter->queue >= bp->rx_nr_rings) {
2544 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2548 switch (nfilter->dst_port_mask) {
2550 bfilter->dst_port_mask = -1;
2551 bfilter->dst_port = nfilter->dst_port;
2552 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2553 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2556 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2560 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2561 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2563 switch (nfilter->proto_mask) {
2565 if (nfilter->proto == 17) /* IPPROTO_UDP */
2566 bfilter->ip_protocol = 17;
2567 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2568 bfilter->ip_protocol = 6;
2571 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2574 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2578 switch (nfilter->dst_ip_mask) {
2580 bfilter->dst_ipaddr_mask[0] = -1;
2581 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2582 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2583 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2586 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2590 switch (nfilter->src_ip_mask) {
2592 bfilter->src_ipaddr_mask[0] = -1;
2593 bfilter->src_ipaddr[0] = nfilter->src_ip;
2594 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2595 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2598 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2602 switch (nfilter->src_port_mask) {
2604 bfilter->src_port_mask = -1;
2605 bfilter->src_port = nfilter->src_port;
2606 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2607 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2610 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2614 bfilter->enables = en;
2618 static struct bnxt_filter_info*
2619 bnxt_match_ntuple_filter(struct bnxt *bp,
2620 struct bnxt_filter_info *bfilter,
2621 struct bnxt_vnic_info **mvnic)
2623 struct bnxt_filter_info *mfilter = NULL;
2626 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2627 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2628 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2629 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2630 bfilter->src_ipaddr_mask[0] ==
2631 mfilter->src_ipaddr_mask[0] &&
2632 bfilter->src_port == mfilter->src_port &&
2633 bfilter->src_port_mask == mfilter->src_port_mask &&
2634 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2635 bfilter->dst_ipaddr_mask[0] ==
2636 mfilter->dst_ipaddr_mask[0] &&
2637 bfilter->dst_port == mfilter->dst_port &&
2638 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2639 bfilter->flags == mfilter->flags &&
2640 bfilter->enables == mfilter->enables) {
2651 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2652 struct rte_eth_ntuple_filter *nfilter,
2653 enum rte_filter_op filter_op)
2655 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2656 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2659 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2660 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2664 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2665 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2669 bfilter = bnxt_get_unused_filter(bp);
2670 if (bfilter == NULL) {
2672 "Not enough resources for a new filter.\n");
2675 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2679 vnic = &bp->vnic_info[nfilter->queue];
2680 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2681 filter1 = STAILQ_FIRST(&vnic0->filter);
2682 if (filter1 == NULL) {
2687 bfilter->dst_id = vnic->fw_vnic_id;
2688 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2690 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2691 bfilter->ethertype = 0x800;
2692 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2694 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2696 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2697 bfilter->dst_id == mfilter->dst_id) {
2698 PMD_DRV_LOG(ERR, "filter exists.\n");
2701 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2702 bfilter->dst_id != mfilter->dst_id) {
2703 mfilter->dst_id = vnic->fw_vnic_id;
2704 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2705 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2706 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2707 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2708 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2711 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2712 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2717 if (filter_op == RTE_ETH_FILTER_ADD) {
2718 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2719 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2722 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2724 if (mfilter == NULL) {
2725 /* This should not happen. But for Coverity! */
2729 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2731 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2732 bnxt_free_filter(bp, mfilter);
2733 bnxt_free_filter(bp, bfilter);
2738 bnxt_free_filter(bp, bfilter);
2743 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2744 enum rte_filter_op filter_op,
2747 struct bnxt *bp = dev->data->dev_private;
2750 if (filter_op == RTE_ETH_FILTER_NOP)
2754 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2759 switch (filter_op) {
2760 case RTE_ETH_FILTER_ADD:
2761 ret = bnxt_cfg_ntuple_filter(bp,
2762 (struct rte_eth_ntuple_filter *)arg,
2765 case RTE_ETH_FILTER_DELETE:
2766 ret = bnxt_cfg_ntuple_filter(bp,
2767 (struct rte_eth_ntuple_filter *)arg,
2771 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2779 bnxt_parse_fdir_filter(struct bnxt *bp,
2780 struct rte_eth_fdir_filter *fdir,
2781 struct bnxt_filter_info *filter)
2783 enum rte_fdir_mode fdir_mode =
2784 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2785 struct bnxt_vnic_info *vnic0, *vnic;
2786 struct bnxt_filter_info *filter1;
2790 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2793 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2794 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2796 switch (fdir->input.flow_type) {
2797 case RTE_ETH_FLOW_IPV4:
2798 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2800 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2801 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2802 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2803 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2804 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2805 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2806 filter->ip_addr_type =
2807 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2808 filter->src_ipaddr_mask[0] = 0xffffffff;
2809 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2810 filter->dst_ipaddr_mask[0] = 0xffffffff;
2811 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2812 filter->ethertype = 0x800;
2813 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2815 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2816 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2817 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2818 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2819 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2820 filter->dst_port_mask = 0xffff;
2821 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2822 filter->src_port_mask = 0xffff;
2823 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2824 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2825 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2826 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2827 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2828 filter->ip_protocol = 6;
2829 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2830 filter->ip_addr_type =
2831 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2832 filter->src_ipaddr_mask[0] = 0xffffffff;
2833 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2834 filter->dst_ipaddr_mask[0] = 0xffffffff;
2835 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2836 filter->ethertype = 0x800;
2837 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2839 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2840 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2841 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2842 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2843 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2844 filter->dst_port_mask = 0xffff;
2845 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2846 filter->src_port_mask = 0xffff;
2847 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2848 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2849 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2850 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2851 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2852 filter->ip_protocol = 17;
2853 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2854 filter->ip_addr_type =
2855 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2856 filter->src_ipaddr_mask[0] = 0xffffffff;
2857 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2858 filter->dst_ipaddr_mask[0] = 0xffffffff;
2859 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2860 filter->ethertype = 0x800;
2861 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2863 case RTE_ETH_FLOW_IPV6:
2864 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2866 filter->ip_addr_type =
2867 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2868 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2869 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2870 rte_memcpy(filter->src_ipaddr,
2871 fdir->input.flow.ipv6_flow.src_ip, 16);
2872 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2873 rte_memcpy(filter->dst_ipaddr,
2874 fdir->input.flow.ipv6_flow.dst_ip, 16);
2875 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2876 memset(filter->dst_ipaddr_mask, 0xff, 16);
2877 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2878 memset(filter->src_ipaddr_mask, 0xff, 16);
2879 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2880 filter->ethertype = 0x86dd;
2881 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2883 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2884 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2885 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2886 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2887 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2888 filter->dst_port_mask = 0xffff;
2889 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2890 filter->src_port_mask = 0xffff;
2891 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2892 filter->ip_addr_type =
2893 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2894 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2895 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2896 rte_memcpy(filter->src_ipaddr,
2897 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2898 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2899 rte_memcpy(filter->dst_ipaddr,
2900 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2901 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2902 memset(filter->dst_ipaddr_mask, 0xff, 16);
2903 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2904 memset(filter->src_ipaddr_mask, 0xff, 16);
2905 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2906 filter->ethertype = 0x86dd;
2907 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2909 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2910 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2911 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2912 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2913 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2914 filter->dst_port_mask = 0xffff;
2915 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2916 filter->src_port_mask = 0xffff;
2917 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2918 filter->ip_addr_type =
2919 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2920 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2921 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2922 rte_memcpy(filter->src_ipaddr,
2923 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2924 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2925 rte_memcpy(filter->dst_ipaddr,
2926 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2927 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2928 memset(filter->dst_ipaddr_mask, 0xff, 16);
2929 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2930 memset(filter->src_ipaddr_mask, 0xff, 16);
2931 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2932 filter->ethertype = 0x86dd;
2933 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2935 case RTE_ETH_FLOW_L2_PAYLOAD:
2936 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2937 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2939 case RTE_ETH_FLOW_VXLAN:
2940 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2942 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2943 filter->tunnel_type =
2944 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2945 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2947 case RTE_ETH_FLOW_NVGRE:
2948 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2950 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2951 filter->tunnel_type =
2952 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2953 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2955 case RTE_ETH_FLOW_UNKNOWN:
2956 case RTE_ETH_FLOW_RAW:
2957 case RTE_ETH_FLOW_FRAG_IPV4:
2958 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2959 case RTE_ETH_FLOW_FRAG_IPV6:
2960 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2961 case RTE_ETH_FLOW_IPV6_EX:
2962 case RTE_ETH_FLOW_IPV6_TCP_EX:
2963 case RTE_ETH_FLOW_IPV6_UDP_EX:
2964 case RTE_ETH_FLOW_GENEVE:
2970 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2971 vnic = &bp->vnic_info[fdir->action.rx_queue];
2973 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2977 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2978 rte_memcpy(filter->dst_macaddr,
2979 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2980 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2983 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2984 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2985 filter1 = STAILQ_FIRST(&vnic0->filter);
2986 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2988 filter->dst_id = vnic->fw_vnic_id;
2989 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
2990 if (filter->dst_macaddr[i] == 0x00)
2991 filter1 = STAILQ_FIRST(&vnic0->filter);
2993 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2996 if (filter1 == NULL)
2999 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3000 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3002 filter->enables = en;
3007 static struct bnxt_filter_info *
3008 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3009 struct bnxt_vnic_info **mvnic)
3011 struct bnxt_filter_info *mf = NULL;
3014 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3015 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3017 STAILQ_FOREACH(mf, &vnic->filter, next) {
3018 if (mf->filter_type == nf->filter_type &&
3019 mf->flags == nf->flags &&
3020 mf->src_port == nf->src_port &&
3021 mf->src_port_mask == nf->src_port_mask &&
3022 mf->dst_port == nf->dst_port &&
3023 mf->dst_port_mask == nf->dst_port_mask &&
3024 mf->ip_protocol == nf->ip_protocol &&
3025 mf->ip_addr_type == nf->ip_addr_type &&
3026 mf->ethertype == nf->ethertype &&
3027 mf->vni == nf->vni &&
3028 mf->tunnel_type == nf->tunnel_type &&
3029 mf->l2_ovlan == nf->l2_ovlan &&
3030 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3031 mf->l2_ivlan == nf->l2_ivlan &&
3032 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3033 !memcmp(mf->l2_addr, nf->l2_addr,
3034 RTE_ETHER_ADDR_LEN) &&
3035 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3036 RTE_ETHER_ADDR_LEN) &&
3037 !memcmp(mf->src_macaddr, nf->src_macaddr,
3038 RTE_ETHER_ADDR_LEN) &&
3039 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3040 RTE_ETHER_ADDR_LEN) &&
3041 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3042 sizeof(nf->src_ipaddr)) &&
3043 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3044 sizeof(nf->src_ipaddr_mask)) &&
3045 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3046 sizeof(nf->dst_ipaddr)) &&
3047 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3048 sizeof(nf->dst_ipaddr_mask))) {
3059 bnxt_fdir_filter(struct rte_eth_dev *dev,
3060 enum rte_filter_op filter_op,
3063 struct bnxt *bp = dev->data->dev_private;
3064 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3065 struct bnxt_filter_info *filter, *match;
3066 struct bnxt_vnic_info *vnic, *mvnic;
3069 if (filter_op == RTE_ETH_FILTER_NOP)
3072 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3075 switch (filter_op) {
3076 case RTE_ETH_FILTER_ADD:
3077 case RTE_ETH_FILTER_DELETE:
3079 filter = bnxt_get_unused_filter(bp);
3080 if (filter == NULL) {
3082 "Not enough resources for a new flow.\n");
3086 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3089 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3091 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3092 vnic = &bp->vnic_info[0];
3094 vnic = &bp->vnic_info[fdir->action.rx_queue];
3096 match = bnxt_match_fdir(bp, filter, &mvnic);
3097 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3098 if (match->dst_id == vnic->fw_vnic_id) {
3099 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3103 match->dst_id = vnic->fw_vnic_id;
3104 ret = bnxt_hwrm_set_ntuple_filter(bp,
3107 STAILQ_REMOVE(&mvnic->filter, match,
3108 bnxt_filter_info, next);
3109 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3111 "Filter with matching pattern exist\n");
3113 "Updated it to new destination q\n");
3117 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3118 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3123 if (filter_op == RTE_ETH_FILTER_ADD) {
3124 ret = bnxt_hwrm_set_ntuple_filter(bp,
3129 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3131 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3132 STAILQ_REMOVE(&vnic->filter, match,
3133 bnxt_filter_info, next);
3134 bnxt_free_filter(bp, match);
3135 bnxt_free_filter(bp, filter);
3138 case RTE_ETH_FILTER_FLUSH:
3139 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3140 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3142 STAILQ_FOREACH(filter, &vnic->filter, next) {
3143 if (filter->filter_type ==
3144 HWRM_CFA_NTUPLE_FILTER) {
3146 bnxt_hwrm_clear_ntuple_filter(bp,
3148 STAILQ_REMOVE(&vnic->filter, filter,
3149 bnxt_filter_info, next);
3154 case RTE_ETH_FILTER_UPDATE:
3155 case RTE_ETH_FILTER_STATS:
3156 case RTE_ETH_FILTER_INFO:
3157 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3160 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3167 bnxt_free_filter(bp, filter);
3172 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3173 enum rte_filter_type filter_type,
3174 enum rte_filter_op filter_op, void *arg)
3178 ret = is_bnxt_in_error(dev->data->dev_private);
3182 switch (filter_type) {
3183 case RTE_ETH_FILTER_TUNNEL:
3185 "filter type: %d: To be implemented\n", filter_type);
3187 case RTE_ETH_FILTER_FDIR:
3188 ret = bnxt_fdir_filter(dev, filter_op, arg);
3190 case RTE_ETH_FILTER_NTUPLE:
3191 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3193 case RTE_ETH_FILTER_ETHERTYPE:
3194 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3196 case RTE_ETH_FILTER_GENERIC:
3197 if (filter_op != RTE_ETH_FILTER_GET)
3199 *(const void **)arg = &bnxt_flow_ops;
3203 "Filter type (%d) not supported", filter_type);
3210 static const uint32_t *
3211 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3213 static const uint32_t ptypes[] = {
3214 RTE_PTYPE_L2_ETHER_VLAN,
3215 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3216 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3220 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3221 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3222 RTE_PTYPE_INNER_L4_ICMP,
3223 RTE_PTYPE_INNER_L4_TCP,
3224 RTE_PTYPE_INNER_L4_UDP,
3228 if (!dev->rx_pkt_burst)
3234 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3237 uint32_t reg_base = *reg_arr & 0xfffff000;
3241 for (i = 0; i < count; i++) {
3242 if ((reg_arr[i] & 0xfffff000) != reg_base)
3245 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3246 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3250 static int bnxt_map_ptp_regs(struct bnxt *bp)
3252 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3256 reg_arr = ptp->rx_regs;
3257 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3261 reg_arr = ptp->tx_regs;
3262 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3266 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3267 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3269 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3270 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3275 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3277 rte_write32(0, (uint8_t *)bp->bar0 +
3278 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3279 rte_write32(0, (uint8_t *)bp->bar0 +
3280 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3283 static uint64_t bnxt_cc_read(struct bnxt *bp)
3287 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3288 BNXT_GRCPF_REG_SYNC_TIME));
3289 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3290 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3294 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3296 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3299 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3300 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3301 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3304 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3305 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3306 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3307 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3308 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3309 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3314 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3316 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3317 struct bnxt_pf_info *pf = &bp->pf;
3324 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3325 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3326 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3329 port_id = pf->port_id;
3330 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3331 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3333 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3334 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3335 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3336 /* bnxt_clr_rx_ts(bp); TBD */
3340 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3341 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3342 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3343 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3349 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3352 struct bnxt *bp = dev->data->dev_private;
3353 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3358 ns = rte_timespec_to_ns(ts);
3359 /* Set the timecounters to a new value. */
3366 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3368 struct bnxt *bp = dev->data->dev_private;
3369 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3370 uint64_t ns, systime_cycles = 0;
3376 if (BNXT_CHIP_THOR(bp))
3377 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3380 systime_cycles = bnxt_cc_read(bp);
3382 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3383 *ts = rte_ns_to_timespec(ns);
3388 bnxt_timesync_enable(struct rte_eth_dev *dev)
3390 struct bnxt *bp = dev->data->dev_private;
3391 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3399 ptp->tx_tstamp_en = 1;
3400 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3402 rc = bnxt_hwrm_ptp_cfg(bp);
3406 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3407 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3408 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3410 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3411 ptp->tc.cc_shift = shift;
3412 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3414 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3415 ptp->rx_tstamp_tc.cc_shift = shift;
3416 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3418 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3419 ptp->tx_tstamp_tc.cc_shift = shift;
3420 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3422 if (!BNXT_CHIP_THOR(bp))
3423 bnxt_map_ptp_regs(bp);
3429 bnxt_timesync_disable(struct rte_eth_dev *dev)
3431 struct bnxt *bp = dev->data->dev_private;
3432 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3438 ptp->tx_tstamp_en = 0;
3441 bnxt_hwrm_ptp_cfg(bp);
3443 if (!BNXT_CHIP_THOR(bp))
3444 bnxt_unmap_ptp_regs(bp);
3450 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3451 struct timespec *timestamp,
3452 uint32_t flags __rte_unused)
3454 struct bnxt *bp = dev->data->dev_private;
3455 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3456 uint64_t rx_tstamp_cycles = 0;
3462 if (BNXT_CHIP_THOR(bp))
3463 rx_tstamp_cycles = ptp->rx_timestamp;
3465 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3467 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3468 *timestamp = rte_ns_to_timespec(ns);
3473 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3474 struct timespec *timestamp)
3476 struct bnxt *bp = dev->data->dev_private;
3477 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3478 uint64_t tx_tstamp_cycles = 0;
3485 if (BNXT_CHIP_THOR(bp))
3486 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3489 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3491 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3492 *timestamp = rte_ns_to_timespec(ns);
3498 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3500 struct bnxt *bp = dev->data->dev_private;
3501 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3506 ptp->tc.nsec += delta;
3512 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3514 struct bnxt *bp = dev->data->dev_private;
3516 uint32_t dir_entries;
3517 uint32_t entry_length;
3519 rc = is_bnxt_in_error(bp);
3523 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3524 bp->pdev->addr.domain, bp->pdev->addr.bus,
3525 bp->pdev->addr.devid, bp->pdev->addr.function);
3527 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3531 return dir_entries * entry_length;
3535 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3536 struct rte_dev_eeprom_info *in_eeprom)
3538 struct bnxt *bp = dev->data->dev_private;
3543 rc = is_bnxt_in_error(bp);
3547 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3548 "len = %d\n", bp->pdev->addr.domain,
3549 bp->pdev->addr.bus, bp->pdev->addr.devid,
3550 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3552 if (in_eeprom->offset == 0) /* special offset value to get directory */
3553 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3556 index = in_eeprom->offset >> 24;
3557 offset = in_eeprom->offset & 0xffffff;
3560 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3561 in_eeprom->length, in_eeprom->data);
3566 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3569 case BNX_DIR_TYPE_CHIMP_PATCH:
3570 case BNX_DIR_TYPE_BOOTCODE:
3571 case BNX_DIR_TYPE_BOOTCODE_2:
3572 case BNX_DIR_TYPE_APE_FW:
3573 case BNX_DIR_TYPE_APE_PATCH:
3574 case BNX_DIR_TYPE_KONG_FW:
3575 case BNX_DIR_TYPE_KONG_PATCH:
3576 case BNX_DIR_TYPE_BONO_FW:
3577 case BNX_DIR_TYPE_BONO_PATCH:
3585 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3588 case BNX_DIR_TYPE_AVS:
3589 case BNX_DIR_TYPE_EXP_ROM_MBA:
3590 case BNX_DIR_TYPE_PCIE:
3591 case BNX_DIR_TYPE_TSCF_UCODE:
3592 case BNX_DIR_TYPE_EXT_PHY:
3593 case BNX_DIR_TYPE_CCM:
3594 case BNX_DIR_TYPE_ISCSI_BOOT:
3595 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3596 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3604 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3606 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3607 bnxt_dir_type_is_other_exec_format(dir_type);
3611 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3612 struct rte_dev_eeprom_info *in_eeprom)
3614 struct bnxt *bp = dev->data->dev_private;
3615 uint8_t index, dir_op;
3616 uint16_t type, ext, ordinal, attr;
3619 rc = is_bnxt_in_error(bp);
3623 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3624 "len = %d\n", bp->pdev->addr.domain,
3625 bp->pdev->addr.bus, bp->pdev->addr.devid,
3626 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3629 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3633 type = in_eeprom->magic >> 16;
3635 if (type == 0xffff) { /* special value for directory operations */
3636 index = in_eeprom->magic & 0xff;
3637 dir_op = in_eeprom->magic >> 8;
3641 case 0x0e: /* erase */
3642 if (in_eeprom->offset != ~in_eeprom->magic)
3644 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3650 /* Create or re-write an NVM item: */
3651 if (bnxt_dir_type_is_executable(type) == true)
3653 ext = in_eeprom->magic & 0xffff;
3654 ordinal = in_eeprom->offset >> 16;
3655 attr = in_eeprom->offset & 0xffff;
3657 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3658 in_eeprom->data, in_eeprom->length);
3665 static const struct eth_dev_ops bnxt_dev_ops = {
3666 .dev_infos_get = bnxt_dev_info_get_op,
3667 .dev_close = bnxt_dev_close_op,
3668 .dev_configure = bnxt_dev_configure_op,
3669 .dev_start = bnxt_dev_start_op,
3670 .dev_stop = bnxt_dev_stop_op,
3671 .dev_set_link_up = bnxt_dev_set_link_up_op,
3672 .dev_set_link_down = bnxt_dev_set_link_down_op,
3673 .stats_get = bnxt_stats_get_op,
3674 .stats_reset = bnxt_stats_reset_op,
3675 .rx_queue_setup = bnxt_rx_queue_setup_op,
3676 .rx_queue_release = bnxt_rx_queue_release_op,
3677 .tx_queue_setup = bnxt_tx_queue_setup_op,
3678 .tx_queue_release = bnxt_tx_queue_release_op,
3679 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3680 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3681 .reta_update = bnxt_reta_update_op,
3682 .reta_query = bnxt_reta_query_op,
3683 .rss_hash_update = bnxt_rss_hash_update_op,
3684 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3685 .link_update = bnxt_link_update_op,
3686 .promiscuous_enable = bnxt_promiscuous_enable_op,
3687 .promiscuous_disable = bnxt_promiscuous_disable_op,
3688 .allmulticast_enable = bnxt_allmulticast_enable_op,
3689 .allmulticast_disable = bnxt_allmulticast_disable_op,
3690 .mac_addr_add = bnxt_mac_addr_add_op,
3691 .mac_addr_remove = bnxt_mac_addr_remove_op,
3692 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3693 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3694 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3695 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3696 .vlan_filter_set = bnxt_vlan_filter_set_op,
3697 .vlan_offload_set = bnxt_vlan_offload_set_op,
3698 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3699 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3700 .mtu_set = bnxt_mtu_set_op,
3701 .mac_addr_set = bnxt_set_default_mac_addr_op,
3702 .xstats_get = bnxt_dev_xstats_get_op,
3703 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3704 .xstats_reset = bnxt_dev_xstats_reset_op,
3705 .fw_version_get = bnxt_fw_version_get,
3706 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3707 .rxq_info_get = bnxt_rxq_info_get_op,
3708 .txq_info_get = bnxt_txq_info_get_op,
3709 .dev_led_on = bnxt_dev_led_on_op,
3710 .dev_led_off = bnxt_dev_led_off_op,
3711 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3712 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3713 .rx_queue_count = bnxt_rx_queue_count_op,
3714 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3715 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3716 .rx_queue_start = bnxt_rx_queue_start,
3717 .rx_queue_stop = bnxt_rx_queue_stop,
3718 .tx_queue_start = bnxt_tx_queue_start,
3719 .tx_queue_stop = bnxt_tx_queue_stop,
3720 .filter_ctrl = bnxt_filter_ctrl_op,
3721 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3722 .get_eeprom_length = bnxt_get_eeprom_length_op,
3723 .get_eeprom = bnxt_get_eeprom_op,
3724 .set_eeprom = bnxt_set_eeprom_op,
3725 .timesync_enable = bnxt_timesync_enable,
3726 .timesync_disable = bnxt_timesync_disable,
3727 .timesync_read_time = bnxt_timesync_read_time,
3728 .timesync_write_time = bnxt_timesync_write_time,
3729 .timesync_adjust_time = bnxt_timesync_adjust_time,
3730 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3731 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3734 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3738 /* Only pre-map the reset GRC registers using window 3 */
3739 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3740 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3742 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3747 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3749 struct bnxt_error_recovery_info *info = bp->recovery_info;
3750 uint32_t reg_base = 0xffffffff;
3753 /* Only pre-map the monitoring GRC registers using window 2 */
3754 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3755 uint32_t reg = info->status_regs[i];
3757 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3760 if (reg_base == 0xffffffff)
3761 reg_base = reg & 0xfffff000;
3762 if ((reg & 0xfffff000) != reg_base)
3765 /* Use mask 0xffc as the Lower 2 bits indicates
3766 * address space location
3768 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3772 if (reg_base == 0xffffffff)
3775 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3776 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3781 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3783 struct bnxt_error_recovery_info *info = bp->recovery_info;
3784 uint32_t delay = info->delay_after_reset[index];
3785 uint32_t val = info->reset_reg_val[index];
3786 uint32_t reg = info->reset_reg[index];
3787 uint32_t type, offset;
3789 type = BNXT_FW_STATUS_REG_TYPE(reg);
3790 offset = BNXT_FW_STATUS_REG_OFF(reg);
3793 case BNXT_FW_STATUS_REG_TYPE_CFG:
3794 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3796 case BNXT_FW_STATUS_REG_TYPE_GRC:
3797 offset = bnxt_map_reset_regs(bp, offset);
3798 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3800 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3801 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3804 /* wait on a specific interval of time until core reset is complete */
3806 rte_delay_ms(delay);
3809 static void bnxt_dev_cleanup(struct bnxt *bp)
3811 bnxt_set_hwrm_link_config(bp, false);
3812 bp->link_info.link_up = 0;
3813 if (bp->dev_stopped == 0)
3814 bnxt_dev_stop_op(bp->eth_dev);
3816 bnxt_uninit_resources(bp, true);
3819 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3821 struct rte_eth_dev *dev = bp->eth_dev;
3822 struct rte_vlan_filter_conf *vfc;
3826 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3827 vfc = &dev->data->vlan_filter_conf;
3828 vidx = vlan_id / 64;
3829 vbit = vlan_id % 64;
3831 /* Each bit corresponds to a VLAN id */
3832 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3833 rc = bnxt_add_vlan_filter(bp, vlan_id);
3842 static int bnxt_restore_mac_filters(struct bnxt *bp)
3844 struct rte_eth_dev *dev = bp->eth_dev;
3845 struct rte_eth_dev_info dev_info;
3846 struct rte_ether_addr *addr;
3852 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
3855 rc = bnxt_dev_info_get_op(dev, &dev_info);
3859 /* replay MAC address configuration */
3860 for (i = 1; i < dev_info.max_mac_addrs; i++) {
3861 addr = &dev->data->mac_addrs[i];
3863 /* skip zero address */
3864 if (rte_is_zero_ether_addr(addr))
3868 pool_mask = dev->data->mac_pool_sel[i];
3871 if (pool_mask & 1ULL) {
3872 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3878 } while (pool_mask);
3884 static int bnxt_restore_filters(struct bnxt *bp)
3886 struct rte_eth_dev *dev = bp->eth_dev;
3889 if (dev->data->all_multicast)
3890 ret = bnxt_allmulticast_enable_op(dev);
3891 if (dev->data->promiscuous)
3892 ret = bnxt_promiscuous_enable_op(dev);
3894 ret = bnxt_restore_mac_filters(bp);
3898 ret = bnxt_restore_vlan_filters(bp);
3899 /* TODO restore other filters as well */
3903 static void bnxt_dev_recover(void *arg)
3905 struct bnxt *bp = arg;
3906 int timeout = bp->fw_reset_max_msecs;
3909 /* Clear Error flag so that device re-init should happen */
3910 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3913 rc = bnxt_hwrm_ver_get(bp);
3916 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3917 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3918 } while (rc && timeout);
3921 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3925 rc = bnxt_init_resources(bp, true);
3928 "Failed to initialize resources after reset\n");
3931 /* clear reset flag as the device is initialized now */
3932 bp->flags &= ~BNXT_FLAG_FW_RESET;
3934 rc = bnxt_dev_start_op(bp->eth_dev);
3936 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3940 rc = bnxt_restore_filters(bp);
3944 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3947 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3948 bnxt_uninit_resources(bp, false);
3949 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3952 void bnxt_dev_reset_and_resume(void *arg)
3954 struct bnxt *bp = arg;
3957 bnxt_dev_cleanup(bp);
3959 bnxt_wait_for_device_shutdown(bp);
3961 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3962 bnxt_dev_recover, (void *)bp);
3964 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3967 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3969 struct bnxt_error_recovery_info *info = bp->recovery_info;
3970 uint32_t reg = info->status_regs[index];
3971 uint32_t type, offset, val = 0;
3973 type = BNXT_FW_STATUS_REG_TYPE(reg);
3974 offset = BNXT_FW_STATUS_REG_OFF(reg);
3977 case BNXT_FW_STATUS_REG_TYPE_CFG:
3978 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3980 case BNXT_FW_STATUS_REG_TYPE_GRC:
3981 offset = info->mapped_status_regs[index];
3983 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3984 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3992 static int bnxt_fw_reset_all(struct bnxt *bp)
3994 struct bnxt_error_recovery_info *info = bp->recovery_info;
3998 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3999 /* Reset through master function driver */
4000 for (i = 0; i < info->reg_array_cnt; i++)
4001 bnxt_write_fw_reset_reg(bp, i);
4002 /* Wait for time specified by FW after triggering reset */
4003 rte_delay_ms(info->master_func_wait_period_after_reset);
4004 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4005 /* Reset with the help of Kong processor */
4006 rc = bnxt_hwrm_fw_reset(bp);
4008 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4014 static void bnxt_fw_reset_cb(void *arg)
4016 struct bnxt *bp = arg;
4017 struct bnxt_error_recovery_info *info = bp->recovery_info;
4020 /* Only Master function can do FW reset */
4021 if (bnxt_is_master_func(bp) &&
4022 bnxt_is_recovery_enabled(bp)) {
4023 rc = bnxt_fw_reset_all(bp);
4025 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4030 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4031 * EXCEPTION_FATAL_ASYNC event to all the functions
4032 * (including MASTER FUNC). After receiving this Async, all the active
4033 * drivers should treat this case as FW initiated recovery
4035 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4036 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4037 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4039 /* To recover from error */
4040 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4045 /* Driver should poll FW heartbeat, reset_counter with the frequency
4046 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4047 * When the driver detects heartbeat stop or change in reset_counter,
4048 * it has to trigger a reset to recover from the error condition.
4049 * A “master PF” is the function who will have the privilege to
4050 * initiate the chimp reset. The master PF will be elected by the
4051 * firmware and will be notified through async message.
4053 static void bnxt_check_fw_health(void *arg)
4055 struct bnxt *bp = arg;
4056 struct bnxt_error_recovery_info *info = bp->recovery_info;
4057 uint32_t val = 0, wait_msec;
4059 if (!info || !bnxt_is_recovery_enabled(bp) ||
4060 is_bnxt_in_error(bp))
4063 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4064 if (val == info->last_heart_beat)
4067 info->last_heart_beat = val;
4069 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4070 if (val != info->last_reset_counter)
4073 info->last_reset_counter = val;
4075 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4076 bnxt_check_fw_health, (void *)bp);
4080 /* Stop DMA to/from device */
4081 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4082 bp->flags |= BNXT_FLAG_FW_RESET;
4084 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4086 if (bnxt_is_master_func(bp))
4087 wait_msec = info->master_func_wait_period;
4089 wait_msec = info->normal_func_wait_period;
4091 rte_eal_alarm_set(US_PER_MS * wait_msec,
4092 bnxt_fw_reset_cb, (void *)bp);
4095 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4097 uint32_t polling_freq;
4099 if (!bnxt_is_recovery_enabled(bp))
4102 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4105 polling_freq = bp->recovery_info->driver_polling_freq;
4107 rte_eal_alarm_set(US_PER_MS * polling_freq,
4108 bnxt_check_fw_health, (void *)bp);
4109 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4112 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4114 if (!bnxt_is_recovery_enabled(bp))
4117 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4118 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4121 static bool bnxt_vf_pciid(uint16_t device_id)
4123 switch (device_id) {
4124 case BROADCOM_DEV_ID_57304_VF:
4125 case BROADCOM_DEV_ID_57406_VF:
4126 case BROADCOM_DEV_ID_5731X_VF:
4127 case BROADCOM_DEV_ID_5741X_VF:
4128 case BROADCOM_DEV_ID_57414_VF:
4129 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4130 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4131 case BROADCOM_DEV_ID_58802_VF:
4132 case BROADCOM_DEV_ID_57500_VF1:
4133 case BROADCOM_DEV_ID_57500_VF2:
4141 static bool bnxt_thor_device(uint16_t device_id)
4143 switch (device_id) {
4144 case BROADCOM_DEV_ID_57508:
4145 case BROADCOM_DEV_ID_57504:
4146 case BROADCOM_DEV_ID_57502:
4147 case BROADCOM_DEV_ID_57508_MF1:
4148 case BROADCOM_DEV_ID_57504_MF1:
4149 case BROADCOM_DEV_ID_57502_MF1:
4150 case BROADCOM_DEV_ID_57508_MF2:
4151 case BROADCOM_DEV_ID_57504_MF2:
4152 case BROADCOM_DEV_ID_57502_MF2:
4153 case BROADCOM_DEV_ID_57500_VF1:
4154 case BROADCOM_DEV_ID_57500_VF2:
4162 bool bnxt_stratus_device(struct bnxt *bp)
4164 uint16_t device_id = bp->pdev->id.device_id;
4166 switch (device_id) {
4167 case BROADCOM_DEV_ID_STRATUS_NIC:
4168 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4169 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4177 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4179 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4180 struct bnxt *bp = eth_dev->data->dev_private;
4182 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4183 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4184 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4185 if (!bp->bar0 || !bp->doorbell_base) {
4186 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4190 bp->eth_dev = eth_dev;
4196 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4197 struct bnxt_ctx_pg_info *ctx_pg,
4202 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4203 const struct rte_memzone *mz = NULL;
4204 char mz_name[RTE_MEMZONE_NAMESIZE];
4205 rte_iova_t mz_phys_addr;
4206 uint64_t valid_bits = 0;
4213 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4215 rmem->page_size = BNXT_PAGE_SIZE;
4216 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4217 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4218 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4220 valid_bits = PTU_PTE_VALID;
4222 if (rmem->nr_pages > 1) {
4223 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4224 "bnxt_ctx_pg_tbl%s_%x_%d",
4225 suffix, idx, bp->eth_dev->data->port_id);
4226 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4227 mz = rte_memzone_lookup(mz_name);
4229 mz = rte_memzone_reserve_aligned(mz_name,
4233 RTE_MEMZONE_SIZE_HINT_ONLY |
4234 RTE_MEMZONE_IOVA_CONTIG,
4240 memset(mz->addr, 0, mz->len);
4241 mz_phys_addr = mz->iova;
4243 rmem->pg_tbl = mz->addr;
4244 rmem->pg_tbl_map = mz_phys_addr;
4245 rmem->pg_tbl_mz = mz;
4248 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4249 suffix, idx, bp->eth_dev->data->port_id);
4250 mz = rte_memzone_lookup(mz_name);
4252 mz = rte_memzone_reserve_aligned(mz_name,
4256 RTE_MEMZONE_SIZE_HINT_ONLY |
4257 RTE_MEMZONE_IOVA_CONTIG,
4263 memset(mz->addr, 0, mz->len);
4264 mz_phys_addr = mz->iova;
4266 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4267 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4268 rmem->dma_arr[i] = mz_phys_addr + sz;
4270 if (rmem->nr_pages > 1) {
4271 if (i == rmem->nr_pages - 2 &&
4272 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4273 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4274 else if (i == rmem->nr_pages - 1 &&
4275 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4276 valid_bits |= PTU_PTE_LAST;
4278 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4284 if (rmem->vmem_size)
4285 rmem->vmem = (void **)mz->addr;
4286 rmem->dma_arr[0] = mz_phys_addr;
4290 static void bnxt_free_ctx_mem(struct bnxt *bp)
4294 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4297 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4298 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4299 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4300 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4301 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4302 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4303 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4304 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4305 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4306 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4307 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4309 for (i = 0; i < BNXT_MAX_Q; i++) {
4310 if (bp->ctx->tqm_mem[i])
4311 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4318 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4320 #define min_t(type, x, y) ({ \
4321 type __min1 = (x); \
4322 type __min2 = (y); \
4323 __min1 < __min2 ? __min1 : __min2; })
4325 #define max_t(type, x, y) ({ \
4326 type __max1 = (x); \
4327 type __max2 = (y); \
4328 __max1 > __max2 ? __max1 : __max2; })
4330 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4332 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4334 struct bnxt_ctx_pg_info *ctx_pg;
4335 struct bnxt_ctx_mem_info *ctx;
4336 uint32_t mem_size, ena, entries;
4339 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4341 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4345 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4348 ctx_pg = &ctx->qp_mem;
4349 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4350 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4351 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4355 ctx_pg = &ctx->srq_mem;
4356 ctx_pg->entries = ctx->srq_max_l2_entries;
4357 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4358 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4362 ctx_pg = &ctx->cq_mem;
4363 ctx_pg->entries = ctx->cq_max_l2_entries;
4364 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4365 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4369 ctx_pg = &ctx->vnic_mem;
4370 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4371 ctx->vnic_max_ring_table_entries;
4372 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4373 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4377 ctx_pg = &ctx->stat_mem;
4378 ctx_pg->entries = ctx->stat_max_entries;
4379 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4380 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4384 entries = ctx->qp_max_l2_entries +
4385 ctx->vnic_max_vnic_entries +
4386 ctx->tqm_min_entries_per_ring;
4387 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4388 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4389 ctx->tqm_max_entries_per_ring);
4390 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4391 ctx_pg = ctx->tqm_mem[i];
4392 /* use min tqm entries for now. */
4393 ctx_pg->entries = entries;
4394 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4395 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4398 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4401 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4402 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4405 "Failed to configure context mem: rc = %d\n", rc);
4407 ctx->flags |= BNXT_CTX_FLAG_INITED;
4412 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4414 struct rte_pci_device *pci_dev = bp->pdev;
4415 char mz_name[RTE_MEMZONE_NAMESIZE];
4416 const struct rte_memzone *mz = NULL;
4417 uint32_t total_alloc_len;
4418 rte_iova_t mz_phys_addr;
4420 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4423 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4424 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4425 pci_dev->addr.bus, pci_dev->addr.devid,
4426 pci_dev->addr.function, "rx_port_stats");
4427 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4428 mz = rte_memzone_lookup(mz_name);
4430 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4431 sizeof(struct rx_port_stats_ext) + 512);
4433 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4436 RTE_MEMZONE_SIZE_HINT_ONLY |
4437 RTE_MEMZONE_IOVA_CONTIG);
4441 memset(mz->addr, 0, mz->len);
4442 mz_phys_addr = mz->iova;
4444 bp->rx_mem_zone = (const void *)mz;
4445 bp->hw_rx_port_stats = mz->addr;
4446 bp->hw_rx_port_stats_map = mz_phys_addr;
4448 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4449 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4450 pci_dev->addr.bus, pci_dev->addr.devid,
4451 pci_dev->addr.function, "tx_port_stats");
4452 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4453 mz = rte_memzone_lookup(mz_name);
4455 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4456 sizeof(struct tx_port_stats_ext) + 512);
4458 mz = rte_memzone_reserve(mz_name,
4462 RTE_MEMZONE_SIZE_HINT_ONLY |
4463 RTE_MEMZONE_IOVA_CONTIG);
4467 memset(mz->addr, 0, mz->len);
4468 mz_phys_addr = mz->iova;
4470 bp->tx_mem_zone = (const void *)mz;
4471 bp->hw_tx_port_stats = mz->addr;
4472 bp->hw_tx_port_stats_map = mz_phys_addr;
4473 bp->flags |= BNXT_FLAG_PORT_STATS;
4475 /* Display extended statistics if FW supports it */
4476 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4477 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4478 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4481 bp->hw_rx_port_stats_ext = (void *)
4482 ((uint8_t *)bp->hw_rx_port_stats +
4483 sizeof(struct rx_port_stats));
4484 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4485 sizeof(struct rx_port_stats);
4486 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4488 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4489 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4490 bp->hw_tx_port_stats_ext = (void *)
4491 ((uint8_t *)bp->hw_tx_port_stats +
4492 sizeof(struct tx_port_stats));
4493 bp->hw_tx_port_stats_ext_map =
4494 bp->hw_tx_port_stats_map +
4495 sizeof(struct tx_port_stats);
4496 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4502 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4504 struct bnxt *bp = eth_dev->data->dev_private;
4507 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4508 RTE_ETHER_ADDR_LEN *
4511 if (eth_dev->data->mac_addrs == NULL) {
4512 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4516 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4520 /* Generate a random MAC address, if none was assigned by PF */
4521 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4522 bnxt_eth_hw_addr_random(bp->mac_addr);
4524 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4525 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4526 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4528 rc = bnxt_hwrm_set_mac(bp);
4530 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4531 RTE_ETHER_ADDR_LEN);
4535 /* Copy the permanent MAC from the FUNC_QCAPS response */
4536 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4537 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4542 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4546 /* MAC is already configured in FW */
4547 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4550 /* Restore the old MAC configured */
4551 rc = bnxt_hwrm_set_mac(bp);
4553 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4558 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4563 #define ALLOW_FUNC(x) \
4565 uint32_t arg = (x); \
4566 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4567 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4570 /* Forward all requests if firmware is new enough */
4571 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4572 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4573 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4574 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4576 PMD_DRV_LOG(WARNING,
4577 "Firmware too old for VF mailbox functionality\n");
4578 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4582 * The following are used for driver cleanup. If we disallow these,
4583 * VF drivers can't clean up cleanly.
4585 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4586 ALLOW_FUNC(HWRM_VNIC_FREE);
4587 ALLOW_FUNC(HWRM_RING_FREE);
4588 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4589 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4590 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4591 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4592 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4593 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4596 static int bnxt_init_fw(struct bnxt *bp)
4603 rc = bnxt_hwrm_ver_get(bp);
4607 rc = bnxt_hwrm_func_reset(bp);
4611 rc = bnxt_hwrm_vnic_qcaps(bp);
4615 rc = bnxt_hwrm_queue_qportcfg(bp);
4619 /* Get the MAX capabilities for this function.
4620 * This function also allocates context memory for TQM rings and
4621 * informs the firmware about this allocated backing store memory.
4623 rc = bnxt_hwrm_func_qcaps(bp);
4627 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4631 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4635 /* Get the adapter error recovery support info */
4636 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4638 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4640 bnxt_hwrm_port_led_qcaps(bp);
4646 bnxt_init_locks(struct bnxt *bp)
4650 err = pthread_mutex_init(&bp->flow_lock, NULL);
4652 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4656 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4658 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4662 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4666 rc = bnxt_init_fw(bp);
4670 if (!reconfig_dev) {
4671 rc = bnxt_setup_mac_addr(bp->eth_dev);
4675 rc = bnxt_restore_dflt_mac(bp);
4680 bnxt_config_vf_req_fwd(bp);
4682 rc = bnxt_hwrm_func_driver_register(bp);
4684 PMD_DRV_LOG(ERR, "Failed to register driver");
4689 if (bp->pdev->max_vfs) {
4690 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4692 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4696 rc = bnxt_hwrm_allocate_pf_only(bp);
4699 "Failed to allocate PF resources");
4705 rc = bnxt_alloc_mem(bp, reconfig_dev);
4709 rc = bnxt_setup_int(bp);
4713 rc = bnxt_request_int(bp);
4717 rc = bnxt_init_locks(bp);
4725 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4727 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4728 static int version_printed;
4732 if (version_printed++ == 0)
4733 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4735 eth_dev->dev_ops = &bnxt_dev_ops;
4736 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4737 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4740 * For secondary processes, we don't initialise any further
4741 * as primary has already done this work.
4743 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4746 rte_eth_copy_pci_info(eth_dev, pci_dev);
4748 bp = eth_dev->data->dev_private;
4750 bp->dev_stopped = 1;
4751 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
4753 if (bnxt_vf_pciid(pci_dev->id.device_id))
4754 bp->flags |= BNXT_FLAG_VF;
4756 if (bnxt_thor_device(pci_dev->id.device_id))
4757 bp->flags |= BNXT_FLAG_THOR_CHIP;
4759 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4760 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4761 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4762 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4763 bp->flags |= BNXT_FLAG_STINGRAY;
4765 rc = bnxt_init_board(eth_dev);
4768 "Failed to initialize board rc: %x\n", rc);
4772 rc = bnxt_alloc_hwrm_resources(bp);
4775 "Failed to allocate hwrm resource rc: %x\n", rc);
4778 rc = bnxt_init_resources(bp, false);
4782 rc = bnxt_alloc_stats_mem(bp);
4787 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4788 pci_dev->mem_resource[0].phys_addr,
4789 pci_dev->mem_resource[0].addr);
4794 bnxt_dev_uninit(eth_dev);
4799 bnxt_uninit_locks(struct bnxt *bp)
4801 pthread_mutex_destroy(&bp->flow_lock);
4802 pthread_mutex_destroy(&bp->def_cp_lock);
4806 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4811 bnxt_free_mem(bp, reconfig_dev);
4812 bnxt_hwrm_func_buf_unrgtr(bp);
4813 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4814 bp->flags &= ~BNXT_FLAG_REGISTERED;
4815 bnxt_free_ctx_mem(bp);
4816 if (!reconfig_dev) {
4817 bnxt_free_hwrm_resources(bp);
4819 if (bp->recovery_info != NULL) {
4820 rte_free(bp->recovery_info);
4821 bp->recovery_info = NULL;
4825 bnxt_uninit_locks(bp);
4826 rte_free(bp->ptp_cfg);
4832 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4834 struct bnxt *bp = eth_dev->data->dev_private;
4837 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4840 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4842 rc = bnxt_uninit_resources(bp, false);
4844 if (bp->tx_mem_zone) {
4845 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4846 bp->tx_mem_zone = NULL;
4849 if (bp->rx_mem_zone) {
4850 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4851 bp->rx_mem_zone = NULL;
4854 if (bp->dev_stopped == 0)
4855 bnxt_dev_close_op(eth_dev);
4857 rte_free(bp->pf.vf_info);
4858 eth_dev->dev_ops = NULL;
4859 eth_dev->rx_pkt_burst = NULL;
4860 eth_dev->tx_pkt_burst = NULL;
4865 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4866 struct rte_pci_device *pci_dev)
4868 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4872 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4874 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4875 return rte_eth_dev_pci_generic_remove(pci_dev,
4878 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4881 static struct rte_pci_driver bnxt_rte_pmd = {
4882 .id_table = bnxt_pci_id_map,
4883 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4884 .probe = bnxt_pci_probe,
4885 .remove = bnxt_pci_remove,
4889 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4891 if (strcmp(dev->device->driver->name, drv->driver.name))
4897 bool is_bnxt_supported(struct rte_eth_dev *dev)
4899 return is_device_supported(dev, &bnxt_rte_pmd);
4902 RTE_INIT(bnxt_init_log)
4904 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4905 if (bnxt_logtype_driver >= 0)
4906 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4909 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4910 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4911 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");