drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15
  16 #include "bnxt.h"
  17 #include "bnxt_filter.h"
  18 #include "bnxt_hwrm.h"
  19 #include "bnxt_irq.h"
  20 #include "bnxt_ring.h"
  21 #include "bnxt_rxq.h"
  22 #include "bnxt_rxr.h"
  23 #include "bnxt_stats.h"
  24 #include "bnxt_txq.h"
  25 #include "bnxt_txr.h"
  26 #include "bnxt_vnic.h"
  27 #include "hsi_struct_def_dpdk.h"
  28 #include "bnxt_nvm_defs.h"
  29
  30 #define DRV_MODULE_NAME         "bnxt"
  31 static const char bnxt_version[] =
  32         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  33 int bnxt_logtype_driver;
  34
  35 #define PCI_VENDOR_ID_BROADCOM 0x14E4
  36
  37 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
  38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
  39 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
  40 #define BROADCOM_DEV_ID_57414_VF 0x16c1
  41 #define BROADCOM_DEV_ID_57301 0x16c8
  42 #define BROADCOM_DEV_ID_57302 0x16c9
  43 #define BROADCOM_DEV_ID_57304_PF 0x16ca
  44 #define BROADCOM_DEV_ID_57304_VF 0x16cb
  45 #define BROADCOM_DEV_ID_57417_MF 0x16cc
  46 #define BROADCOM_DEV_ID_NS2 0x16cd
  47 #define BROADCOM_DEV_ID_57311 0x16ce
  48 #define BROADCOM_DEV_ID_57312 0x16cf
  49 #define BROADCOM_DEV_ID_57402 0x16d0
  50 #define BROADCOM_DEV_ID_57404 0x16d1
  51 #define BROADCOM_DEV_ID_57406_PF 0x16d2
  52 #define BROADCOM_DEV_ID_57406_VF 0x16d3
  53 #define BROADCOM_DEV_ID_57402_MF 0x16d4
  54 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
  55 #define BROADCOM_DEV_ID_57412 0x16d6
  56 #define BROADCOM_DEV_ID_57414 0x16d7
  57 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
  58 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
  59 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
  60 #define BROADCOM_DEV_ID_57412_MF 0x16de
  61 #define BROADCOM_DEV_ID_57314 0x16df
  62 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
  63 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
  64 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
  65 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
  66 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
  67 #define BROADCOM_DEV_ID_57404_MF 0x16e7
  68 #define BROADCOM_DEV_ID_57406_MF 0x16e8
  69 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
  70 #define BROADCOM_DEV_ID_57407_MF 0x16ea
  71 #define BROADCOM_DEV_ID_57414_MF 0x16ec
  72 #define BROADCOM_DEV_ID_57416_MF 0x16ee
  73 #define BROADCOM_DEV_ID_57508 0x1750
  74 #define BROADCOM_DEV_ID_57504 0x1751
  75 #define BROADCOM_DEV_ID_57502 0x1752
  76 #define BROADCOM_DEV_ID_57500_VF1 0x1806
  77 #define BROADCOM_DEV_ID_57500_VF2 0x1807
  78 #define BROADCOM_DEV_ID_58802 0xd802
  79 #define BROADCOM_DEV_ID_58804 0xd804
  80 #define BROADCOM_DEV_ID_58808 0x16f0
  81 #define BROADCOM_DEV_ID_58802_VF 0xd800
  82
  83 static const struct rte_pci_id bnxt_pci_id_map[] = {
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  85                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  87                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  95         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  96         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  97         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  98         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  99         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
 100         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
 101         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
 102         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
 103         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
 104         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
 105         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
 106         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
 107         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
 108         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
 109         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
 110         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
 111         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
 112         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
 113         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
 114         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
 115         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
 116         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
 117         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
 118         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
 119         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
 120         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
 121         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
 122         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
 123         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
 124         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
 125         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
 126         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
 127         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
 128         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
 129         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
 130         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
 131         { .vendor_id = 0, /* sentinel */ },
 132 };
 133
 134 #define BNXT_ETH_RSS_SUPPORT (  \
 135         ETH_RSS_IPV4 |          \
 136         ETH_RSS_NONFRAG_IPV4_TCP |      \
 137         ETH_RSS_NONFRAG_IPV4_UDP |      \
 138         ETH_RSS_IPV6 |          \
 139         ETH_RSS_NONFRAG_IPV6_TCP |      \
 140         ETH_RSS_NONFRAG_IPV6_UDP)
 141
 142 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
 143                                      DEV_TX_OFFLOAD_IPV4_CKSUM | \
 144                                      DEV_TX_OFFLOAD_TCP_CKSUM | \
 145                                      DEV_TX_OFFLOAD_UDP_CKSUM | \
 146                                      DEV_TX_OFFLOAD_TCP_TSO | \
 147                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
 148                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
 149                                      DEV_TX_OFFLOAD_GRE_TNL_TSO | \
 150                                      DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
 151                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
 152                                      DEV_TX_OFFLOAD_QINQ_INSERT | \
 153                                      DEV_TX_OFFLOAD_MULTI_SEGS)
 154
 155 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
 156                                      DEV_RX_OFFLOAD_VLAN_STRIP | \
 157                                      DEV_RX_OFFLOAD_IPV4_CKSUM | \
 158                                      DEV_RX_OFFLOAD_UDP_CKSUM | \
 159                                      DEV_RX_OFFLOAD_TCP_CKSUM | \
 160                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
 161                                      DEV_RX_OFFLOAD_JUMBO_FRAME | \
 162                                      DEV_RX_OFFLOAD_KEEP_CRC | \
 163                                      DEV_RX_OFFLOAD_VLAN_EXTEND | \
 164                                      DEV_RX_OFFLOAD_TCP_LRO | \
 165                                      DEV_RX_OFFLOAD_SCATTER)
 166
 167 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 168 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
 169 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu);
 170 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 171 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 172 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 173 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 174
 175 int is_bnxt_in_error(struct bnxt *bp)
 176 {
 177         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 178                 return -EIO;
 179         if (bp->flags & BNXT_FLAG_FW_RESET)
 180                 return -EBUSY;
 181
 182         return 0;
 183 }
 184
 185 /***********************/
 186
 187 /*
 188  * High level utility functions
 189  */
 190
 191 uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 192 {
 193         if (!BNXT_CHIP_THOR(bp))
 194                 return 1;
 195
 196         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 197                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 198                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 199 }
 200
 201 static uint16_t  bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 202 {
 203         if (!BNXT_CHIP_THOR(bp))
 204                 return HW_HASH_INDEX_SIZE;
 205
 206         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 207 }
 208
 209 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 210 {
 211         bnxt_free_filter_mem(bp);
 212         bnxt_free_vnic_attributes(bp);
 213         bnxt_free_vnic_mem(bp);
 214
 215         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 216          * If the number of rings change across fw update,
 217          * we don't have much choice except to warn the user.
 218          */
 219         if (!reconfig) {
 220                 bnxt_free_stats(bp);
 221                 bnxt_free_tx_rings(bp);
 222                 bnxt_free_rx_rings(bp);
 223         }
 224         bnxt_free_async_cp_ring(bp);
 225         bnxt_free_rxtx_nq_ring(bp);
 226 }
 227
 228 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 229 {
 230         int rc;
 231
 232         rc = bnxt_alloc_ring_grps(bp);
 233         if (rc)
 234                 goto alloc_mem_err;
 235
 236         rc = bnxt_alloc_async_ring_struct(bp);
 237         if (rc)
 238                 goto alloc_mem_err;
 239
 240         rc = bnxt_alloc_vnic_mem(bp);
 241         if (rc)
 242                 goto alloc_mem_err;
 243
 244         rc = bnxt_alloc_vnic_attributes(bp);
 245         if (rc)
 246                 goto alloc_mem_err;
 247
 248         rc = bnxt_alloc_filter_mem(bp);
 249         if (rc)
 250                 goto alloc_mem_err;
 251
 252         rc = bnxt_alloc_async_cp_ring(bp);
 253         if (rc)
 254                 goto alloc_mem_err;
 255
 256         rc = bnxt_alloc_rxtx_nq_ring(bp);
 257         if (rc)
 258                 goto alloc_mem_err;
 259
 260         return 0;
 261
 262 alloc_mem_err:
 263         bnxt_free_mem(bp, reconfig);
 264         return rc;
 265 }
 266
 267 static int bnxt_init_chip(struct bnxt *bp)
 268 {
 269         struct bnxt_rx_queue *rxq;
 270         struct rte_eth_link new;
 271         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 272         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 273         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 274         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 275         uint32_t intr_vector = 0;
 276         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 277         uint32_t vec = BNXT_MISC_VEC_ID;
 278         unsigned int i, j;
 279         int rc;
 280
 281         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 282                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 283                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 284                 bp->flags |= BNXT_FLAG_JUMBO;
 285         } else {
 286                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 287                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 288                 bp->flags &= ~BNXT_FLAG_JUMBO;
 289         }
 290
 291         /* THOR does not support ring groups.
 292          * But we will use the array to save RSS context IDs.
 293          */
 294         if (BNXT_CHIP_THOR(bp))
 295                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 296
 297         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 298         if (rc) {
 299                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 300                 goto err_out;
 301         }
 302
 303         rc = bnxt_alloc_hwrm_rings(bp);
 304         if (rc) {
 305                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 306                 goto err_out;
 307         }
 308
 309         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 310         if (rc) {
 311                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 312                 goto err_out;
 313         }
 314
 315         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 316                 goto skip_cosq_cfg;
 317
 318         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 319                 if (bp->rx_cos_queue[i].id != 0xff) {
 320                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 321
 322                         if (!vnic) {
 323                                 PMD_DRV_LOG(ERR,
 324                                             "Num pools more than FW profile\n");
 325                                 rc = -EINVAL;
 326                                 goto err_out;
 327                         }
 328                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 329                         bp->rx_cosq_cnt++;
 330                 }
 331         }
 332
 333 skip_cosq_cfg:
 334         rc = bnxt_mq_rx_configure(bp);
 335         if (rc) {
 336                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 337                 goto err_out;
 338         }
 339
 340         /* VNIC configuration */
 341         for (i = 0; i < bp->nr_vnics; i++) {
 342                 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 343                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
 344
 345                 rc = bnxt_vnic_grp_alloc(bp, vnic);
 346                 if (rc)
 347                         goto err_out;
 348
 349                 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 350                             i, vnic, vnic->fw_grp_ids);
 351
 352                 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 353                 if (rc) {
 354                         PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
 355                                 i, rc);
 356                         goto err_out;
 357                 }
 358
 359                 /* Alloc RSS context only if RSS mode is enabled */
 360                 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 361                         int j, nr_ctxs = bnxt_rss_ctxts(bp);
 362
 363                         rc = 0;
 364                         for (j = 0; j < nr_ctxs; j++) {
 365                                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 366                                 if (rc)
 367                                         break;
 368                         }
 369                         if (rc) {
 370                                 PMD_DRV_LOG(ERR,
 371                                   "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 372                                   i, j, rc);
 373                                 goto err_out;
 374                         }
 375                         vnic->num_lb_ctxts = nr_ctxs;
 376                 }
 377
 378                 /*
 379                  * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 380                  * setting is not available at this time, it will not be
 381                  * configured correctly in the CFA.
 382                  */
 383                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 384                         vnic->vlan_strip = true;
 385                 else
 386                         vnic->vlan_strip = false;
 387
 388                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 389                 if (rc) {
 390                         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 391                                 i, rc);
 392                         goto err_out;
 393                 }
 394
 395                 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 396                 if (rc) {
 397                         PMD_DRV_LOG(ERR,
 398                                 "HWRM vnic %d filter failure rc: %x\n",
 399                                 i, rc);
 400                         goto err_out;
 401                 }
 402
 403                 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 404                         rxq = bp->eth_dev->data->rx_queues[j];
 405
 406                         PMD_DRV_LOG(DEBUG,
 407                                     "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 408                                     j, rxq->vnic, rxq->vnic->fw_grp_ids);
 409
 410                         if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 411                                 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 412                 }
 413
 414                 rc = bnxt_vnic_rss_configure(bp, vnic);
 415                 if (rc) {
 416                         PMD_DRV_LOG(ERR,
 417                                     "HWRM vnic set RSS failure rc: %x\n", rc);
 418                         goto err_out;
 419                 }
 420
 421                 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 422
 423                 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
 424                     DEV_RX_OFFLOAD_TCP_LRO)
 425                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 426                 else
 427                         bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 428         }
 429         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 430         if (rc) {
 431                 PMD_DRV_LOG(ERR,
 432                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 433                 goto err_out;
 434         }
 435
 436         /* check and configure queue intr-vector mapping */
 437         if ((rte_intr_cap_multiple(intr_handle) ||
 438              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 439             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 440                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 441                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 442                 if (intr_vector > bp->rx_cp_nr_rings) {
 443                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 444                                         bp->rx_cp_nr_rings);
 445                         return -ENOTSUP;
 446                 }
 447                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 448                 if (rc)
 449                         return rc;
 450         }
 451
 452         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 453                 intr_handle->intr_vec =
 454                         rte_zmalloc("intr_vec",
 455                                     bp->eth_dev->data->nb_rx_queues *
 456                                     sizeof(int), 0);
 457                 if (intr_handle->intr_vec == NULL) {
 458                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 459                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 460                         rc = -ENOMEM;
 461                         goto err_disable;
 462                 }
 463                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 464                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 465                          intr_handle->intr_vec, intr_handle->nb_efd,
 466                         intr_handle->max_intr);
 467                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 468                      queue_id++) {
 469                         intr_handle->intr_vec[queue_id] =
 470                                                         vec + BNXT_RX_VEC_START;
 471                         if (vec < base + intr_handle->nb_efd - 1)
 472                                 vec++;
 473                 }
 474         }
 475
 476         /* enable uio/vfio intr/eventfd mapping */
 477         rc = rte_intr_enable(intr_handle);
 478         if (rc)
 479                 goto err_free;
 480
 481         rc = bnxt_get_hwrm_link_config(bp, &new);
 482         if (rc) {
 483                 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
 484                 goto err_free;
 485         }
 486
 487         if (!bp->link_info.link_up) {
 488                 rc = bnxt_set_hwrm_link_config(bp, true);
 489                 if (rc) {
 490                         PMD_DRV_LOG(ERR,
 491                                 "HWRM link config failure rc: %x\n", rc);
 492                         goto err_free;
 493                 }
 494         }
 495         bnxt_print_link_info(bp->eth_dev);
 496
 497         return 0;
 498
 499 err_free:
 500         rte_free(intr_handle->intr_vec);
 501 err_disable:
 502         rte_intr_efd_disable(intr_handle);
 503 err_out:
 504         /* Some of the error status returned by FW may not be from errno.h */
 505         if (rc > 0)
 506                 rc = -EIO;
 507
 508         return rc;
 509 }
 510
 511 static int bnxt_shutdown_nic(struct bnxt *bp)
 512 {
 513         bnxt_free_all_hwrm_resources(bp);
 514         bnxt_free_all_filters(bp);
 515         bnxt_free_all_vnics(bp);
 516         return 0;
 517 }
 518
 519 static int bnxt_init_nic(struct bnxt *bp)
 520 {
 521         int rc;
 522
 523         if (BNXT_HAS_RING_GRPS(bp)) {
 524                 rc = bnxt_init_ring_grps(bp);
 525                 if (rc)
 526                         return rc;
 527         }
 528
 529         bnxt_init_vnics(bp);
 530         bnxt_init_filters(bp);
 531
 532         return 0;
 533 }
 534
 535 /*
 536  * Device configuration and status function
 537  */
 538
 539 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 540                                 struct rte_eth_dev_info *dev_info)
 541 {
 542         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 543         struct bnxt *bp = eth_dev->data->dev_private;
 544         uint16_t max_vnics, i, j, vpool, vrxq;
 545         unsigned int max_rx_rings;
 546         int rc;
 547
 548         rc = is_bnxt_in_error(bp);
 549         if (rc)
 550                 return rc;
 551
 552         /* MAC Specifics */
 553         dev_info->max_mac_addrs = bp->max_l2_ctx;
 554         dev_info->max_hash_mac_addrs = 0;
 555
 556         /* PF/VF specifics */
 557         if (BNXT_PF(bp))
 558                 dev_info->max_vfs = pdev->max_vfs;
 559
 560         max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
 561         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 562         dev_info->max_rx_queues = max_rx_rings;
 563         dev_info->max_tx_queues = max_rx_rings;
 564         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 565         dev_info->hash_key_size = 40;
 566         max_vnics = bp->max_vnics;
 567
 568         /* MTU specifics */
 569         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 570         dev_info->max_mtu = BNXT_MAX_MTU;
 571
 572         /* Fast path specifics */
 573         dev_info->min_rx_bufsize = 1;
 574         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 575
 576         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 577         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 578                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 579         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 580         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 581
 582         /* *INDENT-OFF* */
 583         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 584                 .rx_thresh = {
 585                         .pthresh = 8,
 586                         .hthresh = 8,
 587                         .wthresh = 0,
 588                 },
 589                 .rx_free_thresh = 32,
 590                 /* If no descriptors available, pkts are dropped by default */
 591                 .rx_drop_en = 1,
 592         };
 593
 594         dev_info->default_txconf = (struct rte_eth_txconf) {
 595                 .tx_thresh = {
 596                         .pthresh = 32,
 597                         .hthresh = 0,
 598                         .wthresh = 0,
 599                 },
 600                 .tx_free_thresh = 32,
 601                 .tx_rs_thresh = 32,
 602         };
 603         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 604
 605         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 606         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 607         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 608         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 609         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 610
 611         /* *INDENT-ON* */
 612
 613         /*
 614          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 615          *       need further investigation.
 616          */
 617
 618         /* VMDq resources */
 619         vpool = 64; /* ETH_64_POOLS */
 620         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 621         for (i = 0; i < 4; vpool >>= 1, i++) {
 622                 if (max_vnics > vpool) {
 623                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 624                                 if (dev_info->max_rx_queues > vrxq) {
 625                                         if (vpool > vrxq)
 626                                                 vpool = vrxq;
 627                                         goto found;
 628                                 }
 629                         }
 630                         /* Not enough resources to support VMDq */
 631                         break;
 632                 }
 633         }
 634         /* Not enough resources to support VMDq */
 635         vpool = 0;
 636         vrxq = 0;
 637 found:
 638         dev_info->max_vmdq_pools = vpool;
 639         dev_info->vmdq_queue_num = vrxq;
 640
 641         dev_info->vmdq_pool_base = 0;
 642         dev_info->vmdq_queue_base = 0;
 643
 644         return 0;
 645 }
 646
 647 /* Configure the device based on the configuration provided */
 648 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 649 {
 650         struct bnxt *bp = eth_dev->data->dev_private;
 651         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 652         int rc;
 653
 654         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 655         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 656         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 657         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 658
 659         rc = is_bnxt_in_error(bp);
 660         if (rc)
 661                 return rc;
 662
 663         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 664                 rc = bnxt_hwrm_check_vf_rings(bp);
 665                 if (rc) {
 666                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 667                         return -ENOSPC;
 668                 }
 669
 670                 /* If a resource has already been allocated - in this case
 671                  * it is the async completion ring, free it. Reallocate it after
 672                  * resource reservation. This will ensure the resource counts
 673                  * are calculated correctly.
 674                  */
 675                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 676                         bnxt_disable_int(bp);
 677                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 678                 }
 679
 680                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 681                 if (rc) {
 682                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 683                         return -ENOSPC;
 684                 }
 685
 686                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 687                         rc = bnxt_alloc_async_cp_ring(bp);
 688                         if (rc)
 689                                 return rc;
 690                         bnxt_enable_int(bp);
 691                 }
 692         } else {
 693                 /* legacy driver needs to get updated values */
 694                 rc = bnxt_hwrm_func_qcaps(bp);
 695                 if (rc) {
 696                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
 697                         return rc;
 698                 }
 699         }
 700
 701         /* Inherit new configurations */
 702         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
 703             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
 704             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
 705                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
 706             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
 707             bp->max_stat_ctx)
 708                 goto resource_error;
 709
 710         if (BNXT_HAS_RING_GRPS(bp) &&
 711             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
 712                 goto resource_error;
 713
 714         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
 715             bp->max_vnics < eth_dev->data->nb_rx_queues)
 716                 goto resource_error;
 717
 718         bp->rx_cp_nr_rings = bp->rx_nr_rings;
 719         bp->tx_cp_nr_rings = bp->tx_nr_rings;
 720
 721         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 722                 eth_dev->data->mtu =
 723                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 724                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
 725                         BNXT_NUM_VLANS;
 726                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
 727         }
 728         return 0;
 729
 730 resource_error:
 731         PMD_DRV_LOG(ERR,
 732                     "Insufficient resources to support requested config\n");
 733         PMD_DRV_LOG(ERR,
 734                     "Num Queues Requested: Tx %d, Rx %d\n",
 735                     eth_dev->data->nb_tx_queues,
 736                     eth_dev->data->nb_rx_queues);
 737         PMD_DRV_LOG(ERR,
 738                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
 739                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
 740                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
 741         return -ENOSPC;
 742 }
 743
 744 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
 745 {
 746         struct rte_eth_link *link = &eth_dev->data->dev_link;
 747
 748         if (link->link_status)
 749                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
 750                         eth_dev->data->port_id,
 751                         (uint32_t)link->link_speed,
 752                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
 753                         ("full-duplex") : ("half-duplex\n"));
 754         else
 755                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
 756                         eth_dev->data->port_id);
 757 }
 758
 759 /*
 760  * Determine whether the current configuration requires support for scattered
 761  * receive; return 1 if scattered receive is required and 0 if not.
 762  */
 763 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
 764 {
 765         uint16_t buf_size;
 766         int i;
 767
 768         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
 769                 return 1;
 770
 771         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 772                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
 773
 774                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
 775                                       RTE_PKTMBUF_HEADROOM);
 776                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
 777                         return 1;
 778         }
 779         return 0;
 780 }
 781
 782 static eth_rx_burst_t
 783 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
 784 {
 785 #ifdef RTE_ARCH_X86
 786 #ifndef RTE_LIBRTE_IEEE1588
 787         /*
 788          * Vector mode receive can be enabled only if scatter rx is not
 789          * in use and rx offloads are limited to VLAN stripping and
 790          * CRC stripping.
 791          */
 792         if (!eth_dev->data->scattered_rx &&
 793             !(eth_dev->data->dev_conf.rxmode.offloads &
 794               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
 795                 DEV_RX_OFFLOAD_KEEP_CRC |
 796                 DEV_RX_OFFLOAD_JUMBO_FRAME |
 797                 DEV_RX_OFFLOAD_IPV4_CKSUM |
 798                 DEV_RX_OFFLOAD_UDP_CKSUM |
 799                 DEV_RX_OFFLOAD_TCP_CKSUM |
 800                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 801                 DEV_RX_OFFLOAD_VLAN_FILTER))) {
 802                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
 803                             eth_dev->data->port_id);
 804                 return bnxt_recv_pkts_vec;
 805         }
 806         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
 807                     eth_dev->data->port_id);
 808         PMD_DRV_LOG(INFO,
 809                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
 810                     eth_dev->data->port_id,
 811                     eth_dev->data->scattered_rx,
 812                     eth_dev->data->dev_conf.rxmode.offloads);
 813 #endif
 814 #endif
 815         return bnxt_recv_pkts;
 816 }
 817
 818 static eth_tx_burst_t
 819 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
 820 {
 821 #ifdef RTE_ARCH_X86
 822 #ifndef RTE_LIBRTE_IEEE1588
 823         /*
 824          * Vector mode transmit can be enabled only if not using scatter rx
 825          * or tx offloads.
 826          */
 827         if (!eth_dev->data->scattered_rx &&
 828             !eth_dev->data->dev_conf.txmode.offloads) {
 829                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
 830                             eth_dev->data->port_id);
 831                 return bnxt_xmit_pkts_vec;
 832         }
 833         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
 834                     eth_dev->data->port_id);
 835         PMD_DRV_LOG(INFO,
 836                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
 837                     eth_dev->data->port_id,
 838                     eth_dev->data->scattered_rx,
 839                     eth_dev->data->dev_conf.txmode.offloads);
 840 #endif
 841 #endif
 842         return bnxt_xmit_pkts;
 843 }
 844
 845 static int bnxt_handle_if_change_status(struct bnxt *bp)
 846 {
 847         int rc;
 848
 849         /* Since fw has undergone a reset and lost all contexts,
 850          * set fatal flag to not issue hwrm during cleanup
 851          */
 852         bp->flags |= BNXT_FLAG_FATAL_ERROR;
 853         bnxt_uninit_resources(bp, true);
 854
 855         /* clear fatal flag so that re-init happens */
 856         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
 857         rc = bnxt_init_resources(bp, true);
 858
 859         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
 860
 861         return rc;
 862 }
 863
 864 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
 865 {
 866         struct bnxt *bp = eth_dev->data->dev_private;
 867         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 868         int vlan_mask = 0;
 869         int rc;
 870
 871         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
 872                 PMD_DRV_LOG(ERR,
 873                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
 874                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
 875         }
 876
 877         bnxt_enable_int(bp);
 878         rc = bnxt_hwrm_if_change(bp, 1);
 879         if (!rc) {
 880                 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
 881                         rc = bnxt_handle_if_change_status(bp);
 882                         if (rc)
 883                                 return rc;
 884                 }
 885         }
 886
 887         rc = bnxt_init_chip(bp);
 888         if (rc)
 889                 goto error;
 890
 891         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
 892
 893         bnxt_link_update_op(eth_dev, 1);
 894
 895         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
 896                 vlan_mask |= ETH_VLAN_FILTER_MASK;
 897         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 898                 vlan_mask |= ETH_VLAN_STRIP_MASK;
 899         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
 900         if (rc)
 901                 goto error;
 902
 903         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
 904         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
 905
 906         bp->flags |= BNXT_FLAG_INIT_DONE;
 907         eth_dev->data->dev_started = 1;
 908         bp->dev_stopped = 0;
 909         bnxt_schedule_fw_health_check(bp);
 910         return 0;
 911
 912 error:
 913         bnxt_hwrm_if_change(bp, 0);
 914         bnxt_shutdown_nic(bp);
 915         bnxt_free_tx_mbufs(bp);
 916         bnxt_free_rx_mbufs(bp);
 917         return rc;
 918 }
 919
 920 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
 921 {
 922         struct bnxt *bp = eth_dev->data->dev_private;
 923         int rc = 0;
 924
 925         if (!bp->link_info.link_up)
 926                 rc = bnxt_set_hwrm_link_config(bp, true);
 927         if (!rc)
 928                 eth_dev->data->dev_link.link_status = 1;
 929
 930         bnxt_print_link_info(eth_dev);
 931         return rc;
 932 }
 933
 934 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
 935 {
 936         struct bnxt *bp = eth_dev->data->dev_private;
 937
 938         eth_dev->data->dev_link.link_status = 0;
 939         bnxt_set_hwrm_link_config(bp, false);
 940         bp->link_info.link_up = 0;
 941
 942         return 0;
 943 }
 944
 945 /* Unload the driver, release resources */
 946 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
 947 {
 948         struct bnxt *bp = eth_dev->data->dev_private;
 949         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 950         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 951
 952         eth_dev->data->dev_started = 0;
 953         /* Prevent crashes when queues are still in use */
 954         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
 955         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
 956
 957         bnxt_disable_int(bp);
 958
 959         /* disable uio/vfio intr/eventfd mapping */
 960         rte_intr_disable(intr_handle);
 961
 962         bnxt_cancel_fw_health_check(bp);
 963
 964         bp->flags &= ~BNXT_FLAG_INIT_DONE;
 965         if (bp->eth_dev->data->dev_started) {
 966                 /* TBD: STOP HW queues DMA */
 967                 eth_dev->data->dev_link.link_status = 0;
 968         }
 969         bnxt_dev_set_link_down_op(eth_dev);
 970         /* Wait for link to be reset and the async notification to process. */
 971         rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
 972
 973         /* Clean queue intr-vector mapping */
 974         rte_intr_efd_disable(intr_handle);
 975         if (intr_handle->intr_vec != NULL) {
 976                 rte_free(intr_handle->intr_vec);
 977                 intr_handle->intr_vec = NULL;
 978         }
 979
 980         bnxt_hwrm_port_clr_stats(bp);
 981         bnxt_free_tx_mbufs(bp);
 982         bnxt_free_rx_mbufs(bp);
 983         /* Process any remaining notifications in default completion queue */
 984         bnxt_int_handler(eth_dev);
 985         bnxt_shutdown_nic(bp);
 986         bnxt_hwrm_if_change(bp, 0);
 987         bp->dev_stopped = 1;
 988 }
 989
 990 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
 991 {
 992         struct bnxt *bp = eth_dev->data->dev_private;
 993
 994         if (bp->dev_stopped == 0)
 995                 bnxt_dev_stop_op(eth_dev);
 996
 997         if (eth_dev->data->mac_addrs != NULL) {
 998                 rte_free(eth_dev->data->mac_addrs);
 999                 eth_dev->data->mac_addrs = NULL;
1000         }
1001         if (bp->grp_info != NULL) {
1002                 rte_free(bp->grp_info);
1003                 bp->grp_info = NULL;
1004         }
1005
1006         bnxt_dev_uninit(eth_dev);
1007 }
1008
1009 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1010                                     uint32_t index)
1011 {
1012         struct bnxt *bp = eth_dev->data->dev_private;
1013         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1014         struct bnxt_vnic_info *vnic;
1015         struct bnxt_filter_info *filter, *temp_filter;
1016         uint32_t i;
1017
1018         if (is_bnxt_in_error(bp))
1019                 return;
1020
1021         /*
1022          * Loop through all VNICs from the specified filter flow pools to
1023          * remove the corresponding MAC addr filter
1024          */
1025         for (i = 0; i < bp->nr_vnics; i++) {
1026                 if (!(pool_mask & (1ULL << i)))
1027                         continue;
1028
1029                 vnic = &bp->vnic_info[i];
1030                 filter = STAILQ_FIRST(&vnic->filter);
1031                 while (filter) {
1032                         temp_filter = STAILQ_NEXT(filter, next);
1033                         if (filter->mac_index == index) {
1034                                 STAILQ_REMOVE(&vnic->filter, filter,
1035                                                 bnxt_filter_info, next);
1036                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1037                                 filter->mac_index = INVALID_MAC_INDEX;
1038                                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1039                                 STAILQ_INSERT_TAIL(&bp->free_filter_list,
1040                                                    filter, next);
1041                         }
1042                         filter = temp_filter;
1043                 }
1044         }
1045 }
1046
1047 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1048                                struct rte_ether_addr *mac_addr, uint32_t index)
1049 {
1050         struct bnxt_filter_info *filter;
1051         int rc = 0;
1052
1053         filter = STAILQ_FIRST(&vnic->filter);
1054         /* During bnxt_mac_addr_add_op, default MAC is
1055          * already programmed, so skip it. But, when
1056          * hw-vlan-filter is turned OFF from ON, default
1057          * MAC filter should be restored
1058          */
1059         if (filter->dflt)
1060                 return 0;
1061
1062         filter = bnxt_alloc_filter(bp);
1063         if (!filter) {
1064                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1065                 return -ENODEV;
1066         }
1067
1068         filter->mac_index = index;
1069         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1070          * if the MAC that's been programmed now is a different one, then,
1071          * copy that addr to filter->l2_addr
1072          */
1073         if (mac_addr)
1074                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1075         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1076
1077         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1078         if (!rc) {
1079                 if (filter->mac_index == 0) {
1080                         filter->dflt = true;
1081                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1082                 } else {
1083                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1084                 }
1085         } else {
1086                 filter->mac_index = INVALID_MAC_INDEX;
1087                 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
1088                 bnxt_free_filter(bp, filter);
1089         }
1090
1091         return rc;
1092 }
1093
1094 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1095                                 struct rte_ether_addr *mac_addr,
1096                                 uint32_t index, uint32_t pool)
1097 {
1098         struct bnxt *bp = eth_dev->data->dev_private;
1099         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1100         struct bnxt_filter_info *filter;
1101         int rc = 0;
1102
1103         rc = is_bnxt_in_error(bp);
1104         if (rc)
1105                 return rc;
1106
1107         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1108                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1109                 return -ENOTSUP;
1110         }
1111
1112         if (!vnic) {
1113                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1114                 return -EINVAL;
1115         }
1116         /* Attach requested MAC address to the new l2_filter */
1117         STAILQ_FOREACH(filter, &vnic->filter, next) {
1118                 if (filter->mac_index == index) {
1119                         PMD_DRV_LOG(ERR,
1120                                 "MAC addr already existed for pool %d\n", pool);
1121                         return 0;
1122                 }
1123         }
1124
1125         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index);
1126
1127         return rc;
1128 }
1129
1130 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1131 {
1132         int rc = 0;
1133         struct bnxt *bp = eth_dev->data->dev_private;
1134         struct rte_eth_link new;
1135         unsigned int cnt = BNXT_LINK_WAIT_CNT;
1136
1137         rc = is_bnxt_in_error(bp);
1138         if (rc)
1139                 return rc;
1140
1141         memset(&new, 0, sizeof(new));
1142         do {
1143                 /* Retrieve link info from hardware */
1144                 rc = bnxt_get_hwrm_link_config(bp, &new);
1145                 if (rc) {
1146                         new.link_speed = ETH_LINK_SPEED_100M;
1147                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1148                         PMD_DRV_LOG(ERR,
1149                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1150                         goto out;
1151                 }
1152
1153                 if (!wait_to_complete || new.link_status)
1154                         break;
1155
1156                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1157         } while (cnt--);
1158
1159 out:
1160         /* Timed out or success */
1161         if (new.link_status != eth_dev->data->dev_link.link_status ||
1162         new.link_speed != eth_dev->data->dev_link.link_speed) {
1163                 rte_eth_linkstatus_set(eth_dev, &new);
1164
1165                 _rte_eth_dev_callback_process(eth_dev,
1166                                               RTE_ETH_EVENT_INTR_LSC,
1167                                               NULL);
1168
1169                 bnxt_print_link_info(eth_dev);
1170         }
1171
1172         return rc;
1173 }
1174
1175 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1176 {
1177         struct bnxt *bp = eth_dev->data->dev_private;
1178         struct bnxt_vnic_info *vnic;
1179         uint32_t old_flags;
1180         int rc;
1181
1182         rc = is_bnxt_in_error(bp);
1183         if (rc)
1184                 return rc;
1185
1186         if (bp->vnic_info == NULL)
1187                 return 0;
1188
1189         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1190
1191         old_flags = vnic->flags;
1192         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1193         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1194         if (rc != 0)
1195                 vnic->flags = old_flags;
1196
1197         return rc;
1198 }
1199
1200 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1201 {
1202         struct bnxt *bp = eth_dev->data->dev_private;
1203         struct bnxt_vnic_info *vnic;
1204         uint32_t old_flags;
1205         int rc;
1206
1207         rc = is_bnxt_in_error(bp);
1208         if (rc)
1209                 return rc;
1210
1211         if (bp->vnic_info == NULL)
1212                 return 0;
1213
1214         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1215
1216         old_flags = vnic->flags;
1217         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1218         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1219         if (rc != 0)
1220                 vnic->flags = old_flags;
1221
1222         return rc;
1223 }
1224
1225 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1226 {
1227         struct bnxt *bp = eth_dev->data->dev_private;
1228         struct bnxt_vnic_info *vnic;
1229         uint32_t old_flags;
1230         int rc;
1231
1232         rc = is_bnxt_in_error(bp);
1233         if (rc)
1234                 return rc;
1235
1236         if (bp->vnic_info == NULL)
1237                 return 0;
1238
1239         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1240
1241         old_flags = vnic->flags;
1242         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1243         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1244         if (rc != 0)
1245                 vnic->flags = old_flags;
1246
1247         return rc;
1248 }
1249
1250 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1251 {
1252         struct bnxt *bp = eth_dev->data->dev_private;
1253         struct bnxt_vnic_info *vnic;
1254         uint32_t old_flags;
1255         int rc;
1256
1257         rc = is_bnxt_in_error(bp);
1258         if (rc)
1259                 return rc;
1260
1261         if (bp->vnic_info == NULL)
1262                 return 0;
1263
1264         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1265
1266         old_flags = vnic->flags;
1267         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1268         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1269         if (rc != 0)
1270                 vnic->flags = old_flags;
1271
1272         return rc;
1273 }
1274
1275 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1276 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1277 {
1278         if (qid >= bp->rx_nr_rings)
1279                 return NULL;
1280
1281         return bp->eth_dev->data->rx_queues[qid];
1282 }
1283
1284 /* Return rxq corresponding to a given rss table ring/group ID. */
1285 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1286 {
1287         struct bnxt_rx_queue *rxq;
1288         unsigned int i;
1289
1290         if (!BNXT_HAS_RING_GRPS(bp)) {
1291                 for (i = 0; i < bp->rx_nr_rings; i++) {
1292                         rxq = bp->eth_dev->data->rx_queues[i];
1293                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1294                                 return rxq->index;
1295                 }
1296         } else {
1297                 for (i = 0; i < bp->rx_nr_rings; i++) {
1298                         if (bp->grp_info[i].fw_grp_id == fwr)
1299                                 return i;
1300                 }
1301         }
1302
1303         return INVALID_HW_RING_ID;
1304 }
1305
1306 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1307                             struct rte_eth_rss_reta_entry64 *reta_conf,
1308                             uint16_t reta_size)
1309 {
1310         struct bnxt *bp = eth_dev->data->dev_private;
1311         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1312         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1313         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1314         uint16_t idx, sft;
1315         int i, rc;
1316
1317         rc = is_bnxt_in_error(bp);
1318         if (rc)
1319                 return rc;
1320
1321         if (!vnic->rss_table)
1322                 return -EINVAL;
1323
1324         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1325                 return -EINVAL;
1326
1327         if (reta_size != tbl_size) {
1328                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1329                         "(%d) must equal the size supported by the hardware "
1330                         "(%d)\n", reta_size, tbl_size);
1331                 return -EINVAL;
1332         }
1333
1334         for (i = 0; i < reta_size; i++) {
1335                 struct bnxt_rx_queue *rxq;
1336
1337                 idx = i / RTE_RETA_GROUP_SIZE;
1338                 sft = i % RTE_RETA_GROUP_SIZE;
1339
1340                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1341                         continue;
1342
1343                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1344                 if (!rxq) {
1345                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1346                         return -EINVAL;
1347                 }
1348
1349                 if (BNXT_CHIP_THOR(bp)) {
1350                         vnic->rss_table[i * 2] =
1351                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1352                         vnic->rss_table[i * 2 + 1] =
1353                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1354                 } else {
1355                         vnic->rss_table[i] =
1356                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1357                 }
1358
1359                 vnic->rss_table[i] =
1360                     vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1361         }
1362
1363         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1364         return 0;
1365 }
1366
1367 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1368                               struct rte_eth_rss_reta_entry64 *reta_conf,
1369                               uint16_t reta_size)
1370 {
1371         struct bnxt *bp = eth_dev->data->dev_private;
1372         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1373         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1374         uint16_t idx, sft, i;
1375         int rc;
1376
1377         rc = is_bnxt_in_error(bp);
1378         if (rc)
1379                 return rc;
1380
1381         /* Retrieve from the default VNIC */
1382         if (!vnic)
1383                 return -EINVAL;
1384         if (!vnic->rss_table)
1385                 return -EINVAL;
1386
1387         if (reta_size != tbl_size) {
1388                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1389                         "(%d) must equal the size supported by the hardware "
1390                         "(%d)\n", reta_size, tbl_size);
1391                 return -EINVAL;
1392         }
1393
1394         for (idx = 0, i = 0; i < reta_size; i++) {
1395                 idx = i / RTE_RETA_GROUP_SIZE;
1396                 sft = i % RTE_RETA_GROUP_SIZE;
1397
1398                 if (reta_conf[idx].mask & (1ULL << sft)) {
1399                         uint16_t qid;
1400
1401                         if (BNXT_CHIP_THOR(bp))
1402                                 qid = bnxt_rss_to_qid(bp,
1403                                                       vnic->rss_table[i * 2]);
1404                         else
1405                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1406
1407                         if (qid == INVALID_HW_RING_ID) {
1408                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1409                                 return -EINVAL;
1410                         }
1411                         reta_conf[idx].reta[sft] = qid;
1412                 }
1413         }
1414
1415         return 0;
1416 }
1417
1418 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1419                                    struct rte_eth_rss_conf *rss_conf)
1420 {
1421         struct bnxt *bp = eth_dev->data->dev_private;
1422         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1423         struct bnxt_vnic_info *vnic;
1424         int rc;
1425
1426         rc = is_bnxt_in_error(bp);
1427         if (rc)
1428                 return rc;
1429
1430         /*
1431          * If RSS enablement were different than dev_configure,
1432          * then return -EINVAL
1433          */
1434         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1435                 if (!rss_conf->rss_hf)
1436                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1437         } else {
1438                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1439                         return -EINVAL;
1440         }
1441
1442         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1443         memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1444
1445         /* Update the default RSS VNIC(s) */
1446         vnic = &bp->vnic_info[0];
1447         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1448
1449         /*
1450          * If hashkey is not specified, use the previously configured
1451          * hashkey
1452          */
1453         if (!rss_conf->rss_key)
1454                 goto rss_config;
1455
1456         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1457                 PMD_DRV_LOG(ERR,
1458                             "Invalid hashkey length, should be 16 bytes\n");
1459                 return -EINVAL;
1460         }
1461         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1462
1463 rss_config:
1464         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1465         return 0;
1466 }
1467
1468 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1469                                      struct rte_eth_rss_conf *rss_conf)
1470 {
1471         struct bnxt *bp = eth_dev->data->dev_private;
1472         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1473         int len, rc;
1474         uint32_t hash_types;
1475
1476         rc = is_bnxt_in_error(bp);
1477         if (rc)
1478                 return rc;
1479
1480         /* RSS configuration is the same for all VNICs */
1481         if (vnic && vnic->rss_hash_key) {
1482                 if (rss_conf->rss_key) {
1483                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1484                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1485                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1486                 }
1487
1488                 hash_types = vnic->hash_type;
1489                 rss_conf->rss_hf = 0;
1490                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1491                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1492                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1493                 }
1494                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1495                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1496                         hash_types &=
1497                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1498                 }
1499                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1500                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1501                         hash_types &=
1502                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1503                 }
1504                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1505                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1506                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1507                 }
1508                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1509                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1510                         hash_types &=
1511                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1512                 }
1513                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1514                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1515                         hash_types &=
1516                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1517                 }
1518                 if (hash_types) {
1519                         PMD_DRV_LOG(ERR,
1520                                 "Unknwon RSS config from firmware (%08x), RSS disabled",
1521                                 vnic->hash_type);
1522                         return -ENOTSUP;
1523                 }
1524         } else {
1525                 rss_conf->rss_hf = 0;
1526         }
1527         return 0;
1528 }
1529
1530 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1531                                struct rte_eth_fc_conf *fc_conf)
1532 {
1533         struct bnxt *bp = dev->data->dev_private;
1534         struct rte_eth_link link_info;
1535         int rc;
1536
1537         rc = is_bnxt_in_error(bp);
1538         if (rc)
1539                 return rc;
1540
1541         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1542         if (rc)
1543                 return rc;
1544
1545         memset(fc_conf, 0, sizeof(*fc_conf));
1546         if (bp->link_info.auto_pause)
1547                 fc_conf->autoneg = 1;
1548         switch (bp->link_info.pause) {
1549         case 0:
1550                 fc_conf->mode = RTE_FC_NONE;
1551                 break;
1552         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1553                 fc_conf->mode = RTE_FC_TX_PAUSE;
1554                 break;
1555         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1556                 fc_conf->mode = RTE_FC_RX_PAUSE;
1557                 break;
1558         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1559                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1560                 fc_conf->mode = RTE_FC_FULL;
1561                 break;
1562         }
1563         return 0;
1564 }
1565
1566 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1567                                struct rte_eth_fc_conf *fc_conf)
1568 {
1569         struct bnxt *bp = dev->data->dev_private;
1570         int rc;
1571
1572         rc = is_bnxt_in_error(bp);
1573         if (rc)
1574                 return rc;
1575
1576         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1577                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1578                 return -ENOTSUP;
1579         }
1580
1581         switch (fc_conf->mode) {
1582         case RTE_FC_NONE:
1583                 bp->link_info.auto_pause = 0;
1584                 bp->link_info.force_pause = 0;
1585                 break;
1586         case RTE_FC_RX_PAUSE:
1587                 if (fc_conf->autoneg) {
1588                         bp->link_info.auto_pause =
1589                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1590                         bp->link_info.force_pause = 0;
1591                 } else {
1592                         bp->link_info.auto_pause = 0;
1593                         bp->link_info.force_pause =
1594                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1595                 }
1596                 break;
1597         case RTE_FC_TX_PAUSE:
1598                 if (fc_conf->autoneg) {
1599                         bp->link_info.auto_pause =
1600                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1601                         bp->link_info.force_pause = 0;
1602                 } else {
1603                         bp->link_info.auto_pause = 0;
1604                         bp->link_info.force_pause =
1605                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1606                 }
1607                 break;
1608         case RTE_FC_FULL:
1609                 if (fc_conf->autoneg) {
1610                         bp->link_info.auto_pause =
1611                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1612                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1613                         bp->link_info.force_pause = 0;
1614                 } else {
1615                         bp->link_info.auto_pause = 0;
1616                         bp->link_info.force_pause =
1617                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1618                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1619                 }
1620                 break;
1621         }
1622         return bnxt_set_hwrm_link_config(bp, true);
1623 }
1624
1625 /* Add UDP tunneling port */
1626 static int
1627 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1628                          struct rte_eth_udp_tunnel *udp_tunnel)
1629 {
1630         struct bnxt *bp = eth_dev->data->dev_private;
1631         uint16_t tunnel_type = 0;
1632         int rc = 0;
1633
1634         rc = is_bnxt_in_error(bp);
1635         if (rc)
1636                 return rc;
1637
1638         switch (udp_tunnel->prot_type) {
1639         case RTE_TUNNEL_TYPE_VXLAN:
1640                 if (bp->vxlan_port_cnt) {
1641                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1642                                 udp_tunnel->udp_port);
1643                         if (bp->vxlan_port != udp_tunnel->udp_port) {
1644                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1645                                 return -ENOSPC;
1646                         }
1647                         bp->vxlan_port_cnt++;
1648                         return 0;
1649                 }
1650                 tunnel_type =
1651                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1652                 bp->vxlan_port_cnt++;
1653                 break;
1654         case RTE_TUNNEL_TYPE_GENEVE:
1655                 if (bp->geneve_port_cnt) {
1656                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1657                                 udp_tunnel->udp_port);
1658                         if (bp->geneve_port != udp_tunnel->udp_port) {
1659                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1660                                 return -ENOSPC;
1661                         }
1662                         bp->geneve_port_cnt++;
1663                         return 0;
1664                 }
1665                 tunnel_type =
1666                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1667                 bp->geneve_port_cnt++;
1668                 break;
1669         default:
1670                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1671                 return -ENOTSUP;
1672         }
1673         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1674                                              tunnel_type);
1675         return rc;
1676 }
1677
1678 static int
1679 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1680                          struct rte_eth_udp_tunnel *udp_tunnel)
1681 {
1682         struct bnxt *bp = eth_dev->data->dev_private;
1683         uint16_t tunnel_type = 0;
1684         uint16_t port = 0;
1685         int rc = 0;
1686
1687         rc = is_bnxt_in_error(bp);
1688         if (rc)
1689                 return rc;
1690
1691         switch (udp_tunnel->prot_type) {
1692         case RTE_TUNNEL_TYPE_VXLAN:
1693                 if (!bp->vxlan_port_cnt) {
1694                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1695                         return -EINVAL;
1696                 }
1697                 if (bp->vxlan_port != udp_tunnel->udp_port) {
1698                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1699                                 udp_tunnel->udp_port, bp->vxlan_port);
1700                         return -EINVAL;
1701                 }
1702                 if (--bp->vxlan_port_cnt)
1703                         return 0;
1704
1705                 tunnel_type =
1706                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1707                 port = bp->vxlan_fw_dst_port_id;
1708                 break;
1709         case RTE_TUNNEL_TYPE_GENEVE:
1710                 if (!bp->geneve_port_cnt) {
1711                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1712                         return -EINVAL;
1713                 }
1714                 if (bp->geneve_port != udp_tunnel->udp_port) {
1715                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1716                                 udp_tunnel->udp_port, bp->geneve_port);
1717                         return -EINVAL;
1718                 }
1719                 if (--bp->geneve_port_cnt)
1720                         return 0;
1721
1722                 tunnel_type =
1723                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1724                 port = bp->geneve_fw_dst_port_id;
1725                 break;
1726         default:
1727                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1728                 return -ENOTSUP;
1729         }
1730
1731         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1732         if (!rc) {
1733                 if (tunnel_type ==
1734                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1735                         bp->vxlan_port = 0;
1736                 if (tunnel_type ==
1737                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1738                         bp->geneve_port = 0;
1739         }
1740         return rc;
1741 }
1742
1743 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1744 {
1745         struct bnxt_filter_info *filter;
1746         struct bnxt_vnic_info *vnic;
1747         int rc = 0;
1748         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1749
1750         /* if VLAN exists && VLAN matches vlan_id
1751          *      remove the MAC+VLAN filter
1752          *      add a new MAC only filter
1753          * else
1754          *      VLAN filter doesn't exist, just skip and continue
1755          */
1756         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1757         filter = STAILQ_FIRST(&vnic->filter);
1758         while (filter) {
1759                 /* Search for this matching MAC+VLAN filter */
1760                 if ((filter->enables & chk) &&
1761                     (filter->l2_ivlan == vlan_id &&
1762                      filter->l2_ivlan_mask != 0) &&
1763                     !memcmp(filter->l2_addr, bp->mac_addr,
1764                             RTE_ETHER_ADDR_LEN)) {
1765                         /* Delete the filter */
1766                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1767                         if (rc)
1768                                 return rc;
1769                         STAILQ_REMOVE(&vnic->filter, filter,
1770                                       bnxt_filter_info, next);
1771                         STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1772
1773                         PMD_DRV_LOG(INFO,
1774                                     "Del Vlan filter for %d\n",
1775                                     vlan_id);
1776                         return rc;
1777                 }
1778                 filter = STAILQ_NEXT(filter, next);
1779         }
1780         return -ENOENT;
1781 }
1782
1783 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1784 {
1785         struct bnxt_filter_info *filter;
1786         struct bnxt_vnic_info *vnic;
1787         int rc = 0;
1788         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1789                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1790         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1791
1792         /* Implementation notes on the use of VNIC in this command:
1793          *
1794          * By default, these filters belong to default vnic for the function.
1795          * Once these filters are set up, only destination VNIC can be modified.
1796          * If the destination VNIC is not specified in this command,
1797          * then the HWRM shall only create an l2 context id.
1798          */
1799
1800         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1801         filter = STAILQ_FIRST(&vnic->filter);
1802         /* Check if the VLAN has already been added */
1803         while (filter) {
1804                 if ((filter->enables & chk) &&
1805                     (filter->l2_ivlan == vlan_id &&
1806                      filter->l2_ivlan_mask == 0x0FFF) &&
1807                      !memcmp(filter->l2_addr, bp->mac_addr,
1808                              RTE_ETHER_ADDR_LEN))
1809                         return -EEXIST;
1810
1811                 filter = STAILQ_NEXT(filter, next);
1812         }
1813
1814         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1815          * command to create MAC+VLAN filter with the right flags, enables set.
1816          */
1817         filter = bnxt_alloc_filter(bp);
1818         if (!filter) {
1819                 PMD_DRV_LOG(ERR,
1820                             "MAC/VLAN filter alloc failed\n");
1821                 return -ENOMEM;
1822         }
1823         /* MAC + VLAN ID filter */
1824         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1825          * untagged packets are received
1826          *
1827          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1828          * packets and only the programmed vlan's packets are received
1829          */
1830         filter->l2_ivlan = vlan_id;
1831         filter->l2_ivlan_mask = 0x0FFF;
1832         filter->enables |= en;
1833         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1834
1835         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1836         if (rc) {
1837                 /* Free the newly allocated filter as we were
1838                  * not able to create the filter in hardware.
1839                  */
1840                 filter->fw_l2_filter_id = UINT64_MAX;
1841                 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
1842                 return rc;
1843         } else {
1844                 /* Add this new filter to the list */
1845                 if (vlan_id == 0) {
1846                         filter->dflt = true;
1847                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1848                 } else {
1849                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1850                 }
1851         }
1852
1853         PMD_DRV_LOG(INFO,
1854                     "Added Vlan filter for %d\n", vlan_id);
1855         return rc;
1856 }
1857
1858 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1859                 uint16_t vlan_id, int on)
1860 {
1861         struct bnxt *bp = eth_dev->data->dev_private;
1862         int rc;
1863
1864         rc = is_bnxt_in_error(bp);
1865         if (rc)
1866                 return rc;
1867
1868         /* These operations apply to ALL existing MAC/VLAN filters */
1869         if (on)
1870                 return bnxt_add_vlan_filter(bp, vlan_id);
1871         else
1872                 return bnxt_del_vlan_filter(bp, vlan_id);
1873 }
1874
1875 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1876                                     struct bnxt_vnic_info *vnic)
1877 {
1878         struct bnxt_filter_info *filter;
1879         int rc;
1880
1881         filter = STAILQ_FIRST(&vnic->filter);
1882         while (filter) {
1883                 if (filter->dflt &&
1884                     !memcmp(filter->l2_addr, bp->mac_addr,
1885                             RTE_ETHER_ADDR_LEN)) {
1886                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1887                         if (rc)
1888                                 return rc;
1889                         filter->dflt = false;
1890                         STAILQ_REMOVE(&vnic->filter, filter,
1891                                       bnxt_filter_info, next);
1892                         STAILQ_INSERT_TAIL(&bp->free_filter_list,
1893                                            filter, next);
1894                         filter->fw_l2_filter_id = -1;
1895                         break;
1896                 }
1897                 filter = STAILQ_NEXT(filter, next);
1898         }
1899         return 0;
1900 }
1901
1902 static int
1903 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1904 {
1905         struct bnxt *bp = dev->data->dev_private;
1906         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1907         struct bnxt_vnic_info *vnic;
1908         unsigned int i;
1909         int rc;
1910
1911         rc = is_bnxt_in_error(bp);
1912         if (rc)
1913                 return rc;
1914
1915         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1916         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1917                 /* Remove any VLAN filters programmed */
1918                 for (i = 0; i < 4095; i++)
1919                         bnxt_del_vlan_filter(bp, i);
1920
1921                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0);
1922                 if (rc)
1923                         return rc;
1924         } else {
1925                 /* Default filter will allow packets that match the
1926                  * dest mac. So, it has to be deleted, otherwise, we
1927                  * will endup receiving vlan packets for which the
1928                  * filter is not programmed, when hw-vlan-filter
1929                  * configuration is ON
1930                  */
1931                 bnxt_del_dflt_mac_filter(bp, vnic);
1932                 /* This filter will allow only untagged packets */
1933                 bnxt_add_vlan_filter(bp, 0);
1934         }
1935         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1936                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1937
1938         if (mask & ETH_VLAN_STRIP_MASK) {
1939                 /* Enable or disable VLAN stripping */
1940                 for (i = 0; i < bp->nr_vnics; i++) {
1941                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1942                         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1943                                 vnic->vlan_strip = true;
1944                         else
1945                                 vnic->vlan_strip = false;
1946                         bnxt_hwrm_vnic_cfg(bp, vnic);
1947                 }
1948                 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1949                         !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1950         }
1951
1952         if (mask & ETH_VLAN_EXTEND_MASK) {
1953                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1954                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
1955                 else
1956                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
1957         }
1958
1959         return 0;
1960 }
1961
1962 static int
1963 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
1964                       uint16_t tpid)
1965 {
1966         struct bnxt *bp = dev->data->dev_private;
1967         int qinq = dev->data->dev_conf.rxmode.offloads &
1968                    DEV_RX_OFFLOAD_VLAN_EXTEND;
1969
1970         if (vlan_type != ETH_VLAN_TYPE_INNER &&
1971             vlan_type != ETH_VLAN_TYPE_OUTER) {
1972                 PMD_DRV_LOG(ERR,
1973                             "Unsupported vlan type.");
1974                 return -EINVAL;
1975         }
1976         if (!qinq) {
1977                 PMD_DRV_LOG(ERR,
1978                             "QinQ not enabled. Needs to be ON as we can "
1979                             "accelerate only outer vlan\n");
1980                 return -EINVAL;
1981         }
1982
1983         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
1984                 switch (tpid) {
1985                 case RTE_ETHER_TYPE_QINQ:
1986                         bp->outer_tpid_bd =
1987                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
1988                                 break;
1989                 case RTE_ETHER_TYPE_VLAN:
1990                         bp->outer_tpid_bd =
1991                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
1992                                 break;
1993                 case 0x9100:
1994                         bp->outer_tpid_bd =
1995                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
1996                                 break;
1997                 case 0x9200:
1998                         bp->outer_tpid_bd =
1999                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2000                                 break;
2001                 case 0x9300:
2002                         bp->outer_tpid_bd =
2003                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2004                                 break;
2005                 default:
2006                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2007                         return -EINVAL;
2008                 }
2009                 bp->outer_tpid_bd |= tpid;
2010                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2011         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2012                 PMD_DRV_LOG(ERR,
2013                             "Can accelerate only outer vlan in QinQ\n");
2014                 return -EINVAL;
2015         }
2016
2017         return 0;
2018 }
2019
2020 static int
2021 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2022                              struct rte_ether_addr *addr)
2023 {
2024         struct bnxt *bp = dev->data->dev_private;
2025         /* Default Filter is tied to VNIC 0 */
2026         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
2027         struct bnxt_filter_info *filter;
2028         int rc;
2029
2030         rc = is_bnxt_in_error(bp);
2031         if (rc)
2032                 return rc;
2033
2034         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2035                 return -EPERM;
2036
2037         if (rte_is_zero_ether_addr(addr))
2038                 return -EINVAL;
2039
2040         STAILQ_FOREACH(filter, &vnic->filter, next) {
2041                 /* Default Filter is at Index 0 */
2042                 if (filter->mac_index != 0)
2043                         continue;
2044
2045                 memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN);
2046                 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
2047                 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX |
2048                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2049                 filter->enables |=
2050                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
2051                         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
2052
2053                 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2054                 if (rc) {
2055                         memcpy(filter->l2_addr, bp->mac_addr,
2056                                RTE_ETHER_ADDR_LEN);
2057                         return rc;
2058                 }
2059
2060                 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2061                 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2062                 return 0;
2063         }
2064
2065         return 0;
2066 }
2067
2068 static int
2069 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2070                           struct rte_ether_addr *mc_addr_set,
2071                           uint32_t nb_mc_addr)
2072 {
2073         struct bnxt *bp = eth_dev->data->dev_private;
2074         char *mc_addr_list = (char *)mc_addr_set;
2075         struct bnxt_vnic_info *vnic;
2076         uint32_t off = 0, i = 0;
2077         int rc;
2078
2079         rc = is_bnxt_in_error(bp);
2080         if (rc)
2081                 return rc;
2082
2083         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2084
2085         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2086                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2087                 goto allmulti;
2088         }
2089
2090         /* TODO Check for Duplicate mcast addresses */
2091         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2092         for (i = 0; i < nb_mc_addr; i++) {
2093                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2094                         RTE_ETHER_ADDR_LEN);
2095                 off += RTE_ETHER_ADDR_LEN;
2096         }
2097
2098         vnic->mc_addr_cnt = i;
2099         if (vnic->mc_addr_cnt)
2100                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2101         else
2102                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2103
2104 allmulti:
2105         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2106 }
2107
2108 static int
2109 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2110 {
2111         struct bnxt *bp = dev->data->dev_private;
2112         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2113         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2114         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2115         int ret;
2116
2117         ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2118                         fw_major, fw_minor, fw_updt);
2119
2120         ret += 1; /* add the size of '\0' */
2121         if (fw_size < (uint32_t)ret)
2122                 return ret;
2123         else
2124                 return 0;
2125 }
2126
2127 static void
2128 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2129         struct rte_eth_rxq_info *qinfo)
2130 {
2131         struct bnxt_rx_queue *rxq;
2132
2133         rxq = dev->data->rx_queues[queue_id];
2134
2135         qinfo->mp = rxq->mb_pool;
2136         qinfo->scattered_rx = dev->data->scattered_rx;
2137         qinfo->nb_desc = rxq->nb_rx_desc;
2138
2139         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2140         qinfo->conf.rx_drop_en = 0;
2141         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2142 }
2143
2144 static void
2145 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2146         struct rte_eth_txq_info *qinfo)
2147 {
2148         struct bnxt_tx_queue *txq;
2149
2150         txq = dev->data->tx_queues[queue_id];
2151
2152         qinfo->nb_desc = txq->nb_tx_desc;
2153
2154         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2155         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2156         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2157
2158         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2159         qinfo->conf.tx_rs_thresh = 0;
2160         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2161 }
2162
2163 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2164 {
2165         struct bnxt *bp = eth_dev->data->dev_private;
2166         uint32_t new_pkt_size;
2167         uint32_t rc = 0;
2168         uint32_t i;
2169
2170         rc = is_bnxt_in_error(bp);
2171         if (rc)
2172                 return rc;
2173
2174         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2175                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2176
2177 #ifdef RTE_ARCH_X86
2178         /*
2179          * If vector-mode tx/rx is active, disallow any MTU change that would
2180          * require scattered receive support.
2181          */
2182         if (eth_dev->data->dev_started &&
2183             (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2184              eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2185             (new_pkt_size >
2186              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2187                 PMD_DRV_LOG(ERR,
2188                             "MTU change would require scattered rx support. ");
2189                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2190                 return -EINVAL;
2191         }
2192 #endif
2193
2194         if (new_mtu > RTE_ETHER_MTU) {
2195                 bp->flags |= BNXT_FLAG_JUMBO;
2196                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2197                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2198         } else {
2199                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2200                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2201                 bp->flags &= ~BNXT_FLAG_JUMBO;
2202         }
2203
2204         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2205
2206         for (i = 0; i < bp->nr_vnics; i++) {
2207                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2208                 uint16_t size = 0;
2209
2210                 vnic->mru = new_mtu + RTE_ETHER_HDR_LEN +
2211                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
2212                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2213                 if (rc)
2214                         break;
2215
2216                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2217                 size -= RTE_PKTMBUF_HEADROOM;
2218
2219                 if (size < new_mtu) {
2220                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2221                         if (rc)
2222                                 return rc;
2223                 }
2224         }
2225
2226         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2227
2228         return rc;
2229 }
2230
2231 static int
2232 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2233 {
2234         struct bnxt *bp = dev->data->dev_private;
2235         uint16_t vlan = bp->vlan;
2236         int rc;
2237
2238         rc = is_bnxt_in_error(bp);
2239         if (rc)
2240                 return rc;
2241
2242         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2243                 PMD_DRV_LOG(ERR,
2244                         "PVID cannot be modified for this function\n");
2245                 return -ENOTSUP;
2246         }
2247         bp->vlan = on ? pvid : 0;
2248
2249         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2250         if (rc)
2251                 bp->vlan = vlan;
2252         return rc;
2253 }
2254
2255 static int
2256 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2257 {
2258         struct bnxt *bp = dev->data->dev_private;
2259         int rc;
2260
2261         rc = is_bnxt_in_error(bp);
2262         if (rc)
2263                 return rc;
2264
2265         return bnxt_hwrm_port_led_cfg(bp, true);
2266 }
2267
2268 static int
2269 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2270 {
2271         struct bnxt *bp = dev->data->dev_private;
2272         int rc;
2273
2274         rc = is_bnxt_in_error(bp);
2275         if (rc)
2276                 return rc;
2277
2278         return bnxt_hwrm_port_led_cfg(bp, false);
2279 }
2280
2281 static uint32_t
2282 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2283 {
2284         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2285         uint32_t desc = 0, raw_cons = 0, cons;
2286         struct bnxt_cp_ring_info *cpr;
2287         struct bnxt_rx_queue *rxq;
2288         struct rx_pkt_cmpl *rxcmp;
2289         int rc;
2290
2291         rc = is_bnxt_in_error(bp);
2292         if (rc)
2293                 return rc;
2294
2295         rxq = dev->data->rx_queues[rx_queue_id];
2296         cpr = rxq->cp_ring;
2297         raw_cons = cpr->cp_raw_cons;
2298
2299         while (1) {
2300                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2301                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2302                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2303
2304                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2305                         break;
2306                 } else {
2307                         raw_cons++;
2308                         desc++;
2309                 }
2310         }
2311
2312         return desc;
2313 }
2314
2315 static int
2316 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2317 {
2318         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2319         struct bnxt_rx_ring_info *rxr;
2320         struct bnxt_cp_ring_info *cpr;
2321         struct bnxt_sw_rx_bd *rx_buf;
2322         struct rx_pkt_cmpl *rxcmp;
2323         uint32_t cons, cp_cons;
2324         int rc;
2325
2326         if (!rxq)
2327                 return -EINVAL;
2328
2329         rc = is_bnxt_in_error(rxq->bp);
2330         if (rc)
2331                 return rc;
2332
2333         cpr = rxq->cp_ring;
2334         rxr = rxq->rx_ring;
2335
2336         if (offset >= rxq->nb_rx_desc)
2337                 return -EINVAL;
2338
2339         cons = RING_CMP(cpr->cp_ring_struct, offset);
2340         cp_cons = cpr->cp_raw_cons;
2341         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2342
2343         if (cons > cp_cons) {
2344                 if (CMPL_VALID(rxcmp, cpr->valid))
2345                         return RTE_ETH_RX_DESC_DONE;
2346         } else {
2347                 if (CMPL_VALID(rxcmp, !cpr->valid))
2348                         return RTE_ETH_RX_DESC_DONE;
2349         }
2350         rx_buf = &rxr->rx_buf_ring[cons];
2351         if (rx_buf->mbuf == NULL)
2352                 return RTE_ETH_RX_DESC_UNAVAIL;
2353
2354
2355         return RTE_ETH_RX_DESC_AVAIL;
2356 }
2357
2358 static int
2359 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2360 {
2361         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2362         struct bnxt_tx_ring_info *txr;
2363         struct bnxt_cp_ring_info *cpr;
2364         struct bnxt_sw_tx_bd *tx_buf;
2365         struct tx_pkt_cmpl *txcmp;
2366         uint32_t cons, cp_cons;
2367         int rc;
2368
2369         if (!txq)
2370                 return -EINVAL;
2371
2372         rc = is_bnxt_in_error(txq->bp);
2373         if (rc)
2374                 return rc;
2375
2376         cpr = txq->cp_ring;
2377         txr = txq->tx_ring;
2378
2379         if (offset >= txq->nb_tx_desc)
2380                 return -EINVAL;
2381
2382         cons = RING_CMP(cpr->cp_ring_struct, offset);
2383         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2384         cp_cons = cpr->cp_raw_cons;
2385
2386         if (cons > cp_cons) {
2387                 if (CMPL_VALID(txcmp, cpr->valid))
2388                         return RTE_ETH_TX_DESC_UNAVAIL;
2389         } else {
2390                 if (CMPL_VALID(txcmp, !cpr->valid))
2391                         return RTE_ETH_TX_DESC_UNAVAIL;
2392         }
2393         tx_buf = &txr->tx_buf_ring[cons];
2394         if (tx_buf->mbuf == NULL)
2395                 return RTE_ETH_TX_DESC_DONE;
2396
2397         return RTE_ETH_TX_DESC_FULL;
2398 }
2399
2400 static struct bnxt_filter_info *
2401 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2402                                 struct rte_eth_ethertype_filter *efilter,
2403                                 struct bnxt_vnic_info *vnic0,
2404                                 struct bnxt_vnic_info *vnic,
2405                                 int *ret)
2406 {
2407         struct bnxt_filter_info *mfilter = NULL;
2408         int match = 0;
2409         *ret = 0;
2410
2411         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2412                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2413                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2414                         " ethertype filter.", efilter->ether_type);
2415                 *ret = -EINVAL;
2416                 goto exit;
2417         }
2418         if (efilter->queue >= bp->rx_nr_rings) {
2419                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2420                 *ret = -EINVAL;
2421                 goto exit;
2422         }
2423
2424         vnic0 = &bp->vnic_info[0];
2425         vnic = &bp->vnic_info[efilter->queue];
2426         if (vnic == NULL) {
2427                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2428                 *ret = -EINVAL;
2429                 goto exit;
2430         }
2431
2432         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2433                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2434                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2435                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2436                              mfilter->flags ==
2437                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2438                              mfilter->ethertype == efilter->ether_type)) {
2439                                 match = 1;
2440                                 break;
2441                         }
2442                 }
2443         } else {
2444                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2445                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2446                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2447                              mfilter->ethertype == efilter->ether_type &&
2448                              mfilter->flags ==
2449                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2450                                 match = 1;
2451                                 break;
2452                         }
2453         }
2454
2455         if (match)
2456                 *ret = -EEXIST;
2457
2458 exit:
2459         return mfilter;
2460 }
2461
2462 static int
2463 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2464                         enum rte_filter_op filter_op,
2465                         void *arg)
2466 {
2467         struct bnxt *bp = dev->data->dev_private;
2468         struct rte_eth_ethertype_filter *efilter =
2469                         (struct rte_eth_ethertype_filter *)arg;
2470         struct bnxt_filter_info *bfilter, *filter1;
2471         struct bnxt_vnic_info *vnic, *vnic0;
2472         int ret;
2473
2474         if (filter_op == RTE_ETH_FILTER_NOP)
2475                 return 0;
2476
2477         if (arg == NULL) {
2478                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2479                             filter_op);
2480                 return -EINVAL;
2481         }
2482
2483         vnic0 = &bp->vnic_info[0];
2484         vnic = &bp->vnic_info[efilter->queue];
2485
2486         switch (filter_op) {
2487         case RTE_ETH_FILTER_ADD:
2488                 bnxt_match_and_validate_ether_filter(bp, efilter,
2489                                                         vnic0, vnic, &ret);
2490                 if (ret < 0)
2491                         return ret;
2492
2493                 bfilter = bnxt_get_unused_filter(bp);
2494                 if (bfilter == NULL) {
2495                         PMD_DRV_LOG(ERR,
2496                                 "Not enough resources for a new filter.\n");
2497                         return -ENOMEM;
2498                 }
2499                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2500                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2501                        RTE_ETHER_ADDR_LEN);
2502                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2503                        RTE_ETHER_ADDR_LEN);
2504                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2505                 bfilter->ethertype = efilter->ether_type;
2506                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2507
2508                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2509                 if (filter1 == NULL) {
2510                         ret = -EINVAL;
2511                         goto cleanup;
2512                 }
2513                 bfilter->enables |=
2514                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2515                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2516
2517                 bfilter->dst_id = vnic->fw_vnic_id;
2518
2519                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2520                         bfilter->flags =
2521                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2522                 }
2523
2524                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2525                 if (ret)
2526                         goto cleanup;
2527                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2528                 break;
2529         case RTE_ETH_FILTER_DELETE:
2530                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2531                                                         vnic0, vnic, &ret);
2532                 if (ret == -EEXIST) {
2533                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2534
2535                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2536                                       next);
2537                         bnxt_free_filter(bp, filter1);
2538                 } else if (ret == 0) {
2539                         PMD_DRV_LOG(ERR, "No matching filter found\n");
2540                 }
2541                 break;
2542         default:
2543                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2544                 ret = -EINVAL;
2545                 goto error;
2546         }
2547         return ret;
2548 cleanup:
2549         bnxt_free_filter(bp, bfilter);
2550 error:
2551         return ret;
2552 }
2553
2554 static inline int
2555 parse_ntuple_filter(struct bnxt *bp,
2556                     struct rte_eth_ntuple_filter *nfilter,
2557                     struct bnxt_filter_info *bfilter)
2558 {
2559         uint32_t en = 0;
2560
2561         if (nfilter->queue >= bp->rx_nr_rings) {
2562                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2563                 return -EINVAL;
2564         }
2565
2566         switch (nfilter->dst_port_mask) {
2567         case UINT16_MAX:
2568                 bfilter->dst_port_mask = -1;
2569                 bfilter->dst_port = nfilter->dst_port;
2570                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2571                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2572                 break;
2573         default:
2574                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2575                 return -EINVAL;
2576         }
2577
2578         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2579         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2580
2581         switch (nfilter->proto_mask) {
2582         case UINT8_MAX:
2583                 if (nfilter->proto == 17) /* IPPROTO_UDP */
2584                         bfilter->ip_protocol = 17;
2585                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2586                         bfilter->ip_protocol = 6;
2587                 else
2588                         return -EINVAL;
2589                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2590                 break;
2591         default:
2592                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2593                 return -EINVAL;
2594         }
2595
2596         switch (nfilter->dst_ip_mask) {
2597         case UINT32_MAX:
2598                 bfilter->dst_ipaddr_mask[0] = -1;
2599                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2600                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2601                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2602                 break;
2603         default:
2604                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2605                 return -EINVAL;
2606         }
2607
2608         switch (nfilter->src_ip_mask) {
2609         case UINT32_MAX:
2610                 bfilter->src_ipaddr_mask[0] = -1;
2611                 bfilter->src_ipaddr[0] = nfilter->src_ip;
2612                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2613                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2614                 break;
2615         default:
2616                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2617                 return -EINVAL;
2618         }
2619
2620         switch (nfilter->src_port_mask) {
2621         case UINT16_MAX:
2622                 bfilter->src_port_mask = -1;
2623                 bfilter->src_port = nfilter->src_port;
2624                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2625                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2626                 break;
2627         default:
2628                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2629                 return -EINVAL;
2630         }
2631
2632         //TODO Priority
2633         //nfilter->priority = (uint8_t)filter->priority;
2634
2635         bfilter->enables = en;
2636         return 0;
2637 }
2638
2639 static struct bnxt_filter_info*
2640 bnxt_match_ntuple_filter(struct bnxt *bp,
2641                          struct bnxt_filter_info *bfilter,
2642                          struct bnxt_vnic_info **mvnic)
2643 {
2644         struct bnxt_filter_info *mfilter = NULL;
2645         int i;
2646
2647         for (i = bp->nr_vnics - 1; i >= 0; i--) {
2648                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2649                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2650                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2651                             bfilter->src_ipaddr_mask[0] ==
2652                             mfilter->src_ipaddr_mask[0] &&
2653                             bfilter->src_port == mfilter->src_port &&
2654                             bfilter->src_port_mask == mfilter->src_port_mask &&
2655                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2656                             bfilter->dst_ipaddr_mask[0] ==
2657                             mfilter->dst_ipaddr_mask[0] &&
2658                             bfilter->dst_port == mfilter->dst_port &&
2659                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
2660                             bfilter->flags == mfilter->flags &&
2661                             bfilter->enables == mfilter->enables) {
2662                                 if (mvnic)
2663                                         *mvnic = vnic;
2664                                 return mfilter;
2665                         }
2666                 }
2667         }
2668         return NULL;
2669 }
2670
2671 static int
2672 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2673                        struct rte_eth_ntuple_filter *nfilter,
2674                        enum rte_filter_op filter_op)
2675 {
2676         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2677         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2678         int ret;
2679
2680         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2681                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2682                 return -EINVAL;
2683         }
2684
2685         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2686                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2687                 return -EINVAL;
2688         }
2689
2690         bfilter = bnxt_get_unused_filter(bp);
2691         if (bfilter == NULL) {
2692                 PMD_DRV_LOG(ERR,
2693                         "Not enough resources for a new filter.\n");
2694                 return -ENOMEM;
2695         }
2696         ret = parse_ntuple_filter(bp, nfilter, bfilter);
2697         if (ret < 0)
2698                 goto free_filter;
2699
2700         vnic = &bp->vnic_info[nfilter->queue];
2701         vnic0 = &bp->vnic_info[0];
2702         filter1 = STAILQ_FIRST(&vnic0->filter);
2703         if (filter1 == NULL) {
2704                 ret = -EINVAL;
2705                 goto free_filter;
2706         }
2707
2708         bfilter->dst_id = vnic->fw_vnic_id;
2709         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2710         bfilter->enables |=
2711                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2712         bfilter->ethertype = 0x800;
2713         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2714
2715         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2716
2717         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2718             bfilter->dst_id == mfilter->dst_id) {
2719                 PMD_DRV_LOG(ERR, "filter exists.\n");
2720                 ret = -EEXIST;
2721                 goto free_filter;
2722         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2723                    bfilter->dst_id != mfilter->dst_id) {
2724                 mfilter->dst_id = vnic->fw_vnic_id;
2725                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2726                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2727                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2728                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2729                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2730                 goto free_filter;
2731         }
2732         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2733                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2734                 ret = -ENOENT;
2735                 goto free_filter;
2736         }
2737
2738         if (filter_op == RTE_ETH_FILTER_ADD) {
2739                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2740                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2741                 if (ret)
2742                         goto free_filter;
2743                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2744         } else {
2745                 if (mfilter == NULL) {
2746                         /* This should not happen. But for Coverity! */
2747                         ret = -ENOENT;
2748                         goto free_filter;
2749                 }
2750                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2751
2752                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2753                 bnxt_free_filter(bp, mfilter);
2754                 mfilter->fw_l2_filter_id = -1;
2755                 bnxt_free_filter(bp, bfilter);
2756                 bfilter->fw_l2_filter_id = -1;
2757         }
2758
2759         return 0;
2760 free_filter:
2761         bfilter->fw_l2_filter_id = -1;
2762         bnxt_free_filter(bp, bfilter);
2763         return ret;
2764 }
2765
2766 static int
2767 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2768                         enum rte_filter_op filter_op,
2769                         void *arg)
2770 {
2771         struct bnxt *bp = dev->data->dev_private;
2772         int ret;
2773
2774         if (filter_op == RTE_ETH_FILTER_NOP)
2775                 return 0;
2776
2777         if (arg == NULL) {
2778                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2779                             filter_op);
2780                 return -EINVAL;
2781         }
2782
2783         switch (filter_op) {
2784         case RTE_ETH_FILTER_ADD:
2785                 ret = bnxt_cfg_ntuple_filter(bp,
2786                         (struct rte_eth_ntuple_filter *)arg,
2787                         filter_op);
2788                 break;
2789         case RTE_ETH_FILTER_DELETE:
2790                 ret = bnxt_cfg_ntuple_filter(bp,
2791                         (struct rte_eth_ntuple_filter *)arg,
2792                         filter_op);
2793                 break;
2794         default:
2795                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2796                 ret = -EINVAL;
2797                 break;
2798         }
2799         return ret;
2800 }
2801
2802 static int
2803 bnxt_parse_fdir_filter(struct bnxt *bp,
2804                        struct rte_eth_fdir_filter *fdir,
2805                        struct bnxt_filter_info *filter)
2806 {
2807         enum rte_fdir_mode fdir_mode =
2808                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2809         struct bnxt_vnic_info *vnic0, *vnic;
2810         struct bnxt_filter_info *filter1;
2811         uint32_t en = 0;
2812         int i;
2813
2814         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2815                 return -EINVAL;
2816
2817         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2818         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2819
2820         switch (fdir->input.flow_type) {
2821         case RTE_ETH_FLOW_IPV4:
2822         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2823                 /* FALLTHROUGH */
2824                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2825                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2826                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2827                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2828                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2829                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2830                 filter->ip_addr_type =
2831                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2832                 filter->src_ipaddr_mask[0] = 0xffffffff;
2833                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2834                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2835                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2836                 filter->ethertype = 0x800;
2837                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2838                 break;
2839         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2840                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2841                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2842                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2843                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2844                 filter->dst_port_mask = 0xffff;
2845                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2846                 filter->src_port_mask = 0xffff;
2847                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2848                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2849                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2850                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2851                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2852                 filter->ip_protocol = 6;
2853                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2854                 filter->ip_addr_type =
2855                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2856                 filter->src_ipaddr_mask[0] = 0xffffffff;
2857                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2858                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2859                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2860                 filter->ethertype = 0x800;
2861                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2862                 break;
2863         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2864                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2865                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2866                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2867                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2868                 filter->dst_port_mask = 0xffff;
2869                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2870                 filter->src_port_mask = 0xffff;
2871                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2872                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2873                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2874                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2875                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2876                 filter->ip_protocol = 17;
2877                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2878                 filter->ip_addr_type =
2879                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2880                 filter->src_ipaddr_mask[0] = 0xffffffff;
2881                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2882                 filter->dst_ipaddr_mask[0] = 0xffffffff;
2883                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2884                 filter->ethertype = 0x800;
2885                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2886                 break;
2887         case RTE_ETH_FLOW_IPV6:
2888         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2889                 /* FALLTHROUGH */
2890                 filter->ip_addr_type =
2891                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2892                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2893                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2894                 rte_memcpy(filter->src_ipaddr,
2895                            fdir->input.flow.ipv6_flow.src_ip, 16);
2896                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2897                 rte_memcpy(filter->dst_ipaddr,
2898                            fdir->input.flow.ipv6_flow.dst_ip, 16);
2899                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2900                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2901                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2902                 memset(filter->src_ipaddr_mask, 0xff, 16);
2903                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2904                 filter->ethertype = 0x86dd;
2905                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2906                 break;
2907         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2908                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2909                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2910                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2911                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2912                 filter->dst_port_mask = 0xffff;
2913                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2914                 filter->src_port_mask = 0xffff;
2915                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2916                 filter->ip_addr_type =
2917                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2918                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2919                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2920                 rte_memcpy(filter->src_ipaddr,
2921                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2922                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2923                 rte_memcpy(filter->dst_ipaddr,
2924                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2925                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2926                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2927                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2928                 memset(filter->src_ipaddr_mask, 0xff, 16);
2929                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2930                 filter->ethertype = 0x86dd;
2931                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2932                 break;
2933         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2934                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2935                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2936                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2937                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2938                 filter->dst_port_mask = 0xffff;
2939                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2940                 filter->src_port_mask = 0xffff;
2941                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2942                 filter->ip_addr_type =
2943                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2944                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2945                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2946                 rte_memcpy(filter->src_ipaddr,
2947                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
2948                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2949                 rte_memcpy(filter->dst_ipaddr,
2950                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2951                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2952                 memset(filter->dst_ipaddr_mask, 0xff, 16);
2953                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2954                 memset(filter->src_ipaddr_mask, 0xff, 16);
2955                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2956                 filter->ethertype = 0x86dd;
2957                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2958                 break;
2959         case RTE_ETH_FLOW_L2_PAYLOAD:
2960                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2961                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2962                 break;
2963         case RTE_ETH_FLOW_VXLAN:
2964                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2965                         return -EINVAL;
2966                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2967                 filter->tunnel_type =
2968                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2969                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2970                 break;
2971         case RTE_ETH_FLOW_NVGRE:
2972                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2973                         return -EINVAL;
2974                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2975                 filter->tunnel_type =
2976                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2977                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2978                 break;
2979         case RTE_ETH_FLOW_UNKNOWN:
2980         case RTE_ETH_FLOW_RAW:
2981         case RTE_ETH_FLOW_FRAG_IPV4:
2982         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2983         case RTE_ETH_FLOW_FRAG_IPV6:
2984         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2985         case RTE_ETH_FLOW_IPV6_EX:
2986         case RTE_ETH_FLOW_IPV6_TCP_EX:
2987         case RTE_ETH_FLOW_IPV6_UDP_EX:
2988         case RTE_ETH_FLOW_GENEVE:
2989                 /* FALLTHROUGH */
2990         default:
2991                 return -EINVAL;
2992         }
2993
2994         vnic0 = &bp->vnic_info[0];
2995         vnic = &bp->vnic_info[fdir->action.rx_queue];
2996         if (vnic == NULL) {
2997                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2998                 return -EINVAL;
2999         }
3000
3001
3002         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3003                 rte_memcpy(filter->dst_macaddr,
3004                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3005                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3006         }
3007
3008         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3009                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3010                 filter1 = STAILQ_FIRST(&vnic0->filter);
3011                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3012         } else {
3013                 filter->dst_id = vnic->fw_vnic_id;
3014                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3015                         if (filter->dst_macaddr[i] == 0x00)
3016                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3017                         else
3018                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3019         }
3020
3021         if (filter1 == NULL)
3022                 return -EINVAL;
3023
3024         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3025         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3026
3027         filter->enables = en;
3028
3029         return 0;
3030 }
3031
3032 static struct bnxt_filter_info *
3033 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3034                 struct bnxt_vnic_info **mvnic)
3035 {
3036         struct bnxt_filter_info *mf = NULL;
3037         int i;
3038
3039         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3040                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3041
3042                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3043                         if (mf->filter_type == nf->filter_type &&
3044                             mf->flags == nf->flags &&
3045                             mf->src_port == nf->src_port &&
3046                             mf->src_port_mask == nf->src_port_mask &&
3047                             mf->dst_port == nf->dst_port &&
3048                             mf->dst_port_mask == nf->dst_port_mask &&
3049                             mf->ip_protocol == nf->ip_protocol &&
3050                             mf->ip_addr_type == nf->ip_addr_type &&
3051                             mf->ethertype == nf->ethertype &&
3052                             mf->vni == nf->vni &&
3053                             mf->tunnel_type == nf->tunnel_type &&
3054                             mf->l2_ovlan == nf->l2_ovlan &&
3055                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3056                             mf->l2_ivlan == nf->l2_ivlan &&
3057                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3058                             !memcmp(mf->l2_addr, nf->l2_addr,
3059                                     RTE_ETHER_ADDR_LEN) &&
3060                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3061                                     RTE_ETHER_ADDR_LEN) &&
3062                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3063                                     RTE_ETHER_ADDR_LEN) &&
3064                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3065                                     RTE_ETHER_ADDR_LEN) &&
3066                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3067                                     sizeof(nf->src_ipaddr)) &&
3068                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3069                                     sizeof(nf->src_ipaddr_mask)) &&
3070                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3071                                     sizeof(nf->dst_ipaddr)) &&
3072                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3073                                     sizeof(nf->dst_ipaddr_mask))) {
3074                                 if (mvnic)
3075                                         *mvnic = vnic;
3076                                 return mf;
3077                         }
3078                 }
3079         }
3080         return NULL;
3081 }
3082
3083 static int
3084 bnxt_fdir_filter(struct rte_eth_dev *dev,
3085                  enum rte_filter_op filter_op,
3086                  void *arg)
3087 {
3088         struct bnxt *bp = dev->data->dev_private;
3089         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3090         struct bnxt_filter_info *filter, *match;
3091         struct bnxt_vnic_info *vnic, *mvnic;
3092         int ret = 0, i;
3093
3094         if (filter_op == RTE_ETH_FILTER_NOP)
3095                 return 0;
3096
3097         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3098                 return -EINVAL;
3099
3100         switch (filter_op) {
3101         case RTE_ETH_FILTER_ADD:
3102         case RTE_ETH_FILTER_DELETE:
3103                 /* FALLTHROUGH */
3104                 filter = bnxt_get_unused_filter(bp);
3105                 if (filter == NULL) {
3106                         PMD_DRV_LOG(ERR,
3107                                 "Not enough resources for a new flow.\n");
3108                         return -ENOMEM;
3109                 }
3110
3111                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3112                 if (ret != 0)
3113                         goto free_filter;
3114                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3115
3116                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3117                         vnic = &bp->vnic_info[0];
3118                 else
3119                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3120
3121                 match = bnxt_match_fdir(bp, filter, &mvnic);
3122                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3123                         if (match->dst_id == vnic->fw_vnic_id) {
3124                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3125                                 ret = -EEXIST;
3126                                 goto free_filter;
3127                         } else {
3128                                 match->dst_id = vnic->fw_vnic_id;
3129                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3130                                                                   match->dst_id,
3131                                                                   match);
3132                                 STAILQ_REMOVE(&mvnic->filter, match,
3133                                               bnxt_filter_info, next);
3134                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3135                                 PMD_DRV_LOG(ERR,
3136                                         "Filter with matching pattern exist\n");
3137                                 PMD_DRV_LOG(ERR,
3138                                         "Updated it to new destination q\n");
3139                                 goto free_filter;
3140                         }
3141                 }
3142                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3143                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3144                         ret = -ENOENT;
3145                         goto free_filter;
3146                 }
3147
3148                 if (filter_op == RTE_ETH_FILTER_ADD) {
3149                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3150                                                           filter->dst_id,
3151                                                           filter);
3152                         if (ret)
3153                                 goto free_filter;
3154                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3155                 } else {
3156                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3157                         STAILQ_REMOVE(&vnic->filter, match,
3158                                       bnxt_filter_info, next);
3159                         bnxt_free_filter(bp, match);
3160                         filter->fw_l2_filter_id = -1;
3161                         bnxt_free_filter(bp, filter);
3162                 }
3163                 break;
3164         case RTE_ETH_FILTER_FLUSH:
3165                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3166                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3167
3168                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3169                                 if (filter->filter_type ==
3170                                     HWRM_CFA_NTUPLE_FILTER) {
3171                                         ret =
3172                                         bnxt_hwrm_clear_ntuple_filter(bp,
3173                                                                       filter);
3174                                         STAILQ_REMOVE(&vnic->filter, filter,
3175                                                       bnxt_filter_info, next);
3176                                 }
3177                         }
3178                 }
3179                 return ret;
3180         case RTE_ETH_FILTER_UPDATE:
3181         case RTE_ETH_FILTER_STATS:
3182         case RTE_ETH_FILTER_INFO:
3183                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3184                 break;
3185         default:
3186                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3187                 ret = -EINVAL;
3188                 break;
3189         }
3190         return ret;
3191
3192 free_filter:
3193         filter->fw_l2_filter_id = -1;
3194         bnxt_free_filter(bp, filter);
3195         return ret;
3196 }
3197
3198 static int
3199 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
3200                     enum rte_filter_type filter_type,
3201                     enum rte_filter_op filter_op, void *arg)
3202 {
3203         int ret = 0;
3204
3205         ret = is_bnxt_in_error(dev->data->dev_private);
3206         if (ret)
3207                 return ret;
3208
3209         switch (filter_type) {
3210         case RTE_ETH_FILTER_TUNNEL:
3211                 PMD_DRV_LOG(ERR,
3212                         "filter type: %d: To be implemented\n", filter_type);
3213                 break;
3214         case RTE_ETH_FILTER_FDIR:
3215                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3216                 break;
3217         case RTE_ETH_FILTER_NTUPLE:
3218                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3219                 break;
3220         case RTE_ETH_FILTER_ETHERTYPE:
3221                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3222                 break;
3223         case RTE_ETH_FILTER_GENERIC:
3224                 if (filter_op != RTE_ETH_FILTER_GET)
3225                         return -EINVAL;
3226                 *(const void **)arg = &bnxt_flow_ops;
3227                 break;
3228         default:
3229                 PMD_DRV_LOG(ERR,
3230                         "Filter type (%d) not supported", filter_type);
3231                 ret = -EINVAL;
3232                 break;
3233         }
3234         return ret;
3235 }
3236
3237 static const uint32_t *
3238 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3239 {
3240         static const uint32_t ptypes[] = {
3241                 RTE_PTYPE_L2_ETHER_VLAN,
3242                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3243                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3244                 RTE_PTYPE_L4_ICMP,
3245                 RTE_PTYPE_L4_TCP,
3246                 RTE_PTYPE_L4_UDP,
3247                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3248                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3249                 RTE_PTYPE_INNER_L4_ICMP,
3250                 RTE_PTYPE_INNER_L4_TCP,
3251                 RTE_PTYPE_INNER_L4_UDP,
3252                 RTE_PTYPE_UNKNOWN
3253         };
3254
3255         if (!dev->rx_pkt_burst)
3256                 return NULL;
3257
3258         return ptypes;
3259 }
3260
3261 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3262                          int reg_win)
3263 {
3264         uint32_t reg_base = *reg_arr & 0xfffff000;
3265         uint32_t win_off;
3266         int i;
3267
3268         for (i = 0; i < count; i++) {
3269                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3270                         return -ERANGE;
3271         }
3272         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3273         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3274         return 0;
3275 }
3276
3277 static int bnxt_map_ptp_regs(struct bnxt *bp)
3278 {
3279         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3280         uint32_t *reg_arr;
3281         int rc, i;
3282
3283         reg_arr = ptp->rx_regs;
3284         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3285         if (rc)
3286                 return rc;
3287
3288         reg_arr = ptp->tx_regs;
3289         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3290         if (rc)
3291                 return rc;
3292
3293         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3294                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3295
3296         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3297                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3298
3299         return 0;
3300 }
3301
3302 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3303 {
3304         rte_write32(0, (uint8_t *)bp->bar0 +
3305                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3306         rte_write32(0, (uint8_t *)bp->bar0 +
3307                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3308 }
3309
3310 static uint64_t bnxt_cc_read(struct bnxt *bp)
3311 {
3312         uint64_t ns;
3313
3314         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3315                               BNXT_GRCPF_REG_SYNC_TIME));
3316         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3317                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3318         return ns;
3319 }
3320
3321 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3322 {
3323         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3324         uint32_t fifo;
3325
3326         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3327                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3328         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3329                 return -EAGAIN;
3330
3331         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3332                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3333         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3334                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3335         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3336                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3337
3338         return 0;
3339 }
3340
3341 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3342 {
3343         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3344         struct bnxt_pf_info *pf = &bp->pf;
3345         uint16_t port_id;
3346         uint32_t fifo;
3347
3348         if (!ptp)
3349                 return -ENODEV;
3350
3351         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3352                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3353         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3354                 return -EAGAIN;
3355
3356         port_id = pf->port_id;
3357         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3358                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3359
3360         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3361                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3362         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3363 /*              bnxt_clr_rx_ts(bp);       TBD  */
3364                 return -EBUSY;
3365         }
3366
3367         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3368                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3369         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3370                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3371
3372         return 0;
3373 }
3374
3375 static int
3376 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3377 {
3378         uint64_t ns;
3379         struct bnxt *bp = dev->data->dev_private;
3380         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3381
3382         if (!ptp)
3383                 return 0;
3384
3385         ns = rte_timespec_to_ns(ts);
3386         /* Set the timecounters to a new value. */
3387         ptp->tc.nsec = ns;
3388
3389         return 0;
3390 }
3391
3392 static int
3393 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3394 {
3395         struct bnxt *bp = dev->data->dev_private;
3396         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3397         uint64_t ns, systime_cycles = 0;
3398         int rc = 0;
3399
3400         if (!ptp)
3401                 return 0;
3402
3403         if (BNXT_CHIP_THOR(bp))
3404                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3405                                              &systime_cycles);
3406         else
3407                 systime_cycles = bnxt_cc_read(bp);
3408
3409         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3410         *ts = rte_ns_to_timespec(ns);
3411
3412         return rc;
3413 }
3414 static int
3415 bnxt_timesync_enable(struct rte_eth_dev *dev)
3416 {
3417         struct bnxt *bp = dev->data->dev_private;
3418         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3419         uint32_t shift = 0;
3420         int rc;
3421
3422         if (!ptp)
3423                 return 0;
3424
3425         ptp->rx_filter = 1;
3426         ptp->tx_tstamp_en = 1;
3427         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3428
3429         rc = bnxt_hwrm_ptp_cfg(bp);
3430         if (rc)
3431                 return rc;
3432
3433         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3434         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3435         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3436
3437         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3438         ptp->tc.cc_shift = shift;
3439         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3440
3441         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3442         ptp->rx_tstamp_tc.cc_shift = shift;
3443         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3444
3445         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3446         ptp->tx_tstamp_tc.cc_shift = shift;
3447         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3448
3449         if (!BNXT_CHIP_THOR(bp))
3450                 bnxt_map_ptp_regs(bp);
3451
3452         return 0;
3453 }
3454
3455 static int
3456 bnxt_timesync_disable(struct rte_eth_dev *dev)
3457 {
3458         struct bnxt *bp = dev->data->dev_private;
3459         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3460
3461         if (!ptp)
3462                 return 0;
3463
3464         ptp->rx_filter = 0;
3465         ptp->tx_tstamp_en = 0;
3466         ptp->rxctl = 0;
3467
3468         bnxt_hwrm_ptp_cfg(bp);
3469
3470         if (!BNXT_CHIP_THOR(bp))
3471                 bnxt_unmap_ptp_regs(bp);
3472
3473         return 0;
3474 }
3475
3476 static int
3477 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3478                                  struct timespec *timestamp,
3479                                  uint32_t flags __rte_unused)
3480 {
3481         struct bnxt *bp = dev->data->dev_private;
3482         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3483         uint64_t rx_tstamp_cycles = 0;
3484         uint64_t ns;
3485
3486         if (!ptp)
3487                 return 0;
3488
3489         if (BNXT_CHIP_THOR(bp))
3490                 rx_tstamp_cycles = ptp->rx_timestamp;
3491         else
3492                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3493
3494         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3495         *timestamp = rte_ns_to_timespec(ns);
3496         return  0;
3497 }
3498
3499 static int
3500 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3501                                  struct timespec *timestamp)
3502 {
3503         struct bnxt *bp = dev->data->dev_private;
3504         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3505         uint64_t tx_tstamp_cycles = 0;
3506         uint64_t ns;
3507         int rc = 0;
3508
3509         if (!ptp)
3510                 return 0;
3511
3512         if (BNXT_CHIP_THOR(bp))
3513                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3514                                              &tx_tstamp_cycles);
3515         else
3516                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3517
3518         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3519         *timestamp = rte_ns_to_timespec(ns);
3520
3521         return rc;
3522 }
3523
3524 static int
3525 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3526 {
3527         struct bnxt *bp = dev->data->dev_private;
3528         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3529
3530         if (!ptp)
3531                 return 0;
3532
3533         ptp->tc.nsec += delta;
3534
3535         return 0;
3536 }
3537
3538 static int
3539 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3540 {
3541         struct bnxt *bp = dev->data->dev_private;
3542         int rc;
3543         uint32_t dir_entries;
3544         uint32_t entry_length;
3545
3546         rc = is_bnxt_in_error(bp);
3547         if (rc)
3548                 return rc;
3549
3550         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
3551                 bp->pdev->addr.domain, bp->pdev->addr.bus,
3552                 bp->pdev->addr.devid, bp->pdev->addr.function);
3553
3554         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3555         if (rc != 0)
3556                 return rc;
3557
3558         return dir_entries * entry_length;
3559 }
3560
3561 static int
3562 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3563                 struct rte_dev_eeprom_info *in_eeprom)
3564 {
3565         struct bnxt *bp = dev->data->dev_private;
3566         uint32_t index;
3567         uint32_t offset;
3568         int rc;
3569
3570         rc = is_bnxt_in_error(bp);
3571         if (rc)
3572                 return rc;
3573
3574         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3575                 "len = %d\n", bp->pdev->addr.domain,
3576                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3577                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3578
3579         if (in_eeprom->offset == 0) /* special offset value to get directory */
3580                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3581                                                 in_eeprom->data);
3582
3583         index = in_eeprom->offset >> 24;
3584         offset = in_eeprom->offset & 0xffffff;
3585
3586         if (index != 0)
3587                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3588                                            in_eeprom->length, in_eeprom->data);
3589
3590         return 0;
3591 }
3592
3593 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3594 {
3595         switch (dir_type) {
3596         case BNX_DIR_TYPE_CHIMP_PATCH:
3597         case BNX_DIR_TYPE_BOOTCODE:
3598         case BNX_DIR_TYPE_BOOTCODE_2:
3599         case BNX_DIR_TYPE_APE_FW:
3600         case BNX_DIR_TYPE_APE_PATCH:
3601         case BNX_DIR_TYPE_KONG_FW:
3602         case BNX_DIR_TYPE_KONG_PATCH:
3603         case BNX_DIR_TYPE_BONO_FW:
3604         case BNX_DIR_TYPE_BONO_PATCH:
3605                 /* FALLTHROUGH */
3606                 return true;
3607         }
3608
3609         return false;
3610 }
3611
3612 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3613 {
3614         switch (dir_type) {
3615         case BNX_DIR_TYPE_AVS:
3616         case BNX_DIR_TYPE_EXP_ROM_MBA:
3617         case BNX_DIR_TYPE_PCIE:
3618         case BNX_DIR_TYPE_TSCF_UCODE:
3619         case BNX_DIR_TYPE_EXT_PHY:
3620         case BNX_DIR_TYPE_CCM:
3621         case BNX_DIR_TYPE_ISCSI_BOOT:
3622         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3623         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3624                 /* FALLTHROUGH */
3625                 return true;
3626         }
3627
3628         return false;
3629 }
3630
3631 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3632 {
3633         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3634                 bnxt_dir_type_is_other_exec_format(dir_type);
3635 }
3636
3637 static int
3638 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3639                 struct rte_dev_eeprom_info *in_eeprom)
3640 {
3641         struct bnxt *bp = dev->data->dev_private;
3642         uint8_t index, dir_op;
3643         uint16_t type, ext, ordinal, attr;
3644         int rc;
3645
3646         rc = is_bnxt_in_error(bp);
3647         if (rc)
3648                 return rc;
3649
3650         PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
3651                 "len = %d\n", bp->pdev->addr.domain,
3652                 bp->pdev->addr.bus, bp->pdev->addr.devid,
3653                 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
3654
3655         if (!BNXT_PF(bp)) {
3656                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3657                 return -EINVAL;
3658         }
3659
3660         type = in_eeprom->magic >> 16;
3661
3662         if (type == 0xffff) { /* special value for directory operations */
3663                 index = in_eeprom->magic & 0xff;
3664                 dir_op = in_eeprom->magic >> 8;
3665                 if (index == 0)
3666                         return -EINVAL;
3667                 switch (dir_op) {
3668                 case 0x0e: /* erase */
3669                         if (in_eeprom->offset != ~in_eeprom->magic)
3670                                 return -EINVAL;
3671                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3672                 default:
3673                         return -EINVAL;
3674                 }
3675         }
3676
3677         /* Create or re-write an NVM item: */
3678         if (bnxt_dir_type_is_executable(type) == true)
3679                 return -EOPNOTSUPP;
3680         ext = in_eeprom->magic & 0xffff;
3681         ordinal = in_eeprom->offset >> 16;
3682         attr = in_eeprom->offset & 0xffff;
3683
3684         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3685                                      in_eeprom->data, in_eeprom->length);
3686 }
3687
3688 /*
3689  * Initialization
3690  */
3691
3692 static const struct eth_dev_ops bnxt_dev_ops = {
3693         .dev_infos_get = bnxt_dev_info_get_op,
3694         .dev_close = bnxt_dev_close_op,
3695         .dev_configure = bnxt_dev_configure_op,
3696         .dev_start = bnxt_dev_start_op,
3697         .dev_stop = bnxt_dev_stop_op,
3698         .dev_set_link_up = bnxt_dev_set_link_up_op,
3699         .dev_set_link_down = bnxt_dev_set_link_down_op,
3700         .stats_get = bnxt_stats_get_op,
3701         .stats_reset = bnxt_stats_reset_op,
3702         .rx_queue_setup = bnxt_rx_queue_setup_op,
3703         .rx_queue_release = bnxt_rx_queue_release_op,
3704         .tx_queue_setup = bnxt_tx_queue_setup_op,
3705         .tx_queue_release = bnxt_tx_queue_release_op,
3706         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3707         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3708         .reta_update = bnxt_reta_update_op,
3709         .reta_query = bnxt_reta_query_op,
3710         .rss_hash_update = bnxt_rss_hash_update_op,
3711         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3712         .link_update = bnxt_link_update_op,
3713         .promiscuous_enable = bnxt_promiscuous_enable_op,
3714         .promiscuous_disable = bnxt_promiscuous_disable_op,
3715         .allmulticast_enable = bnxt_allmulticast_enable_op,
3716         .allmulticast_disable = bnxt_allmulticast_disable_op,
3717         .mac_addr_add = bnxt_mac_addr_add_op,
3718         .mac_addr_remove = bnxt_mac_addr_remove_op,
3719         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3720         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3721         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
3722         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
3723         .vlan_filter_set = bnxt_vlan_filter_set_op,
3724         .vlan_offload_set = bnxt_vlan_offload_set_op,
3725         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3726         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3727         .mtu_set = bnxt_mtu_set_op,
3728         .mac_addr_set = bnxt_set_default_mac_addr_op,
3729         .xstats_get = bnxt_dev_xstats_get_op,
3730         .xstats_get_names = bnxt_dev_xstats_get_names_op,
3731         .xstats_reset = bnxt_dev_xstats_reset_op,
3732         .fw_version_get = bnxt_fw_version_get,
3733         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3734         .rxq_info_get = bnxt_rxq_info_get_op,
3735         .txq_info_get = bnxt_txq_info_get_op,
3736         .dev_led_on = bnxt_dev_led_on_op,
3737         .dev_led_off = bnxt_dev_led_off_op,
3738         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3739         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3740         .rx_queue_count = bnxt_rx_queue_count_op,
3741         .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3742         .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3743         .rx_queue_start = bnxt_rx_queue_start,
3744         .rx_queue_stop = bnxt_rx_queue_stop,
3745         .tx_queue_start = bnxt_tx_queue_start,
3746         .tx_queue_stop = bnxt_tx_queue_stop,
3747         .filter_ctrl = bnxt_filter_ctrl_op,
3748         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3749         .get_eeprom_length    = bnxt_get_eeprom_length_op,
3750         .get_eeprom           = bnxt_get_eeprom_op,
3751         .set_eeprom           = bnxt_set_eeprom_op,
3752         .timesync_enable      = bnxt_timesync_enable,
3753         .timesync_disable     = bnxt_timesync_disable,
3754         .timesync_read_time   = bnxt_timesync_read_time,
3755         .timesync_write_time   = bnxt_timesync_write_time,
3756         .timesync_adjust_time = bnxt_timesync_adjust_time,
3757         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3758         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3759 };
3760
3761 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3762 {
3763         uint32_t offset;
3764
3765         /* Only pre-map the reset GRC registers using window 3 */
3766         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3767                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3768
3769         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3770
3771         return offset;
3772 }
3773
3774 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3775 {
3776         struct bnxt_error_recovery_info *info = bp->recovery_info;
3777         uint32_t reg_base = 0xffffffff;
3778         int i;
3779
3780         /* Only pre-map the monitoring GRC registers using window 2 */
3781         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3782                 uint32_t reg = info->status_regs[i];
3783
3784                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3785                         continue;
3786
3787                 if (reg_base == 0xffffffff)
3788                         reg_base = reg & 0xfffff000;
3789                 if ((reg & 0xfffff000) != reg_base)
3790                         return -ERANGE;
3791
3792                 /* Use mask 0xffc as the Lower 2 bits indicates
3793                  * address space location
3794                  */
3795                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3796                                                 (reg & 0xffc);
3797         }
3798
3799         if (reg_base == 0xffffffff)
3800                 return 0;
3801
3802         rte_write32(reg_base, (uint8_t *)bp->bar0 +
3803                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3804
3805         return 0;
3806 }
3807
3808 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3809 {
3810         struct bnxt_error_recovery_info *info = bp->recovery_info;
3811         uint32_t delay = info->delay_after_reset[index];
3812         uint32_t val = info->reset_reg_val[index];
3813         uint32_t reg = info->reset_reg[index];
3814         uint32_t type, offset;
3815
3816         type = BNXT_FW_STATUS_REG_TYPE(reg);
3817         offset = BNXT_FW_STATUS_REG_OFF(reg);
3818
3819         switch (type) {
3820         case BNXT_FW_STATUS_REG_TYPE_CFG:
3821                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3822                 break;
3823         case BNXT_FW_STATUS_REG_TYPE_GRC:
3824                 offset = bnxt_map_reset_regs(bp, offset);
3825                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3826                 break;
3827         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3828                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3829                 break;
3830         }
3831         /* wait on a specific interval of time until core reset is complete */
3832         if (delay)
3833                 rte_delay_ms(delay);
3834 }
3835
3836 static void bnxt_dev_cleanup(struct bnxt *bp)
3837 {
3838         bnxt_set_hwrm_link_config(bp, false);
3839         bp->link_info.link_up = 0;
3840         if (bp->dev_stopped == 0)
3841                 bnxt_dev_stop_op(bp->eth_dev);
3842
3843         bnxt_uninit_resources(bp, true);
3844 }
3845
3846 static int bnxt_restore_filters(struct bnxt *bp)
3847 {
3848         struct rte_eth_dev *dev = bp->eth_dev;
3849         int ret = 0;
3850
3851         if (dev->data->all_multicast)
3852                 ret = bnxt_allmulticast_enable_op(dev);
3853         if (dev->data->promiscuous)
3854                 ret = bnxt_promiscuous_enable_op(dev);
3855
3856         /* TODO restore other filters as well */
3857         return ret;
3858 }
3859
3860 static void bnxt_dev_recover(void *arg)
3861 {
3862         struct bnxt *bp = arg;
3863         int timeout = bp->fw_reset_max_msecs;
3864         int rc = 0;
3865
3866         /* Clear Error flag so that device re-init should happen */
3867         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3868
3869         do {
3870                 rc = bnxt_hwrm_ver_get(bp);
3871                 if (rc == 0)
3872                         break;
3873                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3874                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3875         } while (rc && timeout);
3876
3877         if (rc) {
3878                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3879                 goto err;
3880         }
3881
3882         rc = bnxt_init_resources(bp, true);
3883         if (rc) {
3884                 PMD_DRV_LOG(ERR,
3885                             "Failed to initialize resources after reset\n");
3886                 goto err;
3887         }
3888         /* clear reset flag as the device is initialized now */
3889         bp->flags &= ~BNXT_FLAG_FW_RESET;
3890
3891         rc = bnxt_dev_start_op(bp->eth_dev);
3892         if (rc) {
3893                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3894                 goto err;
3895         }
3896
3897         rc = bnxt_restore_filters(bp);
3898         if (rc)
3899                 goto err;
3900
3901         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3902         return;
3903 err:
3904         bp->flags |= BNXT_FLAG_FATAL_ERROR;
3905         bnxt_uninit_resources(bp, false);
3906         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3907 }
3908
3909 void bnxt_dev_reset_and_resume(void *arg)
3910 {
3911         struct bnxt *bp = arg;
3912         int rc;
3913
3914         bnxt_dev_cleanup(bp);
3915
3916         bnxt_wait_for_device_shutdown(bp);
3917
3918         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3919                                bnxt_dev_recover, (void *)bp);
3920         if (rc)
3921                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3922 }
3923
3924 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3925 {
3926         struct bnxt_error_recovery_info *info = bp->recovery_info;
3927         uint32_t reg = info->status_regs[index];
3928         uint32_t type, offset, val = 0;
3929
3930         type = BNXT_FW_STATUS_REG_TYPE(reg);
3931         offset = BNXT_FW_STATUS_REG_OFF(reg);
3932
3933         switch (type) {
3934         case BNXT_FW_STATUS_REG_TYPE_CFG:
3935                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3936                 break;
3937         case BNXT_FW_STATUS_REG_TYPE_GRC:
3938                 offset = info->mapped_status_regs[index];
3939                 /* FALLTHROUGH */
3940         case BNXT_FW_STATUS_REG_TYPE_BAR0:
3941                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3942                                        offset));
3943                 break;
3944         }
3945
3946         return val;
3947 }
3948
3949 static int bnxt_fw_reset_all(struct bnxt *bp)
3950 {
3951         struct bnxt_error_recovery_info *info = bp->recovery_info;
3952         uint32_t i;
3953         int rc = 0;
3954
3955         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3956                 /* Reset through master function driver */
3957                 for (i = 0; i < info->reg_array_cnt; i++)
3958                         bnxt_write_fw_reset_reg(bp, i);
3959                 /* Wait for time specified by FW after triggering reset */
3960                 rte_delay_ms(info->master_func_wait_period_after_reset);
3961         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3962                 /* Reset with the help of Kong processor */
3963                 rc = bnxt_hwrm_fw_reset(bp);
3964                 if (rc)
3965                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3966         }
3967
3968         return rc;
3969 }
3970
3971 static void bnxt_fw_reset_cb(void *arg)
3972 {
3973         struct bnxt *bp = arg;
3974         struct bnxt_error_recovery_info *info = bp->recovery_info;
3975         int rc = 0;
3976
3977         /* Only Master function can do FW reset */
3978         if (bnxt_is_master_func(bp) &&
3979             bnxt_is_recovery_enabled(bp)) {
3980                 rc = bnxt_fw_reset_all(bp);
3981                 if (rc) {
3982                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3983                         return;
3984                 }
3985         }
3986
3987         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3988          * EXCEPTION_FATAL_ASYNC event to all the functions
3989          * (including MASTER FUNC). After receiving this Async, all the active
3990          * drivers should treat this case as FW initiated recovery
3991          */
3992         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3993                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3994                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3995
3996                 /* To recover from error */
3997                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3998                                   (void *)bp);
3999         }
4000 }
4001
4002 /* Driver should poll FW heartbeat, reset_counter with the frequency
4003  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4004  * When the driver detects heartbeat stop or change in reset_counter,
4005  * it has to trigger a reset to recover from the error condition.
4006  * A “master PF” is the function who will have the privilege to
4007  * initiate the chimp reset. The master PF will be elected by the
4008  * firmware and will be notified through async message.
4009  */
4010 static void bnxt_check_fw_health(void *arg)
4011 {
4012         struct bnxt *bp = arg;
4013         struct bnxt_error_recovery_info *info = bp->recovery_info;
4014         uint32_t val = 0, wait_msec;
4015
4016         if (!info || !bnxt_is_recovery_enabled(bp) ||
4017             is_bnxt_in_error(bp))
4018                 return;
4019
4020         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4021         if (val == info->last_heart_beat)
4022                 goto reset;
4023
4024         info->last_heart_beat = val;
4025
4026         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4027         if (val != info->last_reset_counter)
4028                 goto reset;
4029
4030         info->last_reset_counter = val;
4031
4032         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4033                           bnxt_check_fw_health, (void *)bp);
4034
4035         return;
4036 reset:
4037         /* Stop DMA to/from device */
4038         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4039         bp->flags |= BNXT_FLAG_FW_RESET;
4040
4041         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4042
4043         if (bnxt_is_master_func(bp))
4044                 wait_msec = info->master_func_wait_period;
4045         else
4046                 wait_msec = info->normal_func_wait_period;
4047
4048         rte_eal_alarm_set(US_PER_MS * wait_msec,
4049                           bnxt_fw_reset_cb, (void *)bp);
4050 }
4051
4052 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4053 {
4054         uint32_t polling_freq;
4055
4056         if (!bnxt_is_recovery_enabled(bp))
4057                 return;
4058
4059         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4060                 return;
4061
4062         polling_freq = bp->recovery_info->driver_polling_freq;
4063
4064         rte_eal_alarm_set(US_PER_MS * polling_freq,
4065                           bnxt_check_fw_health, (void *)bp);
4066         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4067 }
4068
4069 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4070 {
4071         if (!bnxt_is_recovery_enabled(bp))
4072                 return;
4073
4074         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4075         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4076 }
4077
4078 static bool bnxt_vf_pciid(uint16_t id)
4079 {
4080         if (id == BROADCOM_DEV_ID_57304_VF ||
4081             id == BROADCOM_DEV_ID_57406_VF ||
4082             id == BROADCOM_DEV_ID_5731X_VF ||
4083             id == BROADCOM_DEV_ID_5741X_VF ||
4084             id == BROADCOM_DEV_ID_57414_VF ||
4085             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4086             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 ||
4087             id == BROADCOM_DEV_ID_58802_VF ||
4088             id == BROADCOM_DEV_ID_57500_VF1 ||
4089             id == BROADCOM_DEV_ID_57500_VF2)
4090                 return true;
4091         return false;
4092 }
4093
4094 bool bnxt_stratus_device(struct bnxt *bp)
4095 {
4096         uint16_t id = bp->pdev->id.device_id;
4097
4098         if (id == BROADCOM_DEV_ID_STRATUS_NIC ||
4099             id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
4100             id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
4101                 return true;
4102         return false;
4103 }
4104
4105 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4106 {
4107         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4108         struct bnxt *bp = eth_dev->data->dev_private;
4109
4110         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4111         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4112         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4113         if (!bp->bar0 || !bp->doorbell_base) {
4114                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4115                 return -ENODEV;
4116         }
4117
4118         bp->eth_dev = eth_dev;
4119         bp->pdev = pci_dev;
4120
4121         return 0;
4122 }
4123
4124 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp,
4125                                   struct bnxt_ctx_pg_info *ctx_pg,
4126                                   uint32_t mem_size,
4127                                   const char *suffix,
4128                                   uint16_t idx)
4129 {
4130         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4131         const struct rte_memzone *mz = NULL;
4132         char mz_name[RTE_MEMZONE_NAMESIZE];
4133         rte_iova_t mz_phys_addr;
4134         uint64_t valid_bits = 0;
4135         uint32_t sz;
4136         int i;
4137
4138         if (!mem_size)
4139                 return 0;
4140
4141         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4142                          BNXT_PAGE_SIZE;
4143         rmem->page_size = BNXT_PAGE_SIZE;
4144         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4145         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4146         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4147
4148         valid_bits = PTU_PTE_VALID;
4149
4150         if (rmem->nr_pages > 1) {
4151                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4152                          "bnxt_ctx_pg_tbl%s_%x_%d",
4153                          suffix, idx, bp->eth_dev->data->port_id);
4154                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4155                 mz = rte_memzone_lookup(mz_name);
4156                 if (!mz) {
4157                         mz = rte_memzone_reserve_aligned(mz_name,
4158                                                 rmem->nr_pages * 8,
4159                                                 SOCKET_ID_ANY,
4160                                                 RTE_MEMZONE_2MB |
4161                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4162                                                 RTE_MEMZONE_IOVA_CONTIG,
4163                                                 BNXT_PAGE_SIZE);
4164                         if (mz == NULL)
4165                                 return -ENOMEM;
4166                 }
4167
4168                 memset(mz->addr, 0, mz->len);
4169                 mz_phys_addr = mz->iova;
4170                 if ((unsigned long)mz->addr == mz_phys_addr) {
4171                         PMD_DRV_LOG(DEBUG,
4172                                     "physical address same as virtual\n");
4173                         PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4174                         mz_phys_addr = rte_mem_virt2iova(mz->addr);
4175                         if (mz_phys_addr == RTE_BAD_IOVA) {
4176                                 PMD_DRV_LOG(ERR,
4177                                         "unable to map addr to phys memory\n");
4178                                 return -ENOMEM;
4179                         }
4180                 }
4181                 rte_mem_lock_page(((char *)mz->addr));
4182
4183                 rmem->pg_tbl = mz->addr;
4184                 rmem->pg_tbl_map = mz_phys_addr;
4185                 rmem->pg_tbl_mz = mz;
4186         }
4187
4188         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4189                  suffix, idx, bp->eth_dev->data->port_id);
4190         mz = rte_memzone_lookup(mz_name);
4191         if (!mz) {
4192                 mz = rte_memzone_reserve_aligned(mz_name,
4193                                                  mem_size,
4194                                                  SOCKET_ID_ANY,
4195                                                  RTE_MEMZONE_1GB |
4196                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4197                                                  RTE_MEMZONE_IOVA_CONTIG,
4198                                                  BNXT_PAGE_SIZE);
4199                 if (mz == NULL)
4200                         return -ENOMEM;
4201         }
4202
4203         memset(mz->addr, 0, mz->len);
4204         mz_phys_addr = mz->iova;
4205         if ((unsigned long)mz->addr == mz_phys_addr) {
4206                 PMD_DRV_LOG(DEBUG,
4207                             "Memzone physical address same as virtual.\n");
4208                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4209                 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
4210                         rte_mem_lock_page(((char *)mz->addr) + sz);
4211                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4212                 if (mz_phys_addr == RTE_BAD_IOVA) {
4213                         PMD_DRV_LOG(ERR,
4214                                     "unable to map addr to phys memory\n");
4215                         return -ENOMEM;
4216                 }
4217         }
4218
4219         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4220                 rte_mem_lock_page(((char *)mz->addr) + sz);
4221                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4222                 rmem->dma_arr[i] = mz_phys_addr + sz;
4223
4224                 if (rmem->nr_pages > 1) {
4225                         if (i == rmem->nr_pages - 2 &&
4226                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4227                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4228                         else if (i == rmem->nr_pages - 1 &&
4229                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4230                                 valid_bits |= PTU_PTE_LAST;
4231
4232                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4233                                                            valid_bits);
4234                 }
4235         }
4236
4237         rmem->mz = mz;
4238         if (rmem->vmem_size)
4239                 rmem->vmem = (void **)mz->addr;
4240         rmem->dma_arr[0] = mz_phys_addr;
4241         return 0;
4242 }
4243
4244 static void bnxt_free_ctx_mem(struct bnxt *bp)
4245 {
4246         int i;
4247
4248         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4249                 return;
4250
4251         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4252         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4253         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4254         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4255         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4256         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4257         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4258         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4259         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4260         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4261         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4262
4263         for (i = 0; i < BNXT_MAX_Q; i++) {
4264                 if (bp->ctx->tqm_mem[i])
4265                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4266         }
4267
4268         rte_free(bp->ctx);
4269         bp->ctx = NULL;
4270 }
4271
4272 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4273
4274 #define min_t(type, x, y) ({                    \
4275         type __min1 = (x);                      \
4276         type __min2 = (y);                      \
4277         __min1 < __min2 ? __min1 : __min2; })
4278
4279 #define max_t(type, x, y) ({                    \
4280         type __max1 = (x);                      \
4281         type __max2 = (y);                      \
4282         __max1 > __max2 ? __max1 : __max2; })
4283
4284 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4285
4286 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4287 {
4288         struct bnxt_ctx_pg_info *ctx_pg;
4289         struct bnxt_ctx_mem_info *ctx;
4290         uint32_t mem_size, ena, entries;
4291         int i, rc;
4292
4293         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4294         if (rc) {
4295                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4296                 return rc;
4297         }
4298         ctx = bp->ctx;
4299         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4300                 return 0;
4301
4302         ctx_pg = &ctx->qp_mem;
4303         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4304         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4305         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4306         if (rc)
4307                 return rc;
4308
4309         ctx_pg = &ctx->srq_mem;
4310         ctx_pg->entries = ctx->srq_max_l2_entries;
4311         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4312         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4313         if (rc)
4314                 return rc;
4315
4316         ctx_pg = &ctx->cq_mem;
4317         ctx_pg->entries = ctx->cq_max_l2_entries;
4318         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4319         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4320         if (rc)
4321                 return rc;
4322
4323         ctx_pg = &ctx->vnic_mem;
4324         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4325                 ctx->vnic_max_ring_table_entries;
4326         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4327         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4328         if (rc)
4329                 return rc;
4330
4331         ctx_pg = &ctx->stat_mem;
4332         ctx_pg->entries = ctx->stat_max_entries;
4333         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4334         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4335         if (rc)
4336                 return rc;
4337
4338         entries = ctx->qp_max_l2_entries +
4339                   ctx->vnic_max_vnic_entries +
4340                   ctx->tqm_min_entries_per_ring;
4341         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4342         entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4343                           ctx->tqm_max_entries_per_ring);
4344         for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4345                 ctx_pg = ctx->tqm_mem[i];
4346                 /* use min tqm entries for now. */
4347                 ctx_pg->entries = entries;
4348                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4349                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4350                 if (rc)
4351                         return rc;
4352                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4353         }
4354
4355         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4356         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4357         if (rc)
4358                 PMD_DRV_LOG(ERR,
4359                             "Failed to configure context mem: rc = %d\n", rc);
4360         else
4361                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4362
4363         return rc;
4364 }
4365
4366 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4367 {
4368         struct rte_pci_device *pci_dev = bp->pdev;
4369         char mz_name[RTE_MEMZONE_NAMESIZE];
4370         const struct rte_memzone *mz = NULL;
4371         uint32_t total_alloc_len;
4372         rte_iova_t mz_phys_addr;
4373
4374         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4375                 return 0;
4376
4377         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4378                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4379                  pci_dev->addr.bus, pci_dev->addr.devid,
4380                  pci_dev->addr.function, "rx_port_stats");
4381         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4382         mz = rte_memzone_lookup(mz_name);
4383         total_alloc_len =
4384                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4385                                        sizeof(struct rx_port_stats_ext) + 512);
4386         if (!mz) {
4387                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4388                                          SOCKET_ID_ANY,
4389                                          RTE_MEMZONE_2MB |
4390                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4391                                          RTE_MEMZONE_IOVA_CONTIG);
4392                 if (mz == NULL)
4393                         return -ENOMEM;
4394         }
4395         memset(mz->addr, 0, mz->len);
4396         mz_phys_addr = mz->iova;
4397         if ((unsigned long)mz->addr == mz_phys_addr) {
4398                 PMD_DRV_LOG(DEBUG,
4399                             "Memzone physical address same as virtual.\n");
4400                 PMD_DRV_LOG(DEBUG,
4401                             "Using rte_mem_virt2iova()\n");
4402                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4403                 if (mz_phys_addr == RTE_BAD_IOVA) {
4404                         PMD_DRV_LOG(ERR,
4405                                     "Can't map address to physical memory\n");
4406                         return -ENOMEM;
4407                 }
4408         }
4409
4410         bp->rx_mem_zone = (const void *)mz;
4411         bp->hw_rx_port_stats = mz->addr;
4412         bp->hw_rx_port_stats_map = mz_phys_addr;
4413
4414         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4415                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4416                  pci_dev->addr.bus, pci_dev->addr.devid,
4417                  pci_dev->addr.function, "tx_port_stats");
4418         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4419         mz = rte_memzone_lookup(mz_name);
4420         total_alloc_len =
4421                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4422                                        sizeof(struct tx_port_stats_ext) + 512);
4423         if (!mz) {
4424                 mz = rte_memzone_reserve(mz_name,
4425                                          total_alloc_len,
4426                                          SOCKET_ID_ANY,
4427                                          RTE_MEMZONE_2MB |
4428                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4429                                          RTE_MEMZONE_IOVA_CONTIG);
4430                 if (mz == NULL)
4431                         return -ENOMEM;
4432         }
4433         memset(mz->addr, 0, mz->len);
4434         mz_phys_addr = mz->iova;
4435         if ((unsigned long)mz->addr == mz_phys_addr) {
4436                 PMD_DRV_LOG(DEBUG,
4437                             "Memzone physical address same as virtual\n");
4438                 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
4439                 mz_phys_addr = rte_mem_virt2iova(mz->addr);
4440                 if (mz_phys_addr == RTE_BAD_IOVA) {
4441                         PMD_DRV_LOG(ERR,
4442                                     "Can't map address to physical memory\n");
4443                         return -ENOMEM;
4444                 }
4445         }
4446
4447         bp->tx_mem_zone = (const void *)mz;
4448         bp->hw_tx_port_stats = mz->addr;
4449         bp->hw_tx_port_stats_map = mz_phys_addr;
4450         bp->flags |= BNXT_FLAG_PORT_STATS;
4451
4452         /* Display extended statistics if FW supports it */
4453         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4454             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4455             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4456                 return 0;
4457
4458         bp->hw_rx_port_stats_ext = (void *)
4459                 ((uint8_t *)bp->hw_rx_port_stats +
4460                  sizeof(struct rx_port_stats));
4461         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4462                 sizeof(struct rx_port_stats);
4463         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4464
4465         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4466             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4467                 bp->hw_tx_port_stats_ext = (void *)
4468                         ((uint8_t *)bp->hw_tx_port_stats +
4469                          sizeof(struct tx_port_stats));
4470                 bp->hw_tx_port_stats_ext_map =
4471                         bp->hw_tx_port_stats_map +
4472                         sizeof(struct tx_port_stats);
4473                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4474         }
4475
4476         return 0;
4477 }
4478
4479 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4480 {
4481         struct bnxt *bp = eth_dev->data->dev_private;
4482         int rc = 0;
4483
4484         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4485                                                RTE_ETHER_ADDR_LEN *
4486                                                bp->max_l2_ctx,
4487                                                0);
4488         if (eth_dev->data->mac_addrs == NULL) {
4489                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4490                 return -ENOMEM;
4491         }
4492
4493         if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4494                 if (BNXT_PF(bp))
4495                         return -EINVAL;
4496
4497                 /* Generate a random MAC address, if none was assigned by PF */
4498                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4499                 bnxt_eth_hw_addr_random(bp->mac_addr);
4500                 PMD_DRV_LOG(INFO,
4501                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4502                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4503                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4504
4505                 rc = bnxt_hwrm_set_mac(bp);
4506                 if (!rc)
4507                         memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4508                                RTE_ETHER_ADDR_LEN);
4509                 return rc;
4510         }
4511
4512         /* Copy the permanent MAC from the FUNC_QCAPS response */
4513         memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4514         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4515
4516         return rc;
4517 }
4518
4519 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4520 {
4521         int rc = 0;
4522
4523         /* MAC is already configured in FW */
4524         if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4525                 return 0;
4526
4527         /* Restore the old MAC configured */
4528         rc = bnxt_hwrm_set_mac(bp);
4529         if (rc)
4530                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4531
4532         return rc;
4533 }
4534
4535 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4536 {
4537         if (!BNXT_PF(bp))
4538                 return;
4539
4540 #define ALLOW_FUNC(x)   \
4541         { \
4542                 uint32_t arg = (x); \
4543                 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4544                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4545         }
4546
4547         /* Forward all requests if firmware is new enough */
4548         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4549              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4550             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4551                 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4552         } else {
4553                 PMD_DRV_LOG(WARNING,
4554                             "Firmware too old for VF mailbox functionality\n");
4555                 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4556         }
4557
4558         /*
4559          * The following are used for driver cleanup. If we disallow these,
4560          * VF drivers can't clean up cleanly.
4561          */
4562         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4563         ALLOW_FUNC(HWRM_VNIC_FREE);
4564         ALLOW_FUNC(HWRM_RING_FREE);
4565         ALLOW_FUNC(HWRM_RING_GRP_FREE);
4566         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4567         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4568         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4569         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4570         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4571 }
4572
4573 static int bnxt_init_fw(struct bnxt *bp)
4574 {
4575         uint16_t mtu;
4576         int rc = 0;
4577
4578         rc = bnxt_hwrm_ver_get(bp);
4579         if (rc)
4580                 return rc;
4581
4582         rc = bnxt_hwrm_func_reset(bp);
4583         if (rc)
4584                 return -EIO;
4585
4586         rc = bnxt_hwrm_vnic_qcaps(bp);
4587         if (rc)
4588                 return rc;
4589
4590         rc = bnxt_hwrm_queue_qportcfg(bp);
4591         if (rc)
4592                 return rc;
4593
4594         /* Get the MAX capabilities for this function.
4595          * This function also allocates context memory for TQM rings and
4596          * informs the firmware about this allocated backing store memory.
4597          */
4598         rc = bnxt_hwrm_func_qcaps(bp);
4599         if (rc)
4600                 return rc;
4601
4602         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4603         if (rc)
4604                 return rc;
4605
4606         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4607         if (rc)
4608                 return rc;
4609
4610         /* Get the adapter error recovery support info */
4611         rc = bnxt_hwrm_error_recovery_qcfg(bp);
4612         if (rc)
4613                 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
4614
4615         if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
4616             mtu != bp->eth_dev->data->mtu)
4617                 bp->eth_dev->data->mtu = mtu;
4618
4619         bnxt_hwrm_port_led_qcaps(bp);
4620
4621         return 0;
4622 }
4623
4624 static int
4625 bnxt_init_locks(struct bnxt *bp)
4626 {
4627         int err;
4628
4629         err = pthread_mutex_init(&bp->flow_lock, NULL);
4630         if (err)
4631                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4632         return err;
4633 }
4634
4635 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4636 {
4637         int rc;
4638
4639         rc = bnxt_init_fw(bp);
4640         if (rc)
4641                 return rc;
4642
4643         if (!reconfig_dev) {
4644                 rc = bnxt_setup_mac_addr(bp->eth_dev);
4645                 if (rc)
4646                         return rc;
4647         } else {
4648                 rc = bnxt_restore_dflt_mac(bp);
4649                 if (rc)
4650                         return rc;
4651         }
4652
4653         bnxt_config_vf_req_fwd(bp);
4654
4655         rc = bnxt_hwrm_func_driver_register(bp);
4656         if (rc) {
4657                 PMD_DRV_LOG(ERR, "Failed to register driver");
4658                 return -EBUSY;
4659         }
4660
4661         if (BNXT_PF(bp)) {
4662                 if (bp->pdev->max_vfs) {
4663                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4664                         if (rc) {
4665                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4666                                 return rc;
4667                         }
4668                 } else {
4669                         rc = bnxt_hwrm_allocate_pf_only(bp);
4670                         if (rc) {
4671                                 PMD_DRV_LOG(ERR,
4672                                             "Failed to allocate PF resources");
4673                                 return rc;
4674                         }
4675                 }
4676         }
4677
4678         rc = bnxt_alloc_mem(bp, reconfig_dev);
4679         if (rc)
4680                 return rc;
4681
4682         rc = bnxt_setup_int(bp);
4683         if (rc)
4684                 return rc;
4685
4686         bnxt_init_nic(bp);
4687
4688         rc = bnxt_request_int(bp);
4689         if (rc)
4690                 return rc;
4691
4692         rc = bnxt_init_locks(bp);
4693         if (rc)
4694                 return rc;
4695
4696         return 0;
4697 }
4698
4699 static int
4700 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4701 {
4702         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4703         static int version_printed;
4704         struct bnxt *bp;
4705         int rc;
4706
4707         if (version_printed++ == 0)
4708                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4709
4710         eth_dev->dev_ops = &bnxt_dev_ops;
4711         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4712         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4713
4714         /*
4715          * For secondary processes, we don't initialise any further
4716          * as primary has already done this work.
4717          */
4718         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4719                 return 0;
4720
4721         rte_eth_copy_pci_info(eth_dev, pci_dev);
4722
4723         bp = eth_dev->data->dev_private;
4724
4725         bp->dev_stopped = 1;
4726
4727         if (bnxt_vf_pciid(pci_dev->id.device_id))
4728                 bp->flags |= BNXT_FLAG_VF;
4729
4730         if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 ||
4731             pci_dev->id.device_id == BROADCOM_DEV_ID_57504 ||
4732             pci_dev->id.device_id == BROADCOM_DEV_ID_57502 ||
4733             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 ||
4734             pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2)
4735                 bp->flags |= BNXT_FLAG_THOR_CHIP;
4736
4737         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4738             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4739             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4740             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4741                 bp->flags |= BNXT_FLAG_STINGRAY;
4742
4743         rc = bnxt_init_board(eth_dev);
4744         if (rc) {
4745                 PMD_DRV_LOG(ERR,
4746                             "Failed to initialize board rc: %x\n", rc);
4747                 return rc;
4748         }
4749
4750         rc = bnxt_alloc_hwrm_resources(bp);
4751         if (rc) {
4752                 PMD_DRV_LOG(ERR,
4753                             "Failed to allocate hwrm resource rc: %x\n", rc);
4754                 goto error_free;
4755         }
4756         rc = bnxt_init_resources(bp, false);
4757         if (rc)
4758                 goto error_free;
4759
4760         rc = bnxt_alloc_stats_mem(bp);
4761         if (rc)
4762                 goto error_free;
4763
4764         PMD_DRV_LOG(INFO,
4765                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4766                     pci_dev->mem_resource[0].phys_addr,
4767                     pci_dev->mem_resource[0].addr);
4768
4769         return 0;
4770
4771 error_free:
4772         bnxt_dev_uninit(eth_dev);
4773         return rc;
4774 }
4775
4776 static void
4777 bnxt_uninit_locks(struct bnxt *bp)
4778 {
4779         pthread_mutex_destroy(&bp->flow_lock);
4780 }
4781
4782 static int
4783 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4784 {
4785         int rc;
4786
4787         bnxt_free_int(bp);
4788         bnxt_free_mem(bp, reconfig_dev);
4789         bnxt_hwrm_func_buf_unrgtr(bp);
4790         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4791         bp->flags &= ~BNXT_FLAG_REGISTERED;
4792         bnxt_free_ctx_mem(bp);
4793         if (!reconfig_dev) {
4794                 bnxt_free_hwrm_resources(bp);
4795
4796                 if (bp->recovery_info != NULL) {
4797                         rte_free(bp->recovery_info);
4798                         bp->recovery_info = NULL;
4799                 }
4800         }
4801
4802         rte_free(bp->ptp_cfg);
4803         bp->ptp_cfg = NULL;
4804         return rc;
4805 }
4806
4807 static int
4808 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4809 {
4810         struct bnxt *bp = eth_dev->data->dev_private;
4811         int rc;
4812
4813         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4814                 return -EPERM;
4815
4816         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4817
4818         rc = bnxt_uninit_resources(bp, false);
4819
4820         if (bp->grp_info != NULL) {
4821                 rte_free(bp->grp_info);
4822                 bp->grp_info = NULL;
4823         }
4824
4825         if (bp->tx_mem_zone) {
4826                 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
4827                 bp->tx_mem_zone = NULL;
4828         }
4829
4830         if (bp->rx_mem_zone) {
4831                 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
4832                 bp->rx_mem_zone = NULL;
4833         }
4834
4835         if (bp->dev_stopped == 0)
4836                 bnxt_dev_close_op(eth_dev);
4837         if (bp->pf.vf_info)
4838                 rte_free(bp->pf.vf_info);
4839         eth_dev->dev_ops = NULL;
4840         eth_dev->rx_pkt_burst = NULL;
4841         eth_dev->tx_pkt_burst = NULL;
4842
4843         bnxt_uninit_locks(bp);
4844
4845         return rc;
4846 }
4847
4848 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4849         struct rte_pci_device *pci_dev)
4850 {
4851         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4852                 bnxt_dev_init);
4853 }
4854
4855 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4856 {
4857         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4858                 return rte_eth_dev_pci_generic_remove(pci_dev,
4859                                 bnxt_dev_uninit);
4860         else
4861                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4862 }
4863
4864 static struct rte_pci_driver bnxt_rte_pmd = {
4865         .id_table = bnxt_pci_id_map,
4866         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4867         .probe = bnxt_pci_probe,
4868         .remove = bnxt_pci_remove,
4869 };
4870
4871 static bool
4872 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4873 {
4874         if (strcmp(dev->device->driver->name, drv->driver.name))
4875                 return false;
4876
4877         return true;
4878 }
4879
4880 bool is_bnxt_supported(struct rte_eth_dev *dev)
4881 {
4882         return is_device_supported(dev, &bnxt_rte_pmd);
4883 }
4884
4885 RTE_INIT(bnxt_init_log)
4886 {
4887         bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4888         if (bnxt_logtype_driver >= 0)
4889                 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4890 }
4891
4892 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4893 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4894 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");