drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <rte_ethdev_driver.h>
  11 #include <rte_ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16
  17 #include "bnxt.h"
  18 #include "bnxt_filter.h"
  19 #include "bnxt_hwrm.h"
  20 #include "bnxt_irq.h"
  21 #include "bnxt_reps.h"
  22 #include "bnxt_ring.h"
  23 #include "bnxt_rxq.h"
  24 #include "bnxt_rxr.h"
  25 #include "bnxt_stats.h"
  26 #include "bnxt_txq.h"
  27 #include "bnxt_txr.h"
  28 #include "bnxt_vnic.h"
  29 #include "hsi_struct_def_dpdk.h"
  30 #include "bnxt_nvm_defs.h"
  31 #include "bnxt_tf_common.h"
  32 #include "ulp_flow_db.h"
  33
  34 #define DRV_MODULE_NAME         "bnxt"
  35 static const char bnxt_version[] =
  36         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  37
  38 /*
  39  * The set of PCI devices this driver supports
  40  */
  41 static const struct rte_pci_id bnxt_pci_id_map[] = {
  42         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  43                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  47         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  87         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  88         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  89         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  90         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  91         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  92         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  93         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  94         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  95         { .vendor_id = 0, /* sentinel */ },
  96 };
  97
  98 #define BNXT_DEVARG_TRUFLOW     "host-based-truflow"
  99 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
 100 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
 101 #define BNXT_DEVARG_REPRESENTOR "representor"
 102
 103 static const char *const bnxt_dev_args[] = {
 104         BNXT_DEVARG_REPRESENTOR,
 105         BNXT_DEVARG_TRUFLOW,
 106         BNXT_DEVARG_FLOW_XSTAT,
 107         BNXT_DEVARG_MAX_NUM_KFLOWS,
 108         NULL
 109 };
 110
 111 /*
 112  * truflow == false to disable the feature
 113  * truflow == true to enable the feature
 114  */
 115 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow)    ((truflow) > 1)
 116
 117 /*
 118  * flow_xstat == false to disable the feature
 119  * flow_xstat == true to enable the feature
 120  */
 121 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 122
 123 /*
 124  * max_num_kflows must be >= 32
 125  * and must be a power-of-2 supported value
 126  * return: 1 -> invalid
 127  *         0 -> valid
 128  */
 129 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 130 {
 131         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 132                 return 1;
 133         return 0;
 134 }
 135
 136 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 137 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 138 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 139 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 140 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 141 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 142 static void bnxt_dev_recover(void *arg);
 143 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 144 static void bnxt_free_rep_info(struct bnxt *bp);
 145
 146 int is_bnxt_in_error(struct bnxt *bp)
 147 {
 148         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 149                 return -EIO;
 150         if (bp->flags & BNXT_FLAG_FW_RESET)
 151                 return -EBUSY;
 152
 153         return 0;
 154 }
 155
 156 /***********************/
 157
 158 /*
 159  * High level utility functions
 160  */
 161
 162 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 163 {
 164         if (!BNXT_CHIP_THOR(bp))
 165                 return 1;
 166
 167         return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
 168                                   BNXT_RSS_ENTRIES_PER_CTX_THOR) /
 169                                     BNXT_RSS_ENTRIES_PER_CTX_THOR;
 170 }
 171
 172 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 173 {
 174         if (!BNXT_CHIP_THOR(bp))
 175                 return HW_HASH_INDEX_SIZE;
 176
 177         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
 178 }
 179
 180 static void bnxt_free_parent_info(struct bnxt *bp)
 181 {
 182         rte_free(bp->parent);
 183 }
 184
 185 static void bnxt_free_pf_info(struct bnxt *bp)
 186 {
 187         rte_free(bp->pf);
 188 }
 189
 190 static void bnxt_free_link_info(struct bnxt *bp)
 191 {
 192         rte_free(bp->link_info);
 193 }
 194
 195 static void bnxt_free_leds_info(struct bnxt *bp)
 196 {
 197         if (BNXT_VF(bp))
 198                 return;
 199
 200         rte_free(bp->leds);
 201         bp->leds = NULL;
 202 }
 203
 204 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 205 {
 206         rte_free(bp->flow_stat);
 207         bp->flow_stat = NULL;
 208 }
 209
 210 static void bnxt_free_cos_queues(struct bnxt *bp)
 211 {
 212         rte_free(bp->rx_cos_queue);
 213         rte_free(bp->tx_cos_queue);
 214 }
 215
 216 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 217 {
 218         bnxt_free_filter_mem(bp);
 219         bnxt_free_vnic_attributes(bp);
 220         bnxt_free_vnic_mem(bp);
 221
 222         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 223          * If the number of rings change across fw update,
 224          * we don't have much choice except to warn the user.
 225          */
 226         if (!reconfig) {
 227                 bnxt_free_stats(bp);
 228                 bnxt_free_tx_rings(bp);
 229                 bnxt_free_rx_rings(bp);
 230         }
 231         bnxt_free_async_cp_ring(bp);
 232         bnxt_free_rxtx_nq_ring(bp);
 233
 234         rte_free(bp->grp_info);
 235         bp->grp_info = NULL;
 236 }
 237
 238 static int bnxt_alloc_parent_info(struct bnxt *bp)
 239 {
 240         bp->parent = rte_zmalloc("bnxt_parent_info",
 241                                  sizeof(struct bnxt_parent_info), 0);
 242         if (bp->parent == NULL)
 243                 return -ENOMEM;
 244
 245         return 0;
 246 }
 247
 248 static int bnxt_alloc_pf_info(struct bnxt *bp)
 249 {
 250         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 251         if (bp->pf == NULL)
 252                 return -ENOMEM;
 253
 254         return 0;
 255 }
 256
 257 static int bnxt_alloc_link_info(struct bnxt *bp)
 258 {
 259         bp->link_info =
 260                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 261         if (bp->link_info == NULL)
 262                 return -ENOMEM;
 263
 264         return 0;
 265 }
 266
 267 static int bnxt_alloc_leds_info(struct bnxt *bp)
 268 {
 269         if (BNXT_VF(bp))
 270                 return 0;
 271
 272         bp->leds = rte_zmalloc("bnxt_leds",
 273                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 274                                0);
 275         if (bp->leds == NULL)
 276                 return -ENOMEM;
 277
 278         return 0;
 279 }
 280
 281 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 282 {
 283         bp->rx_cos_queue =
 284                 rte_zmalloc("bnxt_rx_cosq",
 285                             BNXT_COS_QUEUE_COUNT *
 286                             sizeof(struct bnxt_cos_queue_info),
 287                             0);
 288         if (bp->rx_cos_queue == NULL)
 289                 return -ENOMEM;
 290
 291         bp->tx_cos_queue =
 292                 rte_zmalloc("bnxt_tx_cosq",
 293                             BNXT_COS_QUEUE_COUNT *
 294                             sizeof(struct bnxt_cos_queue_info),
 295                             0);
 296         if (bp->tx_cos_queue == NULL)
 297                 return -ENOMEM;
 298
 299         return 0;
 300 }
 301
 302 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 303 {
 304         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 305                                     sizeof(struct bnxt_flow_stat_info), 0);
 306         if (bp->flow_stat == NULL)
 307                 return -ENOMEM;
 308
 309         return 0;
 310 }
 311
 312 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 313 {
 314         int rc;
 315
 316         rc = bnxt_alloc_ring_grps(bp);
 317         if (rc)
 318                 goto alloc_mem_err;
 319
 320         rc = bnxt_alloc_async_ring_struct(bp);
 321         if (rc)
 322                 goto alloc_mem_err;
 323
 324         rc = bnxt_alloc_vnic_mem(bp);
 325         if (rc)
 326                 goto alloc_mem_err;
 327
 328         rc = bnxt_alloc_vnic_attributes(bp);
 329         if (rc)
 330                 goto alloc_mem_err;
 331
 332         rc = bnxt_alloc_filter_mem(bp);
 333         if (rc)
 334                 goto alloc_mem_err;
 335
 336         rc = bnxt_alloc_async_cp_ring(bp);
 337         if (rc)
 338                 goto alloc_mem_err;
 339
 340         rc = bnxt_alloc_rxtx_nq_ring(bp);
 341         if (rc)
 342                 goto alloc_mem_err;
 343
 344         if (BNXT_FLOW_XSTATS_EN(bp)) {
 345                 rc = bnxt_alloc_flow_stats_info(bp);
 346                 if (rc)
 347                         goto alloc_mem_err;
 348         }
 349
 350         return 0;
 351
 352 alloc_mem_err:
 353         bnxt_free_mem(bp, reconfig);
 354         return rc;
 355 }
 356
 357 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 358 {
 359         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 360         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 361         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 362         struct bnxt_rx_queue *rxq;
 363         unsigned int j;
 364         int rc;
 365
 366         rc = bnxt_vnic_grp_alloc(bp, vnic);
 367         if (rc)
 368                 goto err_out;
 369
 370         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 371                     vnic_id, vnic, vnic->fw_grp_ids);
 372
 373         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 374         if (rc)
 375                 goto err_out;
 376
 377         /* Alloc RSS context only if RSS mode is enabled */
 378         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 379                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 380
 381                 rc = 0;
 382                 for (j = 0; j < nr_ctxs; j++) {
 383                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 384                         if (rc)
 385                                 break;
 386                 }
 387                 if (rc) {
 388                         PMD_DRV_LOG(ERR,
 389                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 390                                     vnic_id, j, rc);
 391                         goto err_out;
 392                 }
 393                 vnic->num_lb_ctxts = nr_ctxs;
 394         }
 395
 396         /*
 397          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 398          * setting is not available at this time, it will not be
 399          * configured correctly in the CFA.
 400          */
 401         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 402                 vnic->vlan_strip = true;
 403         else
 404                 vnic->vlan_strip = false;
 405
 406         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 407         if (rc)
 408                 goto err_out;
 409
 410         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 411         if (rc)
 412                 goto err_out;
 413
 414         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 415                 rxq = bp->eth_dev->data->rx_queues[j];
 416
 417                 PMD_DRV_LOG(DEBUG,
 418                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 419                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 420
 421                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 422                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 423                 else
 424                         vnic->rx_queue_cnt++;
 425         }
 426
 427         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 428
 429         rc = bnxt_vnic_rss_configure(bp, vnic);
 430         if (rc)
 431                 goto err_out;
 432
 433         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 434
 435         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
 436                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
 437         else
 438                 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
 439
 440         return 0;
 441 err_out:
 442         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 443                     vnic_id, rc);
 444         return rc;
 445 }
 446
 447 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 448 {
 449         int rc = 0;
 450
 451         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 452                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 453         if (rc)
 454                 return rc;
 455
 456         PMD_DRV_LOG(DEBUG,
 457                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 458                     " rx_fc_in_tbl.ctx_id = %d\n",
 459                     bp->flow_stat->rx_fc_in_tbl.va,
 460                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 461                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 462
 463         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 464                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 465         if (rc)
 466                 return rc;
 467
 468         PMD_DRV_LOG(DEBUG,
 469                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 470                     " rx_fc_out_tbl.ctx_id = %d\n",
 471                     bp->flow_stat->rx_fc_out_tbl.va,
 472                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 473                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 474
 475         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 476                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 477         if (rc)
 478                 return rc;
 479
 480         PMD_DRV_LOG(DEBUG,
 481                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 482                     " tx_fc_in_tbl.ctx_id = %d\n",
 483                     bp->flow_stat->tx_fc_in_tbl.va,
 484                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 485                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 486
 487         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 488                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 489         if (rc)
 490                 return rc;
 491
 492         PMD_DRV_LOG(DEBUG,
 493                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 494                     " tx_fc_out_tbl.ctx_id = %d\n",
 495                     bp->flow_stat->tx_fc_out_tbl.va,
 496                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 497                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 498
 499         memset(bp->flow_stat->rx_fc_out_tbl.va,
 500                0,
 501                bp->flow_stat->rx_fc_out_tbl.size);
 502         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 503                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 504                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 505                                        bp->flow_stat->max_fc,
 506                                        true);
 507         if (rc)
 508                 return rc;
 509
 510         memset(bp->flow_stat->tx_fc_out_tbl.va,
 511                0,
 512                bp->flow_stat->tx_fc_out_tbl.size);
 513         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 514                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 515                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 516                                        bp->flow_stat->max_fc,
 517                                        true);
 518
 519         return rc;
 520 }
 521
 522 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
 523                                   struct bnxt_ctx_mem_buf_info *ctx)
 524 {
 525         if (!ctx)
 526                 return -EINVAL;
 527
 528         ctx->va = rte_zmalloc(type, size, 0);
 529         if (ctx->va == NULL)
 530                 return -ENOMEM;
 531         rte_mem_lock_page(ctx->va);
 532         ctx->size = size;
 533         ctx->dma = rte_mem_virt2iova(ctx->va);
 534         if (ctx->dma == RTE_BAD_IOVA)
 535                 return -ENOMEM;
 536
 537         return 0;
 538 }
 539
 540 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 541 {
 542         struct rte_pci_device *pdev = bp->pdev;
 543         char type[RTE_MEMZONE_NAMESIZE];
 544         uint16_t max_fc;
 545         int rc = 0;
 546
 547         max_fc = bp->flow_stat->max_fc;
 548
 549         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 550                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 551         /* 4 bytes for each counter-id */
 552         rc = bnxt_alloc_ctx_mem_buf(type,
 553                                     max_fc * 4,
 554                                     &bp->flow_stat->rx_fc_in_tbl);
 555         if (rc)
 556                 return rc;
 557
 558         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 559                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 560         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 561         rc = bnxt_alloc_ctx_mem_buf(type,
 562                                     max_fc * 16,
 563                                     &bp->flow_stat->rx_fc_out_tbl);
 564         if (rc)
 565                 return rc;
 566
 567         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 568                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 569         /* 4 bytes for each counter-id */
 570         rc = bnxt_alloc_ctx_mem_buf(type,
 571                                     max_fc * 4,
 572                                     &bp->flow_stat->tx_fc_in_tbl);
 573         if (rc)
 574                 return rc;
 575
 576         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 577                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 578         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 579         rc = bnxt_alloc_ctx_mem_buf(type,
 580                                     max_fc * 16,
 581                                     &bp->flow_stat->tx_fc_out_tbl);
 582         if (rc)
 583                 return rc;
 584
 585         rc = bnxt_register_fc_ctx_mem(bp);
 586
 587         return rc;
 588 }
 589
 590 static int bnxt_init_ctx_mem(struct bnxt *bp)
 591 {
 592         int rc = 0;
 593
 594         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 595             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 596             !BNXT_FLOW_XSTATS_EN(bp))
 597                 return 0;
 598
 599         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 600         if (rc)
 601                 return rc;
 602
 603         rc = bnxt_init_fc_ctx_mem(bp);
 604
 605         return rc;
 606 }
 607
 608 static int bnxt_update_phy_setting(struct bnxt *bp)
 609 {
 610         struct rte_eth_link new;
 611         int rc;
 612
 613         rc = bnxt_get_hwrm_link_config(bp, &new);
 614         if (rc) {
 615                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 616                 return rc;
 617         }
 618
 619         /*
 620          * On BCM957508-N2100 adapters, FW will not allow any user other
 621          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 622          * always returns link up. Force phy update always in that case.
 623          */
 624         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 625                 rc = bnxt_set_hwrm_link_config(bp, true);
 626                 if (rc) {
 627                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 628                         return rc;
 629                 }
 630         }
 631
 632         return rc;
 633 }
 634
 635 static int bnxt_init_chip(struct bnxt *bp)
 636 {
 637         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 638         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 639         uint32_t intr_vector = 0;
 640         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 641         uint32_t vec = BNXT_MISC_VEC_ID;
 642         unsigned int i, j;
 643         int rc;
 644
 645         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 646                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 647                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 648                 bp->flags |= BNXT_FLAG_JUMBO;
 649         } else {
 650                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 651                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 652                 bp->flags &= ~BNXT_FLAG_JUMBO;
 653         }
 654
 655         /* THOR does not support ring groups.
 656          * But we will use the array to save RSS context IDs.
 657          */
 658         if (BNXT_CHIP_THOR(bp))
 659                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
 660
 661         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 662         if (rc) {
 663                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 664                 goto err_out;
 665         }
 666
 667         rc = bnxt_alloc_hwrm_rings(bp);
 668         if (rc) {
 669                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 670                 goto err_out;
 671         }
 672
 673         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 674         if (rc) {
 675                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 676                 goto err_out;
 677         }
 678
 679         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 680                 goto skip_cosq_cfg;
 681
 682         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 683                 if (bp->rx_cos_queue[i].id != 0xff) {
 684                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 685
 686                         if (!vnic) {
 687                                 PMD_DRV_LOG(ERR,
 688                                             "Num pools more than FW profile\n");
 689                                 rc = -EINVAL;
 690                                 goto err_out;
 691                         }
 692                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 693                         bp->rx_cosq_cnt++;
 694                 }
 695         }
 696
 697 skip_cosq_cfg:
 698         rc = bnxt_mq_rx_configure(bp);
 699         if (rc) {
 700                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 701                 goto err_out;
 702         }
 703
 704         /* VNIC configuration */
 705         for (i = 0; i < bp->nr_vnics; i++) {
 706                 rc = bnxt_setup_one_vnic(bp, i);
 707                 if (rc)
 708                         goto err_out;
 709         }
 710
 711         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 712         if (rc) {
 713                 PMD_DRV_LOG(ERR,
 714                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 715                 goto err_out;
 716         }
 717
 718         /* check and configure queue intr-vector mapping */
 719         if ((rte_intr_cap_multiple(intr_handle) ||
 720              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 721             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 722                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 723                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 724                 if (intr_vector > bp->rx_cp_nr_rings) {
 725                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 726                                         bp->rx_cp_nr_rings);
 727                         return -ENOTSUP;
 728                 }
 729                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 730                 if (rc)
 731                         return rc;
 732         }
 733
 734         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 735                 intr_handle->intr_vec =
 736                         rte_zmalloc("intr_vec",
 737                                     bp->eth_dev->data->nb_rx_queues *
 738                                     sizeof(int), 0);
 739                 if (intr_handle->intr_vec == NULL) {
 740                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 741                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 742                         rc = -ENOMEM;
 743                         goto err_disable;
 744                 }
 745                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 746                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 747                          intr_handle->intr_vec, intr_handle->nb_efd,
 748                         intr_handle->max_intr);
 749                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 750                      queue_id++) {
 751                         intr_handle->intr_vec[queue_id] =
 752                                                         vec + BNXT_RX_VEC_START;
 753                         if (vec < base + intr_handle->nb_efd - 1)
 754                                 vec++;
 755                 }
 756         }
 757
 758         /* enable uio/vfio intr/eventfd mapping */
 759         rc = rte_intr_enable(intr_handle);
 760 #ifndef RTE_EXEC_ENV_FREEBSD
 761         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 762         if (rc)
 763                 goto err_free;
 764 #endif
 765
 766         rc = bnxt_update_phy_setting(bp);
 767         if (rc)
 768                 goto err_free;
 769
 770         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 771         if (!bp->mark_table)
 772                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 773
 774         return 0;
 775
 776 err_free:
 777         rte_free(intr_handle->intr_vec);
 778 err_disable:
 779         rte_intr_efd_disable(intr_handle);
 780 err_out:
 781         /* Some of the error status returned by FW may not be from errno.h */
 782         if (rc > 0)
 783                 rc = -EIO;
 784
 785         return rc;
 786 }
 787
 788 static int bnxt_shutdown_nic(struct bnxt *bp)
 789 {
 790         bnxt_free_all_hwrm_resources(bp);
 791         bnxt_free_all_filters(bp);
 792         bnxt_free_all_vnics(bp);
 793         return 0;
 794 }
 795
 796 /*
 797  * Device configuration and status function
 798  */
 799
 800 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 801 {
 802         uint32_t link_speed = bp->link_info->support_speeds;
 803         uint32_t speed_capa = 0;
 804
 805         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 806                 speed_capa |= ETH_LINK_SPEED_100M;
 807         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 808                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 809         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 810                 speed_capa |= ETH_LINK_SPEED_1G;
 811         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 812                 speed_capa |= ETH_LINK_SPEED_2_5G;
 813         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 814                 speed_capa |= ETH_LINK_SPEED_10G;
 815         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 816                 speed_capa |= ETH_LINK_SPEED_20G;
 817         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 818                 speed_capa |= ETH_LINK_SPEED_25G;
 819         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 820                 speed_capa |= ETH_LINK_SPEED_40G;
 821         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 822                 speed_capa |= ETH_LINK_SPEED_50G;
 823         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 824                 speed_capa |= ETH_LINK_SPEED_100G;
 825         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB)
 826                 speed_capa |= ETH_LINK_SPEED_200G;
 827
 828         if (bp->link_info->auto_mode ==
 829             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 830                 speed_capa |= ETH_LINK_SPEED_FIXED;
 831         else
 832                 speed_capa |= ETH_LINK_SPEED_AUTONEG;
 833
 834         return speed_capa;
 835 }
 836
 837 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 838                                 struct rte_eth_dev_info *dev_info)
 839 {
 840         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 841         struct bnxt *bp = eth_dev->data->dev_private;
 842         uint16_t max_vnics, i, j, vpool, vrxq;
 843         unsigned int max_rx_rings;
 844         int rc;
 845
 846         rc = is_bnxt_in_error(bp);
 847         if (rc)
 848                 return rc;
 849
 850         /* MAC Specifics */
 851         dev_info->max_mac_addrs = bp->max_l2_ctx;
 852         dev_info->max_hash_mac_addrs = 0;
 853
 854         /* PF/VF specifics */
 855         if (BNXT_PF(bp))
 856                 dev_info->max_vfs = pdev->max_vfs;
 857
 858         max_rx_rings = BNXT_MAX_RINGS(bp);
 859         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 860         dev_info->max_rx_queues = max_rx_rings;
 861         dev_info->max_tx_queues = max_rx_rings;
 862         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 863         dev_info->hash_key_size = 40;
 864         max_vnics = bp->max_vnics;
 865
 866         /* MTU specifics */
 867         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 868         dev_info->max_mtu = BNXT_MAX_MTU;
 869
 870         /* Fast path specifics */
 871         dev_info->min_rx_bufsize = 1;
 872         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
 873
 874         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
 875         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
 876                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
 877         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
 878         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
 879
 880         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
 881
 882         /* *INDENT-OFF* */
 883         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 884                 .rx_thresh = {
 885                         .pthresh = 8,
 886                         .hthresh = 8,
 887                         .wthresh = 0,
 888                 },
 889                 .rx_free_thresh = 32,
 890                 /* If no descriptors available, pkts are dropped by default */
 891                 .rx_drop_en = 1,
 892         };
 893
 894         dev_info->default_txconf = (struct rte_eth_txconf) {
 895                 .tx_thresh = {
 896                         .pthresh = 32,
 897                         .hthresh = 0,
 898                         .wthresh = 0,
 899                 },
 900                 .tx_free_thresh = 32,
 901                 .tx_rs_thresh = 32,
 902         };
 903         eth_dev->data->dev_conf.intr_conf.lsc = 1;
 904
 905         eth_dev->data->dev_conf.intr_conf.rxq = 1;
 906         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 907         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
 908         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
 909         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
 910
 911         /* *INDENT-ON* */
 912
 913         /*
 914          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
 915          *       need further investigation.
 916          */
 917
 918         /* VMDq resources */
 919         vpool = 64; /* ETH_64_POOLS */
 920         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
 921         for (i = 0; i < 4; vpool >>= 1, i++) {
 922                 if (max_vnics > vpool) {
 923                         for (j = 0; j < 5; vrxq >>= 1, j++) {
 924                                 if (dev_info->max_rx_queues > vrxq) {
 925                                         if (vpool > vrxq)
 926                                                 vpool = vrxq;
 927                                         goto found;
 928                                 }
 929                         }
 930                         /* Not enough resources to support VMDq */
 931                         break;
 932                 }
 933         }
 934         /* Not enough resources to support VMDq */
 935         vpool = 0;
 936         vrxq = 0;
 937 found:
 938         dev_info->max_vmdq_pools = vpool;
 939         dev_info->vmdq_queue_num = vrxq;
 940
 941         dev_info->vmdq_pool_base = 0;
 942         dev_info->vmdq_queue_base = 0;
 943
 944         return 0;
 945 }
 946
 947 /* Configure the device based on the configuration provided */
 948 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
 949 {
 950         struct bnxt *bp = eth_dev->data->dev_private;
 951         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 952         int rc;
 953
 954         bp->rx_queues = (void *)eth_dev->data->rx_queues;
 955         bp->tx_queues = (void *)eth_dev->data->tx_queues;
 956         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
 957         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
 958
 959         rc = is_bnxt_in_error(bp);
 960         if (rc)
 961                 return rc;
 962
 963         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
 964                 rc = bnxt_hwrm_check_vf_rings(bp);
 965                 if (rc) {
 966                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
 967                         return -ENOSPC;
 968                 }
 969
 970                 /* If a resource has already been allocated - in this case
 971                  * it is the async completion ring, free it. Reallocate it after
 972                  * resource reservation. This will ensure the resource counts
 973                  * are calculated correctly.
 974                  */
 975
 976                 pthread_mutex_lock(&bp->def_cp_lock);
 977
 978                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 979                         bnxt_disable_int(bp);
 980                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
 981                 }
 982
 983                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
 984                 if (rc) {
 985                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
 986                         pthread_mutex_unlock(&bp->def_cp_lock);
 987                         return -ENOSPC;
 988                 }
 989
 990                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
 991                         rc = bnxt_alloc_async_cp_ring(bp);
 992                         if (rc) {
 993                                 pthread_mutex_unlock(&bp->def_cp_lock);
 994                                 return rc;
 995                         }
 996                         bnxt_enable_int(bp);
 997                 }
 998
 999                 pthread_mutex_unlock(&bp->def_cp_lock);
1000         } else {
1001                 /* legacy driver needs to get updated values */
1002                 rc = bnxt_hwrm_func_qcaps(bp);
1003                 if (rc) {
1004                         PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
1005                         return rc;
1006                 }
1007         }
1008
1009         /* Inherit new configurations */
1010         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1011             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1012             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1013                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1014             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1015             bp->max_stat_ctx)
1016                 goto resource_error;
1017
1018         if (BNXT_HAS_RING_GRPS(bp) &&
1019             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1020                 goto resource_error;
1021
1022         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1023             bp->max_vnics < eth_dev->data->nb_rx_queues)
1024                 goto resource_error;
1025
1026         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1027         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1028
1029         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1030                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1031         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1032
1033         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1034                 eth_dev->data->mtu =
1035                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1036                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1037                         BNXT_NUM_VLANS;
1038                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1039         }
1040         return 0;
1041
1042 resource_error:
1043         PMD_DRV_LOG(ERR,
1044                     "Insufficient resources to support requested config\n");
1045         PMD_DRV_LOG(ERR,
1046                     "Num Queues Requested: Tx %d, Rx %d\n",
1047                     eth_dev->data->nb_tx_queues,
1048                     eth_dev->data->nb_rx_queues);
1049         PMD_DRV_LOG(ERR,
1050                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1051                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1052                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1053         return -ENOSPC;
1054 }
1055
1056 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1057 {
1058         struct rte_eth_link *link = &eth_dev->data->dev_link;
1059
1060         if (link->link_status)
1061                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1062                         eth_dev->data->port_id,
1063                         (uint32_t)link->link_speed,
1064                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1065                         ("full-duplex") : ("half-duplex\n"));
1066         else
1067                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1068                         eth_dev->data->port_id);
1069 }
1070
1071 /*
1072  * Determine whether the current configuration requires support for scattered
1073  * receive; return 1 if scattered receive is required and 0 if not.
1074  */
1075 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1076 {
1077         uint16_t buf_size;
1078         int i;
1079
1080         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1081                 return 1;
1082
1083         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1084                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1085
1086                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1087                                       RTE_PKTMBUF_HEADROOM);
1088                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1089                         return 1;
1090         }
1091         return 0;
1092 }
1093
1094 static eth_rx_burst_t
1095 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1096 {
1097         struct bnxt *bp = eth_dev->data->dev_private;
1098
1099 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1100 #ifndef RTE_LIBRTE_IEEE1588
1101         /*
1102          * Vector mode receive can be enabled only if scatter rx is not
1103          * in use and rx offloads are limited to VLAN stripping and
1104          * CRC stripping.
1105          */
1106         if (!eth_dev->data->scattered_rx &&
1107             !(eth_dev->data->dev_conf.rxmode.offloads &
1108               ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1109                 DEV_RX_OFFLOAD_KEEP_CRC |
1110                 DEV_RX_OFFLOAD_JUMBO_FRAME |
1111                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1112                 DEV_RX_OFFLOAD_UDP_CKSUM |
1113                 DEV_RX_OFFLOAD_TCP_CKSUM |
1114                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1115                 DEV_RX_OFFLOAD_RSS_HASH |
1116                 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1117             !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp)) {
1118                 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1119                             eth_dev->data->port_id);
1120                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1121                 return bnxt_recv_pkts_vec;
1122         }
1123         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1124                     eth_dev->data->port_id);
1125         PMD_DRV_LOG(INFO,
1126                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1127                     eth_dev->data->port_id,
1128                     eth_dev->data->scattered_rx,
1129                     eth_dev->data->dev_conf.rxmode.offloads);
1130 #endif
1131 #endif
1132         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1133         return bnxt_recv_pkts;
1134 }
1135
1136 static eth_tx_burst_t
1137 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1138 {
1139 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1140 #ifndef RTE_LIBRTE_IEEE1588
1141         struct bnxt *bp = eth_dev->data->dev_private;
1142
1143         /*
1144          * Vector mode transmit can be enabled only if not using scatter rx
1145          * or tx offloads.
1146          */
1147         if (!eth_dev->data->scattered_rx &&
1148             !eth_dev->data->dev_conf.txmode.offloads &&
1149             !BNXT_TRUFLOW_EN(bp)) {
1150                 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1151                             eth_dev->data->port_id);
1152                 return bnxt_xmit_pkts_vec;
1153         }
1154         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1155                     eth_dev->data->port_id);
1156         PMD_DRV_LOG(INFO,
1157                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1158                     eth_dev->data->port_id,
1159                     eth_dev->data->scattered_rx,
1160                     eth_dev->data->dev_conf.txmode.offloads);
1161 #endif
1162 #endif
1163         return bnxt_xmit_pkts;
1164 }
1165
1166 static int bnxt_handle_if_change_status(struct bnxt *bp)
1167 {
1168         int rc;
1169
1170         /* Since fw has undergone a reset and lost all contexts,
1171          * set fatal flag to not issue hwrm during cleanup
1172          */
1173         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1174         bnxt_uninit_resources(bp, true);
1175
1176         /* clear fatal flag so that re-init happens */
1177         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1178         rc = bnxt_init_resources(bp, true);
1179
1180         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1181
1182         return rc;
1183 }
1184
1185 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1186 {
1187         struct bnxt *bp = eth_dev->data->dev_private;
1188         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1189         int vlan_mask = 0;
1190         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1191
1192         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1193                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1194                 return -EINVAL;
1195         }
1196
1197         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
1198                 PMD_DRV_LOG(ERR,
1199                         "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1200                         bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1201         }
1202
1203         do {
1204                 rc = bnxt_hwrm_if_change(bp, true);
1205                 if (rc == 0 || rc != -EAGAIN)
1206                         break;
1207
1208                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1209         } while (retry_cnt--);
1210
1211         if (rc)
1212                 return rc;
1213
1214         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1215                 rc = bnxt_handle_if_change_status(bp);
1216                 if (rc)
1217                         return rc;
1218         }
1219
1220         bnxt_enable_int(bp);
1221
1222         rc = bnxt_init_chip(bp);
1223         if (rc)
1224                 goto error;
1225
1226         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1227         eth_dev->data->dev_started = 1;
1228
1229         bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
1230
1231         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1232                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1233         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1234                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1235         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1236         if (rc)
1237                 goto error;
1238
1239         /* Initialize bnxt ULP port details */
1240         rc = bnxt_ulp_port_init(bp);
1241         if (rc)
1242                 goto error;
1243
1244         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1245         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1246
1247         pthread_mutex_lock(&bp->def_cp_lock);
1248         bnxt_schedule_fw_health_check(bp);
1249         pthread_mutex_unlock(&bp->def_cp_lock);
1250
1251         return 0;
1252
1253 error:
1254         bnxt_shutdown_nic(bp);
1255         bnxt_free_tx_mbufs(bp);
1256         bnxt_free_rx_mbufs(bp);
1257         bnxt_hwrm_if_change(bp, false);
1258         eth_dev->data->dev_started = 0;
1259         return rc;
1260 }
1261
1262 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1263 {
1264         struct bnxt *bp = eth_dev->data->dev_private;
1265         int rc = 0;
1266
1267         if (!bp->link_info->link_up)
1268                 rc = bnxt_set_hwrm_link_config(bp, true);
1269         if (!rc)
1270                 eth_dev->data->dev_link.link_status = 1;
1271
1272         bnxt_print_link_info(eth_dev);
1273         return rc;
1274 }
1275
1276 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1277 {
1278         struct bnxt *bp = eth_dev->data->dev_private;
1279
1280         eth_dev->data->dev_link.link_status = 0;
1281         bnxt_set_hwrm_link_config(bp, false);
1282         bp->link_info->link_up = 0;
1283
1284         return 0;
1285 }
1286
1287 static void bnxt_free_switch_domain(struct bnxt *bp)
1288 {
1289         if (bp->switch_domain_id)
1290                 rte_eth_switch_domain_free(bp->switch_domain_id);
1291 }
1292
1293 /* Unload the driver, release resources */
1294 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1295 {
1296         struct bnxt *bp = eth_dev->data->dev_private;
1297         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1298         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1299
1300         eth_dev->data->dev_started = 0;
1301         eth_dev->data->scattered_rx = 0;
1302
1303         /* Prevent crashes when queues are still in use */
1304         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1305         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1306
1307         bnxt_disable_int(bp);
1308
1309         /* disable uio/vfio intr/eventfd mapping */
1310         rte_intr_disable(intr_handle);
1311
1312         /* Stop the child representors for this device */
1313         bnxt_vf_rep_stop_all(bp);
1314
1315         /* delete the bnxt ULP port details */
1316         bnxt_ulp_port_deinit(bp);
1317
1318         bnxt_cancel_fw_health_check(bp);
1319
1320         bnxt_dev_set_link_down_op(eth_dev);
1321
1322         /* Wait for link to be reset and the async notification to process.
1323          * During reset recovery, there is no need to wait and
1324          * VF/NPAR functions do not have privilege to change PHY config.
1325          */
1326         if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
1327                 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
1328
1329         /* Clean queue intr-vector mapping */
1330         rte_intr_efd_disable(intr_handle);
1331         if (intr_handle->intr_vec != NULL) {
1332                 rte_free(intr_handle->intr_vec);
1333                 intr_handle->intr_vec = NULL;
1334         }
1335
1336         bnxt_hwrm_port_clr_stats(bp);
1337         bnxt_free_tx_mbufs(bp);
1338         bnxt_free_rx_mbufs(bp);
1339         /* Process any remaining notifications in default completion queue */
1340         bnxt_int_handler(eth_dev);
1341         bnxt_shutdown_nic(bp);
1342         bnxt_hwrm_if_change(bp, false);
1343
1344         rte_free(bp->mark_table);
1345         bp->mark_table = NULL;
1346
1347         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1348         bp->rx_cosq_cnt = 0;
1349         /* All filters are deleted on a port stop. */
1350         if (BNXT_FLOW_XSTATS_EN(bp))
1351                 bp->flow_stat->flow_count = 0;
1352 }
1353
1354 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1355 {
1356         struct bnxt *bp = eth_dev->data->dev_private;
1357
1358         /* cancel the recovery handler before remove dev */
1359         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1360         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1361         bnxt_cancel_fc_thread(bp);
1362
1363         if (eth_dev->data->dev_started)
1364                 bnxt_dev_stop_op(eth_dev);
1365
1366         bnxt_free_switch_domain(bp);
1367
1368         bnxt_uninit_resources(bp, false);
1369
1370         bnxt_free_leds_info(bp);
1371         bnxt_free_cos_queues(bp);
1372         bnxt_free_link_info(bp);
1373         bnxt_free_pf_info(bp);
1374         bnxt_free_parent_info(bp);
1375
1376         eth_dev->dev_ops = NULL;
1377         eth_dev->rx_pkt_burst = NULL;
1378         eth_dev->tx_pkt_burst = NULL;
1379
1380         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1381         bp->tx_mem_zone = NULL;
1382         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1383         bp->rx_mem_zone = NULL;
1384
1385         bnxt_hwrm_free_vf_info(bp);
1386
1387         rte_free(bp->grp_info);
1388         bp->grp_info = NULL;
1389 }
1390
1391 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1392                                     uint32_t index)
1393 {
1394         struct bnxt *bp = eth_dev->data->dev_private;
1395         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1396         struct bnxt_vnic_info *vnic;
1397         struct bnxt_filter_info *filter, *temp_filter;
1398         uint32_t i;
1399
1400         if (is_bnxt_in_error(bp))
1401                 return;
1402
1403         /*
1404          * Loop through all VNICs from the specified filter flow pools to
1405          * remove the corresponding MAC addr filter
1406          */
1407         for (i = 0; i < bp->nr_vnics; i++) {
1408                 if (!(pool_mask & (1ULL << i)))
1409                         continue;
1410
1411                 vnic = &bp->vnic_info[i];
1412                 filter = STAILQ_FIRST(&vnic->filter);
1413                 while (filter) {
1414                         temp_filter = STAILQ_NEXT(filter, next);
1415                         if (filter->mac_index == index) {
1416                                 STAILQ_REMOVE(&vnic->filter, filter,
1417                                                 bnxt_filter_info, next);
1418                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1419                                 bnxt_free_filter(bp, filter);
1420                         }
1421                         filter = temp_filter;
1422                 }
1423         }
1424 }
1425
1426 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1427                                struct rte_ether_addr *mac_addr, uint32_t index,
1428                                uint32_t pool)
1429 {
1430         struct bnxt_filter_info *filter;
1431         int rc = 0;
1432
1433         /* Attach requested MAC address to the new l2_filter */
1434         STAILQ_FOREACH(filter, &vnic->filter, next) {
1435                 if (filter->mac_index == index) {
1436                         PMD_DRV_LOG(DEBUG,
1437                                     "MAC addr already existed for pool %d\n",
1438                                     pool);
1439                         return 0;
1440                 }
1441         }
1442
1443         filter = bnxt_alloc_filter(bp);
1444         if (!filter) {
1445                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1446                 return -ENODEV;
1447         }
1448
1449         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1450          * if the MAC that's been programmed now is a different one, then,
1451          * copy that addr to filter->l2_addr
1452          */
1453         if (mac_addr)
1454                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1455         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1456
1457         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1458         if (!rc) {
1459                 filter->mac_index = index;
1460                 if (filter->mac_index == 0)
1461                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1462                 else
1463                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1464         } else {
1465                 bnxt_free_filter(bp, filter);
1466         }
1467
1468         return rc;
1469 }
1470
1471 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1472                                 struct rte_ether_addr *mac_addr,
1473                                 uint32_t index, uint32_t pool)
1474 {
1475         struct bnxt *bp = eth_dev->data->dev_private;
1476         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1477         int rc = 0;
1478
1479         rc = is_bnxt_in_error(bp);
1480         if (rc)
1481                 return rc;
1482
1483         if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1484                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1485                 return -ENOTSUP;
1486         }
1487
1488         if (!vnic) {
1489                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1490                 return -EINVAL;
1491         }
1492
1493         /* Filter settings will get applied when port is started */
1494         if (!eth_dev->data->dev_started)
1495                 return 0;
1496
1497         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1498
1499         return rc;
1500 }
1501
1502 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1503                      bool exp_link_status)
1504 {
1505         int rc = 0;
1506         struct bnxt *bp = eth_dev->data->dev_private;
1507         struct rte_eth_link new;
1508         int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1509                   BNXT_LINK_DOWN_WAIT_CNT;
1510
1511         rc = is_bnxt_in_error(bp);
1512         if (rc)
1513                 return rc;
1514
1515         memset(&new, 0, sizeof(new));
1516         do {
1517                 /* Retrieve link info from hardware */
1518                 rc = bnxt_get_hwrm_link_config(bp, &new);
1519                 if (rc) {
1520                         new.link_speed = ETH_LINK_SPEED_100M;
1521                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1522                         PMD_DRV_LOG(ERR,
1523                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1524                         goto out;
1525                 }
1526
1527                 if (!wait_to_complete || new.link_status == exp_link_status)
1528                         break;
1529
1530                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1531         } while (cnt--);
1532
1533 out:
1534         /* Timed out or success */
1535         if (new.link_status != eth_dev->data->dev_link.link_status ||
1536         new.link_speed != eth_dev->data->dev_link.link_speed) {
1537                 rte_eth_linkstatus_set(eth_dev, &new);
1538
1539                 rte_eth_dev_callback_process(eth_dev,
1540                                              RTE_ETH_EVENT_INTR_LSC,
1541                                              NULL);
1542
1543                 bnxt_print_link_info(eth_dev);
1544         }
1545
1546         return rc;
1547 }
1548
1549 int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1550                         int wait_to_complete)
1551 {
1552         return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1553 }
1554
1555 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1556 {
1557         struct bnxt *bp = eth_dev->data->dev_private;
1558         struct bnxt_vnic_info *vnic;
1559         uint32_t old_flags;
1560         int rc;
1561
1562         rc = is_bnxt_in_error(bp);
1563         if (rc)
1564                 return rc;
1565
1566         /* Filter settings will get applied when port is started */
1567         if (!eth_dev->data->dev_started)
1568                 return 0;
1569
1570         if (bp->vnic_info == NULL)
1571                 return 0;
1572
1573         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1574
1575         old_flags = vnic->flags;
1576         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1577         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1578         if (rc != 0)
1579                 vnic->flags = old_flags;
1580
1581         return rc;
1582 }
1583
1584 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1585 {
1586         struct bnxt *bp = eth_dev->data->dev_private;
1587         struct bnxt_vnic_info *vnic;
1588         uint32_t old_flags;
1589         int rc;
1590
1591         rc = is_bnxt_in_error(bp);
1592         if (rc)
1593                 return rc;
1594
1595         /* Filter settings will get applied when port is started */
1596         if (!eth_dev->data->dev_started)
1597                 return 0;
1598
1599         if (bp->vnic_info == NULL)
1600                 return 0;
1601
1602         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1603
1604         old_flags = vnic->flags;
1605         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1606         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1607         if (rc != 0)
1608                 vnic->flags = old_flags;
1609
1610         return rc;
1611 }
1612
1613 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1614 {
1615         struct bnxt *bp = eth_dev->data->dev_private;
1616         struct bnxt_vnic_info *vnic;
1617         uint32_t old_flags;
1618         int rc;
1619
1620         rc = is_bnxt_in_error(bp);
1621         if (rc)
1622                 return rc;
1623
1624         /* Filter settings will get applied when port is started */
1625         if (!eth_dev->data->dev_started)
1626                 return 0;
1627
1628         if (bp->vnic_info == NULL)
1629                 return 0;
1630
1631         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1632
1633         old_flags = vnic->flags;
1634         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1635         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1636         if (rc != 0)
1637                 vnic->flags = old_flags;
1638
1639         return rc;
1640 }
1641
1642 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1643 {
1644         struct bnxt *bp = eth_dev->data->dev_private;
1645         struct bnxt_vnic_info *vnic;
1646         uint32_t old_flags;
1647         int rc;
1648
1649         rc = is_bnxt_in_error(bp);
1650         if (rc)
1651                 return rc;
1652
1653         /* Filter settings will get applied when port is started */
1654         if (!eth_dev->data->dev_started)
1655                 return 0;
1656
1657         if (bp->vnic_info == NULL)
1658                 return 0;
1659
1660         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1661
1662         old_flags = vnic->flags;
1663         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1664         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1665         if (rc != 0)
1666                 vnic->flags = old_flags;
1667
1668         return rc;
1669 }
1670
1671 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1672 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1673 {
1674         if (qid >= bp->rx_nr_rings)
1675                 return NULL;
1676
1677         return bp->eth_dev->data->rx_queues[qid];
1678 }
1679
1680 /* Return rxq corresponding to a given rss table ring/group ID. */
1681 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1682 {
1683         struct bnxt_rx_queue *rxq;
1684         unsigned int i;
1685
1686         if (!BNXT_HAS_RING_GRPS(bp)) {
1687                 for (i = 0; i < bp->rx_nr_rings; i++) {
1688                         rxq = bp->eth_dev->data->rx_queues[i];
1689                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1690                                 return rxq->index;
1691                 }
1692         } else {
1693                 for (i = 0; i < bp->rx_nr_rings; i++) {
1694                         if (bp->grp_info[i].fw_grp_id == fwr)
1695                                 return i;
1696                 }
1697         }
1698
1699         return INVALID_HW_RING_ID;
1700 }
1701
1702 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1703                             struct rte_eth_rss_reta_entry64 *reta_conf,
1704                             uint16_t reta_size)
1705 {
1706         struct bnxt *bp = eth_dev->data->dev_private;
1707         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1708         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1709         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1710         uint16_t idx, sft;
1711         int i, rc;
1712
1713         rc = is_bnxt_in_error(bp);
1714         if (rc)
1715                 return rc;
1716
1717         if (!vnic->rss_table)
1718                 return -EINVAL;
1719
1720         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1721                 return -EINVAL;
1722
1723         if (reta_size != tbl_size) {
1724                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1725                         "(%d) must equal the size supported by the hardware "
1726                         "(%d)\n", reta_size, tbl_size);
1727                 return -EINVAL;
1728         }
1729
1730         for (i = 0; i < reta_size; i++) {
1731                 struct bnxt_rx_queue *rxq;
1732
1733                 idx = i / RTE_RETA_GROUP_SIZE;
1734                 sft = i % RTE_RETA_GROUP_SIZE;
1735
1736                 if (!(reta_conf[idx].mask & (1ULL << sft)))
1737                         continue;
1738
1739                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1740                 if (!rxq) {
1741                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1742                         return -EINVAL;
1743                 }
1744
1745                 if (BNXT_CHIP_THOR(bp)) {
1746                         vnic->rss_table[i * 2] =
1747                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1748                         vnic->rss_table[i * 2 + 1] =
1749                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1750                 } else {
1751                         vnic->rss_table[i] =
1752                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1753                 }
1754         }
1755
1756         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1757         return 0;
1758 }
1759
1760 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1761                               struct rte_eth_rss_reta_entry64 *reta_conf,
1762                               uint16_t reta_size)
1763 {
1764         struct bnxt *bp = eth_dev->data->dev_private;
1765         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1766         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1767         uint16_t idx, sft, i;
1768         int rc;
1769
1770         rc = is_bnxt_in_error(bp);
1771         if (rc)
1772                 return rc;
1773
1774         /* Retrieve from the default VNIC */
1775         if (!vnic)
1776                 return -EINVAL;
1777         if (!vnic->rss_table)
1778                 return -EINVAL;
1779
1780         if (reta_size != tbl_size) {
1781                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1782                         "(%d) must equal the size supported by the hardware "
1783                         "(%d)\n", reta_size, tbl_size);
1784                 return -EINVAL;
1785         }
1786
1787         for (idx = 0, i = 0; i < reta_size; i++) {
1788                 idx = i / RTE_RETA_GROUP_SIZE;
1789                 sft = i % RTE_RETA_GROUP_SIZE;
1790
1791                 if (reta_conf[idx].mask & (1ULL << sft)) {
1792                         uint16_t qid;
1793
1794                         if (BNXT_CHIP_THOR(bp))
1795                                 qid = bnxt_rss_to_qid(bp,
1796                                                       vnic->rss_table[i * 2]);
1797                         else
1798                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1799
1800                         if (qid == INVALID_HW_RING_ID) {
1801                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1802                                 return -EINVAL;
1803                         }
1804                         reta_conf[idx].reta[sft] = qid;
1805                 }
1806         }
1807
1808         return 0;
1809 }
1810
1811 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1812                                    struct rte_eth_rss_conf *rss_conf)
1813 {
1814         struct bnxt *bp = eth_dev->data->dev_private;
1815         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1816         struct bnxt_vnic_info *vnic;
1817         int rc;
1818
1819         rc = is_bnxt_in_error(bp);
1820         if (rc)
1821                 return rc;
1822
1823         /*
1824          * If RSS enablement were different than dev_configure,
1825          * then return -EINVAL
1826          */
1827         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1828                 if (!rss_conf->rss_hf)
1829                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
1830         } else {
1831                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1832                         return -EINVAL;
1833         }
1834
1835         bp->flags |= BNXT_FLAG_UPDATE_HASH;
1836         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
1837                rss_conf,
1838                sizeof(*rss_conf));
1839
1840         /* Update the default RSS VNIC(s) */
1841         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1842         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1843
1844         /*
1845          * If hashkey is not specified, use the previously configured
1846          * hashkey
1847          */
1848         if (!rss_conf->rss_key)
1849                 goto rss_config;
1850
1851         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1852                 PMD_DRV_LOG(ERR,
1853                             "Invalid hashkey length, should be 16 bytes\n");
1854                 return -EINVAL;
1855         }
1856         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1857
1858 rss_config:
1859         bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1860         return 0;
1861 }
1862
1863 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1864                                      struct rte_eth_rss_conf *rss_conf)
1865 {
1866         struct bnxt *bp = eth_dev->data->dev_private;
1867         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1868         int len, rc;
1869         uint32_t hash_types;
1870
1871         rc = is_bnxt_in_error(bp);
1872         if (rc)
1873                 return rc;
1874
1875         /* RSS configuration is the same for all VNICs */
1876         if (vnic && vnic->rss_hash_key) {
1877                 if (rss_conf->rss_key) {
1878                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1879                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1880                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1881                 }
1882
1883                 hash_types = vnic->hash_type;
1884                 rss_conf->rss_hf = 0;
1885                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1886                         rss_conf->rss_hf |= ETH_RSS_IPV4;
1887                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1888                 }
1889                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1890                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1891                         hash_types &=
1892                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1893                 }
1894                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1895                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1896                         hash_types &=
1897                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1898                 }
1899                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1900                         rss_conf->rss_hf |= ETH_RSS_IPV6;
1901                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1902                 }
1903                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1904                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1905                         hash_types &=
1906                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1907                 }
1908                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1909                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1910                         hash_types &=
1911                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1912                 }
1913                 if (hash_types) {
1914                         PMD_DRV_LOG(ERR,
1915                                 "Unknown RSS config from firmware (%08x), RSS disabled",
1916                                 vnic->hash_type);
1917                         return -ENOTSUP;
1918                 }
1919         } else {
1920                 rss_conf->rss_hf = 0;
1921         }
1922         return 0;
1923 }
1924
1925 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1926                                struct rte_eth_fc_conf *fc_conf)
1927 {
1928         struct bnxt *bp = dev->data->dev_private;
1929         struct rte_eth_link link_info;
1930         int rc;
1931
1932         rc = is_bnxt_in_error(bp);
1933         if (rc)
1934                 return rc;
1935
1936         rc = bnxt_get_hwrm_link_config(bp, &link_info);
1937         if (rc)
1938                 return rc;
1939
1940         memset(fc_conf, 0, sizeof(*fc_conf));
1941         if (bp->link_info->auto_pause)
1942                 fc_conf->autoneg = 1;
1943         switch (bp->link_info->pause) {
1944         case 0:
1945                 fc_conf->mode = RTE_FC_NONE;
1946                 break;
1947         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1948                 fc_conf->mode = RTE_FC_TX_PAUSE;
1949                 break;
1950         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1951                 fc_conf->mode = RTE_FC_RX_PAUSE;
1952                 break;
1953         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1954                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1955                 fc_conf->mode = RTE_FC_FULL;
1956                 break;
1957         }
1958         return 0;
1959 }
1960
1961 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1962                                struct rte_eth_fc_conf *fc_conf)
1963 {
1964         struct bnxt *bp = dev->data->dev_private;
1965         int rc;
1966
1967         rc = is_bnxt_in_error(bp);
1968         if (rc)
1969                 return rc;
1970
1971         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1972                 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1973                 return -ENOTSUP;
1974         }
1975
1976         switch (fc_conf->mode) {
1977         case RTE_FC_NONE:
1978                 bp->link_info->auto_pause = 0;
1979                 bp->link_info->force_pause = 0;
1980                 break;
1981         case RTE_FC_RX_PAUSE:
1982                 if (fc_conf->autoneg) {
1983                         bp->link_info->auto_pause =
1984                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1985                         bp->link_info->force_pause = 0;
1986                 } else {
1987                         bp->link_info->auto_pause = 0;
1988                         bp->link_info->force_pause =
1989                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1990                 }
1991                 break;
1992         case RTE_FC_TX_PAUSE:
1993                 if (fc_conf->autoneg) {
1994                         bp->link_info->auto_pause =
1995                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1996                         bp->link_info->force_pause = 0;
1997                 } else {
1998                         bp->link_info->auto_pause = 0;
1999                         bp->link_info->force_pause =
2000                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2001                 }
2002                 break;
2003         case RTE_FC_FULL:
2004                 if (fc_conf->autoneg) {
2005                         bp->link_info->auto_pause =
2006                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2007                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2008                         bp->link_info->force_pause = 0;
2009                 } else {
2010                         bp->link_info->auto_pause = 0;
2011                         bp->link_info->force_pause =
2012                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2013                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2014                 }
2015                 break;
2016         }
2017         return bnxt_set_hwrm_link_config(bp, true);
2018 }
2019
2020 /* Add UDP tunneling port */
2021 static int
2022 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2023                          struct rte_eth_udp_tunnel *udp_tunnel)
2024 {
2025         struct bnxt *bp = eth_dev->data->dev_private;
2026         uint16_t tunnel_type = 0;
2027         int rc = 0;
2028
2029         rc = is_bnxt_in_error(bp);
2030         if (rc)
2031                 return rc;
2032
2033         switch (udp_tunnel->prot_type) {
2034         case RTE_TUNNEL_TYPE_VXLAN:
2035                 if (bp->vxlan_port_cnt) {
2036                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2037                                 udp_tunnel->udp_port);
2038                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2039                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2040                                 return -ENOSPC;
2041                         }
2042                         bp->vxlan_port_cnt++;
2043                         return 0;
2044                 }
2045                 tunnel_type =
2046                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2047                 bp->vxlan_port_cnt++;
2048                 break;
2049         case RTE_TUNNEL_TYPE_GENEVE:
2050                 if (bp->geneve_port_cnt) {
2051                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2052                                 udp_tunnel->udp_port);
2053                         if (bp->geneve_port != udp_tunnel->udp_port) {
2054                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2055                                 return -ENOSPC;
2056                         }
2057                         bp->geneve_port_cnt++;
2058                         return 0;
2059                 }
2060                 tunnel_type =
2061                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2062                 bp->geneve_port_cnt++;
2063                 break;
2064         default:
2065                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2066                 return -ENOTSUP;
2067         }
2068         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2069                                              tunnel_type);
2070         return rc;
2071 }
2072
2073 static int
2074 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2075                          struct rte_eth_udp_tunnel *udp_tunnel)
2076 {
2077         struct bnxt *bp = eth_dev->data->dev_private;
2078         uint16_t tunnel_type = 0;
2079         uint16_t port = 0;
2080         int rc = 0;
2081
2082         rc = is_bnxt_in_error(bp);
2083         if (rc)
2084                 return rc;
2085
2086         switch (udp_tunnel->prot_type) {
2087         case RTE_TUNNEL_TYPE_VXLAN:
2088                 if (!bp->vxlan_port_cnt) {
2089                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2090                         return -EINVAL;
2091                 }
2092                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2093                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2094                                 udp_tunnel->udp_port, bp->vxlan_port);
2095                         return -EINVAL;
2096                 }
2097                 if (--bp->vxlan_port_cnt)
2098                         return 0;
2099
2100                 tunnel_type =
2101                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2102                 port = bp->vxlan_fw_dst_port_id;
2103                 break;
2104         case RTE_TUNNEL_TYPE_GENEVE:
2105                 if (!bp->geneve_port_cnt) {
2106                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2107                         return -EINVAL;
2108                 }
2109                 if (bp->geneve_port != udp_tunnel->udp_port) {
2110                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2111                                 udp_tunnel->udp_port, bp->geneve_port);
2112                         return -EINVAL;
2113                 }
2114                 if (--bp->geneve_port_cnt)
2115                         return 0;
2116
2117                 tunnel_type =
2118                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2119                 port = bp->geneve_fw_dst_port_id;
2120                 break;
2121         default:
2122                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2123                 return -ENOTSUP;
2124         }
2125
2126         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2127         if (!rc) {
2128                 if (tunnel_type ==
2129                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
2130                         bp->vxlan_port = 0;
2131                 if (tunnel_type ==
2132                     HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
2133                         bp->geneve_port = 0;
2134         }
2135         return rc;
2136 }
2137
2138 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2139 {
2140         struct bnxt_filter_info *filter;
2141         struct bnxt_vnic_info *vnic;
2142         int rc = 0;
2143         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2144
2145         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2146         filter = STAILQ_FIRST(&vnic->filter);
2147         while (filter) {
2148                 /* Search for this matching MAC+VLAN filter */
2149                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2150                         /* Delete the filter */
2151                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2152                         if (rc)
2153                                 return rc;
2154                         STAILQ_REMOVE(&vnic->filter, filter,
2155                                       bnxt_filter_info, next);
2156                         bnxt_free_filter(bp, filter);
2157                         PMD_DRV_LOG(INFO,
2158                                     "Deleted vlan filter for %d\n",
2159                                     vlan_id);
2160                         return 0;
2161                 }
2162                 filter = STAILQ_NEXT(filter, next);
2163         }
2164         return -ENOENT;
2165 }
2166
2167 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2168 {
2169         struct bnxt_filter_info *filter;
2170         struct bnxt_vnic_info *vnic;
2171         int rc = 0;
2172         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2173                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2174         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2175
2176         /* Implementation notes on the use of VNIC in this command:
2177          *
2178          * By default, these filters belong to default vnic for the function.
2179          * Once these filters are set up, only destination VNIC can be modified.
2180          * If the destination VNIC is not specified in this command,
2181          * then the HWRM shall only create an l2 context id.
2182          */
2183
2184         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2185         filter = STAILQ_FIRST(&vnic->filter);
2186         /* Check if the VLAN has already been added */
2187         while (filter) {
2188                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2189                         return -EEXIST;
2190
2191                 filter = STAILQ_NEXT(filter, next);
2192         }
2193
2194         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2195          * command to create MAC+VLAN filter with the right flags, enables set.
2196          */
2197         filter = bnxt_alloc_filter(bp);
2198         if (!filter) {
2199                 PMD_DRV_LOG(ERR,
2200                             "MAC/VLAN filter alloc failed\n");
2201                 return -ENOMEM;
2202         }
2203         /* MAC + VLAN ID filter */
2204         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2205          * untagged packets are received
2206          *
2207          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2208          * packets and only the programmed vlan's packets are received
2209          */
2210         filter->l2_ivlan = vlan_id;
2211         filter->l2_ivlan_mask = 0x0FFF;
2212         filter->enables |= en;
2213         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2214
2215         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2216         if (rc) {
2217                 /* Free the newly allocated filter as we were
2218                  * not able to create the filter in hardware.
2219                  */
2220                 bnxt_free_filter(bp, filter);
2221                 return rc;
2222         }
2223
2224         filter->mac_index = 0;
2225         /* Add this new filter to the list */
2226         if (vlan_id == 0)
2227                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2228         else
2229                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2230
2231         PMD_DRV_LOG(INFO,
2232                     "Added Vlan filter for %d\n", vlan_id);
2233         return rc;
2234 }
2235
2236 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2237                 uint16_t vlan_id, int on)
2238 {
2239         struct bnxt *bp = eth_dev->data->dev_private;
2240         int rc;
2241
2242         rc = is_bnxt_in_error(bp);
2243         if (rc)
2244                 return rc;
2245
2246         if (!eth_dev->data->dev_started) {
2247                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2248                 return -EINVAL;
2249         }
2250
2251         /* These operations apply to ALL existing MAC/VLAN filters */
2252         if (on)
2253                 return bnxt_add_vlan_filter(bp, vlan_id);
2254         else
2255                 return bnxt_del_vlan_filter(bp, vlan_id);
2256 }
2257
2258 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2259                                     struct bnxt_vnic_info *vnic)
2260 {
2261         struct bnxt_filter_info *filter;
2262         int rc;
2263
2264         filter = STAILQ_FIRST(&vnic->filter);
2265         while (filter) {
2266                 if (filter->mac_index == 0 &&
2267                     !memcmp(filter->l2_addr, bp->mac_addr,
2268                             RTE_ETHER_ADDR_LEN)) {
2269                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2270                         if (!rc) {
2271                                 STAILQ_REMOVE(&vnic->filter, filter,
2272                                               bnxt_filter_info, next);
2273                                 bnxt_free_filter(bp, filter);
2274                         }
2275                         return rc;
2276                 }
2277                 filter = STAILQ_NEXT(filter, next);
2278         }
2279         return 0;
2280 }
2281
2282 static int
2283 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2284 {
2285         struct bnxt_vnic_info *vnic;
2286         unsigned int i;
2287         int rc;
2288
2289         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2290         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2291                 /* Remove any VLAN filters programmed */
2292                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2293                         bnxt_del_vlan_filter(bp, i);
2294
2295                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2296                 if (rc)
2297                         return rc;
2298         } else {
2299                 /* Default filter will allow packets that match the
2300                  * dest mac. So, it has to be deleted, otherwise, we
2301                  * will endup receiving vlan packets for which the
2302                  * filter is not programmed, when hw-vlan-filter
2303                  * configuration is ON
2304                  */
2305                 bnxt_del_dflt_mac_filter(bp, vnic);
2306                 /* This filter will allow only untagged packets */
2307                 bnxt_add_vlan_filter(bp, 0);
2308         }
2309         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2310                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2311
2312         return 0;
2313 }
2314
2315 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2316 {
2317         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2318         unsigned int i;
2319         int rc;
2320
2321         /* Destroy vnic filters and vnic */
2322         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2323             DEV_RX_OFFLOAD_VLAN_FILTER) {
2324                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2325                         bnxt_del_vlan_filter(bp, i);
2326         }
2327         bnxt_del_dflt_mac_filter(bp, vnic);
2328
2329         rc = bnxt_hwrm_vnic_free(bp, vnic);
2330         if (rc)
2331                 return rc;
2332
2333         rte_free(vnic->fw_grp_ids);
2334         vnic->fw_grp_ids = NULL;
2335
2336         vnic->rx_queue_cnt = 0;
2337
2338         return 0;
2339 }
2340
2341 static int
2342 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2343 {
2344         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2345         int rc;
2346
2347         /* Destroy, recreate and reconfigure the default vnic */
2348         rc = bnxt_free_one_vnic(bp, 0);
2349         if (rc)
2350                 return rc;
2351
2352         /* default vnic 0 */
2353         rc = bnxt_setup_one_vnic(bp, 0);
2354         if (rc)
2355                 return rc;
2356
2357         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2358             DEV_RX_OFFLOAD_VLAN_FILTER) {
2359                 rc = bnxt_add_vlan_filter(bp, 0);
2360                 if (rc)
2361                         return rc;
2362                 rc = bnxt_restore_vlan_filters(bp);
2363                 if (rc)
2364                         return rc;
2365         } else {
2366                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2367                 if (rc)
2368                         return rc;
2369         }
2370
2371         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2372         if (rc)
2373                 return rc;
2374
2375         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2376                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2377
2378         return rc;
2379 }
2380
2381 static int
2382 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2383 {
2384         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2385         struct bnxt *bp = dev->data->dev_private;
2386         int rc;
2387
2388         rc = is_bnxt_in_error(bp);
2389         if (rc)
2390                 return rc;
2391
2392         /* Filter settings will get applied when port is started */
2393         if (!dev->data->dev_started)
2394                 return 0;
2395
2396         if (mask & ETH_VLAN_FILTER_MASK) {
2397                 /* Enable or disable VLAN filtering */
2398                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2399                 if (rc)
2400                         return rc;
2401         }
2402
2403         if (mask & ETH_VLAN_STRIP_MASK) {
2404                 /* Enable or disable VLAN stripping */
2405                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2406                 if (rc)
2407                         return rc;
2408         }
2409
2410         if (mask & ETH_VLAN_EXTEND_MASK) {
2411                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2412                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2413                 else
2414                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2415         }
2416
2417         return 0;
2418 }
2419
2420 static int
2421 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2422                       uint16_t tpid)
2423 {
2424         struct bnxt *bp = dev->data->dev_private;
2425         int qinq = dev->data->dev_conf.rxmode.offloads &
2426                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2427
2428         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2429             vlan_type != ETH_VLAN_TYPE_OUTER) {
2430                 PMD_DRV_LOG(ERR,
2431                             "Unsupported vlan type.");
2432                 return -EINVAL;
2433         }
2434         if (!qinq) {
2435                 PMD_DRV_LOG(ERR,
2436                             "QinQ not enabled. Needs to be ON as we can "
2437                             "accelerate only outer vlan\n");
2438                 return -EINVAL;
2439         }
2440
2441         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2442                 switch (tpid) {
2443                 case RTE_ETHER_TYPE_QINQ:
2444                         bp->outer_tpid_bd =
2445                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2446                                 break;
2447                 case RTE_ETHER_TYPE_VLAN:
2448                         bp->outer_tpid_bd =
2449                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2450                                 break;
2451                 case RTE_ETHER_TYPE_QINQ1:
2452                         bp->outer_tpid_bd =
2453                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2454                                 break;
2455                 case RTE_ETHER_TYPE_QINQ2:
2456                         bp->outer_tpid_bd =
2457                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2458                                 break;
2459                 case RTE_ETHER_TYPE_QINQ3:
2460                         bp->outer_tpid_bd =
2461                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2462                                 break;
2463                 default:
2464                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2465                         return -EINVAL;
2466                 }
2467                 bp->outer_tpid_bd |= tpid;
2468                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2469         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2470                 PMD_DRV_LOG(ERR,
2471                             "Can accelerate only outer vlan in QinQ\n");
2472                 return -EINVAL;
2473         }
2474
2475         return 0;
2476 }
2477
2478 static int
2479 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2480                              struct rte_ether_addr *addr)
2481 {
2482         struct bnxt *bp = dev->data->dev_private;
2483         /* Default Filter is tied to VNIC 0 */
2484         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2485         int rc;
2486
2487         rc = is_bnxt_in_error(bp);
2488         if (rc)
2489                 return rc;
2490
2491         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2492                 return -EPERM;
2493
2494         if (rte_is_zero_ether_addr(addr))
2495                 return -EINVAL;
2496
2497         /* Filter settings will get applied when port is started */
2498         if (!dev->data->dev_started)
2499                 return 0;
2500
2501         /* Check if the requested MAC is already added */
2502         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2503                 return 0;
2504
2505         /* Destroy filter and re-create it */
2506         bnxt_del_dflt_mac_filter(bp, vnic);
2507
2508         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2509         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2510                 /* This filter will allow only untagged packets */
2511                 rc = bnxt_add_vlan_filter(bp, 0);
2512         } else {
2513                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2514         }
2515
2516         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2517         return rc;
2518 }
2519
2520 static int
2521 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2522                           struct rte_ether_addr *mc_addr_set,
2523                           uint32_t nb_mc_addr)
2524 {
2525         struct bnxt *bp = eth_dev->data->dev_private;
2526         char *mc_addr_list = (char *)mc_addr_set;
2527         struct bnxt_vnic_info *vnic;
2528         uint32_t off = 0, i = 0;
2529         int rc;
2530
2531         rc = is_bnxt_in_error(bp);
2532         if (rc)
2533                 return rc;
2534
2535         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2536
2537         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2538                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2539                 goto allmulti;
2540         }
2541
2542         /* TODO Check for Duplicate mcast addresses */
2543         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2544         for (i = 0; i < nb_mc_addr; i++) {
2545                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2546                         RTE_ETHER_ADDR_LEN);
2547                 off += RTE_ETHER_ADDR_LEN;
2548         }
2549
2550         vnic->mc_addr_cnt = i;
2551         if (vnic->mc_addr_cnt)
2552                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2553         else
2554                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2555
2556 allmulti:
2557         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2558 }
2559
2560 static int
2561 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2562 {
2563         struct bnxt *bp = dev->data->dev_private;
2564         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2565         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2566         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2567         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2568         int ret;
2569
2570         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2571                         fw_major, fw_minor, fw_updt, fw_rsvd);
2572
2573         ret += 1; /* add the size of '\0' */
2574         if (fw_size < (uint32_t)ret)
2575                 return ret;
2576         else
2577                 return 0;
2578 }
2579
2580 static void
2581 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2582         struct rte_eth_rxq_info *qinfo)
2583 {
2584         struct bnxt *bp = dev->data->dev_private;
2585         struct bnxt_rx_queue *rxq;
2586
2587         if (is_bnxt_in_error(bp))
2588                 return;
2589
2590         rxq = dev->data->rx_queues[queue_id];
2591
2592         qinfo->mp = rxq->mb_pool;
2593         qinfo->scattered_rx = dev->data->scattered_rx;
2594         qinfo->nb_desc = rxq->nb_rx_desc;
2595
2596         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2597         qinfo->conf.rx_drop_en = 0;
2598         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2599 }
2600
2601 static void
2602 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2603         struct rte_eth_txq_info *qinfo)
2604 {
2605         struct bnxt *bp = dev->data->dev_private;
2606         struct bnxt_tx_queue *txq;
2607
2608         if (is_bnxt_in_error(bp))
2609                 return;
2610
2611         txq = dev->data->tx_queues[queue_id];
2612
2613         qinfo->nb_desc = txq->nb_tx_desc;
2614
2615         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2616         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2617         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2618
2619         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2620         qinfo->conf.tx_rs_thresh = 0;
2621         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2622 }
2623
2624 static const struct {
2625         eth_rx_burst_t pkt_burst;
2626         const char *info;
2627 } bnxt_rx_burst_info[] = {
2628         {bnxt_recv_pkts,        "Scalar"},
2629 #if defined(RTE_ARCH_X86)
2630         {bnxt_recv_pkts_vec,    "Vector SSE"},
2631 #elif defined(RTE_ARCH_ARM64)
2632         {bnxt_recv_pkts_vec,    "Vector Neon"},
2633 #endif
2634 };
2635
2636 static int
2637 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2638                        struct rte_eth_burst_mode *mode)
2639 {
2640         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2641         size_t i;
2642
2643         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2644                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2645                         snprintf(mode->info, sizeof(mode->info), "%s",
2646                                  bnxt_rx_burst_info[i].info);
2647                         return 0;
2648                 }
2649         }
2650
2651         return -EINVAL;
2652 }
2653
2654 static const struct {
2655         eth_tx_burst_t pkt_burst;
2656         const char *info;
2657 } bnxt_tx_burst_info[] = {
2658         {bnxt_xmit_pkts,        "Scalar"},
2659 #if defined(RTE_ARCH_X86)
2660         {bnxt_xmit_pkts_vec,    "Vector SSE"},
2661 #elif defined(RTE_ARCH_ARM64)
2662         {bnxt_xmit_pkts_vec,    "Vector Neon"},
2663 #endif
2664 };
2665
2666 static int
2667 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2668                        struct rte_eth_burst_mode *mode)
2669 {
2670         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2671         size_t i;
2672
2673         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2674                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2675                         snprintf(mode->info, sizeof(mode->info), "%s",
2676                                  bnxt_tx_burst_info[i].info);
2677                         return 0;
2678                 }
2679         }
2680
2681         return -EINVAL;
2682 }
2683
2684 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2685 {
2686         struct bnxt *bp = eth_dev->data->dev_private;
2687         uint32_t new_pkt_size;
2688         uint32_t rc = 0;
2689         uint32_t i;
2690
2691         rc = is_bnxt_in_error(bp);
2692         if (rc)
2693                 return rc;
2694
2695         /* Exit if receive queues are not configured yet */
2696         if (!eth_dev->data->nb_rx_queues)
2697                 return rc;
2698
2699         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2700                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2701
2702         /*
2703          * Disallow any MTU change that would require scattered receive support
2704          * if it is not already enabled.
2705          */
2706         if (eth_dev->data->dev_started &&
2707             !eth_dev->data->scattered_rx &&
2708             (new_pkt_size >
2709              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2710                 PMD_DRV_LOG(ERR,
2711                             "MTU change would require scattered rx support. ");
2712                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2713                 return -EINVAL;
2714         }
2715
2716         if (new_mtu > RTE_ETHER_MTU) {
2717                 bp->flags |= BNXT_FLAG_JUMBO;
2718                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2719                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2720         } else {
2721                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2722                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2723                 bp->flags &= ~BNXT_FLAG_JUMBO;
2724         }
2725
2726         /* Is there a change in mtu setting? */
2727         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2728                 return rc;
2729
2730         for (i = 0; i < bp->nr_vnics; i++) {
2731                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2732                 uint16_t size = 0;
2733
2734                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2735                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2736                 if (rc)
2737                         break;
2738
2739                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2740                 size -= RTE_PKTMBUF_HEADROOM;
2741
2742                 if (size < new_mtu) {
2743                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2744                         if (rc)
2745                                 return rc;
2746                 }
2747         }
2748
2749         if (!rc)
2750                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2751
2752         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2753
2754         return rc;
2755 }
2756
2757 static int
2758 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2759 {
2760         struct bnxt *bp = dev->data->dev_private;
2761         uint16_t vlan = bp->vlan;
2762         int rc;
2763
2764         rc = is_bnxt_in_error(bp);
2765         if (rc)
2766                 return rc;
2767
2768         if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2769                 PMD_DRV_LOG(ERR,
2770                         "PVID cannot be modified for this function\n");
2771                 return -ENOTSUP;
2772         }
2773         bp->vlan = on ? pvid : 0;
2774
2775         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2776         if (rc)
2777                 bp->vlan = vlan;
2778         return rc;
2779 }
2780
2781 static int
2782 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2783 {
2784         struct bnxt *bp = dev->data->dev_private;
2785         int rc;
2786
2787         rc = is_bnxt_in_error(bp);
2788         if (rc)
2789                 return rc;
2790
2791         return bnxt_hwrm_port_led_cfg(bp, true);
2792 }
2793
2794 static int
2795 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2796 {
2797         struct bnxt *bp = dev->data->dev_private;
2798         int rc;
2799
2800         rc = is_bnxt_in_error(bp);
2801         if (rc)
2802                 return rc;
2803
2804         return bnxt_hwrm_port_led_cfg(bp, false);
2805 }
2806
2807 static uint32_t
2808 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2809 {
2810         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2811         uint32_t desc = 0, raw_cons = 0, cons;
2812         struct bnxt_cp_ring_info *cpr;
2813         struct bnxt_rx_queue *rxq;
2814         struct rx_pkt_cmpl *rxcmp;
2815         int rc;
2816
2817         rc = is_bnxt_in_error(bp);
2818         if (rc)
2819                 return rc;
2820
2821         rxq = dev->data->rx_queues[rx_queue_id];
2822         cpr = rxq->cp_ring;
2823         raw_cons = cpr->cp_raw_cons;
2824
2825         while (1) {
2826                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2827                 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2828                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2829
2830                 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2831                         break;
2832                 } else {
2833                         raw_cons++;
2834                         desc++;
2835                 }
2836         }
2837
2838         return desc;
2839 }
2840
2841 static int
2842 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2843 {
2844         struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2845         struct bnxt_rx_ring_info *rxr;
2846         struct bnxt_cp_ring_info *cpr;
2847         struct rte_mbuf *rx_buf;
2848         struct rx_pkt_cmpl *rxcmp;
2849         uint32_t cons, cp_cons;
2850         int rc;
2851
2852         if (!rxq)
2853                 return -EINVAL;
2854
2855         rc = is_bnxt_in_error(rxq->bp);
2856         if (rc)
2857                 return rc;
2858
2859         cpr = rxq->cp_ring;
2860         rxr = rxq->rx_ring;
2861
2862         if (offset >= rxq->nb_rx_desc)
2863                 return -EINVAL;
2864
2865         cons = RING_CMP(cpr->cp_ring_struct, offset);
2866         cp_cons = cpr->cp_raw_cons;
2867         rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2868
2869         if (cons > cp_cons) {
2870                 if (CMPL_VALID(rxcmp, cpr->valid))
2871                         return RTE_ETH_RX_DESC_DONE;
2872         } else {
2873                 if (CMPL_VALID(rxcmp, !cpr->valid))
2874                         return RTE_ETH_RX_DESC_DONE;
2875         }
2876         rx_buf = rxr->rx_buf_ring[cons];
2877         if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2878                 return RTE_ETH_RX_DESC_UNAVAIL;
2879
2880
2881         return RTE_ETH_RX_DESC_AVAIL;
2882 }
2883
2884 static int
2885 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2886 {
2887         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2888         struct bnxt_tx_ring_info *txr;
2889         struct bnxt_cp_ring_info *cpr;
2890         struct bnxt_sw_tx_bd *tx_buf;
2891         struct tx_pkt_cmpl *txcmp;
2892         uint32_t cons, cp_cons;
2893         int rc;
2894
2895         if (!txq)
2896                 return -EINVAL;
2897
2898         rc = is_bnxt_in_error(txq->bp);
2899         if (rc)
2900                 return rc;
2901
2902         cpr = txq->cp_ring;
2903         txr = txq->tx_ring;
2904
2905         if (offset >= txq->nb_tx_desc)
2906                 return -EINVAL;
2907
2908         cons = RING_CMP(cpr->cp_ring_struct, offset);
2909         txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2910         cp_cons = cpr->cp_raw_cons;
2911
2912         if (cons > cp_cons) {
2913                 if (CMPL_VALID(txcmp, cpr->valid))
2914                         return RTE_ETH_TX_DESC_UNAVAIL;
2915         } else {
2916                 if (CMPL_VALID(txcmp, !cpr->valid))
2917                         return RTE_ETH_TX_DESC_UNAVAIL;
2918         }
2919         tx_buf = &txr->tx_buf_ring[cons];
2920         if (tx_buf->mbuf == NULL)
2921                 return RTE_ETH_TX_DESC_DONE;
2922
2923         return RTE_ETH_TX_DESC_FULL;
2924 }
2925
2926 static struct bnxt_filter_info *
2927 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2928                                 struct rte_eth_ethertype_filter *efilter,
2929                                 struct bnxt_vnic_info *vnic0,
2930                                 struct bnxt_vnic_info *vnic,
2931                                 int *ret)
2932 {
2933         struct bnxt_filter_info *mfilter = NULL;
2934         int match = 0;
2935         *ret = 0;
2936
2937         if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2938                 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2939                 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2940                         " ethertype filter.", efilter->ether_type);
2941                 *ret = -EINVAL;
2942                 goto exit;
2943         }
2944         if (efilter->queue >= bp->rx_nr_rings) {
2945                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2946                 *ret = -EINVAL;
2947                 goto exit;
2948         }
2949
2950         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2951         vnic = &bp->vnic_info[efilter->queue];
2952         if (vnic == NULL) {
2953                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2954                 *ret = -EINVAL;
2955                 goto exit;
2956         }
2957
2958         if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2959                 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2960                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2961                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2962                              mfilter->flags ==
2963                              HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2964                              mfilter->ethertype == efilter->ether_type)) {
2965                                 match = 1;
2966                                 break;
2967                         }
2968                 }
2969         } else {
2970                 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2971                         if ((!memcmp(efilter->mac_addr.addr_bytes,
2972                                      mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2973                              mfilter->ethertype == efilter->ether_type &&
2974                              mfilter->flags ==
2975                              HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2976                                 match = 1;
2977                                 break;
2978                         }
2979         }
2980
2981         if (match)
2982                 *ret = -EEXIST;
2983
2984 exit:
2985         return mfilter;
2986 }
2987
2988 static int
2989 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2990                         enum rte_filter_op filter_op,
2991                         void *arg)
2992 {
2993         struct bnxt *bp = dev->data->dev_private;
2994         struct rte_eth_ethertype_filter *efilter =
2995                         (struct rte_eth_ethertype_filter *)arg;
2996         struct bnxt_filter_info *bfilter, *filter1;
2997         struct bnxt_vnic_info *vnic, *vnic0;
2998         int ret;
2999
3000         if (filter_op == RTE_ETH_FILTER_NOP)
3001                 return 0;
3002
3003         if (arg == NULL) {
3004                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3005                             filter_op);
3006                 return -EINVAL;
3007         }
3008
3009         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3010         vnic = &bp->vnic_info[efilter->queue];
3011
3012         switch (filter_op) {
3013         case RTE_ETH_FILTER_ADD:
3014                 bnxt_match_and_validate_ether_filter(bp, efilter,
3015                                                         vnic0, vnic, &ret);
3016                 if (ret < 0)
3017                         return ret;
3018
3019                 bfilter = bnxt_get_unused_filter(bp);
3020                 if (bfilter == NULL) {
3021                         PMD_DRV_LOG(ERR,
3022                                 "Not enough resources for a new filter.\n");
3023                         return -ENOMEM;
3024                 }
3025                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3026                 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
3027                        RTE_ETHER_ADDR_LEN);
3028                 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
3029                        RTE_ETHER_ADDR_LEN);
3030                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3031                 bfilter->ethertype = efilter->ether_type;
3032                 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3033
3034                 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
3035                 if (filter1 == NULL) {
3036                         ret = -EINVAL;
3037                         goto cleanup;
3038                 }
3039                 bfilter->enables |=
3040                         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3041                 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3042
3043                 bfilter->dst_id = vnic->fw_vnic_id;
3044
3045                 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3046                         bfilter->flags =
3047                                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3048                 }
3049
3050                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3051                 if (ret)
3052                         goto cleanup;
3053                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3054                 break;
3055         case RTE_ETH_FILTER_DELETE:
3056                 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
3057                                                         vnic0, vnic, &ret);
3058                 if (ret == -EEXIST) {
3059                         ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
3060
3061                         STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
3062                                       next);
3063                         bnxt_free_filter(bp, filter1);
3064                 } else if (ret == 0) {
3065                         PMD_DRV_LOG(ERR, "No matching filter found\n");
3066                 }
3067                 break;
3068         default:
3069                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3070                 ret = -EINVAL;
3071                 goto error;
3072         }
3073         return ret;
3074 cleanup:
3075         bnxt_free_filter(bp, bfilter);
3076 error:
3077         return ret;
3078 }
3079
3080 static inline int
3081 parse_ntuple_filter(struct bnxt *bp,
3082                     struct rte_eth_ntuple_filter *nfilter,
3083                     struct bnxt_filter_info *bfilter)
3084 {
3085         uint32_t en = 0;
3086
3087         if (nfilter->queue >= bp->rx_nr_rings) {
3088                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
3089                 return -EINVAL;
3090         }
3091
3092         switch (nfilter->dst_port_mask) {
3093         case UINT16_MAX:
3094                 bfilter->dst_port_mask = -1;
3095                 bfilter->dst_port = nfilter->dst_port;
3096                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
3097                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3098                 break;
3099         default:
3100                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3101                 return -EINVAL;
3102         }
3103
3104         bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3105         en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3106
3107         switch (nfilter->proto_mask) {
3108         case UINT8_MAX:
3109                 if (nfilter->proto == 17) /* IPPROTO_UDP */
3110                         bfilter->ip_protocol = 17;
3111                 else if (nfilter->proto == 6) /* IPPROTO_TCP */
3112                         bfilter->ip_protocol = 6;
3113                 else
3114                         return -EINVAL;
3115                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3116                 break;
3117         default:
3118                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3119                 return -EINVAL;
3120         }
3121
3122         switch (nfilter->dst_ip_mask) {
3123         case UINT32_MAX:
3124                 bfilter->dst_ipaddr_mask[0] = -1;
3125                 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
3126                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
3127                         NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3128                 break;
3129         default:
3130                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3131                 return -EINVAL;
3132         }
3133
3134         switch (nfilter->src_ip_mask) {
3135         case UINT32_MAX:
3136                 bfilter->src_ipaddr_mask[0] = -1;
3137                 bfilter->src_ipaddr[0] = nfilter->src_ip;
3138                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
3139                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3140                 break;
3141         default:
3142                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3143                 return -EINVAL;
3144         }
3145
3146         switch (nfilter->src_port_mask) {
3147         case UINT16_MAX:
3148                 bfilter->src_port_mask = -1;
3149                 bfilter->src_port = nfilter->src_port;
3150                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
3151                         NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3152                 break;
3153         default:
3154                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3155                 return -EINVAL;
3156         }
3157
3158         bfilter->enables = en;
3159         return 0;
3160 }
3161
3162 static struct bnxt_filter_info*
3163 bnxt_match_ntuple_filter(struct bnxt *bp,
3164                          struct bnxt_filter_info *bfilter,
3165                          struct bnxt_vnic_info **mvnic)
3166 {
3167         struct bnxt_filter_info *mfilter = NULL;
3168         int i;
3169
3170         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3171                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3172                 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
3173                         if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
3174                             bfilter->src_ipaddr_mask[0] ==
3175                             mfilter->src_ipaddr_mask[0] &&
3176                             bfilter->src_port == mfilter->src_port &&
3177                             bfilter->src_port_mask == mfilter->src_port_mask &&
3178                             bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
3179                             bfilter->dst_ipaddr_mask[0] ==
3180                             mfilter->dst_ipaddr_mask[0] &&
3181                             bfilter->dst_port == mfilter->dst_port &&
3182                             bfilter->dst_port_mask == mfilter->dst_port_mask &&
3183                             bfilter->flags == mfilter->flags &&
3184                             bfilter->enables == mfilter->enables) {
3185                                 if (mvnic)
3186                                         *mvnic = vnic;
3187                                 return mfilter;
3188                         }
3189                 }
3190         }
3191         return NULL;
3192 }
3193
3194 static int
3195 bnxt_cfg_ntuple_filter(struct bnxt *bp,
3196                        struct rte_eth_ntuple_filter *nfilter,
3197                        enum rte_filter_op filter_op)
3198 {
3199         struct bnxt_filter_info *bfilter, *mfilter, *filter1;
3200         struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
3201         int ret;
3202
3203         if (nfilter->flags != RTE_5TUPLE_FLAGS) {
3204                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3205                 return -EINVAL;
3206         }
3207
3208         if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
3209                 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
3210                 return -EINVAL;
3211         }
3212
3213         bfilter = bnxt_get_unused_filter(bp);
3214         if (bfilter == NULL) {
3215                 PMD_DRV_LOG(ERR,
3216                         "Not enough resources for a new filter.\n");
3217                 return -ENOMEM;
3218         }
3219         ret = parse_ntuple_filter(bp, nfilter, bfilter);
3220         if (ret < 0)
3221                 goto free_filter;
3222
3223         vnic = &bp->vnic_info[nfilter->queue];
3224         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3225         filter1 = STAILQ_FIRST(&vnic0->filter);
3226         if (filter1 == NULL) {
3227                 ret = -EINVAL;
3228                 goto free_filter;
3229         }
3230
3231         bfilter->dst_id = vnic->fw_vnic_id;
3232         bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3233         bfilter->enables |=
3234                 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3235         bfilter->ethertype = 0x800;
3236         bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3237
3238         mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
3239
3240         if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3241             bfilter->dst_id == mfilter->dst_id) {
3242                 PMD_DRV_LOG(ERR, "filter exists.\n");
3243                 ret = -EEXIST;
3244                 goto free_filter;
3245         } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
3246                    bfilter->dst_id != mfilter->dst_id) {
3247                 mfilter->dst_id = vnic->fw_vnic_id;
3248                 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
3249                 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
3250                 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
3251                 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
3252                 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
3253                 goto free_filter;
3254         }
3255         if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3256                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3257                 ret = -ENOENT;
3258                 goto free_filter;
3259         }
3260
3261         if (filter_op == RTE_ETH_FILTER_ADD) {
3262                 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3263                 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
3264                 if (ret)
3265                         goto free_filter;
3266                 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
3267         } else {
3268                 if (mfilter == NULL) {
3269                         /* This should not happen. But for Coverity! */
3270                         ret = -ENOENT;
3271                         goto free_filter;
3272                 }
3273                 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
3274
3275                 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
3276                 bnxt_free_filter(bp, mfilter);
3277                 bnxt_free_filter(bp, bfilter);
3278         }
3279
3280         return 0;
3281 free_filter:
3282         bnxt_free_filter(bp, bfilter);
3283         return ret;
3284 }
3285
3286 static int
3287 bnxt_ntuple_filter(struct rte_eth_dev *dev,
3288                         enum rte_filter_op filter_op,
3289                         void *arg)
3290 {
3291         struct bnxt *bp = dev->data->dev_private;
3292         int ret;
3293
3294         if (filter_op == RTE_ETH_FILTER_NOP)
3295                 return 0;
3296
3297         if (arg == NULL) {
3298                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
3299                             filter_op);
3300                 return -EINVAL;
3301         }
3302
3303         switch (filter_op) {
3304         case RTE_ETH_FILTER_ADD:
3305                 ret = bnxt_cfg_ntuple_filter(bp,
3306                         (struct rte_eth_ntuple_filter *)arg,
3307                         filter_op);
3308                 break;
3309         case RTE_ETH_FILTER_DELETE:
3310                 ret = bnxt_cfg_ntuple_filter(bp,
3311                         (struct rte_eth_ntuple_filter *)arg,
3312                         filter_op);
3313                 break;
3314         default:
3315                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
3316                 ret = -EINVAL;
3317                 break;
3318         }
3319         return ret;
3320 }
3321
3322 static int
3323 bnxt_parse_fdir_filter(struct bnxt *bp,
3324                        struct rte_eth_fdir_filter *fdir,
3325                        struct bnxt_filter_info *filter)
3326 {
3327         enum rte_fdir_mode fdir_mode =
3328                 bp->eth_dev->data->dev_conf.fdir_conf.mode;
3329         struct bnxt_vnic_info *vnic0, *vnic;
3330         struct bnxt_filter_info *filter1;
3331         uint32_t en = 0;
3332         int i;
3333
3334         if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
3335                 return -EINVAL;
3336
3337         filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
3338         en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
3339
3340         switch (fdir->input.flow_type) {
3341         case RTE_ETH_FLOW_IPV4:
3342         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
3343                 /* FALLTHROUGH */
3344                 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
3345                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3346                 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
3347                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3348                 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
3349                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3350                 filter->ip_addr_type =
3351                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3352                 filter->src_ipaddr_mask[0] = 0xffffffff;
3353                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3354                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3355                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3356                 filter->ethertype = 0x800;
3357                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3358                 break;
3359         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
3360                 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
3361                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3362                 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
3363                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3364                 filter->dst_port_mask = 0xffff;
3365                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3366                 filter->src_port_mask = 0xffff;
3367                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3368                 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
3369                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3370                 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
3371                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3372                 filter->ip_protocol = 6;
3373                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3374                 filter->ip_addr_type =
3375                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3376                 filter->src_ipaddr_mask[0] = 0xffffffff;
3377                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3378                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3379                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3380                 filter->ethertype = 0x800;
3381                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3382                 break;
3383         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
3384                 filter->src_port = fdir->input.flow.udp4_flow.src_port;
3385                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3386                 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
3387                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3388                 filter->dst_port_mask = 0xffff;
3389                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3390                 filter->src_port_mask = 0xffff;
3391                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3392                 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
3393                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3394                 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
3395                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3396                 filter->ip_protocol = 17;
3397                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3398                 filter->ip_addr_type =
3399                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
3400                 filter->src_ipaddr_mask[0] = 0xffffffff;
3401                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3402                 filter->dst_ipaddr_mask[0] = 0xffffffff;
3403                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3404                 filter->ethertype = 0x800;
3405                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3406                 break;
3407         case RTE_ETH_FLOW_IPV6:
3408         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
3409                 /* FALLTHROUGH */
3410                 filter->ip_addr_type =
3411                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3412                 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
3413                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3414                 rte_memcpy(filter->src_ipaddr,
3415                            fdir->input.flow.ipv6_flow.src_ip, 16);
3416                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3417                 rte_memcpy(filter->dst_ipaddr,
3418                            fdir->input.flow.ipv6_flow.dst_ip, 16);
3419                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3420                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3421                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3422                 memset(filter->src_ipaddr_mask, 0xff, 16);
3423                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3424                 filter->ethertype = 0x86dd;
3425                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3426                 break;
3427         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
3428                 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
3429                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3430                 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
3431                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3432                 filter->dst_port_mask = 0xffff;
3433                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3434                 filter->src_port_mask = 0xffff;
3435                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3436                 filter->ip_addr_type =
3437                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3438                 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
3439                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3440                 rte_memcpy(filter->src_ipaddr,
3441                            fdir->input.flow.tcp6_flow.ip.src_ip, 16);
3442                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3443                 rte_memcpy(filter->dst_ipaddr,
3444                            fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
3445                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3446                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3447                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3448                 memset(filter->src_ipaddr_mask, 0xff, 16);
3449                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3450                 filter->ethertype = 0x86dd;
3451                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3452                 break;
3453         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3454                 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3455                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3456                 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3457                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3458                 filter->dst_port_mask = 0xffff;
3459                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3460                 filter->src_port_mask = 0xffff;
3461                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3462                 filter->ip_addr_type =
3463                         NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3464                 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3465                 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3466                 rte_memcpy(filter->src_ipaddr,
3467                            fdir->input.flow.udp6_flow.ip.src_ip, 16);
3468                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3469                 rte_memcpy(filter->dst_ipaddr,
3470                            fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3471                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3472                 memset(filter->dst_ipaddr_mask, 0xff, 16);
3473                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3474                 memset(filter->src_ipaddr_mask, 0xff, 16);
3475                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3476                 filter->ethertype = 0x86dd;
3477                 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3478                 break;
3479         case RTE_ETH_FLOW_L2_PAYLOAD:
3480                 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3481                 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3482                 break;
3483         case RTE_ETH_FLOW_VXLAN:
3484                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3485                         return -EINVAL;
3486                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3487                 filter->tunnel_type =
3488                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3489                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3490                 break;
3491         case RTE_ETH_FLOW_NVGRE:
3492                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3493                         return -EINVAL;
3494                 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3495                 filter->tunnel_type =
3496                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3497                 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3498                 break;
3499         case RTE_ETH_FLOW_UNKNOWN:
3500         case RTE_ETH_FLOW_RAW:
3501         case RTE_ETH_FLOW_FRAG_IPV4:
3502         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3503         case RTE_ETH_FLOW_FRAG_IPV6:
3504         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3505         case RTE_ETH_FLOW_IPV6_EX:
3506         case RTE_ETH_FLOW_IPV6_TCP_EX:
3507         case RTE_ETH_FLOW_IPV6_UDP_EX:
3508         case RTE_ETH_FLOW_GENEVE:
3509                 /* FALLTHROUGH */
3510         default:
3511                 return -EINVAL;
3512         }
3513
3514         vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3515         vnic = &bp->vnic_info[fdir->action.rx_queue];
3516         if (vnic == NULL) {
3517                 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3518                 return -EINVAL;
3519         }
3520
3521         if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3522                 rte_memcpy(filter->dst_macaddr,
3523                         fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3524                         en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3525         }
3526
3527         if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3528                 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3529                 filter1 = STAILQ_FIRST(&vnic0->filter);
3530                 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3531         } else {
3532                 filter->dst_id = vnic->fw_vnic_id;
3533                 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3534                         if (filter->dst_macaddr[i] == 0x00)
3535                                 filter1 = STAILQ_FIRST(&vnic0->filter);
3536                         else
3537                                 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3538         }
3539
3540         if (filter1 == NULL)
3541                 return -EINVAL;
3542
3543         en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3544         filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3545
3546         filter->enables = en;
3547
3548         return 0;
3549 }
3550
3551 static struct bnxt_filter_info *
3552 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3553                 struct bnxt_vnic_info **mvnic)
3554 {
3555         struct bnxt_filter_info *mf = NULL;
3556         int i;
3557
3558         for (i = bp->nr_vnics - 1; i >= 0; i--) {
3559                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3560
3561                 STAILQ_FOREACH(mf, &vnic->filter, next) {
3562                         if (mf->filter_type == nf->filter_type &&
3563                             mf->flags == nf->flags &&
3564                             mf->src_port == nf->src_port &&
3565                             mf->src_port_mask == nf->src_port_mask &&
3566                             mf->dst_port == nf->dst_port &&
3567                             mf->dst_port_mask == nf->dst_port_mask &&
3568                             mf->ip_protocol == nf->ip_protocol &&
3569                             mf->ip_addr_type == nf->ip_addr_type &&
3570                             mf->ethertype == nf->ethertype &&
3571                             mf->vni == nf->vni &&
3572                             mf->tunnel_type == nf->tunnel_type &&
3573                             mf->l2_ovlan == nf->l2_ovlan &&
3574                             mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3575                             mf->l2_ivlan == nf->l2_ivlan &&
3576                             mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3577                             !memcmp(mf->l2_addr, nf->l2_addr,
3578                                     RTE_ETHER_ADDR_LEN) &&
3579                             !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3580                                     RTE_ETHER_ADDR_LEN) &&
3581                             !memcmp(mf->src_macaddr, nf->src_macaddr,
3582                                     RTE_ETHER_ADDR_LEN) &&
3583                             !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3584                                     RTE_ETHER_ADDR_LEN) &&
3585                             !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3586                                     sizeof(nf->src_ipaddr)) &&
3587                             !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3588                                     sizeof(nf->src_ipaddr_mask)) &&
3589                             !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3590                                     sizeof(nf->dst_ipaddr)) &&
3591                             !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3592                                     sizeof(nf->dst_ipaddr_mask))) {
3593                                 if (mvnic)
3594                                         *mvnic = vnic;
3595                                 return mf;
3596                         }
3597                 }
3598         }
3599         return NULL;
3600 }
3601
3602 static int
3603 bnxt_fdir_filter(struct rte_eth_dev *dev,
3604                  enum rte_filter_op filter_op,
3605                  void *arg)
3606 {
3607         struct bnxt *bp = dev->data->dev_private;
3608         struct rte_eth_fdir_filter *fdir  = (struct rte_eth_fdir_filter *)arg;
3609         struct bnxt_filter_info *filter, *match;
3610         struct bnxt_vnic_info *vnic, *mvnic;
3611         int ret = 0, i;
3612
3613         if (filter_op == RTE_ETH_FILTER_NOP)
3614                 return 0;
3615
3616         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3617                 return -EINVAL;
3618
3619         switch (filter_op) {
3620         case RTE_ETH_FILTER_ADD:
3621         case RTE_ETH_FILTER_DELETE:
3622                 /* FALLTHROUGH */
3623                 filter = bnxt_get_unused_filter(bp);
3624                 if (filter == NULL) {
3625                         PMD_DRV_LOG(ERR,
3626                                 "Not enough resources for a new flow.\n");
3627                         return -ENOMEM;
3628                 }
3629
3630                 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3631                 if (ret != 0)
3632                         goto free_filter;
3633                 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3634
3635                 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3636                         vnic = &bp->vnic_info[0];
3637                 else
3638                         vnic = &bp->vnic_info[fdir->action.rx_queue];
3639
3640                 match = bnxt_match_fdir(bp, filter, &mvnic);
3641                 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3642                         if (match->dst_id == vnic->fw_vnic_id) {
3643                                 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3644                                 ret = -EEXIST;
3645                                 goto free_filter;
3646                         } else {
3647                                 match->dst_id = vnic->fw_vnic_id;
3648                                 ret = bnxt_hwrm_set_ntuple_filter(bp,
3649                                                                   match->dst_id,
3650                                                                   match);
3651                                 STAILQ_REMOVE(&mvnic->filter, match,
3652                                               bnxt_filter_info, next);
3653                                 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3654                                 PMD_DRV_LOG(ERR,
3655                                         "Filter with matching pattern exist\n");
3656                                 PMD_DRV_LOG(ERR,
3657                                         "Updated it to new destination q\n");
3658                                 goto free_filter;
3659                         }
3660                 }
3661                 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3662                         PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3663                         ret = -ENOENT;
3664                         goto free_filter;
3665                 }
3666
3667                 if (filter_op == RTE_ETH_FILTER_ADD) {
3668                         ret = bnxt_hwrm_set_ntuple_filter(bp,
3669                                                           filter->dst_id,
3670                                                           filter);
3671                         if (ret)
3672                                 goto free_filter;
3673                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3674                 } else {
3675                         ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3676                         STAILQ_REMOVE(&vnic->filter, match,
3677                                       bnxt_filter_info, next);
3678                         bnxt_free_filter(bp, match);
3679                         bnxt_free_filter(bp, filter);
3680                 }
3681                 break;
3682         case RTE_ETH_FILTER_FLUSH:
3683                 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3684                         struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3685
3686                         STAILQ_FOREACH(filter, &vnic->filter, next) {
3687                                 if (filter->filter_type ==
3688                                     HWRM_CFA_NTUPLE_FILTER) {
3689                                         ret =
3690                                         bnxt_hwrm_clear_ntuple_filter(bp,
3691                                                                       filter);
3692                                         STAILQ_REMOVE(&vnic->filter, filter,
3693                                                       bnxt_filter_info, next);
3694                                 }
3695                         }
3696                 }
3697                 return ret;
3698         case RTE_ETH_FILTER_UPDATE:
3699         case RTE_ETH_FILTER_STATS:
3700         case RTE_ETH_FILTER_INFO:
3701                 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3702                 break;
3703         default:
3704                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3705                 ret = -EINVAL;
3706                 break;
3707         }
3708         return ret;
3709
3710 free_filter:
3711         bnxt_free_filter(bp, filter);
3712         return ret;
3713 }
3714
3715 int
3716 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3717                     enum rte_filter_type filter_type,
3718                     enum rte_filter_op filter_op, void *arg)
3719 {
3720         struct bnxt *bp = dev->data->dev_private;
3721         int ret = 0;
3722
3723         if (!bp)
3724                 return -EIO;
3725
3726         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3727                 struct bnxt_vf_representor *vfr = dev->data->dev_private;
3728                 bp = vfr->parent_dev->data->dev_private;
3729                 /* parent is deleted while children are still valid */
3730                 if (!bp) {
3731                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3732                                     dev->data->port_id,
3733                                     filter_type,
3734                                     filter_op);
3735                         return -EIO;
3736                 }
3737         }
3738
3739         ret = is_bnxt_in_error(bp);
3740         if (ret)
3741                 return ret;
3742
3743         switch (filter_type) {
3744         case RTE_ETH_FILTER_TUNNEL:
3745                 PMD_DRV_LOG(ERR,
3746                         "filter type: %d: To be implemented\n", filter_type);
3747                 break;
3748         case RTE_ETH_FILTER_FDIR:
3749                 ret = bnxt_fdir_filter(dev, filter_op, arg);
3750                 break;
3751         case RTE_ETH_FILTER_NTUPLE:
3752                 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3753                 break;
3754         case RTE_ETH_FILTER_ETHERTYPE:
3755                 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3756                 break;
3757         case RTE_ETH_FILTER_GENERIC:
3758                 if (filter_op != RTE_ETH_FILTER_GET)
3759                         return -EINVAL;
3760                 if (BNXT_TRUFLOW_EN(bp))
3761                         *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3762                 else
3763                         *(const void **)arg = &bnxt_flow_ops;
3764                 break;
3765         default:
3766                 PMD_DRV_LOG(ERR,
3767                         "Filter type (%d) not supported", filter_type);
3768                 ret = -EINVAL;
3769                 break;
3770         }
3771         return ret;
3772 }
3773
3774 static const uint32_t *
3775 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3776 {
3777         static const uint32_t ptypes[] = {
3778                 RTE_PTYPE_L2_ETHER_VLAN,
3779                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3780                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3781                 RTE_PTYPE_L4_ICMP,
3782                 RTE_PTYPE_L4_TCP,
3783                 RTE_PTYPE_L4_UDP,
3784                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3785                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3786                 RTE_PTYPE_INNER_L4_ICMP,
3787                 RTE_PTYPE_INNER_L4_TCP,
3788                 RTE_PTYPE_INNER_L4_UDP,
3789                 RTE_PTYPE_UNKNOWN
3790         };
3791
3792         if (!dev->rx_pkt_burst)
3793                 return NULL;
3794
3795         return ptypes;
3796 }
3797
3798 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3799                          int reg_win)
3800 {
3801         uint32_t reg_base = *reg_arr & 0xfffff000;
3802         uint32_t win_off;
3803         int i;
3804
3805         for (i = 0; i < count; i++) {
3806                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3807                         return -ERANGE;
3808         }
3809         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3810         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3811         return 0;
3812 }
3813
3814 static int bnxt_map_ptp_regs(struct bnxt *bp)
3815 {
3816         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3817         uint32_t *reg_arr;
3818         int rc, i;
3819
3820         reg_arr = ptp->rx_regs;
3821         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3822         if (rc)
3823                 return rc;
3824
3825         reg_arr = ptp->tx_regs;
3826         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3827         if (rc)
3828                 return rc;
3829
3830         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3831                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3832
3833         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3834                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3835
3836         return 0;
3837 }
3838
3839 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3840 {
3841         rte_write32(0, (uint8_t *)bp->bar0 +
3842                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3843         rte_write32(0, (uint8_t *)bp->bar0 +
3844                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3845 }
3846
3847 static uint64_t bnxt_cc_read(struct bnxt *bp)
3848 {
3849         uint64_t ns;
3850
3851         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3852                               BNXT_GRCPF_REG_SYNC_TIME));
3853         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3854                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3855         return ns;
3856 }
3857
3858 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3859 {
3860         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3861         uint32_t fifo;
3862
3863         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3864                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3865         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3866                 return -EAGAIN;
3867
3868         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3869                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3870         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3871                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3872         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3873                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3874
3875         return 0;
3876 }
3877
3878 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3879 {
3880         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3881         struct bnxt_pf_info *pf = bp->pf;
3882         uint16_t port_id;
3883         uint32_t fifo;
3884
3885         if (!ptp)
3886                 return -ENODEV;
3887
3888         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3889                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3890         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3891                 return -EAGAIN;
3892
3893         port_id = pf->port_id;
3894         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3895                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3896
3897         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3898                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3899         if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3900 /*              bnxt_clr_rx_ts(bp);       TBD  */
3901                 return -EBUSY;
3902         }
3903
3904         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3905                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3906         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3907                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3908
3909         return 0;
3910 }
3911
3912 static int
3913 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3914 {
3915         uint64_t ns;
3916         struct bnxt *bp = dev->data->dev_private;
3917         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3918
3919         if (!ptp)
3920                 return 0;
3921
3922         ns = rte_timespec_to_ns(ts);
3923         /* Set the timecounters to a new value. */
3924         ptp->tc.nsec = ns;
3925
3926         return 0;
3927 }
3928
3929 static int
3930 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3931 {
3932         struct bnxt *bp = dev->data->dev_private;
3933         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3934         uint64_t ns, systime_cycles = 0;
3935         int rc = 0;
3936
3937         if (!ptp)
3938                 return 0;
3939
3940         if (BNXT_CHIP_THOR(bp))
3941                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3942                                              &systime_cycles);
3943         else
3944                 systime_cycles = bnxt_cc_read(bp);
3945
3946         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3947         *ts = rte_ns_to_timespec(ns);
3948
3949         return rc;
3950 }
3951 static int
3952 bnxt_timesync_enable(struct rte_eth_dev *dev)
3953 {
3954         struct bnxt *bp = dev->data->dev_private;
3955         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3956         uint32_t shift = 0;
3957         int rc;
3958
3959         if (!ptp)
3960                 return 0;
3961
3962         ptp->rx_filter = 1;
3963         ptp->tx_tstamp_en = 1;
3964         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3965
3966         rc = bnxt_hwrm_ptp_cfg(bp);
3967         if (rc)
3968                 return rc;
3969
3970         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3971         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3972         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3973
3974         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3975         ptp->tc.cc_shift = shift;
3976         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3977
3978         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3979         ptp->rx_tstamp_tc.cc_shift = shift;
3980         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3981
3982         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3983         ptp->tx_tstamp_tc.cc_shift = shift;
3984         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3985
3986         if (!BNXT_CHIP_THOR(bp))
3987                 bnxt_map_ptp_regs(bp);
3988
3989         return 0;
3990 }
3991
3992 static int
3993 bnxt_timesync_disable(struct rte_eth_dev *dev)
3994 {
3995         struct bnxt *bp = dev->data->dev_private;
3996         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3997
3998         if (!ptp)
3999                 return 0;
4000
4001         ptp->rx_filter = 0;
4002         ptp->tx_tstamp_en = 0;
4003         ptp->rxctl = 0;
4004
4005         bnxt_hwrm_ptp_cfg(bp);
4006
4007         if (!BNXT_CHIP_THOR(bp))
4008                 bnxt_unmap_ptp_regs(bp);
4009
4010         return 0;
4011 }
4012
4013 static int
4014 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4015                                  struct timespec *timestamp,
4016                                  uint32_t flags __rte_unused)
4017 {
4018         struct bnxt *bp = dev->data->dev_private;
4019         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4020         uint64_t rx_tstamp_cycles = 0;
4021         uint64_t ns;
4022
4023         if (!ptp)
4024                 return 0;
4025
4026         if (BNXT_CHIP_THOR(bp))
4027                 rx_tstamp_cycles = ptp->rx_timestamp;
4028         else
4029                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
4030
4031         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
4032         *timestamp = rte_ns_to_timespec(ns);
4033         return  0;
4034 }
4035
4036 static int
4037 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4038                                  struct timespec *timestamp)
4039 {
4040         struct bnxt *bp = dev->data->dev_private;
4041         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4042         uint64_t tx_tstamp_cycles = 0;
4043         uint64_t ns;
4044         int rc = 0;
4045
4046         if (!ptp)
4047                 return 0;
4048
4049         if (BNXT_CHIP_THOR(bp))
4050                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
4051                                              &tx_tstamp_cycles);
4052         else
4053                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
4054
4055         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
4056         *timestamp = rte_ns_to_timespec(ns);
4057
4058         return rc;
4059 }
4060
4061 static int
4062 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4063 {
4064         struct bnxt *bp = dev->data->dev_private;
4065         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
4066
4067         if (!ptp)
4068                 return 0;
4069
4070         ptp->tc.nsec += delta;
4071
4072         return 0;
4073 }
4074
4075 static int
4076 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
4077 {
4078         struct bnxt *bp = dev->data->dev_private;
4079         int rc;
4080         uint32_t dir_entries;
4081         uint32_t entry_length;
4082
4083         rc = is_bnxt_in_error(bp);
4084         if (rc)
4085                 return rc;
4086
4087         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
4088                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4089                     bp->pdev->addr.devid, bp->pdev->addr.function);
4090
4091         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4092         if (rc != 0)
4093                 return rc;
4094
4095         return dir_entries * entry_length;
4096 }
4097
4098 static int
4099 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
4100                 struct rte_dev_eeprom_info *in_eeprom)
4101 {
4102         struct bnxt *bp = dev->data->dev_private;
4103         uint32_t index;
4104         uint32_t offset;
4105         int rc;
4106
4107         rc = is_bnxt_in_error(bp);
4108         if (rc)
4109                 return rc;
4110
4111         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4112                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4113                     bp->pdev->addr.devid, bp->pdev->addr.function,
4114                     in_eeprom->offset, in_eeprom->length);
4115
4116         if (in_eeprom->offset == 0) /* special offset value to get directory */
4117                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
4118                                                 in_eeprom->data);
4119
4120         index = in_eeprom->offset >> 24;
4121         offset = in_eeprom->offset & 0xffffff;
4122
4123         if (index != 0)
4124                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
4125                                            in_eeprom->length, in_eeprom->data);
4126
4127         return 0;
4128 }
4129
4130 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
4131 {
4132         switch (dir_type) {
4133         case BNX_DIR_TYPE_CHIMP_PATCH:
4134         case BNX_DIR_TYPE_BOOTCODE:
4135         case BNX_DIR_TYPE_BOOTCODE_2:
4136         case BNX_DIR_TYPE_APE_FW:
4137         case BNX_DIR_TYPE_APE_PATCH:
4138         case BNX_DIR_TYPE_KONG_FW:
4139         case BNX_DIR_TYPE_KONG_PATCH:
4140         case BNX_DIR_TYPE_BONO_FW:
4141         case BNX_DIR_TYPE_BONO_PATCH:
4142                 /* FALLTHROUGH */
4143                 return true;
4144         }
4145
4146         return false;
4147 }
4148
4149 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
4150 {
4151         switch (dir_type) {
4152         case BNX_DIR_TYPE_AVS:
4153         case BNX_DIR_TYPE_EXP_ROM_MBA:
4154         case BNX_DIR_TYPE_PCIE:
4155         case BNX_DIR_TYPE_TSCF_UCODE:
4156         case BNX_DIR_TYPE_EXT_PHY:
4157         case BNX_DIR_TYPE_CCM:
4158         case BNX_DIR_TYPE_ISCSI_BOOT:
4159         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
4160         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
4161                 /* FALLTHROUGH */
4162                 return true;
4163         }
4164
4165         return false;
4166 }
4167
4168 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
4169 {
4170         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
4171                 bnxt_dir_type_is_other_exec_format(dir_type);
4172 }
4173
4174 static int
4175 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
4176                 struct rte_dev_eeprom_info *in_eeprom)
4177 {
4178         struct bnxt *bp = dev->data->dev_private;
4179         uint8_t index, dir_op;
4180         uint16_t type, ext, ordinal, attr;
4181         int rc;
4182
4183         rc = is_bnxt_in_error(bp);
4184         if (rc)
4185                 return rc;
4186
4187         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
4188                     bp->pdev->addr.domain, bp->pdev->addr.bus,
4189                     bp->pdev->addr.devid, bp->pdev->addr.function,
4190                     in_eeprom->offset, in_eeprom->length);
4191
4192         if (!BNXT_PF(bp)) {
4193                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
4194                 return -EINVAL;
4195         }
4196
4197         type = in_eeprom->magic >> 16;
4198
4199         if (type == 0xffff) { /* special value for directory operations */
4200                 index = in_eeprom->magic & 0xff;
4201                 dir_op = in_eeprom->magic >> 8;
4202                 if (index == 0)
4203                         return -EINVAL;
4204                 switch (dir_op) {
4205                 case 0x0e: /* erase */
4206                         if (in_eeprom->offset != ~in_eeprom->magic)
4207                                 return -EINVAL;
4208                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
4209                 default:
4210                         return -EINVAL;
4211                 }
4212         }
4213
4214         /* Create or re-write an NVM item: */
4215         if (bnxt_dir_type_is_executable(type) == true)
4216                 return -EOPNOTSUPP;
4217         ext = in_eeprom->magic & 0xffff;
4218         ordinal = in_eeprom->offset >> 16;
4219         attr = in_eeprom->offset & 0xffff;
4220
4221         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
4222                                      in_eeprom->data, in_eeprom->length);
4223 }
4224
4225 /*
4226  * Initialization
4227  */
4228
4229 static const struct eth_dev_ops bnxt_dev_ops = {
4230         .dev_infos_get = bnxt_dev_info_get_op,
4231         .dev_close = bnxt_dev_close_op,
4232         .dev_configure = bnxt_dev_configure_op,
4233         .dev_start = bnxt_dev_start_op,
4234         .dev_stop = bnxt_dev_stop_op,
4235         .dev_set_link_up = bnxt_dev_set_link_up_op,
4236         .dev_set_link_down = bnxt_dev_set_link_down_op,
4237         .stats_get = bnxt_stats_get_op,
4238         .stats_reset = bnxt_stats_reset_op,
4239         .rx_queue_setup = bnxt_rx_queue_setup_op,
4240         .rx_queue_release = bnxt_rx_queue_release_op,
4241         .tx_queue_setup = bnxt_tx_queue_setup_op,
4242         .tx_queue_release = bnxt_tx_queue_release_op,
4243         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4244         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4245         .reta_update = bnxt_reta_update_op,
4246         .reta_query = bnxt_reta_query_op,
4247         .rss_hash_update = bnxt_rss_hash_update_op,
4248         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4249         .link_update = bnxt_link_update_op,
4250         .promiscuous_enable = bnxt_promiscuous_enable_op,
4251         .promiscuous_disable = bnxt_promiscuous_disable_op,
4252         .allmulticast_enable = bnxt_allmulticast_enable_op,
4253         .allmulticast_disable = bnxt_allmulticast_disable_op,
4254         .mac_addr_add = bnxt_mac_addr_add_op,
4255         .mac_addr_remove = bnxt_mac_addr_remove_op,
4256         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4257         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4258         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4259         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4260         .vlan_filter_set = bnxt_vlan_filter_set_op,
4261         .vlan_offload_set = bnxt_vlan_offload_set_op,
4262         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4263         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4264         .mtu_set = bnxt_mtu_set_op,
4265         .mac_addr_set = bnxt_set_default_mac_addr_op,
4266         .xstats_get = bnxt_dev_xstats_get_op,
4267         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4268         .xstats_reset = bnxt_dev_xstats_reset_op,
4269         .fw_version_get = bnxt_fw_version_get,
4270         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4271         .rxq_info_get = bnxt_rxq_info_get_op,
4272         .txq_info_get = bnxt_txq_info_get_op,
4273         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4274         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4275         .dev_led_on = bnxt_dev_led_on_op,
4276         .dev_led_off = bnxt_dev_led_off_op,
4277         .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
4278         .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
4279         .rx_queue_start = bnxt_rx_queue_start,
4280         .rx_queue_stop = bnxt_rx_queue_stop,
4281         .tx_queue_start = bnxt_tx_queue_start,
4282         .tx_queue_stop = bnxt_tx_queue_stop,
4283         .filter_ctrl = bnxt_filter_ctrl_op,
4284         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4285         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4286         .get_eeprom           = bnxt_get_eeprom_op,
4287         .set_eeprom           = bnxt_set_eeprom_op,
4288         .timesync_enable      = bnxt_timesync_enable,
4289         .timesync_disable     = bnxt_timesync_disable,
4290         .timesync_read_time   = bnxt_timesync_read_time,
4291         .timesync_write_time   = bnxt_timesync_write_time,
4292         .timesync_adjust_time = bnxt_timesync_adjust_time,
4293         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4294         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4295 };
4296
4297 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4298 {
4299         uint32_t offset;
4300
4301         /* Only pre-map the reset GRC registers using window 3 */
4302         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4303                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4304
4305         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4306
4307         return offset;
4308 }
4309
4310 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4311 {
4312         struct bnxt_error_recovery_info *info = bp->recovery_info;
4313         uint32_t reg_base = 0xffffffff;
4314         int i;
4315
4316         /* Only pre-map the monitoring GRC registers using window 2 */
4317         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4318                 uint32_t reg = info->status_regs[i];
4319
4320                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4321                         continue;
4322
4323                 if (reg_base == 0xffffffff)
4324                         reg_base = reg & 0xfffff000;
4325                 if ((reg & 0xfffff000) != reg_base)
4326                         return -ERANGE;
4327
4328                 /* Use mask 0xffc as the Lower 2 bits indicates
4329                  * address space location
4330                  */
4331                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4332                                                 (reg & 0xffc);
4333         }
4334
4335         if (reg_base == 0xffffffff)
4336                 return 0;
4337
4338         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4339                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4340
4341         return 0;
4342 }
4343
4344 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4345 {
4346         struct bnxt_error_recovery_info *info = bp->recovery_info;
4347         uint32_t delay = info->delay_after_reset[index];
4348         uint32_t val = info->reset_reg_val[index];
4349         uint32_t reg = info->reset_reg[index];
4350         uint32_t type, offset;
4351
4352         type = BNXT_FW_STATUS_REG_TYPE(reg);
4353         offset = BNXT_FW_STATUS_REG_OFF(reg);
4354
4355         switch (type) {
4356         case BNXT_FW_STATUS_REG_TYPE_CFG:
4357                 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4358                 break;
4359         case BNXT_FW_STATUS_REG_TYPE_GRC:
4360                 offset = bnxt_map_reset_regs(bp, offset);
4361                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4362                 break;
4363         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4364                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4365                 break;
4366         }
4367         /* wait on a specific interval of time until core reset is complete */
4368         if (delay)
4369                 rte_delay_ms(delay);
4370 }
4371
4372 static void bnxt_dev_cleanup(struct bnxt *bp)
4373 {
4374         bnxt_set_hwrm_link_config(bp, false);
4375         bp->link_info->link_up = 0;
4376         if (bp->eth_dev->data->dev_started)
4377                 bnxt_dev_stop_op(bp->eth_dev);
4378
4379         bnxt_uninit_resources(bp, true);
4380 }
4381
4382 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4383 {
4384         struct rte_eth_dev *dev = bp->eth_dev;
4385         struct rte_vlan_filter_conf *vfc;
4386         int vidx, vbit, rc;
4387         uint16_t vlan_id;
4388
4389         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4390                 vfc = &dev->data->vlan_filter_conf;
4391                 vidx = vlan_id / 64;
4392                 vbit = vlan_id % 64;
4393
4394                 /* Each bit corresponds to a VLAN id */
4395                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4396                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4397                         if (rc)
4398                                 return rc;
4399                 }
4400         }
4401
4402         return 0;
4403 }
4404
4405 static int bnxt_restore_mac_filters(struct bnxt *bp)
4406 {
4407         struct rte_eth_dev *dev = bp->eth_dev;
4408         struct rte_eth_dev_info dev_info;
4409         struct rte_ether_addr *addr;
4410         uint64_t pool_mask;
4411         uint32_t pool = 0;
4412         uint16_t i;
4413         int rc;
4414
4415         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4416                 return 0;
4417
4418         rc = bnxt_dev_info_get_op(dev, &dev_info);
4419         if (rc)
4420                 return rc;
4421
4422         /* replay MAC address configuration */
4423         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4424                 addr = &dev->data->mac_addrs[i];
4425
4426                 /* skip zero address */
4427                 if (rte_is_zero_ether_addr(addr))
4428                         continue;
4429
4430                 pool = 0;
4431                 pool_mask = dev->data->mac_pool_sel[i];
4432
4433                 do {
4434                         if (pool_mask & 1ULL) {
4435                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4436                                 if (rc)
4437                                         return rc;
4438                         }
4439                         pool_mask >>= 1;
4440                         pool++;
4441                 } while (pool_mask);
4442         }
4443
4444         return 0;
4445 }
4446
4447 static int bnxt_restore_filters(struct bnxt *bp)
4448 {
4449         struct rte_eth_dev *dev = bp->eth_dev;
4450         int ret = 0;
4451
4452         if (dev->data->all_multicast) {
4453                 ret = bnxt_allmulticast_enable_op(dev);
4454                 if (ret)
4455                         return ret;
4456         }
4457         if (dev->data->promiscuous) {
4458                 ret = bnxt_promiscuous_enable_op(dev);
4459                 if (ret)
4460                         return ret;
4461         }
4462
4463         ret = bnxt_restore_mac_filters(bp);
4464         if (ret)
4465                 return ret;
4466
4467         ret = bnxt_restore_vlan_filters(bp);
4468         /* TODO restore other filters as well */
4469         return ret;
4470 }
4471
4472 static void bnxt_dev_recover(void *arg)
4473 {
4474         struct bnxt *bp = arg;
4475         int timeout = bp->fw_reset_max_msecs;
4476         int rc = 0;
4477
4478         /* Clear Error flag so that device re-init should happen */
4479         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4480
4481         do {
4482                 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4483                 if (rc == 0)
4484                         break;
4485                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4486                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4487         } while (rc && timeout);
4488
4489         if (rc) {
4490                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4491                 goto err;
4492         }
4493
4494         rc = bnxt_init_resources(bp, true);
4495         if (rc) {
4496                 PMD_DRV_LOG(ERR,
4497                             "Failed to initialize resources after reset\n");
4498                 goto err;
4499         }
4500         /* clear reset flag as the device is initialized now */
4501         bp->flags &= ~BNXT_FLAG_FW_RESET;
4502
4503         rc = bnxt_dev_start_op(bp->eth_dev);
4504         if (rc) {
4505                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4506                 goto err_start;
4507         }
4508
4509         rc = bnxt_restore_filters(bp);
4510         if (rc)
4511                 goto err_start;
4512
4513         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4514         return;
4515 err_start:
4516         bnxt_dev_stop_op(bp->eth_dev);
4517 err:
4518         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4519         bnxt_uninit_resources(bp, false);
4520         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4521 }
4522
4523 void bnxt_dev_reset_and_resume(void *arg)
4524 {
4525         struct bnxt *bp = arg;
4526         int rc;
4527
4528         bnxt_dev_cleanup(bp);
4529
4530         bnxt_wait_for_device_shutdown(bp);
4531
4532         rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4533                                bnxt_dev_recover, (void *)bp);
4534         if (rc)
4535                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4536 }
4537
4538 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4539 {
4540         struct bnxt_error_recovery_info *info = bp->recovery_info;
4541         uint32_t reg = info->status_regs[index];
4542         uint32_t type, offset, val = 0;
4543
4544         type = BNXT_FW_STATUS_REG_TYPE(reg);
4545         offset = BNXT_FW_STATUS_REG_OFF(reg);
4546
4547         switch (type) {
4548         case BNXT_FW_STATUS_REG_TYPE_CFG:
4549                 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4550                 break;
4551         case BNXT_FW_STATUS_REG_TYPE_GRC:
4552                 offset = info->mapped_status_regs[index];
4553                 /* FALLTHROUGH */
4554         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4555                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4556                                        offset));
4557                 break;
4558         }
4559
4560         return val;
4561 }
4562
4563 static int bnxt_fw_reset_all(struct bnxt *bp)
4564 {
4565         struct bnxt_error_recovery_info *info = bp->recovery_info;
4566         uint32_t i;
4567         int rc = 0;
4568
4569         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4570                 /* Reset through master function driver */
4571                 for (i = 0; i < info->reg_array_cnt; i++)
4572                         bnxt_write_fw_reset_reg(bp, i);
4573                 /* Wait for time specified by FW after triggering reset */
4574                 rte_delay_ms(info->master_func_wait_period_after_reset);
4575         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4576                 /* Reset with the help of Kong processor */
4577                 rc = bnxt_hwrm_fw_reset(bp);
4578                 if (rc)
4579                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4580         }
4581
4582         return rc;
4583 }
4584
4585 static void bnxt_fw_reset_cb(void *arg)
4586 {
4587         struct bnxt *bp = arg;
4588         struct bnxt_error_recovery_info *info = bp->recovery_info;
4589         int rc = 0;
4590
4591         /* Only Master function can do FW reset */
4592         if (bnxt_is_master_func(bp) &&
4593             bnxt_is_recovery_enabled(bp)) {
4594                 rc = bnxt_fw_reset_all(bp);
4595                 if (rc) {
4596                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4597                         return;
4598                 }
4599         }
4600
4601         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4602          * EXCEPTION_FATAL_ASYNC event to all the functions
4603          * (including MASTER FUNC). After receiving this Async, all the active
4604          * drivers should treat this case as FW initiated recovery
4605          */
4606         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4607                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4608                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4609
4610                 /* To recover from error */
4611                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4612                                   (void *)bp);
4613         }
4614 }
4615
4616 /* Driver should poll FW heartbeat, reset_counter with the frequency
4617  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4618  * When the driver detects heartbeat stop or change in reset_counter,
4619  * it has to trigger a reset to recover from the error condition.
4620  * A “master PF” is the function who will have the privilege to
4621  * initiate the chimp reset. The master PF will be elected by the
4622  * firmware and will be notified through async message.
4623  */
4624 static void bnxt_check_fw_health(void *arg)
4625 {
4626         struct bnxt *bp = arg;
4627         struct bnxt_error_recovery_info *info = bp->recovery_info;
4628         uint32_t val = 0, wait_msec;
4629
4630         if (!info || !bnxt_is_recovery_enabled(bp) ||
4631             is_bnxt_in_error(bp))
4632                 return;
4633
4634         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4635         if (val == info->last_heart_beat)
4636                 goto reset;
4637
4638         info->last_heart_beat = val;
4639
4640         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4641         if (val != info->last_reset_counter)
4642                 goto reset;
4643
4644         info->last_reset_counter = val;
4645
4646         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4647                           bnxt_check_fw_health, (void *)bp);
4648
4649         return;
4650 reset:
4651         /* Stop DMA to/from device */
4652         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4653         bp->flags |= BNXT_FLAG_FW_RESET;
4654
4655         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4656
4657         if (bnxt_is_master_func(bp))
4658                 wait_msec = info->master_func_wait_period;
4659         else
4660                 wait_msec = info->normal_func_wait_period;
4661
4662         rte_eal_alarm_set(US_PER_MS * wait_msec,
4663                           bnxt_fw_reset_cb, (void *)bp);
4664 }
4665
4666 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4667 {
4668         uint32_t polling_freq;
4669
4670         if (!bnxt_is_recovery_enabled(bp))
4671                 return;
4672
4673         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4674                 return;
4675
4676         polling_freq = bp->recovery_info->driver_polling_freq;
4677
4678         rte_eal_alarm_set(US_PER_MS * polling_freq,
4679                           bnxt_check_fw_health, (void *)bp);
4680         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4681 }
4682
4683 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4684 {
4685         if (!bnxt_is_recovery_enabled(bp))
4686                 return;
4687
4688         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4689         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4690 }
4691
4692 static bool bnxt_vf_pciid(uint16_t device_id)
4693 {
4694         switch (device_id) {
4695         case BROADCOM_DEV_ID_57304_VF:
4696         case BROADCOM_DEV_ID_57406_VF:
4697         case BROADCOM_DEV_ID_5731X_VF:
4698         case BROADCOM_DEV_ID_5741X_VF:
4699         case BROADCOM_DEV_ID_57414_VF:
4700         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4701         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4702         case BROADCOM_DEV_ID_58802_VF:
4703         case BROADCOM_DEV_ID_57500_VF1:
4704         case BROADCOM_DEV_ID_57500_VF2:
4705                 /* FALLTHROUGH */
4706                 return true;
4707         default:
4708                 return false;
4709         }
4710 }
4711
4712 static bool bnxt_thor_device(uint16_t device_id)
4713 {
4714         switch (device_id) {
4715         case BROADCOM_DEV_ID_57508:
4716         case BROADCOM_DEV_ID_57504:
4717         case BROADCOM_DEV_ID_57502:
4718         case BROADCOM_DEV_ID_57508_MF1:
4719         case BROADCOM_DEV_ID_57504_MF1:
4720         case BROADCOM_DEV_ID_57502_MF1:
4721         case BROADCOM_DEV_ID_57508_MF2:
4722         case BROADCOM_DEV_ID_57504_MF2:
4723         case BROADCOM_DEV_ID_57502_MF2:
4724         case BROADCOM_DEV_ID_57500_VF1:
4725         case BROADCOM_DEV_ID_57500_VF2:
4726                 /* FALLTHROUGH */
4727                 return true;
4728         default:
4729                 return false;
4730         }
4731 }
4732
4733 bool bnxt_stratus_device(struct bnxt *bp)
4734 {
4735         uint16_t device_id = bp->pdev->id.device_id;
4736
4737         switch (device_id) {
4738         case BROADCOM_DEV_ID_STRATUS_NIC:
4739         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4740         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4741                 /* FALLTHROUGH */
4742                 return true;
4743         default:
4744                 return false;
4745         }
4746 }
4747
4748 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4749 {
4750         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4751         struct bnxt *bp = eth_dev->data->dev_private;
4752
4753         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4754         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4755         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4756         if (!bp->bar0 || !bp->doorbell_base) {
4757                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4758                 return -ENODEV;
4759         }
4760
4761         bp->eth_dev = eth_dev;
4762         bp->pdev = pci_dev;
4763
4764         return 0;
4765 }
4766
4767 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4768                                   struct bnxt_ctx_pg_info *ctx_pg,
4769                                   uint32_t mem_size,
4770                                   const char *suffix,
4771                                   uint16_t idx)
4772 {
4773         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4774         const struct rte_memzone *mz = NULL;
4775         char mz_name[RTE_MEMZONE_NAMESIZE];
4776         rte_iova_t mz_phys_addr;
4777         uint64_t valid_bits = 0;
4778         uint32_t sz;
4779         int i;
4780
4781         if (!mem_size)
4782                 return 0;
4783
4784         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4785                          BNXT_PAGE_SIZE;
4786         rmem->page_size = BNXT_PAGE_SIZE;
4787         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4788         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4789         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4790
4791         valid_bits = PTU_PTE_VALID;
4792
4793         if (rmem->nr_pages > 1) {
4794                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4795                          "bnxt_ctx_pg_tbl%s_%x_%d",
4796                          suffix, idx, bp->eth_dev->data->port_id);
4797                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4798                 mz = rte_memzone_lookup(mz_name);
4799                 if (!mz) {
4800                         mz = rte_memzone_reserve_aligned(mz_name,
4801                                                 rmem->nr_pages * 8,
4802                                                 SOCKET_ID_ANY,
4803                                                 RTE_MEMZONE_2MB |
4804                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4805                                                 RTE_MEMZONE_IOVA_CONTIG,
4806                                                 BNXT_PAGE_SIZE);
4807                         if (mz == NULL)
4808                                 return -ENOMEM;
4809                 }
4810
4811                 memset(mz->addr, 0, mz->len);
4812                 mz_phys_addr = mz->iova;
4813
4814                 rmem->pg_tbl = mz->addr;
4815                 rmem->pg_tbl_map = mz_phys_addr;
4816                 rmem->pg_tbl_mz = mz;
4817         }
4818
4819         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4820                  suffix, idx, bp->eth_dev->data->port_id);
4821         mz = rte_memzone_lookup(mz_name);
4822         if (!mz) {
4823                 mz = rte_memzone_reserve_aligned(mz_name,
4824                                                  mem_size,
4825                                                  SOCKET_ID_ANY,
4826                                                  RTE_MEMZONE_1GB |
4827                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4828                                                  RTE_MEMZONE_IOVA_CONTIG,
4829                                                  BNXT_PAGE_SIZE);
4830                 if (mz == NULL)
4831                         return -ENOMEM;
4832         }
4833
4834         memset(mz->addr, 0, mz->len);
4835         mz_phys_addr = mz->iova;
4836
4837         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4838                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4839                 rmem->dma_arr[i] = mz_phys_addr + sz;
4840
4841                 if (rmem->nr_pages > 1) {
4842                         if (i == rmem->nr_pages - 2 &&
4843                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4844                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4845                         else if (i == rmem->nr_pages - 1 &&
4846                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4847                                 valid_bits |= PTU_PTE_LAST;
4848
4849                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4850                                                            valid_bits);
4851                 }
4852         }
4853
4854         rmem->mz = mz;
4855         if (rmem->vmem_size)
4856                 rmem->vmem = (void **)mz->addr;
4857         rmem->dma_arr[0] = mz_phys_addr;
4858         return 0;
4859 }
4860
4861 static void bnxt_free_ctx_mem(struct bnxt *bp)
4862 {
4863         int i;
4864
4865         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4866                 return;
4867
4868         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4869         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4870         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4871         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4872         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4873         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4874         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4875         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4876         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4877         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4878         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4879
4880         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4881                 if (bp->ctx->tqm_mem[i])
4882                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4883         }
4884
4885         rte_free(bp->ctx);
4886         bp->ctx = NULL;
4887 }
4888
4889 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4890
4891 #define min_t(type, x, y) ({                    \
4892         type __min1 = (x);                      \
4893         type __min2 = (y);                      \
4894         __min1 < __min2 ? __min1 : __min2; })
4895
4896 #define max_t(type, x, y) ({                    \
4897         type __max1 = (x);                      \
4898         type __max2 = (y);                      \
4899         __max1 > __max2 ? __max1 : __max2; })
4900
4901 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4902
4903 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4904 {
4905         struct bnxt_ctx_pg_info *ctx_pg;
4906         struct bnxt_ctx_mem_info *ctx;
4907         uint32_t mem_size, ena, entries;
4908         uint32_t entries_sp, min;
4909         int i, rc;
4910
4911         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4912         if (rc) {
4913                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4914                 return rc;
4915         }
4916         ctx = bp->ctx;
4917         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4918                 return 0;
4919
4920         ctx_pg = &ctx->qp_mem;
4921         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4922         mem_size = ctx->qp_entry_size * ctx_pg->entries;
4923         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4924         if (rc)
4925                 return rc;
4926
4927         ctx_pg = &ctx->srq_mem;
4928         ctx_pg->entries = ctx->srq_max_l2_entries;
4929         mem_size = ctx->srq_entry_size * ctx_pg->entries;
4930         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4931         if (rc)
4932                 return rc;
4933
4934         ctx_pg = &ctx->cq_mem;
4935         ctx_pg->entries = ctx->cq_max_l2_entries;
4936         mem_size = ctx->cq_entry_size * ctx_pg->entries;
4937         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4938         if (rc)
4939                 return rc;
4940
4941         ctx_pg = &ctx->vnic_mem;
4942         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4943                 ctx->vnic_max_ring_table_entries;
4944         mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4945         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4946         if (rc)
4947                 return rc;
4948
4949         ctx_pg = &ctx->stat_mem;
4950         ctx_pg->entries = ctx->stat_max_entries;
4951         mem_size = ctx->stat_entry_size * ctx_pg->entries;
4952         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4953         if (rc)
4954                 return rc;
4955
4956         min = ctx->tqm_min_entries_per_ring;
4957
4958         entries_sp = ctx->qp_max_l2_entries +
4959                      ctx->vnic_max_vnic_entries +
4960                      2 * ctx->qp_min_qp1_entries + min;
4961         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4962
4963         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4964         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4965         entries = clamp_t(uint32_t, entries, min,
4966                           ctx->tqm_max_entries_per_ring);
4967         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4968                 ctx_pg = ctx->tqm_mem[i];
4969                 ctx_pg->entries = i ? entries : entries_sp;
4970                 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4971                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4972                 if (rc)
4973                         return rc;
4974                 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4975         }
4976
4977         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4978         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4979         if (rc)
4980                 PMD_DRV_LOG(ERR,
4981                             "Failed to configure context mem: rc = %d\n", rc);
4982         else
4983                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4984
4985         return rc;
4986 }
4987
4988 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4989 {
4990         struct rte_pci_device *pci_dev = bp->pdev;
4991         char mz_name[RTE_MEMZONE_NAMESIZE];
4992         const struct rte_memzone *mz = NULL;
4993         uint32_t total_alloc_len;
4994         rte_iova_t mz_phys_addr;
4995
4996         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4997                 return 0;
4998
4999         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5000                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5001                  pci_dev->addr.bus, pci_dev->addr.devid,
5002                  pci_dev->addr.function, "rx_port_stats");
5003         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5004         mz = rte_memzone_lookup(mz_name);
5005         total_alloc_len =
5006                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
5007                                        sizeof(struct rx_port_stats_ext) + 512);
5008         if (!mz) {
5009                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
5010                                          SOCKET_ID_ANY,
5011                                          RTE_MEMZONE_2MB |
5012                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5013                                          RTE_MEMZONE_IOVA_CONTIG);
5014                 if (mz == NULL)
5015                         return -ENOMEM;
5016         }
5017         memset(mz->addr, 0, mz->len);
5018         mz_phys_addr = mz->iova;
5019
5020         bp->rx_mem_zone = (const void *)mz;
5021         bp->hw_rx_port_stats = mz->addr;
5022         bp->hw_rx_port_stats_map = mz_phys_addr;
5023
5024         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
5025                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
5026                  pci_dev->addr.bus, pci_dev->addr.devid,
5027                  pci_dev->addr.function, "tx_port_stats");
5028         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
5029         mz = rte_memzone_lookup(mz_name);
5030         total_alloc_len =
5031                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
5032                                        sizeof(struct tx_port_stats_ext) + 512);
5033         if (!mz) {
5034                 mz = rte_memzone_reserve(mz_name,
5035                                          total_alloc_len,
5036                                          SOCKET_ID_ANY,
5037                                          RTE_MEMZONE_2MB |
5038                                          RTE_MEMZONE_SIZE_HINT_ONLY |
5039                                          RTE_MEMZONE_IOVA_CONTIG);
5040                 if (mz == NULL)
5041                         return -ENOMEM;
5042         }
5043         memset(mz->addr, 0, mz->len);
5044         mz_phys_addr = mz->iova;
5045
5046         bp->tx_mem_zone = (const void *)mz;
5047         bp->hw_tx_port_stats = mz->addr;
5048         bp->hw_tx_port_stats_map = mz_phys_addr;
5049         bp->flags |= BNXT_FLAG_PORT_STATS;
5050
5051         /* Display extended statistics if FW supports it */
5052         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
5053             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
5054             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
5055                 return 0;
5056
5057         bp->hw_rx_port_stats_ext = (void *)
5058                 ((uint8_t *)bp->hw_rx_port_stats +
5059                  sizeof(struct rx_port_stats));
5060         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
5061                 sizeof(struct rx_port_stats);
5062         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
5063
5064         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
5065             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
5066                 bp->hw_tx_port_stats_ext = (void *)
5067                         ((uint8_t *)bp->hw_tx_port_stats +
5068                          sizeof(struct tx_port_stats));
5069                 bp->hw_tx_port_stats_ext_map =
5070                         bp->hw_tx_port_stats_map +
5071                         sizeof(struct tx_port_stats);
5072                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5073         }
5074
5075         return 0;
5076 }
5077
5078 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5079 {
5080         struct bnxt *bp = eth_dev->data->dev_private;
5081         int rc = 0;
5082
5083         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5084                                                RTE_ETHER_ADDR_LEN *
5085                                                bp->max_l2_ctx,
5086                                                0);
5087         if (eth_dev->data->mac_addrs == NULL) {
5088                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5089                 return -ENOMEM;
5090         }
5091
5092         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5093                 if (BNXT_PF(bp))
5094                         return -EINVAL;
5095
5096                 /* Generate a random MAC address, if none was assigned by PF */
5097                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5098                 bnxt_eth_hw_addr_random(bp->mac_addr);
5099                 PMD_DRV_LOG(INFO,
5100                             "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
5101                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5102                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5103
5104                 rc = bnxt_hwrm_set_mac(bp);
5105                 if (rc)
5106                         return rc;
5107         }
5108
5109         /* Copy the permanent MAC from the FUNC_QCAPS response */
5110         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5111
5112         return rc;
5113 }
5114
5115 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5116 {
5117         int rc = 0;
5118
5119         /* MAC is already configured in FW */
5120         if (BNXT_HAS_DFLT_MAC_SET(bp))
5121                 return 0;
5122
5123         /* Restore the old MAC configured */
5124         rc = bnxt_hwrm_set_mac(bp);
5125         if (rc)
5126                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5127
5128         return rc;
5129 }
5130
5131 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5132 {
5133         if (!BNXT_PF(bp))
5134                 return;
5135
5136 #define ALLOW_FUNC(x)   \
5137         { \
5138                 uint32_t arg = (x); \
5139                 bp->pf->vf_req_fwd[((arg) >> 5)] &= \
5140                 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
5141         }
5142
5143         /* Forward all requests if firmware is new enough */
5144         if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
5145              (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
5146             ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
5147                 memset(bp->pf->vf_req_fwd, 0xff, sizeof(bp->pf->vf_req_fwd));
5148         } else {
5149                 PMD_DRV_LOG(WARNING,
5150                             "Firmware too old for VF mailbox functionality\n");
5151                 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5152         }
5153
5154         /*
5155          * The following are used for driver cleanup. If we disallow these,
5156          * VF drivers can't clean up cleanly.
5157          */
5158         ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
5159         ALLOW_FUNC(HWRM_VNIC_FREE);
5160         ALLOW_FUNC(HWRM_RING_FREE);
5161         ALLOW_FUNC(HWRM_RING_GRP_FREE);
5162         ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
5163         ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
5164         ALLOW_FUNC(HWRM_STAT_CTX_FREE);
5165         ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
5166         ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
5167 }
5168
5169 uint16_t
5170 bnxt_get_svif(uint16_t port_id, bool func_svif,
5171               enum bnxt_ulp_intf_type type)
5172 {
5173         struct rte_eth_dev *eth_dev;
5174         struct bnxt *bp;
5175
5176         eth_dev = &rte_eth_devices[port_id];
5177         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5178                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5179                 if (!vfr)
5180                         return 0;
5181
5182                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5183                         return vfr->svif;
5184
5185                 eth_dev = vfr->parent_dev;
5186         }
5187
5188         bp = eth_dev->data->dev_private;
5189
5190         return func_svif ? bp->func_svif : bp->port_svif;
5191 }
5192
5193 uint16_t
5194 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5195 {
5196         struct rte_eth_dev *eth_dev;
5197         struct bnxt_vnic_info *vnic;
5198         struct bnxt *bp;
5199
5200         eth_dev = &rte_eth_devices[port];
5201         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5202                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5203                 if (!vfr)
5204                         return 0;
5205
5206                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5207                         return vfr->dflt_vnic_id;
5208
5209                 eth_dev = vfr->parent_dev;
5210         }
5211
5212         bp = eth_dev->data->dev_private;
5213
5214         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5215
5216         return vnic->fw_vnic_id;
5217 }
5218
5219 uint16_t
5220 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5221 {
5222         struct rte_eth_dev *eth_dev;
5223         struct bnxt *bp;
5224
5225         eth_dev = &rte_eth_devices[port];
5226         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5227                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5228                 if (!vfr)
5229                         return 0;
5230
5231                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5232                         return vfr->fw_fid;
5233
5234                 eth_dev = vfr->parent_dev;
5235         }
5236
5237         bp = eth_dev->data->dev_private;
5238
5239         return bp->fw_fid;
5240 }
5241
5242 enum bnxt_ulp_intf_type
5243 bnxt_get_interface_type(uint16_t port)
5244 {
5245         struct rte_eth_dev *eth_dev;
5246         struct bnxt *bp;
5247
5248         eth_dev = &rte_eth_devices[port];
5249         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5250                 return BNXT_ULP_INTF_TYPE_VF_REP;
5251
5252         bp = eth_dev->data->dev_private;
5253         if (BNXT_PF(bp))
5254                 return BNXT_ULP_INTF_TYPE_PF;
5255         else if (BNXT_VF_IS_TRUSTED(bp))
5256                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5257         else if (BNXT_VF(bp))
5258                 return BNXT_ULP_INTF_TYPE_VF;
5259
5260         return BNXT_ULP_INTF_TYPE_INVALID;
5261 }
5262
5263 uint16_t
5264 bnxt_get_phy_port_id(uint16_t port_id)
5265 {
5266         struct bnxt_vf_representor *vfr;
5267         struct rte_eth_dev *eth_dev;
5268         struct bnxt *bp;
5269
5270         eth_dev = &rte_eth_devices[port_id];
5271         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5272                 vfr = eth_dev->data->dev_private;
5273                 if (!vfr)
5274                         return 0;
5275
5276                 eth_dev = vfr->parent_dev;
5277         }
5278
5279         bp = eth_dev->data->dev_private;
5280
5281         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5282 }
5283
5284 uint16_t
5285 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5286 {
5287         struct rte_eth_dev *eth_dev;
5288         struct bnxt *bp;
5289
5290         eth_dev = &rte_eth_devices[port_id];
5291         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5292                 struct bnxt_vf_representor *vfr = eth_dev->data->dev_private;
5293                 if (!vfr)
5294                         return 0;
5295
5296                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5297                         return vfr->fw_fid - 1;
5298
5299                 eth_dev = vfr->parent_dev;
5300         }
5301
5302         bp = eth_dev->data->dev_private;
5303
5304         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5305 }
5306
5307 uint16_t
5308 bnxt_get_vport(uint16_t port_id)
5309 {
5310         return (1 << bnxt_get_phy_port_id(port_id));
5311 }
5312
5313 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5314 {
5315         struct bnxt_error_recovery_info *info = bp->recovery_info;
5316
5317         if (info) {
5318                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5319                         memset(info, 0, sizeof(*info));
5320                 return;
5321         }
5322
5323         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5324                 return;
5325
5326         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5327                            sizeof(*info), 0);
5328         if (!info)
5329                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5330
5331         bp->recovery_info = info;
5332 }
5333
5334 static void bnxt_check_fw_status(struct bnxt *bp)
5335 {
5336         uint32_t fw_status;
5337
5338         if (!(bp->recovery_info &&
5339               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5340                 return;
5341
5342         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5343         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5344                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5345                             fw_status);
5346 }
5347
5348 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5349 {
5350         struct bnxt_error_recovery_info *info = bp->recovery_info;
5351         uint32_t status_loc;
5352         uint32_t sig_ver;
5353
5354         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5355                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5356         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5357                                    BNXT_GRCP_WINDOW_2_BASE +
5358                                    offsetof(struct hcomm_status,
5359                                             sig_ver)));
5360         /* If the signature is absent, then FW does not support this feature */
5361         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5362             HCOMM_STATUS_SIGNATURE_VAL)
5363                 return 0;
5364
5365         if (!info) {
5366                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5367                                    sizeof(*info), 0);
5368                 if (!info)
5369                         return -ENOMEM;
5370                 bp->recovery_info = info;
5371         } else {
5372                 memset(info, 0, sizeof(*info));
5373         }
5374
5375         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5376                                       BNXT_GRCP_WINDOW_2_BASE +
5377                                       offsetof(struct hcomm_status,
5378                                                fw_status_loc)));
5379
5380         /* Only pre-map the FW health status GRC register */
5381         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5382                 return 0;
5383
5384         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5385         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5386                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5387
5388         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5389                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5390
5391         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5392
5393         return 0;
5394 }
5395
5396 static int bnxt_init_fw(struct bnxt *bp)
5397 {
5398         uint16_t mtu;
5399         int rc = 0;
5400
5401         bp->fw_cap = 0;
5402
5403         rc = bnxt_map_hcomm_fw_status_reg(bp);
5404         if (rc)
5405                 return rc;
5406
5407         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5408         if (rc) {
5409                 bnxt_check_fw_status(bp);
5410                 return rc;
5411         }
5412
5413         rc = bnxt_hwrm_func_reset(bp);
5414         if (rc)
5415                 return -EIO;
5416
5417         rc = bnxt_hwrm_vnic_qcaps(bp);
5418         if (rc)
5419                 return rc;
5420
5421         rc = bnxt_hwrm_queue_qportcfg(bp);
5422         if (rc)
5423                 return rc;
5424
5425         /* Get the MAX capabilities for this function.
5426          * This function also allocates context memory for TQM rings and
5427          * informs the firmware about this allocated backing store memory.
5428          */
5429         rc = bnxt_hwrm_func_qcaps(bp);
5430         if (rc)
5431                 return rc;
5432
5433         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5434         if (rc)
5435                 return rc;
5436
5437         bnxt_hwrm_port_mac_qcfg(bp);
5438
5439         bnxt_hwrm_parent_pf_qcfg(bp);
5440
5441         bnxt_hwrm_port_phy_qcaps(bp);
5442
5443         bnxt_alloc_error_recovery_info(bp);
5444         /* Get the adapter error recovery support info */
5445         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5446         if (rc)
5447                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5448
5449         bnxt_hwrm_port_led_qcaps(bp);
5450
5451         return 0;
5452 }
5453
5454 static int
5455 bnxt_init_locks(struct bnxt *bp)
5456 {
5457         int err;
5458
5459         err = pthread_mutex_init(&bp->flow_lock, NULL);
5460         if (err) {
5461                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5462                 return err;
5463         }
5464
5465         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5466         if (err)
5467                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5468         return err;
5469 }
5470
5471 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5472 {
5473         int rc = 0;
5474
5475         rc = bnxt_init_fw(bp);
5476         if (rc)
5477                 return rc;
5478
5479         if (!reconfig_dev) {
5480                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5481                 if (rc)
5482                         return rc;
5483         } else {
5484                 rc = bnxt_restore_dflt_mac(bp);
5485                 if (rc)
5486                         return rc;
5487         }
5488
5489         bnxt_config_vf_req_fwd(bp);
5490
5491         rc = bnxt_hwrm_func_driver_register(bp);
5492         if (rc) {
5493                 PMD_DRV_LOG(ERR, "Failed to register driver");
5494                 return -EBUSY;
5495         }
5496
5497         if (BNXT_PF(bp)) {
5498                 if (bp->pdev->max_vfs) {
5499                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5500                         if (rc) {
5501                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5502                                 return rc;
5503                         }
5504                 } else {
5505                         rc = bnxt_hwrm_allocate_pf_only(bp);
5506                         if (rc) {
5507                                 PMD_DRV_LOG(ERR,
5508                                             "Failed to allocate PF resources");
5509                                 return rc;
5510                         }
5511                 }
5512         }
5513
5514         rc = bnxt_alloc_mem(bp, reconfig_dev);
5515         if (rc)
5516                 return rc;
5517
5518         rc = bnxt_setup_int(bp);
5519         if (rc)
5520                 return rc;
5521
5522         rc = bnxt_request_int(bp);
5523         if (rc)
5524                 return rc;
5525
5526         rc = bnxt_init_ctx_mem(bp);
5527         if (rc) {
5528                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5529                 return rc;
5530         }
5531
5532         rc = bnxt_init_locks(bp);
5533         if (rc)
5534                 return rc;
5535
5536         return 0;
5537 }
5538
5539 static int
5540 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5541                           const char *value, void *opaque_arg)
5542 {
5543         struct bnxt *bp = opaque_arg;
5544         unsigned long truflow;
5545         char *end = NULL;
5546
5547         if (!value || !opaque_arg) {
5548                 PMD_DRV_LOG(ERR,
5549                             "Invalid parameter passed to truflow devargs.\n");
5550                 return -EINVAL;
5551         }
5552
5553         truflow = strtoul(value, &end, 10);
5554         if (end == NULL || *end != '\0' ||
5555             (truflow == ULONG_MAX && errno == ERANGE)) {
5556                 PMD_DRV_LOG(ERR,
5557                             "Invalid parameter passed to truflow devargs.\n");
5558                 return -EINVAL;
5559         }
5560
5561         if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5562                 PMD_DRV_LOG(ERR,
5563                             "Invalid value passed to truflow devargs.\n");
5564                 return -EINVAL;
5565         }
5566
5567         bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5568         if (BNXT_TRUFLOW_EN(bp))
5569                 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5570
5571         return 0;
5572 }
5573
5574 static int
5575 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5576                              const char *value, void *opaque_arg)
5577 {
5578         struct bnxt *bp = opaque_arg;
5579         unsigned long flow_xstat;
5580         char *end = NULL;
5581
5582         if (!value || !opaque_arg) {
5583                 PMD_DRV_LOG(ERR,
5584                             "Invalid parameter passed to flow_xstat devarg.\n");
5585                 return -EINVAL;
5586         }
5587
5588         flow_xstat = strtoul(value, &end, 10);
5589         if (end == NULL || *end != '\0' ||
5590             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5591                 PMD_DRV_LOG(ERR,
5592                             "Invalid parameter passed to flow_xstat devarg.\n");
5593                 return -EINVAL;
5594         }
5595
5596         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5597                 PMD_DRV_LOG(ERR,
5598                             "Invalid value passed to flow_xstat devarg.\n");
5599                 return -EINVAL;
5600         }
5601
5602         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5603         if (BNXT_FLOW_XSTATS_EN(bp))
5604                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5605
5606         return 0;
5607 }
5608
5609 static int
5610 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5611                                         const char *value, void *opaque_arg)
5612 {
5613         struct bnxt *bp = opaque_arg;
5614         unsigned long max_num_kflows;
5615         char *end = NULL;
5616
5617         if (!value || !opaque_arg) {
5618                 PMD_DRV_LOG(ERR,
5619                         "Invalid parameter passed to max_num_kflows devarg.\n");
5620                 return -EINVAL;
5621         }
5622
5623         max_num_kflows = strtoul(value, &end, 10);
5624         if (end == NULL || *end != '\0' ||
5625                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5626                 PMD_DRV_LOG(ERR,
5627                         "Invalid parameter passed to max_num_kflows devarg.\n");
5628                 return -EINVAL;
5629         }
5630
5631         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5632                 PMD_DRV_LOG(ERR,
5633                         "Invalid value passed to max_num_kflows devarg.\n");
5634                 return -EINVAL;
5635         }
5636
5637         bp->max_num_kflows = max_num_kflows;
5638         if (bp->max_num_kflows)
5639                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5640                                 max_num_kflows);
5641
5642         return 0;
5643 }
5644
5645 static void
5646 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5647 {
5648         struct rte_kvargs *kvlist;
5649
5650         if (devargs == NULL)
5651                 return;
5652
5653         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5654         if (kvlist == NULL)
5655                 return;
5656
5657         /*
5658          * Handler for "truflow" devarg.
5659          * Invoked as for ex: "-w 0000:00:0d.0,host-based-truflow=1"
5660          */
5661         rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5662                            bnxt_parse_devarg_truflow, bp);
5663
5664         /*
5665          * Handler for "flow_xstat" devarg.
5666          * Invoked as for ex: "-w 0000:00:0d.0,flow_xstat=1"
5667          */
5668         rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5669                            bnxt_parse_devarg_flow_xstat, bp);
5670
5671         /*
5672          * Handler for "max_num_kflows" devarg.
5673          * Invoked as for ex: "-w 000:00:0d.0,max_num_kflows=32"
5674          */
5675         rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5676                            bnxt_parse_devarg_max_num_kflows, bp);
5677
5678         rte_kvargs_free(kvlist);
5679 }
5680
5681 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5682 {
5683         int rc = 0;
5684
5685         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5686                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5687                 if (rc)
5688                         PMD_DRV_LOG(ERR,
5689                                     "Failed to alloc switch domain: %d\n", rc);
5690                 else
5691                         PMD_DRV_LOG(INFO,
5692                                     "Switch domain allocated %d\n",
5693                                     bp->switch_domain_id);
5694         }
5695
5696         return rc;
5697 }
5698
5699 static int
5700 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5701 {
5702         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5703         static int version_printed;
5704         struct bnxt *bp;
5705         int rc;
5706
5707         if (version_printed++ == 0)
5708                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5709
5710         eth_dev->dev_ops = &bnxt_dev_ops;
5711         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5712         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5713         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5714         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5715         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5716
5717         /*
5718          * For secondary processes, we don't initialise any further
5719          * as primary has already done this work.
5720          */
5721         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5722                 return 0;
5723
5724         rte_eth_copy_pci_info(eth_dev, pci_dev);
5725
5726         bp = eth_dev->data->dev_private;
5727
5728         /* Parse dev arguments passed on when starting the DPDK application. */
5729         bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5730
5731         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5732
5733         if (bnxt_vf_pciid(pci_dev->id.device_id))
5734                 bp->flags |= BNXT_FLAG_VF;
5735
5736         if (bnxt_thor_device(pci_dev->id.device_id))
5737                 bp->flags |= BNXT_FLAG_THOR_CHIP;
5738
5739         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5740             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5741             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5742             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5743                 bp->flags |= BNXT_FLAG_STINGRAY;
5744
5745         rc = bnxt_init_board(eth_dev);
5746         if (rc) {
5747                 PMD_DRV_LOG(ERR,
5748                             "Failed to initialize board rc: %x\n", rc);
5749                 return rc;
5750         }
5751
5752         rc = bnxt_alloc_pf_info(bp);
5753         if (rc)
5754                 goto error_free;
5755
5756         rc = bnxt_alloc_link_info(bp);
5757         if (rc)
5758                 goto error_free;
5759
5760         rc = bnxt_alloc_parent_info(bp);
5761         if (rc)
5762                 goto error_free;
5763
5764         rc = bnxt_alloc_hwrm_resources(bp);
5765         if (rc) {
5766                 PMD_DRV_LOG(ERR,
5767                             "Failed to allocate hwrm resource rc: %x\n", rc);
5768                 goto error_free;
5769         }
5770         rc = bnxt_alloc_leds_info(bp);
5771         if (rc)
5772                 goto error_free;
5773
5774         rc = bnxt_alloc_cos_queues(bp);
5775         if (rc)
5776                 goto error_free;
5777
5778         rc = bnxt_init_resources(bp, false);
5779         if (rc)
5780                 goto error_free;
5781
5782         rc = bnxt_alloc_stats_mem(bp);
5783         if (rc)
5784                 goto error_free;
5785
5786         bnxt_alloc_switch_domain(bp);
5787
5788         /* Pass the information to the rte_eth_dev_close() that it should also
5789          * release the private port resources.
5790          */
5791         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
5792
5793         PMD_DRV_LOG(INFO,
5794                     DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5795                     pci_dev->mem_resource[0].phys_addr,
5796                     pci_dev->mem_resource[0].addr);
5797
5798         return 0;
5799
5800 error_free:
5801         bnxt_dev_uninit(eth_dev);
5802         return rc;
5803 }
5804
5805
5806 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5807 {
5808         if (!ctx)
5809                 return;
5810
5811         if (ctx->va)
5812                 rte_free(ctx->va);
5813
5814         ctx->va = NULL;
5815         ctx->dma = RTE_BAD_IOVA;
5816         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5817 }
5818
5819 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5820 {
5821         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5822                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5823                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
5824                                   bp->flow_stat->max_fc,
5825                                   false);
5826
5827         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5828                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5829                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
5830                                   bp->flow_stat->max_fc,
5831                                   false);
5832
5833         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5834                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5835         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5836
5837         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5838                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5839         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5840
5841         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5842                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5843         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5844
5845         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5846                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5847         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5848 }
5849
5850 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5851 {
5852         bnxt_unregister_fc_ctx_mem(bp);
5853
5854         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5855         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5856         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5857         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5858 }
5859
5860 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5861 {
5862         if (BNXT_FLOW_XSTATS_EN(bp))
5863                 bnxt_uninit_fc_ctx_mem(bp);
5864 }
5865
5866 static void
5867 bnxt_free_error_recovery_info(struct bnxt *bp)
5868 {
5869         rte_free(bp->recovery_info);
5870         bp->recovery_info = NULL;
5871         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5872 }
5873
5874 static void
5875 bnxt_uninit_locks(struct bnxt *bp)
5876 {
5877         pthread_mutex_destroy(&bp->flow_lock);
5878         pthread_mutex_destroy(&bp->def_cp_lock);
5879         if (bp->rep_info) {
5880                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5881                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
5882         }
5883 }
5884
5885 static int
5886 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5887 {
5888         int rc;
5889
5890         bnxt_free_int(bp);
5891         bnxt_free_mem(bp, reconfig_dev);
5892         bnxt_hwrm_func_buf_unrgtr(bp);
5893         rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5894         bp->flags &= ~BNXT_FLAG_REGISTERED;
5895         bnxt_free_ctx_mem(bp);
5896         if (!reconfig_dev) {
5897                 bnxt_free_hwrm_resources(bp);
5898                 bnxt_free_error_recovery_info(bp);
5899         }
5900
5901         bnxt_uninit_ctx_mem(bp);
5902
5903         bnxt_uninit_locks(bp);
5904         bnxt_free_flow_stats_info(bp);
5905         bnxt_free_rep_info(bp);
5906         rte_free(bp->ptp_cfg);
5907         bp->ptp_cfg = NULL;
5908         return rc;
5909 }
5910
5911 static int
5912 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5913 {
5914         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5915                 return -EPERM;
5916
5917         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5918
5919         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5920                 bnxt_dev_close_op(eth_dev);
5921
5922         return 0;
5923 }
5924
5925 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5926 {
5927         struct bnxt *bp = eth_dev->data->dev_private;
5928         struct rte_eth_dev *vf_rep_eth_dev;
5929         int ret = 0, i;
5930
5931         if (!bp)
5932                 return -EINVAL;
5933
5934         for (i = 0; i < bp->num_reps; i++) {
5935                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5936                 if (!vf_rep_eth_dev)
5937                         continue;
5938                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5939                             vf_rep_eth_dev->data->port_id);
5940                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_vf_representor_uninit);
5941         }
5942         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5943                     eth_dev->data->port_id);
5944         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5945
5946         return ret;
5947 }
5948
5949 static void bnxt_free_rep_info(struct bnxt *bp)
5950 {
5951         rte_free(bp->rep_info);
5952         bp->rep_info = NULL;
5953         rte_free(bp->cfa_code_map);
5954         bp->cfa_code_map = NULL;
5955 }
5956
5957 static int bnxt_init_rep_info(struct bnxt *bp)
5958 {
5959         int i = 0, rc;
5960
5961         if (bp->rep_info)
5962                 return 0;
5963
5964         bp->rep_info = rte_zmalloc("bnxt_rep_info",
5965                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5966                                    0);
5967         if (!bp->rep_info) {
5968                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5969                 return -ENOMEM;
5970         }
5971         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5972                                        sizeof(*bp->cfa_code_map) *
5973                                        BNXT_MAX_CFA_CODE, 0);
5974         if (!bp->cfa_code_map) {
5975                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5976                 bnxt_free_rep_info(bp);
5977                 return -ENOMEM;
5978         }
5979
5980         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5981                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5982
5983         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5984         if (rc) {
5985                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5986                 bnxt_free_rep_info(bp);
5987                 return rc;
5988         }
5989
5990         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5991         if (rc) {
5992                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5993                 bnxt_free_rep_info(bp);
5994                 return rc;
5995         }
5996
5997         return rc;
5998 }
5999
6000 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6001                                struct rte_eth_devargs eth_da,
6002                                struct rte_eth_dev *backing_eth_dev)
6003 {
6004         struct rte_eth_dev *vf_rep_eth_dev;
6005         char name[RTE_ETH_NAME_MAX_LEN];
6006         struct bnxt *backing_bp;
6007         uint16_t num_rep;
6008         int i, ret = 0;
6009
6010         num_rep = eth_da.nb_representor_ports;
6011         if (num_rep > BNXT_MAX_VF_REPS) {
6012                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6013                             num_rep, BNXT_MAX_VF_REPS);
6014                 return -EINVAL;
6015         }
6016
6017         if (num_rep > RTE_MAX_ETHPORTS) {
6018                 PMD_DRV_LOG(ERR,
6019                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6020                             num_rep, RTE_MAX_ETHPORTS);
6021                 return -EINVAL;
6022         }
6023
6024         backing_bp = backing_eth_dev->data->dev_private;
6025
6026         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6027                 PMD_DRV_LOG(ERR,
6028                             "Not a PF or trusted VF. No Representor support\n");
6029                 /* Returning an error is not an option.
6030                  * Applications are not handling this correctly
6031                  */
6032                 return 0;
6033         }
6034
6035         if (bnxt_init_rep_info(backing_bp))
6036                 return 0;
6037
6038         for (i = 0; i < num_rep; i++) {
6039                 struct bnxt_vf_representor representor = {
6040                         .vf_id = eth_da.representor_ports[i],
6041                         .switch_domain_id = backing_bp->switch_domain_id,
6042                         .parent_dev = backing_eth_dev
6043                 };
6044
6045                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6046                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6047                                     representor.vf_id, BNXT_MAX_VF_REPS);
6048                         continue;
6049                 }
6050
6051                 /* representor port net_bdf_port */
6052                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6053                          pci_dev->device.name, eth_da.representor_ports[i]);
6054
6055                 ret = rte_eth_dev_create(&pci_dev->device, name,
6056                                          sizeof(struct bnxt_vf_representor),
6057                                          NULL, NULL,
6058                                          bnxt_vf_representor_init,
6059                                          &representor);
6060
6061                 if (!ret) {
6062                         vf_rep_eth_dev = rte_eth_dev_allocated(name);
6063                         if (!vf_rep_eth_dev) {
6064                                 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6065                                             " for VF-Rep: %s.", name);
6066                                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6067                                 ret = -ENODEV;
6068                                 return ret;
6069                         }
6070                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6071                                     backing_eth_dev->data->port_id);
6072                         backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6073                                 vf_rep_eth_dev;
6074                         backing_bp->num_reps++;
6075                 } else {
6076                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6077                                     "representor %s.", name);
6078                         bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6079                 }
6080         }
6081
6082         return ret;
6083 }
6084
6085 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6086                           struct rte_pci_device *pci_dev)
6087 {
6088         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6089         struct rte_eth_dev *backing_eth_dev;
6090         uint16_t num_rep;
6091         int ret = 0;
6092
6093         if (pci_dev->device.devargs) {
6094                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6095                                             &eth_da);
6096                 if (ret)
6097                         return ret;
6098         }
6099
6100         num_rep = eth_da.nb_representor_ports;
6101         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6102                     num_rep);
6103
6104         /* We could come here after first level of probe is already invoked
6105          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6106          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6107          */
6108         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6109         if (backing_eth_dev == NULL) {
6110                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6111                                          sizeof(struct bnxt),
6112                                          eth_dev_pci_specific_init, pci_dev,
6113                                          bnxt_dev_init, NULL);
6114
6115                 if (ret || !num_rep)
6116                         return ret;
6117
6118                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6119         }
6120         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6121                     backing_eth_dev->data->port_id);
6122         /* probe representor ports now */
6123         ret = bnxt_rep_port_probe(pci_dev, eth_da, backing_eth_dev);
6124
6125         return ret;
6126 }
6127
6128 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6129 {
6130         struct rte_eth_dev *eth_dev;
6131
6132         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6133         if (!eth_dev)
6134                 return 0; /* Invoked typically only by OVS-DPDK, by the
6135                            * time it comes here the eth_dev is already
6136                            * deleted by rte_eth_dev_close(), so returning
6137                            * +ve value will at least help in proper cleanup
6138                            */
6139
6140         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6141         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6142                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6143                         return rte_eth_dev_destroy(eth_dev,
6144                                                    bnxt_vf_representor_uninit);
6145                 else
6146                         return rte_eth_dev_destroy(eth_dev,
6147                                                    bnxt_dev_uninit);
6148         } else {
6149                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6150         }
6151 }
6152
6153 static struct rte_pci_driver bnxt_rte_pmd = {
6154         .id_table = bnxt_pci_id_map,
6155         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6156                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6157                                                   * and OVS-DPDK
6158                                                   */
6159         .probe = bnxt_pci_probe,
6160         .remove = bnxt_pci_remove,
6161 };
6162
6163 static bool
6164 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6165 {
6166         if (strcmp(dev->device->driver->name, drv->driver.name))
6167                 return false;
6168
6169         return true;
6170 }
6171
6172 bool is_bnxt_supported(struct rte_eth_dev *dev)
6173 {
6174         return is_device_supported(dev, &bnxt_rte_pmd);
6175 }
6176
6177 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6178 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6179 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6180 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");