1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
19 #include "bnxt_filter.h"
20 #include "bnxt_hwrm.h"
22 #include "bnxt_reps.h"
23 #include "bnxt_ring.h"
26 #include "bnxt_stats.h"
29 #include "bnxt_vnic.h"
30 #include "hsi_struct_def_dpdk.h"
31 #include "bnxt_nvm_defs.h"
32 #include "bnxt_tf_common.h"
33 #include "ulp_flow_db.h"
34 #include "rte_pmd_bnxt.h"
36 #define DRV_MODULE_NAME "bnxt"
37 static const char bnxt_version[] =
38 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
41 * The set of PCI devices this driver supports
43 static const struct rte_pci_id bnxt_pci_id_map[] = {
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
87 { .vendor_id = 0, /* sentinel */ },
90 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
91 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
92 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
93 #define BNXT_DEVARG_REPRESENTOR "representor"
94 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf"
95 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf"
96 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f"
97 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r"
98 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f"
99 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r"
101 static const char *const bnxt_dev_args[] = {
102 BNXT_DEVARG_REPRESENTOR,
104 BNXT_DEVARG_FLOW_XSTAT,
105 BNXT_DEVARG_MAX_NUM_KFLOWS,
106 BNXT_DEVARG_REP_BASED_PF,
107 BNXT_DEVARG_REP_IS_PF,
108 BNXT_DEVARG_REP_Q_R2F,
109 BNXT_DEVARG_REP_Q_F2R,
110 BNXT_DEVARG_REP_FC_R2F,
111 BNXT_DEVARG_REP_FC_F2R,
116 * truflow == false to disable the feature
117 * truflow == true to enable the feature
119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
122 * flow_xstat == false to disable the feature
123 * flow_xstat == true to enable the feature
125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
128 * rep_is_pf == false to indicate VF representor
129 * rep_is_pf == true to indicate PF representor
131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1)
134 * rep_based_pf == Physical index of the PF
136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15)
138 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3)
143 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3)
148 * rep_fc_r2f == Flow control for the representor to endpoint direction
150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1)
153 * rep_fc_f2r == Flow control for the endpoint to representor direction
155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1)
157 int bnxt_cfa_code_dynfield_offset = -1;
160 * max_num_kflows must be >= 32
161 * and must be a power-of-2 supported value
162 * return: 1 -> invalid
165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
167 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
176 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
177 static int bnxt_restore_vlan_filters(struct bnxt *bp);
178 static void bnxt_dev_recover(void *arg);
179 static void bnxt_free_error_recovery_info(struct bnxt *bp);
180 static void bnxt_free_rep_info(struct bnxt *bp);
182 int is_bnxt_in_error(struct bnxt *bp)
184 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
186 if (bp->flags & BNXT_FLAG_FW_RESET)
192 /***********************/
195 * High level utility functions
198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
200 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
201 BNXT_RSS_TBL_SIZE_P5);
203 if (!BNXT_CHIP_P5(bp))
206 return RTE_ALIGN_MUL_CEIL(num_rss_rings,
207 BNXT_RSS_ENTRIES_PER_CTX_P5) /
208 BNXT_RSS_ENTRIES_PER_CTX_P5;
211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
213 if (!BNXT_CHIP_P5(bp))
214 return HW_HASH_INDEX_SIZE;
216 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
219 static void bnxt_free_parent_info(struct bnxt *bp)
221 rte_free(bp->parent);
224 static void bnxt_free_pf_info(struct bnxt *bp)
229 static void bnxt_free_link_info(struct bnxt *bp)
231 rte_free(bp->link_info);
234 static void bnxt_free_leds_info(struct bnxt *bp)
243 static void bnxt_free_flow_stats_info(struct bnxt *bp)
245 rte_free(bp->flow_stat);
246 bp->flow_stat = NULL;
249 static void bnxt_free_cos_queues(struct bnxt *bp)
251 rte_free(bp->rx_cos_queue);
252 rte_free(bp->tx_cos_queue);
255 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
257 bnxt_free_filter_mem(bp);
258 bnxt_free_vnic_attributes(bp);
259 bnxt_free_vnic_mem(bp);
261 /* tx/rx rings are configured as part of *_queue_setup callbacks.
262 * If the number of rings change across fw update,
263 * we don't have much choice except to warn the user.
267 bnxt_free_tx_rings(bp);
268 bnxt_free_rx_rings(bp);
270 bnxt_free_async_cp_ring(bp);
271 bnxt_free_rxtx_nq_ring(bp);
273 rte_free(bp->grp_info);
277 static int bnxt_alloc_parent_info(struct bnxt *bp)
279 bp->parent = rte_zmalloc("bnxt_parent_info",
280 sizeof(struct bnxt_parent_info), 0);
281 if (bp->parent == NULL)
287 static int bnxt_alloc_pf_info(struct bnxt *bp)
289 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
296 static int bnxt_alloc_link_info(struct bnxt *bp)
299 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
300 if (bp->link_info == NULL)
306 static int bnxt_alloc_leds_info(struct bnxt *bp)
311 bp->leds = rte_zmalloc("bnxt_leds",
312 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
314 if (bp->leds == NULL)
320 static int bnxt_alloc_cos_queues(struct bnxt *bp)
323 rte_zmalloc("bnxt_rx_cosq",
324 BNXT_COS_QUEUE_COUNT *
325 sizeof(struct bnxt_cos_queue_info),
327 if (bp->rx_cos_queue == NULL)
331 rte_zmalloc("bnxt_tx_cosq",
332 BNXT_COS_QUEUE_COUNT *
333 sizeof(struct bnxt_cos_queue_info),
335 if (bp->tx_cos_queue == NULL)
341 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
343 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
344 sizeof(struct bnxt_flow_stat_info), 0);
345 if (bp->flow_stat == NULL)
351 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
355 rc = bnxt_alloc_ring_grps(bp);
359 rc = bnxt_alloc_async_ring_struct(bp);
363 rc = bnxt_alloc_vnic_mem(bp);
367 rc = bnxt_alloc_vnic_attributes(bp);
371 rc = bnxt_alloc_filter_mem(bp);
375 rc = bnxt_alloc_async_cp_ring(bp);
379 rc = bnxt_alloc_rxtx_nq_ring(bp);
383 if (BNXT_FLOW_XSTATS_EN(bp)) {
384 rc = bnxt_alloc_flow_stats_info(bp);
392 bnxt_free_mem(bp, reconfig);
396 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
398 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
399 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
400 uint64_t rx_offloads = dev_conf->rxmode.offloads;
401 struct bnxt_rx_queue *rxq;
405 rc = bnxt_vnic_grp_alloc(bp, vnic);
409 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
410 vnic_id, vnic, vnic->fw_grp_ids);
412 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
416 /* Alloc RSS context only if RSS mode is enabled */
417 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
418 int j, nr_ctxs = bnxt_rss_ctxts(bp);
420 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
421 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
422 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
424 "Only queues 0-%d will be in RSS table\n",
425 BNXT_RSS_TBL_SIZE_P5 - 1);
429 for (j = 0; j < nr_ctxs; j++) {
430 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
436 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
440 vnic->num_lb_ctxts = nr_ctxs;
444 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
445 * setting is not available at this time, it will not be
446 * configured correctly in the CFA.
448 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
449 vnic->vlan_strip = true;
451 vnic->vlan_strip = false;
453 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
457 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
461 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
462 rxq = bp->eth_dev->data->rx_queues[j];
465 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
466 j, rxq->vnic, rxq->vnic->fw_grp_ids);
468 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
469 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
471 vnic->rx_queue_cnt++;
474 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
476 rc = bnxt_vnic_rss_configure(bp, vnic);
480 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
482 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
483 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
485 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
489 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
494 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
498 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
499 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
504 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
505 " rx_fc_in_tbl.ctx_id = %d\n",
506 bp->flow_stat->rx_fc_in_tbl.va,
507 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
508 bp->flow_stat->rx_fc_in_tbl.ctx_id);
510 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
511 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
516 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
517 " rx_fc_out_tbl.ctx_id = %d\n",
518 bp->flow_stat->rx_fc_out_tbl.va,
519 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
520 bp->flow_stat->rx_fc_out_tbl.ctx_id);
522 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
523 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
528 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
529 " tx_fc_in_tbl.ctx_id = %d\n",
530 bp->flow_stat->tx_fc_in_tbl.va,
531 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
532 bp->flow_stat->tx_fc_in_tbl.ctx_id);
534 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
535 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
540 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
541 " tx_fc_out_tbl.ctx_id = %d\n",
542 bp->flow_stat->tx_fc_out_tbl.va,
543 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
544 bp->flow_stat->tx_fc_out_tbl.ctx_id);
546 memset(bp->flow_stat->rx_fc_out_tbl.va,
548 bp->flow_stat->rx_fc_out_tbl.size);
549 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
550 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
551 bp->flow_stat->rx_fc_out_tbl.ctx_id,
552 bp->flow_stat->max_fc,
557 memset(bp->flow_stat->tx_fc_out_tbl.va,
559 bp->flow_stat->tx_fc_out_tbl.size);
560 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
561 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
562 bp->flow_stat->tx_fc_out_tbl.ctx_id,
563 bp->flow_stat->max_fc,
569 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
570 struct bnxt_ctx_mem_buf_info *ctx)
575 ctx->va = rte_zmalloc(type, size, 0);
578 rte_mem_lock_page(ctx->va);
580 ctx->dma = rte_mem_virt2iova(ctx->va);
581 if (ctx->dma == RTE_BAD_IOVA)
587 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
589 struct rte_pci_device *pdev = bp->pdev;
590 char type[RTE_MEMZONE_NAMESIZE];
594 max_fc = bp->flow_stat->max_fc;
596 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
597 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
598 /* 4 bytes for each counter-id */
599 rc = bnxt_alloc_ctx_mem_buf(type,
601 &bp->flow_stat->rx_fc_in_tbl);
605 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
606 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
607 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
608 rc = bnxt_alloc_ctx_mem_buf(type,
610 &bp->flow_stat->rx_fc_out_tbl);
614 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
615 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
616 /* 4 bytes for each counter-id */
617 rc = bnxt_alloc_ctx_mem_buf(type,
619 &bp->flow_stat->tx_fc_in_tbl);
623 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
624 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
625 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
626 rc = bnxt_alloc_ctx_mem_buf(type,
628 &bp->flow_stat->tx_fc_out_tbl);
632 rc = bnxt_register_fc_ctx_mem(bp);
637 static int bnxt_init_ctx_mem(struct bnxt *bp)
641 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
642 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
643 !BNXT_FLOW_XSTATS_EN(bp))
646 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
650 rc = bnxt_init_fc_ctx_mem(bp);
655 static int bnxt_update_phy_setting(struct bnxt *bp)
657 struct rte_eth_link new;
660 rc = bnxt_get_hwrm_link_config(bp, &new);
662 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
667 * On BCM957508-N2100 adapters, FW will not allow any user other
668 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
669 * always returns link up. Force phy update always in that case.
671 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
672 rc = bnxt_set_hwrm_link_config(bp, true);
674 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
682 static int bnxt_init_chip(struct bnxt *bp)
684 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
685 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
686 uint32_t intr_vector = 0;
687 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
688 uint32_t vec = BNXT_MISC_VEC_ID;
692 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
693 bp->eth_dev->data->dev_conf.rxmode.offloads |=
694 DEV_RX_OFFLOAD_JUMBO_FRAME;
695 bp->flags |= BNXT_FLAG_JUMBO;
697 bp->eth_dev->data->dev_conf.rxmode.offloads &=
698 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
699 bp->flags &= ~BNXT_FLAG_JUMBO;
702 /* THOR does not support ring groups.
703 * But we will use the array to save RSS context IDs.
705 if (BNXT_CHIP_P5(bp))
706 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
708 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
710 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
714 rc = bnxt_alloc_hwrm_rings(bp);
716 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
720 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
722 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
726 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
729 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
730 if (bp->rx_cos_queue[i].id != 0xff) {
731 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
735 "Num pools more than FW profile\n");
739 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
745 rc = bnxt_mq_rx_configure(bp);
747 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
752 rc = bnxt_setup_one_vnic(bp, 0);
755 /* VNIC configuration */
756 if (BNXT_RFS_NEEDS_VNIC(bp)) {
757 for (i = 1; i < bp->nr_vnics; i++) {
758 rc = bnxt_setup_one_vnic(bp, i);
764 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
767 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
771 /* check and configure queue intr-vector mapping */
772 if ((rte_intr_cap_multiple(intr_handle) ||
773 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
774 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
775 intr_vector = bp->eth_dev->data->nb_rx_queues;
776 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
777 if (intr_vector > bp->rx_cp_nr_rings) {
778 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
782 rc = rte_intr_efd_enable(intr_handle, intr_vector);
787 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
788 intr_handle->intr_vec =
789 rte_zmalloc("intr_vec",
790 bp->eth_dev->data->nb_rx_queues *
792 if (intr_handle->intr_vec == NULL) {
793 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
794 " intr_vec", bp->eth_dev->data->nb_rx_queues);
798 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
799 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
800 intr_handle->intr_vec, intr_handle->nb_efd,
801 intr_handle->max_intr);
802 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
804 intr_handle->intr_vec[queue_id] =
805 vec + BNXT_RX_VEC_START;
806 if (vec < base + intr_handle->nb_efd - 1)
811 /* enable uio/vfio intr/eventfd mapping */
812 rc = rte_intr_enable(intr_handle);
813 #ifndef RTE_EXEC_ENV_FREEBSD
814 /* In FreeBSD OS, nic_uio driver does not support interrupts */
819 rc = bnxt_update_phy_setting(bp);
823 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
825 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
830 rte_free(intr_handle->intr_vec);
832 rte_intr_efd_disable(intr_handle);
834 /* Some of the error status returned by FW may not be from errno.h */
841 static int bnxt_shutdown_nic(struct bnxt *bp)
843 bnxt_free_all_hwrm_resources(bp);
844 bnxt_free_all_filters(bp);
845 bnxt_free_all_vnics(bp);
850 * Device configuration and status function
853 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
855 uint32_t link_speed = bp->link_info->support_speeds;
856 uint32_t speed_capa = 0;
858 /* If PAM4 is configured, use PAM4 supported speed */
859 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
860 link_speed = bp->link_info->support_pam4_speeds;
862 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
863 speed_capa |= ETH_LINK_SPEED_100M;
864 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
865 speed_capa |= ETH_LINK_SPEED_100M_HD;
866 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
867 speed_capa |= ETH_LINK_SPEED_1G;
868 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
869 speed_capa |= ETH_LINK_SPEED_2_5G;
870 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
871 speed_capa |= ETH_LINK_SPEED_10G;
872 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
873 speed_capa |= ETH_LINK_SPEED_20G;
874 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
875 speed_capa |= ETH_LINK_SPEED_25G;
876 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
877 speed_capa |= ETH_LINK_SPEED_40G;
878 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
879 speed_capa |= ETH_LINK_SPEED_50G;
880 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
881 speed_capa |= ETH_LINK_SPEED_100G;
882 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
883 speed_capa |= ETH_LINK_SPEED_50G;
884 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
885 speed_capa |= ETH_LINK_SPEED_100G;
886 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
887 speed_capa |= ETH_LINK_SPEED_200G;
889 if (bp->link_info->auto_mode ==
890 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
891 speed_capa |= ETH_LINK_SPEED_FIXED;
893 speed_capa |= ETH_LINK_SPEED_AUTONEG;
898 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
899 struct rte_eth_dev_info *dev_info)
901 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
902 struct bnxt *bp = eth_dev->data->dev_private;
903 uint16_t max_vnics, i, j, vpool, vrxq;
904 unsigned int max_rx_rings;
907 rc = is_bnxt_in_error(bp);
912 dev_info->max_mac_addrs = bp->max_l2_ctx;
913 dev_info->max_hash_mac_addrs = 0;
915 /* PF/VF specifics */
917 dev_info->max_vfs = pdev->max_vfs;
919 max_rx_rings = bnxt_max_rings(bp);
920 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
921 dev_info->max_rx_queues = max_rx_rings;
922 dev_info->max_tx_queues = max_rx_rings;
923 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
924 dev_info->hash_key_size = 40;
925 max_vnics = bp->max_vnics;
928 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
929 dev_info->max_mtu = BNXT_MAX_MTU;
931 /* Fast path specifics */
932 dev_info->min_rx_bufsize = 1;
933 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
935 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
936 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
937 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
938 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
939 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
940 dev_info->tx_queue_offload_capa;
941 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
943 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
946 dev_info->default_rxconf = (struct rte_eth_rxconf) {
952 .rx_free_thresh = 32,
953 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
956 dev_info->default_txconf = (struct rte_eth_txconf) {
962 .tx_free_thresh = 32,
965 eth_dev->data->dev_conf.intr_conf.lsc = 1;
967 eth_dev->data->dev_conf.intr_conf.rxq = 1;
968 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
969 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
970 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
971 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
973 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
974 dev_info->switch_info.name = eth_dev->device->name;
975 dev_info->switch_info.domain_id = bp->switch_domain_id;
976 dev_info->switch_info.port_id =
977 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
978 BNXT_SWITCH_PORT_ID_TRUSTED_VF;
984 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
985 * need further investigation.
989 vpool = 64; /* ETH_64_POOLS */
990 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
991 for (i = 0; i < 4; vpool >>= 1, i++) {
992 if (max_vnics > vpool) {
993 for (j = 0; j < 5; vrxq >>= 1, j++) {
994 if (dev_info->max_rx_queues > vrxq) {
1000 /* Not enough resources to support VMDq */
1004 /* Not enough resources to support VMDq */
1008 dev_info->max_vmdq_pools = vpool;
1009 dev_info->vmdq_queue_num = vrxq;
1011 dev_info->vmdq_pool_base = 0;
1012 dev_info->vmdq_queue_base = 0;
1017 /* Configure the device based on the configuration provided */
1018 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1020 struct bnxt *bp = eth_dev->data->dev_private;
1021 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1024 bp->rx_queues = (void *)eth_dev->data->rx_queues;
1025 bp->tx_queues = (void *)eth_dev->data->tx_queues;
1026 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1027 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1029 rc = is_bnxt_in_error(bp);
1033 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1034 rc = bnxt_hwrm_check_vf_rings(bp);
1036 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1040 /* If a resource has already been allocated - in this case
1041 * it is the async completion ring, free it. Reallocate it after
1042 * resource reservation. This will ensure the resource counts
1043 * are calculated correctly.
1046 pthread_mutex_lock(&bp->def_cp_lock);
1048 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1049 bnxt_disable_int(bp);
1050 bnxt_free_cp_ring(bp, bp->async_cp_ring);
1053 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1055 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1056 pthread_mutex_unlock(&bp->def_cp_lock);
1060 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1061 rc = bnxt_alloc_async_cp_ring(bp);
1063 pthread_mutex_unlock(&bp->def_cp_lock);
1066 bnxt_enable_int(bp);
1069 pthread_mutex_unlock(&bp->def_cp_lock);
1072 /* Inherit new configurations */
1073 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1074 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1075 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1076 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1077 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1079 goto resource_error;
1081 if (BNXT_HAS_RING_GRPS(bp) &&
1082 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1083 goto resource_error;
1085 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1086 bp->max_vnics < eth_dev->data->nb_rx_queues)
1087 goto resource_error;
1089 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1090 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1092 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1093 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1094 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1096 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1097 eth_dev->data->mtu =
1098 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1099 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1101 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1107 "Insufficient resources to support requested config\n");
1109 "Num Queues Requested: Tx %d, Rx %d\n",
1110 eth_dev->data->nb_tx_queues,
1111 eth_dev->data->nb_rx_queues);
1113 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1114 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1115 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1119 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1121 struct rte_eth_link *link = ð_dev->data->dev_link;
1123 if (link->link_status)
1124 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1125 eth_dev->data->port_id,
1126 (uint32_t)link->link_speed,
1127 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1128 ("full-duplex") : ("half-duplex\n"));
1130 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1131 eth_dev->data->port_id);
1135 * Determine whether the current configuration requires support for scattered
1136 * receive; return 1 if scattered receive is required and 0 if not.
1138 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1143 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1146 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1147 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1149 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1150 RTE_PKTMBUF_HEADROOM);
1151 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1157 static eth_rx_burst_t
1158 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1160 struct bnxt *bp = eth_dev->data->dev_private;
1162 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1163 #ifndef RTE_LIBRTE_IEEE1588
1165 * Vector mode receive can be enabled only if scatter rx is not
1166 * in use and rx offloads are limited to VLAN stripping and
1169 if (!eth_dev->data->scattered_rx &&
1170 !(eth_dev->data->dev_conf.rxmode.offloads &
1171 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1172 DEV_RX_OFFLOAD_KEEP_CRC |
1173 DEV_RX_OFFLOAD_JUMBO_FRAME |
1174 DEV_RX_OFFLOAD_IPV4_CKSUM |
1175 DEV_RX_OFFLOAD_UDP_CKSUM |
1176 DEV_RX_OFFLOAD_TCP_CKSUM |
1177 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1178 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1179 DEV_RX_OFFLOAD_RSS_HASH |
1180 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1181 !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) &&
1182 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1183 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1184 eth_dev->data->port_id);
1185 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1186 return bnxt_recv_pkts_vec;
1188 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1189 eth_dev->data->port_id);
1191 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1192 eth_dev->data->port_id,
1193 eth_dev->data->scattered_rx,
1194 eth_dev->data->dev_conf.rxmode.offloads);
1197 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1198 return bnxt_recv_pkts;
1201 static eth_tx_burst_t
1202 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
1204 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1205 #ifndef RTE_LIBRTE_IEEE1588
1206 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1207 struct bnxt *bp = eth_dev->data->dev_private;
1210 * Vector mode transmit can be enabled only if not using scatter rx
1213 if (!eth_dev->data->scattered_rx &&
1214 !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1215 !BNXT_TRUFLOW_EN(bp) &&
1216 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1217 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1218 eth_dev->data->port_id);
1219 return bnxt_xmit_pkts_vec;
1221 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1222 eth_dev->data->port_id);
1224 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1225 eth_dev->data->port_id,
1226 eth_dev->data->scattered_rx,
1230 return bnxt_xmit_pkts;
1233 static int bnxt_handle_if_change_status(struct bnxt *bp)
1237 /* Since fw has undergone a reset and lost all contexts,
1238 * set fatal flag to not issue hwrm during cleanup
1240 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1241 bnxt_uninit_resources(bp, true);
1243 /* clear fatal flag so that re-init happens */
1244 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1245 rc = bnxt_init_resources(bp, true);
1247 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1252 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1254 struct bnxt *bp = eth_dev->data->dev_private;
1255 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1257 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1259 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1260 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1264 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1266 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1267 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1270 rc = bnxt_hwrm_if_change(bp, true);
1271 if (rc == 0 || rc != -EAGAIN)
1274 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1275 } while (retry_cnt--);
1280 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1281 rc = bnxt_handle_if_change_status(bp);
1286 bnxt_enable_int(bp);
1288 rc = bnxt_init_chip(bp);
1292 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1293 eth_dev->data->dev_started = 1;
1295 bnxt_link_update_op(eth_dev, 1);
1297 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1298 vlan_mask |= ETH_VLAN_FILTER_MASK;
1299 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1300 vlan_mask |= ETH_VLAN_STRIP_MASK;
1301 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1305 /* Initialize bnxt ULP port details */
1306 rc = bnxt_ulp_port_init(bp);
1310 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1311 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1313 bnxt_schedule_fw_health_check(bp);
1318 bnxt_shutdown_nic(bp);
1319 bnxt_free_tx_mbufs(bp);
1320 bnxt_free_rx_mbufs(bp);
1321 bnxt_hwrm_if_change(bp, false);
1322 eth_dev->data->dev_started = 0;
1326 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1328 struct bnxt *bp = eth_dev->data->dev_private;
1331 if (!bp->link_info->link_up)
1332 rc = bnxt_set_hwrm_link_config(bp, true);
1334 eth_dev->data->dev_link.link_status = 1;
1336 bnxt_print_link_info(eth_dev);
1340 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1342 struct bnxt *bp = eth_dev->data->dev_private;
1344 eth_dev->data->dev_link.link_status = 0;
1345 bnxt_set_hwrm_link_config(bp, false);
1346 bp->link_info->link_up = 0;
1351 static void bnxt_free_switch_domain(struct bnxt *bp)
1355 if (bp->switch_domain_id) {
1356 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1358 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1359 bp->switch_domain_id, rc);
1363 /* Unload the driver, release resources */
1364 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1366 struct bnxt *bp = eth_dev->data->dev_private;
1367 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1368 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1369 struct rte_eth_link link;
1372 eth_dev->data->dev_started = 0;
1373 eth_dev->data->scattered_rx = 0;
1375 /* Prevent crashes when queues are still in use */
1376 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1377 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1379 bnxt_disable_int(bp);
1381 /* disable uio/vfio intr/eventfd mapping */
1382 rte_intr_disable(intr_handle);
1384 /* Stop the child representors for this device */
1385 ret = bnxt_rep_stop_all(bp);
1389 /* delete the bnxt ULP port details */
1390 bnxt_ulp_port_deinit(bp);
1392 bnxt_cancel_fw_health_check(bp);
1394 /* Do not bring link down during reset recovery */
1395 if (!is_bnxt_in_error(bp)) {
1396 bnxt_dev_set_link_down_op(eth_dev);
1397 /* Wait for link to be reset */
1398 if (BNXT_SINGLE_PF(bp))
1400 /* clear the recorded link status */
1401 memset(&link, 0, sizeof(link));
1402 rte_eth_linkstatus_set(eth_dev, &link);
1405 /* Clean queue intr-vector mapping */
1406 rte_intr_efd_disable(intr_handle);
1407 if (intr_handle->intr_vec != NULL) {
1408 rte_free(intr_handle->intr_vec);
1409 intr_handle->intr_vec = NULL;
1412 bnxt_hwrm_port_clr_stats(bp);
1413 bnxt_free_tx_mbufs(bp);
1414 bnxt_free_rx_mbufs(bp);
1415 /* Process any remaining notifications in default completion queue */
1416 bnxt_int_handler(eth_dev);
1417 bnxt_shutdown_nic(bp);
1418 bnxt_hwrm_if_change(bp, false);
1420 rte_free(bp->mark_table);
1421 bp->mark_table = NULL;
1423 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1424 bp->rx_cosq_cnt = 0;
1425 /* All filters are deleted on a port stop. */
1426 if (BNXT_FLOW_XSTATS_EN(bp))
1427 bp->flow_stat->flow_count = 0;
1432 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1434 struct bnxt *bp = eth_dev->data->dev_private;
1437 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1440 /* cancel the recovery handler before remove dev */
1441 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1442 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1443 bnxt_cancel_fc_thread(bp);
1445 if (eth_dev->data->dev_started)
1446 ret = bnxt_dev_stop_op(eth_dev);
1448 bnxt_free_switch_domain(bp);
1450 bnxt_uninit_resources(bp, false);
1452 bnxt_free_leds_info(bp);
1453 bnxt_free_cos_queues(bp);
1454 bnxt_free_link_info(bp);
1455 bnxt_free_pf_info(bp);
1456 bnxt_free_parent_info(bp);
1458 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1459 bp->tx_mem_zone = NULL;
1460 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1461 bp->rx_mem_zone = NULL;
1463 bnxt_hwrm_free_vf_info(bp);
1465 rte_free(bp->grp_info);
1466 bp->grp_info = NULL;
1471 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1474 struct bnxt *bp = eth_dev->data->dev_private;
1475 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1476 struct bnxt_vnic_info *vnic;
1477 struct bnxt_filter_info *filter, *temp_filter;
1480 if (is_bnxt_in_error(bp))
1484 * Loop through all VNICs from the specified filter flow pools to
1485 * remove the corresponding MAC addr filter
1487 for (i = 0; i < bp->nr_vnics; i++) {
1488 if (!(pool_mask & (1ULL << i)))
1491 vnic = &bp->vnic_info[i];
1492 filter = STAILQ_FIRST(&vnic->filter);
1494 temp_filter = STAILQ_NEXT(filter, next);
1495 if (filter->mac_index == index) {
1496 STAILQ_REMOVE(&vnic->filter, filter,
1497 bnxt_filter_info, next);
1498 bnxt_hwrm_clear_l2_filter(bp, filter);
1499 bnxt_free_filter(bp, filter);
1501 filter = temp_filter;
1506 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1507 struct rte_ether_addr *mac_addr, uint32_t index,
1510 struct bnxt_filter_info *filter;
1513 /* Attach requested MAC address to the new l2_filter */
1514 STAILQ_FOREACH(filter, &vnic->filter, next) {
1515 if (filter->mac_index == index) {
1517 "MAC addr already existed for pool %d\n",
1523 filter = bnxt_alloc_filter(bp);
1525 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1529 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1530 * if the MAC that's been programmed now is a different one, then,
1531 * copy that addr to filter->l2_addr
1534 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1535 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1537 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1539 filter->mac_index = index;
1540 if (filter->mac_index == 0)
1541 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1543 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1545 bnxt_free_filter(bp, filter);
1551 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1552 struct rte_ether_addr *mac_addr,
1553 uint32_t index, uint32_t pool)
1555 struct bnxt *bp = eth_dev->data->dev_private;
1556 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1559 rc = is_bnxt_in_error(bp);
1563 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1564 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1569 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1573 /* Filter settings will get applied when port is started */
1574 if (!eth_dev->data->dev_started)
1577 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1582 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1585 struct bnxt *bp = eth_dev->data->dev_private;
1586 struct rte_eth_link new;
1587 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1588 BNXT_MIN_LINK_WAIT_CNT;
1590 rc = is_bnxt_in_error(bp);
1594 memset(&new, 0, sizeof(new));
1596 /* Retrieve link info from hardware */
1597 rc = bnxt_get_hwrm_link_config(bp, &new);
1599 new.link_speed = ETH_LINK_SPEED_100M;
1600 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1602 "Failed to retrieve link rc = 0x%x!\n", rc);
1606 if (!wait_to_complete || new.link_status)
1609 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1612 /* Only single function PF can bring phy down.
1613 * When port is stopped, report link down for VF/MH/NPAR functions.
1615 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1616 memset(&new, 0, sizeof(new));
1619 /* Timed out or success */
1620 if (new.link_status != eth_dev->data->dev_link.link_status ||
1621 new.link_speed != eth_dev->data->dev_link.link_speed) {
1622 rte_eth_linkstatus_set(eth_dev, &new);
1624 rte_eth_dev_callback_process(eth_dev,
1625 RTE_ETH_EVENT_INTR_LSC,
1628 bnxt_print_link_info(eth_dev);
1634 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1636 struct bnxt *bp = eth_dev->data->dev_private;
1637 struct bnxt_vnic_info *vnic;
1641 rc = is_bnxt_in_error(bp);
1645 /* Filter settings will get applied when port is started */
1646 if (!eth_dev->data->dev_started)
1649 if (bp->vnic_info == NULL)
1652 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1654 old_flags = vnic->flags;
1655 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1656 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1658 vnic->flags = old_flags;
1663 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1665 struct bnxt *bp = eth_dev->data->dev_private;
1666 struct bnxt_vnic_info *vnic;
1670 rc = is_bnxt_in_error(bp);
1674 /* Filter settings will get applied when port is started */
1675 if (!eth_dev->data->dev_started)
1678 if (bp->vnic_info == NULL)
1681 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1683 old_flags = vnic->flags;
1684 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1685 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1687 vnic->flags = old_flags;
1692 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1694 struct bnxt *bp = eth_dev->data->dev_private;
1695 struct bnxt_vnic_info *vnic;
1699 rc = is_bnxt_in_error(bp);
1703 /* Filter settings will get applied when port is started */
1704 if (!eth_dev->data->dev_started)
1707 if (bp->vnic_info == NULL)
1710 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1712 old_flags = vnic->flags;
1713 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1714 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1716 vnic->flags = old_flags;
1721 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1723 struct bnxt *bp = eth_dev->data->dev_private;
1724 struct bnxt_vnic_info *vnic;
1728 rc = is_bnxt_in_error(bp);
1732 /* Filter settings will get applied when port is started */
1733 if (!eth_dev->data->dev_started)
1736 if (bp->vnic_info == NULL)
1739 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1741 old_flags = vnic->flags;
1742 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1743 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1745 vnic->flags = old_flags;
1750 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1751 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1753 if (qid >= bp->rx_nr_rings)
1756 return bp->eth_dev->data->rx_queues[qid];
1759 /* Return rxq corresponding to a given rss table ring/group ID. */
1760 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1762 struct bnxt_rx_queue *rxq;
1765 if (!BNXT_HAS_RING_GRPS(bp)) {
1766 for (i = 0; i < bp->rx_nr_rings; i++) {
1767 rxq = bp->eth_dev->data->rx_queues[i];
1768 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1772 for (i = 0; i < bp->rx_nr_rings; i++) {
1773 if (bp->grp_info[i].fw_grp_id == fwr)
1778 return INVALID_HW_RING_ID;
1781 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1782 struct rte_eth_rss_reta_entry64 *reta_conf,
1785 struct bnxt *bp = eth_dev->data->dev_private;
1786 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1787 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1788 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1792 rc = is_bnxt_in_error(bp);
1796 if (!vnic->rss_table)
1799 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1802 if (reta_size != tbl_size) {
1803 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1804 "(%d) must equal the size supported by the hardware "
1805 "(%d)\n", reta_size, tbl_size);
1809 for (i = 0; i < reta_size; i++) {
1810 struct bnxt_rx_queue *rxq;
1812 idx = i / RTE_RETA_GROUP_SIZE;
1813 sft = i % RTE_RETA_GROUP_SIZE;
1815 if (!(reta_conf[idx].mask & (1ULL << sft)))
1818 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1820 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1824 if (BNXT_CHIP_P5(bp)) {
1825 vnic->rss_table[i * 2] =
1826 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1827 vnic->rss_table[i * 2 + 1] =
1828 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1830 vnic->rss_table[i] =
1831 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1835 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1839 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1840 struct rte_eth_rss_reta_entry64 *reta_conf,
1843 struct bnxt *bp = eth_dev->data->dev_private;
1844 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1845 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1846 uint16_t idx, sft, i;
1849 rc = is_bnxt_in_error(bp);
1853 /* Retrieve from the default VNIC */
1856 if (!vnic->rss_table)
1859 if (reta_size != tbl_size) {
1860 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1861 "(%d) must equal the size supported by the hardware "
1862 "(%d)\n", reta_size, tbl_size);
1866 for (idx = 0, i = 0; i < reta_size; i++) {
1867 idx = i / RTE_RETA_GROUP_SIZE;
1868 sft = i % RTE_RETA_GROUP_SIZE;
1870 if (reta_conf[idx].mask & (1ULL << sft)) {
1873 if (BNXT_CHIP_P5(bp))
1874 qid = bnxt_rss_to_qid(bp,
1875 vnic->rss_table[i * 2]);
1877 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1879 if (qid == INVALID_HW_RING_ID) {
1880 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1883 reta_conf[idx].reta[sft] = qid;
1890 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1891 struct rte_eth_rss_conf *rss_conf)
1893 struct bnxt *bp = eth_dev->data->dev_private;
1894 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1895 struct bnxt_vnic_info *vnic;
1898 rc = is_bnxt_in_error(bp);
1903 * If RSS enablement were different than dev_configure,
1904 * then return -EINVAL
1906 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1907 if (!rss_conf->rss_hf)
1908 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1910 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1914 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1915 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
1919 /* Update the default RSS VNIC(s) */
1920 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1921 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1923 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
1924 ETH_RSS_LEVEL(rss_conf->rss_hf));
1927 * If hashkey is not specified, use the previously configured
1930 if (!rss_conf->rss_key)
1933 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1935 "Invalid hashkey length, should be 16 bytes\n");
1938 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1941 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1945 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1946 struct rte_eth_rss_conf *rss_conf)
1948 struct bnxt *bp = eth_dev->data->dev_private;
1949 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1951 uint32_t hash_types;
1953 rc = is_bnxt_in_error(bp);
1957 /* RSS configuration is the same for all VNICs */
1958 if (vnic && vnic->rss_hash_key) {
1959 if (rss_conf->rss_key) {
1960 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1961 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1962 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1965 hash_types = vnic->hash_type;
1966 rss_conf->rss_hf = 0;
1967 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1968 rss_conf->rss_hf |= ETH_RSS_IPV4;
1969 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1971 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1972 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1974 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1976 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1977 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1979 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1981 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1982 rss_conf->rss_hf |= ETH_RSS_IPV6;
1983 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1985 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1986 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1988 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1990 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1991 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1993 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1997 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2001 "Unknown RSS config from firmware (%08x), RSS disabled",
2006 rss_conf->rss_hf = 0;
2011 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2012 struct rte_eth_fc_conf *fc_conf)
2014 struct bnxt *bp = dev->data->dev_private;
2015 struct rte_eth_link link_info;
2018 rc = is_bnxt_in_error(bp);
2022 rc = bnxt_get_hwrm_link_config(bp, &link_info);
2026 memset(fc_conf, 0, sizeof(*fc_conf));
2027 if (bp->link_info->auto_pause)
2028 fc_conf->autoneg = 1;
2029 switch (bp->link_info->pause) {
2031 fc_conf->mode = RTE_FC_NONE;
2033 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2034 fc_conf->mode = RTE_FC_TX_PAUSE;
2036 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2037 fc_conf->mode = RTE_FC_RX_PAUSE;
2039 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2040 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2041 fc_conf->mode = RTE_FC_FULL;
2047 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2048 struct rte_eth_fc_conf *fc_conf)
2050 struct bnxt *bp = dev->data->dev_private;
2053 rc = is_bnxt_in_error(bp);
2057 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2058 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2062 switch (fc_conf->mode) {
2064 bp->link_info->auto_pause = 0;
2065 bp->link_info->force_pause = 0;
2067 case RTE_FC_RX_PAUSE:
2068 if (fc_conf->autoneg) {
2069 bp->link_info->auto_pause =
2070 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2071 bp->link_info->force_pause = 0;
2073 bp->link_info->auto_pause = 0;
2074 bp->link_info->force_pause =
2075 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2078 case RTE_FC_TX_PAUSE:
2079 if (fc_conf->autoneg) {
2080 bp->link_info->auto_pause =
2081 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2082 bp->link_info->force_pause = 0;
2084 bp->link_info->auto_pause = 0;
2085 bp->link_info->force_pause =
2086 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2090 if (fc_conf->autoneg) {
2091 bp->link_info->auto_pause =
2092 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2093 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2094 bp->link_info->force_pause = 0;
2096 bp->link_info->auto_pause = 0;
2097 bp->link_info->force_pause =
2098 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2099 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2103 return bnxt_set_hwrm_link_config(bp, true);
2106 /* Add UDP tunneling port */
2108 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2109 struct rte_eth_udp_tunnel *udp_tunnel)
2111 struct bnxt *bp = eth_dev->data->dev_private;
2112 uint16_t tunnel_type = 0;
2115 rc = is_bnxt_in_error(bp);
2119 switch (udp_tunnel->prot_type) {
2120 case RTE_TUNNEL_TYPE_VXLAN:
2121 if (bp->vxlan_port_cnt) {
2122 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2123 udp_tunnel->udp_port);
2124 if (bp->vxlan_port != udp_tunnel->udp_port) {
2125 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2128 bp->vxlan_port_cnt++;
2132 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2133 bp->vxlan_port_cnt++;
2135 case RTE_TUNNEL_TYPE_GENEVE:
2136 if (bp->geneve_port_cnt) {
2137 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2138 udp_tunnel->udp_port);
2139 if (bp->geneve_port != udp_tunnel->udp_port) {
2140 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2143 bp->geneve_port_cnt++;
2147 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2148 bp->geneve_port_cnt++;
2151 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2154 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2160 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2161 struct rte_eth_udp_tunnel *udp_tunnel)
2163 struct bnxt *bp = eth_dev->data->dev_private;
2164 uint16_t tunnel_type = 0;
2168 rc = is_bnxt_in_error(bp);
2172 switch (udp_tunnel->prot_type) {
2173 case RTE_TUNNEL_TYPE_VXLAN:
2174 if (!bp->vxlan_port_cnt) {
2175 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2178 if (bp->vxlan_port != udp_tunnel->udp_port) {
2179 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2180 udp_tunnel->udp_port, bp->vxlan_port);
2183 if (--bp->vxlan_port_cnt)
2187 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2188 port = bp->vxlan_fw_dst_port_id;
2190 case RTE_TUNNEL_TYPE_GENEVE:
2191 if (!bp->geneve_port_cnt) {
2192 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2195 if (bp->geneve_port != udp_tunnel->udp_port) {
2196 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2197 udp_tunnel->udp_port, bp->geneve_port);
2200 if (--bp->geneve_port_cnt)
2204 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2205 port = bp->geneve_fw_dst_port_id;
2208 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2212 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2216 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2218 struct bnxt_filter_info *filter;
2219 struct bnxt_vnic_info *vnic;
2221 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2223 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2224 filter = STAILQ_FIRST(&vnic->filter);
2226 /* Search for this matching MAC+VLAN filter */
2227 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2228 /* Delete the filter */
2229 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2232 STAILQ_REMOVE(&vnic->filter, filter,
2233 bnxt_filter_info, next);
2234 bnxt_free_filter(bp, filter);
2236 "Deleted vlan filter for %d\n",
2240 filter = STAILQ_NEXT(filter, next);
2245 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2247 struct bnxt_filter_info *filter;
2248 struct bnxt_vnic_info *vnic;
2250 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2251 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2252 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2254 /* Implementation notes on the use of VNIC in this command:
2256 * By default, these filters belong to default vnic for the function.
2257 * Once these filters are set up, only destination VNIC can be modified.
2258 * If the destination VNIC is not specified in this command,
2259 * then the HWRM shall only create an l2 context id.
2262 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2263 filter = STAILQ_FIRST(&vnic->filter);
2264 /* Check if the VLAN has already been added */
2266 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2269 filter = STAILQ_NEXT(filter, next);
2272 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2273 * command to create MAC+VLAN filter with the right flags, enables set.
2275 filter = bnxt_alloc_filter(bp);
2278 "MAC/VLAN filter alloc failed\n");
2281 /* MAC + VLAN ID filter */
2282 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2283 * untagged packets are received
2285 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2286 * packets and only the programmed vlan's packets are received
2288 filter->l2_ivlan = vlan_id;
2289 filter->l2_ivlan_mask = 0x0FFF;
2290 filter->enables |= en;
2291 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2293 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2295 /* Free the newly allocated filter as we were
2296 * not able to create the filter in hardware.
2298 bnxt_free_filter(bp, filter);
2302 filter->mac_index = 0;
2303 /* Add this new filter to the list */
2305 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2307 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2310 "Added Vlan filter for %d\n", vlan_id);
2314 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2315 uint16_t vlan_id, int on)
2317 struct bnxt *bp = eth_dev->data->dev_private;
2320 rc = is_bnxt_in_error(bp);
2324 if (!eth_dev->data->dev_started) {
2325 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2329 /* These operations apply to ALL existing MAC/VLAN filters */
2331 return bnxt_add_vlan_filter(bp, vlan_id);
2333 return bnxt_del_vlan_filter(bp, vlan_id);
2336 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2337 struct bnxt_vnic_info *vnic)
2339 struct bnxt_filter_info *filter;
2342 filter = STAILQ_FIRST(&vnic->filter);
2344 if (filter->mac_index == 0 &&
2345 !memcmp(filter->l2_addr, bp->mac_addr,
2346 RTE_ETHER_ADDR_LEN)) {
2347 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2349 STAILQ_REMOVE(&vnic->filter, filter,
2350 bnxt_filter_info, next);
2351 bnxt_free_filter(bp, filter);
2355 filter = STAILQ_NEXT(filter, next);
2361 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2363 struct bnxt_vnic_info *vnic;
2367 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2368 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2369 /* Remove any VLAN filters programmed */
2370 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2371 bnxt_del_vlan_filter(bp, i);
2373 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2377 /* Default filter will allow packets that match the
2378 * dest mac. So, it has to be deleted, otherwise, we
2379 * will endup receiving vlan packets for which the
2380 * filter is not programmed, when hw-vlan-filter
2381 * configuration is ON
2383 bnxt_del_dflt_mac_filter(bp, vnic);
2384 /* This filter will allow only untagged packets */
2385 bnxt_add_vlan_filter(bp, 0);
2387 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2388 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2393 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2395 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2399 /* Destroy vnic filters and vnic */
2400 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2401 DEV_RX_OFFLOAD_VLAN_FILTER) {
2402 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2403 bnxt_del_vlan_filter(bp, i);
2405 bnxt_del_dflt_mac_filter(bp, vnic);
2407 rc = bnxt_hwrm_vnic_free(bp, vnic);
2411 rte_free(vnic->fw_grp_ids);
2412 vnic->fw_grp_ids = NULL;
2414 vnic->rx_queue_cnt = 0;
2420 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2422 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2425 /* Destroy, recreate and reconfigure the default vnic */
2426 rc = bnxt_free_one_vnic(bp, 0);
2430 /* default vnic 0 */
2431 rc = bnxt_setup_one_vnic(bp, 0);
2435 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2436 DEV_RX_OFFLOAD_VLAN_FILTER) {
2437 rc = bnxt_add_vlan_filter(bp, 0);
2440 rc = bnxt_restore_vlan_filters(bp);
2444 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2449 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2453 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2454 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2460 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2462 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2463 struct bnxt *bp = dev->data->dev_private;
2466 rc = is_bnxt_in_error(bp);
2470 /* Filter settings will get applied when port is started */
2471 if (!dev->data->dev_started)
2474 if (mask & ETH_VLAN_FILTER_MASK) {
2475 /* Enable or disable VLAN filtering */
2476 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2481 if (mask & ETH_VLAN_STRIP_MASK) {
2482 /* Enable or disable VLAN stripping */
2483 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2488 if (mask & ETH_VLAN_EXTEND_MASK) {
2489 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2490 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2492 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2499 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2502 struct bnxt *bp = dev->data->dev_private;
2503 int qinq = dev->data->dev_conf.rxmode.offloads &
2504 DEV_RX_OFFLOAD_VLAN_EXTEND;
2506 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2507 vlan_type != ETH_VLAN_TYPE_OUTER) {
2509 "Unsupported vlan type.");
2514 "QinQ not enabled. Needs to be ON as we can "
2515 "accelerate only outer vlan\n");
2519 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2521 case RTE_ETHER_TYPE_QINQ:
2523 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2525 case RTE_ETHER_TYPE_VLAN:
2527 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2529 case RTE_ETHER_TYPE_QINQ1:
2531 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2533 case RTE_ETHER_TYPE_QINQ2:
2535 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2537 case RTE_ETHER_TYPE_QINQ3:
2539 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2542 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2545 bp->outer_tpid_bd |= tpid;
2546 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2547 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2549 "Can accelerate only outer vlan in QinQ\n");
2557 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2558 struct rte_ether_addr *addr)
2560 struct bnxt *bp = dev->data->dev_private;
2561 /* Default Filter is tied to VNIC 0 */
2562 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2565 rc = is_bnxt_in_error(bp);
2569 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2572 if (rte_is_zero_ether_addr(addr))
2575 /* Filter settings will get applied when port is started */
2576 if (!dev->data->dev_started)
2579 /* Check if the requested MAC is already added */
2580 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2583 /* Destroy filter and re-create it */
2584 bnxt_del_dflt_mac_filter(bp, vnic);
2586 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2587 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2588 /* This filter will allow only untagged packets */
2589 rc = bnxt_add_vlan_filter(bp, 0);
2591 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2594 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2599 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2600 struct rte_ether_addr *mc_addr_set,
2601 uint32_t nb_mc_addr)
2603 struct bnxt *bp = eth_dev->data->dev_private;
2604 char *mc_addr_list = (char *)mc_addr_set;
2605 struct bnxt_vnic_info *vnic;
2606 uint32_t off = 0, i = 0;
2609 rc = is_bnxt_in_error(bp);
2613 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2615 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2616 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2620 /* TODO Check for Duplicate mcast addresses */
2621 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2622 for (i = 0; i < nb_mc_addr; i++) {
2623 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2624 RTE_ETHER_ADDR_LEN);
2625 off += RTE_ETHER_ADDR_LEN;
2628 vnic->mc_addr_cnt = i;
2629 if (vnic->mc_addr_cnt)
2630 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2632 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2635 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2639 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2641 struct bnxt *bp = dev->data->dev_private;
2642 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2643 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2644 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2645 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2648 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2649 fw_major, fw_minor, fw_updt, fw_rsvd);
2651 ret += 1; /* add the size of '\0' */
2652 if (fw_size < (uint32_t)ret)
2659 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2660 struct rte_eth_rxq_info *qinfo)
2662 struct bnxt *bp = dev->data->dev_private;
2663 struct bnxt_rx_queue *rxq;
2665 if (is_bnxt_in_error(bp))
2668 rxq = dev->data->rx_queues[queue_id];
2670 qinfo->mp = rxq->mb_pool;
2671 qinfo->scattered_rx = dev->data->scattered_rx;
2672 qinfo->nb_desc = rxq->nb_rx_desc;
2674 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2675 qinfo->conf.rx_drop_en = rxq->drop_en;
2676 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2677 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2681 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2682 struct rte_eth_txq_info *qinfo)
2684 struct bnxt *bp = dev->data->dev_private;
2685 struct bnxt_tx_queue *txq;
2687 if (is_bnxt_in_error(bp))
2690 txq = dev->data->tx_queues[queue_id];
2692 qinfo->nb_desc = txq->nb_tx_desc;
2694 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2695 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2696 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2698 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2699 qinfo->conf.tx_rs_thresh = 0;
2700 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2701 qinfo->conf.offloads = txq->offloads;
2704 static const struct {
2705 eth_rx_burst_t pkt_burst;
2707 } bnxt_rx_burst_info[] = {
2708 {bnxt_recv_pkts, "Scalar"},
2709 #if defined(RTE_ARCH_X86)
2710 {bnxt_recv_pkts_vec, "Vector SSE"},
2711 #elif defined(RTE_ARCH_ARM64)
2712 {bnxt_recv_pkts_vec, "Vector Neon"},
2717 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2718 struct rte_eth_burst_mode *mode)
2720 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2723 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2724 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2725 snprintf(mode->info, sizeof(mode->info), "%s",
2726 bnxt_rx_burst_info[i].info);
2734 static const struct {
2735 eth_tx_burst_t pkt_burst;
2737 } bnxt_tx_burst_info[] = {
2738 {bnxt_xmit_pkts, "Scalar"},
2739 #if defined(RTE_ARCH_X86)
2740 {bnxt_xmit_pkts_vec, "Vector SSE"},
2741 #elif defined(RTE_ARCH_ARM64)
2742 {bnxt_xmit_pkts_vec, "Vector Neon"},
2747 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2748 struct rte_eth_burst_mode *mode)
2750 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2753 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2754 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2755 snprintf(mode->info, sizeof(mode->info), "%s",
2756 bnxt_tx_burst_info[i].info);
2764 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2766 struct bnxt *bp = eth_dev->data->dev_private;
2767 uint32_t new_pkt_size;
2771 rc = is_bnxt_in_error(bp);
2775 /* Exit if receive queues are not configured yet */
2776 if (!eth_dev->data->nb_rx_queues)
2779 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2780 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2783 * Disallow any MTU change that would require scattered receive support
2784 * if it is not already enabled.
2786 if (eth_dev->data->dev_started &&
2787 !eth_dev->data->scattered_rx &&
2789 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2791 "MTU change would require scattered rx support. ");
2792 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2796 if (new_mtu > RTE_ETHER_MTU) {
2797 bp->flags |= BNXT_FLAG_JUMBO;
2798 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2799 DEV_RX_OFFLOAD_JUMBO_FRAME;
2801 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2802 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2803 bp->flags &= ~BNXT_FLAG_JUMBO;
2806 /* Is there a change in mtu setting? */
2807 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2810 for (i = 0; i < bp->nr_vnics; i++) {
2811 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2814 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2815 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2819 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2820 size -= RTE_PKTMBUF_HEADROOM;
2822 if (size < new_mtu) {
2823 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2830 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2832 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2838 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2840 struct bnxt *bp = dev->data->dev_private;
2841 uint16_t vlan = bp->vlan;
2844 rc = is_bnxt_in_error(bp);
2848 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2850 "PVID cannot be modified for this function\n");
2853 bp->vlan = on ? pvid : 0;
2855 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2862 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2864 struct bnxt *bp = dev->data->dev_private;
2867 rc = is_bnxt_in_error(bp);
2871 return bnxt_hwrm_port_led_cfg(bp, true);
2875 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2877 struct bnxt *bp = dev->data->dev_private;
2880 rc = is_bnxt_in_error(bp);
2884 return bnxt_hwrm_port_led_cfg(bp, false);
2888 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2890 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2891 uint32_t desc = 0, raw_cons = 0, cons;
2892 struct bnxt_cp_ring_info *cpr;
2893 struct bnxt_rx_queue *rxq;
2894 struct rx_pkt_cmpl *rxcmp;
2897 rc = is_bnxt_in_error(bp);
2901 rxq = dev->data->rx_queues[rx_queue_id];
2903 raw_cons = cpr->cp_raw_cons;
2906 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2907 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2908 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2910 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2922 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2924 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2925 struct bnxt_rx_ring_info *rxr;
2926 struct bnxt_cp_ring_info *cpr;
2927 struct rte_mbuf *rx_buf;
2928 struct rx_pkt_cmpl *rxcmp;
2929 uint32_t cons, cp_cons;
2935 rc = is_bnxt_in_error(rxq->bp);
2942 if (offset >= rxq->nb_rx_desc)
2945 cons = RING_CMP(cpr->cp_ring_struct, offset);
2946 cp_cons = cpr->cp_raw_cons;
2947 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2949 if (cons > cp_cons) {
2950 if (CMPL_VALID(rxcmp, cpr->valid))
2951 return RTE_ETH_RX_DESC_DONE;
2953 if (CMPL_VALID(rxcmp, !cpr->valid))
2954 return RTE_ETH_RX_DESC_DONE;
2956 rx_buf = rxr->rx_buf_ring[cons];
2957 if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
2958 return RTE_ETH_RX_DESC_UNAVAIL;
2961 return RTE_ETH_RX_DESC_AVAIL;
2965 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2967 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2968 struct bnxt_tx_ring_info *txr;
2969 struct bnxt_cp_ring_info *cpr;
2970 struct bnxt_sw_tx_bd *tx_buf;
2971 struct tx_pkt_cmpl *txcmp;
2972 uint32_t cons, cp_cons;
2978 rc = is_bnxt_in_error(txq->bp);
2985 if (offset >= txq->nb_tx_desc)
2988 cons = RING_CMP(cpr->cp_ring_struct, offset);
2989 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2990 cp_cons = cpr->cp_raw_cons;
2992 if (cons > cp_cons) {
2993 if (CMPL_VALID(txcmp, cpr->valid))
2994 return RTE_ETH_TX_DESC_UNAVAIL;
2996 if (CMPL_VALID(txcmp, !cpr->valid))
2997 return RTE_ETH_TX_DESC_UNAVAIL;
2999 tx_buf = &txr->tx_buf_ring[cons];
3000 if (tx_buf->mbuf == NULL)
3001 return RTE_ETH_TX_DESC_DONE;
3003 return RTE_ETH_TX_DESC_FULL;
3007 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3008 enum rte_filter_type filter_type,
3009 enum rte_filter_op filter_op, void *arg)
3011 struct bnxt *bp = dev->data->dev_private;
3017 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3018 struct bnxt_representor *vfr = dev->data->dev_private;
3019 bp = vfr->parent_dev->data->dev_private;
3020 /* parent is deleted while children are still valid */
3022 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3030 ret = is_bnxt_in_error(bp);
3034 switch (filter_type) {
3035 case RTE_ETH_FILTER_GENERIC:
3036 if (filter_op != RTE_ETH_FILTER_GET)
3039 /* PMD supports thread-safe flow operations. rte_flow API
3040 * functions can avoid mutex for multi-thread safety.
3042 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3044 if (BNXT_TRUFLOW_EN(bp))
3045 *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3047 *(const void **)arg = &bnxt_flow_ops;
3051 "Filter type (%d) not supported", filter_type);
3058 static const uint32_t *
3059 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3061 static const uint32_t ptypes[] = {
3062 RTE_PTYPE_L2_ETHER_VLAN,
3063 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3064 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3068 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3069 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3070 RTE_PTYPE_INNER_L4_ICMP,
3071 RTE_PTYPE_INNER_L4_TCP,
3072 RTE_PTYPE_INNER_L4_UDP,
3076 if (!dev->rx_pkt_burst)
3082 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3085 uint32_t reg_base = *reg_arr & 0xfffff000;
3089 for (i = 0; i < count; i++) {
3090 if ((reg_arr[i] & 0xfffff000) != reg_base)
3093 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3094 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3098 static int bnxt_map_ptp_regs(struct bnxt *bp)
3100 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3104 reg_arr = ptp->rx_regs;
3105 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3109 reg_arr = ptp->tx_regs;
3110 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3114 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3115 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3117 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3118 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3123 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3125 rte_write32(0, (uint8_t *)bp->bar0 +
3126 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3127 rte_write32(0, (uint8_t *)bp->bar0 +
3128 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3131 static uint64_t bnxt_cc_read(struct bnxt *bp)
3135 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3136 BNXT_GRCPF_REG_SYNC_TIME));
3137 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3138 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3142 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3144 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3147 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3148 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3149 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3152 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3153 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3154 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3155 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3156 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3157 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3162 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3164 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3165 struct bnxt_pf_info *pf = bp->pf;
3172 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3173 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3174 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3177 port_id = pf->port_id;
3178 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3179 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3181 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3182 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3183 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3184 /* bnxt_clr_rx_ts(bp); TBD */
3188 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3189 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3190 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3191 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3197 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3200 struct bnxt *bp = dev->data->dev_private;
3201 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3206 ns = rte_timespec_to_ns(ts);
3207 /* Set the timecounters to a new value. */
3214 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3216 struct bnxt *bp = dev->data->dev_private;
3217 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3218 uint64_t ns, systime_cycles = 0;
3224 if (BNXT_CHIP_P5(bp))
3225 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3228 systime_cycles = bnxt_cc_read(bp);
3230 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3231 *ts = rte_ns_to_timespec(ns);
3236 bnxt_timesync_enable(struct rte_eth_dev *dev)
3238 struct bnxt *bp = dev->data->dev_private;
3239 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3247 ptp->tx_tstamp_en = 1;
3248 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3250 rc = bnxt_hwrm_ptp_cfg(bp);
3254 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3255 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3256 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3258 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3259 ptp->tc.cc_shift = shift;
3260 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3262 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3263 ptp->rx_tstamp_tc.cc_shift = shift;
3264 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3266 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3267 ptp->tx_tstamp_tc.cc_shift = shift;
3268 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3270 if (!BNXT_CHIP_P5(bp))
3271 bnxt_map_ptp_regs(bp);
3277 bnxt_timesync_disable(struct rte_eth_dev *dev)
3279 struct bnxt *bp = dev->data->dev_private;
3280 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3286 ptp->tx_tstamp_en = 0;
3289 bnxt_hwrm_ptp_cfg(bp);
3291 if (!BNXT_CHIP_P5(bp))
3292 bnxt_unmap_ptp_regs(bp);
3298 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3299 struct timespec *timestamp,
3300 uint32_t flags __rte_unused)
3302 struct bnxt *bp = dev->data->dev_private;
3303 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3304 uint64_t rx_tstamp_cycles = 0;
3310 if (BNXT_CHIP_P5(bp))
3311 rx_tstamp_cycles = ptp->rx_timestamp;
3313 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3315 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3316 *timestamp = rte_ns_to_timespec(ns);
3321 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3322 struct timespec *timestamp)
3324 struct bnxt *bp = dev->data->dev_private;
3325 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3326 uint64_t tx_tstamp_cycles = 0;
3333 if (BNXT_CHIP_P5(bp))
3334 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3337 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3339 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3340 *timestamp = rte_ns_to_timespec(ns);
3346 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3348 struct bnxt *bp = dev->data->dev_private;
3349 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3354 ptp->tc.nsec += delta;
3360 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3362 struct bnxt *bp = dev->data->dev_private;
3364 uint32_t dir_entries;
3365 uint32_t entry_length;
3367 rc = is_bnxt_in_error(bp);
3371 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3372 bp->pdev->addr.domain, bp->pdev->addr.bus,
3373 bp->pdev->addr.devid, bp->pdev->addr.function);
3375 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3379 return dir_entries * entry_length;
3383 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3384 struct rte_dev_eeprom_info *in_eeprom)
3386 struct bnxt *bp = dev->data->dev_private;
3391 rc = is_bnxt_in_error(bp);
3395 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3396 bp->pdev->addr.domain, bp->pdev->addr.bus,
3397 bp->pdev->addr.devid, bp->pdev->addr.function,
3398 in_eeprom->offset, in_eeprom->length);
3400 if (in_eeprom->offset == 0) /* special offset value to get directory */
3401 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3404 index = in_eeprom->offset >> 24;
3405 offset = in_eeprom->offset & 0xffffff;
3408 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3409 in_eeprom->length, in_eeprom->data);
3414 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3417 case BNX_DIR_TYPE_CHIMP_PATCH:
3418 case BNX_DIR_TYPE_BOOTCODE:
3419 case BNX_DIR_TYPE_BOOTCODE_2:
3420 case BNX_DIR_TYPE_APE_FW:
3421 case BNX_DIR_TYPE_APE_PATCH:
3422 case BNX_DIR_TYPE_KONG_FW:
3423 case BNX_DIR_TYPE_KONG_PATCH:
3424 case BNX_DIR_TYPE_BONO_FW:
3425 case BNX_DIR_TYPE_BONO_PATCH:
3433 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3436 case BNX_DIR_TYPE_AVS:
3437 case BNX_DIR_TYPE_EXP_ROM_MBA:
3438 case BNX_DIR_TYPE_PCIE:
3439 case BNX_DIR_TYPE_TSCF_UCODE:
3440 case BNX_DIR_TYPE_EXT_PHY:
3441 case BNX_DIR_TYPE_CCM:
3442 case BNX_DIR_TYPE_ISCSI_BOOT:
3443 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3444 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3452 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3454 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3455 bnxt_dir_type_is_other_exec_format(dir_type);
3459 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3460 struct rte_dev_eeprom_info *in_eeprom)
3462 struct bnxt *bp = dev->data->dev_private;
3463 uint8_t index, dir_op;
3464 uint16_t type, ext, ordinal, attr;
3467 rc = is_bnxt_in_error(bp);
3471 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3472 bp->pdev->addr.domain, bp->pdev->addr.bus,
3473 bp->pdev->addr.devid, bp->pdev->addr.function,
3474 in_eeprom->offset, in_eeprom->length);
3477 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3481 type = in_eeprom->magic >> 16;
3483 if (type == 0xffff) { /* special value for directory operations */
3484 index = in_eeprom->magic & 0xff;
3485 dir_op = in_eeprom->magic >> 8;
3489 case 0x0e: /* erase */
3490 if (in_eeprom->offset != ~in_eeprom->magic)
3492 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3498 /* Create or re-write an NVM item: */
3499 if (bnxt_dir_type_is_executable(type) == true)
3501 ext = in_eeprom->magic & 0xffff;
3502 ordinal = in_eeprom->offset >> 16;
3503 attr = in_eeprom->offset & 0xffff;
3505 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3506 in_eeprom->data, in_eeprom->length);
3513 static const struct eth_dev_ops bnxt_dev_ops = {
3514 .dev_infos_get = bnxt_dev_info_get_op,
3515 .dev_close = bnxt_dev_close_op,
3516 .dev_configure = bnxt_dev_configure_op,
3517 .dev_start = bnxt_dev_start_op,
3518 .dev_stop = bnxt_dev_stop_op,
3519 .dev_set_link_up = bnxt_dev_set_link_up_op,
3520 .dev_set_link_down = bnxt_dev_set_link_down_op,
3521 .stats_get = bnxt_stats_get_op,
3522 .stats_reset = bnxt_stats_reset_op,
3523 .rx_queue_setup = bnxt_rx_queue_setup_op,
3524 .rx_queue_release = bnxt_rx_queue_release_op,
3525 .tx_queue_setup = bnxt_tx_queue_setup_op,
3526 .tx_queue_release = bnxt_tx_queue_release_op,
3527 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3528 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3529 .reta_update = bnxt_reta_update_op,
3530 .reta_query = bnxt_reta_query_op,
3531 .rss_hash_update = bnxt_rss_hash_update_op,
3532 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3533 .link_update = bnxt_link_update_op,
3534 .promiscuous_enable = bnxt_promiscuous_enable_op,
3535 .promiscuous_disable = bnxt_promiscuous_disable_op,
3536 .allmulticast_enable = bnxt_allmulticast_enable_op,
3537 .allmulticast_disable = bnxt_allmulticast_disable_op,
3538 .mac_addr_add = bnxt_mac_addr_add_op,
3539 .mac_addr_remove = bnxt_mac_addr_remove_op,
3540 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3541 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3542 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3543 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3544 .vlan_filter_set = bnxt_vlan_filter_set_op,
3545 .vlan_offload_set = bnxt_vlan_offload_set_op,
3546 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3547 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3548 .mtu_set = bnxt_mtu_set_op,
3549 .mac_addr_set = bnxt_set_default_mac_addr_op,
3550 .xstats_get = bnxt_dev_xstats_get_op,
3551 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3552 .xstats_reset = bnxt_dev_xstats_reset_op,
3553 .fw_version_get = bnxt_fw_version_get,
3554 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3555 .rxq_info_get = bnxt_rxq_info_get_op,
3556 .txq_info_get = bnxt_txq_info_get_op,
3557 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3558 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3559 .dev_led_on = bnxt_dev_led_on_op,
3560 .dev_led_off = bnxt_dev_led_off_op,
3561 .rx_queue_start = bnxt_rx_queue_start,
3562 .rx_queue_stop = bnxt_rx_queue_stop,
3563 .tx_queue_start = bnxt_tx_queue_start,
3564 .tx_queue_stop = bnxt_tx_queue_stop,
3565 .filter_ctrl = bnxt_filter_ctrl_op,
3566 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3567 .get_eeprom_length = bnxt_get_eeprom_length_op,
3568 .get_eeprom = bnxt_get_eeprom_op,
3569 .set_eeprom = bnxt_set_eeprom_op,
3570 .timesync_enable = bnxt_timesync_enable,
3571 .timesync_disable = bnxt_timesync_disable,
3572 .timesync_read_time = bnxt_timesync_read_time,
3573 .timesync_write_time = bnxt_timesync_write_time,
3574 .timesync_adjust_time = bnxt_timesync_adjust_time,
3575 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3576 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3579 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3583 /* Only pre-map the reset GRC registers using window 3 */
3584 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3585 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3587 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3592 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3594 struct bnxt_error_recovery_info *info = bp->recovery_info;
3595 uint32_t reg_base = 0xffffffff;
3598 /* Only pre-map the monitoring GRC registers using window 2 */
3599 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3600 uint32_t reg = info->status_regs[i];
3602 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3605 if (reg_base == 0xffffffff)
3606 reg_base = reg & 0xfffff000;
3607 if ((reg & 0xfffff000) != reg_base)
3610 /* Use mask 0xffc as the Lower 2 bits indicates
3611 * address space location
3613 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3617 if (reg_base == 0xffffffff)
3620 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3621 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3626 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3628 struct bnxt_error_recovery_info *info = bp->recovery_info;
3629 uint32_t delay = info->delay_after_reset[index];
3630 uint32_t val = info->reset_reg_val[index];
3631 uint32_t reg = info->reset_reg[index];
3632 uint32_t type, offset;
3634 type = BNXT_FW_STATUS_REG_TYPE(reg);
3635 offset = BNXT_FW_STATUS_REG_OFF(reg);
3638 case BNXT_FW_STATUS_REG_TYPE_CFG:
3639 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3641 case BNXT_FW_STATUS_REG_TYPE_GRC:
3642 offset = bnxt_map_reset_regs(bp, offset);
3643 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3645 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3646 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3649 /* wait on a specific interval of time until core reset is complete */
3651 rte_delay_ms(delay);
3654 static void bnxt_dev_cleanup(struct bnxt *bp)
3656 bp->eth_dev->data->dev_link.link_status = 0;
3657 bp->link_info->link_up = 0;
3658 if (bp->eth_dev->data->dev_started)
3659 bnxt_dev_stop_op(bp->eth_dev);
3661 bnxt_uninit_resources(bp, true);
3664 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3666 struct rte_eth_dev *dev = bp->eth_dev;
3667 struct rte_vlan_filter_conf *vfc;
3671 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3672 vfc = &dev->data->vlan_filter_conf;
3673 vidx = vlan_id / 64;
3674 vbit = vlan_id % 64;
3676 /* Each bit corresponds to a VLAN id */
3677 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3678 rc = bnxt_add_vlan_filter(bp, vlan_id);
3687 static int bnxt_restore_mac_filters(struct bnxt *bp)
3689 struct rte_eth_dev *dev = bp->eth_dev;
3690 struct rte_eth_dev_info dev_info;
3691 struct rte_ether_addr *addr;
3697 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3700 rc = bnxt_dev_info_get_op(dev, &dev_info);
3704 /* replay MAC address configuration */
3705 for (i = 1; i < dev_info.max_mac_addrs; i++) {
3706 addr = &dev->data->mac_addrs[i];
3708 /* skip zero address */
3709 if (rte_is_zero_ether_addr(addr))
3713 pool_mask = dev->data->mac_pool_sel[i];
3716 if (pool_mask & 1ULL) {
3717 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3723 } while (pool_mask);
3729 static int bnxt_restore_filters(struct bnxt *bp)
3731 struct rte_eth_dev *dev = bp->eth_dev;
3734 if (dev->data->all_multicast) {
3735 ret = bnxt_allmulticast_enable_op(dev);
3739 if (dev->data->promiscuous) {
3740 ret = bnxt_promiscuous_enable_op(dev);
3745 ret = bnxt_restore_mac_filters(bp);
3749 ret = bnxt_restore_vlan_filters(bp);
3750 /* TODO restore other filters as well */
3754 static void bnxt_dev_recover(void *arg)
3756 struct bnxt *bp = arg;
3757 int timeout = bp->fw_reset_max_msecs;
3760 /* Clear Error flag so that device re-init should happen */
3761 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3764 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
3767 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3768 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3769 } while (rc && timeout);
3772 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3776 rc = bnxt_init_resources(bp, true);
3779 "Failed to initialize resources after reset\n");
3782 /* clear reset flag as the device is initialized now */
3783 bp->flags &= ~BNXT_FLAG_FW_RESET;
3785 rc = bnxt_dev_start_op(bp->eth_dev);
3787 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3791 rc = bnxt_restore_filters(bp);
3795 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3798 bnxt_dev_stop_op(bp->eth_dev);
3800 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3801 bnxt_uninit_resources(bp, false);
3802 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3805 void bnxt_dev_reset_and_resume(void *arg)
3807 struct bnxt *bp = arg;
3810 bnxt_dev_cleanup(bp);
3812 bnxt_wait_for_device_shutdown(bp);
3814 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3815 bnxt_dev_recover, (void *)bp);
3817 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3820 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3822 struct bnxt_error_recovery_info *info = bp->recovery_info;
3823 uint32_t reg = info->status_regs[index];
3824 uint32_t type, offset, val = 0;
3826 type = BNXT_FW_STATUS_REG_TYPE(reg);
3827 offset = BNXT_FW_STATUS_REG_OFF(reg);
3830 case BNXT_FW_STATUS_REG_TYPE_CFG:
3831 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3833 case BNXT_FW_STATUS_REG_TYPE_GRC:
3834 offset = info->mapped_status_regs[index];
3836 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3837 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3845 static int bnxt_fw_reset_all(struct bnxt *bp)
3847 struct bnxt_error_recovery_info *info = bp->recovery_info;
3851 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3852 /* Reset through master function driver */
3853 for (i = 0; i < info->reg_array_cnt; i++)
3854 bnxt_write_fw_reset_reg(bp, i);
3855 /* Wait for time specified by FW after triggering reset */
3856 rte_delay_ms(info->master_func_wait_period_after_reset);
3857 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3858 /* Reset with the help of Kong processor */
3859 rc = bnxt_hwrm_fw_reset(bp);
3861 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3867 static void bnxt_fw_reset_cb(void *arg)
3869 struct bnxt *bp = arg;
3870 struct bnxt_error_recovery_info *info = bp->recovery_info;
3873 /* Only Master function can do FW reset */
3874 if (bnxt_is_master_func(bp) &&
3875 bnxt_is_recovery_enabled(bp)) {
3876 rc = bnxt_fw_reset_all(bp);
3878 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3883 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3884 * EXCEPTION_FATAL_ASYNC event to all the functions
3885 * (including MASTER FUNC). After receiving this Async, all the active
3886 * drivers should treat this case as FW initiated recovery
3888 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3889 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3890 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3892 /* To recover from error */
3893 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3898 /* Driver should poll FW heartbeat, reset_counter with the frequency
3899 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3900 * When the driver detects heartbeat stop or change in reset_counter,
3901 * it has to trigger a reset to recover from the error condition.
3902 * A “master PF” is the function who will have the privilege to
3903 * initiate the chimp reset. The master PF will be elected by the
3904 * firmware and will be notified through async message.
3906 static void bnxt_check_fw_health(void *arg)
3908 struct bnxt *bp = arg;
3909 struct bnxt_error_recovery_info *info = bp->recovery_info;
3910 uint32_t val = 0, wait_msec;
3912 if (!info || !bnxt_is_recovery_enabled(bp) ||
3913 is_bnxt_in_error(bp))
3916 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
3917 if (val == info->last_heart_beat)
3920 info->last_heart_beat = val;
3922 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
3923 if (val != info->last_reset_counter)
3926 info->last_reset_counter = val;
3928 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
3929 bnxt_check_fw_health, (void *)bp);
3933 /* Stop DMA to/from device */
3934 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3935 bp->flags |= BNXT_FLAG_FW_RESET;
3937 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
3939 if (bnxt_is_master_func(bp))
3940 wait_msec = info->master_func_wait_period;
3942 wait_msec = info->normal_func_wait_period;
3944 rte_eal_alarm_set(US_PER_MS * wait_msec,
3945 bnxt_fw_reset_cb, (void *)bp);
3948 void bnxt_schedule_fw_health_check(struct bnxt *bp)
3950 uint32_t polling_freq;
3952 pthread_mutex_lock(&bp->health_check_lock);
3954 if (!bnxt_is_recovery_enabled(bp))
3957 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
3960 polling_freq = bp->recovery_info->driver_polling_freq;
3962 rte_eal_alarm_set(US_PER_MS * polling_freq,
3963 bnxt_check_fw_health, (void *)bp);
3964 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3967 pthread_mutex_unlock(&bp->health_check_lock);
3970 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
3972 if (!bnxt_is_recovery_enabled(bp))
3975 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
3976 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
3979 static bool bnxt_vf_pciid(uint16_t device_id)
3981 switch (device_id) {
3982 case BROADCOM_DEV_ID_57304_VF:
3983 case BROADCOM_DEV_ID_57406_VF:
3984 case BROADCOM_DEV_ID_5731X_VF:
3985 case BROADCOM_DEV_ID_5741X_VF:
3986 case BROADCOM_DEV_ID_57414_VF:
3987 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
3988 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
3989 case BROADCOM_DEV_ID_58802_VF:
3990 case BROADCOM_DEV_ID_57500_VF1:
3991 case BROADCOM_DEV_ID_57500_VF2:
3992 case BROADCOM_DEV_ID_58818_VF:
4000 /* Phase 5 device */
4001 static bool bnxt_p5_device(uint16_t device_id)
4003 switch (device_id) {
4004 case BROADCOM_DEV_ID_57508:
4005 case BROADCOM_DEV_ID_57504:
4006 case BROADCOM_DEV_ID_57502:
4007 case BROADCOM_DEV_ID_57508_MF1:
4008 case BROADCOM_DEV_ID_57504_MF1:
4009 case BROADCOM_DEV_ID_57502_MF1:
4010 case BROADCOM_DEV_ID_57508_MF2:
4011 case BROADCOM_DEV_ID_57504_MF2:
4012 case BROADCOM_DEV_ID_57502_MF2:
4013 case BROADCOM_DEV_ID_57500_VF1:
4014 case BROADCOM_DEV_ID_57500_VF2:
4015 case BROADCOM_DEV_ID_58812:
4016 case BROADCOM_DEV_ID_58814:
4017 case BROADCOM_DEV_ID_58818:
4018 case BROADCOM_DEV_ID_58818_VF:
4026 bool bnxt_stratus_device(struct bnxt *bp)
4028 uint16_t device_id = bp->pdev->id.device_id;
4030 switch (device_id) {
4031 case BROADCOM_DEV_ID_STRATUS_NIC:
4032 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4033 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4041 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4043 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4044 struct bnxt *bp = eth_dev->data->dev_private;
4046 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4047 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4048 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4049 if (!bp->bar0 || !bp->doorbell_base) {
4050 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4054 bp->eth_dev = eth_dev;
4060 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4061 struct bnxt_ctx_pg_info *ctx_pg,
4066 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4067 const struct rte_memzone *mz = NULL;
4068 char mz_name[RTE_MEMZONE_NAMESIZE];
4069 rte_iova_t mz_phys_addr;
4070 uint64_t valid_bits = 0;
4077 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4079 rmem->page_size = BNXT_PAGE_SIZE;
4080 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4081 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4082 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4084 valid_bits = PTU_PTE_VALID;
4086 if (rmem->nr_pages > 1) {
4087 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4088 "bnxt_ctx_pg_tbl%s_%x_%d",
4089 suffix, idx, bp->eth_dev->data->port_id);
4090 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4091 mz = rte_memzone_lookup(mz_name);
4093 mz = rte_memzone_reserve_aligned(mz_name,
4097 RTE_MEMZONE_SIZE_HINT_ONLY |
4098 RTE_MEMZONE_IOVA_CONTIG,
4104 memset(mz->addr, 0, mz->len);
4105 mz_phys_addr = mz->iova;
4107 rmem->pg_tbl = mz->addr;
4108 rmem->pg_tbl_map = mz_phys_addr;
4109 rmem->pg_tbl_mz = mz;
4112 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4113 suffix, idx, bp->eth_dev->data->port_id);
4114 mz = rte_memzone_lookup(mz_name);
4116 mz = rte_memzone_reserve_aligned(mz_name,
4120 RTE_MEMZONE_SIZE_HINT_ONLY |
4121 RTE_MEMZONE_IOVA_CONTIG,
4127 memset(mz->addr, 0, mz->len);
4128 mz_phys_addr = mz->iova;
4130 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4131 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4132 rmem->dma_arr[i] = mz_phys_addr + sz;
4134 if (rmem->nr_pages > 1) {
4135 if (i == rmem->nr_pages - 2 &&
4136 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4137 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4138 else if (i == rmem->nr_pages - 1 &&
4139 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4140 valid_bits |= PTU_PTE_LAST;
4142 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4148 if (rmem->vmem_size)
4149 rmem->vmem = (void **)mz->addr;
4150 rmem->dma_arr[0] = mz_phys_addr;
4154 static void bnxt_free_ctx_mem(struct bnxt *bp)
4158 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4161 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4162 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4163 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4164 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4165 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4166 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4167 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4168 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4169 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4170 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4171 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4173 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4174 if (bp->ctx->tqm_mem[i])
4175 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4182 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4184 #define min_t(type, x, y) ({ \
4185 type __min1 = (x); \
4186 type __min2 = (y); \
4187 __min1 < __min2 ? __min1 : __min2; })
4189 #define max_t(type, x, y) ({ \
4190 type __max1 = (x); \
4191 type __max2 = (y); \
4192 __max1 > __max2 ? __max1 : __max2; })
4194 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4196 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4198 struct bnxt_ctx_pg_info *ctx_pg;
4199 struct bnxt_ctx_mem_info *ctx;
4200 uint32_t mem_size, ena, entries;
4201 uint32_t entries_sp, min;
4204 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4206 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4210 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4213 ctx_pg = &ctx->qp_mem;
4214 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4215 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4216 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4220 ctx_pg = &ctx->srq_mem;
4221 ctx_pg->entries = ctx->srq_max_l2_entries;
4222 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4223 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4227 ctx_pg = &ctx->cq_mem;
4228 ctx_pg->entries = ctx->cq_max_l2_entries;
4229 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4230 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4234 ctx_pg = &ctx->vnic_mem;
4235 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4236 ctx->vnic_max_ring_table_entries;
4237 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4238 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4242 ctx_pg = &ctx->stat_mem;
4243 ctx_pg->entries = ctx->stat_max_entries;
4244 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4245 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4249 min = ctx->tqm_min_entries_per_ring;
4251 entries_sp = ctx->qp_max_l2_entries +
4252 ctx->vnic_max_vnic_entries +
4253 2 * ctx->qp_min_qp1_entries + min;
4254 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4256 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4257 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4258 entries = clamp_t(uint32_t, entries, min,
4259 ctx->tqm_max_entries_per_ring);
4260 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4261 ctx_pg = ctx->tqm_mem[i];
4262 ctx_pg->entries = i ? entries : entries_sp;
4263 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4264 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4267 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4270 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4271 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4274 "Failed to configure context mem: rc = %d\n", rc);
4276 ctx->flags |= BNXT_CTX_FLAG_INITED;
4281 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4283 struct rte_pci_device *pci_dev = bp->pdev;
4284 char mz_name[RTE_MEMZONE_NAMESIZE];
4285 const struct rte_memzone *mz = NULL;
4286 uint32_t total_alloc_len;
4287 rte_iova_t mz_phys_addr;
4289 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4292 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4293 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4294 pci_dev->addr.bus, pci_dev->addr.devid,
4295 pci_dev->addr.function, "rx_port_stats");
4296 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4297 mz = rte_memzone_lookup(mz_name);
4299 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4300 sizeof(struct rx_port_stats_ext) + 512);
4302 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4305 RTE_MEMZONE_SIZE_HINT_ONLY |
4306 RTE_MEMZONE_IOVA_CONTIG);
4310 memset(mz->addr, 0, mz->len);
4311 mz_phys_addr = mz->iova;
4313 bp->rx_mem_zone = (const void *)mz;
4314 bp->hw_rx_port_stats = mz->addr;
4315 bp->hw_rx_port_stats_map = mz_phys_addr;
4317 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4318 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4319 pci_dev->addr.bus, pci_dev->addr.devid,
4320 pci_dev->addr.function, "tx_port_stats");
4321 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4322 mz = rte_memzone_lookup(mz_name);
4324 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4325 sizeof(struct tx_port_stats_ext) + 512);
4327 mz = rte_memzone_reserve(mz_name,
4331 RTE_MEMZONE_SIZE_HINT_ONLY |
4332 RTE_MEMZONE_IOVA_CONTIG);
4336 memset(mz->addr, 0, mz->len);
4337 mz_phys_addr = mz->iova;
4339 bp->tx_mem_zone = (const void *)mz;
4340 bp->hw_tx_port_stats = mz->addr;
4341 bp->hw_tx_port_stats_map = mz_phys_addr;
4342 bp->flags |= BNXT_FLAG_PORT_STATS;
4344 /* Display extended statistics if FW supports it */
4345 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4346 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4347 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4350 bp->hw_rx_port_stats_ext = (void *)
4351 ((uint8_t *)bp->hw_rx_port_stats +
4352 sizeof(struct rx_port_stats));
4353 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4354 sizeof(struct rx_port_stats);
4355 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4357 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4358 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4359 bp->hw_tx_port_stats_ext = (void *)
4360 ((uint8_t *)bp->hw_tx_port_stats +
4361 sizeof(struct tx_port_stats));
4362 bp->hw_tx_port_stats_ext_map =
4363 bp->hw_tx_port_stats_map +
4364 sizeof(struct tx_port_stats);
4365 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4371 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4373 struct bnxt *bp = eth_dev->data->dev_private;
4376 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4377 RTE_ETHER_ADDR_LEN *
4380 if (eth_dev->data->mac_addrs == NULL) {
4381 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4385 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4389 /* Generate a random MAC address, if none was assigned by PF */
4390 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4391 bnxt_eth_hw_addr_random(bp->mac_addr);
4393 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4394 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4395 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4397 rc = bnxt_hwrm_set_mac(bp);
4402 /* Copy the permanent MAC from the FUNC_QCAPS response */
4403 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4408 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4412 /* MAC is already configured in FW */
4413 if (BNXT_HAS_DFLT_MAC_SET(bp))
4416 /* Restore the old MAC configured */
4417 rc = bnxt_hwrm_set_mac(bp);
4419 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4424 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4429 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4431 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4432 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4433 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4434 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4435 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4436 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4440 bnxt_get_svif(uint16_t port_id, bool func_svif,
4441 enum bnxt_ulp_intf_type type)
4443 struct rte_eth_dev *eth_dev;
4446 eth_dev = &rte_eth_devices[port_id];
4447 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4448 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4452 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4455 eth_dev = vfr->parent_dev;
4458 bp = eth_dev->data->dev_private;
4460 return func_svif ? bp->func_svif : bp->port_svif;
4464 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4466 struct rte_eth_dev *eth_dev;
4467 struct bnxt_vnic_info *vnic;
4470 eth_dev = &rte_eth_devices[port];
4471 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4472 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4476 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4477 return vfr->dflt_vnic_id;
4479 eth_dev = vfr->parent_dev;
4482 bp = eth_dev->data->dev_private;
4484 vnic = BNXT_GET_DEFAULT_VNIC(bp);
4486 return vnic->fw_vnic_id;
4490 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4492 struct rte_eth_dev *eth_dev;
4495 eth_dev = &rte_eth_devices[port];
4496 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4497 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4501 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4504 eth_dev = vfr->parent_dev;
4507 bp = eth_dev->data->dev_private;
4512 enum bnxt_ulp_intf_type
4513 bnxt_get_interface_type(uint16_t port)
4515 struct rte_eth_dev *eth_dev;
4518 eth_dev = &rte_eth_devices[port];
4519 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4520 return BNXT_ULP_INTF_TYPE_VF_REP;
4522 bp = eth_dev->data->dev_private;
4524 return BNXT_ULP_INTF_TYPE_PF;
4525 else if (BNXT_VF_IS_TRUSTED(bp))
4526 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4527 else if (BNXT_VF(bp))
4528 return BNXT_ULP_INTF_TYPE_VF;
4530 return BNXT_ULP_INTF_TYPE_INVALID;
4534 bnxt_get_phy_port_id(uint16_t port_id)
4536 struct bnxt_representor *vfr;
4537 struct rte_eth_dev *eth_dev;
4540 eth_dev = &rte_eth_devices[port_id];
4541 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4542 vfr = eth_dev->data->dev_private;
4546 eth_dev = vfr->parent_dev;
4549 bp = eth_dev->data->dev_private;
4551 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4555 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4557 struct rte_eth_dev *eth_dev;
4560 eth_dev = &rte_eth_devices[port_id];
4561 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4562 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4566 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4567 return vfr->fw_fid - 1;
4569 eth_dev = vfr->parent_dev;
4572 bp = eth_dev->data->dev_private;
4574 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
4578 bnxt_get_vport(uint16_t port_id)
4580 return (1 << bnxt_get_phy_port_id(port_id));
4583 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4585 struct bnxt_error_recovery_info *info = bp->recovery_info;
4588 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4589 memset(info, 0, sizeof(*info));
4593 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4596 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4599 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4601 bp->recovery_info = info;
4604 static void bnxt_check_fw_status(struct bnxt *bp)
4608 if (!(bp->recovery_info &&
4609 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
4612 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
4613 if (fw_status != BNXT_FW_STATUS_HEALTHY)
4614 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
4618 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
4620 struct bnxt_error_recovery_info *info = bp->recovery_info;
4621 uint32_t status_loc;
4624 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
4625 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4626 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4627 BNXT_GRCP_WINDOW_2_BASE +
4628 offsetof(struct hcomm_status,
4630 /* If the signature is absent, then FW does not support this feature */
4631 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
4632 HCOMM_STATUS_SIGNATURE_VAL)
4636 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4640 bp->recovery_info = info;
4642 memset(info, 0, sizeof(*info));
4645 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4646 BNXT_GRCP_WINDOW_2_BASE +
4647 offsetof(struct hcomm_status,
4650 /* Only pre-map the FW health status GRC register */
4651 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
4654 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
4655 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
4656 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
4658 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
4659 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4661 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
4666 static int bnxt_init_fw(struct bnxt *bp)
4673 rc = bnxt_map_hcomm_fw_status_reg(bp);
4677 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4679 bnxt_check_fw_status(bp);
4683 rc = bnxt_hwrm_func_reset(bp);
4687 rc = bnxt_hwrm_vnic_qcaps(bp);
4691 rc = bnxt_hwrm_queue_qportcfg(bp);
4695 /* Get the MAX capabilities for this function.
4696 * This function also allocates context memory for TQM rings and
4697 * informs the firmware about this allocated backing store memory.
4699 rc = bnxt_hwrm_func_qcaps(bp);
4703 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4707 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4711 bnxt_hwrm_port_mac_qcfg(bp);
4713 bnxt_hwrm_parent_pf_qcfg(bp);
4715 bnxt_hwrm_port_phy_qcaps(bp);
4717 bnxt_alloc_error_recovery_info(bp);
4718 /* Get the adapter error recovery support info */
4719 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4721 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4723 bnxt_hwrm_port_led_qcaps(bp);
4729 bnxt_init_locks(struct bnxt *bp)
4733 err = pthread_mutex_init(&bp->flow_lock, NULL);
4735 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4739 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4741 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4745 err = pthread_mutex_init(&bp->health_check_lock, NULL);
4747 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
4751 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4755 rc = bnxt_init_fw(bp);
4759 if (!reconfig_dev) {
4760 rc = bnxt_setup_mac_addr(bp->eth_dev);
4764 rc = bnxt_restore_dflt_mac(bp);
4769 bnxt_config_vf_req_fwd(bp);
4771 rc = bnxt_hwrm_func_driver_register(bp);
4773 PMD_DRV_LOG(ERR, "Failed to register driver");
4778 if (bp->pdev->max_vfs) {
4779 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4781 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4785 rc = bnxt_hwrm_allocate_pf_only(bp);
4788 "Failed to allocate PF resources");
4794 rc = bnxt_alloc_mem(bp, reconfig_dev);
4798 rc = bnxt_setup_int(bp);
4802 rc = bnxt_request_int(bp);
4806 rc = bnxt_init_ctx_mem(bp);
4808 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
4812 rc = bnxt_init_locks(bp);
4820 bnxt_parse_devarg_truflow(__rte_unused const char *key,
4821 const char *value, void *opaque_arg)
4823 struct bnxt *bp = opaque_arg;
4824 unsigned long truflow;
4827 if (!value || !opaque_arg) {
4829 "Invalid parameter passed to truflow devargs.\n");
4833 truflow = strtoul(value, &end, 10);
4834 if (end == NULL || *end != '\0' ||
4835 (truflow == ULONG_MAX && errno == ERANGE)) {
4837 "Invalid parameter passed to truflow devargs.\n");
4841 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
4843 "Invalid value passed to truflow devargs.\n");
4848 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
4849 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
4851 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
4852 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
4859 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
4860 const char *value, void *opaque_arg)
4862 struct bnxt *bp = opaque_arg;
4863 unsigned long flow_xstat;
4866 if (!value || !opaque_arg) {
4868 "Invalid parameter passed to flow_xstat devarg.\n");
4872 flow_xstat = strtoul(value, &end, 10);
4873 if (end == NULL || *end != '\0' ||
4874 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
4876 "Invalid parameter passed to flow_xstat devarg.\n");
4880 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
4882 "Invalid value passed to flow_xstat devarg.\n");
4886 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
4887 if (BNXT_FLOW_XSTATS_EN(bp))
4888 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
4894 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
4895 const char *value, void *opaque_arg)
4897 struct bnxt *bp = opaque_arg;
4898 unsigned long max_num_kflows;
4901 if (!value || !opaque_arg) {
4903 "Invalid parameter passed to max_num_kflows devarg.\n");
4907 max_num_kflows = strtoul(value, &end, 10);
4908 if (end == NULL || *end != '\0' ||
4909 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
4911 "Invalid parameter passed to max_num_kflows devarg.\n");
4915 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
4917 "Invalid value passed to max_num_kflows devarg.\n");
4921 bp->max_num_kflows = max_num_kflows;
4922 if (bp->max_num_kflows)
4923 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
4930 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
4931 const char *value, void *opaque_arg)
4933 struct bnxt_representor *vfr_bp = opaque_arg;
4934 unsigned long rep_is_pf;
4937 if (!value || !opaque_arg) {
4939 "Invalid parameter passed to rep_is_pf devargs.\n");
4943 rep_is_pf = strtoul(value, &end, 10);
4944 if (end == NULL || *end != '\0' ||
4945 (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
4947 "Invalid parameter passed to rep_is_pf devargs.\n");
4951 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
4953 "Invalid value passed to rep_is_pf devargs.\n");
4957 vfr_bp->flags |= rep_is_pf;
4958 if (BNXT_REP_PF(vfr_bp))
4959 PMD_DRV_LOG(INFO, "PF representor\n");
4961 PMD_DRV_LOG(INFO, "VF representor\n");
4967 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
4968 const char *value, void *opaque_arg)
4970 struct bnxt_representor *vfr_bp = opaque_arg;
4971 unsigned long rep_based_pf;
4974 if (!value || !opaque_arg) {
4976 "Invalid parameter passed to rep_based_pf "
4981 rep_based_pf = strtoul(value, &end, 10);
4982 if (end == NULL || *end != '\0' ||
4983 (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
4985 "Invalid parameter passed to rep_based_pf "
4990 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
4992 "Invalid value passed to rep_based_pf devargs.\n");
4996 vfr_bp->rep_based_pf = rep_based_pf;
4997 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
4999 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5005 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5006 const char *value, void *opaque_arg)
5008 struct bnxt_representor *vfr_bp = opaque_arg;
5009 unsigned long rep_q_r2f;
5012 if (!value || !opaque_arg) {
5014 "Invalid parameter passed to rep_q_r2f "
5019 rep_q_r2f = strtoul(value, &end, 10);
5020 if (end == NULL || *end != '\0' ||
5021 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5023 "Invalid parameter passed to rep_q_r2f "
5028 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5030 "Invalid value passed to rep_q_r2f devargs.\n");
5034 vfr_bp->rep_q_r2f = rep_q_r2f;
5035 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5036 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5042 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5043 const char *value, void *opaque_arg)
5045 struct bnxt_representor *vfr_bp = opaque_arg;
5046 unsigned long rep_q_f2r;
5049 if (!value || !opaque_arg) {
5051 "Invalid parameter passed to rep_q_f2r "
5056 rep_q_f2r = strtoul(value, &end, 10);
5057 if (end == NULL || *end != '\0' ||
5058 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5060 "Invalid parameter passed to rep_q_f2r "
5065 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5067 "Invalid value passed to rep_q_f2r devargs.\n");
5071 vfr_bp->rep_q_f2r = rep_q_f2r;
5072 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5073 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5079 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5080 const char *value, void *opaque_arg)
5082 struct bnxt_representor *vfr_bp = opaque_arg;
5083 unsigned long rep_fc_r2f;
5086 if (!value || !opaque_arg) {
5088 "Invalid parameter passed to rep_fc_r2f "
5093 rep_fc_r2f = strtoul(value, &end, 10);
5094 if (end == NULL || *end != '\0' ||
5095 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5097 "Invalid parameter passed to rep_fc_r2f "
5102 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5104 "Invalid value passed to rep_fc_r2f devargs.\n");
5108 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5109 vfr_bp->rep_fc_r2f = rep_fc_r2f;
5110 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5116 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5117 const char *value, void *opaque_arg)
5119 struct bnxt_representor *vfr_bp = opaque_arg;
5120 unsigned long rep_fc_f2r;
5123 if (!value || !opaque_arg) {
5125 "Invalid parameter passed to rep_fc_f2r "
5130 rep_fc_f2r = strtoul(value, &end, 10);
5131 if (end == NULL || *end != '\0' ||
5132 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5134 "Invalid parameter passed to rep_fc_f2r "
5139 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5141 "Invalid value passed to rep_fc_f2r devargs.\n");
5145 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5146 vfr_bp->rep_fc_f2r = rep_fc_f2r;
5147 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5153 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5155 struct rte_kvargs *kvlist;
5157 if (devargs == NULL)
5160 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5165 * Handler for "truflow" devarg.
5166 * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1"
5168 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5169 bnxt_parse_devarg_truflow, bp);
5172 * Handler for "flow_xstat" devarg.
5173 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5175 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5176 bnxt_parse_devarg_flow_xstat, bp);
5179 * Handler for "max_num_kflows" devarg.
5180 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5182 rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5183 bnxt_parse_devarg_max_num_kflows, bp);
5185 rte_kvargs_free(kvlist);
5188 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5192 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5193 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5196 "Failed to alloc switch domain: %d\n", rc);
5199 "Switch domain allocated %d\n",
5200 bp->switch_domain_id);
5207 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5209 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5210 static int version_printed;
5214 if (version_printed++ == 0)
5215 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5217 eth_dev->dev_ops = &bnxt_dev_ops;
5218 eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5219 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5220 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5221 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5222 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5225 * For secondary processes, we don't initialise any further
5226 * as primary has already done this work.
5228 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5231 rte_eth_copy_pci_info(eth_dev, pci_dev);
5232 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5234 bp = eth_dev->data->dev_private;
5236 /* Parse dev arguments passed on when starting the DPDK application. */
5237 bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5239 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5241 if (bnxt_vf_pciid(pci_dev->id.device_id))
5242 bp->flags |= BNXT_FLAG_VF;
5244 if (bnxt_p5_device(pci_dev->id.device_id))
5245 bp->flags |= BNXT_FLAG_CHIP_P5;
5247 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5248 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5249 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5250 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5251 bp->flags |= BNXT_FLAG_STINGRAY;
5253 if (BNXT_TRUFLOW_EN(bp)) {
5254 /* extra mbuf field is required to store CFA code from mark */
5255 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5256 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5257 .size = sizeof(bnxt_cfa_code_dynfield_t),
5258 .align = __alignof__(bnxt_cfa_code_dynfield_t),
5260 bnxt_cfa_code_dynfield_offset =
5261 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5262 if (bnxt_cfa_code_dynfield_offset < 0) {
5264 "Failed to register mbuf field for TruFlow mark\n");
5269 rc = bnxt_init_board(eth_dev);
5272 "Failed to initialize board rc: %x\n", rc);
5276 rc = bnxt_alloc_pf_info(bp);
5280 rc = bnxt_alloc_link_info(bp);
5284 rc = bnxt_alloc_parent_info(bp);
5288 rc = bnxt_alloc_hwrm_resources(bp);
5291 "Failed to allocate hwrm resource rc: %x\n", rc);
5294 rc = bnxt_alloc_leds_info(bp);
5298 rc = bnxt_alloc_cos_queues(bp);
5302 rc = bnxt_init_resources(bp, false);
5306 rc = bnxt_alloc_stats_mem(bp);
5310 bnxt_alloc_switch_domain(bp);
5313 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5314 pci_dev->mem_resource[0].phys_addr,
5315 pci_dev->mem_resource[0].addr);
5320 bnxt_dev_uninit(eth_dev);
5325 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5334 ctx->dma = RTE_BAD_IOVA;
5335 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5338 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5340 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5341 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5342 bp->flow_stat->rx_fc_out_tbl.ctx_id,
5343 bp->flow_stat->max_fc,
5346 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5347 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5348 bp->flow_stat->tx_fc_out_tbl.ctx_id,
5349 bp->flow_stat->max_fc,
5352 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5353 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5354 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5356 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5357 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5358 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5360 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5361 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5362 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5364 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5365 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5366 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5369 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5371 bnxt_unregister_fc_ctx_mem(bp);
5373 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5374 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5375 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5376 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5379 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5381 if (BNXT_FLOW_XSTATS_EN(bp))
5382 bnxt_uninit_fc_ctx_mem(bp);
5386 bnxt_free_error_recovery_info(struct bnxt *bp)
5388 rte_free(bp->recovery_info);
5389 bp->recovery_info = NULL;
5390 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5394 bnxt_uninit_locks(struct bnxt *bp)
5396 pthread_mutex_destroy(&bp->flow_lock);
5397 pthread_mutex_destroy(&bp->def_cp_lock);
5398 pthread_mutex_destroy(&bp->health_check_lock);
5400 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
5401 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
5406 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5411 bnxt_free_mem(bp, reconfig_dev);
5413 bnxt_hwrm_func_buf_unrgtr(bp);
5414 rte_free(bp->pf->vf_req_buf);
5416 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5417 bp->flags &= ~BNXT_FLAG_REGISTERED;
5418 bnxt_free_ctx_mem(bp);
5419 if (!reconfig_dev) {
5420 bnxt_free_hwrm_resources(bp);
5421 bnxt_free_error_recovery_info(bp);
5424 bnxt_uninit_ctx_mem(bp);
5426 bnxt_uninit_locks(bp);
5427 bnxt_free_flow_stats_info(bp);
5428 bnxt_free_rep_info(bp);
5429 rte_free(bp->ptp_cfg);
5435 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5437 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5440 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5442 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5443 bnxt_dev_close_op(eth_dev);
5448 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5450 struct bnxt *bp = eth_dev->data->dev_private;
5451 struct rte_eth_dev *vf_rep_eth_dev;
5457 for (i = 0; i < bp->num_reps; i++) {
5458 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5459 if (!vf_rep_eth_dev)
5461 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5462 vf_rep_eth_dev->data->port_id);
5463 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5465 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5466 eth_dev->data->port_id);
5467 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5472 static void bnxt_free_rep_info(struct bnxt *bp)
5474 rte_free(bp->rep_info);
5475 bp->rep_info = NULL;
5476 rte_free(bp->cfa_code_map);
5477 bp->cfa_code_map = NULL;
5480 static int bnxt_init_rep_info(struct bnxt *bp)
5487 bp->rep_info = rte_zmalloc("bnxt_rep_info",
5488 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5490 if (!bp->rep_info) {
5491 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5494 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5495 sizeof(*bp->cfa_code_map) *
5496 BNXT_MAX_CFA_CODE, 0);
5497 if (!bp->cfa_code_map) {
5498 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5499 bnxt_free_rep_info(bp);
5503 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5504 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5506 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5508 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5509 bnxt_free_rep_info(bp);
5513 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5515 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5516 bnxt_free_rep_info(bp);
5523 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5524 struct rte_eth_devargs *eth_da,
5525 struct rte_eth_dev *backing_eth_dev,
5526 const char *dev_args)
5528 struct rte_eth_dev *vf_rep_eth_dev;
5529 char name[RTE_ETH_NAME_MAX_LEN];
5530 struct bnxt *backing_bp;
5533 struct rte_kvargs *kvlist = NULL;
5535 num_rep = eth_da->nb_representor_ports;
5536 if (num_rep > BNXT_MAX_VF_REPS) {
5537 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5538 num_rep, BNXT_MAX_VF_REPS);
5542 if (num_rep >= RTE_MAX_ETHPORTS) {
5544 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5545 num_rep, RTE_MAX_ETHPORTS);
5549 backing_bp = backing_eth_dev->data->dev_private;
5551 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5553 "Not a PF or trusted VF. No Representor support\n");
5554 /* Returning an error is not an option.
5555 * Applications are not handling this correctly
5560 if (bnxt_init_rep_info(backing_bp))
5563 for (i = 0; i < num_rep; i++) {
5564 struct bnxt_representor representor = {
5565 .vf_id = eth_da->representor_ports[i],
5566 .switch_domain_id = backing_bp->switch_domain_id,
5567 .parent_dev = backing_eth_dev
5570 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5571 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5572 representor.vf_id, BNXT_MAX_VF_REPS);
5576 /* representor port net_bdf_port */
5577 snprintf(name, sizeof(name), "net_%s_representor_%d",
5578 pci_dev->device.name, eth_da->representor_ports[i]);
5580 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
5583 * Handler for "rep_is_pf" devarg.
5584 * Invoked as for ex: "-a 000:00:0d.0,
5585 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5587 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
5588 bnxt_parse_devarg_rep_is_pf,
5589 (void *)&representor);
5595 * Handler for "rep_based_pf" devarg.
5596 * Invoked as for ex: "-a 000:00:0d.0,
5597 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5599 ret = rte_kvargs_process(kvlist,
5600 BNXT_DEVARG_REP_BASED_PF,
5601 bnxt_parse_devarg_rep_based_pf,
5602 (void *)&representor);
5608 * Handler for "rep_based_pf" devarg.
5609 * Invoked as for ex: "-a 000:00:0d.0,
5610 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5612 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
5613 bnxt_parse_devarg_rep_q_r2f,
5614 (void *)&representor);
5620 * Handler for "rep_based_pf" devarg.
5621 * Invoked as for ex: "-a 000:00:0d.0,
5622 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5624 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
5625 bnxt_parse_devarg_rep_q_f2r,
5626 (void *)&representor);
5632 * Handler for "rep_based_pf" devarg.
5633 * Invoked as for ex: "-a 000:00:0d.0,
5634 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5636 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
5637 bnxt_parse_devarg_rep_fc_r2f,
5638 (void *)&representor);
5644 * Handler for "rep_based_pf" devarg.
5645 * Invoked as for ex: "-a 000:00:0d.0,
5646 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5648 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
5649 bnxt_parse_devarg_rep_fc_f2r,
5650 (void *)&representor);
5657 ret = rte_eth_dev_create(&pci_dev->device, name,
5658 sizeof(struct bnxt_representor),
5660 bnxt_representor_init,
5663 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
5664 "representor %s.", name);
5668 vf_rep_eth_dev = rte_eth_dev_allocated(name);
5669 if (!vf_rep_eth_dev) {
5670 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
5671 " for VF-Rep: %s.", name);
5676 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
5677 backing_eth_dev->data->port_id);
5678 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
5680 backing_bp->num_reps++;
5684 rte_kvargs_free(kvlist);
5688 /* If num_rep > 1, then rollback already created
5689 * ports, since we'll be failing the probe anyway
5692 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
5694 rte_kvargs_free(kvlist);
5699 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5700 struct rte_pci_device *pci_dev)
5702 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
5703 struct rte_eth_dev *backing_eth_dev;
5707 if (pci_dev->device.devargs) {
5708 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
5714 num_rep = eth_da.nb_representor_ports;
5715 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
5718 /* We could come here after first level of probe is already invoked
5719 * as part of an application bringup(OVS-DPDK vswitchd), so first check
5720 * for already allocated eth_dev for the backing device (PF/Trusted VF)
5722 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5723 if (backing_eth_dev == NULL) {
5724 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
5725 sizeof(struct bnxt),
5726 eth_dev_pci_specific_init, pci_dev,
5727 bnxt_dev_init, NULL);
5729 if (ret || !num_rep)
5732 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5734 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
5735 backing_eth_dev->data->port_id);
5740 /* probe representor ports now */
5741 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev,
5742 pci_dev->device.devargs->args);
5747 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5749 struct rte_eth_dev *eth_dev;
5751 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5753 return 0; /* Invoked typically only by OVS-DPDK, by the
5754 * time it comes here the eth_dev is already
5755 * deleted by rte_eth_dev_close(), so returning
5756 * +ve value will at least help in proper cleanup
5759 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
5760 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
5761 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
5762 return rte_eth_dev_destroy(eth_dev,
5763 bnxt_representor_uninit);
5765 return rte_eth_dev_destroy(eth_dev,
5768 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5772 static struct rte_pci_driver bnxt_rte_pmd = {
5773 .id_table = bnxt_pci_id_map,
5774 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
5775 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
5778 .probe = bnxt_pci_probe,
5779 .remove = bnxt_pci_remove,
5783 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5785 if (strcmp(dev->device->driver->name, drv->driver.name))
5791 bool is_bnxt_supported(struct rte_eth_dev *dev)
5793 return is_device_supported(dev, &bnxt_rte_pmd);
5796 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
5797 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5798 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5799 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");