1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
30 #define DRV_MODULE_NAME "bnxt"
31 static const char bnxt_version[] =
32 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
33 int bnxt_logtype_driver;
36 * The set of PCI devices this driver supports
38 static const struct rte_pci_id bnxt_pci_id_map[] = {
39 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
40 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
41 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
42 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
43 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
45 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
92 { .vendor_id = 0, /* sentinel */ },
95 #define BNXT_ETH_RSS_SUPPORT ( \
97 ETH_RSS_NONFRAG_IPV4_TCP | \
98 ETH_RSS_NONFRAG_IPV4_UDP | \
100 ETH_RSS_NONFRAG_IPV6_TCP | \
101 ETH_RSS_NONFRAG_IPV6_UDP)
103 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
104 DEV_TX_OFFLOAD_IPV4_CKSUM | \
105 DEV_TX_OFFLOAD_TCP_CKSUM | \
106 DEV_TX_OFFLOAD_UDP_CKSUM | \
107 DEV_TX_OFFLOAD_TCP_TSO | \
108 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
109 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
110 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
111 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
112 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
113 DEV_TX_OFFLOAD_QINQ_INSERT | \
114 DEV_TX_OFFLOAD_MULTI_SEGS)
116 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
117 DEV_RX_OFFLOAD_VLAN_STRIP | \
118 DEV_RX_OFFLOAD_IPV4_CKSUM | \
119 DEV_RX_OFFLOAD_UDP_CKSUM | \
120 DEV_RX_OFFLOAD_TCP_CKSUM | \
121 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
122 DEV_RX_OFFLOAD_JUMBO_FRAME | \
123 DEV_RX_OFFLOAD_KEEP_CRC | \
124 DEV_RX_OFFLOAD_VLAN_EXTEND | \
125 DEV_RX_OFFLOAD_TCP_LRO | \
126 DEV_RX_OFFLOAD_SCATTER | \
127 DEV_RX_OFFLOAD_RSS_HASH)
129 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
130 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
131 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
132 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
133 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
134 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
135 static int bnxt_restore_vlan_filters(struct bnxt *bp);
136 static void bnxt_dev_recover(void *arg);
138 int is_bnxt_in_error(struct bnxt *bp)
140 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
142 if (bp->flags & BNXT_FLAG_FW_RESET)
148 /***********************/
151 * High level utility functions
154 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
156 if (!BNXT_CHIP_THOR(bp))
159 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings,
160 BNXT_RSS_ENTRIES_PER_CTX_THOR) /
161 BNXT_RSS_ENTRIES_PER_CTX_THOR;
164 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
166 if (!BNXT_CHIP_THOR(bp))
167 return HW_HASH_INDEX_SIZE;
169 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR;
172 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
174 bnxt_free_filter_mem(bp);
175 bnxt_free_vnic_attributes(bp);
176 bnxt_free_vnic_mem(bp);
178 /* tx/rx rings are configured as part of *_queue_setup callbacks.
179 * If the number of rings change across fw update,
180 * we don't have much choice except to warn the user.
184 bnxt_free_tx_rings(bp);
185 bnxt_free_rx_rings(bp);
187 bnxt_free_async_cp_ring(bp);
188 bnxt_free_rxtx_nq_ring(bp);
190 rte_free(bp->grp_info);
194 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
198 rc = bnxt_alloc_ring_grps(bp);
202 rc = bnxt_alloc_async_ring_struct(bp);
206 rc = bnxt_alloc_vnic_mem(bp);
210 rc = bnxt_alloc_vnic_attributes(bp);
214 rc = bnxt_alloc_filter_mem(bp);
218 rc = bnxt_alloc_async_cp_ring(bp);
222 rc = bnxt_alloc_rxtx_nq_ring(bp);
229 bnxt_free_mem(bp, reconfig);
233 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
235 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
236 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
237 uint64_t rx_offloads = dev_conf->rxmode.offloads;
238 struct bnxt_rx_queue *rxq;
242 rc = bnxt_vnic_grp_alloc(bp, vnic);
246 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
247 vnic_id, vnic, vnic->fw_grp_ids);
249 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
253 /* Alloc RSS context only if RSS mode is enabled */
254 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
255 int j, nr_ctxs = bnxt_rss_ctxts(bp);
258 for (j = 0; j < nr_ctxs; j++) {
259 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
265 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
269 vnic->num_lb_ctxts = nr_ctxs;
273 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
274 * setting is not available at this time, it will not be
275 * configured correctly in the CFA.
277 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
278 vnic->vlan_strip = true;
280 vnic->vlan_strip = false;
282 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
286 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
290 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
291 rxq = bp->eth_dev->data->rx_queues[j];
294 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
295 j, rxq->vnic, rxq->vnic->fw_grp_ids);
297 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
298 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
300 vnic->rx_queue_cnt++;
303 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
305 rc = bnxt_vnic_rss_configure(bp, vnic);
309 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
311 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
312 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
314 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
318 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
323 static int bnxt_init_chip(struct bnxt *bp)
325 struct rte_eth_link new;
326 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
327 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
328 uint32_t intr_vector = 0;
329 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
330 uint32_t vec = BNXT_MISC_VEC_ID;
334 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
335 bp->eth_dev->data->dev_conf.rxmode.offloads |=
336 DEV_RX_OFFLOAD_JUMBO_FRAME;
337 bp->flags |= BNXT_FLAG_JUMBO;
339 bp->eth_dev->data->dev_conf.rxmode.offloads &=
340 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
341 bp->flags &= ~BNXT_FLAG_JUMBO;
344 /* THOR does not support ring groups.
345 * But we will use the array to save RSS context IDs.
347 if (BNXT_CHIP_THOR(bp))
348 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR;
350 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
352 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
356 rc = bnxt_alloc_hwrm_rings(bp);
358 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
362 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
364 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
368 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
371 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
372 if (bp->rx_cos_queue[i].id != 0xff) {
373 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
377 "Num pools more than FW profile\n");
381 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
387 rc = bnxt_mq_rx_configure(bp);
389 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
393 /* VNIC configuration */
394 for (i = 0; i < bp->nr_vnics; i++) {
395 rc = bnxt_setup_one_vnic(bp, i);
400 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
403 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
407 /* check and configure queue intr-vector mapping */
408 if ((rte_intr_cap_multiple(intr_handle) ||
409 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
410 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
411 intr_vector = bp->eth_dev->data->nb_rx_queues;
412 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
413 if (intr_vector > bp->rx_cp_nr_rings) {
414 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
418 rc = rte_intr_efd_enable(intr_handle, intr_vector);
423 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
424 intr_handle->intr_vec =
425 rte_zmalloc("intr_vec",
426 bp->eth_dev->data->nb_rx_queues *
428 if (intr_handle->intr_vec == NULL) {
429 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
430 " intr_vec", bp->eth_dev->data->nb_rx_queues);
434 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
435 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
436 intr_handle->intr_vec, intr_handle->nb_efd,
437 intr_handle->max_intr);
438 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
440 intr_handle->intr_vec[queue_id] =
441 vec + BNXT_RX_VEC_START;
442 if (vec < base + intr_handle->nb_efd - 1)
447 /* enable uio/vfio intr/eventfd mapping */
448 rc = rte_intr_enable(intr_handle);
449 #ifndef RTE_EXEC_ENV_FREEBSD
450 /* In FreeBSD OS, nic_uio driver does not support interrupts */
455 rc = bnxt_get_hwrm_link_config(bp, &new);
457 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
461 if (!bp->link_info.link_up) {
462 rc = bnxt_set_hwrm_link_config(bp, true);
465 "HWRM link config failure rc: %x\n", rc);
469 bnxt_print_link_info(bp->eth_dev);
471 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
473 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
478 rte_free(intr_handle->intr_vec);
480 rte_intr_efd_disable(intr_handle);
482 /* Some of the error status returned by FW may not be from errno.h */
489 static int bnxt_shutdown_nic(struct bnxt *bp)
491 bnxt_free_all_hwrm_resources(bp);
492 bnxt_free_all_filters(bp);
493 bnxt_free_all_vnics(bp);
498 * Device configuration and status function
501 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
502 struct rte_eth_dev_info *dev_info)
504 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
505 struct bnxt *bp = eth_dev->data->dev_private;
506 uint16_t max_vnics, i, j, vpool, vrxq;
507 unsigned int max_rx_rings;
510 rc = is_bnxt_in_error(bp);
515 dev_info->max_mac_addrs = bp->max_l2_ctx;
516 dev_info->max_hash_mac_addrs = 0;
518 /* PF/VF specifics */
520 dev_info->max_vfs = pdev->max_vfs;
522 max_rx_rings = BNXT_MAX_RINGS(bp);
523 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
524 dev_info->max_rx_queues = max_rx_rings;
525 dev_info->max_tx_queues = max_rx_rings;
526 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
527 dev_info->hash_key_size = 40;
528 max_vnics = bp->max_vnics;
531 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
532 dev_info->max_mtu = BNXT_MAX_MTU;
534 /* Fast path specifics */
535 dev_info->min_rx_bufsize = 1;
536 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
538 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
539 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
540 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
541 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
542 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
545 dev_info->default_rxconf = (struct rte_eth_rxconf) {
551 .rx_free_thresh = 32,
552 /* If no descriptors available, pkts are dropped by default */
556 dev_info->default_txconf = (struct rte_eth_txconf) {
562 .tx_free_thresh = 32,
565 eth_dev->data->dev_conf.intr_conf.lsc = 1;
567 eth_dev->data->dev_conf.intr_conf.rxq = 1;
568 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
569 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
570 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
571 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
576 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
577 * need further investigation.
581 vpool = 64; /* ETH_64_POOLS */
582 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
583 for (i = 0; i < 4; vpool >>= 1, i++) {
584 if (max_vnics > vpool) {
585 for (j = 0; j < 5; vrxq >>= 1, j++) {
586 if (dev_info->max_rx_queues > vrxq) {
592 /* Not enough resources to support VMDq */
596 /* Not enough resources to support VMDq */
600 dev_info->max_vmdq_pools = vpool;
601 dev_info->vmdq_queue_num = vrxq;
603 dev_info->vmdq_pool_base = 0;
604 dev_info->vmdq_queue_base = 0;
609 /* Configure the device based on the configuration provided */
610 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
612 struct bnxt *bp = eth_dev->data->dev_private;
613 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
616 bp->rx_queues = (void *)eth_dev->data->rx_queues;
617 bp->tx_queues = (void *)eth_dev->data->tx_queues;
618 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
619 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
621 rc = is_bnxt_in_error(bp);
625 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
626 rc = bnxt_hwrm_check_vf_rings(bp);
628 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
632 /* If a resource has already been allocated - in this case
633 * it is the async completion ring, free it. Reallocate it after
634 * resource reservation. This will ensure the resource counts
635 * are calculated correctly.
638 pthread_mutex_lock(&bp->def_cp_lock);
640 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
641 bnxt_disable_int(bp);
642 bnxt_free_cp_ring(bp, bp->async_cp_ring);
645 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
647 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
648 pthread_mutex_unlock(&bp->def_cp_lock);
652 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
653 rc = bnxt_alloc_async_cp_ring(bp);
655 pthread_mutex_unlock(&bp->def_cp_lock);
661 pthread_mutex_unlock(&bp->def_cp_lock);
663 /* legacy driver needs to get updated values */
664 rc = bnxt_hwrm_func_qcaps(bp);
666 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc);
671 /* Inherit new configurations */
672 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
673 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
674 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
675 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
676 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
680 if (BNXT_HAS_RING_GRPS(bp) &&
681 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
684 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
685 bp->max_vnics < eth_dev->data->nb_rx_queues)
688 bp->rx_cp_nr_rings = bp->rx_nr_rings;
689 bp->tx_cp_nr_rings = bp->tx_nr_rings;
691 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
692 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
693 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
695 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
697 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
698 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
700 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
706 "Insufficient resources to support requested config\n");
708 "Num Queues Requested: Tx %d, Rx %d\n",
709 eth_dev->data->nb_tx_queues,
710 eth_dev->data->nb_rx_queues);
712 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
713 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
714 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
718 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
720 struct rte_eth_link *link = ð_dev->data->dev_link;
722 if (link->link_status)
723 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
724 eth_dev->data->port_id,
725 (uint32_t)link->link_speed,
726 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
727 ("full-duplex") : ("half-duplex\n"));
729 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
730 eth_dev->data->port_id);
734 * Determine whether the current configuration requires support for scattered
735 * receive; return 1 if scattered receive is required and 0 if not.
737 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
742 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
745 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
746 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
748 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
749 RTE_PKTMBUF_HEADROOM);
750 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
756 static eth_rx_burst_t
757 bnxt_receive_function(struct rte_eth_dev *eth_dev)
759 struct bnxt *bp = eth_dev->data->dev_private;
762 #ifndef RTE_LIBRTE_IEEE1588
764 * Vector mode receive can be enabled only if scatter rx is not
765 * in use and rx offloads are limited to VLAN stripping and
768 if (!eth_dev->data->scattered_rx &&
769 !(eth_dev->data->dev_conf.rxmode.offloads &
770 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
771 DEV_RX_OFFLOAD_KEEP_CRC |
772 DEV_RX_OFFLOAD_JUMBO_FRAME |
773 DEV_RX_OFFLOAD_IPV4_CKSUM |
774 DEV_RX_OFFLOAD_UDP_CKSUM |
775 DEV_RX_OFFLOAD_TCP_CKSUM |
776 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
777 DEV_RX_OFFLOAD_RSS_HASH |
778 DEV_RX_OFFLOAD_VLAN_FILTER))) {
779 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
780 eth_dev->data->port_id);
781 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
782 return bnxt_recv_pkts_vec;
784 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
785 eth_dev->data->port_id);
787 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
788 eth_dev->data->port_id,
789 eth_dev->data->scattered_rx,
790 eth_dev->data->dev_conf.rxmode.offloads);
793 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
794 return bnxt_recv_pkts;
797 static eth_tx_burst_t
798 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
801 #ifndef RTE_LIBRTE_IEEE1588
803 * Vector mode transmit can be enabled only if not using scatter rx
806 if (!eth_dev->data->scattered_rx &&
807 !eth_dev->data->dev_conf.txmode.offloads) {
808 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
809 eth_dev->data->port_id);
810 return bnxt_xmit_pkts_vec;
812 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
813 eth_dev->data->port_id);
815 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
816 eth_dev->data->port_id,
817 eth_dev->data->scattered_rx,
818 eth_dev->data->dev_conf.txmode.offloads);
821 return bnxt_xmit_pkts;
824 static int bnxt_handle_if_change_status(struct bnxt *bp)
828 /* Since fw has undergone a reset and lost all contexts,
829 * set fatal flag to not issue hwrm during cleanup
831 bp->flags |= BNXT_FLAG_FATAL_ERROR;
832 bnxt_uninit_resources(bp, true);
834 /* clear fatal flag so that re-init happens */
835 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
836 rc = bnxt_init_resources(bp, true);
838 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
843 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
845 struct bnxt *bp = eth_dev->data->dev_private;
846 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
850 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
851 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
855 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
857 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
858 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
861 rc = bnxt_hwrm_if_change(bp, 1);
863 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
864 rc = bnxt_handle_if_change_status(bp);
871 rc = bnxt_init_chip(bp);
875 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
876 eth_dev->data->dev_started = 1;
878 bnxt_link_update(eth_dev, 1, ETH_LINK_UP);
880 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
881 vlan_mask |= ETH_VLAN_FILTER_MASK;
882 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
883 vlan_mask |= ETH_VLAN_STRIP_MASK;
884 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
888 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
889 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
891 pthread_mutex_lock(&bp->def_cp_lock);
892 bnxt_schedule_fw_health_check(bp);
893 pthread_mutex_unlock(&bp->def_cp_lock);
897 bnxt_hwrm_if_change(bp, 0);
898 bnxt_shutdown_nic(bp);
899 bnxt_free_tx_mbufs(bp);
900 bnxt_free_rx_mbufs(bp);
901 eth_dev->data->dev_started = 0;
905 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
907 struct bnxt *bp = eth_dev->data->dev_private;
910 if (!bp->link_info.link_up)
911 rc = bnxt_set_hwrm_link_config(bp, true);
913 eth_dev->data->dev_link.link_status = 1;
915 bnxt_print_link_info(eth_dev);
919 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
921 struct bnxt *bp = eth_dev->data->dev_private;
923 eth_dev->data->dev_link.link_status = 0;
924 bnxt_set_hwrm_link_config(bp, false);
925 bp->link_info.link_up = 0;
930 /* Unload the driver, release resources */
931 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
933 struct bnxt *bp = eth_dev->data->dev_private;
934 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
935 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
937 eth_dev->data->dev_started = 0;
938 /* Prevent crashes when queues are still in use */
939 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
940 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
942 bnxt_disable_int(bp);
944 /* disable uio/vfio intr/eventfd mapping */
945 rte_intr_disable(intr_handle);
947 bnxt_cancel_fw_health_check(bp);
949 bnxt_dev_set_link_down_op(eth_dev);
951 /* Wait for link to be reset and the async notification to process.
952 * During reset recovery, there is no need to wait and
953 * VF/NPAR functions do not have privilege to change PHY config.
955 if (!is_bnxt_in_error(bp) && BNXT_SINGLE_PF(bp))
956 bnxt_link_update(eth_dev, 1, ETH_LINK_DOWN);
958 /* Clean queue intr-vector mapping */
959 rte_intr_efd_disable(intr_handle);
960 if (intr_handle->intr_vec != NULL) {
961 rte_free(intr_handle->intr_vec);
962 intr_handle->intr_vec = NULL;
965 bnxt_hwrm_port_clr_stats(bp);
966 bnxt_free_tx_mbufs(bp);
967 bnxt_free_rx_mbufs(bp);
968 /* Process any remaining notifications in default completion queue */
969 bnxt_int_handler(eth_dev);
970 bnxt_shutdown_nic(bp);
971 bnxt_hwrm_if_change(bp, 0);
973 rte_free(bp->mark_table);
974 bp->mark_table = NULL;
976 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
980 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
982 struct bnxt *bp = eth_dev->data->dev_private;
984 /* cancel the recovery handler before remove dev */
985 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
986 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
988 if (eth_dev->data->dev_started)
989 bnxt_dev_stop_op(eth_dev);
991 bnxt_uninit_resources(bp, false);
993 eth_dev->dev_ops = NULL;
994 eth_dev->rx_pkt_burst = NULL;
995 eth_dev->tx_pkt_burst = NULL;
997 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
998 bp->tx_mem_zone = NULL;
999 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1000 bp->rx_mem_zone = NULL;
1002 rte_free(bp->pf.vf_info);
1003 bp->pf.vf_info = NULL;
1005 rte_free(bp->grp_info);
1006 bp->grp_info = NULL;
1009 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1012 struct bnxt *bp = eth_dev->data->dev_private;
1013 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1014 struct bnxt_vnic_info *vnic;
1015 struct bnxt_filter_info *filter, *temp_filter;
1018 if (is_bnxt_in_error(bp))
1022 * Loop through all VNICs from the specified filter flow pools to
1023 * remove the corresponding MAC addr filter
1025 for (i = 0; i < bp->nr_vnics; i++) {
1026 if (!(pool_mask & (1ULL << i)))
1029 vnic = &bp->vnic_info[i];
1030 filter = STAILQ_FIRST(&vnic->filter);
1032 temp_filter = STAILQ_NEXT(filter, next);
1033 if (filter->mac_index == index) {
1034 STAILQ_REMOVE(&vnic->filter, filter,
1035 bnxt_filter_info, next);
1036 bnxt_hwrm_clear_l2_filter(bp, filter);
1037 bnxt_free_filter(bp, filter);
1039 filter = temp_filter;
1044 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1045 struct rte_ether_addr *mac_addr, uint32_t index,
1048 struct bnxt_filter_info *filter;
1051 /* Attach requested MAC address to the new l2_filter */
1052 STAILQ_FOREACH(filter, &vnic->filter, next) {
1053 if (filter->mac_index == index) {
1055 "MAC addr already existed for pool %d\n",
1061 filter = bnxt_alloc_filter(bp);
1063 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1067 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1068 * if the MAC that's been programmed now is a different one, then,
1069 * copy that addr to filter->l2_addr
1072 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1073 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1075 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1077 filter->mac_index = index;
1078 if (filter->mac_index == 0)
1079 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1081 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1083 bnxt_free_filter(bp, filter);
1089 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1090 struct rte_ether_addr *mac_addr,
1091 uint32_t index, uint32_t pool)
1093 struct bnxt *bp = eth_dev->data->dev_private;
1094 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1097 rc = is_bnxt_in_error(bp);
1101 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) {
1102 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1107 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1111 /* Filter settings will get applied when port is started */
1112 if (!eth_dev->data->dev_started)
1115 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1120 int bnxt_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete,
1121 bool exp_link_status)
1124 struct bnxt *bp = eth_dev->data->dev_private;
1125 struct rte_eth_link new;
1126 int cnt = exp_link_status ? BNXT_LINK_UP_WAIT_CNT :
1127 BNXT_LINK_DOWN_WAIT_CNT;
1129 rc = is_bnxt_in_error(bp);
1133 memset(&new, 0, sizeof(new));
1135 /* Retrieve link info from hardware */
1136 rc = bnxt_get_hwrm_link_config(bp, &new);
1138 new.link_speed = ETH_LINK_SPEED_100M;
1139 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1141 "Failed to retrieve link rc = 0x%x!\n", rc);
1145 if (!wait_to_complete || new.link_status == exp_link_status)
1148 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1152 /* Timed out or success */
1153 if (new.link_status != eth_dev->data->dev_link.link_status ||
1154 new.link_speed != eth_dev->data->dev_link.link_speed) {
1155 rte_eth_linkstatus_set(eth_dev, &new);
1157 _rte_eth_dev_callback_process(eth_dev,
1158 RTE_ETH_EVENT_INTR_LSC,
1161 bnxt_print_link_info(eth_dev);
1167 static int bnxt_link_update_op(struct rte_eth_dev *eth_dev,
1168 int wait_to_complete)
1170 return bnxt_link_update(eth_dev, wait_to_complete, ETH_LINK_UP);
1173 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1175 struct bnxt *bp = eth_dev->data->dev_private;
1176 struct bnxt_vnic_info *vnic;
1180 rc = is_bnxt_in_error(bp);
1184 /* Filter settings will get applied when port is started */
1185 if (!eth_dev->data->dev_started)
1188 if (bp->vnic_info == NULL)
1191 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1193 old_flags = vnic->flags;
1194 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1195 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1197 vnic->flags = old_flags;
1202 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1204 struct bnxt *bp = eth_dev->data->dev_private;
1205 struct bnxt_vnic_info *vnic;
1209 rc = is_bnxt_in_error(bp);
1213 /* Filter settings will get applied when port is started */
1214 if (!eth_dev->data->dev_started)
1217 if (bp->vnic_info == NULL)
1220 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1222 old_flags = vnic->flags;
1223 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1224 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1226 vnic->flags = old_flags;
1231 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1233 struct bnxt *bp = eth_dev->data->dev_private;
1234 struct bnxt_vnic_info *vnic;
1238 rc = is_bnxt_in_error(bp);
1242 /* Filter settings will get applied when port is started */
1243 if (!eth_dev->data->dev_started)
1246 if (bp->vnic_info == NULL)
1249 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1251 old_flags = vnic->flags;
1252 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1253 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1255 vnic->flags = old_flags;
1260 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1262 struct bnxt *bp = eth_dev->data->dev_private;
1263 struct bnxt_vnic_info *vnic;
1267 rc = is_bnxt_in_error(bp);
1271 /* Filter settings will get applied when port is started */
1272 if (!eth_dev->data->dev_started)
1275 if (bp->vnic_info == NULL)
1278 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1280 old_flags = vnic->flags;
1281 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1282 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1284 vnic->flags = old_flags;
1289 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1290 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1292 if (qid >= bp->rx_nr_rings)
1295 return bp->eth_dev->data->rx_queues[qid];
1298 /* Return rxq corresponding to a given rss table ring/group ID. */
1299 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1301 struct bnxt_rx_queue *rxq;
1304 if (!BNXT_HAS_RING_GRPS(bp)) {
1305 for (i = 0; i < bp->rx_nr_rings; i++) {
1306 rxq = bp->eth_dev->data->rx_queues[i];
1307 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1311 for (i = 0; i < bp->rx_nr_rings; i++) {
1312 if (bp->grp_info[i].fw_grp_id == fwr)
1317 return INVALID_HW_RING_ID;
1320 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1321 struct rte_eth_rss_reta_entry64 *reta_conf,
1324 struct bnxt *bp = eth_dev->data->dev_private;
1325 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1326 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1327 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1331 rc = is_bnxt_in_error(bp);
1335 if (!vnic->rss_table)
1338 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1341 if (reta_size != tbl_size) {
1342 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1343 "(%d) must equal the size supported by the hardware "
1344 "(%d)\n", reta_size, tbl_size);
1348 for (i = 0; i < reta_size; i++) {
1349 struct bnxt_rx_queue *rxq;
1351 idx = i / RTE_RETA_GROUP_SIZE;
1352 sft = i % RTE_RETA_GROUP_SIZE;
1354 if (!(reta_conf[idx].mask & (1ULL << sft)))
1357 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1359 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1363 if (BNXT_CHIP_THOR(bp)) {
1364 vnic->rss_table[i * 2] =
1365 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1366 vnic->rss_table[i * 2 + 1] =
1367 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1369 vnic->rss_table[i] =
1370 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1374 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1378 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1379 struct rte_eth_rss_reta_entry64 *reta_conf,
1382 struct bnxt *bp = eth_dev->data->dev_private;
1383 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1384 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1385 uint16_t idx, sft, i;
1388 rc = is_bnxt_in_error(bp);
1392 /* Retrieve from the default VNIC */
1395 if (!vnic->rss_table)
1398 if (reta_size != tbl_size) {
1399 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1400 "(%d) must equal the size supported by the hardware "
1401 "(%d)\n", reta_size, tbl_size);
1405 for (idx = 0, i = 0; i < reta_size; i++) {
1406 idx = i / RTE_RETA_GROUP_SIZE;
1407 sft = i % RTE_RETA_GROUP_SIZE;
1409 if (reta_conf[idx].mask & (1ULL << sft)) {
1412 if (BNXT_CHIP_THOR(bp))
1413 qid = bnxt_rss_to_qid(bp,
1414 vnic->rss_table[i * 2]);
1416 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1418 if (qid == INVALID_HW_RING_ID) {
1419 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1422 reta_conf[idx].reta[sft] = qid;
1429 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1430 struct rte_eth_rss_conf *rss_conf)
1432 struct bnxt *bp = eth_dev->data->dev_private;
1433 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1434 struct bnxt_vnic_info *vnic;
1437 rc = is_bnxt_in_error(bp);
1442 * If RSS enablement were different than dev_configure,
1443 * then return -EINVAL
1445 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1446 if (!rss_conf->rss_hf)
1447 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1449 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1453 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1454 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
1456 /* Update the default RSS VNIC(s) */
1457 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1458 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1461 * If hashkey is not specified, use the previously configured
1464 if (!rss_conf->rss_key)
1467 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1469 "Invalid hashkey length, should be 16 bytes\n");
1472 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1475 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1479 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
1480 struct rte_eth_rss_conf *rss_conf)
1482 struct bnxt *bp = eth_dev->data->dev_private;
1483 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1485 uint32_t hash_types;
1487 rc = is_bnxt_in_error(bp);
1491 /* RSS configuration is the same for all VNICs */
1492 if (vnic && vnic->rss_hash_key) {
1493 if (rss_conf->rss_key) {
1494 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
1495 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
1496 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
1499 hash_types = vnic->hash_type;
1500 rss_conf->rss_hf = 0;
1501 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
1502 rss_conf->rss_hf |= ETH_RSS_IPV4;
1503 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
1505 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
1506 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1508 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
1510 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
1511 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
1513 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
1515 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1516 rss_conf->rss_hf |= ETH_RSS_IPV6;
1517 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1519 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1520 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1522 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1524 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1525 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1527 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1531 "Unknwon RSS config from firmware (%08x), RSS disabled",
1536 rss_conf->rss_hf = 0;
1541 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1542 struct rte_eth_fc_conf *fc_conf)
1544 struct bnxt *bp = dev->data->dev_private;
1545 struct rte_eth_link link_info;
1548 rc = is_bnxt_in_error(bp);
1552 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1556 memset(fc_conf, 0, sizeof(*fc_conf));
1557 if (bp->link_info.auto_pause)
1558 fc_conf->autoneg = 1;
1559 switch (bp->link_info.pause) {
1561 fc_conf->mode = RTE_FC_NONE;
1563 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1564 fc_conf->mode = RTE_FC_TX_PAUSE;
1566 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1567 fc_conf->mode = RTE_FC_RX_PAUSE;
1569 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1570 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1571 fc_conf->mode = RTE_FC_FULL;
1577 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1578 struct rte_eth_fc_conf *fc_conf)
1580 struct bnxt *bp = dev->data->dev_private;
1583 rc = is_bnxt_in_error(bp);
1587 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1588 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1592 switch (fc_conf->mode) {
1594 bp->link_info.auto_pause = 0;
1595 bp->link_info.force_pause = 0;
1597 case RTE_FC_RX_PAUSE:
1598 if (fc_conf->autoneg) {
1599 bp->link_info.auto_pause =
1600 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1601 bp->link_info.force_pause = 0;
1603 bp->link_info.auto_pause = 0;
1604 bp->link_info.force_pause =
1605 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1608 case RTE_FC_TX_PAUSE:
1609 if (fc_conf->autoneg) {
1610 bp->link_info.auto_pause =
1611 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1612 bp->link_info.force_pause = 0;
1614 bp->link_info.auto_pause = 0;
1615 bp->link_info.force_pause =
1616 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1620 if (fc_conf->autoneg) {
1621 bp->link_info.auto_pause =
1622 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1623 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1624 bp->link_info.force_pause = 0;
1626 bp->link_info.auto_pause = 0;
1627 bp->link_info.force_pause =
1628 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1629 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1633 return bnxt_set_hwrm_link_config(bp, true);
1636 /* Add UDP tunneling port */
1638 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1639 struct rte_eth_udp_tunnel *udp_tunnel)
1641 struct bnxt *bp = eth_dev->data->dev_private;
1642 uint16_t tunnel_type = 0;
1645 rc = is_bnxt_in_error(bp);
1649 switch (udp_tunnel->prot_type) {
1650 case RTE_TUNNEL_TYPE_VXLAN:
1651 if (bp->vxlan_port_cnt) {
1652 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1653 udp_tunnel->udp_port);
1654 if (bp->vxlan_port != udp_tunnel->udp_port) {
1655 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1658 bp->vxlan_port_cnt++;
1662 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1663 bp->vxlan_port_cnt++;
1665 case RTE_TUNNEL_TYPE_GENEVE:
1666 if (bp->geneve_port_cnt) {
1667 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1668 udp_tunnel->udp_port);
1669 if (bp->geneve_port != udp_tunnel->udp_port) {
1670 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1673 bp->geneve_port_cnt++;
1677 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1678 bp->geneve_port_cnt++;
1681 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1684 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1690 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1691 struct rte_eth_udp_tunnel *udp_tunnel)
1693 struct bnxt *bp = eth_dev->data->dev_private;
1694 uint16_t tunnel_type = 0;
1698 rc = is_bnxt_in_error(bp);
1702 switch (udp_tunnel->prot_type) {
1703 case RTE_TUNNEL_TYPE_VXLAN:
1704 if (!bp->vxlan_port_cnt) {
1705 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1708 if (bp->vxlan_port != udp_tunnel->udp_port) {
1709 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1710 udp_tunnel->udp_port, bp->vxlan_port);
1713 if (--bp->vxlan_port_cnt)
1717 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1718 port = bp->vxlan_fw_dst_port_id;
1720 case RTE_TUNNEL_TYPE_GENEVE:
1721 if (!bp->geneve_port_cnt) {
1722 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1725 if (bp->geneve_port != udp_tunnel->udp_port) {
1726 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1727 udp_tunnel->udp_port, bp->geneve_port);
1730 if (--bp->geneve_port_cnt)
1734 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1735 port = bp->geneve_fw_dst_port_id;
1738 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1742 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1745 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1748 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1749 bp->geneve_port = 0;
1754 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1756 struct bnxt_filter_info *filter;
1757 struct bnxt_vnic_info *vnic;
1759 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1761 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1762 filter = STAILQ_FIRST(&vnic->filter);
1764 /* Search for this matching MAC+VLAN filter */
1765 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
1766 /* Delete the filter */
1767 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1770 STAILQ_REMOVE(&vnic->filter, filter,
1771 bnxt_filter_info, next);
1772 bnxt_free_filter(bp, filter);
1774 "Deleted vlan filter for %d\n",
1778 filter = STAILQ_NEXT(filter, next);
1783 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1785 struct bnxt_filter_info *filter;
1786 struct bnxt_vnic_info *vnic;
1788 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
1789 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
1790 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
1792 /* Implementation notes on the use of VNIC in this command:
1794 * By default, these filters belong to default vnic for the function.
1795 * Once these filters are set up, only destination VNIC can be modified.
1796 * If the destination VNIC is not specified in this command,
1797 * then the HWRM shall only create an l2 context id.
1800 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1801 filter = STAILQ_FIRST(&vnic->filter);
1802 /* Check if the VLAN has already been added */
1804 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
1807 filter = STAILQ_NEXT(filter, next);
1810 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
1811 * command to create MAC+VLAN filter with the right flags, enables set.
1813 filter = bnxt_alloc_filter(bp);
1816 "MAC/VLAN filter alloc failed\n");
1819 /* MAC + VLAN ID filter */
1820 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
1821 * untagged packets are received
1823 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
1824 * packets and only the programmed vlan's packets are received
1826 filter->l2_ivlan = vlan_id;
1827 filter->l2_ivlan_mask = 0x0FFF;
1828 filter->enables |= en;
1829 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1831 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1833 /* Free the newly allocated filter as we were
1834 * not able to create the filter in hardware.
1836 bnxt_free_filter(bp, filter);
1840 filter->mac_index = 0;
1841 /* Add this new filter to the list */
1843 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1845 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1848 "Added Vlan filter for %d\n", vlan_id);
1852 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1853 uint16_t vlan_id, int on)
1855 struct bnxt *bp = eth_dev->data->dev_private;
1858 rc = is_bnxt_in_error(bp);
1862 /* These operations apply to ALL existing MAC/VLAN filters */
1864 return bnxt_add_vlan_filter(bp, vlan_id);
1866 return bnxt_del_vlan_filter(bp, vlan_id);
1869 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
1870 struct bnxt_vnic_info *vnic)
1872 struct bnxt_filter_info *filter;
1875 filter = STAILQ_FIRST(&vnic->filter);
1877 if (filter->mac_index == 0 &&
1878 !memcmp(filter->l2_addr, bp->mac_addr,
1879 RTE_ETHER_ADDR_LEN)) {
1880 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1882 STAILQ_REMOVE(&vnic->filter, filter,
1883 bnxt_filter_info, next);
1884 bnxt_free_filter(bp, filter);
1888 filter = STAILQ_NEXT(filter, next);
1894 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
1896 struct bnxt_vnic_info *vnic;
1900 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1901 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1902 /* Remove any VLAN filters programmed */
1903 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1904 bnxt_del_vlan_filter(bp, i);
1906 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1910 /* Default filter will allow packets that match the
1911 * dest mac. So, it has to be deleted, otherwise, we
1912 * will endup receiving vlan packets for which the
1913 * filter is not programmed, when hw-vlan-filter
1914 * configuration is ON
1916 bnxt_del_dflt_mac_filter(bp, vnic);
1917 /* This filter will allow only untagged packets */
1918 bnxt_add_vlan_filter(bp, 0);
1920 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1921 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1926 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
1928 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
1932 /* Destroy vnic filters and vnic */
1933 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1934 DEV_RX_OFFLOAD_VLAN_FILTER) {
1935 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
1936 bnxt_del_vlan_filter(bp, i);
1938 bnxt_del_dflt_mac_filter(bp, vnic);
1940 rc = bnxt_hwrm_vnic_free(bp, vnic);
1944 rte_free(vnic->fw_grp_ids);
1945 vnic->fw_grp_ids = NULL;
1951 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
1953 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1956 /* Destroy, recreate and reconfigure the default vnic */
1957 rc = bnxt_free_one_vnic(bp, 0);
1961 /* default vnic 0 */
1962 rc = bnxt_setup_one_vnic(bp, 0);
1966 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
1967 DEV_RX_OFFLOAD_VLAN_FILTER) {
1968 rc = bnxt_add_vlan_filter(bp, 0);
1971 rc = bnxt_restore_vlan_filters(bp);
1975 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
1980 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1984 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1985 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1991 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1993 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1994 struct bnxt *bp = dev->data->dev_private;
1997 rc = is_bnxt_in_error(bp);
2001 /* Filter settings will get applied when port is started */
2002 if (!dev->data->dev_started)
2005 if (mask & ETH_VLAN_FILTER_MASK) {
2006 /* Enable or disable VLAN filtering */
2007 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2012 if (mask & ETH_VLAN_STRIP_MASK) {
2013 /* Enable or disable VLAN stripping */
2014 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2019 if (mask & ETH_VLAN_EXTEND_MASK) {
2020 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2021 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2023 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2030 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2033 struct bnxt *bp = dev->data->dev_private;
2034 int qinq = dev->data->dev_conf.rxmode.offloads &
2035 DEV_RX_OFFLOAD_VLAN_EXTEND;
2037 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2038 vlan_type != ETH_VLAN_TYPE_OUTER) {
2040 "Unsupported vlan type.");
2045 "QinQ not enabled. Needs to be ON as we can "
2046 "accelerate only outer vlan\n");
2050 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2052 case RTE_ETHER_TYPE_QINQ:
2054 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2056 case RTE_ETHER_TYPE_VLAN:
2058 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2062 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2066 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2070 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2073 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2076 bp->outer_tpid_bd |= tpid;
2077 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2078 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2080 "Can accelerate only outer vlan in QinQ\n");
2088 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2089 struct rte_ether_addr *addr)
2091 struct bnxt *bp = dev->data->dev_private;
2092 /* Default Filter is tied to VNIC 0 */
2093 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2096 rc = is_bnxt_in_error(bp);
2100 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2103 if (rte_is_zero_ether_addr(addr))
2106 /* Filter settings will get applied when port is started */
2107 if (!dev->data->dev_started)
2110 /* Check if the requested MAC is already added */
2111 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2114 /* Destroy filter and re-create it */
2115 bnxt_del_dflt_mac_filter(bp, vnic);
2117 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2118 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2119 /* This filter will allow only untagged packets */
2120 rc = bnxt_add_vlan_filter(bp, 0);
2122 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2125 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2130 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2131 struct rte_ether_addr *mc_addr_set,
2132 uint32_t nb_mc_addr)
2134 struct bnxt *bp = eth_dev->data->dev_private;
2135 char *mc_addr_list = (char *)mc_addr_set;
2136 struct bnxt_vnic_info *vnic;
2137 uint32_t off = 0, i = 0;
2140 rc = is_bnxt_in_error(bp);
2144 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2146 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2147 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2151 /* TODO Check for Duplicate mcast addresses */
2152 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2153 for (i = 0; i < nb_mc_addr; i++) {
2154 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2155 RTE_ETHER_ADDR_LEN);
2156 off += RTE_ETHER_ADDR_LEN;
2159 vnic->mc_addr_cnt = i;
2160 if (vnic->mc_addr_cnt)
2161 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2163 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2166 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2170 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2172 struct bnxt *bp = dev->data->dev_private;
2173 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2174 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2175 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2178 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
2179 fw_major, fw_minor, fw_updt);
2181 ret += 1; /* add the size of '\0' */
2182 if (fw_size < (uint32_t)ret)
2189 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2190 struct rte_eth_rxq_info *qinfo)
2192 struct bnxt *bp = dev->data->dev_private;
2193 struct bnxt_rx_queue *rxq;
2195 if (is_bnxt_in_error(bp))
2198 rxq = dev->data->rx_queues[queue_id];
2200 qinfo->mp = rxq->mb_pool;
2201 qinfo->scattered_rx = dev->data->scattered_rx;
2202 qinfo->nb_desc = rxq->nb_rx_desc;
2204 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2205 qinfo->conf.rx_drop_en = 0;
2206 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2210 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2211 struct rte_eth_txq_info *qinfo)
2213 struct bnxt *bp = dev->data->dev_private;
2214 struct bnxt_tx_queue *txq;
2216 if (is_bnxt_in_error(bp))
2219 txq = dev->data->tx_queues[queue_id];
2221 qinfo->nb_desc = txq->nb_tx_desc;
2223 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2224 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2225 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2227 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2228 qinfo->conf.tx_rs_thresh = 0;
2229 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2232 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2234 struct bnxt *bp = eth_dev->data->dev_private;
2235 uint32_t new_pkt_size;
2239 rc = is_bnxt_in_error(bp);
2243 /* Exit if receive queues are not configured yet */
2244 if (!eth_dev->data->nb_rx_queues)
2247 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2248 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2252 * If vector-mode tx/rx is active, disallow any MTU change that would
2253 * require scattered receive support.
2255 if (eth_dev->data->dev_started &&
2256 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
2257 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
2259 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2261 "MTU change would require scattered rx support. ");
2262 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2267 if (new_mtu > RTE_ETHER_MTU) {
2268 bp->flags |= BNXT_FLAG_JUMBO;
2269 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2270 DEV_RX_OFFLOAD_JUMBO_FRAME;
2272 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2273 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2274 bp->flags &= ~BNXT_FLAG_JUMBO;
2277 /* Is there a change in mtu setting? */
2278 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2281 for (i = 0; i < bp->nr_vnics; i++) {
2282 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2285 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2286 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2290 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2291 size -= RTE_PKTMBUF_HEADROOM;
2293 if (size < new_mtu) {
2294 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2301 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2303 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2309 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2311 struct bnxt *bp = dev->data->dev_private;
2312 uint16_t vlan = bp->vlan;
2315 rc = is_bnxt_in_error(bp);
2319 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2321 "PVID cannot be modified for this function\n");
2324 bp->vlan = on ? pvid : 0;
2326 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2333 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2335 struct bnxt *bp = dev->data->dev_private;
2338 rc = is_bnxt_in_error(bp);
2342 return bnxt_hwrm_port_led_cfg(bp, true);
2346 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2348 struct bnxt *bp = dev->data->dev_private;
2351 rc = is_bnxt_in_error(bp);
2355 return bnxt_hwrm_port_led_cfg(bp, false);
2359 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2361 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2362 uint32_t desc = 0, raw_cons = 0, cons;
2363 struct bnxt_cp_ring_info *cpr;
2364 struct bnxt_rx_queue *rxq;
2365 struct rx_pkt_cmpl *rxcmp;
2368 rc = is_bnxt_in_error(bp);
2372 rxq = dev->data->rx_queues[rx_queue_id];
2374 raw_cons = cpr->cp_raw_cons;
2377 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2378 rte_prefetch0(&cpr->cp_desc_ring[cons]);
2379 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2381 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
2393 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
2395 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
2396 struct bnxt_rx_ring_info *rxr;
2397 struct bnxt_cp_ring_info *cpr;
2398 struct bnxt_sw_rx_bd *rx_buf;
2399 struct rx_pkt_cmpl *rxcmp;
2400 uint32_t cons, cp_cons;
2406 rc = is_bnxt_in_error(rxq->bp);
2413 if (offset >= rxq->nb_rx_desc)
2416 cons = RING_CMP(cpr->cp_ring_struct, offset);
2417 cp_cons = cpr->cp_raw_cons;
2418 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2420 if (cons > cp_cons) {
2421 if (CMPL_VALID(rxcmp, cpr->valid))
2422 return RTE_ETH_RX_DESC_DONE;
2424 if (CMPL_VALID(rxcmp, !cpr->valid))
2425 return RTE_ETH_RX_DESC_DONE;
2427 rx_buf = &rxr->rx_buf_ring[cons];
2428 if (rx_buf->mbuf == NULL)
2429 return RTE_ETH_RX_DESC_UNAVAIL;
2432 return RTE_ETH_RX_DESC_AVAIL;
2436 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
2438 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
2439 struct bnxt_tx_ring_info *txr;
2440 struct bnxt_cp_ring_info *cpr;
2441 struct bnxt_sw_tx_bd *tx_buf;
2442 struct tx_pkt_cmpl *txcmp;
2443 uint32_t cons, cp_cons;
2449 rc = is_bnxt_in_error(txq->bp);
2456 if (offset >= txq->nb_tx_desc)
2459 cons = RING_CMP(cpr->cp_ring_struct, offset);
2460 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2461 cp_cons = cpr->cp_raw_cons;
2463 if (cons > cp_cons) {
2464 if (CMPL_VALID(txcmp, cpr->valid))
2465 return RTE_ETH_TX_DESC_UNAVAIL;
2467 if (CMPL_VALID(txcmp, !cpr->valid))
2468 return RTE_ETH_TX_DESC_UNAVAIL;
2470 tx_buf = &txr->tx_buf_ring[cons];
2471 if (tx_buf->mbuf == NULL)
2472 return RTE_ETH_TX_DESC_DONE;
2474 return RTE_ETH_TX_DESC_FULL;
2477 static struct bnxt_filter_info *
2478 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
2479 struct rte_eth_ethertype_filter *efilter,
2480 struct bnxt_vnic_info *vnic0,
2481 struct bnxt_vnic_info *vnic,
2484 struct bnxt_filter_info *mfilter = NULL;
2488 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 ||
2489 efilter->ether_type == RTE_ETHER_TYPE_IPV6) {
2490 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
2491 " ethertype filter.", efilter->ether_type);
2495 if (efilter->queue >= bp->rx_nr_rings) {
2496 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2501 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2502 vnic = &bp->vnic_info[efilter->queue];
2504 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
2509 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2510 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
2511 if ((!memcmp(efilter->mac_addr.addr_bytes,
2512 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2514 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
2515 mfilter->ethertype == efilter->ether_type)) {
2521 STAILQ_FOREACH(mfilter, &vnic->filter, next)
2522 if ((!memcmp(efilter->mac_addr.addr_bytes,
2523 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) &&
2524 mfilter->ethertype == efilter->ether_type &&
2526 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
2540 bnxt_ethertype_filter(struct rte_eth_dev *dev,
2541 enum rte_filter_op filter_op,
2544 struct bnxt *bp = dev->data->dev_private;
2545 struct rte_eth_ethertype_filter *efilter =
2546 (struct rte_eth_ethertype_filter *)arg;
2547 struct bnxt_filter_info *bfilter, *filter1;
2548 struct bnxt_vnic_info *vnic, *vnic0;
2551 if (filter_op == RTE_ETH_FILTER_NOP)
2555 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2560 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2561 vnic = &bp->vnic_info[efilter->queue];
2563 switch (filter_op) {
2564 case RTE_ETH_FILTER_ADD:
2565 bnxt_match_and_validate_ether_filter(bp, efilter,
2570 bfilter = bnxt_get_unused_filter(bp);
2571 if (bfilter == NULL) {
2573 "Not enough resources for a new filter.\n");
2576 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2577 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
2578 RTE_ETHER_ADDR_LEN);
2579 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
2580 RTE_ETHER_ADDR_LEN);
2581 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2582 bfilter->ethertype = efilter->ether_type;
2583 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2585 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
2586 if (filter1 == NULL) {
2591 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2592 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2594 bfilter->dst_id = vnic->fw_vnic_id;
2596 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
2598 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2601 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2604 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2606 case RTE_ETH_FILTER_DELETE:
2607 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
2609 if (ret == -EEXIST) {
2610 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
2612 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
2614 bnxt_free_filter(bp, filter1);
2615 } else if (ret == 0) {
2616 PMD_DRV_LOG(ERR, "No matching filter found\n");
2620 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2626 bnxt_free_filter(bp, bfilter);
2632 parse_ntuple_filter(struct bnxt *bp,
2633 struct rte_eth_ntuple_filter *nfilter,
2634 struct bnxt_filter_info *bfilter)
2638 if (nfilter->queue >= bp->rx_nr_rings) {
2639 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
2643 switch (nfilter->dst_port_mask) {
2645 bfilter->dst_port_mask = -1;
2646 bfilter->dst_port = nfilter->dst_port;
2647 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
2648 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2651 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
2655 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2656 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2658 switch (nfilter->proto_mask) {
2660 if (nfilter->proto == 17) /* IPPROTO_UDP */
2661 bfilter->ip_protocol = 17;
2662 else if (nfilter->proto == 6) /* IPPROTO_TCP */
2663 bfilter->ip_protocol = 6;
2666 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2669 PMD_DRV_LOG(ERR, "invalid protocol mask.");
2673 switch (nfilter->dst_ip_mask) {
2675 bfilter->dst_ipaddr_mask[0] = -1;
2676 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
2677 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
2678 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2681 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
2685 switch (nfilter->src_ip_mask) {
2687 bfilter->src_ipaddr_mask[0] = -1;
2688 bfilter->src_ipaddr[0] = nfilter->src_ip;
2689 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
2690 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2693 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
2697 switch (nfilter->src_port_mask) {
2699 bfilter->src_port_mask = -1;
2700 bfilter->src_port = nfilter->src_port;
2701 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
2702 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2705 PMD_DRV_LOG(ERR, "invalid src_port mask.");
2709 bfilter->enables = en;
2713 static struct bnxt_filter_info*
2714 bnxt_match_ntuple_filter(struct bnxt *bp,
2715 struct bnxt_filter_info *bfilter,
2716 struct bnxt_vnic_info **mvnic)
2718 struct bnxt_filter_info *mfilter = NULL;
2721 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2722 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2723 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
2724 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
2725 bfilter->src_ipaddr_mask[0] ==
2726 mfilter->src_ipaddr_mask[0] &&
2727 bfilter->src_port == mfilter->src_port &&
2728 bfilter->src_port_mask == mfilter->src_port_mask &&
2729 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2730 bfilter->dst_ipaddr_mask[0] ==
2731 mfilter->dst_ipaddr_mask[0] &&
2732 bfilter->dst_port == mfilter->dst_port &&
2733 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2734 bfilter->flags == mfilter->flags &&
2735 bfilter->enables == mfilter->enables) {
2746 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2747 struct rte_eth_ntuple_filter *nfilter,
2748 enum rte_filter_op filter_op)
2750 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2751 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2754 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2755 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2759 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2760 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2764 bfilter = bnxt_get_unused_filter(bp);
2765 if (bfilter == NULL) {
2767 "Not enough resources for a new filter.\n");
2770 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2774 vnic = &bp->vnic_info[nfilter->queue];
2775 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
2776 filter1 = STAILQ_FIRST(&vnic0->filter);
2777 if (filter1 == NULL) {
2782 bfilter->dst_id = vnic->fw_vnic_id;
2783 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2785 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2786 bfilter->ethertype = 0x800;
2787 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2789 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2791 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2792 bfilter->dst_id == mfilter->dst_id) {
2793 PMD_DRV_LOG(ERR, "filter exists.\n");
2796 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2797 bfilter->dst_id != mfilter->dst_id) {
2798 mfilter->dst_id = vnic->fw_vnic_id;
2799 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2800 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2801 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2802 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2803 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2806 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2807 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2812 if (filter_op == RTE_ETH_FILTER_ADD) {
2813 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2814 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2817 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2819 if (mfilter == NULL) {
2820 /* This should not happen. But for Coverity! */
2824 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2826 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2827 bnxt_free_filter(bp, mfilter);
2828 bnxt_free_filter(bp, bfilter);
2833 bnxt_free_filter(bp, bfilter);
2838 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2839 enum rte_filter_op filter_op,
2842 struct bnxt *bp = dev->data->dev_private;
2845 if (filter_op == RTE_ETH_FILTER_NOP)
2849 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2854 switch (filter_op) {
2855 case RTE_ETH_FILTER_ADD:
2856 ret = bnxt_cfg_ntuple_filter(bp,
2857 (struct rte_eth_ntuple_filter *)arg,
2860 case RTE_ETH_FILTER_DELETE:
2861 ret = bnxt_cfg_ntuple_filter(bp,
2862 (struct rte_eth_ntuple_filter *)arg,
2866 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2874 bnxt_parse_fdir_filter(struct bnxt *bp,
2875 struct rte_eth_fdir_filter *fdir,
2876 struct bnxt_filter_info *filter)
2878 enum rte_fdir_mode fdir_mode =
2879 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2880 struct bnxt_vnic_info *vnic0, *vnic;
2881 struct bnxt_filter_info *filter1;
2885 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2888 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2889 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2891 switch (fdir->input.flow_type) {
2892 case RTE_ETH_FLOW_IPV4:
2893 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2895 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2896 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2897 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2898 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2899 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2900 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2901 filter->ip_addr_type =
2902 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2903 filter->src_ipaddr_mask[0] = 0xffffffff;
2904 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2905 filter->dst_ipaddr_mask[0] = 0xffffffff;
2906 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2907 filter->ethertype = 0x800;
2908 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2910 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2911 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2912 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2913 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2914 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2915 filter->dst_port_mask = 0xffff;
2916 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2917 filter->src_port_mask = 0xffff;
2918 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2919 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2920 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2921 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2922 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2923 filter->ip_protocol = 6;
2924 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2925 filter->ip_addr_type =
2926 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2927 filter->src_ipaddr_mask[0] = 0xffffffff;
2928 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2929 filter->dst_ipaddr_mask[0] = 0xffffffff;
2930 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2931 filter->ethertype = 0x800;
2932 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2934 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2935 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2936 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2937 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2938 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2939 filter->dst_port_mask = 0xffff;
2940 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2941 filter->src_port_mask = 0xffff;
2942 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2943 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2944 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2945 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2946 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2947 filter->ip_protocol = 17;
2948 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2949 filter->ip_addr_type =
2950 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2951 filter->src_ipaddr_mask[0] = 0xffffffff;
2952 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2953 filter->dst_ipaddr_mask[0] = 0xffffffff;
2954 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2955 filter->ethertype = 0x800;
2956 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2958 case RTE_ETH_FLOW_IPV6:
2959 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2961 filter->ip_addr_type =
2962 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2963 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2964 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2965 rte_memcpy(filter->src_ipaddr,
2966 fdir->input.flow.ipv6_flow.src_ip, 16);
2967 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2968 rte_memcpy(filter->dst_ipaddr,
2969 fdir->input.flow.ipv6_flow.dst_ip, 16);
2970 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2971 memset(filter->dst_ipaddr_mask, 0xff, 16);
2972 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2973 memset(filter->src_ipaddr_mask, 0xff, 16);
2974 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2975 filter->ethertype = 0x86dd;
2976 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2978 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2979 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2980 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2981 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2982 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2983 filter->dst_port_mask = 0xffff;
2984 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2985 filter->src_port_mask = 0xffff;
2986 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2987 filter->ip_addr_type =
2988 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2989 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2990 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2991 rte_memcpy(filter->src_ipaddr,
2992 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2993 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2994 rte_memcpy(filter->dst_ipaddr,
2995 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2996 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2997 memset(filter->dst_ipaddr_mask, 0xff, 16);
2998 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2999 memset(filter->src_ipaddr_mask, 0xff, 16);
3000 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3001 filter->ethertype = 0x86dd;
3002 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3004 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
3005 filter->src_port = fdir->input.flow.udp6_flow.src_port;
3006 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
3007 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
3008 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
3009 filter->dst_port_mask = 0xffff;
3010 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
3011 filter->src_port_mask = 0xffff;
3012 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
3013 filter->ip_addr_type =
3014 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
3015 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
3016 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
3017 rte_memcpy(filter->src_ipaddr,
3018 fdir->input.flow.udp6_flow.ip.src_ip, 16);
3019 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
3020 rte_memcpy(filter->dst_ipaddr,
3021 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
3022 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
3023 memset(filter->dst_ipaddr_mask, 0xff, 16);
3024 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
3025 memset(filter->src_ipaddr_mask, 0xff, 16);
3026 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
3027 filter->ethertype = 0x86dd;
3028 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3030 case RTE_ETH_FLOW_L2_PAYLOAD:
3031 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
3032 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
3034 case RTE_ETH_FLOW_VXLAN:
3035 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3037 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3038 filter->tunnel_type =
3039 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
3040 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3042 case RTE_ETH_FLOW_NVGRE:
3043 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3045 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
3046 filter->tunnel_type =
3047 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
3048 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
3050 case RTE_ETH_FLOW_UNKNOWN:
3051 case RTE_ETH_FLOW_RAW:
3052 case RTE_ETH_FLOW_FRAG_IPV4:
3053 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
3054 case RTE_ETH_FLOW_FRAG_IPV6:
3055 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
3056 case RTE_ETH_FLOW_IPV6_EX:
3057 case RTE_ETH_FLOW_IPV6_TCP_EX:
3058 case RTE_ETH_FLOW_IPV6_UDP_EX:
3059 case RTE_ETH_FLOW_GENEVE:
3065 vnic0 = BNXT_GET_DEFAULT_VNIC(bp);
3066 vnic = &bp->vnic_info[fdir->action.rx_queue];
3068 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
3072 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
3073 rte_memcpy(filter->dst_macaddr,
3074 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
3075 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
3078 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
3079 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
3080 filter1 = STAILQ_FIRST(&vnic0->filter);
3081 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
3083 filter->dst_id = vnic->fw_vnic_id;
3084 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++)
3085 if (filter->dst_macaddr[i] == 0x00)
3086 filter1 = STAILQ_FIRST(&vnic0->filter);
3088 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
3091 if (filter1 == NULL)
3094 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
3095 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
3097 filter->enables = en;
3102 static struct bnxt_filter_info *
3103 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
3104 struct bnxt_vnic_info **mvnic)
3106 struct bnxt_filter_info *mf = NULL;
3109 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3110 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3112 STAILQ_FOREACH(mf, &vnic->filter, next) {
3113 if (mf->filter_type == nf->filter_type &&
3114 mf->flags == nf->flags &&
3115 mf->src_port == nf->src_port &&
3116 mf->src_port_mask == nf->src_port_mask &&
3117 mf->dst_port == nf->dst_port &&
3118 mf->dst_port_mask == nf->dst_port_mask &&
3119 mf->ip_protocol == nf->ip_protocol &&
3120 mf->ip_addr_type == nf->ip_addr_type &&
3121 mf->ethertype == nf->ethertype &&
3122 mf->vni == nf->vni &&
3123 mf->tunnel_type == nf->tunnel_type &&
3124 mf->l2_ovlan == nf->l2_ovlan &&
3125 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
3126 mf->l2_ivlan == nf->l2_ivlan &&
3127 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
3128 !memcmp(mf->l2_addr, nf->l2_addr,
3129 RTE_ETHER_ADDR_LEN) &&
3130 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
3131 RTE_ETHER_ADDR_LEN) &&
3132 !memcmp(mf->src_macaddr, nf->src_macaddr,
3133 RTE_ETHER_ADDR_LEN) &&
3134 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
3135 RTE_ETHER_ADDR_LEN) &&
3136 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
3137 sizeof(nf->src_ipaddr)) &&
3138 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
3139 sizeof(nf->src_ipaddr_mask)) &&
3140 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
3141 sizeof(nf->dst_ipaddr)) &&
3142 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
3143 sizeof(nf->dst_ipaddr_mask))) {
3154 bnxt_fdir_filter(struct rte_eth_dev *dev,
3155 enum rte_filter_op filter_op,
3158 struct bnxt *bp = dev->data->dev_private;
3159 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
3160 struct bnxt_filter_info *filter, *match;
3161 struct bnxt_vnic_info *vnic, *mvnic;
3164 if (filter_op == RTE_ETH_FILTER_NOP)
3167 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
3170 switch (filter_op) {
3171 case RTE_ETH_FILTER_ADD:
3172 case RTE_ETH_FILTER_DELETE:
3174 filter = bnxt_get_unused_filter(bp);
3175 if (filter == NULL) {
3177 "Not enough resources for a new flow.\n");
3181 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
3184 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
3186 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
3187 vnic = &bp->vnic_info[0];
3189 vnic = &bp->vnic_info[fdir->action.rx_queue];
3191 match = bnxt_match_fdir(bp, filter, &mvnic);
3192 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
3193 if (match->dst_id == vnic->fw_vnic_id) {
3194 PMD_DRV_LOG(ERR, "Flow already exists.\n");
3198 match->dst_id = vnic->fw_vnic_id;
3199 ret = bnxt_hwrm_set_ntuple_filter(bp,
3202 STAILQ_REMOVE(&mvnic->filter, match,
3203 bnxt_filter_info, next);
3204 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
3206 "Filter with matching pattern exist\n");
3208 "Updated it to new destination q\n");
3212 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
3213 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
3218 if (filter_op == RTE_ETH_FILTER_ADD) {
3219 ret = bnxt_hwrm_set_ntuple_filter(bp,
3224 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
3226 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
3227 STAILQ_REMOVE(&vnic->filter, match,
3228 bnxt_filter_info, next);
3229 bnxt_free_filter(bp, match);
3230 bnxt_free_filter(bp, filter);
3233 case RTE_ETH_FILTER_FLUSH:
3234 for (i = bp->nr_vnics - 1; i >= 0; i--) {
3235 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3237 STAILQ_FOREACH(filter, &vnic->filter, next) {
3238 if (filter->filter_type ==
3239 HWRM_CFA_NTUPLE_FILTER) {
3241 bnxt_hwrm_clear_ntuple_filter(bp,
3243 STAILQ_REMOVE(&vnic->filter, filter,
3244 bnxt_filter_info, next);
3249 case RTE_ETH_FILTER_UPDATE:
3250 case RTE_ETH_FILTER_STATS:
3251 case RTE_ETH_FILTER_INFO:
3252 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
3255 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3262 bnxt_free_filter(bp, filter);
3267 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3268 enum rte_filter_type filter_type,
3269 enum rte_filter_op filter_op, void *arg)
3273 ret = is_bnxt_in_error(dev->data->dev_private);
3277 switch (filter_type) {
3278 case RTE_ETH_FILTER_TUNNEL:
3280 "filter type: %d: To be implemented\n", filter_type);
3282 case RTE_ETH_FILTER_FDIR:
3283 ret = bnxt_fdir_filter(dev, filter_op, arg);
3285 case RTE_ETH_FILTER_NTUPLE:
3286 ret = bnxt_ntuple_filter(dev, filter_op, arg);
3288 case RTE_ETH_FILTER_ETHERTYPE:
3289 ret = bnxt_ethertype_filter(dev, filter_op, arg);
3291 case RTE_ETH_FILTER_GENERIC:
3292 if (filter_op != RTE_ETH_FILTER_GET)
3294 *(const void **)arg = &bnxt_flow_ops;
3298 "Filter type (%d) not supported", filter_type);
3305 static const uint32_t *
3306 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3308 static const uint32_t ptypes[] = {
3309 RTE_PTYPE_L2_ETHER_VLAN,
3310 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3311 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3315 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3316 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3317 RTE_PTYPE_INNER_L4_ICMP,
3318 RTE_PTYPE_INNER_L4_TCP,
3319 RTE_PTYPE_INNER_L4_UDP,
3323 if (!dev->rx_pkt_burst)
3329 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3332 uint32_t reg_base = *reg_arr & 0xfffff000;
3336 for (i = 0; i < count; i++) {
3337 if ((reg_arr[i] & 0xfffff000) != reg_base)
3340 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3341 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3345 static int bnxt_map_ptp_regs(struct bnxt *bp)
3347 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3351 reg_arr = ptp->rx_regs;
3352 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3356 reg_arr = ptp->tx_regs;
3357 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3361 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3362 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3364 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3365 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3370 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3372 rte_write32(0, (uint8_t *)bp->bar0 +
3373 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3374 rte_write32(0, (uint8_t *)bp->bar0 +
3375 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3378 static uint64_t bnxt_cc_read(struct bnxt *bp)
3382 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3383 BNXT_GRCPF_REG_SYNC_TIME));
3384 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3385 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3389 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3391 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3394 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3395 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3396 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3399 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3400 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3401 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3402 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3403 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3404 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3409 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3411 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3412 struct bnxt_pf_info *pf = &bp->pf;
3419 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3420 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3421 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3424 port_id = pf->port_id;
3425 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3426 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3428 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3429 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3430 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3431 /* bnxt_clr_rx_ts(bp); TBD */
3435 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3436 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3437 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3438 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3444 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3447 struct bnxt *bp = dev->data->dev_private;
3448 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3453 ns = rte_timespec_to_ns(ts);
3454 /* Set the timecounters to a new value. */
3461 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3463 struct bnxt *bp = dev->data->dev_private;
3464 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3465 uint64_t ns, systime_cycles = 0;
3471 if (BNXT_CHIP_THOR(bp))
3472 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3475 systime_cycles = bnxt_cc_read(bp);
3477 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3478 *ts = rte_ns_to_timespec(ns);
3483 bnxt_timesync_enable(struct rte_eth_dev *dev)
3485 struct bnxt *bp = dev->data->dev_private;
3486 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3494 ptp->tx_tstamp_en = 1;
3495 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3497 rc = bnxt_hwrm_ptp_cfg(bp);
3501 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3502 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3503 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3505 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3506 ptp->tc.cc_shift = shift;
3507 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3509 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3510 ptp->rx_tstamp_tc.cc_shift = shift;
3511 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3513 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3514 ptp->tx_tstamp_tc.cc_shift = shift;
3515 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3517 if (!BNXT_CHIP_THOR(bp))
3518 bnxt_map_ptp_regs(bp);
3524 bnxt_timesync_disable(struct rte_eth_dev *dev)
3526 struct bnxt *bp = dev->data->dev_private;
3527 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3533 ptp->tx_tstamp_en = 0;
3536 bnxt_hwrm_ptp_cfg(bp);
3538 if (!BNXT_CHIP_THOR(bp))
3539 bnxt_unmap_ptp_regs(bp);
3545 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3546 struct timespec *timestamp,
3547 uint32_t flags __rte_unused)
3549 struct bnxt *bp = dev->data->dev_private;
3550 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3551 uint64_t rx_tstamp_cycles = 0;
3557 if (BNXT_CHIP_THOR(bp))
3558 rx_tstamp_cycles = ptp->rx_timestamp;
3560 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3562 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3563 *timestamp = rte_ns_to_timespec(ns);
3568 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3569 struct timespec *timestamp)
3571 struct bnxt *bp = dev->data->dev_private;
3572 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3573 uint64_t tx_tstamp_cycles = 0;
3580 if (BNXT_CHIP_THOR(bp))
3581 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3584 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3586 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3587 *timestamp = rte_ns_to_timespec(ns);
3593 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3595 struct bnxt *bp = dev->data->dev_private;
3596 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3601 ptp->tc.nsec += delta;
3607 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3609 struct bnxt *bp = dev->data->dev_private;
3611 uint32_t dir_entries;
3612 uint32_t entry_length;
3614 rc = is_bnxt_in_error(bp);
3618 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3619 bp->pdev->addr.domain, bp->pdev->addr.bus,
3620 bp->pdev->addr.devid, bp->pdev->addr.function);
3622 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3626 return dir_entries * entry_length;
3630 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3631 struct rte_dev_eeprom_info *in_eeprom)
3633 struct bnxt *bp = dev->data->dev_private;
3638 rc = is_bnxt_in_error(bp);
3642 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3643 bp->pdev->addr.domain, bp->pdev->addr.bus,
3644 bp->pdev->addr.devid, bp->pdev->addr.function,
3645 in_eeprom->offset, in_eeprom->length);
3647 if (in_eeprom->offset == 0) /* special offset value to get directory */
3648 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3651 index = in_eeprom->offset >> 24;
3652 offset = in_eeprom->offset & 0xffffff;
3655 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3656 in_eeprom->length, in_eeprom->data);
3661 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3664 case BNX_DIR_TYPE_CHIMP_PATCH:
3665 case BNX_DIR_TYPE_BOOTCODE:
3666 case BNX_DIR_TYPE_BOOTCODE_2:
3667 case BNX_DIR_TYPE_APE_FW:
3668 case BNX_DIR_TYPE_APE_PATCH:
3669 case BNX_DIR_TYPE_KONG_FW:
3670 case BNX_DIR_TYPE_KONG_PATCH:
3671 case BNX_DIR_TYPE_BONO_FW:
3672 case BNX_DIR_TYPE_BONO_PATCH:
3680 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3683 case BNX_DIR_TYPE_AVS:
3684 case BNX_DIR_TYPE_EXP_ROM_MBA:
3685 case BNX_DIR_TYPE_PCIE:
3686 case BNX_DIR_TYPE_TSCF_UCODE:
3687 case BNX_DIR_TYPE_EXT_PHY:
3688 case BNX_DIR_TYPE_CCM:
3689 case BNX_DIR_TYPE_ISCSI_BOOT:
3690 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3691 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3699 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3701 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3702 bnxt_dir_type_is_other_exec_format(dir_type);
3706 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3707 struct rte_dev_eeprom_info *in_eeprom)
3709 struct bnxt *bp = dev->data->dev_private;
3710 uint8_t index, dir_op;
3711 uint16_t type, ext, ordinal, attr;
3714 rc = is_bnxt_in_error(bp);
3718 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3719 bp->pdev->addr.domain, bp->pdev->addr.bus,
3720 bp->pdev->addr.devid, bp->pdev->addr.function,
3721 in_eeprom->offset, in_eeprom->length);
3724 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3728 type = in_eeprom->magic >> 16;
3730 if (type == 0xffff) { /* special value for directory operations */
3731 index = in_eeprom->magic & 0xff;
3732 dir_op = in_eeprom->magic >> 8;
3736 case 0x0e: /* erase */
3737 if (in_eeprom->offset != ~in_eeprom->magic)
3739 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3745 /* Create or re-write an NVM item: */
3746 if (bnxt_dir_type_is_executable(type) == true)
3748 ext = in_eeprom->magic & 0xffff;
3749 ordinal = in_eeprom->offset >> 16;
3750 attr = in_eeprom->offset & 0xffff;
3752 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3753 in_eeprom->data, in_eeprom->length);
3760 static const struct eth_dev_ops bnxt_dev_ops = {
3761 .dev_infos_get = bnxt_dev_info_get_op,
3762 .dev_close = bnxt_dev_close_op,
3763 .dev_configure = bnxt_dev_configure_op,
3764 .dev_start = bnxt_dev_start_op,
3765 .dev_stop = bnxt_dev_stop_op,
3766 .dev_set_link_up = bnxt_dev_set_link_up_op,
3767 .dev_set_link_down = bnxt_dev_set_link_down_op,
3768 .stats_get = bnxt_stats_get_op,
3769 .stats_reset = bnxt_stats_reset_op,
3770 .rx_queue_setup = bnxt_rx_queue_setup_op,
3771 .rx_queue_release = bnxt_rx_queue_release_op,
3772 .tx_queue_setup = bnxt_tx_queue_setup_op,
3773 .tx_queue_release = bnxt_tx_queue_release_op,
3774 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3775 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3776 .reta_update = bnxt_reta_update_op,
3777 .reta_query = bnxt_reta_query_op,
3778 .rss_hash_update = bnxt_rss_hash_update_op,
3779 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3780 .link_update = bnxt_link_update_op,
3781 .promiscuous_enable = bnxt_promiscuous_enable_op,
3782 .promiscuous_disable = bnxt_promiscuous_disable_op,
3783 .allmulticast_enable = bnxt_allmulticast_enable_op,
3784 .allmulticast_disable = bnxt_allmulticast_disable_op,
3785 .mac_addr_add = bnxt_mac_addr_add_op,
3786 .mac_addr_remove = bnxt_mac_addr_remove_op,
3787 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3788 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3789 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3790 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3791 .vlan_filter_set = bnxt_vlan_filter_set_op,
3792 .vlan_offload_set = bnxt_vlan_offload_set_op,
3793 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3794 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3795 .mtu_set = bnxt_mtu_set_op,
3796 .mac_addr_set = bnxt_set_default_mac_addr_op,
3797 .xstats_get = bnxt_dev_xstats_get_op,
3798 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3799 .xstats_reset = bnxt_dev_xstats_reset_op,
3800 .fw_version_get = bnxt_fw_version_get,
3801 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3802 .rxq_info_get = bnxt_rxq_info_get_op,
3803 .txq_info_get = bnxt_txq_info_get_op,
3804 .dev_led_on = bnxt_dev_led_on_op,
3805 .dev_led_off = bnxt_dev_led_off_op,
3806 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3807 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3808 .rx_queue_count = bnxt_rx_queue_count_op,
3809 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3810 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3811 .rx_queue_start = bnxt_rx_queue_start,
3812 .rx_queue_stop = bnxt_rx_queue_stop,
3813 .tx_queue_start = bnxt_tx_queue_start,
3814 .tx_queue_stop = bnxt_tx_queue_stop,
3815 .filter_ctrl = bnxt_filter_ctrl_op,
3816 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3817 .get_eeprom_length = bnxt_get_eeprom_length_op,
3818 .get_eeprom = bnxt_get_eeprom_op,
3819 .set_eeprom = bnxt_set_eeprom_op,
3820 .timesync_enable = bnxt_timesync_enable,
3821 .timesync_disable = bnxt_timesync_disable,
3822 .timesync_read_time = bnxt_timesync_read_time,
3823 .timesync_write_time = bnxt_timesync_write_time,
3824 .timesync_adjust_time = bnxt_timesync_adjust_time,
3825 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3826 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3829 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3833 /* Only pre-map the reset GRC registers using window 3 */
3834 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3835 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3837 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3842 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3844 struct bnxt_error_recovery_info *info = bp->recovery_info;
3845 uint32_t reg_base = 0xffffffff;
3848 /* Only pre-map the monitoring GRC registers using window 2 */
3849 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3850 uint32_t reg = info->status_regs[i];
3852 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3855 if (reg_base == 0xffffffff)
3856 reg_base = reg & 0xfffff000;
3857 if ((reg & 0xfffff000) != reg_base)
3860 /* Use mask 0xffc as the Lower 2 bits indicates
3861 * address space location
3863 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3867 if (reg_base == 0xffffffff)
3870 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3871 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3876 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3878 struct bnxt_error_recovery_info *info = bp->recovery_info;
3879 uint32_t delay = info->delay_after_reset[index];
3880 uint32_t val = info->reset_reg_val[index];
3881 uint32_t reg = info->reset_reg[index];
3882 uint32_t type, offset;
3884 type = BNXT_FW_STATUS_REG_TYPE(reg);
3885 offset = BNXT_FW_STATUS_REG_OFF(reg);
3888 case BNXT_FW_STATUS_REG_TYPE_CFG:
3889 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3891 case BNXT_FW_STATUS_REG_TYPE_GRC:
3892 offset = bnxt_map_reset_regs(bp, offset);
3893 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3895 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3896 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3899 /* wait on a specific interval of time until core reset is complete */
3901 rte_delay_ms(delay);
3904 static void bnxt_dev_cleanup(struct bnxt *bp)
3906 bnxt_set_hwrm_link_config(bp, false);
3907 bp->link_info.link_up = 0;
3908 if (bp->eth_dev->data->dev_started)
3909 bnxt_dev_stop_op(bp->eth_dev);
3911 bnxt_uninit_resources(bp, true);
3914 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3916 struct rte_eth_dev *dev = bp->eth_dev;
3917 struct rte_vlan_filter_conf *vfc;
3921 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3922 vfc = &dev->data->vlan_filter_conf;
3923 vidx = vlan_id / 64;
3924 vbit = vlan_id % 64;
3926 /* Each bit corresponds to a VLAN id */
3927 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3928 rc = bnxt_add_vlan_filter(bp, vlan_id);
3937 static int bnxt_restore_mac_filters(struct bnxt *bp)
3939 struct rte_eth_dev *dev = bp->eth_dev;
3940 struct rte_eth_dev_info dev_info;
3941 struct rte_ether_addr *addr;
3947 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp))
3950 rc = bnxt_dev_info_get_op(dev, &dev_info);
3954 /* replay MAC address configuration */
3955 for (i = 1; i < dev_info.max_mac_addrs; i++) {
3956 addr = &dev->data->mac_addrs[i];
3958 /* skip zero address */
3959 if (rte_is_zero_ether_addr(addr))
3963 pool_mask = dev->data->mac_pool_sel[i];
3966 if (pool_mask & 1ULL) {
3967 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3973 } while (pool_mask);
3979 static int bnxt_restore_filters(struct bnxt *bp)
3981 struct rte_eth_dev *dev = bp->eth_dev;
3984 if (dev->data->all_multicast) {
3985 ret = bnxt_allmulticast_enable_op(dev);
3989 if (dev->data->promiscuous) {
3990 ret = bnxt_promiscuous_enable_op(dev);
3995 ret = bnxt_restore_mac_filters(bp);
3999 ret = bnxt_restore_vlan_filters(bp);
4000 /* TODO restore other filters as well */
4004 static void bnxt_dev_recover(void *arg)
4006 struct bnxt *bp = arg;
4007 int timeout = bp->fw_reset_max_msecs;
4010 /* Clear Error flag so that device re-init should happen */
4011 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4014 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
4017 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4018 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4019 } while (rc && timeout);
4022 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4026 rc = bnxt_init_resources(bp, true);
4029 "Failed to initialize resources after reset\n");
4032 /* clear reset flag as the device is initialized now */
4033 bp->flags &= ~BNXT_FLAG_FW_RESET;
4035 rc = bnxt_dev_start_op(bp->eth_dev);
4037 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4041 rc = bnxt_restore_filters(bp);
4045 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4048 bnxt_dev_stop_op(bp->eth_dev);
4050 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4051 bnxt_uninit_resources(bp, false);
4052 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4055 void bnxt_dev_reset_and_resume(void *arg)
4057 struct bnxt *bp = arg;
4060 bnxt_dev_cleanup(bp);
4062 bnxt_wait_for_device_shutdown(bp);
4064 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
4065 bnxt_dev_recover, (void *)bp);
4067 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4070 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4072 struct bnxt_error_recovery_info *info = bp->recovery_info;
4073 uint32_t reg = info->status_regs[index];
4074 uint32_t type, offset, val = 0;
4076 type = BNXT_FW_STATUS_REG_TYPE(reg);
4077 offset = BNXT_FW_STATUS_REG_OFF(reg);
4080 case BNXT_FW_STATUS_REG_TYPE_CFG:
4081 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4083 case BNXT_FW_STATUS_REG_TYPE_GRC:
4084 offset = info->mapped_status_regs[index];
4086 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4087 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4095 static int bnxt_fw_reset_all(struct bnxt *bp)
4097 struct bnxt_error_recovery_info *info = bp->recovery_info;
4101 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4102 /* Reset through master function driver */
4103 for (i = 0; i < info->reg_array_cnt; i++)
4104 bnxt_write_fw_reset_reg(bp, i);
4105 /* Wait for time specified by FW after triggering reset */
4106 rte_delay_ms(info->master_func_wait_period_after_reset);
4107 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4108 /* Reset with the help of Kong processor */
4109 rc = bnxt_hwrm_fw_reset(bp);
4111 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4117 static void bnxt_fw_reset_cb(void *arg)
4119 struct bnxt *bp = arg;
4120 struct bnxt_error_recovery_info *info = bp->recovery_info;
4123 /* Only Master function can do FW reset */
4124 if (bnxt_is_master_func(bp) &&
4125 bnxt_is_recovery_enabled(bp)) {
4126 rc = bnxt_fw_reset_all(bp);
4128 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4133 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4134 * EXCEPTION_FATAL_ASYNC event to all the functions
4135 * (including MASTER FUNC). After receiving this Async, all the active
4136 * drivers should treat this case as FW initiated recovery
4138 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4139 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4140 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4142 /* To recover from error */
4143 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4148 /* Driver should poll FW heartbeat, reset_counter with the frequency
4149 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4150 * When the driver detects heartbeat stop or change in reset_counter,
4151 * it has to trigger a reset to recover from the error condition.
4152 * A “master PF” is the function who will have the privilege to
4153 * initiate the chimp reset. The master PF will be elected by the
4154 * firmware and will be notified through async message.
4156 static void bnxt_check_fw_health(void *arg)
4158 struct bnxt *bp = arg;
4159 struct bnxt_error_recovery_info *info = bp->recovery_info;
4160 uint32_t val = 0, wait_msec;
4162 if (!info || !bnxt_is_recovery_enabled(bp) ||
4163 is_bnxt_in_error(bp))
4166 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4167 if (val == info->last_heart_beat)
4170 info->last_heart_beat = val;
4172 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4173 if (val != info->last_reset_counter)
4176 info->last_reset_counter = val;
4178 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4179 bnxt_check_fw_health, (void *)bp);
4183 /* Stop DMA to/from device */
4184 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4185 bp->flags |= BNXT_FLAG_FW_RESET;
4187 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4189 if (bnxt_is_master_func(bp))
4190 wait_msec = info->master_func_wait_period;
4192 wait_msec = info->normal_func_wait_period;
4194 rte_eal_alarm_set(US_PER_MS * wait_msec,
4195 bnxt_fw_reset_cb, (void *)bp);
4198 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4200 uint32_t polling_freq;
4202 if (!bnxt_is_recovery_enabled(bp))
4205 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4208 polling_freq = bp->recovery_info->driver_polling_freq;
4210 rte_eal_alarm_set(US_PER_MS * polling_freq,
4211 bnxt_check_fw_health, (void *)bp);
4212 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4215 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4217 if (!bnxt_is_recovery_enabled(bp))
4220 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4221 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4224 static bool bnxt_vf_pciid(uint16_t device_id)
4226 switch (device_id) {
4227 case BROADCOM_DEV_ID_57304_VF:
4228 case BROADCOM_DEV_ID_57406_VF:
4229 case BROADCOM_DEV_ID_5731X_VF:
4230 case BROADCOM_DEV_ID_5741X_VF:
4231 case BROADCOM_DEV_ID_57414_VF:
4232 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4233 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4234 case BROADCOM_DEV_ID_58802_VF:
4235 case BROADCOM_DEV_ID_57500_VF1:
4236 case BROADCOM_DEV_ID_57500_VF2:
4244 static bool bnxt_thor_device(uint16_t device_id)
4246 switch (device_id) {
4247 case BROADCOM_DEV_ID_57508:
4248 case BROADCOM_DEV_ID_57504:
4249 case BROADCOM_DEV_ID_57502:
4250 case BROADCOM_DEV_ID_57508_MF1:
4251 case BROADCOM_DEV_ID_57504_MF1:
4252 case BROADCOM_DEV_ID_57502_MF1:
4253 case BROADCOM_DEV_ID_57508_MF2:
4254 case BROADCOM_DEV_ID_57504_MF2:
4255 case BROADCOM_DEV_ID_57502_MF2:
4256 case BROADCOM_DEV_ID_57500_VF1:
4257 case BROADCOM_DEV_ID_57500_VF2:
4265 bool bnxt_stratus_device(struct bnxt *bp)
4267 uint16_t device_id = bp->pdev->id.device_id;
4269 switch (device_id) {
4270 case BROADCOM_DEV_ID_STRATUS_NIC:
4271 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4272 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4280 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
4282 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4283 struct bnxt *bp = eth_dev->data->dev_private;
4285 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4286 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4287 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4288 if (!bp->bar0 || !bp->doorbell_base) {
4289 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4293 bp->eth_dev = eth_dev;
4299 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4300 struct bnxt_ctx_pg_info *ctx_pg,
4305 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4306 const struct rte_memzone *mz = NULL;
4307 char mz_name[RTE_MEMZONE_NAMESIZE];
4308 rte_iova_t mz_phys_addr;
4309 uint64_t valid_bits = 0;
4316 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4318 rmem->page_size = BNXT_PAGE_SIZE;
4319 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4320 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4321 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4323 valid_bits = PTU_PTE_VALID;
4325 if (rmem->nr_pages > 1) {
4326 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4327 "bnxt_ctx_pg_tbl%s_%x_%d",
4328 suffix, idx, bp->eth_dev->data->port_id);
4329 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4330 mz = rte_memzone_lookup(mz_name);
4332 mz = rte_memzone_reserve_aligned(mz_name,
4336 RTE_MEMZONE_SIZE_HINT_ONLY |
4337 RTE_MEMZONE_IOVA_CONTIG,
4343 memset(mz->addr, 0, mz->len);
4344 mz_phys_addr = mz->iova;
4346 rmem->pg_tbl = mz->addr;
4347 rmem->pg_tbl_map = mz_phys_addr;
4348 rmem->pg_tbl_mz = mz;
4351 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4352 suffix, idx, bp->eth_dev->data->port_id);
4353 mz = rte_memzone_lookup(mz_name);
4355 mz = rte_memzone_reserve_aligned(mz_name,
4359 RTE_MEMZONE_SIZE_HINT_ONLY |
4360 RTE_MEMZONE_IOVA_CONTIG,
4366 memset(mz->addr, 0, mz->len);
4367 mz_phys_addr = mz->iova;
4369 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4370 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4371 rmem->dma_arr[i] = mz_phys_addr + sz;
4373 if (rmem->nr_pages > 1) {
4374 if (i == rmem->nr_pages - 2 &&
4375 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4376 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4377 else if (i == rmem->nr_pages - 1 &&
4378 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4379 valid_bits |= PTU_PTE_LAST;
4381 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4387 if (rmem->vmem_size)
4388 rmem->vmem = (void **)mz->addr;
4389 rmem->dma_arr[0] = mz_phys_addr;
4393 static void bnxt_free_ctx_mem(struct bnxt *bp)
4397 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4400 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4401 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4402 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4403 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4404 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4405 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4406 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4407 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4408 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4409 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4410 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4412 for (i = 0; i < BNXT_MAX_Q; i++) {
4413 if (bp->ctx->tqm_mem[i])
4414 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4421 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4423 #define min_t(type, x, y) ({ \
4424 type __min1 = (x); \
4425 type __min2 = (y); \
4426 __min1 < __min2 ? __min1 : __min2; })
4428 #define max_t(type, x, y) ({ \
4429 type __max1 = (x); \
4430 type __max2 = (y); \
4431 __max1 > __max2 ? __max1 : __max2; })
4433 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4435 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4437 struct bnxt_ctx_pg_info *ctx_pg;
4438 struct bnxt_ctx_mem_info *ctx;
4439 uint32_t mem_size, ena, entries;
4442 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4444 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4448 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4451 ctx_pg = &ctx->qp_mem;
4452 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4453 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4454 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4458 ctx_pg = &ctx->srq_mem;
4459 ctx_pg->entries = ctx->srq_max_l2_entries;
4460 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4461 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4465 ctx_pg = &ctx->cq_mem;
4466 ctx_pg->entries = ctx->cq_max_l2_entries;
4467 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4468 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4472 ctx_pg = &ctx->vnic_mem;
4473 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4474 ctx->vnic_max_ring_table_entries;
4475 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4476 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4480 ctx_pg = &ctx->stat_mem;
4481 ctx_pg->entries = ctx->stat_max_entries;
4482 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4483 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4487 entries = ctx->qp_max_l2_entries +
4488 ctx->vnic_max_vnic_entries +
4489 ctx->tqm_min_entries_per_ring;
4490 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4491 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
4492 ctx->tqm_max_entries_per_ring);
4493 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) {
4494 ctx_pg = ctx->tqm_mem[i];
4495 /* use min tqm entries for now. */
4496 ctx_pg->entries = entries;
4497 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4498 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4501 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4504 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4505 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4508 "Failed to configure context mem: rc = %d\n", rc);
4510 ctx->flags |= BNXT_CTX_FLAG_INITED;
4515 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4517 struct rte_pci_device *pci_dev = bp->pdev;
4518 char mz_name[RTE_MEMZONE_NAMESIZE];
4519 const struct rte_memzone *mz = NULL;
4520 uint32_t total_alloc_len;
4521 rte_iova_t mz_phys_addr;
4523 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4526 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4527 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4528 pci_dev->addr.bus, pci_dev->addr.devid,
4529 pci_dev->addr.function, "rx_port_stats");
4530 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4531 mz = rte_memzone_lookup(mz_name);
4533 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4534 sizeof(struct rx_port_stats_ext) + 512);
4536 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4539 RTE_MEMZONE_SIZE_HINT_ONLY |
4540 RTE_MEMZONE_IOVA_CONTIG);
4544 memset(mz->addr, 0, mz->len);
4545 mz_phys_addr = mz->iova;
4547 bp->rx_mem_zone = (const void *)mz;
4548 bp->hw_rx_port_stats = mz->addr;
4549 bp->hw_rx_port_stats_map = mz_phys_addr;
4551 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4552 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4553 pci_dev->addr.bus, pci_dev->addr.devid,
4554 pci_dev->addr.function, "tx_port_stats");
4555 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4556 mz = rte_memzone_lookup(mz_name);
4558 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4559 sizeof(struct tx_port_stats_ext) + 512);
4561 mz = rte_memzone_reserve(mz_name,
4565 RTE_MEMZONE_SIZE_HINT_ONLY |
4566 RTE_MEMZONE_IOVA_CONTIG);
4570 memset(mz->addr, 0, mz->len);
4571 mz_phys_addr = mz->iova;
4573 bp->tx_mem_zone = (const void *)mz;
4574 bp->hw_tx_port_stats = mz->addr;
4575 bp->hw_tx_port_stats_map = mz_phys_addr;
4576 bp->flags |= BNXT_FLAG_PORT_STATS;
4578 /* Display extended statistics if FW supports it */
4579 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4580 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4581 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4584 bp->hw_rx_port_stats_ext = (void *)
4585 ((uint8_t *)bp->hw_rx_port_stats +
4586 sizeof(struct rx_port_stats));
4587 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4588 sizeof(struct rx_port_stats);
4589 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4591 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4592 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4593 bp->hw_tx_port_stats_ext = (void *)
4594 ((uint8_t *)bp->hw_tx_port_stats +
4595 sizeof(struct tx_port_stats));
4596 bp->hw_tx_port_stats_ext_map =
4597 bp->hw_tx_port_stats_map +
4598 sizeof(struct tx_port_stats);
4599 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4605 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4607 struct bnxt *bp = eth_dev->data->dev_private;
4610 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4611 RTE_ETHER_ADDR_LEN *
4614 if (eth_dev->data->mac_addrs == NULL) {
4615 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4619 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) {
4623 /* Generate a random MAC address, if none was assigned by PF */
4624 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4625 bnxt_eth_hw_addr_random(bp->mac_addr);
4627 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4628 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4629 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4631 rc = bnxt_hwrm_set_mac(bp);
4633 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr,
4634 RTE_ETHER_ADDR_LEN);
4638 /* Copy the permanent MAC from the FUNC_QCAPS response */
4639 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN);
4640 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4645 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4649 /* MAC is already configured in FW */
4650 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN))
4653 /* Restore the old MAC configured */
4654 rc = bnxt_hwrm_set_mac(bp);
4656 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4661 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4666 #define ALLOW_FUNC(x) \
4668 uint32_t arg = (x); \
4669 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
4670 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
4673 /* Forward all requests if firmware is new enough */
4674 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
4675 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
4676 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
4677 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
4679 PMD_DRV_LOG(WARNING,
4680 "Firmware too old for VF mailbox functionality\n");
4681 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
4685 * The following are used for driver cleanup. If we disallow these,
4686 * VF drivers can't clean up cleanly.
4688 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
4689 ALLOW_FUNC(HWRM_VNIC_FREE);
4690 ALLOW_FUNC(HWRM_RING_FREE);
4691 ALLOW_FUNC(HWRM_RING_GRP_FREE);
4692 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
4693 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
4694 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
4695 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
4696 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
4699 static int bnxt_init_fw(struct bnxt *bp)
4706 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4710 rc = bnxt_hwrm_func_reset(bp);
4714 rc = bnxt_hwrm_vnic_qcaps(bp);
4718 rc = bnxt_hwrm_queue_qportcfg(bp);
4722 /* Get the MAX capabilities for this function.
4723 * This function also allocates context memory for TQM rings and
4724 * informs the firmware about this allocated backing store memory.
4726 rc = bnxt_hwrm_func_qcaps(bp);
4730 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4734 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4738 /* Get the adapter error recovery support info */
4739 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4741 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4743 bnxt_hwrm_port_led_qcaps(bp);
4749 bnxt_init_locks(struct bnxt *bp)
4753 err = pthread_mutex_init(&bp->flow_lock, NULL);
4755 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4759 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4761 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4765 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4769 rc = bnxt_init_fw(bp);
4773 if (!reconfig_dev) {
4774 rc = bnxt_setup_mac_addr(bp->eth_dev);
4778 rc = bnxt_restore_dflt_mac(bp);
4783 bnxt_config_vf_req_fwd(bp);
4785 rc = bnxt_hwrm_func_driver_register(bp);
4787 PMD_DRV_LOG(ERR, "Failed to register driver");
4792 if (bp->pdev->max_vfs) {
4793 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4795 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4799 rc = bnxt_hwrm_allocate_pf_only(bp);
4802 "Failed to allocate PF resources");
4808 rc = bnxt_alloc_mem(bp, reconfig_dev);
4812 rc = bnxt_setup_int(bp);
4816 rc = bnxt_request_int(bp);
4820 rc = bnxt_init_locks(bp);
4828 bnxt_dev_init(struct rte_eth_dev *eth_dev)
4830 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4831 static int version_printed;
4835 if (version_printed++ == 0)
4836 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
4838 eth_dev->dev_ops = &bnxt_dev_ops;
4839 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
4840 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
4843 * For secondary processes, we don't initialise any further
4844 * as primary has already done this work.
4846 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4849 rte_eth_copy_pci_info(eth_dev, pci_dev);
4851 bp = eth_dev->data->dev_private;
4853 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
4855 if (bnxt_vf_pciid(pci_dev->id.device_id))
4856 bp->flags |= BNXT_FLAG_VF;
4858 if (bnxt_thor_device(pci_dev->id.device_id))
4859 bp->flags |= BNXT_FLAG_THOR_CHIP;
4861 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
4862 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
4863 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
4864 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
4865 bp->flags |= BNXT_FLAG_STINGRAY;
4867 rc = bnxt_init_board(eth_dev);
4870 "Failed to initialize board rc: %x\n", rc);
4874 rc = bnxt_alloc_hwrm_resources(bp);
4877 "Failed to allocate hwrm resource rc: %x\n", rc);
4880 rc = bnxt_init_resources(bp, false);
4884 rc = bnxt_alloc_stats_mem(bp);
4888 /* Pass the information to the rte_eth_dev_close() that it should also
4889 * release the private port resources.
4891 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
4894 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
4895 pci_dev->mem_resource[0].phys_addr,
4896 pci_dev->mem_resource[0].addr);
4901 bnxt_dev_uninit(eth_dev);
4906 bnxt_uninit_locks(struct bnxt *bp)
4908 pthread_mutex_destroy(&bp->flow_lock);
4909 pthread_mutex_destroy(&bp->def_cp_lock);
4913 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
4918 bnxt_free_mem(bp, reconfig_dev);
4919 bnxt_hwrm_func_buf_unrgtr(bp);
4920 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
4921 bp->flags &= ~BNXT_FLAG_REGISTERED;
4922 bnxt_free_ctx_mem(bp);
4923 if (!reconfig_dev) {
4924 bnxt_free_hwrm_resources(bp);
4926 if (bp->recovery_info != NULL) {
4927 rte_free(bp->recovery_info);
4928 bp->recovery_info = NULL;
4932 bnxt_uninit_locks(bp);
4933 rte_free(bp->ptp_cfg);
4939 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
4941 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
4944 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
4946 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
4947 bnxt_dev_close_op(eth_dev);
4952 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4953 struct rte_pci_device *pci_dev)
4955 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
4959 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
4961 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
4962 return rte_eth_dev_pci_generic_remove(pci_dev,
4965 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
4968 static struct rte_pci_driver bnxt_rte_pmd = {
4969 .id_table = bnxt_pci_id_map,
4970 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4971 .probe = bnxt_pci_probe,
4972 .remove = bnxt_pci_remove,
4976 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4978 if (strcmp(dev->device->driver->name, drv->driver.name))
4984 bool is_bnxt_supported(struct rte_eth_dev *dev)
4986 return is_device_supported(dev, &bnxt_rte_pmd);
4989 RTE_INIT(bnxt_init_log)
4991 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver");
4992 if (bnxt_logtype_driver >= 0)
4993 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
4996 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
4997 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
4998 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");