1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2021 Broadcom
10 #include <ethdev_driver.h>
11 #include <ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
19 #include "bnxt_filter.h"
20 #include "bnxt_hwrm.h"
22 #include "bnxt_reps.h"
23 #include "bnxt_ring.h"
26 #include "bnxt_stats.h"
29 #include "bnxt_vnic.h"
30 #include "hsi_struct_def_dpdk.h"
31 #include "bnxt_nvm_defs.h"
32 #include "bnxt_tf_common.h"
33 #include "ulp_flow_db.h"
34 #include "rte_pmd_bnxt.h"
36 #define DRV_MODULE_NAME "bnxt"
37 static const char bnxt_version[] =
38 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
41 * The set of PCI devices this driver supports
43 static const struct rte_pci_id bnxt_pci_id_map[] = {
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
87 { .vendor_id = 0, /* sentinel */ },
90 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
91 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
92 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
93 #define BNXT_DEVARG_REPRESENTOR "representor"
94 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf"
95 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf"
96 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f"
97 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r"
98 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f"
99 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r"
101 static const char *const bnxt_dev_args[] = {
102 BNXT_DEVARG_REPRESENTOR,
104 BNXT_DEVARG_FLOW_XSTAT,
105 BNXT_DEVARG_MAX_NUM_KFLOWS,
106 BNXT_DEVARG_REP_BASED_PF,
107 BNXT_DEVARG_REP_IS_PF,
108 BNXT_DEVARG_REP_Q_R2F,
109 BNXT_DEVARG_REP_Q_F2R,
110 BNXT_DEVARG_REP_FC_R2F,
111 BNXT_DEVARG_REP_FC_F2R,
116 * truflow == false to disable the feature
117 * truflow == true to enable the feature
119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
122 * flow_xstat == false to disable the feature
123 * flow_xstat == true to enable the feature
125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
128 * rep_is_pf == false to indicate VF representor
129 * rep_is_pf == true to indicate PF representor
131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1)
134 * rep_based_pf == Physical index of the PF
136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15)
138 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3)
143 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3)
148 * rep_fc_r2f == Flow control for the representor to endpoint direction
150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1)
153 * rep_fc_f2r == Flow control for the endpoint to representor direction
155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1)
157 int bnxt_cfa_code_dynfield_offset = -1;
160 * max_num_kflows must be >= 32
161 * and must be a power-of-2 supported value
162 * return: 1 -> invalid
165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
167 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
176 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
177 static int bnxt_restore_vlan_filters(struct bnxt *bp);
178 static void bnxt_dev_recover(void *arg);
179 static void bnxt_free_error_recovery_info(struct bnxt *bp);
180 static void bnxt_free_rep_info(struct bnxt *bp);
182 int is_bnxt_in_error(struct bnxt *bp)
184 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
186 if (bp->flags & BNXT_FLAG_FW_RESET)
192 /***********************/
195 * High level utility functions
198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
200 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
201 BNXT_RSS_TBL_SIZE_P5);
203 if (!BNXT_CHIP_P5(bp))
206 return RTE_ALIGN_MUL_CEIL(num_rss_rings,
207 BNXT_RSS_ENTRIES_PER_CTX_P5) /
208 BNXT_RSS_ENTRIES_PER_CTX_P5;
211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
213 if (!BNXT_CHIP_P5(bp))
214 return HW_HASH_INDEX_SIZE;
216 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
219 static void bnxt_free_parent_info(struct bnxt *bp)
221 rte_free(bp->parent);
224 static void bnxt_free_pf_info(struct bnxt *bp)
229 static void bnxt_free_link_info(struct bnxt *bp)
231 rte_free(bp->link_info);
234 static void bnxt_free_leds_info(struct bnxt *bp)
243 static void bnxt_free_flow_stats_info(struct bnxt *bp)
245 rte_free(bp->flow_stat);
246 bp->flow_stat = NULL;
249 static void bnxt_free_cos_queues(struct bnxt *bp)
251 rte_free(bp->rx_cos_queue);
252 rte_free(bp->tx_cos_queue);
255 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
257 bnxt_free_filter_mem(bp);
258 bnxt_free_vnic_attributes(bp);
259 bnxt_free_vnic_mem(bp);
261 /* tx/rx rings are configured as part of *_queue_setup callbacks.
262 * If the number of rings change across fw update,
263 * we don't have much choice except to warn the user.
267 bnxt_free_tx_rings(bp);
268 bnxt_free_rx_rings(bp);
270 bnxt_free_async_cp_ring(bp);
271 bnxt_free_rxtx_nq_ring(bp);
273 rte_free(bp->grp_info);
277 static int bnxt_alloc_parent_info(struct bnxt *bp)
279 bp->parent = rte_zmalloc("bnxt_parent_info",
280 sizeof(struct bnxt_parent_info), 0);
281 if (bp->parent == NULL)
287 static int bnxt_alloc_pf_info(struct bnxt *bp)
289 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
296 static int bnxt_alloc_link_info(struct bnxt *bp)
299 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
300 if (bp->link_info == NULL)
306 static int bnxt_alloc_leds_info(struct bnxt *bp)
311 bp->leds = rte_zmalloc("bnxt_leds",
312 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
314 if (bp->leds == NULL)
320 static int bnxt_alloc_cos_queues(struct bnxt *bp)
323 rte_zmalloc("bnxt_rx_cosq",
324 BNXT_COS_QUEUE_COUNT *
325 sizeof(struct bnxt_cos_queue_info),
327 if (bp->rx_cos_queue == NULL)
331 rte_zmalloc("bnxt_tx_cosq",
332 BNXT_COS_QUEUE_COUNT *
333 sizeof(struct bnxt_cos_queue_info),
335 if (bp->tx_cos_queue == NULL)
341 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
343 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
344 sizeof(struct bnxt_flow_stat_info), 0);
345 if (bp->flow_stat == NULL)
351 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
355 rc = bnxt_alloc_ring_grps(bp);
359 rc = bnxt_alloc_async_ring_struct(bp);
363 rc = bnxt_alloc_vnic_mem(bp);
367 rc = bnxt_alloc_vnic_attributes(bp);
371 rc = bnxt_alloc_filter_mem(bp);
375 rc = bnxt_alloc_async_cp_ring(bp);
379 rc = bnxt_alloc_rxtx_nq_ring(bp);
383 if (BNXT_FLOW_XSTATS_EN(bp)) {
384 rc = bnxt_alloc_flow_stats_info(bp);
392 bnxt_free_mem(bp, reconfig);
396 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
398 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
399 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
400 uint64_t rx_offloads = dev_conf->rxmode.offloads;
401 struct bnxt_rx_queue *rxq;
405 rc = bnxt_vnic_grp_alloc(bp, vnic);
409 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
410 vnic_id, vnic, vnic->fw_grp_ids);
412 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
416 /* Alloc RSS context only if RSS mode is enabled */
417 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
418 int j, nr_ctxs = bnxt_rss_ctxts(bp);
420 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
421 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
422 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
424 "Only queues 0-%d will be in RSS table\n",
425 BNXT_RSS_TBL_SIZE_P5 - 1);
429 for (j = 0; j < nr_ctxs; j++) {
430 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
436 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
440 vnic->num_lb_ctxts = nr_ctxs;
444 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
445 * setting is not available at this time, it will not be
446 * configured correctly in the CFA.
448 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
449 vnic->vlan_strip = true;
451 vnic->vlan_strip = false;
453 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
457 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
461 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
462 rxq = bp->eth_dev->data->rx_queues[j];
465 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
466 j, rxq->vnic, rxq->vnic->fw_grp_ids);
468 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
469 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
471 vnic->rx_queue_cnt++;
474 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
476 rc = bnxt_vnic_rss_configure(bp, vnic);
480 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
482 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
483 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
485 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
489 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
494 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
498 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
499 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
504 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
505 " rx_fc_in_tbl.ctx_id = %d\n",
506 bp->flow_stat->rx_fc_in_tbl.va,
507 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
508 bp->flow_stat->rx_fc_in_tbl.ctx_id);
510 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
511 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
516 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
517 " rx_fc_out_tbl.ctx_id = %d\n",
518 bp->flow_stat->rx_fc_out_tbl.va,
519 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
520 bp->flow_stat->rx_fc_out_tbl.ctx_id);
522 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
523 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
528 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
529 " tx_fc_in_tbl.ctx_id = %d\n",
530 bp->flow_stat->tx_fc_in_tbl.va,
531 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
532 bp->flow_stat->tx_fc_in_tbl.ctx_id);
534 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
535 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
540 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
541 " tx_fc_out_tbl.ctx_id = %d\n",
542 bp->flow_stat->tx_fc_out_tbl.va,
543 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
544 bp->flow_stat->tx_fc_out_tbl.ctx_id);
546 memset(bp->flow_stat->rx_fc_out_tbl.va,
548 bp->flow_stat->rx_fc_out_tbl.size);
549 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
550 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
551 bp->flow_stat->rx_fc_out_tbl.ctx_id,
552 bp->flow_stat->max_fc,
557 memset(bp->flow_stat->tx_fc_out_tbl.va,
559 bp->flow_stat->tx_fc_out_tbl.size);
560 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
561 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
562 bp->flow_stat->tx_fc_out_tbl.ctx_id,
563 bp->flow_stat->max_fc,
569 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
570 struct bnxt_ctx_mem_buf_info *ctx)
575 ctx->va = rte_zmalloc(type, size, 0);
578 rte_mem_lock_page(ctx->va);
580 ctx->dma = rte_mem_virt2iova(ctx->va);
581 if (ctx->dma == RTE_BAD_IOVA)
587 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
589 struct rte_pci_device *pdev = bp->pdev;
590 char type[RTE_MEMZONE_NAMESIZE];
594 max_fc = bp->flow_stat->max_fc;
596 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
597 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
598 /* 4 bytes for each counter-id */
599 rc = bnxt_alloc_ctx_mem_buf(type,
601 &bp->flow_stat->rx_fc_in_tbl);
605 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
606 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
607 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
608 rc = bnxt_alloc_ctx_mem_buf(type,
610 &bp->flow_stat->rx_fc_out_tbl);
614 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
615 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
616 /* 4 bytes for each counter-id */
617 rc = bnxt_alloc_ctx_mem_buf(type,
619 &bp->flow_stat->tx_fc_in_tbl);
623 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
624 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
625 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
626 rc = bnxt_alloc_ctx_mem_buf(type,
628 &bp->flow_stat->tx_fc_out_tbl);
632 rc = bnxt_register_fc_ctx_mem(bp);
637 static int bnxt_init_ctx_mem(struct bnxt *bp)
641 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
642 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
643 !BNXT_FLOW_XSTATS_EN(bp))
646 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
650 rc = bnxt_init_fc_ctx_mem(bp);
655 static int bnxt_update_phy_setting(struct bnxt *bp)
657 struct rte_eth_link new;
660 rc = bnxt_get_hwrm_link_config(bp, &new);
662 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
667 * On BCM957508-N2100 adapters, FW will not allow any user other
668 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
669 * always returns link up. Force phy update always in that case.
671 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
672 rc = bnxt_set_hwrm_link_config(bp, true);
674 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
682 static int bnxt_start_nic(struct bnxt *bp)
684 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
685 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
686 uint32_t intr_vector = 0;
687 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
688 uint32_t vec = BNXT_MISC_VEC_ID;
692 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
693 bp->eth_dev->data->dev_conf.rxmode.offloads |=
694 DEV_RX_OFFLOAD_JUMBO_FRAME;
695 bp->flags |= BNXT_FLAG_JUMBO;
697 bp->eth_dev->data->dev_conf.rxmode.offloads &=
698 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
699 bp->flags &= ~BNXT_FLAG_JUMBO;
702 /* THOR does not support ring groups.
703 * But we will use the array to save RSS context IDs.
705 if (BNXT_CHIP_P5(bp))
706 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
708 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
710 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
714 rc = bnxt_alloc_hwrm_rings(bp);
716 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
720 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
722 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
726 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
729 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
730 if (bp->rx_cos_queue[i].id != 0xff) {
731 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
735 "Num pools more than FW profile\n");
739 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
745 rc = bnxt_mq_rx_configure(bp);
747 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
752 rc = bnxt_setup_one_vnic(bp, 0);
755 /* VNIC configuration */
756 if (BNXT_RFS_NEEDS_VNIC(bp)) {
757 for (i = 1; i < bp->nr_vnics; i++) {
758 rc = bnxt_setup_one_vnic(bp, i);
764 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
767 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
771 /* check and configure queue intr-vector mapping */
772 if ((rte_intr_cap_multiple(intr_handle) ||
773 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
774 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
775 intr_vector = bp->eth_dev->data->nb_rx_queues;
776 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
777 if (intr_vector > bp->rx_cp_nr_rings) {
778 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
782 rc = rte_intr_efd_enable(intr_handle, intr_vector);
787 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
788 intr_handle->intr_vec =
789 rte_zmalloc("intr_vec",
790 bp->eth_dev->data->nb_rx_queues *
792 if (intr_handle->intr_vec == NULL) {
793 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
794 " intr_vec", bp->eth_dev->data->nb_rx_queues);
798 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
799 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
800 intr_handle->intr_vec, intr_handle->nb_efd,
801 intr_handle->max_intr);
802 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
804 intr_handle->intr_vec[queue_id] =
805 vec + BNXT_RX_VEC_START;
806 if (vec < base + intr_handle->nb_efd - 1)
811 /* enable uio/vfio intr/eventfd mapping */
812 rc = rte_intr_enable(intr_handle);
813 #ifndef RTE_EXEC_ENV_FREEBSD
814 /* In FreeBSD OS, nic_uio driver does not support interrupts */
819 rc = bnxt_update_phy_setting(bp);
823 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
825 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
830 rte_free(intr_handle->intr_vec);
832 rte_intr_efd_disable(intr_handle);
834 /* Some of the error status returned by FW may not be from errno.h */
841 static int bnxt_shutdown_nic(struct bnxt *bp)
843 bnxt_free_all_hwrm_resources(bp);
844 bnxt_free_all_filters(bp);
845 bnxt_free_all_vnics(bp);
850 * Device configuration and status function
853 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
855 uint32_t link_speed = bp->link_info->support_speeds;
856 uint32_t speed_capa = 0;
858 /* If PAM4 is configured, use PAM4 supported speed */
859 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
860 link_speed = bp->link_info->support_pam4_speeds;
862 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
863 speed_capa |= ETH_LINK_SPEED_100M;
864 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
865 speed_capa |= ETH_LINK_SPEED_100M_HD;
866 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
867 speed_capa |= ETH_LINK_SPEED_1G;
868 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
869 speed_capa |= ETH_LINK_SPEED_2_5G;
870 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
871 speed_capa |= ETH_LINK_SPEED_10G;
872 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
873 speed_capa |= ETH_LINK_SPEED_20G;
874 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
875 speed_capa |= ETH_LINK_SPEED_25G;
876 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
877 speed_capa |= ETH_LINK_SPEED_40G;
878 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
879 speed_capa |= ETH_LINK_SPEED_50G;
880 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
881 speed_capa |= ETH_LINK_SPEED_100G;
882 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
883 speed_capa |= ETH_LINK_SPEED_50G;
884 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
885 speed_capa |= ETH_LINK_SPEED_100G;
886 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
887 speed_capa |= ETH_LINK_SPEED_200G;
889 if (bp->link_info->auto_mode ==
890 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
891 speed_capa |= ETH_LINK_SPEED_FIXED;
893 speed_capa |= ETH_LINK_SPEED_AUTONEG;
898 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
899 struct rte_eth_dev_info *dev_info)
901 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
902 struct bnxt *bp = eth_dev->data->dev_private;
903 uint16_t max_vnics, i, j, vpool, vrxq;
904 unsigned int max_rx_rings;
907 rc = is_bnxt_in_error(bp);
912 dev_info->max_mac_addrs = bp->max_l2_ctx;
913 dev_info->max_hash_mac_addrs = 0;
915 /* PF/VF specifics */
917 dev_info->max_vfs = pdev->max_vfs;
919 max_rx_rings = bnxt_max_rings(bp);
920 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
921 dev_info->max_rx_queues = max_rx_rings;
922 dev_info->max_tx_queues = max_rx_rings;
923 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
924 dev_info->hash_key_size = 40;
925 max_vnics = bp->max_vnics;
928 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
929 dev_info->max_mtu = BNXT_MAX_MTU;
931 /* Fast path specifics */
932 dev_info->min_rx_bufsize = 1;
933 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
935 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
936 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
937 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
938 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
939 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
940 dev_info->tx_queue_offload_capa;
941 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
943 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
946 dev_info->default_rxconf = (struct rte_eth_rxconf) {
952 .rx_free_thresh = 32,
953 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
956 dev_info->default_txconf = (struct rte_eth_txconf) {
962 .tx_free_thresh = 32,
965 eth_dev->data->dev_conf.intr_conf.lsc = 1;
967 eth_dev->data->dev_conf.intr_conf.rxq = 1;
968 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
969 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
970 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
971 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
973 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
974 dev_info->switch_info.name = eth_dev->device->name;
975 dev_info->switch_info.domain_id = bp->switch_domain_id;
976 dev_info->switch_info.port_id =
977 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
978 BNXT_SWITCH_PORT_ID_TRUSTED_VF;
984 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
985 * need further investigation.
989 vpool = 64; /* ETH_64_POOLS */
990 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
991 for (i = 0; i < 4; vpool >>= 1, i++) {
992 if (max_vnics > vpool) {
993 for (j = 0; j < 5; vrxq >>= 1, j++) {
994 if (dev_info->max_rx_queues > vrxq) {
1000 /* Not enough resources to support VMDq */
1004 /* Not enough resources to support VMDq */
1008 dev_info->max_vmdq_pools = vpool;
1009 dev_info->vmdq_queue_num = vrxq;
1011 dev_info->vmdq_pool_base = 0;
1012 dev_info->vmdq_queue_base = 0;
1017 /* Configure the device based on the configuration provided */
1018 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1020 struct bnxt *bp = eth_dev->data->dev_private;
1021 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1024 bp->rx_queues = (void *)eth_dev->data->rx_queues;
1025 bp->tx_queues = (void *)eth_dev->data->tx_queues;
1026 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1027 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1029 rc = is_bnxt_in_error(bp);
1033 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1034 rc = bnxt_hwrm_check_vf_rings(bp);
1036 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1040 /* If a resource has already been allocated - in this case
1041 * it is the async completion ring, free it. Reallocate it after
1042 * resource reservation. This will ensure the resource counts
1043 * are calculated correctly.
1046 pthread_mutex_lock(&bp->def_cp_lock);
1048 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1049 bnxt_disable_int(bp);
1050 bnxt_free_cp_ring(bp, bp->async_cp_ring);
1053 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1055 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1056 pthread_mutex_unlock(&bp->def_cp_lock);
1060 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1061 rc = bnxt_alloc_async_cp_ring(bp);
1063 pthread_mutex_unlock(&bp->def_cp_lock);
1066 bnxt_enable_int(bp);
1069 pthread_mutex_unlock(&bp->def_cp_lock);
1072 /* Inherit new configurations */
1073 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1074 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1075 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1076 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1077 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1079 goto resource_error;
1081 if (BNXT_HAS_RING_GRPS(bp) &&
1082 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1083 goto resource_error;
1085 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1086 bp->max_vnics < eth_dev->data->nb_rx_queues)
1087 goto resource_error;
1089 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1090 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1092 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1093 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1094 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1096 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1097 eth_dev->data->mtu =
1098 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1099 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1101 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1107 "Insufficient resources to support requested config\n");
1109 "Num Queues Requested: Tx %d, Rx %d\n",
1110 eth_dev->data->nb_tx_queues,
1111 eth_dev->data->nb_rx_queues);
1113 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1114 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1115 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1119 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1121 struct rte_eth_link *link = ð_dev->data->dev_link;
1123 if (link->link_status)
1124 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1125 eth_dev->data->port_id,
1126 (uint32_t)link->link_speed,
1127 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1128 ("full-duplex") : ("half-duplex\n"));
1130 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1131 eth_dev->data->port_id);
1135 * Determine whether the current configuration requires support for scattered
1136 * receive; return 1 if scattered receive is required and 0 if not.
1138 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1143 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1146 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
1149 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1150 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1152 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1153 RTE_PKTMBUF_HEADROOM);
1154 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1160 static eth_rx_burst_t
1161 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1163 struct bnxt *bp = eth_dev->data->dev_private;
1165 /* Disable vector mode RX for Stingray2 for now */
1166 if (BNXT_CHIP_SR2(bp)) {
1167 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1168 return bnxt_recv_pkts;
1171 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1172 #ifndef RTE_LIBRTE_IEEE1588
1174 * Vector mode receive can be enabled only if scatter rx is not
1175 * in use and rx offloads are limited to VLAN stripping and
1178 if (!eth_dev->data->scattered_rx &&
1179 !(eth_dev->data->dev_conf.rxmode.offloads &
1180 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1181 DEV_RX_OFFLOAD_KEEP_CRC |
1182 DEV_RX_OFFLOAD_JUMBO_FRAME |
1183 DEV_RX_OFFLOAD_IPV4_CKSUM |
1184 DEV_RX_OFFLOAD_UDP_CKSUM |
1185 DEV_RX_OFFLOAD_TCP_CKSUM |
1186 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1187 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1188 DEV_RX_OFFLOAD_RSS_HASH |
1189 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1190 !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) &&
1191 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1192 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1193 eth_dev->data->port_id);
1194 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1195 return bnxt_recv_pkts_vec;
1197 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1198 eth_dev->data->port_id);
1200 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1201 eth_dev->data->port_id,
1202 eth_dev->data->scattered_rx,
1203 eth_dev->data->dev_conf.rxmode.offloads);
1206 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1207 return bnxt_recv_pkts;
1210 static eth_tx_burst_t
1211 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1213 struct bnxt *bp = eth_dev->data->dev_private;
1215 /* Disable vector mode TX for Stingray2 for now */
1216 if (BNXT_CHIP_SR2(bp))
1217 return bnxt_xmit_pkts;
1219 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1220 #ifndef RTE_LIBRTE_IEEE1588
1221 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1224 * Vector mode transmit can be enabled only if not using scatter rx
1227 if (!eth_dev->data->scattered_rx &&
1228 !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1229 !BNXT_TRUFLOW_EN(bp) &&
1230 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1231 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1232 eth_dev->data->port_id);
1233 return bnxt_xmit_pkts_vec;
1235 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1236 eth_dev->data->port_id);
1238 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1239 eth_dev->data->port_id,
1240 eth_dev->data->scattered_rx,
1244 return bnxt_xmit_pkts;
1247 static int bnxt_handle_if_change_status(struct bnxt *bp)
1251 /* Since fw has undergone a reset and lost all contexts,
1252 * set fatal flag to not issue hwrm during cleanup
1254 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1255 bnxt_uninit_resources(bp, true);
1257 /* clear fatal flag so that re-init happens */
1258 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1259 rc = bnxt_init_resources(bp, true);
1261 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1266 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1268 struct bnxt *bp = eth_dev->data->dev_private;
1271 if (!bp->link_info->link_up)
1272 rc = bnxt_set_hwrm_link_config(bp, true);
1274 eth_dev->data->dev_link.link_status = 1;
1276 bnxt_print_link_info(eth_dev);
1280 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1282 struct bnxt *bp = eth_dev->data->dev_private;
1284 eth_dev->data->dev_link.link_status = 0;
1285 bnxt_set_hwrm_link_config(bp, false);
1286 bp->link_info->link_up = 0;
1291 static void bnxt_free_switch_domain(struct bnxt *bp)
1295 if (bp->switch_domain_id) {
1296 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1298 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1299 bp->switch_domain_id, rc);
1303 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1305 struct bnxt *bp = eth_dev->data->dev_private;
1306 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1307 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1308 struct rte_eth_link link;
1311 eth_dev->data->dev_started = 0;
1312 eth_dev->data->scattered_rx = 0;
1314 /* Prevent crashes when queues are still in use */
1315 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1316 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1318 bnxt_disable_int(bp);
1320 /* disable uio/vfio intr/eventfd mapping */
1321 rte_intr_disable(intr_handle);
1323 /* Stop the child representors for this device */
1324 ret = bnxt_rep_stop_all(bp);
1328 /* delete the bnxt ULP port details */
1329 bnxt_ulp_port_deinit(bp);
1331 bnxt_cancel_fw_health_check(bp);
1333 /* Do not bring link down during reset recovery */
1334 if (!is_bnxt_in_error(bp)) {
1335 bnxt_dev_set_link_down_op(eth_dev);
1336 /* Wait for link to be reset */
1337 if (BNXT_SINGLE_PF(bp))
1339 /* clear the recorded link status */
1340 memset(&link, 0, sizeof(link));
1341 rte_eth_linkstatus_set(eth_dev, &link);
1344 /* Clean queue intr-vector mapping */
1345 rte_intr_efd_disable(intr_handle);
1346 if (intr_handle->intr_vec != NULL) {
1347 rte_free(intr_handle->intr_vec);
1348 intr_handle->intr_vec = NULL;
1351 bnxt_hwrm_port_clr_stats(bp);
1352 bnxt_free_tx_mbufs(bp);
1353 bnxt_free_rx_mbufs(bp);
1354 /* Process any remaining notifications in default completion queue */
1355 bnxt_int_handler(eth_dev);
1356 bnxt_shutdown_nic(bp);
1357 bnxt_hwrm_if_change(bp, false);
1359 rte_free(bp->mark_table);
1360 bp->mark_table = NULL;
1362 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1363 bp->rx_cosq_cnt = 0;
1364 /* All filters are deleted on a port stop. */
1365 if (BNXT_FLOW_XSTATS_EN(bp))
1366 bp->flow_stat->flow_count = 0;
1371 /* Unload the driver, release resources */
1372 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1374 struct bnxt *bp = eth_dev->data->dev_private;
1376 pthread_mutex_lock(&bp->err_recovery_lock);
1377 if (bp->flags & BNXT_FLAG_FW_RESET) {
1379 "Adapter recovering from error..Please retry\n");
1380 pthread_mutex_unlock(&bp->err_recovery_lock);
1383 pthread_mutex_unlock(&bp->err_recovery_lock);
1385 return bnxt_dev_stop(eth_dev);
1388 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1390 struct bnxt *bp = eth_dev->data->dev_private;
1391 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1393 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1395 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1396 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1400 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1402 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1403 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1406 rc = bnxt_hwrm_if_change(bp, true);
1407 if (rc == 0 || rc != -EAGAIN)
1410 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1411 } while (retry_cnt--);
1416 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1417 rc = bnxt_handle_if_change_status(bp);
1422 bnxt_enable_int(bp);
1424 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1426 rc = bnxt_start_nic(bp);
1430 eth_dev->data->dev_started = 1;
1432 bnxt_link_update_op(eth_dev, 1);
1434 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1435 vlan_mask |= ETH_VLAN_FILTER_MASK;
1436 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1437 vlan_mask |= ETH_VLAN_STRIP_MASK;
1438 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1442 /* Initialize bnxt ULP port details */
1443 rc = bnxt_ulp_port_init(bp);
1447 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1448 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1450 bnxt_schedule_fw_health_check(bp);
1455 bnxt_dev_stop(eth_dev);
1460 bnxt_uninit_locks(struct bnxt *bp)
1462 pthread_mutex_destroy(&bp->flow_lock);
1463 pthread_mutex_destroy(&bp->def_cp_lock);
1464 pthread_mutex_destroy(&bp->health_check_lock);
1465 pthread_mutex_destroy(&bp->err_recovery_lock);
1467 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1468 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1472 static void bnxt_drv_uninit(struct bnxt *bp)
1474 bnxt_free_switch_domain(bp);
1475 bnxt_free_leds_info(bp);
1476 bnxt_free_cos_queues(bp);
1477 bnxt_free_link_info(bp);
1478 bnxt_free_pf_info(bp);
1479 bnxt_free_parent_info(bp);
1480 bnxt_uninit_locks(bp);
1482 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1483 bp->tx_mem_zone = NULL;
1484 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1485 bp->rx_mem_zone = NULL;
1487 bnxt_hwrm_free_vf_info(bp);
1489 rte_free(bp->grp_info);
1490 bp->grp_info = NULL;
1493 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1495 struct bnxt *bp = eth_dev->data->dev_private;
1498 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1501 pthread_mutex_lock(&bp->err_recovery_lock);
1502 if (bp->flags & BNXT_FLAG_FW_RESET) {
1504 "Adapter recovering from error...Please retry\n");
1505 pthread_mutex_unlock(&bp->err_recovery_lock);
1508 pthread_mutex_unlock(&bp->err_recovery_lock);
1510 /* cancel the recovery handler before remove dev */
1511 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1512 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1513 bnxt_cancel_fc_thread(bp);
1515 if (eth_dev->data->dev_started)
1516 ret = bnxt_dev_stop(eth_dev);
1518 bnxt_uninit_resources(bp, false);
1520 bnxt_drv_uninit(bp);
1525 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1528 struct bnxt *bp = eth_dev->data->dev_private;
1529 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1530 struct bnxt_vnic_info *vnic;
1531 struct bnxt_filter_info *filter, *temp_filter;
1534 if (is_bnxt_in_error(bp))
1538 * Loop through all VNICs from the specified filter flow pools to
1539 * remove the corresponding MAC addr filter
1541 for (i = 0; i < bp->nr_vnics; i++) {
1542 if (!(pool_mask & (1ULL << i)))
1545 vnic = &bp->vnic_info[i];
1546 filter = STAILQ_FIRST(&vnic->filter);
1548 temp_filter = STAILQ_NEXT(filter, next);
1549 if (filter->mac_index == index) {
1550 STAILQ_REMOVE(&vnic->filter, filter,
1551 bnxt_filter_info, next);
1552 bnxt_hwrm_clear_l2_filter(bp, filter);
1553 bnxt_free_filter(bp, filter);
1555 filter = temp_filter;
1560 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1561 struct rte_ether_addr *mac_addr, uint32_t index,
1564 struct bnxt_filter_info *filter;
1567 /* Attach requested MAC address to the new l2_filter */
1568 STAILQ_FOREACH(filter, &vnic->filter, next) {
1569 if (filter->mac_index == index) {
1571 "MAC addr already existed for pool %d\n",
1577 filter = bnxt_alloc_filter(bp);
1579 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1583 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1584 * if the MAC that's been programmed now is a different one, then,
1585 * copy that addr to filter->l2_addr
1588 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1589 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1591 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1593 filter->mac_index = index;
1594 if (filter->mac_index == 0)
1595 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1597 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1599 bnxt_free_filter(bp, filter);
1605 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1606 struct rte_ether_addr *mac_addr,
1607 uint32_t index, uint32_t pool)
1609 struct bnxt *bp = eth_dev->data->dev_private;
1610 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1613 rc = is_bnxt_in_error(bp);
1617 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1618 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1623 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1627 /* Filter settings will get applied when port is started */
1628 if (!eth_dev->data->dev_started)
1631 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1636 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1639 struct bnxt *bp = eth_dev->data->dev_private;
1640 struct rte_eth_link new;
1641 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1642 BNXT_MIN_LINK_WAIT_CNT;
1644 rc = is_bnxt_in_error(bp);
1648 memset(&new, 0, sizeof(new));
1650 /* Retrieve link info from hardware */
1651 rc = bnxt_get_hwrm_link_config(bp, &new);
1653 new.link_speed = ETH_LINK_SPEED_100M;
1654 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1656 "Failed to retrieve link rc = 0x%x!\n", rc);
1660 if (!wait_to_complete || new.link_status)
1663 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1666 /* Only single function PF can bring phy down.
1667 * When port is stopped, report link down for VF/MH/NPAR functions.
1669 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1670 memset(&new, 0, sizeof(new));
1673 /* Timed out or success */
1674 if (new.link_status != eth_dev->data->dev_link.link_status ||
1675 new.link_speed != eth_dev->data->dev_link.link_speed) {
1676 rte_eth_linkstatus_set(eth_dev, &new);
1678 rte_eth_dev_callback_process(eth_dev,
1679 RTE_ETH_EVENT_INTR_LSC,
1682 bnxt_print_link_info(eth_dev);
1688 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1690 struct bnxt *bp = eth_dev->data->dev_private;
1691 struct bnxt_vnic_info *vnic;
1695 rc = is_bnxt_in_error(bp);
1699 /* Filter settings will get applied when port is started */
1700 if (!eth_dev->data->dev_started)
1703 if (bp->vnic_info == NULL)
1706 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1708 old_flags = vnic->flags;
1709 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1710 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1712 vnic->flags = old_flags;
1717 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1719 struct bnxt *bp = eth_dev->data->dev_private;
1720 struct bnxt_vnic_info *vnic;
1724 rc = is_bnxt_in_error(bp);
1728 /* Filter settings will get applied when port is started */
1729 if (!eth_dev->data->dev_started)
1732 if (bp->vnic_info == NULL)
1735 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1737 old_flags = vnic->flags;
1738 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1739 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1741 vnic->flags = old_flags;
1746 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1748 struct bnxt *bp = eth_dev->data->dev_private;
1749 struct bnxt_vnic_info *vnic;
1753 rc = is_bnxt_in_error(bp);
1757 /* Filter settings will get applied when port is started */
1758 if (!eth_dev->data->dev_started)
1761 if (bp->vnic_info == NULL)
1764 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1766 old_flags = vnic->flags;
1767 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1768 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1770 vnic->flags = old_flags;
1775 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1777 struct bnxt *bp = eth_dev->data->dev_private;
1778 struct bnxt_vnic_info *vnic;
1782 rc = is_bnxt_in_error(bp);
1786 /* Filter settings will get applied when port is started */
1787 if (!eth_dev->data->dev_started)
1790 if (bp->vnic_info == NULL)
1793 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1795 old_flags = vnic->flags;
1796 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1797 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1799 vnic->flags = old_flags;
1804 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1805 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1807 if (qid >= bp->rx_nr_rings)
1810 return bp->eth_dev->data->rx_queues[qid];
1813 /* Return rxq corresponding to a given rss table ring/group ID. */
1814 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1816 struct bnxt_rx_queue *rxq;
1819 if (!BNXT_HAS_RING_GRPS(bp)) {
1820 for (i = 0; i < bp->rx_nr_rings; i++) {
1821 rxq = bp->eth_dev->data->rx_queues[i];
1822 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1826 for (i = 0; i < bp->rx_nr_rings; i++) {
1827 if (bp->grp_info[i].fw_grp_id == fwr)
1832 return INVALID_HW_RING_ID;
1835 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1836 struct rte_eth_rss_reta_entry64 *reta_conf,
1839 struct bnxt *bp = eth_dev->data->dev_private;
1840 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1841 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1842 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1846 rc = is_bnxt_in_error(bp);
1850 if (!vnic->rss_table)
1853 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1856 if (reta_size != tbl_size) {
1857 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1858 "(%d) must equal the size supported by the hardware "
1859 "(%d)\n", reta_size, tbl_size);
1863 for (i = 0; i < reta_size; i++) {
1864 struct bnxt_rx_queue *rxq;
1866 idx = i / RTE_RETA_GROUP_SIZE;
1867 sft = i % RTE_RETA_GROUP_SIZE;
1869 if (!(reta_conf[idx].mask & (1ULL << sft)))
1872 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1874 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1878 if (BNXT_CHIP_P5(bp)) {
1879 vnic->rss_table[i * 2] =
1880 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1881 vnic->rss_table[i * 2 + 1] =
1882 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1884 vnic->rss_table[i] =
1885 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1889 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1893 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1894 struct rte_eth_rss_reta_entry64 *reta_conf,
1897 struct bnxt *bp = eth_dev->data->dev_private;
1898 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1899 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1900 uint16_t idx, sft, i;
1903 rc = is_bnxt_in_error(bp);
1907 /* Retrieve from the default VNIC */
1910 if (!vnic->rss_table)
1913 if (reta_size != tbl_size) {
1914 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1915 "(%d) must equal the size supported by the hardware "
1916 "(%d)\n", reta_size, tbl_size);
1920 for (idx = 0, i = 0; i < reta_size; i++) {
1921 idx = i / RTE_RETA_GROUP_SIZE;
1922 sft = i % RTE_RETA_GROUP_SIZE;
1924 if (reta_conf[idx].mask & (1ULL << sft)) {
1927 if (BNXT_CHIP_P5(bp))
1928 qid = bnxt_rss_to_qid(bp,
1929 vnic->rss_table[i * 2]);
1931 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
1933 if (qid == INVALID_HW_RING_ID) {
1934 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
1937 reta_conf[idx].reta[sft] = qid;
1944 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
1945 struct rte_eth_rss_conf *rss_conf)
1947 struct bnxt *bp = eth_dev->data->dev_private;
1948 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1949 struct bnxt_vnic_info *vnic;
1952 rc = is_bnxt_in_error(bp);
1957 * If RSS enablement were different than dev_configure,
1958 * then return -EINVAL
1960 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
1961 if (!rss_conf->rss_hf)
1962 PMD_DRV_LOG(ERR, "Hash type NONE\n");
1964 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
1968 bp->flags |= BNXT_FLAG_UPDATE_HASH;
1969 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
1973 /* Update the default RSS VNIC(s) */
1974 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1975 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
1977 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
1978 ETH_RSS_LEVEL(rss_conf->rss_hf));
1981 * If hashkey is not specified, use the previously configured
1984 if (!rss_conf->rss_key)
1987 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
1989 "Invalid hashkey length, should be 16 bytes\n");
1992 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
1995 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1999 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2000 struct rte_eth_rss_conf *rss_conf)
2002 struct bnxt *bp = eth_dev->data->dev_private;
2003 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2005 uint32_t hash_types;
2007 rc = is_bnxt_in_error(bp);
2011 /* RSS configuration is the same for all VNICs */
2012 if (vnic && vnic->rss_hash_key) {
2013 if (rss_conf->rss_key) {
2014 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2015 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2016 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2019 hash_types = vnic->hash_type;
2020 rss_conf->rss_hf = 0;
2021 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2022 rss_conf->rss_hf |= ETH_RSS_IPV4;
2023 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2025 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2026 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2028 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2030 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2031 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2033 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2035 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2036 rss_conf->rss_hf |= ETH_RSS_IPV6;
2037 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2039 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2040 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2042 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2044 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2045 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2047 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2051 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2055 "Unknown RSS config from firmware (%08x), RSS disabled",
2060 rss_conf->rss_hf = 0;
2065 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2066 struct rte_eth_fc_conf *fc_conf)
2068 struct bnxt *bp = dev->data->dev_private;
2069 struct rte_eth_link link_info;
2072 rc = is_bnxt_in_error(bp);
2076 rc = bnxt_get_hwrm_link_config(bp, &link_info);
2080 memset(fc_conf, 0, sizeof(*fc_conf));
2081 if (bp->link_info->auto_pause)
2082 fc_conf->autoneg = 1;
2083 switch (bp->link_info->pause) {
2085 fc_conf->mode = RTE_FC_NONE;
2087 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2088 fc_conf->mode = RTE_FC_TX_PAUSE;
2090 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2091 fc_conf->mode = RTE_FC_RX_PAUSE;
2093 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2094 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2095 fc_conf->mode = RTE_FC_FULL;
2101 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2102 struct rte_eth_fc_conf *fc_conf)
2104 struct bnxt *bp = dev->data->dev_private;
2107 rc = is_bnxt_in_error(bp);
2111 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2112 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2116 switch (fc_conf->mode) {
2118 bp->link_info->auto_pause = 0;
2119 bp->link_info->force_pause = 0;
2121 case RTE_FC_RX_PAUSE:
2122 if (fc_conf->autoneg) {
2123 bp->link_info->auto_pause =
2124 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2125 bp->link_info->force_pause = 0;
2127 bp->link_info->auto_pause = 0;
2128 bp->link_info->force_pause =
2129 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2132 case RTE_FC_TX_PAUSE:
2133 if (fc_conf->autoneg) {
2134 bp->link_info->auto_pause =
2135 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2136 bp->link_info->force_pause = 0;
2138 bp->link_info->auto_pause = 0;
2139 bp->link_info->force_pause =
2140 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2144 if (fc_conf->autoneg) {
2145 bp->link_info->auto_pause =
2146 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2147 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2148 bp->link_info->force_pause = 0;
2150 bp->link_info->auto_pause = 0;
2151 bp->link_info->force_pause =
2152 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2153 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2157 return bnxt_set_hwrm_link_config(bp, true);
2160 /* Add UDP tunneling port */
2162 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2163 struct rte_eth_udp_tunnel *udp_tunnel)
2165 struct bnxt *bp = eth_dev->data->dev_private;
2166 uint16_t tunnel_type = 0;
2169 rc = is_bnxt_in_error(bp);
2173 switch (udp_tunnel->prot_type) {
2174 case RTE_TUNNEL_TYPE_VXLAN:
2175 if (bp->vxlan_port_cnt) {
2176 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2177 udp_tunnel->udp_port);
2178 if (bp->vxlan_port != udp_tunnel->udp_port) {
2179 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2182 bp->vxlan_port_cnt++;
2186 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2187 bp->vxlan_port_cnt++;
2189 case RTE_TUNNEL_TYPE_GENEVE:
2190 if (bp->geneve_port_cnt) {
2191 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2192 udp_tunnel->udp_port);
2193 if (bp->geneve_port != udp_tunnel->udp_port) {
2194 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2197 bp->geneve_port_cnt++;
2201 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2202 bp->geneve_port_cnt++;
2205 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2208 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2214 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2215 struct rte_eth_udp_tunnel *udp_tunnel)
2217 struct bnxt *bp = eth_dev->data->dev_private;
2218 uint16_t tunnel_type = 0;
2222 rc = is_bnxt_in_error(bp);
2226 switch (udp_tunnel->prot_type) {
2227 case RTE_TUNNEL_TYPE_VXLAN:
2228 if (!bp->vxlan_port_cnt) {
2229 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2232 if (bp->vxlan_port != udp_tunnel->udp_port) {
2233 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2234 udp_tunnel->udp_port, bp->vxlan_port);
2237 if (--bp->vxlan_port_cnt)
2241 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2242 port = bp->vxlan_fw_dst_port_id;
2244 case RTE_TUNNEL_TYPE_GENEVE:
2245 if (!bp->geneve_port_cnt) {
2246 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2249 if (bp->geneve_port != udp_tunnel->udp_port) {
2250 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2251 udp_tunnel->udp_port, bp->geneve_port);
2254 if (--bp->geneve_port_cnt)
2258 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2259 port = bp->geneve_fw_dst_port_id;
2262 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2266 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2270 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2272 struct bnxt_filter_info *filter;
2273 struct bnxt_vnic_info *vnic;
2275 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2277 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2278 filter = STAILQ_FIRST(&vnic->filter);
2280 /* Search for this matching MAC+VLAN filter */
2281 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2282 /* Delete the filter */
2283 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2286 STAILQ_REMOVE(&vnic->filter, filter,
2287 bnxt_filter_info, next);
2288 bnxt_free_filter(bp, filter);
2290 "Deleted vlan filter for %d\n",
2294 filter = STAILQ_NEXT(filter, next);
2299 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2301 struct bnxt_filter_info *filter;
2302 struct bnxt_vnic_info *vnic;
2304 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2305 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2306 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2308 /* Implementation notes on the use of VNIC in this command:
2310 * By default, these filters belong to default vnic for the function.
2311 * Once these filters are set up, only destination VNIC can be modified.
2312 * If the destination VNIC is not specified in this command,
2313 * then the HWRM shall only create an l2 context id.
2316 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2317 filter = STAILQ_FIRST(&vnic->filter);
2318 /* Check if the VLAN has already been added */
2320 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2323 filter = STAILQ_NEXT(filter, next);
2326 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2327 * command to create MAC+VLAN filter with the right flags, enables set.
2329 filter = bnxt_alloc_filter(bp);
2332 "MAC/VLAN filter alloc failed\n");
2335 /* MAC + VLAN ID filter */
2336 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2337 * untagged packets are received
2339 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2340 * packets and only the programmed vlan's packets are received
2342 filter->l2_ivlan = vlan_id;
2343 filter->l2_ivlan_mask = 0x0FFF;
2344 filter->enables |= en;
2345 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2347 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2349 /* Free the newly allocated filter as we were
2350 * not able to create the filter in hardware.
2352 bnxt_free_filter(bp, filter);
2356 filter->mac_index = 0;
2357 /* Add this new filter to the list */
2359 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2361 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2364 "Added Vlan filter for %d\n", vlan_id);
2368 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2369 uint16_t vlan_id, int on)
2371 struct bnxt *bp = eth_dev->data->dev_private;
2374 rc = is_bnxt_in_error(bp);
2378 if (!eth_dev->data->dev_started) {
2379 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2383 /* These operations apply to ALL existing MAC/VLAN filters */
2385 return bnxt_add_vlan_filter(bp, vlan_id);
2387 return bnxt_del_vlan_filter(bp, vlan_id);
2390 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2391 struct bnxt_vnic_info *vnic)
2393 struct bnxt_filter_info *filter;
2396 filter = STAILQ_FIRST(&vnic->filter);
2398 if (filter->mac_index == 0 &&
2399 !memcmp(filter->l2_addr, bp->mac_addr,
2400 RTE_ETHER_ADDR_LEN)) {
2401 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2403 STAILQ_REMOVE(&vnic->filter, filter,
2404 bnxt_filter_info, next);
2405 bnxt_free_filter(bp, filter);
2409 filter = STAILQ_NEXT(filter, next);
2415 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2417 struct bnxt_vnic_info *vnic;
2421 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2422 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2423 /* Remove any VLAN filters programmed */
2424 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2425 bnxt_del_vlan_filter(bp, i);
2427 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2431 /* Default filter will allow packets that match the
2432 * dest mac. So, it has to be deleted, otherwise, we
2433 * will endup receiving vlan packets for which the
2434 * filter is not programmed, when hw-vlan-filter
2435 * configuration is ON
2437 bnxt_del_dflt_mac_filter(bp, vnic);
2438 /* This filter will allow only untagged packets */
2439 bnxt_add_vlan_filter(bp, 0);
2441 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2442 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2447 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2449 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2453 /* Destroy vnic filters and vnic */
2454 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2455 DEV_RX_OFFLOAD_VLAN_FILTER) {
2456 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2457 bnxt_del_vlan_filter(bp, i);
2459 bnxt_del_dflt_mac_filter(bp, vnic);
2461 rc = bnxt_hwrm_vnic_free(bp, vnic);
2465 rte_free(vnic->fw_grp_ids);
2466 vnic->fw_grp_ids = NULL;
2468 vnic->rx_queue_cnt = 0;
2474 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2476 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2479 /* Destroy, recreate and reconfigure the default vnic */
2480 rc = bnxt_free_one_vnic(bp, 0);
2484 /* default vnic 0 */
2485 rc = bnxt_setup_one_vnic(bp, 0);
2489 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2490 DEV_RX_OFFLOAD_VLAN_FILTER) {
2491 rc = bnxt_add_vlan_filter(bp, 0);
2494 rc = bnxt_restore_vlan_filters(bp);
2498 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2503 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2507 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2508 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2514 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2516 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2517 struct bnxt *bp = dev->data->dev_private;
2520 rc = is_bnxt_in_error(bp);
2524 /* Filter settings will get applied when port is started */
2525 if (!dev->data->dev_started)
2528 if (mask & ETH_VLAN_FILTER_MASK) {
2529 /* Enable or disable VLAN filtering */
2530 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2535 if (mask & ETH_VLAN_STRIP_MASK) {
2536 /* Enable or disable VLAN stripping */
2537 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2542 if (mask & ETH_VLAN_EXTEND_MASK) {
2543 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2544 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2546 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2553 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2556 struct bnxt *bp = dev->data->dev_private;
2557 int qinq = dev->data->dev_conf.rxmode.offloads &
2558 DEV_RX_OFFLOAD_VLAN_EXTEND;
2560 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2561 vlan_type != ETH_VLAN_TYPE_OUTER) {
2563 "Unsupported vlan type.");
2568 "QinQ not enabled. Needs to be ON as we can "
2569 "accelerate only outer vlan\n");
2573 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2575 case RTE_ETHER_TYPE_QINQ:
2577 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2579 case RTE_ETHER_TYPE_VLAN:
2581 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2583 case RTE_ETHER_TYPE_QINQ1:
2585 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2587 case RTE_ETHER_TYPE_QINQ2:
2589 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2591 case RTE_ETHER_TYPE_QINQ3:
2593 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2596 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2599 bp->outer_tpid_bd |= tpid;
2600 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2601 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2603 "Can accelerate only outer vlan in QinQ\n");
2611 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2612 struct rte_ether_addr *addr)
2614 struct bnxt *bp = dev->data->dev_private;
2615 /* Default Filter is tied to VNIC 0 */
2616 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2619 rc = is_bnxt_in_error(bp);
2623 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2626 if (rte_is_zero_ether_addr(addr))
2629 /* Filter settings will get applied when port is started */
2630 if (!dev->data->dev_started)
2633 /* Check if the requested MAC is already added */
2634 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2637 /* Destroy filter and re-create it */
2638 bnxt_del_dflt_mac_filter(bp, vnic);
2640 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2641 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2642 /* This filter will allow only untagged packets */
2643 rc = bnxt_add_vlan_filter(bp, 0);
2645 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2648 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2653 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2654 struct rte_ether_addr *mc_addr_set,
2655 uint32_t nb_mc_addr)
2657 struct bnxt *bp = eth_dev->data->dev_private;
2658 char *mc_addr_list = (char *)mc_addr_set;
2659 struct bnxt_vnic_info *vnic;
2660 uint32_t off = 0, i = 0;
2663 rc = is_bnxt_in_error(bp);
2667 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2669 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2670 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2674 /* TODO Check for Duplicate mcast addresses */
2675 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2676 for (i = 0; i < nb_mc_addr; i++) {
2677 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2678 RTE_ETHER_ADDR_LEN);
2679 off += RTE_ETHER_ADDR_LEN;
2682 vnic->mc_addr_cnt = i;
2683 if (vnic->mc_addr_cnt)
2684 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2686 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2689 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2693 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2695 struct bnxt *bp = dev->data->dev_private;
2696 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2697 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2698 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2699 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2702 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2703 fw_major, fw_minor, fw_updt, fw_rsvd);
2705 ret += 1; /* add the size of '\0' */
2706 if (fw_size < (uint32_t)ret)
2713 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2714 struct rte_eth_rxq_info *qinfo)
2716 struct bnxt *bp = dev->data->dev_private;
2717 struct bnxt_rx_queue *rxq;
2719 if (is_bnxt_in_error(bp))
2722 rxq = dev->data->rx_queues[queue_id];
2724 qinfo->mp = rxq->mb_pool;
2725 qinfo->scattered_rx = dev->data->scattered_rx;
2726 qinfo->nb_desc = rxq->nb_rx_desc;
2728 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2729 qinfo->conf.rx_drop_en = rxq->drop_en;
2730 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2731 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2735 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2736 struct rte_eth_txq_info *qinfo)
2738 struct bnxt *bp = dev->data->dev_private;
2739 struct bnxt_tx_queue *txq;
2741 if (is_bnxt_in_error(bp))
2744 txq = dev->data->tx_queues[queue_id];
2746 qinfo->nb_desc = txq->nb_tx_desc;
2748 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2749 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2750 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2752 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2753 qinfo->conf.tx_rs_thresh = 0;
2754 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2755 qinfo->conf.offloads = txq->offloads;
2758 static const struct {
2759 eth_rx_burst_t pkt_burst;
2761 } bnxt_rx_burst_info[] = {
2762 {bnxt_recv_pkts, "Scalar"},
2763 #if defined(RTE_ARCH_X86)
2764 {bnxt_recv_pkts_vec, "Vector SSE"},
2765 #elif defined(RTE_ARCH_ARM64)
2766 {bnxt_recv_pkts_vec, "Vector Neon"},
2771 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2772 struct rte_eth_burst_mode *mode)
2774 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2777 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2778 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2779 snprintf(mode->info, sizeof(mode->info), "%s",
2780 bnxt_rx_burst_info[i].info);
2788 static const struct {
2789 eth_tx_burst_t pkt_burst;
2791 } bnxt_tx_burst_info[] = {
2792 {bnxt_xmit_pkts, "Scalar"},
2793 #if defined(RTE_ARCH_X86)
2794 {bnxt_xmit_pkts_vec, "Vector SSE"},
2795 #elif defined(RTE_ARCH_ARM64)
2796 {bnxt_xmit_pkts_vec, "Vector Neon"},
2801 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2802 struct rte_eth_burst_mode *mode)
2804 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2807 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2808 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2809 snprintf(mode->info, sizeof(mode->info), "%s",
2810 bnxt_tx_burst_info[i].info);
2818 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2820 struct bnxt *bp = eth_dev->data->dev_private;
2821 uint32_t new_pkt_size;
2825 rc = is_bnxt_in_error(bp);
2829 /* Exit if receive queues are not configured yet */
2830 if (!eth_dev->data->nb_rx_queues)
2833 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2834 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2837 * Disallow any MTU change that would require scattered receive support
2838 * if it is not already enabled.
2840 if (eth_dev->data->dev_started &&
2841 !eth_dev->data->scattered_rx &&
2843 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2845 "MTU change would require scattered rx support. ");
2846 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2850 if (new_mtu > RTE_ETHER_MTU) {
2851 bp->flags |= BNXT_FLAG_JUMBO;
2852 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2853 DEV_RX_OFFLOAD_JUMBO_FRAME;
2855 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2856 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2857 bp->flags &= ~BNXT_FLAG_JUMBO;
2860 /* Is there a change in mtu setting? */
2861 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2864 for (i = 0; i < bp->nr_vnics; i++) {
2865 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2868 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2869 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2873 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2874 size -= RTE_PKTMBUF_HEADROOM;
2876 if (size < new_mtu) {
2877 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2884 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2886 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2892 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2894 struct bnxt *bp = dev->data->dev_private;
2895 uint16_t vlan = bp->vlan;
2898 rc = is_bnxt_in_error(bp);
2902 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2904 "PVID cannot be modified for this function\n");
2907 bp->vlan = on ? pvid : 0;
2909 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2916 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2918 struct bnxt *bp = dev->data->dev_private;
2921 rc = is_bnxt_in_error(bp);
2925 return bnxt_hwrm_port_led_cfg(bp, true);
2929 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
2931 struct bnxt *bp = dev->data->dev_private;
2934 rc = is_bnxt_in_error(bp);
2938 return bnxt_hwrm_port_led_cfg(bp, false);
2942 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2944 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2945 struct bnxt_cp_ring_info *cpr;
2946 uint32_t desc = 0, raw_cons;
2947 struct bnxt_rx_queue *rxq;
2948 struct rx_pkt_cmpl *rxcmp;
2951 rc = is_bnxt_in_error(bp);
2955 rxq = dev->data->rx_queues[rx_queue_id];
2957 raw_cons = cpr->cp_raw_cons;
2960 uint32_t agg_cnt, cons, cmpl_type;
2962 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
2963 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
2965 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
2968 cmpl_type = CMP_TYPE(rxcmp);
2970 switch (cmpl_type) {
2971 case CMPL_BASE_TYPE_RX_L2:
2972 case CMPL_BASE_TYPE_RX_L2_V2:
2973 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
2974 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
2978 case CMPL_BASE_TYPE_RX_TPA_END:
2979 if (BNXT_CHIP_P5(rxq->bp)) {
2980 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
2982 p5_tpa_end = (void *)rxcmp;
2983 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
2985 struct rx_tpa_end_cmpl *tpa_end;
2987 tpa_end = (void *)rxcmp;
2988 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
2991 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
2996 raw_cons += CMP_LEN(cmpl_type);
3004 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3006 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
3007 struct bnxt_rx_ring_info *rxr;
3008 struct bnxt_cp_ring_info *cpr;
3009 struct rte_mbuf *rx_buf;
3010 struct rx_pkt_cmpl *rxcmp;
3011 uint32_t cons, cp_cons;
3017 rc = is_bnxt_in_error(rxq->bp);
3024 if (offset >= rxq->nb_rx_desc)
3027 cons = RING_CMP(cpr->cp_ring_struct, offset);
3028 cp_cons = cpr->cp_raw_cons;
3029 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3031 if (cons > cp_cons) {
3032 if (CMPL_VALID(rxcmp, cpr->valid))
3033 return RTE_ETH_RX_DESC_DONE;
3035 if (CMPL_VALID(rxcmp, !cpr->valid))
3036 return RTE_ETH_RX_DESC_DONE;
3038 rx_buf = rxr->rx_buf_ring[cons];
3039 if (rx_buf == NULL || rx_buf == &rxq->fake_mbuf)
3040 return RTE_ETH_RX_DESC_UNAVAIL;
3043 return RTE_ETH_RX_DESC_AVAIL;
3047 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3049 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3050 struct bnxt_tx_ring_info *txr;
3051 struct bnxt_cp_ring_info *cpr;
3052 struct bnxt_sw_tx_bd *tx_buf;
3053 struct tx_pkt_cmpl *txcmp;
3054 uint32_t cons, cp_cons;
3060 rc = is_bnxt_in_error(txq->bp);
3067 if (offset >= txq->nb_tx_desc)
3070 cons = RING_CMP(cpr->cp_ring_struct, offset);
3071 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3072 cp_cons = cpr->cp_raw_cons;
3074 if (cons > cp_cons) {
3075 if (CMPL_VALID(txcmp, cpr->valid))
3076 return RTE_ETH_TX_DESC_UNAVAIL;
3078 if (CMPL_VALID(txcmp, !cpr->valid))
3079 return RTE_ETH_TX_DESC_UNAVAIL;
3081 tx_buf = &txr->tx_buf_ring[cons];
3082 if (tx_buf->mbuf == NULL)
3083 return RTE_ETH_TX_DESC_DONE;
3085 return RTE_ETH_TX_DESC_FULL;
3089 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3090 enum rte_filter_type filter_type,
3091 enum rte_filter_op filter_op, void *arg)
3093 struct bnxt *bp = dev->data->dev_private;
3099 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3100 struct bnxt_representor *vfr = dev->data->dev_private;
3101 bp = vfr->parent_dev->data->dev_private;
3102 /* parent is deleted while children are still valid */
3104 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3112 ret = is_bnxt_in_error(bp);
3116 switch (filter_type) {
3117 case RTE_ETH_FILTER_GENERIC:
3118 if (filter_op != RTE_ETH_FILTER_GET)
3121 /* PMD supports thread-safe flow operations. rte_flow API
3122 * functions can avoid mutex for multi-thread safety.
3124 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3126 if (BNXT_TRUFLOW_EN(bp))
3127 *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3129 *(const void **)arg = &bnxt_flow_ops;
3133 "Filter type (%d) not supported", filter_type);
3140 static const uint32_t *
3141 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3143 static const uint32_t ptypes[] = {
3144 RTE_PTYPE_L2_ETHER_VLAN,
3145 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3146 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3150 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3151 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3152 RTE_PTYPE_INNER_L4_ICMP,
3153 RTE_PTYPE_INNER_L4_TCP,
3154 RTE_PTYPE_INNER_L4_UDP,
3158 if (!dev->rx_pkt_burst)
3164 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3167 uint32_t reg_base = *reg_arr & 0xfffff000;
3171 for (i = 0; i < count; i++) {
3172 if ((reg_arr[i] & 0xfffff000) != reg_base)
3175 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3176 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3180 static int bnxt_map_ptp_regs(struct bnxt *bp)
3182 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3186 reg_arr = ptp->rx_regs;
3187 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3191 reg_arr = ptp->tx_regs;
3192 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3196 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3197 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3199 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3200 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3205 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3207 rte_write32(0, (uint8_t *)bp->bar0 +
3208 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3209 rte_write32(0, (uint8_t *)bp->bar0 +
3210 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3213 static uint64_t bnxt_cc_read(struct bnxt *bp)
3217 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3218 BNXT_GRCPF_REG_SYNC_TIME));
3219 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3220 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3224 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3226 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3229 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3230 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3231 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3234 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3235 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3236 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3237 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3238 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3239 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3244 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3246 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3247 struct bnxt_pf_info *pf = bp->pf;
3254 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3255 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3256 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3259 port_id = pf->port_id;
3260 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3261 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3263 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3264 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3265 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3266 /* bnxt_clr_rx_ts(bp); TBD */
3270 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3271 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3272 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3273 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3279 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3282 struct bnxt *bp = dev->data->dev_private;
3283 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3288 ns = rte_timespec_to_ns(ts);
3289 /* Set the timecounters to a new value. */
3296 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3298 struct bnxt *bp = dev->data->dev_private;
3299 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3300 uint64_t ns, systime_cycles = 0;
3306 if (BNXT_CHIP_P5(bp))
3307 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3310 systime_cycles = bnxt_cc_read(bp);
3312 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3313 *ts = rte_ns_to_timespec(ns);
3318 bnxt_timesync_enable(struct rte_eth_dev *dev)
3320 struct bnxt *bp = dev->data->dev_private;
3321 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3329 ptp->tx_tstamp_en = 1;
3330 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3332 rc = bnxt_hwrm_ptp_cfg(bp);
3336 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3337 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3338 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3340 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3341 ptp->tc.cc_shift = shift;
3342 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3344 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3345 ptp->rx_tstamp_tc.cc_shift = shift;
3346 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3348 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3349 ptp->tx_tstamp_tc.cc_shift = shift;
3350 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3352 if (!BNXT_CHIP_P5(bp))
3353 bnxt_map_ptp_regs(bp);
3359 bnxt_timesync_disable(struct rte_eth_dev *dev)
3361 struct bnxt *bp = dev->data->dev_private;
3362 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3368 ptp->tx_tstamp_en = 0;
3371 bnxt_hwrm_ptp_cfg(bp);
3373 if (!BNXT_CHIP_P5(bp))
3374 bnxt_unmap_ptp_regs(bp);
3380 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3381 struct timespec *timestamp,
3382 uint32_t flags __rte_unused)
3384 struct bnxt *bp = dev->data->dev_private;
3385 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3386 uint64_t rx_tstamp_cycles = 0;
3392 if (BNXT_CHIP_P5(bp))
3393 rx_tstamp_cycles = ptp->rx_timestamp;
3395 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3397 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3398 *timestamp = rte_ns_to_timespec(ns);
3403 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3404 struct timespec *timestamp)
3406 struct bnxt *bp = dev->data->dev_private;
3407 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3408 uint64_t tx_tstamp_cycles = 0;
3415 if (BNXT_CHIP_P5(bp))
3416 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3419 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3421 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3422 *timestamp = rte_ns_to_timespec(ns);
3428 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3430 struct bnxt *bp = dev->data->dev_private;
3431 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3436 ptp->tc.nsec += delta;
3442 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3444 struct bnxt *bp = dev->data->dev_private;
3446 uint32_t dir_entries;
3447 uint32_t entry_length;
3449 rc = is_bnxt_in_error(bp);
3453 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3454 bp->pdev->addr.domain, bp->pdev->addr.bus,
3455 bp->pdev->addr.devid, bp->pdev->addr.function);
3457 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3461 return dir_entries * entry_length;
3465 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3466 struct rte_dev_eeprom_info *in_eeprom)
3468 struct bnxt *bp = dev->data->dev_private;
3473 rc = is_bnxt_in_error(bp);
3477 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3478 bp->pdev->addr.domain, bp->pdev->addr.bus,
3479 bp->pdev->addr.devid, bp->pdev->addr.function,
3480 in_eeprom->offset, in_eeprom->length);
3482 if (in_eeprom->offset == 0) /* special offset value to get directory */
3483 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3486 index = in_eeprom->offset >> 24;
3487 offset = in_eeprom->offset & 0xffffff;
3490 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3491 in_eeprom->length, in_eeprom->data);
3496 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3499 case BNX_DIR_TYPE_CHIMP_PATCH:
3500 case BNX_DIR_TYPE_BOOTCODE:
3501 case BNX_DIR_TYPE_BOOTCODE_2:
3502 case BNX_DIR_TYPE_APE_FW:
3503 case BNX_DIR_TYPE_APE_PATCH:
3504 case BNX_DIR_TYPE_KONG_FW:
3505 case BNX_DIR_TYPE_KONG_PATCH:
3506 case BNX_DIR_TYPE_BONO_FW:
3507 case BNX_DIR_TYPE_BONO_PATCH:
3515 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3518 case BNX_DIR_TYPE_AVS:
3519 case BNX_DIR_TYPE_EXP_ROM_MBA:
3520 case BNX_DIR_TYPE_PCIE:
3521 case BNX_DIR_TYPE_TSCF_UCODE:
3522 case BNX_DIR_TYPE_EXT_PHY:
3523 case BNX_DIR_TYPE_CCM:
3524 case BNX_DIR_TYPE_ISCSI_BOOT:
3525 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3526 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3534 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3536 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3537 bnxt_dir_type_is_other_exec_format(dir_type);
3541 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3542 struct rte_dev_eeprom_info *in_eeprom)
3544 struct bnxt *bp = dev->data->dev_private;
3545 uint8_t index, dir_op;
3546 uint16_t type, ext, ordinal, attr;
3549 rc = is_bnxt_in_error(bp);
3553 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3554 bp->pdev->addr.domain, bp->pdev->addr.bus,
3555 bp->pdev->addr.devid, bp->pdev->addr.function,
3556 in_eeprom->offset, in_eeprom->length);
3559 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3563 type = in_eeprom->magic >> 16;
3565 if (type == 0xffff) { /* special value for directory operations */
3566 index = in_eeprom->magic & 0xff;
3567 dir_op = in_eeprom->magic >> 8;
3571 case 0x0e: /* erase */
3572 if (in_eeprom->offset != ~in_eeprom->magic)
3574 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3580 /* Create or re-write an NVM item: */
3581 if (bnxt_dir_type_is_executable(type) == true)
3583 ext = in_eeprom->magic & 0xffff;
3584 ordinal = in_eeprom->offset >> 16;
3585 attr = in_eeprom->offset & 0xffff;
3587 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3588 in_eeprom->data, in_eeprom->length);
3595 static const struct eth_dev_ops bnxt_dev_ops = {
3596 .dev_infos_get = bnxt_dev_info_get_op,
3597 .dev_close = bnxt_dev_close_op,
3598 .dev_configure = bnxt_dev_configure_op,
3599 .dev_start = bnxt_dev_start_op,
3600 .dev_stop = bnxt_dev_stop_op,
3601 .dev_set_link_up = bnxt_dev_set_link_up_op,
3602 .dev_set_link_down = bnxt_dev_set_link_down_op,
3603 .stats_get = bnxt_stats_get_op,
3604 .stats_reset = bnxt_stats_reset_op,
3605 .rx_queue_setup = bnxt_rx_queue_setup_op,
3606 .rx_queue_release = bnxt_rx_queue_release_op,
3607 .tx_queue_setup = bnxt_tx_queue_setup_op,
3608 .tx_queue_release = bnxt_tx_queue_release_op,
3609 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3610 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3611 .reta_update = bnxt_reta_update_op,
3612 .reta_query = bnxt_reta_query_op,
3613 .rss_hash_update = bnxt_rss_hash_update_op,
3614 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3615 .link_update = bnxt_link_update_op,
3616 .promiscuous_enable = bnxt_promiscuous_enable_op,
3617 .promiscuous_disable = bnxt_promiscuous_disable_op,
3618 .allmulticast_enable = bnxt_allmulticast_enable_op,
3619 .allmulticast_disable = bnxt_allmulticast_disable_op,
3620 .mac_addr_add = bnxt_mac_addr_add_op,
3621 .mac_addr_remove = bnxt_mac_addr_remove_op,
3622 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3623 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3624 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3625 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3626 .vlan_filter_set = bnxt_vlan_filter_set_op,
3627 .vlan_offload_set = bnxt_vlan_offload_set_op,
3628 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3629 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3630 .mtu_set = bnxt_mtu_set_op,
3631 .mac_addr_set = bnxt_set_default_mac_addr_op,
3632 .xstats_get = bnxt_dev_xstats_get_op,
3633 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3634 .xstats_reset = bnxt_dev_xstats_reset_op,
3635 .fw_version_get = bnxt_fw_version_get,
3636 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3637 .rxq_info_get = bnxt_rxq_info_get_op,
3638 .txq_info_get = bnxt_txq_info_get_op,
3639 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3640 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3641 .dev_led_on = bnxt_dev_led_on_op,
3642 .dev_led_off = bnxt_dev_led_off_op,
3643 .rx_queue_start = bnxt_rx_queue_start,
3644 .rx_queue_stop = bnxt_rx_queue_stop,
3645 .tx_queue_start = bnxt_tx_queue_start,
3646 .tx_queue_stop = bnxt_tx_queue_stop,
3647 .filter_ctrl = bnxt_filter_ctrl_op,
3648 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3649 .get_eeprom_length = bnxt_get_eeprom_length_op,
3650 .get_eeprom = bnxt_get_eeprom_op,
3651 .set_eeprom = bnxt_set_eeprom_op,
3652 .timesync_enable = bnxt_timesync_enable,
3653 .timesync_disable = bnxt_timesync_disable,
3654 .timesync_read_time = bnxt_timesync_read_time,
3655 .timesync_write_time = bnxt_timesync_write_time,
3656 .timesync_adjust_time = bnxt_timesync_adjust_time,
3657 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3658 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3661 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3665 /* Only pre-map the reset GRC registers using window 3 */
3666 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3667 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3669 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3674 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3676 struct bnxt_error_recovery_info *info = bp->recovery_info;
3677 uint32_t reg_base = 0xffffffff;
3680 /* Only pre-map the monitoring GRC registers using window 2 */
3681 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3682 uint32_t reg = info->status_regs[i];
3684 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3687 if (reg_base == 0xffffffff)
3688 reg_base = reg & 0xfffff000;
3689 if ((reg & 0xfffff000) != reg_base)
3692 /* Use mask 0xffc as the Lower 2 bits indicates
3693 * address space location
3695 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3699 if (reg_base == 0xffffffff)
3702 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3703 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3708 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3710 struct bnxt_error_recovery_info *info = bp->recovery_info;
3711 uint32_t delay = info->delay_after_reset[index];
3712 uint32_t val = info->reset_reg_val[index];
3713 uint32_t reg = info->reset_reg[index];
3714 uint32_t type, offset;
3716 type = BNXT_FW_STATUS_REG_TYPE(reg);
3717 offset = BNXT_FW_STATUS_REG_OFF(reg);
3720 case BNXT_FW_STATUS_REG_TYPE_CFG:
3721 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3723 case BNXT_FW_STATUS_REG_TYPE_GRC:
3724 offset = bnxt_map_reset_regs(bp, offset);
3725 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3727 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3728 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3731 /* wait on a specific interval of time until core reset is complete */
3733 rte_delay_ms(delay);
3736 static void bnxt_dev_cleanup(struct bnxt *bp)
3738 bp->eth_dev->data->dev_link.link_status = 0;
3739 bp->link_info->link_up = 0;
3740 if (bp->eth_dev->data->dev_started)
3741 bnxt_dev_stop(bp->eth_dev);
3743 bnxt_uninit_resources(bp, true);
3746 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3748 struct rte_eth_dev *dev = bp->eth_dev;
3749 struct rte_vlan_filter_conf *vfc;
3753 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3754 vfc = &dev->data->vlan_filter_conf;
3755 vidx = vlan_id / 64;
3756 vbit = vlan_id % 64;
3758 /* Each bit corresponds to a VLAN id */
3759 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3760 rc = bnxt_add_vlan_filter(bp, vlan_id);
3769 static int bnxt_restore_mac_filters(struct bnxt *bp)
3771 struct rte_eth_dev *dev = bp->eth_dev;
3772 struct rte_eth_dev_info dev_info;
3773 struct rte_ether_addr *addr;
3779 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3782 rc = bnxt_dev_info_get_op(dev, &dev_info);
3786 /* replay MAC address configuration */
3787 for (i = 1; i < dev_info.max_mac_addrs; i++) {
3788 addr = &dev->data->mac_addrs[i];
3790 /* skip zero address */
3791 if (rte_is_zero_ether_addr(addr))
3795 pool_mask = dev->data->mac_pool_sel[i];
3798 if (pool_mask & 1ULL) {
3799 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3805 } while (pool_mask);
3811 static int bnxt_restore_filters(struct bnxt *bp)
3813 struct rte_eth_dev *dev = bp->eth_dev;
3816 if (dev->data->all_multicast) {
3817 ret = bnxt_allmulticast_enable_op(dev);
3821 if (dev->data->promiscuous) {
3822 ret = bnxt_promiscuous_enable_op(dev);
3827 ret = bnxt_restore_mac_filters(bp);
3831 ret = bnxt_restore_vlan_filters(bp);
3832 /* TODO restore other filters as well */
3836 static void bnxt_dev_recover(void *arg)
3838 struct bnxt *bp = arg;
3839 int timeout = bp->fw_reset_max_msecs;
3842 pthread_mutex_lock(&bp->err_recovery_lock);
3843 /* Clear Error flag so that device re-init should happen */
3844 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
3847 rc = bnxt_hwrm_ver_get(bp, SHORT_HWRM_CMD_TIMEOUT);
3850 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
3851 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
3852 } while (rc && timeout);
3855 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
3859 rc = bnxt_init_resources(bp, true);
3862 "Failed to initialize resources after reset\n");
3865 /* clear reset flag as the device is initialized now */
3866 bp->flags &= ~BNXT_FLAG_FW_RESET;
3868 rc = bnxt_dev_start_op(bp->eth_dev);
3870 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
3874 rc = bnxt_restore_filters(bp);
3878 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
3879 pthread_mutex_unlock(&bp->err_recovery_lock);
3883 bnxt_dev_stop(bp->eth_dev);
3885 bp->flags |= BNXT_FLAG_FATAL_ERROR;
3886 bnxt_uninit_resources(bp, false);
3887 pthread_mutex_unlock(&bp->err_recovery_lock);
3888 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
3891 void bnxt_dev_reset_and_resume(void *arg)
3893 struct bnxt *bp = arg;
3896 bnxt_dev_cleanup(bp);
3898 bnxt_wait_for_device_shutdown(bp);
3900 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
3901 bnxt_dev_recover, (void *)bp);
3903 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
3906 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
3908 struct bnxt_error_recovery_info *info = bp->recovery_info;
3909 uint32_t reg = info->status_regs[index];
3910 uint32_t type, offset, val = 0;
3912 type = BNXT_FW_STATUS_REG_TYPE(reg);
3913 offset = BNXT_FW_STATUS_REG_OFF(reg);
3916 case BNXT_FW_STATUS_REG_TYPE_CFG:
3917 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
3919 case BNXT_FW_STATUS_REG_TYPE_GRC:
3920 offset = info->mapped_status_regs[index];
3922 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3923 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3931 static int bnxt_fw_reset_all(struct bnxt *bp)
3933 struct bnxt_error_recovery_info *info = bp->recovery_info;
3937 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3938 /* Reset through master function driver */
3939 for (i = 0; i < info->reg_array_cnt; i++)
3940 bnxt_write_fw_reset_reg(bp, i);
3941 /* Wait for time specified by FW after triggering reset */
3942 rte_delay_ms(info->master_func_wait_period_after_reset);
3943 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
3944 /* Reset with the help of Kong processor */
3945 rc = bnxt_hwrm_fw_reset(bp);
3947 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
3953 static void bnxt_fw_reset_cb(void *arg)
3955 struct bnxt *bp = arg;
3956 struct bnxt_error_recovery_info *info = bp->recovery_info;
3959 /* Only Master function can do FW reset */
3960 if (bnxt_is_master_func(bp) &&
3961 bnxt_is_recovery_enabled(bp)) {
3962 rc = bnxt_fw_reset_all(bp);
3964 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
3969 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
3970 * EXCEPTION_FATAL_ASYNC event to all the functions
3971 * (including MASTER FUNC). After receiving this Async, all the active
3972 * drivers should treat this case as FW initiated recovery
3974 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
3975 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
3976 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
3978 /* To recover from error */
3979 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
3984 /* Driver should poll FW heartbeat, reset_counter with the frequency
3985 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
3986 * When the driver detects heartbeat stop or change in reset_counter,
3987 * it has to trigger a reset to recover from the error condition.
3988 * A “master PF” is the function who will have the privilege to
3989 * initiate the chimp reset. The master PF will be elected by the
3990 * firmware and will be notified through async message.
3992 static void bnxt_check_fw_health(void *arg)
3994 struct bnxt *bp = arg;
3995 struct bnxt_error_recovery_info *info = bp->recovery_info;
3996 uint32_t val = 0, wait_msec;
3998 if (!info || !bnxt_is_recovery_enabled(bp) ||
3999 is_bnxt_in_error(bp))
4002 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4003 if (val == info->last_heart_beat)
4006 info->last_heart_beat = val;
4008 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4009 if (val != info->last_reset_counter)
4012 info->last_reset_counter = val;
4014 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4015 bnxt_check_fw_health, (void *)bp);
4019 /* Stop DMA to/from device */
4020 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4021 bp->flags |= BNXT_FLAG_FW_RESET;
4023 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4025 if (bnxt_is_master_func(bp))
4026 wait_msec = info->master_func_wait_period;
4028 wait_msec = info->normal_func_wait_period;
4030 rte_eal_alarm_set(US_PER_MS * wait_msec,
4031 bnxt_fw_reset_cb, (void *)bp);
4034 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4036 uint32_t polling_freq;
4038 pthread_mutex_lock(&bp->health_check_lock);
4040 if (!bnxt_is_recovery_enabled(bp))
4043 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4046 polling_freq = bp->recovery_info->driver_polling_freq;
4048 rte_eal_alarm_set(US_PER_MS * polling_freq,
4049 bnxt_check_fw_health, (void *)bp);
4050 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4053 pthread_mutex_unlock(&bp->health_check_lock);
4056 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4058 if (!bnxt_is_recovery_enabled(bp))
4061 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4062 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4065 static bool bnxt_vf_pciid(uint16_t device_id)
4067 switch (device_id) {
4068 case BROADCOM_DEV_ID_57304_VF:
4069 case BROADCOM_DEV_ID_57406_VF:
4070 case BROADCOM_DEV_ID_5731X_VF:
4071 case BROADCOM_DEV_ID_5741X_VF:
4072 case BROADCOM_DEV_ID_57414_VF:
4073 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4074 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4075 case BROADCOM_DEV_ID_58802_VF:
4076 case BROADCOM_DEV_ID_57500_VF1:
4077 case BROADCOM_DEV_ID_57500_VF2:
4078 case BROADCOM_DEV_ID_58818_VF:
4086 /* Phase 5 device */
4087 static bool bnxt_p5_device(uint16_t device_id)
4089 switch (device_id) {
4090 case BROADCOM_DEV_ID_57508:
4091 case BROADCOM_DEV_ID_57504:
4092 case BROADCOM_DEV_ID_57502:
4093 case BROADCOM_DEV_ID_57508_MF1:
4094 case BROADCOM_DEV_ID_57504_MF1:
4095 case BROADCOM_DEV_ID_57502_MF1:
4096 case BROADCOM_DEV_ID_57508_MF2:
4097 case BROADCOM_DEV_ID_57504_MF2:
4098 case BROADCOM_DEV_ID_57502_MF2:
4099 case BROADCOM_DEV_ID_57500_VF1:
4100 case BROADCOM_DEV_ID_57500_VF2:
4101 case BROADCOM_DEV_ID_58812:
4102 case BROADCOM_DEV_ID_58814:
4103 case BROADCOM_DEV_ID_58818:
4104 case BROADCOM_DEV_ID_58818_VF:
4112 bool bnxt_stratus_device(struct bnxt *bp)
4114 uint16_t device_id = bp->pdev->id.device_id;
4116 switch (device_id) {
4117 case BROADCOM_DEV_ID_STRATUS_NIC:
4118 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4119 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4127 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4129 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4130 struct bnxt *bp = eth_dev->data->dev_private;
4132 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4133 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4134 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4135 if (!bp->bar0 || !bp->doorbell_base) {
4136 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4140 bp->eth_dev = eth_dev;
4146 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4147 struct bnxt_ctx_pg_info *ctx_pg,
4152 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4153 const struct rte_memzone *mz = NULL;
4154 char mz_name[RTE_MEMZONE_NAMESIZE];
4155 rte_iova_t mz_phys_addr;
4156 uint64_t valid_bits = 0;
4163 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4165 rmem->page_size = BNXT_PAGE_SIZE;
4166 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4167 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4168 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4170 valid_bits = PTU_PTE_VALID;
4172 if (rmem->nr_pages > 1) {
4173 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4174 "bnxt_ctx_pg_tbl%s_%x_%d",
4175 suffix, idx, bp->eth_dev->data->port_id);
4176 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4177 mz = rte_memzone_lookup(mz_name);
4179 mz = rte_memzone_reserve_aligned(mz_name,
4183 RTE_MEMZONE_SIZE_HINT_ONLY |
4184 RTE_MEMZONE_IOVA_CONTIG,
4190 memset(mz->addr, 0, mz->len);
4191 mz_phys_addr = mz->iova;
4193 rmem->pg_tbl = mz->addr;
4194 rmem->pg_tbl_map = mz_phys_addr;
4195 rmem->pg_tbl_mz = mz;
4198 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4199 suffix, idx, bp->eth_dev->data->port_id);
4200 mz = rte_memzone_lookup(mz_name);
4202 mz = rte_memzone_reserve_aligned(mz_name,
4206 RTE_MEMZONE_SIZE_HINT_ONLY |
4207 RTE_MEMZONE_IOVA_CONTIG,
4213 memset(mz->addr, 0, mz->len);
4214 mz_phys_addr = mz->iova;
4216 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4217 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4218 rmem->dma_arr[i] = mz_phys_addr + sz;
4220 if (rmem->nr_pages > 1) {
4221 if (i == rmem->nr_pages - 2 &&
4222 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4223 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4224 else if (i == rmem->nr_pages - 1 &&
4225 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4226 valid_bits |= PTU_PTE_LAST;
4228 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4234 if (rmem->vmem_size)
4235 rmem->vmem = (void **)mz->addr;
4236 rmem->dma_arr[0] = mz_phys_addr;
4240 static void bnxt_free_ctx_mem(struct bnxt *bp)
4244 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4247 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4248 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4249 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4250 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4251 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4252 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4253 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4254 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4255 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4256 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4257 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4259 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4260 if (bp->ctx->tqm_mem[i])
4261 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4268 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4270 #define min_t(type, x, y) ({ \
4271 type __min1 = (x); \
4272 type __min2 = (y); \
4273 __min1 < __min2 ? __min1 : __min2; })
4275 #define max_t(type, x, y) ({ \
4276 type __max1 = (x); \
4277 type __max2 = (y); \
4278 __max1 > __max2 ? __max1 : __max2; })
4280 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4282 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4284 struct bnxt_ctx_pg_info *ctx_pg;
4285 struct bnxt_ctx_mem_info *ctx;
4286 uint32_t mem_size, ena, entries;
4287 uint32_t entries_sp, min;
4290 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4292 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4296 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4299 ctx_pg = &ctx->qp_mem;
4300 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4301 if (ctx->qp_entry_size) {
4302 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4303 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4308 ctx_pg = &ctx->srq_mem;
4309 ctx_pg->entries = ctx->srq_max_l2_entries;
4310 if (ctx->srq_entry_size) {
4311 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4312 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4317 ctx_pg = &ctx->cq_mem;
4318 ctx_pg->entries = ctx->cq_max_l2_entries;
4319 if (ctx->cq_entry_size) {
4320 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4321 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4326 ctx_pg = &ctx->vnic_mem;
4327 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4328 ctx->vnic_max_ring_table_entries;
4329 if (ctx->vnic_entry_size) {
4330 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4331 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4336 ctx_pg = &ctx->stat_mem;
4337 ctx_pg->entries = ctx->stat_max_entries;
4338 if (ctx->stat_entry_size) {
4339 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4340 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4345 min = ctx->tqm_min_entries_per_ring;
4347 entries_sp = ctx->qp_max_l2_entries +
4348 ctx->vnic_max_vnic_entries +
4349 2 * ctx->qp_min_qp1_entries + min;
4350 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4352 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4353 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4354 entries = clamp_t(uint32_t, entries, min,
4355 ctx->tqm_max_entries_per_ring);
4356 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4357 ctx_pg = ctx->tqm_mem[i];
4358 ctx_pg->entries = i ? entries : entries_sp;
4359 if (ctx->tqm_entry_size) {
4360 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4361 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i);
4365 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4368 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4369 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4372 "Failed to configure context mem: rc = %d\n", rc);
4374 ctx->flags |= BNXT_CTX_FLAG_INITED;
4379 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4381 struct rte_pci_device *pci_dev = bp->pdev;
4382 char mz_name[RTE_MEMZONE_NAMESIZE];
4383 const struct rte_memzone *mz = NULL;
4384 uint32_t total_alloc_len;
4385 rte_iova_t mz_phys_addr;
4387 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4390 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4391 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4392 pci_dev->addr.bus, pci_dev->addr.devid,
4393 pci_dev->addr.function, "rx_port_stats");
4394 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4395 mz = rte_memzone_lookup(mz_name);
4397 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4398 sizeof(struct rx_port_stats_ext) + 512);
4400 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4403 RTE_MEMZONE_SIZE_HINT_ONLY |
4404 RTE_MEMZONE_IOVA_CONTIG);
4408 memset(mz->addr, 0, mz->len);
4409 mz_phys_addr = mz->iova;
4411 bp->rx_mem_zone = (const void *)mz;
4412 bp->hw_rx_port_stats = mz->addr;
4413 bp->hw_rx_port_stats_map = mz_phys_addr;
4415 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4416 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4417 pci_dev->addr.bus, pci_dev->addr.devid,
4418 pci_dev->addr.function, "tx_port_stats");
4419 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4420 mz = rte_memzone_lookup(mz_name);
4422 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4423 sizeof(struct tx_port_stats_ext) + 512);
4425 mz = rte_memzone_reserve(mz_name,
4429 RTE_MEMZONE_SIZE_HINT_ONLY |
4430 RTE_MEMZONE_IOVA_CONTIG);
4434 memset(mz->addr, 0, mz->len);
4435 mz_phys_addr = mz->iova;
4437 bp->tx_mem_zone = (const void *)mz;
4438 bp->hw_tx_port_stats = mz->addr;
4439 bp->hw_tx_port_stats_map = mz_phys_addr;
4440 bp->flags |= BNXT_FLAG_PORT_STATS;
4442 /* Display extended statistics if FW supports it */
4443 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4444 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4445 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4448 bp->hw_rx_port_stats_ext = (void *)
4449 ((uint8_t *)bp->hw_rx_port_stats +
4450 sizeof(struct rx_port_stats));
4451 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4452 sizeof(struct rx_port_stats);
4453 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4455 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4456 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4457 bp->hw_tx_port_stats_ext = (void *)
4458 ((uint8_t *)bp->hw_tx_port_stats +
4459 sizeof(struct tx_port_stats));
4460 bp->hw_tx_port_stats_ext_map =
4461 bp->hw_tx_port_stats_map +
4462 sizeof(struct tx_port_stats);
4463 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4469 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4471 struct bnxt *bp = eth_dev->data->dev_private;
4474 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4475 RTE_ETHER_ADDR_LEN *
4478 if (eth_dev->data->mac_addrs == NULL) {
4479 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4483 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4487 /* Generate a random MAC address, if none was assigned by PF */
4488 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4489 bnxt_eth_hw_addr_random(bp->mac_addr);
4491 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4492 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4493 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4495 rc = bnxt_hwrm_set_mac(bp);
4500 /* Copy the permanent MAC from the FUNC_QCAPS response */
4501 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4506 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4510 /* MAC is already configured in FW */
4511 if (BNXT_HAS_DFLT_MAC_SET(bp))
4514 /* Restore the old MAC configured */
4515 rc = bnxt_hwrm_set_mac(bp);
4517 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4522 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4527 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4529 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4530 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4531 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4532 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4533 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4534 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4538 bnxt_get_svif(uint16_t port_id, bool func_svif,
4539 enum bnxt_ulp_intf_type type)
4541 struct rte_eth_dev *eth_dev;
4544 eth_dev = &rte_eth_devices[port_id];
4545 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4546 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4550 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4553 eth_dev = vfr->parent_dev;
4556 bp = eth_dev->data->dev_private;
4558 return func_svif ? bp->func_svif : bp->port_svif;
4562 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4564 struct rte_eth_dev *eth_dev;
4565 struct bnxt_vnic_info *vnic;
4568 eth_dev = &rte_eth_devices[port];
4569 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4570 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4574 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4575 return vfr->dflt_vnic_id;
4577 eth_dev = vfr->parent_dev;
4580 bp = eth_dev->data->dev_private;
4582 vnic = BNXT_GET_DEFAULT_VNIC(bp);
4584 return vnic->fw_vnic_id;
4588 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4590 struct rte_eth_dev *eth_dev;
4593 eth_dev = &rte_eth_devices[port];
4594 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4595 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4599 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4602 eth_dev = vfr->parent_dev;
4605 bp = eth_dev->data->dev_private;
4610 enum bnxt_ulp_intf_type
4611 bnxt_get_interface_type(uint16_t port)
4613 struct rte_eth_dev *eth_dev;
4616 eth_dev = &rte_eth_devices[port];
4617 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4618 return BNXT_ULP_INTF_TYPE_VF_REP;
4620 bp = eth_dev->data->dev_private;
4622 return BNXT_ULP_INTF_TYPE_PF;
4623 else if (BNXT_VF_IS_TRUSTED(bp))
4624 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4625 else if (BNXT_VF(bp))
4626 return BNXT_ULP_INTF_TYPE_VF;
4628 return BNXT_ULP_INTF_TYPE_INVALID;
4632 bnxt_get_phy_port_id(uint16_t port_id)
4634 struct bnxt_representor *vfr;
4635 struct rte_eth_dev *eth_dev;
4638 eth_dev = &rte_eth_devices[port_id];
4639 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4640 vfr = eth_dev->data->dev_private;
4644 eth_dev = vfr->parent_dev;
4647 bp = eth_dev->data->dev_private;
4649 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4653 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4655 struct rte_eth_dev *eth_dev;
4658 eth_dev = &rte_eth_devices[port_id];
4659 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4660 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4664 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4665 return vfr->fw_fid - 1;
4667 eth_dev = vfr->parent_dev;
4670 bp = eth_dev->data->dev_private;
4672 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
4676 bnxt_get_vport(uint16_t port_id)
4678 return (1 << bnxt_get_phy_port_id(port_id));
4681 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4683 struct bnxt_error_recovery_info *info = bp->recovery_info;
4686 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4687 memset(info, 0, sizeof(*info));
4691 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4694 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4697 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4699 bp->recovery_info = info;
4702 static void bnxt_check_fw_status(struct bnxt *bp)
4706 if (!(bp->recovery_info &&
4707 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
4710 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
4711 if (fw_status != BNXT_FW_STATUS_HEALTHY)
4712 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
4716 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
4718 struct bnxt_error_recovery_info *info = bp->recovery_info;
4719 uint32_t status_loc;
4722 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
4723 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4724 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4725 BNXT_GRCP_WINDOW_2_BASE +
4726 offsetof(struct hcomm_status,
4728 /* If the signature is absent, then FW does not support this feature */
4729 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
4730 HCOMM_STATUS_SIGNATURE_VAL)
4734 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4738 bp->recovery_info = info;
4740 memset(info, 0, sizeof(*info));
4743 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4744 BNXT_GRCP_WINDOW_2_BASE +
4745 offsetof(struct hcomm_status,
4748 /* Only pre-map the FW health status GRC register */
4749 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
4752 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
4753 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
4754 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
4756 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
4757 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4759 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
4764 /* This function gets the FW version along with the
4765 * capabilities(MAX and current) of the function, vnic,
4766 * error recovery, phy and other chip related info
4768 static int bnxt_get_config(struct bnxt *bp)
4775 rc = bnxt_map_hcomm_fw_status_reg(bp);
4779 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4781 bnxt_check_fw_status(bp);
4785 rc = bnxt_hwrm_func_reset(bp);
4789 rc = bnxt_hwrm_vnic_qcaps(bp);
4793 rc = bnxt_hwrm_queue_qportcfg(bp);
4797 /* Get the MAX capabilities for this function.
4798 * This function also allocates context memory for TQM rings and
4799 * informs the firmware about this allocated backing store memory.
4801 rc = bnxt_hwrm_func_qcaps(bp);
4805 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
4809 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
4813 bnxt_hwrm_port_mac_qcfg(bp);
4815 bnxt_hwrm_parent_pf_qcfg(bp);
4817 bnxt_hwrm_port_phy_qcaps(bp);
4819 bnxt_alloc_error_recovery_info(bp);
4820 /* Get the adapter error recovery support info */
4821 rc = bnxt_hwrm_error_recovery_qcfg(bp);
4823 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4825 bnxt_hwrm_port_led_qcaps(bp);
4831 bnxt_init_locks(struct bnxt *bp)
4835 err = pthread_mutex_init(&bp->flow_lock, NULL);
4837 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
4841 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
4843 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
4847 err = pthread_mutex_init(&bp->health_check_lock, NULL);
4849 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
4853 err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
4855 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
4860 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
4864 rc = bnxt_get_config(bp);
4868 if (!reconfig_dev) {
4869 rc = bnxt_setup_mac_addr(bp->eth_dev);
4873 rc = bnxt_restore_dflt_mac(bp);
4878 bnxt_config_vf_req_fwd(bp);
4880 rc = bnxt_hwrm_func_driver_register(bp);
4882 PMD_DRV_LOG(ERR, "Failed to register driver");
4887 if (bp->pdev->max_vfs) {
4888 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
4890 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
4894 rc = bnxt_hwrm_allocate_pf_only(bp);
4897 "Failed to allocate PF resources");
4903 rc = bnxt_alloc_mem(bp, reconfig_dev);
4907 rc = bnxt_setup_int(bp);
4911 rc = bnxt_request_int(bp);
4915 rc = bnxt_init_ctx_mem(bp);
4917 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
4925 bnxt_parse_devarg_truflow(__rte_unused const char *key,
4926 const char *value, void *opaque_arg)
4928 struct bnxt *bp = opaque_arg;
4929 unsigned long truflow;
4932 if (!value || !opaque_arg) {
4934 "Invalid parameter passed to truflow devargs.\n");
4938 truflow = strtoul(value, &end, 10);
4939 if (end == NULL || *end != '\0' ||
4940 (truflow == ULONG_MAX && errno == ERANGE)) {
4942 "Invalid parameter passed to truflow devargs.\n");
4946 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
4948 "Invalid value passed to truflow devargs.\n");
4953 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
4954 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
4956 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
4957 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
4964 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
4965 const char *value, void *opaque_arg)
4967 struct bnxt *bp = opaque_arg;
4968 unsigned long flow_xstat;
4971 if (!value || !opaque_arg) {
4973 "Invalid parameter passed to flow_xstat devarg.\n");
4977 flow_xstat = strtoul(value, &end, 10);
4978 if (end == NULL || *end != '\0' ||
4979 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
4981 "Invalid parameter passed to flow_xstat devarg.\n");
4985 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
4987 "Invalid value passed to flow_xstat devarg.\n");
4991 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
4992 if (BNXT_FLOW_XSTATS_EN(bp))
4993 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
4999 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5000 const char *value, void *opaque_arg)
5002 struct bnxt *bp = opaque_arg;
5003 unsigned long max_num_kflows;
5006 if (!value || !opaque_arg) {
5008 "Invalid parameter passed to max_num_kflows devarg.\n");
5012 max_num_kflows = strtoul(value, &end, 10);
5013 if (end == NULL || *end != '\0' ||
5014 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5016 "Invalid parameter passed to max_num_kflows devarg.\n");
5020 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5022 "Invalid value passed to max_num_kflows devarg.\n");
5026 bp->max_num_kflows = max_num_kflows;
5027 if (bp->max_num_kflows)
5028 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5035 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5036 const char *value, void *opaque_arg)
5038 struct bnxt_representor *vfr_bp = opaque_arg;
5039 unsigned long rep_is_pf;
5042 if (!value || !opaque_arg) {
5044 "Invalid parameter passed to rep_is_pf devargs.\n");
5048 rep_is_pf = strtoul(value, &end, 10);
5049 if (end == NULL || *end != '\0' ||
5050 (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5052 "Invalid parameter passed to rep_is_pf devargs.\n");
5056 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5058 "Invalid value passed to rep_is_pf devargs.\n");
5062 vfr_bp->flags |= rep_is_pf;
5063 if (BNXT_REP_PF(vfr_bp))
5064 PMD_DRV_LOG(INFO, "PF representor\n");
5066 PMD_DRV_LOG(INFO, "VF representor\n");
5072 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5073 const char *value, void *opaque_arg)
5075 struct bnxt_representor *vfr_bp = opaque_arg;
5076 unsigned long rep_based_pf;
5079 if (!value || !opaque_arg) {
5081 "Invalid parameter passed to rep_based_pf "
5086 rep_based_pf = strtoul(value, &end, 10);
5087 if (end == NULL || *end != '\0' ||
5088 (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5090 "Invalid parameter passed to rep_based_pf "
5095 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5097 "Invalid value passed to rep_based_pf devargs.\n");
5101 vfr_bp->rep_based_pf = rep_based_pf;
5102 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5104 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5110 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5111 const char *value, void *opaque_arg)
5113 struct bnxt_representor *vfr_bp = opaque_arg;
5114 unsigned long rep_q_r2f;
5117 if (!value || !opaque_arg) {
5119 "Invalid parameter passed to rep_q_r2f "
5124 rep_q_r2f = strtoul(value, &end, 10);
5125 if (end == NULL || *end != '\0' ||
5126 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5128 "Invalid parameter passed to rep_q_r2f "
5133 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5135 "Invalid value passed to rep_q_r2f devargs.\n");
5139 vfr_bp->rep_q_r2f = rep_q_r2f;
5140 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5141 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5147 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5148 const char *value, void *opaque_arg)
5150 struct bnxt_representor *vfr_bp = opaque_arg;
5151 unsigned long rep_q_f2r;
5154 if (!value || !opaque_arg) {
5156 "Invalid parameter passed to rep_q_f2r "
5161 rep_q_f2r = strtoul(value, &end, 10);
5162 if (end == NULL || *end != '\0' ||
5163 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5165 "Invalid parameter passed to rep_q_f2r "
5170 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5172 "Invalid value passed to rep_q_f2r devargs.\n");
5176 vfr_bp->rep_q_f2r = rep_q_f2r;
5177 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5178 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5184 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5185 const char *value, void *opaque_arg)
5187 struct bnxt_representor *vfr_bp = opaque_arg;
5188 unsigned long rep_fc_r2f;
5191 if (!value || !opaque_arg) {
5193 "Invalid parameter passed to rep_fc_r2f "
5198 rep_fc_r2f = strtoul(value, &end, 10);
5199 if (end == NULL || *end != '\0' ||
5200 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5202 "Invalid parameter passed to rep_fc_r2f "
5207 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5209 "Invalid value passed to rep_fc_r2f devargs.\n");
5213 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5214 vfr_bp->rep_fc_r2f = rep_fc_r2f;
5215 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5221 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5222 const char *value, void *opaque_arg)
5224 struct bnxt_representor *vfr_bp = opaque_arg;
5225 unsigned long rep_fc_f2r;
5228 if (!value || !opaque_arg) {
5230 "Invalid parameter passed to rep_fc_f2r "
5235 rep_fc_f2r = strtoul(value, &end, 10);
5236 if (end == NULL || *end != '\0' ||
5237 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5239 "Invalid parameter passed to rep_fc_f2r "
5244 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5246 "Invalid value passed to rep_fc_f2r devargs.\n");
5250 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5251 vfr_bp->rep_fc_f2r = rep_fc_f2r;
5252 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5258 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5260 struct rte_kvargs *kvlist;
5262 if (devargs == NULL)
5265 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5270 * Handler for "truflow" devarg.
5271 * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1"
5273 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5274 bnxt_parse_devarg_truflow, bp);
5277 * Handler for "flow_xstat" devarg.
5278 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5280 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5281 bnxt_parse_devarg_flow_xstat, bp);
5284 * Handler for "max_num_kflows" devarg.
5285 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5287 rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5288 bnxt_parse_devarg_max_num_kflows, bp);
5290 rte_kvargs_free(kvlist);
5293 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5297 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5298 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5301 "Failed to alloc switch domain: %d\n", rc);
5304 "Switch domain allocated %d\n",
5305 bp->switch_domain_id);
5311 /* Allocate and initialize various fields in bnxt struct that
5312 * need to be allocated/destroyed only once in the lifetime of the driver
5314 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5316 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5317 struct bnxt *bp = eth_dev->data->dev_private;
5320 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5322 if (bnxt_vf_pciid(pci_dev->id.device_id))
5323 bp->flags |= BNXT_FLAG_VF;
5325 if (bnxt_p5_device(pci_dev->id.device_id))
5326 bp->flags |= BNXT_FLAG_CHIP_P5;
5328 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5329 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5330 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5331 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5332 bp->flags |= BNXT_FLAG_STINGRAY;
5334 if (BNXT_TRUFLOW_EN(bp)) {
5335 /* extra mbuf field is required to store CFA code from mark */
5336 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5337 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5338 .size = sizeof(bnxt_cfa_code_dynfield_t),
5339 .align = __alignof__(bnxt_cfa_code_dynfield_t),
5341 bnxt_cfa_code_dynfield_offset =
5342 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5343 if (bnxt_cfa_code_dynfield_offset < 0) {
5345 "Failed to register mbuf field for TruFlow mark\n");
5350 rc = bnxt_map_pci_bars(eth_dev);
5353 "Failed to initialize board rc: %x\n", rc);
5357 rc = bnxt_alloc_pf_info(bp);
5361 rc = bnxt_alloc_link_info(bp);
5365 rc = bnxt_alloc_parent_info(bp);
5369 rc = bnxt_alloc_hwrm_resources(bp);
5372 "Failed to allocate hwrm resource rc: %x\n", rc);
5375 rc = bnxt_alloc_leds_info(bp);
5379 rc = bnxt_alloc_cos_queues(bp);
5383 rc = bnxt_init_locks(bp);
5387 rc = bnxt_alloc_switch_domain(bp);
5395 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5397 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5398 static int version_printed;
5402 if (version_printed++ == 0)
5403 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5405 eth_dev->dev_ops = &bnxt_dev_ops;
5406 eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5407 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5408 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5409 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5410 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5413 * For secondary processes, we don't initialise any further
5414 * as primary has already done this work.
5416 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5419 rte_eth_copy_pci_info(eth_dev, pci_dev);
5420 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5422 bp = eth_dev->data->dev_private;
5424 /* Parse dev arguments passed on when starting the DPDK application. */
5425 bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5427 rc = bnxt_drv_init(eth_dev);
5431 rc = bnxt_init_resources(bp, false);
5435 rc = bnxt_alloc_stats_mem(bp);
5440 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5441 pci_dev->mem_resource[0].phys_addr,
5442 pci_dev->mem_resource[0].addr);
5447 bnxt_dev_uninit(eth_dev);
5452 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5461 ctx->dma = RTE_BAD_IOVA;
5462 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5465 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5467 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5468 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5469 bp->flow_stat->rx_fc_out_tbl.ctx_id,
5470 bp->flow_stat->max_fc,
5473 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5474 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5475 bp->flow_stat->tx_fc_out_tbl.ctx_id,
5476 bp->flow_stat->max_fc,
5479 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5480 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5481 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5483 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5484 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5485 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5487 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5488 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5489 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5491 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5492 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5493 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5496 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5498 bnxt_unregister_fc_ctx_mem(bp);
5500 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5501 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5502 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5503 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5506 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5508 if (BNXT_FLOW_XSTATS_EN(bp))
5509 bnxt_uninit_fc_ctx_mem(bp);
5513 bnxt_free_error_recovery_info(struct bnxt *bp)
5515 rte_free(bp->recovery_info);
5516 bp->recovery_info = NULL;
5517 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5521 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5526 bnxt_free_mem(bp, reconfig_dev);
5528 bnxt_hwrm_func_buf_unrgtr(bp);
5529 rte_free(bp->pf->vf_req_buf);
5531 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5532 bp->flags &= ~BNXT_FLAG_REGISTERED;
5533 bnxt_free_ctx_mem(bp);
5534 if (!reconfig_dev) {
5535 bnxt_free_hwrm_resources(bp);
5536 bnxt_free_error_recovery_info(bp);
5539 bnxt_uninit_ctx_mem(bp);
5541 bnxt_free_flow_stats_info(bp);
5542 bnxt_free_rep_info(bp);
5543 rte_free(bp->ptp_cfg);
5549 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5551 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5554 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5556 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5557 bnxt_dev_close_op(eth_dev);
5562 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5564 struct bnxt *bp = eth_dev->data->dev_private;
5565 struct rte_eth_dev *vf_rep_eth_dev;
5571 for (i = 0; i < bp->num_reps; i++) {
5572 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5573 if (!vf_rep_eth_dev)
5575 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5576 vf_rep_eth_dev->data->port_id);
5577 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5579 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5580 eth_dev->data->port_id);
5581 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5586 static void bnxt_free_rep_info(struct bnxt *bp)
5588 rte_free(bp->rep_info);
5589 bp->rep_info = NULL;
5590 rte_free(bp->cfa_code_map);
5591 bp->cfa_code_map = NULL;
5594 static int bnxt_init_rep_info(struct bnxt *bp)
5601 bp->rep_info = rte_zmalloc("bnxt_rep_info",
5602 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5604 if (!bp->rep_info) {
5605 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5608 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5609 sizeof(*bp->cfa_code_map) *
5610 BNXT_MAX_CFA_CODE, 0);
5611 if (!bp->cfa_code_map) {
5612 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5613 bnxt_free_rep_info(bp);
5617 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5618 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5620 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5622 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5623 bnxt_free_rep_info(bp);
5627 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5629 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5630 bnxt_free_rep_info(bp);
5637 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5638 struct rte_eth_devargs *eth_da,
5639 struct rte_eth_dev *backing_eth_dev,
5640 const char *dev_args)
5642 struct rte_eth_dev *vf_rep_eth_dev;
5643 char name[RTE_ETH_NAME_MAX_LEN];
5644 struct bnxt *backing_bp;
5647 struct rte_kvargs *kvlist = NULL;
5649 num_rep = eth_da->nb_representor_ports;
5650 if (num_rep > BNXT_MAX_VF_REPS) {
5651 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5652 num_rep, BNXT_MAX_VF_REPS);
5656 if (num_rep >= RTE_MAX_ETHPORTS) {
5658 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5659 num_rep, RTE_MAX_ETHPORTS);
5663 backing_bp = backing_eth_dev->data->dev_private;
5665 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5667 "Not a PF or trusted VF. No Representor support\n");
5668 /* Returning an error is not an option.
5669 * Applications are not handling this correctly
5674 if (bnxt_init_rep_info(backing_bp))
5677 for (i = 0; i < num_rep; i++) {
5678 struct bnxt_representor representor = {
5679 .vf_id = eth_da->representor_ports[i],
5680 .switch_domain_id = backing_bp->switch_domain_id,
5681 .parent_dev = backing_eth_dev
5684 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5685 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5686 representor.vf_id, BNXT_MAX_VF_REPS);
5690 /* representor port net_bdf_port */
5691 snprintf(name, sizeof(name), "net_%s_representor_%d",
5692 pci_dev->device.name, eth_da->representor_ports[i]);
5694 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
5697 * Handler for "rep_is_pf" devarg.
5698 * Invoked as for ex: "-a 000:00:0d.0,
5699 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5701 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
5702 bnxt_parse_devarg_rep_is_pf,
5703 (void *)&representor);
5709 * Handler for "rep_based_pf" devarg.
5710 * Invoked as for ex: "-a 000:00:0d.0,
5711 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5713 ret = rte_kvargs_process(kvlist,
5714 BNXT_DEVARG_REP_BASED_PF,
5715 bnxt_parse_devarg_rep_based_pf,
5716 (void *)&representor);
5722 * Handler for "rep_based_pf" devarg.
5723 * Invoked as for ex: "-a 000:00:0d.0,
5724 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5726 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
5727 bnxt_parse_devarg_rep_q_r2f,
5728 (void *)&representor);
5734 * Handler for "rep_based_pf" devarg.
5735 * Invoked as for ex: "-a 000:00:0d.0,
5736 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5738 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
5739 bnxt_parse_devarg_rep_q_f2r,
5740 (void *)&representor);
5746 * Handler for "rep_based_pf" devarg.
5747 * Invoked as for ex: "-a 000:00:0d.0,
5748 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5750 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
5751 bnxt_parse_devarg_rep_fc_r2f,
5752 (void *)&representor);
5758 * Handler for "rep_based_pf" devarg.
5759 * Invoked as for ex: "-a 000:00:0d.0,
5760 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5762 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
5763 bnxt_parse_devarg_rep_fc_f2r,
5764 (void *)&representor);
5771 ret = rte_eth_dev_create(&pci_dev->device, name,
5772 sizeof(struct bnxt_representor),
5774 bnxt_representor_init,
5777 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
5778 "representor %s.", name);
5782 vf_rep_eth_dev = rte_eth_dev_allocated(name);
5783 if (!vf_rep_eth_dev) {
5784 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
5785 " for VF-Rep: %s.", name);
5790 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
5791 backing_eth_dev->data->port_id);
5792 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
5794 backing_bp->num_reps++;
5798 rte_kvargs_free(kvlist);
5802 /* If num_rep > 1, then rollback already created
5803 * ports, since we'll be failing the probe anyway
5806 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
5808 rte_kvargs_free(kvlist);
5813 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5814 struct rte_pci_device *pci_dev)
5816 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
5817 struct rte_eth_dev *backing_eth_dev;
5821 if (pci_dev->device.devargs) {
5822 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
5828 num_rep = eth_da.nb_representor_ports;
5829 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
5832 /* We could come here after first level of probe is already invoked
5833 * as part of an application bringup(OVS-DPDK vswitchd), so first check
5834 * for already allocated eth_dev for the backing device (PF/Trusted VF)
5836 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5837 if (backing_eth_dev == NULL) {
5838 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
5839 sizeof(struct bnxt),
5840 eth_dev_pci_specific_init, pci_dev,
5841 bnxt_dev_init, NULL);
5843 if (ret || !num_rep)
5846 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5848 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
5849 backing_eth_dev->data->port_id);
5854 /* probe representor ports now */
5855 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev,
5856 pci_dev->device.devargs->args);
5861 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
5863 struct rte_eth_dev *eth_dev;
5865 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
5867 return 0; /* Invoked typically only by OVS-DPDK, by the
5868 * time it comes here the eth_dev is already
5869 * deleted by rte_eth_dev_close(), so returning
5870 * +ve value will at least help in proper cleanup
5873 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
5874 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
5875 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
5876 return rte_eth_dev_destroy(eth_dev,
5877 bnxt_representor_uninit);
5879 return rte_eth_dev_destroy(eth_dev,
5882 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
5886 static struct rte_pci_driver bnxt_rte_pmd = {
5887 .id_table = bnxt_pci_id_map,
5888 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
5889 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
5892 .probe = bnxt_pci_probe,
5893 .remove = bnxt_pci_remove,
5897 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5899 if (strcmp(dev->device->driver->name, drv->driver.name))
5905 bool is_bnxt_supported(struct rte_eth_dev *dev)
5907 return is_device_supported(dev, &bnxt_rte_pmd);
5910 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
5911 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
5912 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
5913 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");