1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
30 #define DRV_MODULE_NAME "bnxt"
31 static const char bnxt_version[] =
32 "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
33 int bnxt_logtype_driver;
35 #define PCI_VENDOR_ID_BROADCOM 0x14E4
37 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
39 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
40 #define BROADCOM_DEV_ID_57414_VF 0x16c1
41 #define BROADCOM_DEV_ID_57301 0x16c8
42 #define BROADCOM_DEV_ID_57302 0x16c9
43 #define BROADCOM_DEV_ID_57304_PF 0x16ca
44 #define BROADCOM_DEV_ID_57304_VF 0x16cb
45 #define BROADCOM_DEV_ID_57417_MF 0x16cc
46 #define BROADCOM_DEV_ID_NS2 0x16cd
47 #define BROADCOM_DEV_ID_57311 0x16ce
48 #define BROADCOM_DEV_ID_57312 0x16cf
49 #define BROADCOM_DEV_ID_57402 0x16d0
50 #define BROADCOM_DEV_ID_57404 0x16d1
51 #define BROADCOM_DEV_ID_57406_PF 0x16d2
52 #define BROADCOM_DEV_ID_57406_VF 0x16d3
53 #define BROADCOM_DEV_ID_57402_MF 0x16d4
54 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
55 #define BROADCOM_DEV_ID_57412 0x16d6
56 #define BROADCOM_DEV_ID_57414 0x16d7
57 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
58 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
59 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
60 #define BROADCOM_DEV_ID_57412_MF 0x16de
61 #define BROADCOM_DEV_ID_57314 0x16df
62 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
63 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
64 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
65 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
66 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
67 #define BROADCOM_DEV_ID_57404_MF 0x16e7
68 #define BROADCOM_DEV_ID_57406_MF 0x16e8
69 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
70 #define BROADCOM_DEV_ID_57407_MF 0x16ea
71 #define BROADCOM_DEV_ID_57414_MF 0x16ec
72 #define BROADCOM_DEV_ID_57416_MF 0x16ee
73 #define BROADCOM_DEV_ID_58802 0xd802
74 #define BROADCOM_DEV_ID_58804 0xd804
75 #define BROADCOM_DEV_ID_58808 0x16f0
77 static const struct rte_pci_id bnxt_pci_id_map[] = {
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
79 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
81 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
119 { .vendor_id = 0, /* sentinel */ },
122 #define BNXT_ETH_RSS_SUPPORT ( \
124 ETH_RSS_NONFRAG_IPV4_TCP | \
125 ETH_RSS_NONFRAG_IPV4_UDP | \
127 ETH_RSS_NONFRAG_IPV6_TCP | \
128 ETH_RSS_NONFRAG_IPV6_UDP)
130 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
131 DEV_TX_OFFLOAD_IPV4_CKSUM | \
132 DEV_TX_OFFLOAD_TCP_CKSUM | \
133 DEV_TX_OFFLOAD_UDP_CKSUM | \
134 DEV_TX_OFFLOAD_TCP_TSO | \
135 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
136 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
137 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
138 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
139 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
140 DEV_TX_OFFLOAD_MULTI_SEGS)
142 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
143 DEV_RX_OFFLOAD_VLAN_STRIP | \
144 DEV_RX_OFFLOAD_IPV4_CKSUM | \
145 DEV_RX_OFFLOAD_UDP_CKSUM | \
146 DEV_RX_OFFLOAD_TCP_CKSUM | \
147 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
148 DEV_RX_OFFLOAD_JUMBO_FRAME | \
149 DEV_RX_OFFLOAD_CRC_STRIP | \
150 DEV_RX_OFFLOAD_TCP_LRO)
152 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
153 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
155 /***********************/
158 * High level utility functions
161 static void bnxt_free_mem(struct bnxt *bp)
163 bnxt_free_filter_mem(bp);
164 bnxt_free_vnic_attributes(bp);
165 bnxt_free_vnic_mem(bp);
168 bnxt_free_tx_rings(bp);
169 bnxt_free_rx_rings(bp);
170 bnxt_free_def_cp_ring(bp);
173 static int bnxt_alloc_mem(struct bnxt *bp)
177 /* Default completion ring */
178 rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
182 rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
183 bp->def_cp_ring, "def_cp");
187 rc = bnxt_alloc_vnic_mem(bp);
191 rc = bnxt_alloc_vnic_attributes(bp);
195 rc = bnxt_alloc_filter_mem(bp);
206 static int bnxt_init_chip(struct bnxt *bp)
209 struct rte_eth_link new;
210 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
211 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
212 uint32_t intr_vector = 0;
213 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
214 uint32_t vec = BNXT_MISC_VEC_ID;
217 /* disable uio/vfio intr/eventfd mapping */
218 rte_intr_disable(intr_handle);
220 if (bp->eth_dev->data->mtu > ETHER_MTU) {
221 bp->eth_dev->data->dev_conf.rxmode.offloads |=
222 DEV_RX_OFFLOAD_JUMBO_FRAME;
223 bp->flags |= BNXT_FLAG_JUMBO;
225 bp->eth_dev->data->dev_conf.rxmode.offloads &=
226 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
227 bp->flags &= ~BNXT_FLAG_JUMBO;
230 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
232 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
236 rc = bnxt_alloc_hwrm_rings(bp);
238 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
242 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
244 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
248 rc = bnxt_mq_rx_configure(bp);
250 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
254 /* VNIC configuration */
255 for (i = 0; i < bp->nr_vnics; i++) {
256 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
258 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
260 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
265 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
268 "HWRM vnic %d ctx alloc failure rc: %x\n",
273 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
275 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
280 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
283 "HWRM vnic %d filter failure rc: %x\n",
288 rc = bnxt_vnic_rss_configure(bp, vnic);
291 "HWRM vnic set RSS failure rc: %x\n", rc);
295 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
297 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
298 DEV_RX_OFFLOAD_TCP_LRO)
299 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
301 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
303 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
306 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
310 /* check and configure queue intr-vector mapping */
311 if ((rte_intr_cap_multiple(intr_handle) ||
312 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
313 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
314 intr_vector = bp->eth_dev->data->nb_rx_queues;
315 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
316 if (intr_vector > bp->rx_cp_nr_rings) {
317 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
321 if (rte_intr_efd_enable(intr_handle, intr_vector))
325 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
326 intr_handle->intr_vec =
327 rte_zmalloc("intr_vec",
328 bp->eth_dev->data->nb_rx_queues *
330 if (intr_handle->intr_vec == NULL) {
331 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
332 " intr_vec", bp->eth_dev->data->nb_rx_queues);
335 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
336 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
337 intr_handle->intr_vec, intr_handle->nb_efd,
338 intr_handle->max_intr);
341 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
343 intr_handle->intr_vec[queue_id] = vec;
344 if (vec < base + intr_handle->nb_efd - 1)
348 /* enable uio/vfio intr/eventfd mapping */
349 rte_intr_enable(intr_handle);
351 rc = bnxt_get_hwrm_link_config(bp, &new);
353 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
357 if (!bp->link_info.link_up) {
358 rc = bnxt_set_hwrm_link_config(bp, true);
361 "HWRM link config failure rc: %x\n", rc);
365 bnxt_print_link_info(bp->eth_dev);
370 bnxt_free_all_hwrm_resources(bp);
372 /* Some of the error status returned by FW may not be from errno.h */
379 static int bnxt_shutdown_nic(struct bnxt *bp)
381 bnxt_free_all_hwrm_resources(bp);
382 bnxt_free_all_filters(bp);
383 bnxt_free_all_vnics(bp);
387 static int bnxt_init_nic(struct bnxt *bp)
391 rc = bnxt_init_ring_grps(bp);
396 bnxt_init_filters(bp);
398 rc = bnxt_init_chip(bp);
406 * Device configuration and status function
409 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
410 struct rte_eth_dev_info *dev_info)
412 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
413 uint16_t max_vnics, i, j, vpool, vrxq;
414 unsigned int max_rx_rings;
417 dev_info->max_mac_addrs = bp->max_l2_ctx;
418 dev_info->max_hash_mac_addrs = 0;
420 /* PF/VF specifics */
422 dev_info->max_vfs = bp->pdev->max_vfs;
423 max_rx_rings = RTE_MIN(bp->max_vnics, RTE_MIN(bp->max_l2_ctx,
424 RTE_MIN(bp->max_rsscos_ctx,
426 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
427 dev_info->max_rx_queues = max_rx_rings;
428 dev_info->max_tx_queues = max_rx_rings;
429 dev_info->reta_size = bp->max_rsscos_ctx;
430 dev_info->hash_key_size = 40;
431 max_vnics = bp->max_vnics;
433 /* Fast path specifics */
434 dev_info->min_rx_bufsize = 1;
435 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
438 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
439 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
440 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
441 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
442 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
445 dev_info->default_rxconf = (struct rte_eth_rxconf) {
451 .rx_free_thresh = 32,
452 /* If no descriptors available, pkts are dropped by default */
456 dev_info->default_txconf = (struct rte_eth_txconf) {
462 .tx_free_thresh = 32,
465 eth_dev->data->dev_conf.intr_conf.lsc = 1;
467 eth_dev->data->dev_conf.intr_conf.rxq = 1;
472 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
473 * need further investigation.
477 vpool = 64; /* ETH_64_POOLS */
478 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
479 for (i = 0; i < 4; vpool >>= 1, i++) {
480 if (max_vnics > vpool) {
481 for (j = 0; j < 5; vrxq >>= 1, j++) {
482 if (dev_info->max_rx_queues > vrxq) {
488 /* Not enough resources to support VMDq */
492 /* Not enough resources to support VMDq */
496 dev_info->max_vmdq_pools = vpool;
497 dev_info->vmdq_queue_num = vrxq;
499 dev_info->vmdq_pool_base = 0;
500 dev_info->vmdq_queue_base = 0;
503 /* Configure the device based on the configuration provided */
504 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
506 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
507 uint64_t tx_offloads = eth_dev->data->dev_conf.txmode.offloads;
508 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
510 if (tx_offloads != (tx_offloads & BNXT_DEV_TX_OFFLOAD_SUPPORT)) {
513 "Tx offloads requested 0x%" PRIx64 " supported 0x%x\n",
514 tx_offloads, BNXT_DEV_TX_OFFLOAD_SUPPORT);
518 if (rx_offloads != (rx_offloads & BNXT_DEV_RX_OFFLOAD_SUPPORT)) {
521 "Rx offloads requested 0x%" PRIx64 " supported 0x%x\n",
522 rx_offloads, BNXT_DEV_RX_OFFLOAD_SUPPORT);
526 bp->rx_queues = (void *)eth_dev->data->rx_queues;
527 bp->tx_queues = (void *)eth_dev->data->tx_queues;
529 /* Inherit new configurations */
530 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
531 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
532 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues + 1 >
534 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
536 (uint32_t)(eth_dev->data->nb_rx_queues + 1) > bp->max_ring_grps) {
538 "Insufficient resources to support requested config\n");
540 "Num Queues Requested: Tx %d, Rx %d\n",
541 eth_dev->data->nb_tx_queues,
542 eth_dev->data->nb_rx_queues);
544 "Res available: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d\n",
545 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
546 bp->max_stat_ctx, bp->max_ring_grps);
550 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
551 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
552 bp->rx_cp_nr_rings = bp->rx_nr_rings;
553 bp->tx_cp_nr_rings = bp->tx_nr_rings;
555 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
557 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
558 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
562 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
564 struct rte_eth_link *link = ð_dev->data->dev_link;
566 if (link->link_status)
567 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
568 eth_dev->data->port_id,
569 (uint32_t)link->link_speed,
570 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
571 ("full-duplex") : ("half-duplex\n"));
573 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
574 eth_dev->data->port_id);
577 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
579 bnxt_print_link_info(eth_dev);
583 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
585 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
586 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
590 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
592 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
593 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
597 rc = bnxt_init_nic(bp);
601 bnxt_link_update_op(eth_dev, 1);
603 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
604 vlan_mask |= ETH_VLAN_FILTER_MASK;
605 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
606 vlan_mask |= ETH_VLAN_STRIP_MASK;
607 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
611 bp->flags |= BNXT_FLAG_INIT_DONE;
615 bnxt_shutdown_nic(bp);
616 bnxt_free_tx_mbufs(bp);
617 bnxt_free_rx_mbufs(bp);
621 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
623 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
626 if (!bp->link_info.link_up)
627 rc = bnxt_set_hwrm_link_config(bp, true);
629 eth_dev->data->dev_link.link_status = 1;
631 bnxt_print_link_info(eth_dev);
635 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
637 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
639 eth_dev->data->dev_link.link_status = 0;
640 bnxt_set_hwrm_link_config(bp, false);
641 bp->link_info.link_up = 0;
646 /* Unload the driver, release resources */
647 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
649 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
651 if (bp->eth_dev->data->dev_started) {
652 /* TBD: STOP HW queues DMA */
653 eth_dev->data->dev_link.link_status = 0;
655 bnxt_set_hwrm_link_config(bp, false);
656 bnxt_hwrm_port_clr_stats(bp);
657 bp->flags &= ~BNXT_FLAG_INIT_DONE;
658 bnxt_shutdown_nic(bp);
662 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
664 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
666 if (bp->dev_stopped == 0)
667 bnxt_dev_stop_op(eth_dev);
669 bnxt_free_tx_mbufs(bp);
670 bnxt_free_rx_mbufs(bp);
672 if (eth_dev->data->mac_addrs != NULL) {
673 rte_free(eth_dev->data->mac_addrs);
674 eth_dev->data->mac_addrs = NULL;
676 if (bp->grp_info != NULL) {
677 rte_free(bp->grp_info);
682 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
685 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
686 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
687 struct bnxt_vnic_info *vnic;
688 struct bnxt_filter_info *filter, *temp_filter;
689 uint32_t pool = RTE_MIN(MAX_FF_POOLS, ETH_64_POOLS);
693 * Loop through all VNICs from the specified filter flow pools to
694 * remove the corresponding MAC addr filter
696 for (i = 0; i < pool; i++) {
697 if (!(pool_mask & (1ULL << i)))
700 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
701 filter = STAILQ_FIRST(&vnic->filter);
703 temp_filter = STAILQ_NEXT(filter, next);
704 if (filter->mac_index == index) {
705 STAILQ_REMOVE(&vnic->filter, filter,
706 bnxt_filter_info, next);
707 bnxt_hwrm_clear_l2_filter(bp, filter);
708 filter->mac_index = INVALID_MAC_INDEX;
709 memset(&filter->l2_addr, 0,
712 &bp->free_filter_list,
715 filter = temp_filter;
721 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
722 struct ether_addr *mac_addr,
723 uint32_t index, uint32_t pool)
725 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
726 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
727 struct bnxt_filter_info *filter;
730 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
735 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
738 /* Attach requested MAC address to the new l2_filter */
739 STAILQ_FOREACH(filter, &vnic->filter, next) {
740 if (filter->mac_index == index) {
742 "MAC addr already existed for pool %d\n", pool);
746 filter = bnxt_alloc_filter(bp);
748 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
751 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
752 filter->mac_index = index;
753 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
754 return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
757 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
760 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
761 struct rte_eth_link new;
762 unsigned int cnt = BNXT_LINK_WAIT_CNT;
764 memset(&new, 0, sizeof(new));
766 /* Retrieve link info from hardware */
767 rc = bnxt_get_hwrm_link_config(bp, &new);
769 new.link_speed = ETH_LINK_SPEED_100M;
770 new.link_duplex = ETH_LINK_FULL_DUPLEX;
772 "Failed to retrieve link rc = 0x%x!\n", rc);
775 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
777 if (!wait_to_complete)
779 } while (!new.link_status && cnt--);
782 /* Timed out or success */
783 if (new.link_status != eth_dev->data->dev_link.link_status ||
784 new.link_speed != eth_dev->data->dev_link.link_speed) {
785 memcpy(ð_dev->data->dev_link, &new,
786 sizeof(struct rte_eth_link));
787 bnxt_print_link_info(eth_dev);
793 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
795 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
796 struct bnxt_vnic_info *vnic;
798 if (bp->vnic_info == NULL)
801 vnic = &bp->vnic_info[0];
803 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
804 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
807 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
809 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
810 struct bnxt_vnic_info *vnic;
812 if (bp->vnic_info == NULL)
815 vnic = &bp->vnic_info[0];
817 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
818 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
821 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
823 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
824 struct bnxt_vnic_info *vnic;
826 if (bp->vnic_info == NULL)
829 vnic = &bp->vnic_info[0];
831 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
832 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
835 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
837 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
838 struct bnxt_vnic_info *vnic;
840 if (bp->vnic_info == NULL)
843 vnic = &bp->vnic_info[0];
845 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
846 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
849 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
850 struct rte_eth_rss_reta_entry64 *reta_conf,
853 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
854 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
855 struct bnxt_vnic_info *vnic;
858 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
861 if (reta_size != HW_HASH_INDEX_SIZE) {
862 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
863 "(%d) must equal the size supported by the hardware "
864 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
867 /* Update the RSS VNIC(s) */
868 for (i = 0; i < MAX_FF_POOLS; i++) {
869 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
870 memcpy(vnic->rss_table, reta_conf, reta_size);
872 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
878 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
879 struct rte_eth_rss_reta_entry64 *reta_conf,
882 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
883 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
884 struct rte_intr_handle *intr_handle
885 = &bp->pdev->intr_handle;
887 /* Retrieve from the default VNIC */
890 if (!vnic->rss_table)
893 if (reta_size != HW_HASH_INDEX_SIZE) {
894 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
895 "(%d) must equal the size supported by the hardware "
896 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
899 /* EW - need to revisit here copying from uint64_t to uint16_t */
900 memcpy(reta_conf, vnic->rss_table, reta_size);
902 if (rte_intr_allow_others(intr_handle)) {
903 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
904 bnxt_dev_lsc_intr_setup(eth_dev);
910 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
911 struct rte_eth_rss_conf *rss_conf)
913 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
914 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
915 struct bnxt_vnic_info *vnic;
916 uint16_t hash_type = 0;
920 * If RSS enablement were different than dev_configure,
921 * then return -EINVAL
923 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
924 if (!rss_conf->rss_hf)
925 PMD_DRV_LOG(ERR, "Hash type NONE\n");
927 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
931 bp->flags |= BNXT_FLAG_UPDATE_HASH;
932 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
934 if (rss_conf->rss_hf & ETH_RSS_IPV4)
935 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
936 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
937 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
938 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
939 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
940 if (rss_conf->rss_hf & ETH_RSS_IPV6)
941 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
942 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
943 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
944 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
945 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
947 /* Update the RSS VNIC(s) */
948 for (i = 0; i < MAX_FF_POOLS; i++) {
949 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
950 vnic->hash_type = hash_type;
953 * Use the supplied key if the key length is
954 * acceptable and the rss_key is not NULL
956 if (rss_conf->rss_key &&
957 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
958 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
959 rss_conf->rss_key_len);
961 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
967 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
968 struct rte_eth_rss_conf *rss_conf)
970 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
971 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
975 /* RSS configuration is the same for all VNICs */
976 if (vnic && vnic->rss_hash_key) {
977 if (rss_conf->rss_key) {
978 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
979 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
980 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
983 hash_types = vnic->hash_type;
984 rss_conf->rss_hf = 0;
985 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
986 rss_conf->rss_hf |= ETH_RSS_IPV4;
987 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
989 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
990 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
992 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
994 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
995 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
997 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
999 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
1000 rss_conf->rss_hf |= ETH_RSS_IPV6;
1001 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
1003 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
1004 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
1006 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
1008 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1009 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1011 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1015 "Unknwon RSS config from firmware (%08x), RSS disabled",
1020 rss_conf->rss_hf = 0;
1025 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1026 struct rte_eth_fc_conf *fc_conf)
1028 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1029 struct rte_eth_link link_info;
1032 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1036 memset(fc_conf, 0, sizeof(*fc_conf));
1037 if (bp->link_info.auto_pause)
1038 fc_conf->autoneg = 1;
1039 switch (bp->link_info.pause) {
1041 fc_conf->mode = RTE_FC_NONE;
1043 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1044 fc_conf->mode = RTE_FC_TX_PAUSE;
1046 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1047 fc_conf->mode = RTE_FC_RX_PAUSE;
1049 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1050 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1051 fc_conf->mode = RTE_FC_FULL;
1057 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1058 struct rte_eth_fc_conf *fc_conf)
1060 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1062 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1063 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1067 switch (fc_conf->mode) {
1069 bp->link_info.auto_pause = 0;
1070 bp->link_info.force_pause = 0;
1072 case RTE_FC_RX_PAUSE:
1073 if (fc_conf->autoneg) {
1074 bp->link_info.auto_pause =
1075 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1076 bp->link_info.force_pause = 0;
1078 bp->link_info.auto_pause = 0;
1079 bp->link_info.force_pause =
1080 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1083 case RTE_FC_TX_PAUSE:
1084 if (fc_conf->autoneg) {
1085 bp->link_info.auto_pause =
1086 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1087 bp->link_info.force_pause = 0;
1089 bp->link_info.auto_pause = 0;
1090 bp->link_info.force_pause =
1091 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1095 if (fc_conf->autoneg) {
1096 bp->link_info.auto_pause =
1097 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1098 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1099 bp->link_info.force_pause = 0;
1101 bp->link_info.auto_pause = 0;
1102 bp->link_info.force_pause =
1103 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1104 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1108 return bnxt_set_hwrm_link_config(bp, true);
1111 /* Add UDP tunneling port */
1113 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1114 struct rte_eth_udp_tunnel *udp_tunnel)
1116 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1117 uint16_t tunnel_type = 0;
1120 switch (udp_tunnel->prot_type) {
1121 case RTE_TUNNEL_TYPE_VXLAN:
1122 if (bp->vxlan_port_cnt) {
1123 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1124 udp_tunnel->udp_port);
1125 if (bp->vxlan_port != udp_tunnel->udp_port) {
1126 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1129 bp->vxlan_port_cnt++;
1133 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1134 bp->vxlan_port_cnt++;
1136 case RTE_TUNNEL_TYPE_GENEVE:
1137 if (bp->geneve_port_cnt) {
1138 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1139 udp_tunnel->udp_port);
1140 if (bp->geneve_port != udp_tunnel->udp_port) {
1141 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1144 bp->geneve_port_cnt++;
1148 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1149 bp->geneve_port_cnt++;
1152 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1155 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1161 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1162 struct rte_eth_udp_tunnel *udp_tunnel)
1164 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1165 uint16_t tunnel_type = 0;
1169 switch (udp_tunnel->prot_type) {
1170 case RTE_TUNNEL_TYPE_VXLAN:
1171 if (!bp->vxlan_port_cnt) {
1172 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1175 if (bp->vxlan_port != udp_tunnel->udp_port) {
1176 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1177 udp_tunnel->udp_port, bp->vxlan_port);
1180 if (--bp->vxlan_port_cnt)
1184 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1185 port = bp->vxlan_fw_dst_port_id;
1187 case RTE_TUNNEL_TYPE_GENEVE:
1188 if (!bp->geneve_port_cnt) {
1189 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1192 if (bp->geneve_port != udp_tunnel->udp_port) {
1193 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1194 udp_tunnel->udp_port, bp->geneve_port);
1197 if (--bp->geneve_port_cnt)
1201 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1202 port = bp->geneve_fw_dst_port_id;
1205 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1209 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1212 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1215 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1216 bp->geneve_port = 0;
1221 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1223 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1224 struct bnxt_vnic_info *vnic;
1227 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1229 /* Cycle through all VNICs */
1230 for (i = 0; i < bp->nr_vnics; i++) {
1232 * For each VNIC and each associated filter(s)
1233 * if VLAN exists && VLAN matches vlan_id
1234 * remove the MAC+VLAN filter
1235 * add a new MAC only filter
1237 * VLAN filter doesn't exist, just skip and continue
1239 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1240 filter = STAILQ_FIRST(&vnic->filter);
1242 temp_filter = STAILQ_NEXT(filter, next);
1244 if (filter->enables & chk &&
1245 filter->l2_ovlan == vlan_id) {
1246 /* Must delete the filter */
1247 STAILQ_REMOVE(&vnic->filter, filter,
1248 bnxt_filter_info, next);
1249 bnxt_hwrm_clear_l2_filter(bp, filter);
1251 &bp->free_filter_list,
1255 * Need to examine to see if the MAC
1256 * filter already existed or not before
1257 * allocating a new one
1260 new_filter = bnxt_alloc_filter(bp);
1263 "MAC/VLAN filter alloc failed\n");
1267 STAILQ_INSERT_TAIL(&vnic->filter,
1269 /* Inherit MAC from previous filter */
1270 new_filter->mac_index =
1272 memcpy(new_filter->l2_addr,
1273 filter->l2_addr, ETHER_ADDR_LEN);
1274 /* MAC only filter */
1275 rc = bnxt_hwrm_set_l2_filter(bp,
1281 "Del Vlan filter for %d\n",
1284 filter = temp_filter;
1292 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1294 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1295 struct bnxt_vnic_info *vnic;
1298 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN |
1299 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK;
1300 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1302 /* Cycle through all VNICs */
1303 for (i = 0; i < bp->nr_vnics; i++) {
1305 * For each VNIC and each associated filter(s)
1307 * if VLAN matches vlan_id
1308 * VLAN filter already exists, just skip and continue
1310 * add a new MAC+VLAN filter
1312 * Remove the old MAC only filter
1313 * Add a new MAC+VLAN filter
1315 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1316 filter = STAILQ_FIRST(&vnic->filter);
1318 temp_filter = STAILQ_NEXT(filter, next);
1320 if (filter->enables & chk) {
1321 if (filter->l2_ovlan == vlan_id)
1324 /* Must delete the MAC filter */
1325 STAILQ_REMOVE(&vnic->filter, filter,
1326 bnxt_filter_info, next);
1327 bnxt_hwrm_clear_l2_filter(bp, filter);
1328 filter->l2_ovlan = 0;
1330 &bp->free_filter_list,
1333 new_filter = bnxt_alloc_filter(bp);
1336 "MAC/VLAN filter alloc failed\n");
1340 STAILQ_INSERT_TAIL(&vnic->filter, new_filter,
1342 /* Inherit MAC from the previous filter */
1343 new_filter->mac_index = filter->mac_index;
1344 memcpy(new_filter->l2_addr, filter->l2_addr,
1346 /* MAC + VLAN ID filter */
1347 new_filter->l2_ovlan = vlan_id;
1348 new_filter->l2_ovlan_mask = 0xF000;
1349 new_filter->enables |= en;
1350 rc = bnxt_hwrm_set_l2_filter(bp,
1356 "Added Vlan filter for %d\n", vlan_id);
1358 filter = temp_filter;
1366 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1367 uint16_t vlan_id, int on)
1369 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1371 /* These operations apply to ALL existing MAC/VLAN filters */
1373 return bnxt_add_vlan_filter(bp, vlan_id);
1375 return bnxt_del_vlan_filter(bp, vlan_id);
1379 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1381 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1382 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1385 if (mask & ETH_VLAN_FILTER_MASK) {
1386 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1387 /* Remove any VLAN filters programmed */
1388 for (i = 0; i < 4095; i++)
1389 bnxt_del_vlan_filter(bp, i);
1391 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1392 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1395 if (mask & ETH_VLAN_STRIP_MASK) {
1396 /* Enable or disable VLAN stripping */
1397 for (i = 0; i < bp->nr_vnics; i++) {
1398 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1399 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1400 vnic->vlan_strip = true;
1402 vnic->vlan_strip = false;
1403 bnxt_hwrm_vnic_cfg(bp, vnic);
1405 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1406 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1409 if (mask & ETH_VLAN_EXTEND_MASK)
1410 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1416 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr)
1418 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1419 /* Default Filter is tied to VNIC 0 */
1420 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1421 struct bnxt_filter_info *filter;
1427 memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1429 STAILQ_FOREACH(filter, &vnic->filter, next) {
1430 /* Default Filter is at Index 0 */
1431 if (filter->mac_index != 0)
1433 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1436 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN);
1437 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN);
1438 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1440 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1441 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1442 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1445 filter->mac_index = 0;
1446 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1453 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1454 struct ether_addr *mc_addr_set,
1455 uint32_t nb_mc_addr)
1457 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1458 char *mc_addr_list = (char *)mc_addr_set;
1459 struct bnxt_vnic_info *vnic;
1460 uint32_t off = 0, i = 0;
1462 vnic = &bp->vnic_info[0];
1464 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1465 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1469 /* TODO Check for Duplicate mcast addresses */
1470 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1471 for (i = 0; i < nb_mc_addr; i++) {
1472 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN);
1473 off += ETHER_ADDR_LEN;
1476 vnic->mc_addr_cnt = i;
1479 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1483 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1485 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1486 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1487 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1488 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1491 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1492 fw_major, fw_minor, fw_updt);
1494 ret += 1; /* add the size of '\0' */
1495 if (fw_size < (uint32_t)ret)
1502 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1503 struct rte_eth_rxq_info *qinfo)
1505 struct bnxt_rx_queue *rxq;
1507 rxq = dev->data->rx_queues[queue_id];
1509 qinfo->mp = rxq->mb_pool;
1510 qinfo->scattered_rx = dev->data->scattered_rx;
1511 qinfo->nb_desc = rxq->nb_rx_desc;
1513 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1514 qinfo->conf.rx_drop_en = 0;
1515 qinfo->conf.rx_deferred_start = 0;
1519 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1520 struct rte_eth_txq_info *qinfo)
1522 struct bnxt_tx_queue *txq;
1524 txq = dev->data->tx_queues[queue_id];
1526 qinfo->nb_desc = txq->nb_tx_desc;
1528 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1529 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1530 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1532 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1533 qinfo->conf.tx_rs_thresh = 0;
1534 qinfo->conf.txq_flags = txq->txq_flags;
1535 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1538 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1540 struct bnxt *bp = eth_dev->data->dev_private;
1541 struct rte_eth_dev_info dev_info;
1542 uint32_t max_dev_mtu;
1546 bnxt_dev_info_get_op(eth_dev, &dev_info);
1547 max_dev_mtu = dev_info.max_rx_pktlen -
1548 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2;
1550 if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) {
1551 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1552 ETHER_MIN_MTU, max_dev_mtu);
1557 if (new_mtu > ETHER_MTU) {
1558 bp->flags |= BNXT_FLAG_JUMBO;
1559 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1560 DEV_RX_OFFLOAD_JUMBO_FRAME;
1562 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1563 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1564 bp->flags &= ~BNXT_FLAG_JUMBO;
1567 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
1568 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1570 eth_dev->data->mtu = new_mtu;
1571 PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1573 for (i = 0; i < bp->nr_vnics; i++) {
1574 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1576 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1577 ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1578 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1582 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1591 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1593 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1594 uint16_t vlan = bp->vlan;
1597 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1599 "PVID cannot be modified for this function\n");
1602 bp->vlan = on ? pvid : 0;
1604 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1611 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1613 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1615 return bnxt_hwrm_port_led_cfg(bp, true);
1619 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1621 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1623 return bnxt_hwrm_port_led_cfg(bp, false);
1627 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1629 uint32_t desc = 0, raw_cons = 0, cons;
1630 struct bnxt_cp_ring_info *cpr;
1631 struct bnxt_rx_queue *rxq;
1632 struct rx_pkt_cmpl *rxcmp;
1637 rxq = dev->data->rx_queues[rx_queue_id];
1641 while (raw_cons < rxq->nb_rx_desc) {
1642 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1643 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1645 if (!CMPL_VALID(rxcmp, valid))
1647 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1648 cmp_type = CMP_TYPE(rxcmp);
1649 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1650 cmp = (rte_le_to_cpu_32(
1651 ((struct rx_tpa_end_cmpl *)
1652 (rxcmp))->agg_bufs_v1) &
1653 RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1654 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1656 } else if (cmp_type == 0x11) {
1658 cmp = (rxcmp->agg_bufs_v1 &
1659 RX_PKT_CMPL_AGG_BUFS_MASK) >>
1660 RX_PKT_CMPL_AGG_BUFS_SFT;
1665 raw_cons += cmp ? cmp : 2;
1672 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1674 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1675 struct bnxt_rx_ring_info *rxr;
1676 struct bnxt_cp_ring_info *cpr;
1677 struct bnxt_sw_rx_bd *rx_buf;
1678 struct rx_pkt_cmpl *rxcmp;
1679 uint32_t cons, cp_cons;
1687 if (offset >= rxq->nb_rx_desc)
1690 cons = RING_CMP(cpr->cp_ring_struct, offset);
1691 cp_cons = cpr->cp_raw_cons;
1692 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1694 if (cons > cp_cons) {
1695 if (CMPL_VALID(rxcmp, cpr->valid))
1696 return RTE_ETH_RX_DESC_DONE;
1698 if (CMPL_VALID(rxcmp, !cpr->valid))
1699 return RTE_ETH_RX_DESC_DONE;
1701 rx_buf = &rxr->rx_buf_ring[cons];
1702 if (rx_buf->mbuf == NULL)
1703 return RTE_ETH_RX_DESC_UNAVAIL;
1706 return RTE_ETH_RX_DESC_AVAIL;
1710 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1712 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1713 struct bnxt_tx_ring_info *txr;
1714 struct bnxt_cp_ring_info *cpr;
1715 struct bnxt_sw_tx_bd *tx_buf;
1716 struct tx_pkt_cmpl *txcmp;
1717 uint32_t cons, cp_cons;
1725 if (offset >= txq->nb_tx_desc)
1728 cons = RING_CMP(cpr->cp_ring_struct, offset);
1729 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1730 cp_cons = cpr->cp_raw_cons;
1732 if (cons > cp_cons) {
1733 if (CMPL_VALID(txcmp, cpr->valid))
1734 return RTE_ETH_TX_DESC_UNAVAIL;
1736 if (CMPL_VALID(txcmp, !cpr->valid))
1737 return RTE_ETH_TX_DESC_UNAVAIL;
1739 tx_buf = &txr->tx_buf_ring[cons];
1740 if (tx_buf->mbuf == NULL)
1741 return RTE_ETH_TX_DESC_DONE;
1743 return RTE_ETH_TX_DESC_FULL;
1746 static struct bnxt_filter_info *
1747 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1748 struct rte_eth_ethertype_filter *efilter,
1749 struct bnxt_vnic_info *vnic0,
1750 struct bnxt_vnic_info *vnic,
1753 struct bnxt_filter_info *mfilter = NULL;
1757 if (efilter->ether_type == ETHER_TYPE_IPv4 ||
1758 efilter->ether_type == ETHER_TYPE_IPv6) {
1759 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
1760 " ethertype filter.", efilter->ether_type);
1764 if (efilter->queue >= bp->rx_nr_rings) {
1765 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1770 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1771 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1773 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1778 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1779 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1780 if ((!memcmp(efilter->mac_addr.addr_bytes,
1781 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1783 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1784 mfilter->ethertype == efilter->ether_type)) {
1790 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1791 if ((!memcmp(efilter->mac_addr.addr_bytes,
1792 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1793 mfilter->ethertype == efilter->ether_type &&
1795 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
1809 bnxt_ethertype_filter(struct rte_eth_dev *dev,
1810 enum rte_filter_op filter_op,
1813 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1814 struct rte_eth_ethertype_filter *efilter =
1815 (struct rte_eth_ethertype_filter *)arg;
1816 struct bnxt_filter_info *bfilter, *filter1;
1817 struct bnxt_vnic_info *vnic, *vnic0;
1820 if (filter_op == RTE_ETH_FILTER_NOP)
1824 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
1829 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1830 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1832 switch (filter_op) {
1833 case RTE_ETH_FILTER_ADD:
1834 bnxt_match_and_validate_ether_filter(bp, efilter,
1839 bfilter = bnxt_get_unused_filter(bp);
1840 if (bfilter == NULL) {
1842 "Not enough resources for a new filter.\n");
1845 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
1846 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
1848 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
1850 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
1851 bfilter->ethertype = efilter->ether_type;
1852 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
1854 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
1855 if (filter1 == NULL) {
1860 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
1861 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
1863 bfilter->dst_id = vnic->fw_vnic_id;
1865 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1867 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
1870 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
1873 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
1875 case RTE_ETH_FILTER_DELETE:
1876 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
1878 if (ret == -EEXIST) {
1879 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
1881 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
1883 bnxt_free_filter(bp, filter1);
1884 } else if (ret == 0) {
1885 PMD_DRV_LOG(ERR, "No matching filter found\n");
1889 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
1895 bnxt_free_filter(bp, bfilter);
1901 parse_ntuple_filter(struct bnxt *bp,
1902 struct rte_eth_ntuple_filter *nfilter,
1903 struct bnxt_filter_info *bfilter)
1907 if (nfilter->queue >= bp->rx_nr_rings) {
1908 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
1912 switch (nfilter->dst_port_mask) {
1914 bfilter->dst_port_mask = -1;
1915 bfilter->dst_port = nfilter->dst_port;
1916 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
1917 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
1920 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
1924 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
1925 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1927 switch (nfilter->proto_mask) {
1929 if (nfilter->proto == 17) /* IPPROTO_UDP */
1930 bfilter->ip_protocol = 17;
1931 else if (nfilter->proto == 6) /* IPPROTO_TCP */
1932 bfilter->ip_protocol = 6;
1935 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1938 PMD_DRV_LOG(ERR, "invalid protocol mask.");
1942 switch (nfilter->dst_ip_mask) {
1944 bfilter->dst_ipaddr_mask[0] = -1;
1945 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
1946 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
1947 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
1950 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
1954 switch (nfilter->src_ip_mask) {
1956 bfilter->src_ipaddr_mask[0] = -1;
1957 bfilter->src_ipaddr[0] = nfilter->src_ip;
1958 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
1959 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
1962 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
1966 switch (nfilter->src_port_mask) {
1968 bfilter->src_port_mask = -1;
1969 bfilter->src_port = nfilter->src_port;
1970 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
1971 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
1974 PMD_DRV_LOG(ERR, "invalid src_port mask.");
1979 //nfilter->priority = (uint8_t)filter->priority;
1981 bfilter->enables = en;
1985 static struct bnxt_filter_info*
1986 bnxt_match_ntuple_filter(struct bnxt *bp,
1987 struct bnxt_filter_info *bfilter,
1988 struct bnxt_vnic_info **mvnic)
1990 struct bnxt_filter_info *mfilter = NULL;
1993 for (i = bp->nr_vnics - 1; i >= 0; i--) {
1994 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1995 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
1996 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
1997 bfilter->src_ipaddr_mask[0] ==
1998 mfilter->src_ipaddr_mask[0] &&
1999 bfilter->src_port == mfilter->src_port &&
2000 bfilter->src_port_mask == mfilter->src_port_mask &&
2001 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
2002 bfilter->dst_ipaddr_mask[0] ==
2003 mfilter->dst_ipaddr_mask[0] &&
2004 bfilter->dst_port == mfilter->dst_port &&
2005 bfilter->dst_port_mask == mfilter->dst_port_mask &&
2006 bfilter->flags == mfilter->flags &&
2007 bfilter->enables == mfilter->enables) {
2018 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2019 struct rte_eth_ntuple_filter *nfilter,
2020 enum rte_filter_op filter_op)
2022 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2023 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2026 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2027 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2031 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2032 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2036 bfilter = bnxt_get_unused_filter(bp);
2037 if (bfilter == NULL) {
2039 "Not enough resources for a new filter.\n");
2042 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2046 vnic = STAILQ_FIRST(&bp->ff_pool[nfilter->queue]);
2047 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2048 filter1 = STAILQ_FIRST(&vnic0->filter);
2049 if (filter1 == NULL) {
2054 bfilter->dst_id = vnic->fw_vnic_id;
2055 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2057 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2058 bfilter->ethertype = 0x800;
2059 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2061 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2063 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2064 bfilter->dst_id == mfilter->dst_id) {
2065 PMD_DRV_LOG(ERR, "filter exists.\n");
2068 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2069 bfilter->dst_id != mfilter->dst_id) {
2070 mfilter->dst_id = vnic->fw_vnic_id;
2071 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2072 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2073 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2074 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2075 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2078 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2079 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2084 if (filter_op == RTE_ETH_FILTER_ADD) {
2085 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2086 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2089 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2091 if (mfilter == NULL) {
2092 /* This should not happen. But for Coverity! */
2096 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2098 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2099 bnxt_free_filter(bp, mfilter);
2100 mfilter->fw_l2_filter_id = -1;
2101 bnxt_free_filter(bp, bfilter);
2102 bfilter->fw_l2_filter_id = -1;
2107 bfilter->fw_l2_filter_id = -1;
2108 bnxt_free_filter(bp, bfilter);
2113 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2114 enum rte_filter_op filter_op,
2117 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2120 if (filter_op == RTE_ETH_FILTER_NOP)
2124 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2129 switch (filter_op) {
2130 case RTE_ETH_FILTER_ADD:
2131 ret = bnxt_cfg_ntuple_filter(bp,
2132 (struct rte_eth_ntuple_filter *)arg,
2135 case RTE_ETH_FILTER_DELETE:
2136 ret = bnxt_cfg_ntuple_filter(bp,
2137 (struct rte_eth_ntuple_filter *)arg,
2141 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2149 bnxt_parse_fdir_filter(struct bnxt *bp,
2150 struct rte_eth_fdir_filter *fdir,
2151 struct bnxt_filter_info *filter)
2153 enum rte_fdir_mode fdir_mode =
2154 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2155 struct bnxt_vnic_info *vnic0, *vnic;
2156 struct bnxt_filter_info *filter1;
2160 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2163 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2164 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2166 switch (fdir->input.flow_type) {
2167 case RTE_ETH_FLOW_IPV4:
2168 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2170 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2171 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2172 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2173 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2174 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2175 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2176 filter->ip_addr_type =
2177 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2178 filter->src_ipaddr_mask[0] = 0xffffffff;
2179 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2180 filter->dst_ipaddr_mask[0] = 0xffffffff;
2181 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2182 filter->ethertype = 0x800;
2183 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2185 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2186 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2187 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2188 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2189 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2190 filter->dst_port_mask = 0xffff;
2191 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2192 filter->src_port_mask = 0xffff;
2193 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2194 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2195 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2196 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2197 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2198 filter->ip_protocol = 6;
2199 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2200 filter->ip_addr_type =
2201 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2202 filter->src_ipaddr_mask[0] = 0xffffffff;
2203 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2204 filter->dst_ipaddr_mask[0] = 0xffffffff;
2205 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2206 filter->ethertype = 0x800;
2207 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2209 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2210 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2211 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2212 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2213 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2214 filter->dst_port_mask = 0xffff;
2215 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2216 filter->src_port_mask = 0xffff;
2217 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2218 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2219 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2220 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2221 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2222 filter->ip_protocol = 17;
2223 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2224 filter->ip_addr_type =
2225 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2226 filter->src_ipaddr_mask[0] = 0xffffffff;
2227 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2228 filter->dst_ipaddr_mask[0] = 0xffffffff;
2229 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2230 filter->ethertype = 0x800;
2231 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2233 case RTE_ETH_FLOW_IPV6:
2234 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2236 filter->ip_addr_type =
2237 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2238 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2239 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2240 rte_memcpy(filter->src_ipaddr,
2241 fdir->input.flow.ipv6_flow.src_ip, 16);
2242 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2243 rte_memcpy(filter->dst_ipaddr,
2244 fdir->input.flow.ipv6_flow.dst_ip, 16);
2245 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2246 memset(filter->dst_ipaddr_mask, 0xff, 16);
2247 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2248 memset(filter->src_ipaddr_mask, 0xff, 16);
2249 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2250 filter->ethertype = 0x86dd;
2251 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2253 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2254 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2255 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2256 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2257 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2258 filter->dst_port_mask = 0xffff;
2259 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2260 filter->src_port_mask = 0xffff;
2261 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2262 filter->ip_addr_type =
2263 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2264 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2265 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2266 rte_memcpy(filter->src_ipaddr,
2267 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2268 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2269 rte_memcpy(filter->dst_ipaddr,
2270 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2271 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2272 memset(filter->dst_ipaddr_mask, 0xff, 16);
2273 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2274 memset(filter->src_ipaddr_mask, 0xff, 16);
2275 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2276 filter->ethertype = 0x86dd;
2277 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2279 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2280 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2281 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2282 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2283 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2284 filter->dst_port_mask = 0xffff;
2285 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2286 filter->src_port_mask = 0xffff;
2287 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2288 filter->ip_addr_type =
2289 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2290 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2291 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2292 rte_memcpy(filter->src_ipaddr,
2293 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2294 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2295 rte_memcpy(filter->dst_ipaddr,
2296 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2297 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2298 memset(filter->dst_ipaddr_mask, 0xff, 16);
2299 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2300 memset(filter->src_ipaddr_mask, 0xff, 16);
2301 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2302 filter->ethertype = 0x86dd;
2303 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2305 case RTE_ETH_FLOW_L2_PAYLOAD:
2306 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2307 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2309 case RTE_ETH_FLOW_VXLAN:
2310 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2312 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2313 filter->tunnel_type =
2314 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2315 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2317 case RTE_ETH_FLOW_NVGRE:
2318 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2320 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2321 filter->tunnel_type =
2322 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2323 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2325 case RTE_ETH_FLOW_UNKNOWN:
2326 case RTE_ETH_FLOW_RAW:
2327 case RTE_ETH_FLOW_FRAG_IPV4:
2328 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2329 case RTE_ETH_FLOW_FRAG_IPV6:
2330 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2331 case RTE_ETH_FLOW_IPV6_EX:
2332 case RTE_ETH_FLOW_IPV6_TCP_EX:
2333 case RTE_ETH_FLOW_IPV6_UDP_EX:
2334 case RTE_ETH_FLOW_GENEVE:
2340 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2341 vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2343 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2348 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2349 rte_memcpy(filter->dst_macaddr,
2350 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2351 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2354 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2355 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2356 filter1 = STAILQ_FIRST(&vnic0->filter);
2357 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2359 filter->dst_id = vnic->fw_vnic_id;
2360 for (i = 0; i < ETHER_ADDR_LEN; i++)
2361 if (filter->dst_macaddr[i] == 0x00)
2362 filter1 = STAILQ_FIRST(&vnic0->filter);
2364 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2367 if (filter1 == NULL)
2370 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2371 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2373 filter->enables = en;
2378 static struct bnxt_filter_info *
2379 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2380 struct bnxt_vnic_info **mvnic)
2382 struct bnxt_filter_info *mf = NULL;
2385 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2386 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2388 STAILQ_FOREACH(mf, &vnic->filter, next) {
2389 if (mf->filter_type == nf->filter_type &&
2390 mf->flags == nf->flags &&
2391 mf->src_port == nf->src_port &&
2392 mf->src_port_mask == nf->src_port_mask &&
2393 mf->dst_port == nf->dst_port &&
2394 mf->dst_port_mask == nf->dst_port_mask &&
2395 mf->ip_protocol == nf->ip_protocol &&
2396 mf->ip_addr_type == nf->ip_addr_type &&
2397 mf->ethertype == nf->ethertype &&
2398 mf->vni == nf->vni &&
2399 mf->tunnel_type == nf->tunnel_type &&
2400 mf->l2_ovlan == nf->l2_ovlan &&
2401 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2402 mf->l2_ivlan == nf->l2_ivlan &&
2403 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2404 !memcmp(mf->l2_addr, nf->l2_addr, ETHER_ADDR_LEN) &&
2405 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2407 !memcmp(mf->src_macaddr, nf->src_macaddr,
2409 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2411 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2412 sizeof(nf->src_ipaddr)) &&
2413 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2414 sizeof(nf->src_ipaddr_mask)) &&
2415 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2416 sizeof(nf->dst_ipaddr)) &&
2417 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2418 sizeof(nf->dst_ipaddr_mask))) {
2429 bnxt_fdir_filter(struct rte_eth_dev *dev,
2430 enum rte_filter_op filter_op,
2433 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2434 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2435 struct bnxt_filter_info *filter, *match;
2436 struct bnxt_vnic_info *vnic, *mvnic;
2439 if (filter_op == RTE_ETH_FILTER_NOP)
2442 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2445 switch (filter_op) {
2446 case RTE_ETH_FILTER_ADD:
2447 case RTE_ETH_FILTER_DELETE:
2448 filter = bnxt_get_unused_filter(bp);
2449 if (filter == NULL) {
2451 "Not enough resources for a new flow.\n");
2455 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2458 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2460 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2461 vnic = STAILQ_FIRST(&bp->ff_pool[0]);
2463 vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2465 match = bnxt_match_fdir(bp, filter, &mvnic);
2466 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2467 if (match->dst_id == vnic->fw_vnic_id) {
2468 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2472 match->dst_id = vnic->fw_vnic_id;
2473 ret = bnxt_hwrm_set_ntuple_filter(bp,
2476 STAILQ_REMOVE(&mvnic->filter, match,
2477 bnxt_filter_info, next);
2478 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2480 "Filter with matching pattern exist\n");
2482 "Updated it to new destination q\n");
2486 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2487 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2492 if (filter_op == RTE_ETH_FILTER_ADD) {
2493 ret = bnxt_hwrm_set_ntuple_filter(bp,
2498 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2500 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2501 STAILQ_REMOVE(&vnic->filter, match,
2502 bnxt_filter_info, next);
2503 bnxt_free_filter(bp, match);
2504 filter->fw_l2_filter_id = -1;
2505 bnxt_free_filter(bp, filter);
2508 case RTE_ETH_FILTER_FLUSH:
2509 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2510 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2512 STAILQ_FOREACH(filter, &vnic->filter, next) {
2513 if (filter->filter_type ==
2514 HWRM_CFA_NTUPLE_FILTER) {
2516 bnxt_hwrm_clear_ntuple_filter(bp,
2518 STAILQ_REMOVE(&vnic->filter, filter,
2519 bnxt_filter_info, next);
2524 case RTE_ETH_FILTER_UPDATE:
2525 case RTE_ETH_FILTER_STATS:
2526 case RTE_ETH_FILTER_INFO:
2527 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2530 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2537 filter->fw_l2_filter_id = -1;
2538 bnxt_free_filter(bp, filter);
2543 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2544 enum rte_filter_type filter_type,
2545 enum rte_filter_op filter_op, void *arg)
2549 switch (filter_type) {
2550 case RTE_ETH_FILTER_TUNNEL:
2552 "filter type: %d: To be implemented\n", filter_type);
2554 case RTE_ETH_FILTER_FDIR:
2555 ret = bnxt_fdir_filter(dev, filter_op, arg);
2557 case RTE_ETH_FILTER_NTUPLE:
2558 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2560 case RTE_ETH_FILTER_ETHERTYPE:
2561 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2563 case RTE_ETH_FILTER_GENERIC:
2564 if (filter_op != RTE_ETH_FILTER_GET)
2566 *(const void **)arg = &bnxt_flow_ops;
2570 "Filter type (%d) not supported", filter_type);
2577 static const uint32_t *
2578 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2580 static const uint32_t ptypes[] = {
2581 RTE_PTYPE_L2_ETHER_VLAN,
2582 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2583 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2587 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2588 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2589 RTE_PTYPE_INNER_L4_ICMP,
2590 RTE_PTYPE_INNER_L4_TCP,
2591 RTE_PTYPE_INNER_L4_UDP,
2595 if (dev->rx_pkt_burst == bnxt_recv_pkts)
2600 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2603 uint32_t reg_base = *reg_arr & 0xfffff000;
2607 for (i = 0; i < count; i++) {
2608 if ((reg_arr[i] & 0xfffff000) != reg_base)
2611 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2612 rte_cpu_to_le_32(rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off));
2616 static int bnxt_map_ptp_regs(struct bnxt *bp)
2618 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2622 reg_arr = ptp->rx_regs;
2623 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2627 reg_arr = ptp->tx_regs;
2628 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2632 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2633 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2635 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2636 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2641 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2643 rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2644 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16));
2645 rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2646 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20));
2649 static uint64_t bnxt_cc_read(struct bnxt *bp)
2653 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2654 BNXT_GRCPF_REG_SYNC_TIME));
2655 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2656 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2660 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2662 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2665 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2666 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2667 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2670 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2671 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2672 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2673 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2674 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2675 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2680 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2682 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2683 struct bnxt_pf_info *pf = &bp->pf;
2690 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2691 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2692 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2695 port_id = pf->port_id;
2696 rte_cpu_to_le_32(rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2697 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]));
2699 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2700 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2701 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2702 /* bnxt_clr_rx_ts(bp); TBD */
2706 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2707 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2708 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2709 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2715 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2718 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2719 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2724 ns = rte_timespec_to_ns(ts);
2725 /* Set the timecounters to a new value. */
2732 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2734 uint64_t ns, systime_cycles;
2735 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2736 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2741 systime_cycles = bnxt_cc_read(bp);
2742 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
2743 *ts = rte_ns_to_timespec(ns);
2748 bnxt_timesync_enable(struct rte_eth_dev *dev)
2750 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2751 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2758 ptp->tx_tstamp_en = 1;
2759 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
2761 if (!bnxt_hwrm_ptp_cfg(bp))
2762 bnxt_map_ptp_regs(bp);
2764 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
2765 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2766 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2768 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2769 ptp->tc.cc_shift = shift;
2770 ptp->tc.nsec_mask = (1ULL << shift) - 1;
2772 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2773 ptp->rx_tstamp_tc.cc_shift = shift;
2774 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2776 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2777 ptp->tx_tstamp_tc.cc_shift = shift;
2778 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2784 bnxt_timesync_disable(struct rte_eth_dev *dev)
2786 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2787 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2793 ptp->tx_tstamp_en = 0;
2796 bnxt_hwrm_ptp_cfg(bp);
2798 bnxt_unmap_ptp_regs(bp);
2804 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
2805 struct timespec *timestamp,
2806 uint32_t flags __rte_unused)
2808 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2809 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2810 uint64_t rx_tstamp_cycles = 0;
2816 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
2817 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
2818 *timestamp = rte_ns_to_timespec(ns);
2823 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
2824 struct timespec *timestamp)
2826 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2827 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2828 uint64_t tx_tstamp_cycles = 0;
2834 bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
2835 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
2836 *timestamp = rte_ns_to_timespec(ns);
2842 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
2844 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2845 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2850 ptp->tc.nsec += delta;
2856 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
2858 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2860 uint32_t dir_entries;
2861 uint32_t entry_length;
2863 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
2864 bp->pdev->addr.domain, bp->pdev->addr.bus,
2865 bp->pdev->addr.devid, bp->pdev->addr.function);
2867 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
2871 return dir_entries * entry_length;
2875 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
2876 struct rte_dev_eeprom_info *in_eeprom)
2878 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2882 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2883 "len = %d\n", bp->pdev->addr.domain,
2884 bp->pdev->addr.bus, bp->pdev->addr.devid,
2885 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2887 if (in_eeprom->offset == 0) /* special offset value to get directory */
2888 return bnxt_get_nvram_directory(bp, in_eeprom->length,
2891 index = in_eeprom->offset >> 24;
2892 offset = in_eeprom->offset & 0xffffff;
2895 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
2896 in_eeprom->length, in_eeprom->data);
2901 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
2904 case BNX_DIR_TYPE_CHIMP_PATCH:
2905 case BNX_DIR_TYPE_BOOTCODE:
2906 case BNX_DIR_TYPE_BOOTCODE_2:
2907 case BNX_DIR_TYPE_APE_FW:
2908 case BNX_DIR_TYPE_APE_PATCH:
2909 case BNX_DIR_TYPE_KONG_FW:
2910 case BNX_DIR_TYPE_KONG_PATCH:
2911 case BNX_DIR_TYPE_BONO_FW:
2912 case BNX_DIR_TYPE_BONO_PATCH:
2919 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
2922 case BNX_DIR_TYPE_AVS:
2923 case BNX_DIR_TYPE_EXP_ROM_MBA:
2924 case BNX_DIR_TYPE_PCIE:
2925 case BNX_DIR_TYPE_TSCF_UCODE:
2926 case BNX_DIR_TYPE_EXT_PHY:
2927 case BNX_DIR_TYPE_CCM:
2928 case BNX_DIR_TYPE_ISCSI_BOOT:
2929 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2930 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2937 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
2939 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2940 bnxt_dir_type_is_other_exec_format(dir_type);
2944 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
2945 struct rte_dev_eeprom_info *in_eeprom)
2947 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2948 uint8_t index, dir_op;
2949 uint16_t type, ext, ordinal, attr;
2951 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2952 "len = %d\n", bp->pdev->addr.domain,
2953 bp->pdev->addr.bus, bp->pdev->addr.devid,
2954 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2957 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
2961 type = in_eeprom->magic >> 16;
2963 if (type == 0xffff) { /* special value for directory operations */
2964 index = in_eeprom->magic & 0xff;
2965 dir_op = in_eeprom->magic >> 8;
2969 case 0x0e: /* erase */
2970 if (in_eeprom->offset != ~in_eeprom->magic)
2972 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
2978 /* Create or re-write an NVM item: */
2979 if (bnxt_dir_type_is_executable(type) == true)
2981 ext = in_eeprom->magic & 0xffff;
2982 ordinal = in_eeprom->offset >> 16;
2983 attr = in_eeprom->offset & 0xffff;
2985 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
2986 in_eeprom->data, in_eeprom->length);
2994 static const struct eth_dev_ops bnxt_dev_ops = {
2995 .dev_infos_get = bnxt_dev_info_get_op,
2996 .dev_close = bnxt_dev_close_op,
2997 .dev_configure = bnxt_dev_configure_op,
2998 .dev_start = bnxt_dev_start_op,
2999 .dev_stop = bnxt_dev_stop_op,
3000 .dev_set_link_up = bnxt_dev_set_link_up_op,
3001 .dev_set_link_down = bnxt_dev_set_link_down_op,
3002 .stats_get = bnxt_stats_get_op,
3003 .stats_reset = bnxt_stats_reset_op,
3004 .rx_queue_setup = bnxt_rx_queue_setup_op,
3005 .rx_queue_release = bnxt_rx_queue_release_op,
3006 .tx_queue_setup = bnxt_tx_queue_setup_op,
3007 .tx_queue_release = bnxt_tx_queue_release_op,
3008 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3009 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3010 .reta_update = bnxt_reta_update_op,
3011 .reta_query = bnxt_reta_query_op,
3012 .rss_hash_update = bnxt_rss_hash_update_op,
3013 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3014 .link_update = bnxt_link_update_op,
3015 .promiscuous_enable = bnxt_promiscuous_enable_op,
3016 .promiscuous_disable = bnxt_promiscuous_disable_op,
3017 .allmulticast_enable = bnxt_allmulticast_enable_op,
3018 .allmulticast_disable = bnxt_allmulticast_disable_op,
3019 .mac_addr_add = bnxt_mac_addr_add_op,
3020 .mac_addr_remove = bnxt_mac_addr_remove_op,
3021 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3022 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3023 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3024 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3025 .vlan_filter_set = bnxt_vlan_filter_set_op,
3026 .vlan_offload_set = bnxt_vlan_offload_set_op,
3027 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3028 .mtu_set = bnxt_mtu_set_op,
3029 .mac_addr_set = bnxt_set_default_mac_addr_op,
3030 .xstats_get = bnxt_dev_xstats_get_op,
3031 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3032 .xstats_reset = bnxt_dev_xstats_reset_op,
3033 .fw_version_get = bnxt_fw_version_get,
3034 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3035 .rxq_info_get = bnxt_rxq_info_get_op,
3036 .txq_info_get = bnxt_txq_info_get_op,
3037 .dev_led_on = bnxt_dev_led_on_op,
3038 .dev_led_off = bnxt_dev_led_off_op,
3039 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3040 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3041 .rx_queue_count = bnxt_rx_queue_count_op,
3042 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3043 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3044 .rx_queue_start = bnxt_rx_queue_start,
3045 .rx_queue_stop = bnxt_rx_queue_stop,
3046 .tx_queue_start = bnxt_tx_queue_start,
3047 .tx_queue_stop = bnxt_tx_queue_stop,
3048 .filter_ctrl = bnxt_filter_ctrl_op,
3049 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3050 .get_eeprom_length = bnxt_get_eeprom_length_op,
3051 .get_eeprom = bnxt_get_eeprom_op,
3052 .set_eeprom = bnxt_set_eeprom_op,
3053 .timesync_enable = bnxt_timesync_enable,
3054 .timesync_disable = bnxt_timesync_disable,
3055 .timesync_read_time = bnxt_timesync_read_time,
3056 .timesync_write_time = bnxt_timesync_write_time,
3057 .timesync_adjust_time = bnxt_timesync_adjust_time,
3058 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3059 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3062 static bool bnxt_vf_pciid(uint16_t id)
3064 if (id == BROADCOM_DEV_ID_57304_VF ||
3065 id == BROADCOM_DEV_ID_57406_VF ||
3066 id == BROADCOM_DEV_ID_5731X_VF ||
3067 id == BROADCOM_DEV_ID_5741X_VF ||
3068 id == BROADCOM_DEV_ID_57414_VF ||
3069 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 ||
3070 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2)
3075 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3077 struct bnxt *bp = eth_dev->data->dev_private;
3078 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3081 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3082 if (!pci_dev->mem_resource[0].addr) {
3084 "Cannot find PCI device base address, aborting\n");
3086 goto init_err_disable;
3089 bp->eth_dev = eth_dev;
3092 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3094 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3096 goto init_err_release;
3099 if (!pci_dev->mem_resource[2].addr) {
3101 "Cannot find PCI device BAR 2 address, aborting\n");
3103 goto init_err_release;
3105 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
3113 if (bp->doorbell_base)
3114 bp->doorbell_base = NULL;
3121 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
3123 #define ALLOW_FUNC(x) \
3125 typeof(x) arg = (x); \
3126 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3127 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3130 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3132 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3133 char mz_name[RTE_MEMZONE_NAMESIZE];
3134 const struct rte_memzone *mz = NULL;
3135 static int version_printed;
3136 uint32_t total_alloc_len;
3137 rte_iova_t mz_phys_addr;
3141 if (version_printed++ == 0)
3142 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3144 rte_eth_copy_pci_info(eth_dev, pci_dev);
3146 bp = eth_dev->data->dev_private;
3148 bp->dev_stopped = 1;
3150 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3153 if (bnxt_vf_pciid(pci_dev->id.device_id))
3154 bp->flags |= BNXT_FLAG_VF;
3156 rc = bnxt_init_board(eth_dev);
3159 "Board initialization failed rc: %x\n", rc);
3163 eth_dev->dev_ops = &bnxt_dev_ops;
3164 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3166 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3167 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3169 if (BNXT_PF(bp) && pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3170 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3171 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3172 pci_dev->addr.bus, pci_dev->addr.devid,
3173 pci_dev->addr.function, "rx_port_stats");
3174 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3175 mz = rte_memzone_lookup(mz_name);
3176 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3177 sizeof(struct rx_port_stats) + 512);
3179 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3182 RTE_MEMZONE_SIZE_HINT_ONLY |
3183 RTE_MEMZONE_IOVA_CONTIG);
3187 memset(mz->addr, 0, mz->len);
3188 mz_phys_addr = mz->iova;
3189 if ((unsigned long)mz->addr == mz_phys_addr) {
3190 PMD_DRV_LOG(WARNING,
3191 "Memzone physical address same as virtual.\n");
3192 PMD_DRV_LOG(WARNING,
3193 "Using rte_mem_virt2iova()\n");
3194 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3195 if (mz_phys_addr == 0) {
3197 "unable to map address to physical memory\n");
3202 bp->rx_mem_zone = (const void *)mz;
3203 bp->hw_rx_port_stats = mz->addr;
3204 bp->hw_rx_port_stats_map = mz_phys_addr;
3206 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3207 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3208 pci_dev->addr.bus, pci_dev->addr.devid,
3209 pci_dev->addr.function, "tx_port_stats");
3210 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3211 mz = rte_memzone_lookup(mz_name);
3212 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3213 sizeof(struct tx_port_stats) + 512);
3215 mz = rte_memzone_reserve(mz_name,
3219 RTE_MEMZONE_SIZE_HINT_ONLY |
3220 RTE_MEMZONE_IOVA_CONTIG);
3224 memset(mz->addr, 0, mz->len);
3225 mz_phys_addr = mz->iova;
3226 if ((unsigned long)mz->addr == mz_phys_addr) {
3227 PMD_DRV_LOG(WARNING,
3228 "Memzone physical address same as virtual.\n");
3229 PMD_DRV_LOG(WARNING,
3230 "Using rte_mem_virt2iova()\n");
3231 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3232 if (mz_phys_addr == 0) {
3234 "unable to map address to physical memory\n");
3239 bp->tx_mem_zone = (const void *)mz;
3240 bp->hw_tx_port_stats = mz->addr;
3241 bp->hw_tx_port_stats_map = mz_phys_addr;
3243 bp->flags |= BNXT_FLAG_PORT_STATS;
3246 rc = bnxt_alloc_hwrm_resources(bp);
3249 "hwrm resource allocation failure rc: %x\n", rc);
3252 rc = bnxt_hwrm_ver_get(bp);
3255 rc = bnxt_hwrm_queue_qportcfg(bp);
3257 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3261 rc = bnxt_hwrm_func_qcfg(bp);
3263 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3267 /* Get the MAX capabilities for this function */
3268 rc = bnxt_hwrm_func_qcaps(bp);
3270 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3273 if (bp->max_tx_rings == 0) {
3274 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3278 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3279 ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3280 if (eth_dev->data->mac_addrs == NULL) {
3282 "Failed to alloc %u bytes needed to store MAC addr tbl",
3283 ETHER_ADDR_LEN * bp->max_l2_ctx);
3288 if (check_zero_bytes(bp->dflt_mac_addr, ETHER_ADDR_LEN)) {
3290 "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
3291 bp->dflt_mac_addr[0], bp->dflt_mac_addr[1],
3292 bp->dflt_mac_addr[2], bp->dflt_mac_addr[3],
3293 bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]);
3297 /* Copy the permanent MAC from the qcap response address now. */
3298 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3299 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
3301 if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3302 /* 1 ring is for default completion ring */
3303 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3308 bp->grp_info = rte_zmalloc("bnxt_grp_info",
3309 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3310 if (!bp->grp_info) {
3312 "Failed to alloc %zu bytes to store group info table\n",
3313 sizeof(*bp->grp_info) * bp->max_ring_grps);
3318 /* Forward all requests if firmware is new enough */
3319 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3320 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3321 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3322 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3324 PMD_DRV_LOG(WARNING,
3325 "Firmware too old for VF mailbox functionality\n");
3326 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3330 * The following are used for driver cleanup. If we disallow these,
3331 * VF drivers can't clean up cleanly.
3333 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3334 ALLOW_FUNC(HWRM_VNIC_FREE);
3335 ALLOW_FUNC(HWRM_RING_FREE);
3336 ALLOW_FUNC(HWRM_RING_GRP_FREE);
3337 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3338 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3339 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3340 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3341 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3342 rc = bnxt_hwrm_func_driver_register(bp);
3345 "Failed to register driver");
3351 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3352 pci_dev->mem_resource[0].phys_addr,
3353 pci_dev->mem_resource[0].addr);
3355 rc = bnxt_hwrm_func_reset(bp);
3357 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3363 //if (bp->pf.active_vfs) {
3364 // TODO: Deallocate VF resources?
3366 if (bp->pdev->max_vfs) {
3367 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3369 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3373 rc = bnxt_hwrm_allocate_pf_only(bp);
3376 "Failed to allocate PF resources\n");
3382 bnxt_hwrm_port_led_qcaps(bp);
3384 rc = bnxt_setup_int(bp);
3388 rc = bnxt_alloc_mem(bp);
3390 goto error_free_int;
3392 rc = bnxt_request_int(bp);
3394 goto error_free_int;
3396 rc = bnxt_alloc_def_cp_ring(bp);
3398 goto error_free_int;
3400 bnxt_enable_int(bp);
3405 bnxt_disable_int(bp);
3406 bnxt_free_def_cp_ring(bp);
3407 bnxt_hwrm_func_buf_unrgtr(bp);
3411 bnxt_dev_uninit(eth_dev);
3417 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
3418 struct bnxt *bp = eth_dev->data->dev_private;
3421 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3424 bnxt_disable_int(bp);
3427 if (eth_dev->data->mac_addrs != NULL) {
3428 rte_free(eth_dev->data->mac_addrs);
3429 eth_dev->data->mac_addrs = NULL;
3431 if (bp->grp_info != NULL) {
3432 rte_free(bp->grp_info);
3433 bp->grp_info = NULL;
3435 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3436 bnxt_free_hwrm_resources(bp);
3437 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3438 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3439 if (bp->dev_stopped == 0)
3440 bnxt_dev_close_op(eth_dev);
3442 rte_free(bp->pf.vf_info);
3443 eth_dev->dev_ops = NULL;
3444 eth_dev->rx_pkt_burst = NULL;
3445 eth_dev->tx_pkt_burst = NULL;
3450 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3451 struct rte_pci_device *pci_dev)
3453 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
3457 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
3459 return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
3462 static struct rte_pci_driver bnxt_rte_pmd = {
3463 .id_table = bnxt_pci_id_map,
3464 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
3465 RTE_PCI_DRV_INTR_LSC,
3466 .probe = bnxt_pci_probe,
3467 .remove = bnxt_pci_remove,
3471 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
3473 if (strcmp(dev->device->driver->name, drv->driver.name))
3479 bool is_bnxt_supported(struct rte_eth_dev *dev)
3481 return is_device_supported(dev, &bnxt_rte_pmd);
3484 RTE_INIT(bnxt_init_log);
3488 bnxt_logtype_driver = rte_log_register("pmd.bnxt.driver");
3489 if (bnxt_logtype_driver >= 0)
3490 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_INFO);
3493 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
3494 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
3495 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");