1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
10 #include <rte_ethdev_driver.h>
11 #include <rte_ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
20 #include "bnxt_ring.h"
23 #include "bnxt_stats.h"
26 #include "bnxt_vnic.h"
27 #include "hsi_struct_def_dpdk.h"
28 #include "bnxt_nvm_defs.h"
30 #define DRV_MODULE_NAME "bnxt"
31 static const char bnxt_version[] =
32 "Broadcom Cumulus driver " DRV_MODULE_NAME "\n";
33 int bnxt_logtype_driver;
35 #define PCI_VENDOR_ID_BROADCOM 0x14E4
37 #define BROADCOM_DEV_ID_STRATUS_NIC_VF 0x1609
38 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
39 #define BROADCOM_DEV_ID_57414_VF 0x16c1
40 #define BROADCOM_DEV_ID_57301 0x16c8
41 #define BROADCOM_DEV_ID_57302 0x16c9
42 #define BROADCOM_DEV_ID_57304_PF 0x16ca
43 #define BROADCOM_DEV_ID_57304_VF 0x16cb
44 #define BROADCOM_DEV_ID_57417_MF 0x16cc
45 #define BROADCOM_DEV_ID_NS2 0x16cd
46 #define BROADCOM_DEV_ID_57311 0x16ce
47 #define BROADCOM_DEV_ID_57312 0x16cf
48 #define BROADCOM_DEV_ID_57402 0x16d0
49 #define BROADCOM_DEV_ID_57404 0x16d1
50 #define BROADCOM_DEV_ID_57406_PF 0x16d2
51 #define BROADCOM_DEV_ID_57406_VF 0x16d3
52 #define BROADCOM_DEV_ID_57402_MF 0x16d4
53 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5
54 #define BROADCOM_DEV_ID_57412 0x16d6
55 #define BROADCOM_DEV_ID_57414 0x16d7
56 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8
57 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9
58 #define BROADCOM_DEV_ID_5741X_VF 0x16dc
59 #define BROADCOM_DEV_ID_57412_MF 0x16de
60 #define BROADCOM_DEV_ID_57314 0x16df
61 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0
62 #define BROADCOM_DEV_ID_5731X_VF 0x16e1
63 #define BROADCOM_DEV_ID_57417_SFP 0x16e2
64 #define BROADCOM_DEV_ID_57416_SFP 0x16e3
65 #define BROADCOM_DEV_ID_57317_SFP 0x16e4
66 #define BROADCOM_DEV_ID_57404_MF 0x16e7
67 #define BROADCOM_DEV_ID_57406_MF 0x16e8
68 #define BROADCOM_DEV_ID_57407_SFP 0x16e9
69 #define BROADCOM_DEV_ID_57407_MF 0x16ea
70 #define BROADCOM_DEV_ID_57414_MF 0x16ec
71 #define BROADCOM_DEV_ID_57416_MF 0x16ee
73 static const struct rte_pci_id bnxt_pci_id_map[] = {
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
75 BROADCOM_DEV_ID_STRATUS_NIC_VF) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) },
88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) },
89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) },
90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) },
91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) },
92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) },
96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) },
98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) },
99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
110 { .vendor_id = 0, /* sentinel */ },
113 #define BNXT_ETH_RSS_SUPPORT ( \
115 ETH_RSS_NONFRAG_IPV4_TCP | \
116 ETH_RSS_NONFRAG_IPV4_UDP | \
118 ETH_RSS_NONFRAG_IPV6_TCP | \
119 ETH_RSS_NONFRAG_IPV6_UDP)
121 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \
122 DEV_TX_OFFLOAD_IPV4_CKSUM | \
123 DEV_TX_OFFLOAD_TCP_CKSUM | \
124 DEV_TX_OFFLOAD_UDP_CKSUM | \
125 DEV_TX_OFFLOAD_TCP_TSO | \
126 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \
127 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \
128 DEV_TX_OFFLOAD_GRE_TNL_TSO | \
129 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
130 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
131 DEV_TX_OFFLOAD_MULTI_SEGS)
133 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
134 DEV_RX_OFFLOAD_VLAN_STRIP | \
135 DEV_RX_OFFLOAD_IPV4_CKSUM | \
136 DEV_RX_OFFLOAD_UDP_CKSUM | \
137 DEV_RX_OFFLOAD_TCP_CKSUM | \
138 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
139 DEV_RX_OFFLOAD_JUMBO_FRAME | \
140 DEV_RX_OFFLOAD_CRC_STRIP | \
141 DEV_RX_OFFLOAD_TCP_LRO)
143 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
144 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
146 /***********************/
149 * High level utility functions
152 static void bnxt_free_mem(struct bnxt *bp)
154 bnxt_free_filter_mem(bp);
155 bnxt_free_vnic_attributes(bp);
156 bnxt_free_vnic_mem(bp);
159 bnxt_free_tx_rings(bp);
160 bnxt_free_rx_rings(bp);
161 bnxt_free_def_cp_ring(bp);
164 static int bnxt_alloc_mem(struct bnxt *bp)
168 /* Default completion ring */
169 rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY);
173 rc = bnxt_alloc_rings(bp, 0, NULL, NULL,
174 bp->def_cp_ring, "def_cp");
178 rc = bnxt_alloc_vnic_mem(bp);
182 rc = bnxt_alloc_vnic_attributes(bp);
186 rc = bnxt_alloc_filter_mem(bp);
197 static int bnxt_init_chip(struct bnxt *bp)
200 struct rte_eth_link new;
201 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
202 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
203 uint32_t intr_vector = 0;
204 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
205 uint32_t vec = BNXT_MISC_VEC_ID;
208 /* disable uio/vfio intr/eventfd mapping */
209 rte_intr_disable(intr_handle);
211 if (bp->eth_dev->data->mtu > ETHER_MTU) {
212 bp->eth_dev->data->dev_conf.rxmode.offloads |=
213 DEV_RX_OFFLOAD_JUMBO_FRAME;
214 bp->flags |= BNXT_FLAG_JUMBO;
216 bp->eth_dev->data->dev_conf.rxmode.offloads &=
217 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
218 bp->flags &= ~BNXT_FLAG_JUMBO;
221 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
223 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
227 rc = bnxt_alloc_hwrm_rings(bp);
229 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
233 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
235 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
239 rc = bnxt_mq_rx_configure(bp);
241 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
245 /* VNIC configuration */
246 for (i = 0; i < bp->nr_vnics; i++) {
247 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
249 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
251 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n",
256 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic);
259 "HWRM vnic %d ctx alloc failure rc: %x\n",
264 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
266 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
271 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
274 "HWRM vnic %d filter failure rc: %x\n",
279 rc = bnxt_vnic_rss_configure(bp, vnic);
282 "HWRM vnic set RSS failure rc: %x\n", rc);
286 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
288 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
289 DEV_RX_OFFLOAD_TCP_LRO)
290 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
292 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
294 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
297 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
301 /* check and configure queue intr-vector mapping */
302 if ((rte_intr_cap_multiple(intr_handle) ||
303 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
304 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
305 intr_vector = bp->eth_dev->data->nb_rx_queues;
306 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
307 if (intr_vector > bp->rx_cp_nr_rings) {
308 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
312 if (rte_intr_efd_enable(intr_handle, intr_vector))
316 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
317 intr_handle->intr_vec =
318 rte_zmalloc("intr_vec",
319 bp->eth_dev->data->nb_rx_queues *
321 if (intr_handle->intr_vec == NULL) {
322 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
323 " intr_vec", bp->eth_dev->data->nb_rx_queues);
326 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
327 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
328 intr_handle->intr_vec, intr_handle->nb_efd,
329 intr_handle->max_intr);
332 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
334 intr_handle->intr_vec[queue_id] = vec;
335 if (vec < base + intr_handle->nb_efd - 1)
339 /* enable uio/vfio intr/eventfd mapping */
340 rte_intr_enable(intr_handle);
342 rc = bnxt_get_hwrm_link_config(bp, &new);
344 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc);
348 if (!bp->link_info.link_up) {
349 rc = bnxt_set_hwrm_link_config(bp, true);
352 "HWRM link config failure rc: %x\n", rc);
356 bnxt_print_link_info(bp->eth_dev);
361 bnxt_free_all_hwrm_resources(bp);
363 /* Some of the error status returned by FW may not be from errno.h */
370 static int bnxt_shutdown_nic(struct bnxt *bp)
372 bnxt_free_all_hwrm_resources(bp);
373 bnxt_free_all_filters(bp);
374 bnxt_free_all_vnics(bp);
378 static int bnxt_init_nic(struct bnxt *bp)
382 rc = bnxt_init_ring_grps(bp);
387 bnxt_init_filters(bp);
389 rc = bnxt_init_chip(bp);
397 * Device configuration and status function
400 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
401 struct rte_eth_dev_info *dev_info)
403 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
404 uint16_t max_vnics, i, j, vpool, vrxq;
405 unsigned int max_rx_rings;
408 dev_info->max_mac_addrs = bp->max_l2_ctx;
409 dev_info->max_hash_mac_addrs = 0;
411 /* PF/VF specifics */
413 dev_info->max_vfs = bp->pdev->max_vfs;
414 max_rx_rings = RTE_MIN(bp->max_vnics, RTE_MIN(bp->max_l2_ctx,
415 RTE_MIN(bp->max_rsscos_ctx,
417 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
418 dev_info->max_rx_queues = max_rx_rings;
419 dev_info->max_tx_queues = max_rx_rings;
420 dev_info->reta_size = bp->max_rsscos_ctx;
421 dev_info->hash_key_size = 40;
422 max_vnics = bp->max_vnics;
424 /* Fast path specifics */
425 dev_info->min_rx_bufsize = 1;
426 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN
429 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
430 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
431 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
432 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT;
433 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
436 dev_info->default_rxconf = (struct rte_eth_rxconf) {
442 .rx_free_thresh = 32,
443 /* If no descriptors available, pkts are dropped by default */
447 dev_info->default_txconf = (struct rte_eth_txconf) {
453 .tx_free_thresh = 32,
456 eth_dev->data->dev_conf.intr_conf.lsc = 1;
458 eth_dev->data->dev_conf.intr_conf.rxq = 1;
463 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
464 * need further investigation.
468 vpool = 64; /* ETH_64_POOLS */
469 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
470 for (i = 0; i < 4; vpool >>= 1, i++) {
471 if (max_vnics > vpool) {
472 for (j = 0; j < 5; vrxq >>= 1, j++) {
473 if (dev_info->max_rx_queues > vrxq) {
479 /* Not enough resources to support VMDq */
483 /* Not enough resources to support VMDq */
487 dev_info->max_vmdq_pools = vpool;
488 dev_info->vmdq_queue_num = vrxq;
490 dev_info->vmdq_pool_base = 0;
491 dev_info->vmdq_queue_base = 0;
494 /* Configure the device based on the configuration provided */
495 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
497 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
498 uint64_t tx_offloads = eth_dev->data->dev_conf.txmode.offloads;
499 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
501 if (tx_offloads != (tx_offloads & BNXT_DEV_TX_OFFLOAD_SUPPORT)) {
504 "Tx offloads requested 0x%" PRIx64 " supported 0x%x\n",
505 tx_offloads, BNXT_DEV_TX_OFFLOAD_SUPPORT);
509 if (rx_offloads != (rx_offloads & BNXT_DEV_RX_OFFLOAD_SUPPORT)) {
512 "Rx offloads requested 0x%" PRIx64 " supported 0x%x\n",
513 rx_offloads, BNXT_DEV_RX_OFFLOAD_SUPPORT);
517 bp->rx_queues = (void *)eth_dev->data->rx_queues;
518 bp->tx_queues = (void *)eth_dev->data->tx_queues;
520 /* Inherit new configurations */
521 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
522 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
523 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues + 1 >
525 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
527 (uint32_t)(eth_dev->data->nb_rx_queues + 1) > bp->max_ring_grps) {
529 "Insufficient resources to support requested config\n");
531 "Num Queues Requested: Tx %d, Rx %d\n",
532 eth_dev->data->nb_tx_queues,
533 eth_dev->data->nb_rx_queues);
535 "Res available: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d\n",
536 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
537 bp->max_stat_ctx, bp->max_ring_grps);
541 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
542 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
543 bp->rx_cp_nr_rings = bp->rx_nr_rings;
544 bp->tx_cp_nr_rings = bp->tx_nr_rings;
546 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
548 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
549 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
553 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
555 struct rte_eth_link *link = ð_dev->data->dev_link;
557 if (link->link_status)
558 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
559 eth_dev->data->port_id,
560 (uint32_t)link->link_speed,
561 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
562 ("full-duplex") : ("half-duplex\n"));
564 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
565 eth_dev->data->port_id);
568 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
570 bnxt_print_link_info(eth_dev);
574 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
576 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
577 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
581 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) {
583 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
584 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
588 rc = bnxt_init_nic(bp);
592 bnxt_link_update_op(eth_dev, 1);
594 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
595 vlan_mask |= ETH_VLAN_FILTER_MASK;
596 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
597 vlan_mask |= ETH_VLAN_STRIP_MASK;
598 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
602 bp->flags |= BNXT_FLAG_INIT_DONE;
606 bnxt_shutdown_nic(bp);
607 bnxt_free_tx_mbufs(bp);
608 bnxt_free_rx_mbufs(bp);
612 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
614 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
617 if (!bp->link_info.link_up)
618 rc = bnxt_set_hwrm_link_config(bp, true);
620 eth_dev->data->dev_link.link_status = 1;
622 bnxt_print_link_info(eth_dev);
626 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
628 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
630 eth_dev->data->dev_link.link_status = 0;
631 bnxt_set_hwrm_link_config(bp, false);
632 bp->link_info.link_up = 0;
637 /* Unload the driver, release resources */
638 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
640 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
642 if (bp->eth_dev->data->dev_started) {
643 /* TBD: STOP HW queues DMA */
644 eth_dev->data->dev_link.link_status = 0;
646 bnxt_set_hwrm_link_config(bp, false);
647 bnxt_hwrm_port_clr_stats(bp);
648 bp->flags &= ~BNXT_FLAG_INIT_DONE;
649 bnxt_shutdown_nic(bp);
653 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
655 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
657 if (bp->dev_stopped == 0)
658 bnxt_dev_stop_op(eth_dev);
660 bnxt_free_tx_mbufs(bp);
661 bnxt_free_rx_mbufs(bp);
663 if (eth_dev->data->mac_addrs != NULL) {
664 rte_free(eth_dev->data->mac_addrs);
665 eth_dev->data->mac_addrs = NULL;
667 if (bp->grp_info != NULL) {
668 rte_free(bp->grp_info);
673 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
676 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
677 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
678 struct bnxt_vnic_info *vnic;
679 struct bnxt_filter_info *filter, *temp_filter;
680 uint32_t pool = RTE_MIN(MAX_FF_POOLS, ETH_64_POOLS);
684 * Loop through all VNICs from the specified filter flow pools to
685 * remove the corresponding MAC addr filter
687 for (i = 0; i < pool; i++) {
688 if (!(pool_mask & (1ULL << i)))
691 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
692 filter = STAILQ_FIRST(&vnic->filter);
694 temp_filter = STAILQ_NEXT(filter, next);
695 if (filter->mac_index == index) {
696 STAILQ_REMOVE(&vnic->filter, filter,
697 bnxt_filter_info, next);
698 bnxt_hwrm_clear_l2_filter(bp, filter);
699 filter->mac_index = INVALID_MAC_INDEX;
700 memset(&filter->l2_addr, 0,
703 &bp->free_filter_list,
706 filter = temp_filter;
712 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
713 struct ether_addr *mac_addr,
714 uint32_t index, uint32_t pool)
716 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
717 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]);
718 struct bnxt_filter_info *filter;
721 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
726 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
729 /* Attach requested MAC address to the new l2_filter */
730 STAILQ_FOREACH(filter, &vnic->filter, next) {
731 if (filter->mac_index == index) {
733 "MAC addr already existed for pool %d\n", pool);
737 filter = bnxt_alloc_filter(bp);
739 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
742 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
743 filter->mac_index = index;
744 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN);
745 return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
748 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
751 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
752 struct rte_eth_link new;
753 unsigned int cnt = BNXT_LINK_WAIT_CNT;
755 memset(&new, 0, sizeof(new));
757 /* Retrieve link info from hardware */
758 rc = bnxt_get_hwrm_link_config(bp, &new);
760 new.link_speed = ETH_LINK_SPEED_100M;
761 new.link_duplex = ETH_LINK_FULL_DUPLEX;
763 "Failed to retrieve link rc = 0x%x!\n", rc);
766 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
768 if (!wait_to_complete)
770 } while (!new.link_status && cnt--);
773 /* Timed out or success */
774 if (new.link_status != eth_dev->data->dev_link.link_status ||
775 new.link_speed != eth_dev->data->dev_link.link_speed) {
776 memcpy(ð_dev->data->dev_link, &new,
777 sizeof(struct rte_eth_link));
778 bnxt_print_link_info(eth_dev);
784 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
786 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
787 struct bnxt_vnic_info *vnic;
789 if (bp->vnic_info == NULL)
792 vnic = &bp->vnic_info[0];
794 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
795 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
798 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
800 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
801 struct bnxt_vnic_info *vnic;
803 if (bp->vnic_info == NULL)
806 vnic = &bp->vnic_info[0];
808 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
809 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
812 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
814 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
815 struct bnxt_vnic_info *vnic;
817 if (bp->vnic_info == NULL)
820 vnic = &bp->vnic_info[0];
822 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
823 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
826 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
828 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
829 struct bnxt_vnic_info *vnic;
831 if (bp->vnic_info == NULL)
834 vnic = &bp->vnic_info[0];
836 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
837 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
840 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
841 struct rte_eth_rss_reta_entry64 *reta_conf,
844 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
845 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
846 struct bnxt_vnic_info *vnic;
849 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
852 if (reta_size != HW_HASH_INDEX_SIZE) {
853 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
854 "(%d) must equal the size supported by the hardware "
855 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
858 /* Update the RSS VNIC(s) */
859 for (i = 0; i < MAX_FF_POOLS; i++) {
860 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
861 memcpy(vnic->rss_table, reta_conf, reta_size);
863 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
869 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
870 struct rte_eth_rss_reta_entry64 *reta_conf,
873 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
874 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
875 struct rte_intr_handle *intr_handle
876 = &bp->pdev->intr_handle;
878 /* Retrieve from the default VNIC */
881 if (!vnic->rss_table)
884 if (reta_size != HW_HASH_INDEX_SIZE) {
885 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
886 "(%d) must equal the size supported by the hardware "
887 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
890 /* EW - need to revisit here copying from uint64_t to uint16_t */
891 memcpy(reta_conf, vnic->rss_table, reta_size);
893 if (rte_intr_allow_others(intr_handle)) {
894 if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
895 bnxt_dev_lsc_intr_setup(eth_dev);
901 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
902 struct rte_eth_rss_conf *rss_conf)
904 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
905 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
906 struct bnxt_vnic_info *vnic;
907 uint16_t hash_type = 0;
911 * If RSS enablement were different than dev_configure,
912 * then return -EINVAL
914 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
915 if (!rss_conf->rss_hf)
916 PMD_DRV_LOG(ERR, "Hash type NONE\n");
918 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
922 bp->flags |= BNXT_FLAG_UPDATE_HASH;
923 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
925 if (rss_conf->rss_hf & ETH_RSS_IPV4)
926 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
927 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
928 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
929 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
930 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
931 if (rss_conf->rss_hf & ETH_RSS_IPV6)
932 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
933 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
934 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
935 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
936 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
938 /* Update the RSS VNIC(s) */
939 for (i = 0; i < MAX_FF_POOLS; i++) {
940 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
941 vnic->hash_type = hash_type;
944 * Use the supplied key if the key length is
945 * acceptable and the rss_key is not NULL
947 if (rss_conf->rss_key &&
948 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
949 memcpy(vnic->rss_hash_key, rss_conf->rss_key,
950 rss_conf->rss_key_len);
952 bnxt_hwrm_vnic_rss_cfg(bp, vnic);
958 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
959 struct rte_eth_rss_conf *rss_conf)
961 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
962 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
966 /* RSS configuration is the same for all VNICs */
967 if (vnic && vnic->rss_hash_key) {
968 if (rss_conf->rss_key) {
969 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
970 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
971 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
974 hash_types = vnic->hash_type;
975 rss_conf->rss_hf = 0;
976 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
977 rss_conf->rss_hf |= ETH_RSS_IPV4;
978 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
980 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
981 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
983 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
985 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
986 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
988 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
990 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
991 rss_conf->rss_hf |= ETH_RSS_IPV6;
992 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
994 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
995 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
997 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
999 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
1000 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
1002 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
1006 "Unknwon RSS config from firmware (%08x), RSS disabled",
1011 rss_conf->rss_hf = 0;
1016 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
1017 struct rte_eth_fc_conf *fc_conf)
1019 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1020 struct rte_eth_link link_info;
1023 rc = bnxt_get_hwrm_link_config(bp, &link_info);
1027 memset(fc_conf, 0, sizeof(*fc_conf));
1028 if (bp->link_info.auto_pause)
1029 fc_conf->autoneg = 1;
1030 switch (bp->link_info.pause) {
1032 fc_conf->mode = RTE_FC_NONE;
1034 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
1035 fc_conf->mode = RTE_FC_TX_PAUSE;
1037 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
1038 fc_conf->mode = RTE_FC_RX_PAUSE;
1040 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
1041 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
1042 fc_conf->mode = RTE_FC_FULL;
1048 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
1049 struct rte_eth_fc_conf *fc_conf)
1051 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1053 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1054 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
1058 switch (fc_conf->mode) {
1060 bp->link_info.auto_pause = 0;
1061 bp->link_info.force_pause = 0;
1063 case RTE_FC_RX_PAUSE:
1064 if (fc_conf->autoneg) {
1065 bp->link_info.auto_pause =
1066 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1067 bp->link_info.force_pause = 0;
1069 bp->link_info.auto_pause = 0;
1070 bp->link_info.force_pause =
1071 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1074 case RTE_FC_TX_PAUSE:
1075 if (fc_conf->autoneg) {
1076 bp->link_info.auto_pause =
1077 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
1078 bp->link_info.force_pause = 0;
1080 bp->link_info.auto_pause = 0;
1081 bp->link_info.force_pause =
1082 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
1086 if (fc_conf->autoneg) {
1087 bp->link_info.auto_pause =
1088 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
1089 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
1090 bp->link_info.force_pause = 0;
1092 bp->link_info.auto_pause = 0;
1093 bp->link_info.force_pause =
1094 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
1095 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
1099 return bnxt_set_hwrm_link_config(bp, true);
1102 /* Add UDP tunneling port */
1104 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
1105 struct rte_eth_udp_tunnel *udp_tunnel)
1107 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1108 uint16_t tunnel_type = 0;
1111 switch (udp_tunnel->prot_type) {
1112 case RTE_TUNNEL_TYPE_VXLAN:
1113 if (bp->vxlan_port_cnt) {
1114 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1115 udp_tunnel->udp_port);
1116 if (bp->vxlan_port != udp_tunnel->udp_port) {
1117 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1120 bp->vxlan_port_cnt++;
1124 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
1125 bp->vxlan_port_cnt++;
1127 case RTE_TUNNEL_TYPE_GENEVE:
1128 if (bp->geneve_port_cnt) {
1129 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
1130 udp_tunnel->udp_port);
1131 if (bp->geneve_port != udp_tunnel->udp_port) {
1132 PMD_DRV_LOG(ERR, "Only one port allowed\n");
1135 bp->geneve_port_cnt++;
1139 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
1140 bp->geneve_port_cnt++;
1143 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1146 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
1152 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
1153 struct rte_eth_udp_tunnel *udp_tunnel)
1155 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1156 uint16_t tunnel_type = 0;
1160 switch (udp_tunnel->prot_type) {
1161 case RTE_TUNNEL_TYPE_VXLAN:
1162 if (!bp->vxlan_port_cnt) {
1163 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1166 if (bp->vxlan_port != udp_tunnel->udp_port) {
1167 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1168 udp_tunnel->udp_port, bp->vxlan_port);
1171 if (--bp->vxlan_port_cnt)
1175 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
1176 port = bp->vxlan_fw_dst_port_id;
1178 case RTE_TUNNEL_TYPE_GENEVE:
1179 if (!bp->geneve_port_cnt) {
1180 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
1183 if (bp->geneve_port != udp_tunnel->udp_port) {
1184 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
1185 udp_tunnel->udp_port, bp->geneve_port);
1188 if (--bp->geneve_port_cnt)
1192 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
1193 port = bp->geneve_fw_dst_port_id;
1196 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
1200 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
1203 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN)
1206 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE)
1207 bp->geneve_port = 0;
1212 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1214 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1215 struct bnxt_vnic_info *vnic;
1218 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1220 /* Cycle through all VNICs */
1221 for (i = 0; i < bp->nr_vnics; i++) {
1223 * For each VNIC and each associated filter(s)
1224 * if VLAN exists && VLAN matches vlan_id
1225 * remove the MAC+VLAN filter
1226 * add a new MAC only filter
1228 * VLAN filter doesn't exist, just skip and continue
1230 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1231 filter = STAILQ_FIRST(&vnic->filter);
1233 temp_filter = STAILQ_NEXT(filter, next);
1235 if (filter->enables & chk &&
1236 filter->l2_ovlan == vlan_id) {
1237 /* Must delete the filter */
1238 STAILQ_REMOVE(&vnic->filter, filter,
1239 bnxt_filter_info, next);
1240 bnxt_hwrm_clear_l2_filter(bp, filter);
1242 &bp->free_filter_list,
1246 * Need to examine to see if the MAC
1247 * filter already existed or not before
1248 * allocating a new one
1251 new_filter = bnxt_alloc_filter(bp);
1254 "MAC/VLAN filter alloc failed\n");
1258 STAILQ_INSERT_TAIL(&vnic->filter,
1260 /* Inherit MAC from previous filter */
1261 new_filter->mac_index =
1263 memcpy(new_filter->l2_addr,
1264 filter->l2_addr, ETHER_ADDR_LEN);
1265 /* MAC only filter */
1266 rc = bnxt_hwrm_set_l2_filter(bp,
1272 "Del Vlan filter for %d\n",
1275 filter = temp_filter;
1283 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
1285 struct bnxt_filter_info *filter, *temp_filter, *new_filter;
1286 struct bnxt_vnic_info *vnic;
1289 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN |
1290 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK;
1291 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN;
1293 /* Cycle through all VNICs */
1294 for (i = 0; i < bp->nr_vnics; i++) {
1296 * For each VNIC and each associated filter(s)
1298 * if VLAN matches vlan_id
1299 * VLAN filter already exists, just skip and continue
1301 * add a new MAC+VLAN filter
1303 * Remove the old MAC only filter
1304 * Add a new MAC+VLAN filter
1306 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) {
1307 filter = STAILQ_FIRST(&vnic->filter);
1309 temp_filter = STAILQ_NEXT(filter, next);
1311 if (filter->enables & chk) {
1312 if (filter->l2_ovlan == vlan_id)
1315 /* Must delete the MAC filter */
1316 STAILQ_REMOVE(&vnic->filter, filter,
1317 bnxt_filter_info, next);
1318 bnxt_hwrm_clear_l2_filter(bp, filter);
1319 filter->l2_ovlan = 0;
1321 &bp->free_filter_list,
1324 new_filter = bnxt_alloc_filter(bp);
1327 "MAC/VLAN filter alloc failed\n");
1331 STAILQ_INSERT_TAIL(&vnic->filter, new_filter,
1333 /* Inherit MAC from the previous filter */
1334 new_filter->mac_index = filter->mac_index;
1335 memcpy(new_filter->l2_addr, filter->l2_addr,
1337 /* MAC + VLAN ID filter */
1338 new_filter->l2_ovlan = vlan_id;
1339 new_filter->l2_ovlan_mask = 0xF000;
1340 new_filter->enables |= en;
1341 rc = bnxt_hwrm_set_l2_filter(bp,
1347 "Added Vlan filter for %d\n", vlan_id);
1349 filter = temp_filter;
1357 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
1358 uint16_t vlan_id, int on)
1360 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1362 /* These operations apply to ALL existing MAC/VLAN filters */
1364 return bnxt_add_vlan_filter(bp, vlan_id);
1366 return bnxt_del_vlan_filter(bp, vlan_id);
1370 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
1372 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1373 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1376 if (mask & ETH_VLAN_FILTER_MASK) {
1377 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
1378 /* Remove any VLAN filters programmed */
1379 for (i = 0; i < 4095; i++)
1380 bnxt_del_vlan_filter(bp, i);
1382 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
1383 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
1386 if (mask & ETH_VLAN_STRIP_MASK) {
1387 /* Enable or disable VLAN stripping */
1388 for (i = 0; i < bp->nr_vnics; i++) {
1389 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1390 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1391 vnic->vlan_strip = true;
1393 vnic->vlan_strip = false;
1394 bnxt_hwrm_vnic_cfg(bp, vnic);
1396 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
1397 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
1400 if (mask & ETH_VLAN_EXTEND_MASK)
1401 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
1407 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr)
1409 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1410 /* Default Filter is tied to VNIC 0 */
1411 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
1412 struct bnxt_filter_info *filter;
1418 memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr));
1420 STAILQ_FOREACH(filter, &vnic->filter, next) {
1421 /* Default Filter is at Index 0 */
1422 if (filter->mac_index != 0)
1424 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
1427 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN);
1428 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN);
1429 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
1431 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
1432 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
1433 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1436 filter->mac_index = 0;
1437 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
1444 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
1445 struct ether_addr *mc_addr_set,
1446 uint32_t nb_mc_addr)
1448 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
1449 char *mc_addr_list = (char *)mc_addr_set;
1450 struct bnxt_vnic_info *vnic;
1451 uint32_t off = 0, i = 0;
1453 vnic = &bp->vnic_info[0];
1455 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
1456 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1460 /* TODO Check for Duplicate mcast addresses */
1461 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1462 for (i = 0; i < nb_mc_addr; i++) {
1463 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN);
1464 off += ETHER_ADDR_LEN;
1467 vnic->mc_addr_cnt = i;
1470 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1474 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
1476 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1477 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
1478 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
1479 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
1482 ret = snprintf(fw_version, fw_size, "%d.%d.%d",
1483 fw_major, fw_minor, fw_updt);
1485 ret += 1; /* add the size of '\0' */
1486 if (fw_size < (uint32_t)ret)
1493 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1494 struct rte_eth_rxq_info *qinfo)
1496 struct bnxt_rx_queue *rxq;
1498 rxq = dev->data->rx_queues[queue_id];
1500 qinfo->mp = rxq->mb_pool;
1501 qinfo->scattered_rx = dev->data->scattered_rx;
1502 qinfo->nb_desc = rxq->nb_rx_desc;
1504 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1505 qinfo->conf.rx_drop_en = 0;
1506 qinfo->conf.rx_deferred_start = 0;
1510 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
1511 struct rte_eth_txq_info *qinfo)
1513 struct bnxt_tx_queue *txq;
1515 txq = dev->data->tx_queues[queue_id];
1517 qinfo->nb_desc = txq->nb_tx_desc;
1519 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1520 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1521 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1523 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1524 qinfo->conf.tx_rs_thresh = 0;
1525 qinfo->conf.txq_flags = txq->txq_flags;
1526 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1529 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
1531 struct bnxt *bp = eth_dev->data->dev_private;
1532 struct rte_eth_dev_info dev_info;
1533 uint32_t max_dev_mtu;
1537 bnxt_dev_info_get_op(eth_dev, &dev_info);
1538 max_dev_mtu = dev_info.max_rx_pktlen -
1539 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2;
1541 if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) {
1542 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
1543 ETHER_MIN_MTU, max_dev_mtu);
1548 if (new_mtu > ETHER_MTU) {
1549 bp->flags |= BNXT_FLAG_JUMBO;
1550 bp->eth_dev->data->dev_conf.rxmode.offloads |=
1551 DEV_RX_OFFLOAD_JUMBO_FRAME;
1553 bp->eth_dev->data->dev_conf.rxmode.offloads &=
1554 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1555 bp->flags &= ~BNXT_FLAG_JUMBO;
1558 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
1559 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1561 eth_dev->data->mtu = new_mtu;
1562 PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
1564 for (i = 0; i < bp->nr_vnics; i++) {
1565 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1567 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN +
1568 ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
1569 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
1573 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
1582 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
1584 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1585 uint16_t vlan = bp->vlan;
1588 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
1590 "PVID cannot be modified for this function\n");
1593 bp->vlan = on ? pvid : 0;
1595 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
1602 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
1604 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1606 return bnxt_hwrm_port_led_cfg(bp, true);
1610 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
1612 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1614 return bnxt_hwrm_port_led_cfg(bp, false);
1618 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1620 uint32_t desc = 0, raw_cons = 0, cons;
1621 struct bnxt_cp_ring_info *cpr;
1622 struct bnxt_rx_queue *rxq;
1623 struct rx_pkt_cmpl *rxcmp;
1628 rxq = dev->data->rx_queues[rx_queue_id];
1632 while (raw_cons < rxq->nb_rx_desc) {
1633 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
1634 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1636 if (!CMPL_VALID(rxcmp, valid))
1638 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
1639 cmp_type = CMP_TYPE(rxcmp);
1640 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
1641 cmp = (rte_le_to_cpu_32(
1642 ((struct rx_tpa_end_cmpl *)
1643 (rxcmp))->agg_bufs_v1) &
1644 RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
1645 RX_TPA_END_CMPL_AGG_BUFS_SFT;
1647 } else if (cmp_type == 0x11) {
1649 cmp = (rxcmp->agg_bufs_v1 &
1650 RX_PKT_CMPL_AGG_BUFS_MASK) >>
1651 RX_PKT_CMPL_AGG_BUFS_SFT;
1656 raw_cons += cmp ? cmp : 2;
1663 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
1665 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
1666 struct bnxt_rx_ring_info *rxr;
1667 struct bnxt_cp_ring_info *cpr;
1668 struct bnxt_sw_rx_bd *rx_buf;
1669 struct rx_pkt_cmpl *rxcmp;
1670 uint32_t cons, cp_cons;
1678 if (offset >= rxq->nb_rx_desc)
1681 cons = RING_CMP(cpr->cp_ring_struct, offset);
1682 cp_cons = cpr->cp_raw_cons;
1683 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1685 if (cons > cp_cons) {
1686 if (CMPL_VALID(rxcmp, cpr->valid))
1687 return RTE_ETH_RX_DESC_DONE;
1689 if (CMPL_VALID(rxcmp, !cpr->valid))
1690 return RTE_ETH_RX_DESC_DONE;
1692 rx_buf = &rxr->rx_buf_ring[cons];
1693 if (rx_buf->mbuf == NULL)
1694 return RTE_ETH_RX_DESC_UNAVAIL;
1697 return RTE_ETH_RX_DESC_AVAIL;
1701 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
1703 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
1704 struct bnxt_tx_ring_info *txr;
1705 struct bnxt_cp_ring_info *cpr;
1706 struct bnxt_sw_tx_bd *tx_buf;
1707 struct tx_pkt_cmpl *txcmp;
1708 uint32_t cons, cp_cons;
1716 if (offset >= txq->nb_tx_desc)
1719 cons = RING_CMP(cpr->cp_ring_struct, offset);
1720 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
1721 cp_cons = cpr->cp_raw_cons;
1723 if (cons > cp_cons) {
1724 if (CMPL_VALID(txcmp, cpr->valid))
1725 return RTE_ETH_TX_DESC_UNAVAIL;
1727 if (CMPL_VALID(txcmp, !cpr->valid))
1728 return RTE_ETH_TX_DESC_UNAVAIL;
1730 tx_buf = &txr->tx_buf_ring[cons];
1731 if (tx_buf->mbuf == NULL)
1732 return RTE_ETH_TX_DESC_DONE;
1734 return RTE_ETH_TX_DESC_FULL;
1737 static struct bnxt_filter_info *
1738 bnxt_match_and_validate_ether_filter(struct bnxt *bp,
1739 struct rte_eth_ethertype_filter *efilter,
1740 struct bnxt_vnic_info *vnic0,
1741 struct bnxt_vnic_info *vnic,
1744 struct bnxt_filter_info *mfilter = NULL;
1748 if (efilter->ether_type == ETHER_TYPE_IPv4 ||
1749 efilter->ether_type == ETHER_TYPE_IPv6) {
1750 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in"
1751 " ethertype filter.", efilter->ether_type);
1755 if (efilter->queue >= bp->rx_nr_rings) {
1756 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1761 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1762 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1764 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue);
1769 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1770 STAILQ_FOREACH(mfilter, &vnic0->filter, next) {
1771 if ((!memcmp(efilter->mac_addr.addr_bytes,
1772 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1774 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP &&
1775 mfilter->ethertype == efilter->ether_type)) {
1781 STAILQ_FOREACH(mfilter, &vnic->filter, next)
1782 if ((!memcmp(efilter->mac_addr.addr_bytes,
1783 mfilter->l2_addr, ETHER_ADDR_LEN) &&
1784 mfilter->ethertype == efilter->ether_type &&
1786 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) {
1800 bnxt_ethertype_filter(struct rte_eth_dev *dev,
1801 enum rte_filter_op filter_op,
1804 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
1805 struct rte_eth_ethertype_filter *efilter =
1806 (struct rte_eth_ethertype_filter *)arg;
1807 struct bnxt_filter_info *bfilter, *filter1;
1808 struct bnxt_vnic_info *vnic, *vnic0;
1811 if (filter_op == RTE_ETH_FILTER_NOP)
1815 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
1820 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
1821 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]);
1823 switch (filter_op) {
1824 case RTE_ETH_FILTER_ADD:
1825 bnxt_match_and_validate_ether_filter(bp, efilter,
1830 bfilter = bnxt_get_unused_filter(bp);
1831 if (bfilter == NULL) {
1833 "Not enough resources for a new filter.\n");
1836 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
1837 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes,
1839 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes,
1841 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
1842 bfilter->ethertype = efilter->ether_type;
1843 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
1845 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0);
1846 if (filter1 == NULL) {
1851 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
1852 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
1854 bfilter->dst_id = vnic->fw_vnic_id;
1856 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) {
1858 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
1861 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
1864 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
1866 case RTE_ETH_FILTER_DELETE:
1867 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter,
1869 if (ret == -EEXIST) {
1870 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1);
1872 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info,
1874 bnxt_free_filter(bp, filter1);
1875 } else if (ret == 0) {
1876 PMD_DRV_LOG(ERR, "No matching filter found\n");
1880 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
1886 bnxt_free_filter(bp, bfilter);
1892 parse_ntuple_filter(struct bnxt *bp,
1893 struct rte_eth_ntuple_filter *nfilter,
1894 struct bnxt_filter_info *bfilter)
1898 if (nfilter->queue >= bp->rx_nr_rings) {
1899 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue);
1903 switch (nfilter->dst_port_mask) {
1905 bfilter->dst_port_mask = -1;
1906 bfilter->dst_port = nfilter->dst_port;
1907 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT |
1908 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
1911 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
1915 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
1916 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1918 switch (nfilter->proto_mask) {
1920 if (nfilter->proto == 17) /* IPPROTO_UDP */
1921 bfilter->ip_protocol = 17;
1922 else if (nfilter->proto == 6) /* IPPROTO_TCP */
1923 bfilter->ip_protocol = 6;
1926 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
1929 PMD_DRV_LOG(ERR, "invalid protocol mask.");
1933 switch (nfilter->dst_ip_mask) {
1935 bfilter->dst_ipaddr_mask[0] = -1;
1936 bfilter->dst_ipaddr[0] = nfilter->dst_ip;
1937 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR |
1938 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
1941 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
1945 switch (nfilter->src_ip_mask) {
1947 bfilter->src_ipaddr_mask[0] = -1;
1948 bfilter->src_ipaddr[0] = nfilter->src_ip;
1949 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR |
1950 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
1953 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
1957 switch (nfilter->src_port_mask) {
1959 bfilter->src_port_mask = -1;
1960 bfilter->src_port = nfilter->src_port;
1961 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT |
1962 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
1965 PMD_DRV_LOG(ERR, "invalid src_port mask.");
1970 //nfilter->priority = (uint8_t)filter->priority;
1972 bfilter->enables = en;
1976 static struct bnxt_filter_info*
1977 bnxt_match_ntuple_filter(struct bnxt *bp,
1978 struct bnxt_filter_info *bfilter,
1979 struct bnxt_vnic_info **mvnic)
1981 struct bnxt_filter_info *mfilter = NULL;
1984 for (i = bp->nr_vnics - 1; i >= 0; i--) {
1985 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
1986 STAILQ_FOREACH(mfilter, &vnic->filter, next) {
1987 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] &&
1988 bfilter->src_ipaddr_mask[0] ==
1989 mfilter->src_ipaddr_mask[0] &&
1990 bfilter->src_port == mfilter->src_port &&
1991 bfilter->src_port_mask == mfilter->src_port_mask &&
1992 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] &&
1993 bfilter->dst_ipaddr_mask[0] ==
1994 mfilter->dst_ipaddr_mask[0] &&
1995 bfilter->dst_port == mfilter->dst_port &&
1996 bfilter->dst_port_mask == mfilter->dst_port_mask &&
1997 bfilter->flags == mfilter->flags &&
1998 bfilter->enables == mfilter->enables) {
2009 bnxt_cfg_ntuple_filter(struct bnxt *bp,
2010 struct rte_eth_ntuple_filter *nfilter,
2011 enum rte_filter_op filter_op)
2013 struct bnxt_filter_info *bfilter, *mfilter, *filter1;
2014 struct bnxt_vnic_info *vnic, *vnic0, *mvnic;
2017 if (nfilter->flags != RTE_5TUPLE_FLAGS) {
2018 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
2022 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) {
2023 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n");
2027 bfilter = bnxt_get_unused_filter(bp);
2028 if (bfilter == NULL) {
2030 "Not enough resources for a new filter.\n");
2033 ret = parse_ntuple_filter(bp, nfilter, bfilter);
2037 vnic = STAILQ_FIRST(&bp->ff_pool[nfilter->queue]);
2038 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2039 filter1 = STAILQ_FIRST(&vnic0->filter);
2040 if (filter1 == NULL) {
2045 bfilter->dst_id = vnic->fw_vnic_id;
2046 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2048 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2049 bfilter->ethertype = 0x800;
2050 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2052 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic);
2054 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2055 bfilter->dst_id == mfilter->dst_id) {
2056 PMD_DRV_LOG(ERR, "filter exists.\n");
2059 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD &&
2060 bfilter->dst_id != mfilter->dst_id) {
2061 mfilter->dst_id = vnic->fw_vnic_id;
2062 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter);
2063 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next);
2064 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next);
2065 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n");
2066 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n");
2069 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2070 PMD_DRV_LOG(ERR, "filter doesn't exist.");
2075 if (filter_op == RTE_ETH_FILTER_ADD) {
2076 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2077 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter);
2080 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next);
2082 if (mfilter == NULL) {
2083 /* This should not happen. But for Coverity! */
2087 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter);
2089 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next);
2090 bnxt_free_filter(bp, mfilter);
2091 mfilter->fw_l2_filter_id = -1;
2092 bnxt_free_filter(bp, bfilter);
2093 bfilter->fw_l2_filter_id = -1;
2098 bfilter->fw_l2_filter_id = -1;
2099 bnxt_free_filter(bp, bfilter);
2104 bnxt_ntuple_filter(struct rte_eth_dev *dev,
2105 enum rte_filter_op filter_op,
2108 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2111 if (filter_op == RTE_ETH_FILTER_NOP)
2115 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
2120 switch (filter_op) {
2121 case RTE_ETH_FILTER_ADD:
2122 ret = bnxt_cfg_ntuple_filter(bp,
2123 (struct rte_eth_ntuple_filter *)arg,
2126 case RTE_ETH_FILTER_DELETE:
2127 ret = bnxt_cfg_ntuple_filter(bp,
2128 (struct rte_eth_ntuple_filter *)arg,
2132 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
2140 bnxt_parse_fdir_filter(struct bnxt *bp,
2141 struct rte_eth_fdir_filter *fdir,
2142 struct bnxt_filter_info *filter)
2144 enum rte_fdir_mode fdir_mode =
2145 bp->eth_dev->data->dev_conf.fdir_conf.mode;
2146 struct bnxt_vnic_info *vnic0, *vnic;
2147 struct bnxt_filter_info *filter1;
2151 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
2154 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci;
2155 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID;
2157 switch (fdir->input.flow_type) {
2158 case RTE_ETH_FLOW_IPV4:
2159 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
2161 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip;
2162 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2163 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip;
2164 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2165 filter->ip_protocol = fdir->input.flow.ip4_flow.proto;
2166 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2167 filter->ip_addr_type =
2168 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2169 filter->src_ipaddr_mask[0] = 0xffffffff;
2170 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2171 filter->dst_ipaddr_mask[0] = 0xffffffff;
2172 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2173 filter->ethertype = 0x800;
2174 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2176 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
2177 filter->src_port = fdir->input.flow.tcp4_flow.src_port;
2178 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2179 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port;
2180 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2181 filter->dst_port_mask = 0xffff;
2182 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2183 filter->src_port_mask = 0xffff;
2184 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2185 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip;
2186 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2187 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip;
2188 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2189 filter->ip_protocol = 6;
2190 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2191 filter->ip_addr_type =
2192 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2193 filter->src_ipaddr_mask[0] = 0xffffffff;
2194 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2195 filter->dst_ipaddr_mask[0] = 0xffffffff;
2196 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2197 filter->ethertype = 0x800;
2198 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2200 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
2201 filter->src_port = fdir->input.flow.udp4_flow.src_port;
2202 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2203 filter->dst_port = fdir->input.flow.udp4_flow.dst_port;
2204 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2205 filter->dst_port_mask = 0xffff;
2206 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2207 filter->src_port_mask = 0xffff;
2208 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2209 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip;
2210 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2211 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip;
2212 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2213 filter->ip_protocol = 17;
2214 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2215 filter->ip_addr_type =
2216 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4;
2217 filter->src_ipaddr_mask[0] = 0xffffffff;
2218 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2219 filter->dst_ipaddr_mask[0] = 0xffffffff;
2220 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2221 filter->ethertype = 0x800;
2222 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2224 case RTE_ETH_FLOW_IPV6:
2225 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
2227 filter->ip_addr_type =
2228 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2229 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto;
2230 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2231 rte_memcpy(filter->src_ipaddr,
2232 fdir->input.flow.ipv6_flow.src_ip, 16);
2233 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2234 rte_memcpy(filter->dst_ipaddr,
2235 fdir->input.flow.ipv6_flow.dst_ip, 16);
2236 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2237 memset(filter->dst_ipaddr_mask, 0xff, 16);
2238 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2239 memset(filter->src_ipaddr_mask, 0xff, 16);
2240 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2241 filter->ethertype = 0x86dd;
2242 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2244 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
2245 filter->src_port = fdir->input.flow.tcp6_flow.src_port;
2246 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2247 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port;
2248 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2249 filter->dst_port_mask = 0xffff;
2250 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2251 filter->src_port_mask = 0xffff;
2252 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2253 filter->ip_addr_type =
2254 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2255 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto;
2256 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2257 rte_memcpy(filter->src_ipaddr,
2258 fdir->input.flow.tcp6_flow.ip.src_ip, 16);
2259 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2260 rte_memcpy(filter->dst_ipaddr,
2261 fdir->input.flow.tcp6_flow.ip.dst_ip, 16);
2262 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2263 memset(filter->dst_ipaddr_mask, 0xff, 16);
2264 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2265 memset(filter->src_ipaddr_mask, 0xff, 16);
2266 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2267 filter->ethertype = 0x86dd;
2268 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2270 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
2271 filter->src_port = fdir->input.flow.udp6_flow.src_port;
2272 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT;
2273 filter->dst_port = fdir->input.flow.udp6_flow.dst_port;
2274 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT;
2275 filter->dst_port_mask = 0xffff;
2276 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK;
2277 filter->src_port_mask = 0xffff;
2278 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK;
2279 filter->ip_addr_type =
2280 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6;
2281 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto;
2282 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO;
2283 rte_memcpy(filter->src_ipaddr,
2284 fdir->input.flow.udp6_flow.ip.src_ip, 16);
2285 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR;
2286 rte_memcpy(filter->dst_ipaddr,
2287 fdir->input.flow.udp6_flow.ip.dst_ip, 16);
2288 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR;
2289 memset(filter->dst_ipaddr_mask, 0xff, 16);
2290 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK;
2291 memset(filter->src_ipaddr_mask, 0xff, 16);
2292 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK;
2293 filter->ethertype = 0x86dd;
2294 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2296 case RTE_ETH_FLOW_L2_PAYLOAD:
2297 filter->ethertype = fdir->input.flow.l2_flow.ether_type;
2298 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE;
2300 case RTE_ETH_FLOW_VXLAN:
2301 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2303 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2304 filter->tunnel_type =
2305 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN;
2306 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2308 case RTE_ETH_FLOW_NVGRE:
2309 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2311 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id;
2312 filter->tunnel_type =
2313 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE;
2314 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE;
2316 case RTE_ETH_FLOW_UNKNOWN:
2317 case RTE_ETH_FLOW_RAW:
2318 case RTE_ETH_FLOW_FRAG_IPV4:
2319 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
2320 case RTE_ETH_FLOW_FRAG_IPV6:
2321 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
2322 case RTE_ETH_FLOW_IPV6_EX:
2323 case RTE_ETH_FLOW_IPV6_TCP_EX:
2324 case RTE_ETH_FLOW_IPV6_UDP_EX:
2325 case RTE_ETH_FLOW_GENEVE:
2331 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]);
2332 vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2334 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue);
2339 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
2340 rte_memcpy(filter->dst_macaddr,
2341 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
2342 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR;
2345 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) {
2346 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP;
2347 filter1 = STAILQ_FIRST(&vnic0->filter);
2348 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0);
2350 filter->dst_id = vnic->fw_vnic_id;
2351 for (i = 0; i < ETHER_ADDR_LEN; i++)
2352 if (filter->dst_macaddr[i] == 0x00)
2353 filter1 = STAILQ_FIRST(&vnic0->filter);
2355 filter1 = bnxt_get_l2_filter(bp, filter, vnic);
2358 if (filter1 == NULL)
2361 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID;
2362 filter->fw_l2_filter_id = filter1->fw_l2_filter_id;
2364 filter->enables = en;
2369 static struct bnxt_filter_info *
2370 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf,
2371 struct bnxt_vnic_info **mvnic)
2373 struct bnxt_filter_info *mf = NULL;
2376 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2377 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2379 STAILQ_FOREACH(mf, &vnic->filter, next) {
2380 if (mf->filter_type == nf->filter_type &&
2381 mf->flags == nf->flags &&
2382 mf->src_port == nf->src_port &&
2383 mf->src_port_mask == nf->src_port_mask &&
2384 mf->dst_port == nf->dst_port &&
2385 mf->dst_port_mask == nf->dst_port_mask &&
2386 mf->ip_protocol == nf->ip_protocol &&
2387 mf->ip_addr_type == nf->ip_addr_type &&
2388 mf->ethertype == nf->ethertype &&
2389 mf->vni == nf->vni &&
2390 mf->tunnel_type == nf->tunnel_type &&
2391 mf->l2_ovlan == nf->l2_ovlan &&
2392 mf->l2_ovlan_mask == nf->l2_ovlan_mask &&
2393 mf->l2_ivlan == nf->l2_ivlan &&
2394 mf->l2_ivlan_mask == nf->l2_ivlan_mask &&
2395 !memcmp(mf->l2_addr, nf->l2_addr, ETHER_ADDR_LEN) &&
2396 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask,
2398 !memcmp(mf->src_macaddr, nf->src_macaddr,
2400 !memcmp(mf->dst_macaddr, nf->dst_macaddr,
2402 !memcmp(mf->src_ipaddr, nf->src_ipaddr,
2403 sizeof(nf->src_ipaddr)) &&
2404 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask,
2405 sizeof(nf->src_ipaddr_mask)) &&
2406 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr,
2407 sizeof(nf->dst_ipaddr)) &&
2408 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask,
2409 sizeof(nf->dst_ipaddr_mask))) {
2420 bnxt_fdir_filter(struct rte_eth_dev *dev,
2421 enum rte_filter_op filter_op,
2424 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2425 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg;
2426 struct bnxt_filter_info *filter, *match;
2427 struct bnxt_vnic_info *vnic, *mvnic;
2430 if (filter_op == RTE_ETH_FILTER_NOP)
2433 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2436 switch (filter_op) {
2437 case RTE_ETH_FILTER_ADD:
2438 case RTE_ETH_FILTER_DELETE:
2439 filter = bnxt_get_unused_filter(bp);
2440 if (filter == NULL) {
2442 "Not enough resources for a new flow.\n");
2446 ret = bnxt_parse_fdir_filter(bp, fdir, filter);
2449 filter->filter_type = HWRM_CFA_NTUPLE_FILTER;
2451 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT)
2452 vnic = STAILQ_FIRST(&bp->ff_pool[0]);
2454 vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]);
2456 match = bnxt_match_fdir(bp, filter, &mvnic);
2457 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) {
2458 if (match->dst_id == vnic->fw_vnic_id) {
2459 PMD_DRV_LOG(ERR, "Flow already exists.\n");
2463 match->dst_id = vnic->fw_vnic_id;
2464 ret = bnxt_hwrm_set_ntuple_filter(bp,
2467 STAILQ_REMOVE(&mvnic->filter, match,
2468 bnxt_filter_info, next);
2469 STAILQ_INSERT_TAIL(&vnic->filter, match, next);
2471 "Filter with matching pattern exist\n");
2473 "Updated it to new destination q\n");
2477 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) {
2478 PMD_DRV_LOG(ERR, "Flow does not exist.\n");
2483 if (filter_op == RTE_ETH_FILTER_ADD) {
2484 ret = bnxt_hwrm_set_ntuple_filter(bp,
2489 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2491 ret = bnxt_hwrm_clear_ntuple_filter(bp, match);
2492 STAILQ_REMOVE(&vnic->filter, match,
2493 bnxt_filter_info, next);
2494 bnxt_free_filter(bp, match);
2495 filter->fw_l2_filter_id = -1;
2496 bnxt_free_filter(bp, filter);
2499 case RTE_ETH_FILTER_FLUSH:
2500 for (i = bp->nr_vnics - 1; i >= 0; i--) {
2501 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2503 STAILQ_FOREACH(filter, &vnic->filter, next) {
2504 if (filter->filter_type ==
2505 HWRM_CFA_NTUPLE_FILTER) {
2507 bnxt_hwrm_clear_ntuple_filter(bp,
2509 STAILQ_REMOVE(&vnic->filter, filter,
2510 bnxt_filter_info, next);
2515 case RTE_ETH_FILTER_UPDATE:
2516 case RTE_ETH_FILTER_STATS:
2517 case RTE_ETH_FILTER_INFO:
2518 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op);
2521 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2528 filter->fw_l2_filter_id = -1;
2529 bnxt_free_filter(bp, filter);
2534 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused,
2535 enum rte_filter_type filter_type,
2536 enum rte_filter_op filter_op, void *arg)
2540 switch (filter_type) {
2541 case RTE_ETH_FILTER_TUNNEL:
2543 "filter type: %d: To be implemented\n", filter_type);
2545 case RTE_ETH_FILTER_FDIR:
2546 ret = bnxt_fdir_filter(dev, filter_op, arg);
2548 case RTE_ETH_FILTER_NTUPLE:
2549 ret = bnxt_ntuple_filter(dev, filter_op, arg);
2551 case RTE_ETH_FILTER_ETHERTYPE:
2552 ret = bnxt_ethertype_filter(dev, filter_op, arg);
2554 case RTE_ETH_FILTER_GENERIC:
2555 if (filter_op != RTE_ETH_FILTER_GET)
2557 *(const void **)arg = &bnxt_flow_ops;
2561 "Filter type (%d) not supported", filter_type);
2568 static const uint32_t *
2569 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
2571 static const uint32_t ptypes[] = {
2572 RTE_PTYPE_L2_ETHER_VLAN,
2573 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2574 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2578 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2579 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2580 RTE_PTYPE_INNER_L4_ICMP,
2581 RTE_PTYPE_INNER_L4_TCP,
2582 RTE_PTYPE_INNER_L4_UDP,
2586 if (dev->rx_pkt_burst == bnxt_recv_pkts)
2591 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
2594 uint32_t reg_base = *reg_arr & 0xfffff000;
2598 for (i = 0; i < count; i++) {
2599 if ((reg_arr[i] & 0xfffff000) != reg_base)
2602 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
2603 rte_cpu_to_le_32(rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off));
2607 static int bnxt_map_ptp_regs(struct bnxt *bp)
2609 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2613 reg_arr = ptp->rx_regs;
2614 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
2618 reg_arr = ptp->tx_regs;
2619 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
2623 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
2624 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
2626 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
2627 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
2632 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
2634 rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2635 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16));
2636 rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 +
2637 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20));
2640 static uint64_t bnxt_cc_read(struct bnxt *bp)
2644 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2645 BNXT_GRCPF_REG_SYNC_TIME));
2646 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2647 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
2651 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
2653 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2656 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2657 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2658 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
2661 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2662 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
2663 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2664 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
2665 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2666 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
2671 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
2673 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2674 struct bnxt_pf_info *pf = &bp->pf;
2681 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2682 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2683 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
2686 port_id = pf->port_id;
2687 rte_cpu_to_le_32(rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
2688 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]));
2690 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2691 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
2692 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
2693 /* bnxt_clr_rx_ts(bp); TBD */
2697 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2698 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
2699 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
2700 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
2706 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
2709 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2710 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2715 ns = rte_timespec_to_ns(ts);
2716 /* Set the timecounters to a new value. */
2723 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
2725 uint64_t ns, systime_cycles;
2726 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2727 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2732 systime_cycles = bnxt_cc_read(bp);
2733 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
2734 *ts = rte_ns_to_timespec(ns);
2739 bnxt_timesync_enable(struct rte_eth_dev *dev)
2741 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2742 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2749 ptp->tx_tstamp_en = 1;
2750 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
2752 if (!bnxt_hwrm_ptp_cfg(bp))
2753 bnxt_map_ptp_regs(bp);
2755 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
2756 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2757 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
2759 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2760 ptp->tc.cc_shift = shift;
2761 ptp->tc.nsec_mask = (1ULL << shift) - 1;
2763 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2764 ptp->rx_tstamp_tc.cc_shift = shift;
2765 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2767 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
2768 ptp->tx_tstamp_tc.cc_shift = shift;
2769 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
2775 bnxt_timesync_disable(struct rte_eth_dev *dev)
2777 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2778 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2784 ptp->tx_tstamp_en = 0;
2787 bnxt_hwrm_ptp_cfg(bp);
2789 bnxt_unmap_ptp_regs(bp);
2795 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
2796 struct timespec *timestamp,
2797 uint32_t flags __rte_unused)
2799 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2800 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2801 uint64_t rx_tstamp_cycles = 0;
2807 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
2808 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
2809 *timestamp = rte_ns_to_timespec(ns);
2814 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
2815 struct timespec *timestamp)
2817 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2818 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2819 uint64_t tx_tstamp_cycles = 0;
2825 bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
2826 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
2827 *timestamp = rte_ns_to_timespec(ns);
2833 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
2835 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2836 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
2841 ptp->tc.nsec += delta;
2847 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
2849 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2851 uint32_t dir_entries;
2852 uint32_t entry_length;
2854 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n",
2855 bp->pdev->addr.domain, bp->pdev->addr.bus,
2856 bp->pdev->addr.devid, bp->pdev->addr.function);
2858 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
2862 return dir_entries * entry_length;
2866 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
2867 struct rte_dev_eeprom_info *in_eeprom)
2869 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2873 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2874 "len = %d\n", bp->pdev->addr.domain,
2875 bp->pdev->addr.bus, bp->pdev->addr.devid,
2876 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2878 if (in_eeprom->offset == 0) /* special offset value to get directory */
2879 return bnxt_get_nvram_directory(bp, in_eeprom->length,
2882 index = in_eeprom->offset >> 24;
2883 offset = in_eeprom->offset & 0xffffff;
2886 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
2887 in_eeprom->length, in_eeprom->data);
2892 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
2895 case BNX_DIR_TYPE_CHIMP_PATCH:
2896 case BNX_DIR_TYPE_BOOTCODE:
2897 case BNX_DIR_TYPE_BOOTCODE_2:
2898 case BNX_DIR_TYPE_APE_FW:
2899 case BNX_DIR_TYPE_APE_PATCH:
2900 case BNX_DIR_TYPE_KONG_FW:
2901 case BNX_DIR_TYPE_KONG_PATCH:
2902 case BNX_DIR_TYPE_BONO_FW:
2903 case BNX_DIR_TYPE_BONO_PATCH:
2910 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
2913 case BNX_DIR_TYPE_AVS:
2914 case BNX_DIR_TYPE_EXP_ROM_MBA:
2915 case BNX_DIR_TYPE_PCIE:
2916 case BNX_DIR_TYPE_TSCF_UCODE:
2917 case BNX_DIR_TYPE_EXT_PHY:
2918 case BNX_DIR_TYPE_CCM:
2919 case BNX_DIR_TYPE_ISCSI_BOOT:
2920 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
2921 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
2928 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
2930 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
2931 bnxt_dir_type_is_other_exec_format(dir_type);
2935 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
2936 struct rte_dev_eeprom_info *in_eeprom)
2938 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
2939 uint8_t index, dir_op;
2940 uint16_t type, ext, ordinal, attr;
2942 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d "
2943 "len = %d\n", bp->pdev->addr.domain,
2944 bp->pdev->addr.bus, bp->pdev->addr.devid,
2945 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length);
2948 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
2952 type = in_eeprom->magic >> 16;
2954 if (type == 0xffff) { /* special value for directory operations */
2955 index = in_eeprom->magic & 0xff;
2956 dir_op = in_eeprom->magic >> 8;
2960 case 0x0e: /* erase */
2961 if (in_eeprom->offset != ~in_eeprom->magic)
2963 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
2969 /* Create or re-write an NVM item: */
2970 if (bnxt_dir_type_is_executable(type) == true)
2972 ext = in_eeprom->magic & 0xffff;
2973 ordinal = in_eeprom->offset >> 16;
2974 attr = in_eeprom->offset & 0xffff;
2976 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
2977 in_eeprom->data, in_eeprom->length);
2985 static const struct eth_dev_ops bnxt_dev_ops = {
2986 .dev_infos_get = bnxt_dev_info_get_op,
2987 .dev_close = bnxt_dev_close_op,
2988 .dev_configure = bnxt_dev_configure_op,
2989 .dev_start = bnxt_dev_start_op,
2990 .dev_stop = bnxt_dev_stop_op,
2991 .dev_set_link_up = bnxt_dev_set_link_up_op,
2992 .dev_set_link_down = bnxt_dev_set_link_down_op,
2993 .stats_get = bnxt_stats_get_op,
2994 .stats_reset = bnxt_stats_reset_op,
2995 .rx_queue_setup = bnxt_rx_queue_setup_op,
2996 .rx_queue_release = bnxt_rx_queue_release_op,
2997 .tx_queue_setup = bnxt_tx_queue_setup_op,
2998 .tx_queue_release = bnxt_tx_queue_release_op,
2999 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3000 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3001 .reta_update = bnxt_reta_update_op,
3002 .reta_query = bnxt_reta_query_op,
3003 .rss_hash_update = bnxt_rss_hash_update_op,
3004 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3005 .link_update = bnxt_link_update_op,
3006 .promiscuous_enable = bnxt_promiscuous_enable_op,
3007 .promiscuous_disable = bnxt_promiscuous_disable_op,
3008 .allmulticast_enable = bnxt_allmulticast_enable_op,
3009 .allmulticast_disable = bnxt_allmulticast_disable_op,
3010 .mac_addr_add = bnxt_mac_addr_add_op,
3011 .mac_addr_remove = bnxt_mac_addr_remove_op,
3012 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3013 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3014 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3015 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3016 .vlan_filter_set = bnxt_vlan_filter_set_op,
3017 .vlan_offload_set = bnxt_vlan_offload_set_op,
3018 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3019 .mtu_set = bnxt_mtu_set_op,
3020 .mac_addr_set = bnxt_set_default_mac_addr_op,
3021 .xstats_get = bnxt_dev_xstats_get_op,
3022 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3023 .xstats_reset = bnxt_dev_xstats_reset_op,
3024 .fw_version_get = bnxt_fw_version_get,
3025 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3026 .rxq_info_get = bnxt_rxq_info_get_op,
3027 .txq_info_get = bnxt_txq_info_get_op,
3028 .dev_led_on = bnxt_dev_led_on_op,
3029 .dev_led_off = bnxt_dev_led_off_op,
3030 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op,
3031 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op,
3032 .rx_queue_count = bnxt_rx_queue_count_op,
3033 .rx_descriptor_status = bnxt_rx_descriptor_status_op,
3034 .tx_descriptor_status = bnxt_tx_descriptor_status_op,
3035 .rx_queue_start = bnxt_rx_queue_start,
3036 .rx_queue_stop = bnxt_rx_queue_stop,
3037 .tx_queue_start = bnxt_tx_queue_start,
3038 .tx_queue_stop = bnxt_tx_queue_stop,
3039 .filter_ctrl = bnxt_filter_ctrl_op,
3040 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3041 .get_eeprom_length = bnxt_get_eeprom_length_op,
3042 .get_eeprom = bnxt_get_eeprom_op,
3043 .set_eeprom = bnxt_set_eeprom_op,
3044 .timesync_enable = bnxt_timesync_enable,
3045 .timesync_disable = bnxt_timesync_disable,
3046 .timesync_read_time = bnxt_timesync_read_time,
3047 .timesync_write_time = bnxt_timesync_write_time,
3048 .timesync_adjust_time = bnxt_timesync_adjust_time,
3049 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3050 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3053 static bool bnxt_vf_pciid(uint16_t id)
3055 if (id == BROADCOM_DEV_ID_57304_VF ||
3056 id == BROADCOM_DEV_ID_57406_VF ||
3057 id == BROADCOM_DEV_ID_5731X_VF ||
3058 id == BROADCOM_DEV_ID_5741X_VF ||
3059 id == BROADCOM_DEV_ID_57414_VF ||
3060 id == BROADCOM_DEV_ID_STRATUS_NIC_VF)
3065 static int bnxt_init_board(struct rte_eth_dev *eth_dev)
3067 struct bnxt *bp = eth_dev->data->dev_private;
3068 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3071 /* enable device (incl. PCI PM wakeup), and bus-mastering */
3072 if (!pci_dev->mem_resource[0].addr) {
3074 "Cannot find PCI device base address, aborting\n");
3076 goto init_err_disable;
3079 bp->eth_dev = eth_dev;
3082 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
3084 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n");
3086 goto init_err_release;
3099 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
3101 #define ALLOW_FUNC(x) \
3103 typeof(x) arg = (x); \
3104 bp->pf.vf_req_fwd[((arg) >> 5)] &= \
3105 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \
3108 bnxt_dev_init(struct rte_eth_dev *eth_dev)
3110 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3111 char mz_name[RTE_MEMZONE_NAMESIZE];
3112 const struct rte_memzone *mz = NULL;
3113 static int version_printed;
3114 uint32_t total_alloc_len;
3115 rte_iova_t mz_phys_addr;
3119 if (version_printed++ == 0)
3120 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
3122 rte_eth_copy_pci_info(eth_dev, pci_dev);
3124 bp = eth_dev->data->dev_private;
3126 rte_atomic64_init(&bp->rx_mbuf_alloc_fail);
3127 bp->dev_stopped = 1;
3129 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3132 if (bnxt_vf_pciid(pci_dev->id.device_id))
3133 bp->flags |= BNXT_FLAG_VF;
3135 rc = bnxt_init_board(eth_dev);
3138 "Board initialization failed rc: %x\n", rc);
3142 eth_dev->dev_ops = &bnxt_dev_ops;
3143 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3145 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
3146 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
3148 if (BNXT_PF(bp) && pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) {
3149 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3150 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3151 pci_dev->addr.bus, pci_dev->addr.devid,
3152 pci_dev->addr.function, "rx_port_stats");
3153 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3154 mz = rte_memzone_lookup(mz_name);
3155 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3156 sizeof(struct rx_port_stats) + 512);
3158 mz = rte_memzone_reserve(mz_name, total_alloc_len,
3161 RTE_MEMZONE_SIZE_HINT_ONLY |
3162 RTE_MEMZONE_IOVA_CONTIG);
3166 memset(mz->addr, 0, mz->len);
3167 mz_phys_addr = mz->iova;
3168 if ((unsigned long)mz->addr == mz_phys_addr) {
3169 PMD_DRV_LOG(WARNING,
3170 "Memzone physical address same as virtual.\n");
3171 PMD_DRV_LOG(WARNING,
3172 "Using rte_mem_virt2iova()\n");
3173 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3174 if (mz_phys_addr == 0) {
3176 "unable to map address to physical memory\n");
3181 bp->rx_mem_zone = (const void *)mz;
3182 bp->hw_rx_port_stats = mz->addr;
3183 bp->hw_rx_port_stats_map = mz_phys_addr;
3185 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
3186 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain,
3187 pci_dev->addr.bus, pci_dev->addr.devid,
3188 pci_dev->addr.function, "tx_port_stats");
3189 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
3190 mz = rte_memzone_lookup(mz_name);
3191 total_alloc_len = RTE_CACHE_LINE_ROUNDUP(
3192 sizeof(struct tx_port_stats) + 512);
3194 mz = rte_memzone_reserve(mz_name,
3198 RTE_MEMZONE_SIZE_HINT_ONLY |
3199 RTE_MEMZONE_IOVA_CONTIG);
3203 memset(mz->addr, 0, mz->len);
3204 mz_phys_addr = mz->iova;
3205 if ((unsigned long)mz->addr == mz_phys_addr) {
3206 PMD_DRV_LOG(WARNING,
3207 "Memzone physical address same as virtual.\n");
3208 PMD_DRV_LOG(WARNING,
3209 "Using rte_mem_virt2iova()\n");
3210 mz_phys_addr = rte_mem_virt2iova(mz->addr);
3211 if (mz_phys_addr == 0) {
3213 "unable to map address to physical memory\n");
3218 bp->tx_mem_zone = (const void *)mz;
3219 bp->hw_tx_port_stats = mz->addr;
3220 bp->hw_tx_port_stats_map = mz_phys_addr;
3222 bp->flags |= BNXT_FLAG_PORT_STATS;
3225 rc = bnxt_alloc_hwrm_resources(bp);
3228 "hwrm resource allocation failure rc: %x\n", rc);
3231 rc = bnxt_hwrm_ver_get(bp);
3234 rc = bnxt_hwrm_queue_qportcfg(bp);
3236 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n");
3240 rc = bnxt_hwrm_func_qcfg(bp);
3242 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n");
3246 /* Get the MAX capabilities for this function */
3247 rc = bnxt_hwrm_func_qcaps(bp);
3249 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc);
3252 if (bp->max_tx_rings == 0) {
3253 PMD_DRV_LOG(ERR, "No TX rings available!\n");
3257 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
3258 ETHER_ADDR_LEN * bp->max_l2_ctx, 0);
3259 if (eth_dev->data->mac_addrs == NULL) {
3261 "Failed to alloc %u bytes needed to store MAC addr tbl",
3262 ETHER_ADDR_LEN * bp->max_l2_ctx);
3267 if (check_zero_bytes(bp->dflt_mac_addr, ETHER_ADDR_LEN)) {
3269 "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
3270 bp->dflt_mac_addr[0], bp->dflt_mac_addr[1],
3271 bp->dflt_mac_addr[2], bp->dflt_mac_addr[3],
3272 bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]);
3276 /* Copy the permanent MAC from the qcap response address now. */
3277 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr));
3278 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN);
3280 if (bp->max_ring_grps < bp->rx_cp_nr_rings) {
3281 /* 1 ring is for default completion ring */
3282 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n");
3287 bp->grp_info = rte_zmalloc("bnxt_grp_info",
3288 sizeof(*bp->grp_info) * bp->max_ring_grps, 0);
3289 if (!bp->grp_info) {
3291 "Failed to alloc %zu bytes to store group info table\n",
3292 sizeof(*bp->grp_info) * bp->max_ring_grps);
3297 /* Forward all requests if firmware is new enough */
3298 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) &&
3299 (bp->fw_ver < ((20 << 24) | (7 << 16)))) ||
3300 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) {
3301 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd));
3303 PMD_DRV_LOG(WARNING,
3304 "Firmware too old for VF mailbox functionality\n");
3305 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd));
3309 * The following are used for driver cleanup. If we disallow these,
3310 * VF drivers can't clean up cleanly.
3312 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR);
3313 ALLOW_FUNC(HWRM_VNIC_FREE);
3314 ALLOW_FUNC(HWRM_RING_FREE);
3315 ALLOW_FUNC(HWRM_RING_GRP_FREE);
3316 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE);
3317 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE);
3318 ALLOW_FUNC(HWRM_STAT_CTX_FREE);
3319 ALLOW_FUNC(HWRM_PORT_PHY_QCFG);
3320 ALLOW_FUNC(HWRM_VNIC_TPA_CFG);
3321 rc = bnxt_hwrm_func_driver_register(bp);
3324 "Failed to register driver");
3330 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n",
3331 pci_dev->mem_resource[0].phys_addr,
3332 pci_dev->mem_resource[0].addr);
3334 rc = bnxt_hwrm_func_reset(bp);
3336 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc);
3342 //if (bp->pf.active_vfs) {
3343 // TODO: Deallocate VF resources?
3345 if (bp->pdev->max_vfs) {
3346 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
3348 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
3352 rc = bnxt_hwrm_allocate_pf_only(bp);
3355 "Failed to allocate PF resources\n");
3361 bnxt_hwrm_port_led_qcaps(bp);
3363 rc = bnxt_setup_int(bp);
3367 rc = bnxt_alloc_mem(bp);
3369 goto error_free_int;
3371 rc = bnxt_request_int(bp);
3373 goto error_free_int;
3375 rc = bnxt_alloc_def_cp_ring(bp);
3377 goto error_free_int;
3379 bnxt_enable_int(bp);
3384 bnxt_disable_int(bp);
3385 bnxt_free_def_cp_ring(bp);
3386 bnxt_hwrm_func_buf_unrgtr(bp);
3390 bnxt_dev_uninit(eth_dev);
3396 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) {
3397 struct bnxt *bp = eth_dev->data->dev_private;
3400 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3403 bnxt_disable_int(bp);
3406 if (eth_dev->data->mac_addrs != NULL) {
3407 rte_free(eth_dev->data->mac_addrs);
3408 eth_dev->data->mac_addrs = NULL;
3410 if (bp->grp_info != NULL) {
3411 rte_free(bp->grp_info);
3412 bp->grp_info = NULL;
3414 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
3415 bnxt_free_hwrm_resources(bp);
3416 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
3417 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
3418 if (bp->dev_stopped == 0)
3419 bnxt_dev_close_op(eth_dev);
3421 rte_free(bp->pf.vf_info);
3422 eth_dev->dev_ops = NULL;
3423 eth_dev->rx_pkt_burst = NULL;
3424 eth_dev->tx_pkt_burst = NULL;
3429 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3430 struct rte_pci_device *pci_dev)
3432 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt),
3436 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
3438 return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit);
3441 static struct rte_pci_driver bnxt_rte_pmd = {
3442 .id_table = bnxt_pci_id_map,
3443 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
3444 RTE_PCI_DRV_INTR_LSC,
3445 .probe = bnxt_pci_probe,
3446 .remove = bnxt_pci_remove,
3450 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
3452 if (strcmp(dev->device->driver->name, drv->driver.name))
3458 bool is_bnxt_supported(struct rte_eth_dev *dev)
3460 return is_device_supported(dev, &bnxt_rte_pmd);
3463 RTE_INIT(bnxt_init_log);
3467 bnxt_logtype_driver = rte_log_register("pmd.bnxt.driver");
3468 if (bnxt_logtype_driver >= 0)
3469 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE);
3472 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
3473 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
3474 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");