drivers/net/bnxt/bnxt_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2021 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #include <inttypes.h>
   7 #include <stdbool.h>
   8
   9 #include <rte_dev.h>
  10 #include <ethdev_driver.h>
  11 #include <ethdev_pci.h>
  12 #include <rte_malloc.h>
  13 #include <rte_cycles.h>
  14 #include <rte_alarm.h>
  15 #include <rte_kvargs.h>
  16 #include <rte_vect.h>
  17
  18 #include "bnxt.h"
  19 #include "bnxt_filter.h"
  20 #include "bnxt_hwrm.h"
  21 #include "bnxt_irq.h"
  22 #include "bnxt_reps.h"
  23 #include "bnxt_ring.h"
  24 #include "bnxt_rxq.h"
  25 #include "bnxt_rxr.h"
  26 #include "bnxt_stats.h"
  27 #include "bnxt_txq.h"
  28 #include "bnxt_txr.h"
  29 #include "bnxt_vnic.h"
  30 #include "hsi_struct_def_dpdk.h"
  31 #include "bnxt_nvm_defs.h"
  32 #include "bnxt_tf_common.h"
  33 #include "ulp_flow_db.h"
  34 #include "rte_pmd_bnxt.h"
  35
  36 #define DRV_MODULE_NAME         "bnxt"
  37 static const char bnxt_version[] =
  38         "Broadcom NetXtreme driver " DRV_MODULE_NAME;
  39
  40 /*
  41  * The set of PCI devices this driver supports
  42  */
  43 static const struct rte_pci_id bnxt_pci_id_map[] = {
  44         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  45                          BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
  46         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
  47                          BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
  48         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
  49         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
  50         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
  51         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
  52         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
  53         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
  54         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
  55         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
  56         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
  57         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
  58         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
  59         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
  60         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
  61         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
  62         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
  63         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
  74         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
  75         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
  76         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
  77         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
  78         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
  79         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
  80         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
  81         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
  82         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
  83         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
  84         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
  85         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
  86         { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
  87         { .vendor_id = 0, /* sentinel */ },
  88 };
  89
  90 #define BNXT_DEVARG_ACCUM_STATS "accum-stats"
  91 #define BNXT_DEVARG_FLOW_XSTAT  "flow-xstat"
  92 #define BNXT_DEVARG_MAX_NUM_KFLOWS  "max-num-kflows"
  93 #define BNXT_DEVARG_REPRESENTOR "representor"
  94 #define BNXT_DEVARG_REP_BASED_PF  "rep-based-pf"
  95 #define BNXT_DEVARG_REP_IS_PF  "rep-is-pf"
  96 #define BNXT_DEVARG_REP_Q_R2F  "rep-q-r2f"
  97 #define BNXT_DEVARG_REP_Q_F2R  "rep-q-f2r"
  98 #define BNXT_DEVARG_REP_FC_R2F  "rep-fc-r2f"
  99 #define BNXT_DEVARG_REP_FC_F2R  "rep-fc-f2r"
 100 #define BNXT_DEVARG_APP_ID      "app-id"
 101
 102 static const char *const bnxt_dev_args[] = {
 103         BNXT_DEVARG_REPRESENTOR,
 104         BNXT_DEVARG_ACCUM_STATS,
 105         BNXT_DEVARG_FLOW_XSTAT,
 106         BNXT_DEVARG_MAX_NUM_KFLOWS,
 107         BNXT_DEVARG_REP_BASED_PF,
 108         BNXT_DEVARG_REP_IS_PF,
 109         BNXT_DEVARG_REP_Q_R2F,
 110         BNXT_DEVARG_REP_Q_F2R,
 111         BNXT_DEVARG_REP_FC_R2F,
 112         BNXT_DEVARG_REP_FC_F2R,
 113         BNXT_DEVARG_APP_ID,
 114         NULL
 115 };
 116
 117 /*
 118  * accum-stats == false to disable flow counter accumulation
 119  * accum-stats == true to enable flow counter accumulation
 120  */
 121 #define BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)    ((accum_stats) > 1)
 122
 123 /*
 124  * app-id = an non-negative 8-bit number
 125  */
 126 #define BNXT_DEVARG_APP_ID_INVALID(val)                 ((val) > 255)
 127
 128 /*
 129  * flow_xstat == false to disable the feature
 130  * flow_xstat == true to enable the feature
 131  */
 132 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)      ((flow_xstat) > 1)
 133
 134 /*
 135  * rep_is_pf == false to indicate VF representor
 136  * rep_is_pf == true to indicate PF representor
 137  */
 138 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)        ((rep_is_pf) > 1)
 139
 140 /*
 141  * rep_based_pf == Physical index of the PF
 142  */
 143 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)  ((rep_based_pf) > 15)
 144 /*
 145  * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
 146  */
 147 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)        ((rep_q_r2f) > 3)
 148
 149 /*
 150  * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
 151  */
 152 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)        ((rep_q_f2r) > 3)
 153
 154 /*
 155  * rep_fc_r2f == Flow control for the representor to endpoint direction
 156  */
 157 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)      ((rep_fc_r2f) > 1)
 158
 159 /*
 160  * rep_fc_f2r == Flow control for the endpoint to representor direction
 161  */
 162 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)      ((rep_fc_f2r) > 1)
 163
 164 int bnxt_cfa_code_dynfield_offset = -1;
 165
 166 /*
 167  * max_num_kflows must be >= 32
 168  * and must be a power-of-2 supported value
 169  * return: 1 -> invalid
 170  *         0 -> valid
 171  */
 172 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
 173 {
 174         if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
 175                 return 1;
 176         return 0;
 177 }
 178
 179 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
 180 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
 181 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
 182 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
 183 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
 184 static int bnxt_restore_vlan_filters(struct bnxt *bp);
 185 static void bnxt_dev_recover(void *arg);
 186 static void bnxt_free_error_recovery_info(struct bnxt *bp);
 187 static void bnxt_free_rep_info(struct bnxt *bp);
 188
 189 int is_bnxt_in_error(struct bnxt *bp)
 190 {
 191         if (bp->flags & BNXT_FLAG_FATAL_ERROR)
 192                 return -EIO;
 193         if (bp->flags & BNXT_FLAG_FW_RESET)
 194                 return -EBUSY;
 195
 196         return 0;
 197 }
 198
 199 /***********************/
 200
 201 /*
 202  * High level utility functions
 203  */
 204
 205 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
 206 {
 207         unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
 208                                              BNXT_RSS_TBL_SIZE_P5);
 209
 210         if (!BNXT_CHIP_P5(bp))
 211                 return 1;
 212
 213         return RTE_ALIGN_MUL_CEIL(num_rss_rings,
 214                                   BNXT_RSS_ENTRIES_PER_CTX_P5) /
 215                                   BNXT_RSS_ENTRIES_PER_CTX_P5;
 216 }
 217
 218 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
 219 {
 220         if (!BNXT_CHIP_P5(bp))
 221                 return HW_HASH_INDEX_SIZE;
 222
 223         return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
 224 }
 225
 226 static void bnxt_free_parent_info(struct bnxt *bp)
 227 {
 228         rte_free(bp->parent);
 229         bp->parent = NULL;
 230 }
 231
 232 static void bnxt_free_pf_info(struct bnxt *bp)
 233 {
 234         rte_free(bp->pf);
 235         bp->pf = NULL;
 236 }
 237
 238 static void bnxt_free_link_info(struct bnxt *bp)
 239 {
 240         rte_free(bp->link_info);
 241         bp->link_info = NULL;
 242 }
 243
 244 static void bnxt_free_leds_info(struct bnxt *bp)
 245 {
 246         if (BNXT_VF(bp))
 247                 return;
 248
 249         rte_free(bp->leds);
 250         bp->leds = NULL;
 251 }
 252
 253 static void bnxt_free_flow_stats_info(struct bnxt *bp)
 254 {
 255         rte_free(bp->flow_stat);
 256         bp->flow_stat = NULL;
 257 }
 258
 259 static void bnxt_free_cos_queues(struct bnxt *bp)
 260 {
 261         rte_free(bp->rx_cos_queue);
 262         bp->rx_cos_queue = NULL;
 263         rte_free(bp->tx_cos_queue);
 264         bp->tx_cos_queue = NULL;
 265 }
 266
 267 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
 268 {
 269         bnxt_free_filter_mem(bp);
 270         bnxt_free_vnic_attributes(bp);
 271         bnxt_free_vnic_mem(bp);
 272
 273         /* tx/rx rings are configured as part of *_queue_setup callbacks.
 274          * If the number of rings change across fw update,
 275          * we don't have much choice except to warn the user.
 276          */
 277         if (!reconfig) {
 278                 bnxt_free_stats(bp);
 279                 bnxt_free_tx_rings(bp);
 280                 bnxt_free_rx_rings(bp);
 281         }
 282         bnxt_free_async_cp_ring(bp);
 283         bnxt_free_rxtx_nq_ring(bp);
 284
 285         rte_free(bp->grp_info);
 286         bp->grp_info = NULL;
 287 }
 288
 289 static int bnxt_alloc_parent_info(struct bnxt *bp)
 290 {
 291         bp->parent = rte_zmalloc("bnxt_parent_info",
 292                                  sizeof(struct bnxt_parent_info), 0);
 293         if (bp->parent == NULL)
 294                 return -ENOMEM;
 295
 296         return 0;
 297 }
 298
 299 static int bnxt_alloc_pf_info(struct bnxt *bp)
 300 {
 301         bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
 302         if (bp->pf == NULL)
 303                 return -ENOMEM;
 304
 305         return 0;
 306 }
 307
 308 static int bnxt_alloc_link_info(struct bnxt *bp)
 309 {
 310         bp->link_info =
 311                 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
 312         if (bp->link_info == NULL)
 313                 return -ENOMEM;
 314
 315         return 0;
 316 }
 317
 318 static int bnxt_alloc_leds_info(struct bnxt *bp)
 319 {
 320         if (BNXT_VF(bp))
 321                 return 0;
 322
 323         bp->leds = rte_zmalloc("bnxt_leds",
 324                                BNXT_MAX_LED * sizeof(struct bnxt_led_info),
 325                                0);
 326         if (bp->leds == NULL)
 327                 return -ENOMEM;
 328
 329         return 0;
 330 }
 331
 332 static int bnxt_alloc_cos_queues(struct bnxt *bp)
 333 {
 334         bp->rx_cos_queue =
 335                 rte_zmalloc("bnxt_rx_cosq",
 336                             BNXT_COS_QUEUE_COUNT *
 337                             sizeof(struct bnxt_cos_queue_info),
 338                             0);
 339         if (bp->rx_cos_queue == NULL)
 340                 return -ENOMEM;
 341
 342         bp->tx_cos_queue =
 343                 rte_zmalloc("bnxt_tx_cosq",
 344                             BNXT_COS_QUEUE_COUNT *
 345                             sizeof(struct bnxt_cos_queue_info),
 346                             0);
 347         if (bp->tx_cos_queue == NULL)
 348                 return -ENOMEM;
 349
 350         return 0;
 351 }
 352
 353 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
 354 {
 355         bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
 356                                     sizeof(struct bnxt_flow_stat_info), 0);
 357         if (bp->flow_stat == NULL)
 358                 return -ENOMEM;
 359
 360         return 0;
 361 }
 362
 363 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
 364 {
 365         int rc;
 366
 367         rc = bnxt_alloc_ring_grps(bp);
 368         if (rc)
 369                 goto alloc_mem_err;
 370
 371         rc = bnxt_alloc_async_ring_struct(bp);
 372         if (rc)
 373                 goto alloc_mem_err;
 374
 375         rc = bnxt_alloc_vnic_mem(bp);
 376         if (rc)
 377                 goto alloc_mem_err;
 378
 379         rc = bnxt_alloc_vnic_attributes(bp);
 380         if (rc)
 381                 goto alloc_mem_err;
 382
 383         rc = bnxt_alloc_filter_mem(bp);
 384         if (rc)
 385                 goto alloc_mem_err;
 386
 387         rc = bnxt_alloc_async_cp_ring(bp);
 388         if (rc)
 389                 goto alloc_mem_err;
 390
 391         rc = bnxt_alloc_rxtx_nq_ring(bp);
 392         if (rc)
 393                 goto alloc_mem_err;
 394
 395         if (BNXT_FLOW_XSTATS_EN(bp)) {
 396                 rc = bnxt_alloc_flow_stats_info(bp);
 397                 if (rc)
 398                         goto alloc_mem_err;
 399         }
 400
 401         return 0;
 402
 403 alloc_mem_err:
 404         bnxt_free_mem(bp, reconfig);
 405         return rc;
 406 }
 407
 408 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
 409 {
 410         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
 411         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
 412         uint64_t rx_offloads = dev_conf->rxmode.offloads;
 413         struct bnxt_rx_queue *rxq;
 414         unsigned int j;
 415         int rc;
 416
 417         rc = bnxt_vnic_grp_alloc(bp, vnic);
 418         if (rc)
 419                 goto err_out;
 420
 421         PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
 422                     vnic_id, vnic, vnic->fw_grp_ids);
 423
 424         rc = bnxt_hwrm_vnic_alloc(bp, vnic);
 425         if (rc)
 426                 goto err_out;
 427
 428         /* Alloc RSS context only if RSS mode is enabled */
 429         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
 430                 int j, nr_ctxs = bnxt_rss_ctxts(bp);
 431
 432                 /* RSS table size in Thor is 512.
 433                  * Cap max Rx rings to same value
 434                  */
 435                 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
 436                         PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
 437                                     bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
 438                         goto err_out;
 439                 }
 440
 441                 rc = 0;
 442                 for (j = 0; j < nr_ctxs; j++) {
 443                         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
 444                         if (rc)
 445                                 break;
 446                 }
 447                 if (rc) {
 448                         PMD_DRV_LOG(ERR,
 449                                     "HWRM vnic %d ctx %d alloc failure rc: %x\n",
 450                                     vnic_id, j, rc);
 451                         goto err_out;
 452                 }
 453                 vnic->num_lb_ctxts = nr_ctxs;
 454         }
 455
 456         /*
 457          * Firmware sets pf pair in default vnic cfg. If the VLAN strip
 458          * setting is not available at this time, it will not be
 459          * configured correctly in the CFA.
 460          */
 461         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 462                 vnic->vlan_strip = true;
 463         else
 464                 vnic->vlan_strip = false;
 465
 466         rc = bnxt_hwrm_vnic_cfg(bp, vnic);
 467         if (rc)
 468                 goto err_out;
 469
 470         rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
 471         if (rc)
 472                 goto err_out;
 473
 474         for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
 475                 rxq = bp->eth_dev->data->rx_queues[j];
 476
 477                 PMD_DRV_LOG(DEBUG,
 478                             "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
 479                             j, rxq->vnic, rxq->vnic->fw_grp_ids);
 480
 481                 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
 482                         rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
 483                 else
 484                         vnic->rx_queue_cnt++;
 485         }
 486
 487         PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
 488
 489         rc = bnxt_vnic_rss_configure(bp, vnic);
 490         if (rc)
 491                 goto err_out;
 492
 493         bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
 494
 495         rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic,
 496                                     (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) ?
 497                                     true : false);
 498         if (rc)
 499                 goto err_out;
 500
 501         return 0;
 502 err_out:
 503         PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
 504                     vnic_id, rc);
 505         return rc;
 506 }
 507
 508 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
 509 {
 510         int rc = 0;
 511
 512         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
 513                                 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
 514         if (rc)
 515                 return rc;
 516
 517         PMD_DRV_LOG(DEBUG,
 518                     "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
 519                     " rx_fc_in_tbl.ctx_id = %d\n",
 520                     bp->flow_stat->rx_fc_in_tbl.va,
 521                     (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
 522                     bp->flow_stat->rx_fc_in_tbl.ctx_id);
 523
 524         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
 525                                 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
 526         if (rc)
 527                 return rc;
 528
 529         PMD_DRV_LOG(DEBUG,
 530                     "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
 531                     " rx_fc_out_tbl.ctx_id = %d\n",
 532                     bp->flow_stat->rx_fc_out_tbl.va,
 533                     (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
 534                     bp->flow_stat->rx_fc_out_tbl.ctx_id);
 535
 536         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
 537                                 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
 538         if (rc)
 539                 return rc;
 540
 541         PMD_DRV_LOG(DEBUG,
 542                     "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
 543                     " tx_fc_in_tbl.ctx_id = %d\n",
 544                     bp->flow_stat->tx_fc_in_tbl.va,
 545                     (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
 546                     bp->flow_stat->tx_fc_in_tbl.ctx_id);
 547
 548         rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
 549                                 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
 550         if (rc)
 551                 return rc;
 552
 553         PMD_DRV_LOG(DEBUG,
 554                     "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
 555                     " tx_fc_out_tbl.ctx_id = %d\n",
 556                     bp->flow_stat->tx_fc_out_tbl.va,
 557                     (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
 558                     bp->flow_stat->tx_fc_out_tbl.ctx_id);
 559
 560         memset(bp->flow_stat->rx_fc_out_tbl.va,
 561                0,
 562                bp->flow_stat->rx_fc_out_tbl.size);
 563         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
 564                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 565                                        bp->flow_stat->rx_fc_out_tbl.ctx_id,
 566                                        bp->flow_stat->max_fc,
 567                                        true);
 568         if (rc)
 569                 return rc;
 570
 571         memset(bp->flow_stat->tx_fc_out_tbl.va,
 572                0,
 573                bp->flow_stat->tx_fc_out_tbl.size);
 574         rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
 575                                        CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
 576                                        bp->flow_stat->tx_fc_out_tbl.ctx_id,
 577                                        bp->flow_stat->max_fc,
 578                                        true);
 579
 580         return rc;
 581 }
 582
 583 static int bnxt_alloc_ctx_mem_buf(struct bnxt *bp, char *type, size_t size,
 584                                   struct bnxt_ctx_mem_buf_info *ctx)
 585 {
 586         if (!ctx)
 587                 return -EINVAL;
 588
 589         ctx->va = rte_zmalloc_socket(type, size, 0,
 590                                      bp->eth_dev->device->numa_node);
 591         if (ctx->va == NULL)
 592                 return -ENOMEM;
 593         rte_mem_lock_page(ctx->va);
 594         ctx->size = size;
 595         ctx->dma = rte_mem_virt2iova(ctx->va);
 596         if (ctx->dma == RTE_BAD_IOVA)
 597                 return -ENOMEM;
 598
 599         return 0;
 600 }
 601
 602 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
 603 {
 604         struct rte_pci_device *pdev = bp->pdev;
 605         char type[RTE_MEMZONE_NAMESIZE];
 606         uint16_t max_fc;
 607         int rc = 0;
 608
 609         max_fc = bp->flow_stat->max_fc;
 610
 611         sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 612                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 613         /* 4 bytes for each counter-id */
 614         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 615                                     max_fc * 4,
 616                                     &bp->flow_stat->rx_fc_in_tbl);
 617         if (rc)
 618                 return rc;
 619
 620         sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 621                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 622         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 623         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 624                                     max_fc * 16,
 625                                     &bp->flow_stat->rx_fc_out_tbl);
 626         if (rc)
 627                 return rc;
 628
 629         sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
 630                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 631         /* 4 bytes for each counter-id */
 632         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 633                                     max_fc * 4,
 634                                     &bp->flow_stat->tx_fc_in_tbl);
 635         if (rc)
 636                 return rc;
 637
 638         sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
 639                 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
 640         /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
 641         rc = bnxt_alloc_ctx_mem_buf(bp, type,
 642                                     max_fc * 16,
 643                                     &bp->flow_stat->tx_fc_out_tbl);
 644         if (rc)
 645                 return rc;
 646
 647         rc = bnxt_register_fc_ctx_mem(bp);
 648
 649         return rc;
 650 }
 651
 652 static int bnxt_init_ctx_mem(struct bnxt *bp)
 653 {
 654         int rc = 0;
 655
 656         if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
 657             !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
 658             !BNXT_FLOW_XSTATS_EN(bp))
 659                 return 0;
 660
 661         rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
 662         if (rc)
 663                 return rc;
 664
 665         rc = bnxt_init_fc_ctx_mem(bp);
 666
 667         return rc;
 668 }
 669
 670 static int bnxt_update_phy_setting(struct bnxt *bp)
 671 {
 672         struct rte_eth_link new;
 673         int rc;
 674
 675         rc = bnxt_get_hwrm_link_config(bp, &new);
 676         if (rc) {
 677                 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
 678                 return rc;
 679         }
 680
 681         /*
 682          * On BCM957508-N2100 adapters, FW will not allow any user other
 683          * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
 684          * always returns link up. Force phy update always in that case.
 685          */
 686         if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
 687                 rc = bnxt_set_hwrm_link_config(bp, true);
 688                 if (rc) {
 689                         PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
 690                         return rc;
 691                 }
 692         }
 693
 694         return rc;
 695 }
 696
 697 static void bnxt_free_prev_ring_stats(struct bnxt *bp)
 698 {
 699         rte_free(bp->prev_rx_ring_stats);
 700         rte_free(bp->prev_tx_ring_stats);
 701
 702         bp->prev_rx_ring_stats = NULL;
 703         bp->prev_tx_ring_stats = NULL;
 704 }
 705
 706 static int bnxt_alloc_prev_ring_stats(struct bnxt *bp)
 707 {
 708         bp->prev_rx_ring_stats =  rte_zmalloc("bnxt_prev_rx_ring_stats",
 709                                               sizeof(struct bnxt_ring_stats) *
 710                                               bp->rx_cp_nr_rings,
 711                                               0);
 712         if (bp->prev_rx_ring_stats == NULL)
 713                 return -ENOMEM;
 714
 715         bp->prev_tx_ring_stats = rte_zmalloc("bnxt_prev_tx_ring_stats",
 716                                              sizeof(struct bnxt_ring_stats) *
 717                                              bp->tx_cp_nr_rings,
 718                                              0);
 719         if (bp->prev_tx_ring_stats == NULL)
 720                 goto error;
 721
 722         return 0;
 723
 724 error:
 725         bnxt_free_prev_ring_stats(bp);
 726         return -ENOMEM;
 727 }
 728
 729 static int bnxt_start_nic(struct bnxt *bp)
 730 {
 731         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
 732         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 733         uint32_t intr_vector = 0;
 734         uint32_t queue_id, base = BNXT_MISC_VEC_ID;
 735         uint32_t vec = BNXT_MISC_VEC_ID;
 736         unsigned int i, j;
 737         int rc;
 738
 739         if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
 740                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
 741                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 742                 bp->flags |= BNXT_FLAG_JUMBO;
 743         } else {
 744                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
 745                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 746                 bp->flags &= ~BNXT_FLAG_JUMBO;
 747         }
 748
 749         /* THOR does not support ring groups.
 750          * But we will use the array to save RSS context IDs.
 751          */
 752         if (BNXT_CHIP_P5(bp))
 753                 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
 754
 755         rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
 756         if (rc) {
 757                 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
 758                 goto err_out;
 759         }
 760
 761         rc = bnxt_alloc_hwrm_rings(bp);
 762         if (rc) {
 763                 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
 764                 goto err_out;
 765         }
 766
 767         rc = bnxt_alloc_all_hwrm_ring_grps(bp);
 768         if (rc) {
 769                 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
 770                 goto err_out;
 771         }
 772
 773         if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
 774                 goto skip_cosq_cfg;
 775
 776         for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
 777                 if (bp->rx_cos_queue[i].id != 0xff) {
 778                         struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
 779
 780                         if (!vnic) {
 781                                 PMD_DRV_LOG(ERR,
 782                                             "Num pools more than FW profile\n");
 783                                 rc = -EINVAL;
 784                                 goto err_out;
 785                         }
 786                         vnic->cos_queue_id = bp->rx_cos_queue[i].id;
 787                         bp->rx_cosq_cnt++;
 788                 }
 789         }
 790
 791 skip_cosq_cfg:
 792         rc = bnxt_mq_rx_configure(bp);
 793         if (rc) {
 794                 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
 795                 goto err_out;
 796         }
 797
 798         /* default vnic 0 */
 799         rc = bnxt_setup_one_vnic(bp, 0);
 800         if (rc)
 801                 goto err_out;
 802         /* VNIC configuration */
 803         if (BNXT_RFS_NEEDS_VNIC(bp)) {
 804                 for (i = 1; i < bp->nr_vnics; i++) {
 805                         rc = bnxt_setup_one_vnic(bp, i);
 806                         if (rc)
 807                                 goto err_out;
 808                 }
 809         }
 810
 811         for (j = 0; j < bp->tx_nr_rings; j++) {
 812                 struct bnxt_tx_queue *txq = bp->tx_queues[j];
 813
 814                 if (!txq->tx_deferred_start) {
 815                         bp->eth_dev->data->tx_queue_state[j] =
 816                                 RTE_ETH_QUEUE_STATE_STARTED;
 817                         txq->tx_started = true;
 818                 }
 819         }
 820
 821         for (j = 0; j < bp->rx_nr_rings; j++) {
 822                 struct bnxt_rx_queue *rxq = bp->rx_queues[j];
 823
 824                 if (!rxq->rx_deferred_start) {
 825                         bp->eth_dev->data->rx_queue_state[j] =
 826                                 RTE_ETH_QUEUE_STATE_STARTED;
 827                         rxq->rx_started = true;
 828                 }
 829         }
 830
 831         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
 832         if (rc) {
 833                 PMD_DRV_LOG(ERR,
 834                         "HWRM cfa l2 rx mask failure rc: %x\n", rc);
 835                 goto err_out;
 836         }
 837
 838         /* check and configure queue intr-vector mapping */
 839         if ((rte_intr_cap_multiple(intr_handle) ||
 840              !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
 841             bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
 842                 intr_vector = bp->eth_dev->data->nb_rx_queues;
 843                 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
 844                 if (intr_vector > bp->rx_cp_nr_rings) {
 845                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
 846                                         bp->rx_cp_nr_rings);
 847                         return -ENOTSUP;
 848                 }
 849                 rc = rte_intr_efd_enable(intr_handle, intr_vector);
 850                 if (rc)
 851                         return rc;
 852         }
 853
 854         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 855                 intr_handle->intr_vec =
 856                         rte_zmalloc("intr_vec",
 857                                     bp->eth_dev->data->nb_rx_queues *
 858                                     sizeof(int), 0);
 859                 if (intr_handle->intr_vec == NULL) {
 860                         PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
 861                                 " intr_vec", bp->eth_dev->data->nb_rx_queues);
 862                         rc = -ENOMEM;
 863                         goto err_out;
 864                 }
 865                 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
 866                         "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
 867                          intr_handle->intr_vec, intr_handle->nb_efd,
 868                         intr_handle->max_intr);
 869                 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
 870                      queue_id++) {
 871                         intr_handle->intr_vec[queue_id] =
 872                                                         vec + BNXT_RX_VEC_START;
 873                         if (vec < base + intr_handle->nb_efd - 1)
 874                                 vec++;
 875                 }
 876         }
 877
 878         /* enable uio/vfio intr/eventfd mapping */
 879         rc = rte_intr_enable(intr_handle);
 880 #ifndef RTE_EXEC_ENV_FREEBSD
 881         /* In FreeBSD OS, nic_uio driver does not support interrupts */
 882         if (rc)
 883                 goto err_out;
 884 #endif
 885
 886         rc = bnxt_update_phy_setting(bp);
 887         if (rc)
 888                 goto err_out;
 889
 890         bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
 891         if (!bp->mark_table)
 892                 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
 893
 894         return 0;
 895
 896 err_out:
 897         /* Some of the error status returned by FW may not be from errno.h */
 898         if (rc > 0)
 899                 rc = -EIO;
 900
 901         return rc;
 902 }
 903
 904 static int bnxt_shutdown_nic(struct bnxt *bp)
 905 {
 906         bnxt_free_all_hwrm_resources(bp);
 907         bnxt_free_all_filters(bp);
 908         bnxt_free_all_vnics(bp);
 909         return 0;
 910 }
 911
 912 /*
 913  * Device configuration and status function
 914  */
 915
 916 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
 917 {
 918         uint32_t link_speed = 0;
 919         uint32_t speed_capa = 0;
 920
 921         if (bp->link_info == NULL)
 922                 return 0;
 923
 924         link_speed = bp->link_info->support_speeds;
 925
 926         /* If PAM4 is configured, use PAM4 supported speed */
 927         if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
 928                 link_speed = bp->link_info->support_pam4_speeds;
 929
 930         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
 931                 speed_capa |= ETH_LINK_SPEED_100M;
 932         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
 933                 speed_capa |= ETH_LINK_SPEED_100M_HD;
 934         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
 935                 speed_capa |= ETH_LINK_SPEED_1G;
 936         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
 937                 speed_capa |= ETH_LINK_SPEED_2_5G;
 938         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
 939                 speed_capa |= ETH_LINK_SPEED_10G;
 940         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
 941                 speed_capa |= ETH_LINK_SPEED_20G;
 942         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
 943                 speed_capa |= ETH_LINK_SPEED_25G;
 944         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
 945                 speed_capa |= ETH_LINK_SPEED_40G;
 946         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
 947                 speed_capa |= ETH_LINK_SPEED_50G;
 948         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
 949                 speed_capa |= ETH_LINK_SPEED_100G;
 950         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
 951                 speed_capa |= ETH_LINK_SPEED_50G;
 952         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
 953                 speed_capa |= ETH_LINK_SPEED_100G;
 954         if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
 955                 speed_capa |= ETH_LINK_SPEED_200G;
 956
 957         if (bp->link_info->auto_mode ==
 958             HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
 959                 speed_capa |= ETH_LINK_SPEED_FIXED;
 960
 961         return speed_capa;
 962 }
 963
 964 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
 965                                 struct rte_eth_dev_info *dev_info)
 966 {
 967         struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
 968         struct bnxt *bp = eth_dev->data->dev_private;
 969         uint16_t max_vnics, i, j, vpool, vrxq;
 970         unsigned int max_rx_rings;
 971         int rc;
 972
 973         rc = is_bnxt_in_error(bp);
 974         if (rc)
 975                 return rc;
 976
 977         /* MAC Specifics */
 978         dev_info->max_mac_addrs = bp->max_l2_ctx;
 979         dev_info->max_hash_mac_addrs = 0;
 980
 981         /* PF/VF specifics */
 982         if (BNXT_PF(bp))
 983                 dev_info->max_vfs = pdev->max_vfs;
 984
 985         max_rx_rings = bnxt_max_rings(bp);
 986         /* For the sake of symmetry, max_rx_queues = max_tx_queues */
 987         dev_info->max_rx_queues = max_rx_rings;
 988         dev_info->max_tx_queues = max_rx_rings;
 989         dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
 990         dev_info->hash_key_size = HW_HASH_KEY_SIZE;
 991         max_vnics = bp->max_vnics;
 992
 993         /* MTU specifics */
 994         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
 995         dev_info->max_mtu = BNXT_MAX_MTU;
 996
 997         /* Fast path specifics */
 998         dev_info->min_rx_bufsize = 1;
 999         dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
1000
1001         dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
1002         if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
1003                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
1004         if (bp->vnic_cap_flags & BNXT_VNIC_CAP_VLAN_RX_STRIP)
1005                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_VLAN_STRIP;
1006         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
1007         dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
1008                                     dev_info->tx_queue_offload_capa;
1009         if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT)
1010                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_VLAN_INSERT;
1011         dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
1012
1013         dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
1014         dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
1015                              RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
1016
1017         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1018                 .rx_thresh = {
1019                         .pthresh = 8,
1020                         .hthresh = 8,
1021                         .wthresh = 0,
1022                 },
1023                 .rx_free_thresh = 32,
1024                 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
1025         };
1026
1027         dev_info->default_txconf = (struct rte_eth_txconf) {
1028                 .tx_thresh = {
1029                         .pthresh = 32,
1030                         .hthresh = 0,
1031                         .wthresh = 0,
1032                 },
1033                 .tx_free_thresh = 32,
1034                 .tx_rs_thresh = 32,
1035         };
1036         eth_dev->data->dev_conf.intr_conf.lsc = 1;
1037
1038         dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1039         dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
1040         dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
1041         dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
1042
1043         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
1044                 dev_info->switch_info.name = eth_dev->device->name;
1045                 dev_info->switch_info.domain_id = bp->switch_domain_id;
1046                 dev_info->switch_info.port_id =
1047                                 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
1048                                     BNXT_SWITCH_PORT_ID_TRUSTED_VF;
1049         }
1050
1051         /*
1052          * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
1053          *       need further investigation.
1054          */
1055
1056         /* VMDq resources */
1057         vpool = 64; /* ETH_64_POOLS */
1058         vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
1059         for (i = 0; i < 4; vpool >>= 1, i++) {
1060                 if (max_vnics > vpool) {
1061                         for (j = 0; j < 5; vrxq >>= 1, j++) {
1062                                 if (dev_info->max_rx_queues > vrxq) {
1063                                         if (vpool > vrxq)
1064                                                 vpool = vrxq;
1065                                         goto found;
1066                                 }
1067                         }
1068                         /* Not enough resources to support VMDq */
1069                         break;
1070                 }
1071         }
1072         /* Not enough resources to support VMDq */
1073         vpool = 0;
1074         vrxq = 0;
1075 found:
1076         dev_info->max_vmdq_pools = vpool;
1077         dev_info->vmdq_queue_num = vrxq;
1078
1079         dev_info->vmdq_pool_base = 0;
1080         dev_info->vmdq_queue_base = 0;
1081
1082         return 0;
1083 }
1084
1085 /* Configure the device based on the configuration provided */
1086 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1087 {
1088         struct bnxt *bp = eth_dev->data->dev_private;
1089         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1090         int rc;
1091
1092         bp->rx_queues = (void *)eth_dev->data->rx_queues;
1093         bp->tx_queues = (void *)eth_dev->data->tx_queues;
1094         bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1095         bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1096
1097         rc = is_bnxt_in_error(bp);
1098         if (rc)
1099                 return rc;
1100
1101         if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1102                 rc = bnxt_hwrm_check_vf_rings(bp);
1103                 if (rc) {
1104                         PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1105                         return -ENOSPC;
1106                 }
1107
1108                 /* If a resource has already been allocated - in this case
1109                  * it is the async completion ring, free it. Reallocate it after
1110                  * resource reservation. This will ensure the resource counts
1111                  * are calculated correctly.
1112                  */
1113
1114                 pthread_mutex_lock(&bp->def_cp_lock);
1115
1116                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1117                         bnxt_disable_int(bp);
1118                         bnxt_free_cp_ring(bp, bp->async_cp_ring);
1119                 }
1120
1121                 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1122                 if (rc) {
1123                         PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1124                         pthread_mutex_unlock(&bp->def_cp_lock);
1125                         return -ENOSPC;
1126                 }
1127
1128                 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1129                         rc = bnxt_alloc_async_cp_ring(bp);
1130                         if (rc) {
1131                                 pthread_mutex_unlock(&bp->def_cp_lock);
1132                                 return rc;
1133                         }
1134                         bnxt_enable_int(bp);
1135                 }
1136
1137                 pthread_mutex_unlock(&bp->def_cp_lock);
1138         }
1139
1140         /* Inherit new configurations */
1141         if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1142             eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1143             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1144                 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1145             eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1146             bp->max_stat_ctx)
1147                 goto resource_error;
1148
1149         if (BNXT_HAS_RING_GRPS(bp) &&
1150             (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1151                 goto resource_error;
1152
1153         if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1154             bp->max_vnics < eth_dev->data->nb_rx_queues)
1155                 goto resource_error;
1156
1157         bp->rx_cp_nr_rings = bp->rx_nr_rings;
1158         bp->tx_cp_nr_rings = bp->tx_nr_rings;
1159
1160         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1161                 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1162         eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1163
1164         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1165                 eth_dev->data->mtu =
1166                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1167                         RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1168                         BNXT_NUM_VLANS;
1169                 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1170         }
1171         return 0;
1172
1173 resource_error:
1174         PMD_DRV_LOG(ERR,
1175                     "Insufficient resources to support requested config\n");
1176         PMD_DRV_LOG(ERR,
1177                     "Num Queues Requested: Tx %d, Rx %d\n",
1178                     eth_dev->data->nb_tx_queues,
1179                     eth_dev->data->nb_rx_queues);
1180         PMD_DRV_LOG(ERR,
1181                     "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1182                     bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1183                     bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1184         return -ENOSPC;
1185 }
1186
1187 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1188 {
1189         struct rte_eth_link *link = &eth_dev->data->dev_link;
1190
1191         if (link->link_status)
1192                 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1193                         eth_dev->data->port_id,
1194                         (uint32_t)link->link_speed,
1195                         (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1196                         ("full-duplex") : ("half-duplex\n"));
1197         else
1198                 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1199                         eth_dev->data->port_id);
1200 }
1201
1202 /*
1203  * Determine whether the current configuration requires support for scattered
1204  * receive; return 1 if scattered receive is required and 0 if not.
1205  */
1206 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1207 {
1208         uint16_t buf_size;
1209         int i;
1210
1211         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1212                 return 1;
1213
1214         if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
1215                 return 1;
1216
1217         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1218                 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1219
1220                 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1221                                       RTE_PKTMBUF_HEADROOM);
1222                 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1223                         return 1;
1224         }
1225         return 0;
1226 }
1227
1228 static eth_rx_burst_t
1229 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1230 {
1231         struct bnxt *bp = eth_dev->data->dev_private;
1232
1233         /* Disable vector mode RX for Stingray2 for now */
1234         if (BNXT_CHIP_SR2(bp)) {
1235                 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1236                 return bnxt_recv_pkts;
1237         }
1238
1239 #if (defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)) && \
1240         !defined(RTE_LIBRTE_IEEE1588)
1241
1242         /* Vector mode receive cannot be enabled if scattered rx is in use. */
1243         if (eth_dev->data->scattered_rx)
1244                 goto use_scalar_rx;
1245
1246         /*
1247          * Vector mode receive cannot be enabled if Truflow is enabled or if
1248          * asynchronous completions and receive completions can be placed in
1249          * the same completion ring.
1250          */
1251         if (BNXT_TRUFLOW_EN(bp) || !BNXT_NUM_ASYNC_CPR(bp))
1252                 goto use_scalar_rx;
1253
1254         /*
1255          * Vector mode receive cannot be enabled if any receive offloads outside
1256          * a limited subset have been enabled.
1257          */
1258         if (eth_dev->data->dev_conf.rxmode.offloads &
1259                 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1260                   DEV_RX_OFFLOAD_KEEP_CRC |
1261                   DEV_RX_OFFLOAD_JUMBO_FRAME |
1262                   DEV_RX_OFFLOAD_IPV4_CKSUM |
1263                   DEV_RX_OFFLOAD_UDP_CKSUM |
1264                   DEV_RX_OFFLOAD_TCP_CKSUM |
1265                   DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1266                   DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1267                   DEV_RX_OFFLOAD_RSS_HASH |
1268                   DEV_RX_OFFLOAD_VLAN_FILTER))
1269                 goto use_scalar_rx;
1270
1271 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1272         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1273             rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1274                 PMD_DRV_LOG(INFO,
1275                             "Using AVX2 vector mode receive for port %d\n",
1276                             eth_dev->data->port_id);
1277                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1278                 return bnxt_recv_pkts_vec_avx2;
1279         }
1280  #endif
1281         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1282                 PMD_DRV_LOG(INFO,
1283                             "Using SSE vector mode receive for port %d\n",
1284                             eth_dev->data->port_id);
1285                 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1286                 return bnxt_recv_pkts_vec;
1287         }
1288
1289 use_scalar_rx:
1290         PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1291                     eth_dev->data->port_id);
1292         PMD_DRV_LOG(INFO,
1293                     "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1294                     eth_dev->data->port_id,
1295                     eth_dev->data->scattered_rx,
1296                     eth_dev->data->dev_conf.rxmode.offloads);
1297 #endif
1298         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1299         return bnxt_recv_pkts;
1300 }
1301
1302 static eth_tx_burst_t
1303 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1304 {
1305         struct bnxt *bp = eth_dev->data->dev_private;
1306
1307         /* Disable vector mode TX for Stingray2 for now */
1308         if (BNXT_CHIP_SR2(bp))
1309                 return bnxt_xmit_pkts;
1310
1311 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) && \
1312         !defined(RTE_LIBRTE_IEEE1588)
1313         uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1314
1315         /*
1316          * Vector mode transmit can be enabled only if not using scatter rx
1317          * or tx offloads.
1318          */
1319         if (eth_dev->data->scattered_rx ||
1320             (offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) ||
1321             BNXT_TRUFLOW_EN(bp))
1322                 goto use_scalar_tx;
1323
1324 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
1325         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 &&
1326             rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) {
1327                 PMD_DRV_LOG(INFO,
1328                             "Using AVX2 vector mode transmit for port %d\n",
1329                             eth_dev->data->port_id);
1330                 return bnxt_xmit_pkts_vec_avx2;
1331         }
1332 #endif
1333         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1334                 PMD_DRV_LOG(INFO,
1335                             "Using SSE vector mode transmit for port %d\n",
1336                             eth_dev->data->port_id);
1337                 return bnxt_xmit_pkts_vec;
1338         }
1339
1340 use_scalar_tx:
1341         PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1342                     eth_dev->data->port_id);
1343         PMD_DRV_LOG(INFO,
1344                     "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1345                     eth_dev->data->port_id,
1346                     eth_dev->data->scattered_rx,
1347                     offloads);
1348 #endif
1349         return bnxt_xmit_pkts;
1350 }
1351
1352 static int bnxt_handle_if_change_status(struct bnxt *bp)
1353 {
1354         int rc;
1355
1356         /* Since fw has undergone a reset and lost all contexts,
1357          * set fatal flag to not issue hwrm during cleanup
1358          */
1359         bp->flags |= BNXT_FLAG_FATAL_ERROR;
1360         bnxt_uninit_resources(bp, true);
1361
1362         /* clear fatal flag so that re-init happens */
1363         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1364         rc = bnxt_init_resources(bp, true);
1365
1366         bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1367
1368         return rc;
1369 }
1370
1371 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1372 {
1373         struct bnxt *bp = eth_dev->data->dev_private;
1374         int rc = 0;
1375
1376         if (!BNXT_SINGLE_PF(bp))
1377                 return -ENOTSUP;
1378
1379         if (!bp->link_info->link_up)
1380                 rc = bnxt_set_hwrm_link_config(bp, true);
1381         if (!rc)
1382                 eth_dev->data->dev_link.link_status = 1;
1383
1384         bnxt_print_link_info(eth_dev);
1385         return rc;
1386 }
1387
1388 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1389 {
1390         struct bnxt *bp = eth_dev->data->dev_private;
1391
1392         if (!BNXT_SINGLE_PF(bp))
1393                 return -ENOTSUP;
1394
1395         eth_dev->data->dev_link.link_status = 0;
1396         bnxt_set_hwrm_link_config(bp, false);
1397         bp->link_info->link_up = 0;
1398
1399         return 0;
1400 }
1401
1402 static void bnxt_free_switch_domain(struct bnxt *bp)
1403 {
1404         int rc = 0;
1405
1406         if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)))
1407                 return;
1408
1409         rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1410         if (rc)
1411                 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1412                             bp->switch_domain_id, rc);
1413 }
1414
1415 static void bnxt_ptp_get_current_time(void *arg)
1416 {
1417         struct bnxt *bp = arg;
1418         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1419         int rc;
1420
1421         rc = is_bnxt_in_error(bp);
1422         if (rc)
1423                 return;
1424
1425         if (!ptp)
1426                 return;
1427
1428         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1429                                 &ptp->current_time);
1430
1431         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1432         if (rc != 0) {
1433                 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1434                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1435         }
1436 }
1437
1438 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1439 {
1440         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1441         int rc;
1442
1443         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1444                 return 0;
1445
1446         bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1447                                 &ptp->current_time);
1448
1449         rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1450         return rc;
1451 }
1452
1453 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1454 {
1455         if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1456                 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1457                 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1458         }
1459 }
1460
1461 static void bnxt_ptp_stop(struct bnxt *bp)
1462 {
1463         bnxt_cancel_ptp_alarm(bp);
1464         bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1465 }
1466
1467 static int bnxt_ptp_start(struct bnxt *bp)
1468 {
1469         int rc;
1470
1471         rc = bnxt_schedule_ptp_alarm(bp);
1472         if (rc != 0) {
1473                 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1474         } else {
1475                 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1476                 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1477         }
1478
1479         return rc;
1480 }
1481
1482 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1483 {
1484         struct bnxt *bp = eth_dev->data->dev_private;
1485         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1486         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1487         struct rte_eth_link link;
1488         int ret;
1489
1490         eth_dev->data->dev_started = 0;
1491         eth_dev->data->scattered_rx = 0;
1492
1493         /* Prevent crashes when queues are still in use */
1494         eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1495         eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1496
1497         bnxt_disable_int(bp);
1498
1499         /* disable uio/vfio intr/eventfd mapping */
1500         rte_intr_disable(intr_handle);
1501
1502         /* Stop the child representors for this device */
1503         ret = bnxt_rep_stop_all(bp);
1504         if (ret != 0)
1505                 return ret;
1506
1507         /* delete the bnxt ULP port details */
1508         bnxt_ulp_port_deinit(bp);
1509
1510         bnxt_cancel_fw_health_check(bp);
1511
1512         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1513                 bnxt_cancel_ptp_alarm(bp);
1514
1515         /* Do not bring link down during reset recovery */
1516         if (!is_bnxt_in_error(bp)) {
1517                 bnxt_dev_set_link_down_op(eth_dev);
1518                 /* Wait for link to be reset */
1519                 if (BNXT_SINGLE_PF(bp))
1520                         rte_delay_ms(500);
1521                 /* clear the recorded link status */
1522                 memset(&link, 0, sizeof(link));
1523                 rte_eth_linkstatus_set(eth_dev, &link);
1524         }
1525
1526         /* Clean queue intr-vector mapping */
1527         rte_intr_efd_disable(intr_handle);
1528         if (intr_handle->intr_vec != NULL) {
1529                 rte_free(intr_handle->intr_vec);
1530                 intr_handle->intr_vec = NULL;
1531         }
1532
1533         bnxt_hwrm_port_clr_stats(bp);
1534         bnxt_free_tx_mbufs(bp);
1535         bnxt_free_rx_mbufs(bp);
1536         /* Process any remaining notifications in default completion queue */
1537         bnxt_int_handler(eth_dev);
1538         bnxt_shutdown_nic(bp);
1539         bnxt_hwrm_if_change(bp, false);
1540
1541         bnxt_free_prev_ring_stats(bp);
1542         rte_free(bp->mark_table);
1543         bp->mark_table = NULL;
1544
1545         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1546         bp->rx_cosq_cnt = 0;
1547         /* All filters are deleted on a port stop. */
1548         if (BNXT_FLOW_XSTATS_EN(bp))
1549                 bp->flow_stat->flow_count = 0;
1550
1551         return 0;
1552 }
1553
1554 /* Unload the driver, release resources */
1555 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1556 {
1557         struct bnxt *bp = eth_dev->data->dev_private;
1558
1559         pthread_mutex_lock(&bp->err_recovery_lock);
1560         if (bp->flags & BNXT_FLAG_FW_RESET) {
1561                 PMD_DRV_LOG(ERR,
1562                             "Adapter recovering from error..Please retry\n");
1563                 pthread_mutex_unlock(&bp->err_recovery_lock);
1564                 return -EAGAIN;
1565         }
1566         pthread_mutex_unlock(&bp->err_recovery_lock);
1567
1568         return bnxt_dev_stop(eth_dev);
1569 }
1570
1571 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1572 {
1573         struct bnxt *bp = eth_dev->data->dev_private;
1574         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1575         int vlan_mask = 0;
1576         int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1577
1578         if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1579                 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1580                 return -EINVAL;
1581         }
1582
1583         if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1584                 PMD_DRV_LOG(ERR,
1585                             "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1586                             bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1587
1588         do {
1589                 rc = bnxt_hwrm_if_change(bp, true);
1590                 if (rc == 0 || rc != -EAGAIN)
1591                         break;
1592
1593                 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1594         } while (retry_cnt--);
1595
1596         if (rc)
1597                 return rc;
1598
1599         if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1600                 rc = bnxt_handle_if_change_status(bp);
1601                 if (rc)
1602                         return rc;
1603         }
1604
1605         bnxt_enable_int(bp);
1606
1607         eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1608
1609         rc = bnxt_start_nic(bp);
1610         if (rc)
1611                 goto error;
1612
1613         rc = bnxt_alloc_prev_ring_stats(bp);
1614         if (rc)
1615                 goto error;
1616
1617         eth_dev->data->dev_started = 1;
1618
1619         bnxt_link_update_op(eth_dev, 1);
1620
1621         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1622                 vlan_mask |= ETH_VLAN_FILTER_MASK;
1623         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1624                 vlan_mask |= ETH_VLAN_STRIP_MASK;
1625         rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1626         if (rc)
1627                 goto error;
1628
1629         /* Initialize bnxt ULP port details */
1630         rc = bnxt_ulp_port_init(bp);
1631         if (rc)
1632                 goto error;
1633
1634         eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1635         eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1636
1637         bnxt_schedule_fw_health_check(bp);
1638
1639         if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1640                 bnxt_schedule_ptp_alarm(bp);
1641
1642         return 0;
1643
1644 error:
1645         bnxt_dev_stop(eth_dev);
1646         return rc;
1647 }
1648
1649 static void
1650 bnxt_uninit_locks(struct bnxt *bp)
1651 {
1652         pthread_mutex_destroy(&bp->flow_lock);
1653         pthread_mutex_destroy(&bp->def_cp_lock);
1654         pthread_mutex_destroy(&bp->health_check_lock);
1655         pthread_mutex_destroy(&bp->err_recovery_lock);
1656         if (bp->rep_info) {
1657                 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1658                 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1659         }
1660 }
1661
1662 static void bnxt_drv_uninit(struct bnxt *bp)
1663 {
1664         bnxt_free_leds_info(bp);
1665         bnxt_free_cos_queues(bp);
1666         bnxt_free_link_info(bp);
1667         bnxt_free_parent_info(bp);
1668         bnxt_uninit_locks(bp);
1669
1670         rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1671         bp->tx_mem_zone = NULL;
1672         rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1673         bp->rx_mem_zone = NULL;
1674
1675         bnxt_free_vf_info(bp);
1676         bnxt_free_pf_info(bp);
1677
1678         rte_free(bp->grp_info);
1679         bp->grp_info = NULL;
1680 }
1681
1682 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1683 {
1684         struct bnxt *bp = eth_dev->data->dev_private;
1685         int ret = 0;
1686
1687         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1688                 return 0;
1689
1690         pthread_mutex_lock(&bp->err_recovery_lock);
1691         if (bp->flags & BNXT_FLAG_FW_RESET) {
1692                 PMD_DRV_LOG(ERR,
1693                             "Adapter recovering from error...Please retry\n");
1694                 pthread_mutex_unlock(&bp->err_recovery_lock);
1695                 return -EAGAIN;
1696         }
1697         pthread_mutex_unlock(&bp->err_recovery_lock);
1698
1699         /* cancel the recovery handler before remove dev */
1700         rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1701         rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1702         bnxt_cancel_fc_thread(bp);
1703
1704         if (eth_dev->data->dev_started)
1705                 ret = bnxt_dev_stop(eth_dev);
1706
1707         bnxt_uninit_resources(bp, false);
1708
1709         bnxt_drv_uninit(bp);
1710
1711         return ret;
1712 }
1713
1714 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1715                                     uint32_t index)
1716 {
1717         struct bnxt *bp = eth_dev->data->dev_private;
1718         uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1719         struct bnxt_vnic_info *vnic;
1720         struct bnxt_filter_info *filter, *temp_filter;
1721         uint32_t i;
1722
1723         if (is_bnxt_in_error(bp))
1724                 return;
1725
1726         /*
1727          * Loop through all VNICs from the specified filter flow pools to
1728          * remove the corresponding MAC addr filter
1729          */
1730         for (i = 0; i < bp->nr_vnics; i++) {
1731                 if (!(pool_mask & (1ULL << i)))
1732                         continue;
1733
1734                 vnic = &bp->vnic_info[i];
1735                 filter = STAILQ_FIRST(&vnic->filter);
1736                 while (filter) {
1737                         temp_filter = STAILQ_NEXT(filter, next);
1738                         if (filter->mac_index == index) {
1739                                 STAILQ_REMOVE(&vnic->filter, filter,
1740                                                 bnxt_filter_info, next);
1741                                 bnxt_hwrm_clear_l2_filter(bp, filter);
1742                                 bnxt_free_filter(bp, filter);
1743                         }
1744                         filter = temp_filter;
1745                 }
1746         }
1747 }
1748
1749 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1750                                struct rte_ether_addr *mac_addr, uint32_t index,
1751                                uint32_t pool)
1752 {
1753         struct bnxt_filter_info *filter;
1754         int rc = 0;
1755
1756         /* Attach requested MAC address to the new l2_filter */
1757         STAILQ_FOREACH(filter, &vnic->filter, next) {
1758                 if (filter->mac_index == index) {
1759                         PMD_DRV_LOG(DEBUG,
1760                                     "MAC addr already existed for pool %d\n",
1761                                     pool);
1762                         return 0;
1763                 }
1764         }
1765
1766         filter = bnxt_alloc_filter(bp);
1767         if (!filter) {
1768                 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1769                 return -ENODEV;
1770         }
1771
1772         /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1773          * if the MAC that's been programmed now is a different one, then,
1774          * copy that addr to filter->l2_addr
1775          */
1776         if (mac_addr)
1777                 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1778         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1779
1780         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1781         if (!rc) {
1782                 filter->mac_index = index;
1783                 if (filter->mac_index == 0)
1784                         STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1785                 else
1786                         STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1787         } else {
1788                 bnxt_free_filter(bp, filter);
1789         }
1790
1791         return rc;
1792 }
1793
1794 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1795                                 struct rte_ether_addr *mac_addr,
1796                                 uint32_t index, uint32_t pool)
1797 {
1798         struct bnxt *bp = eth_dev->data->dev_private;
1799         struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1800         int rc = 0;
1801
1802         rc = is_bnxt_in_error(bp);
1803         if (rc)
1804                 return rc;
1805
1806         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1807                 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1808                 return -ENOTSUP;
1809         }
1810
1811         if (!vnic) {
1812                 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1813                 return -EINVAL;
1814         }
1815
1816         /* Filter settings will get applied when port is started */
1817         if (!eth_dev->data->dev_started)
1818                 return 0;
1819
1820         rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1821
1822         return rc;
1823 }
1824
1825 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1826 {
1827         int rc = 0;
1828         struct bnxt *bp = eth_dev->data->dev_private;
1829         struct rte_eth_link new;
1830         int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1831                         BNXT_MIN_LINK_WAIT_CNT;
1832
1833         rc = is_bnxt_in_error(bp);
1834         if (rc)
1835                 return rc;
1836
1837         memset(&new, 0, sizeof(new));
1838
1839         if (bp->link_info == NULL)
1840                 goto out;
1841
1842         do {
1843                 /* Retrieve link info from hardware */
1844                 rc = bnxt_get_hwrm_link_config(bp, &new);
1845                 if (rc) {
1846                         new.link_speed = ETH_LINK_SPEED_100M;
1847                         new.link_duplex = ETH_LINK_FULL_DUPLEX;
1848                         PMD_DRV_LOG(ERR,
1849                                 "Failed to retrieve link rc = 0x%x!\n", rc);
1850                         goto out;
1851                 }
1852
1853                 if (!wait_to_complete || new.link_status)
1854                         break;
1855
1856                 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1857         } while (cnt--);
1858
1859         /* Only single function PF can bring phy down.
1860          * When port is stopped, report link down for VF/MH/NPAR functions.
1861          */
1862         if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1863                 memset(&new, 0, sizeof(new));
1864
1865 out:
1866         /* Timed out or success */
1867         if (new.link_status != eth_dev->data->dev_link.link_status ||
1868             new.link_speed != eth_dev->data->dev_link.link_speed) {
1869                 rte_eth_linkstatus_set(eth_dev, &new);
1870                 bnxt_print_link_info(eth_dev);
1871         }
1872
1873         return rc;
1874 }
1875
1876 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1877 {
1878         struct bnxt *bp = eth_dev->data->dev_private;
1879         struct bnxt_vnic_info *vnic;
1880         uint32_t old_flags;
1881         int rc;
1882
1883         rc = is_bnxt_in_error(bp);
1884         if (rc)
1885                 return rc;
1886
1887         /* Filter settings will get applied when port is started */
1888         if (!eth_dev->data->dev_started)
1889                 return 0;
1890
1891         if (bp->vnic_info == NULL)
1892                 return 0;
1893
1894         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1895
1896         old_flags = vnic->flags;
1897         vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1898         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1899         if (rc != 0)
1900                 vnic->flags = old_flags;
1901
1902         return rc;
1903 }
1904
1905 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1906 {
1907         struct bnxt *bp = eth_dev->data->dev_private;
1908         struct bnxt_vnic_info *vnic;
1909         uint32_t old_flags;
1910         int rc;
1911
1912         rc = is_bnxt_in_error(bp);
1913         if (rc)
1914                 return rc;
1915
1916         /* Filter settings will get applied when port is started */
1917         if (!eth_dev->data->dev_started)
1918                 return 0;
1919
1920         if (bp->vnic_info == NULL)
1921                 return 0;
1922
1923         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1924
1925         old_flags = vnic->flags;
1926         vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1927         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1928         if (rc != 0)
1929                 vnic->flags = old_flags;
1930
1931         return rc;
1932 }
1933
1934 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1935 {
1936         struct bnxt *bp = eth_dev->data->dev_private;
1937         struct bnxt_vnic_info *vnic;
1938         uint32_t old_flags;
1939         int rc;
1940
1941         rc = is_bnxt_in_error(bp);
1942         if (rc)
1943                 return rc;
1944
1945         /* Filter settings will get applied when port is started */
1946         if (!eth_dev->data->dev_started)
1947                 return 0;
1948
1949         if (bp->vnic_info == NULL)
1950                 return 0;
1951
1952         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1953
1954         old_flags = vnic->flags;
1955         vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1956         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1957         if (rc != 0)
1958                 vnic->flags = old_flags;
1959
1960         return rc;
1961 }
1962
1963 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1964 {
1965         struct bnxt *bp = eth_dev->data->dev_private;
1966         struct bnxt_vnic_info *vnic;
1967         uint32_t old_flags;
1968         int rc;
1969
1970         rc = is_bnxt_in_error(bp);
1971         if (rc)
1972                 return rc;
1973
1974         /* Filter settings will get applied when port is started */
1975         if (!eth_dev->data->dev_started)
1976                 return 0;
1977
1978         if (bp->vnic_info == NULL)
1979                 return 0;
1980
1981         vnic = BNXT_GET_DEFAULT_VNIC(bp);
1982
1983         old_flags = vnic->flags;
1984         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1985         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1986         if (rc != 0)
1987                 vnic->flags = old_flags;
1988
1989         return rc;
1990 }
1991
1992 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1993 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1994 {
1995         if (qid >= bp->rx_nr_rings)
1996                 return NULL;
1997
1998         return bp->eth_dev->data->rx_queues[qid];
1999 }
2000
2001 /* Return rxq corresponding to a given rss table ring/group ID. */
2002 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
2003 {
2004         struct bnxt_rx_queue *rxq;
2005         unsigned int i;
2006
2007         if (!BNXT_HAS_RING_GRPS(bp)) {
2008                 for (i = 0; i < bp->rx_nr_rings; i++) {
2009                         rxq = bp->eth_dev->data->rx_queues[i];
2010                         if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
2011                                 return rxq->index;
2012                 }
2013         } else {
2014                 for (i = 0; i < bp->rx_nr_rings; i++) {
2015                         if (bp->grp_info[i].fw_grp_id == fwr)
2016                                 return i;
2017                 }
2018         }
2019
2020         return INVALID_HW_RING_ID;
2021 }
2022
2023 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
2024                             struct rte_eth_rss_reta_entry64 *reta_conf,
2025                             uint16_t reta_size)
2026 {
2027         struct bnxt *bp = eth_dev->data->dev_private;
2028         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2029         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2030         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2031         uint16_t idx, sft;
2032         int i, rc;
2033
2034         rc = is_bnxt_in_error(bp);
2035         if (rc)
2036                 return rc;
2037
2038         if (!vnic->rss_table)
2039                 return -EINVAL;
2040
2041         if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
2042                 return -EINVAL;
2043
2044         if (reta_size != tbl_size) {
2045                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2046                         "(%d) must equal the size supported by the hardware "
2047                         "(%d)\n", reta_size, tbl_size);
2048                 return -EINVAL;
2049         }
2050
2051         for (i = 0; i < reta_size; i++) {
2052                 struct bnxt_rx_queue *rxq;
2053
2054                 idx = i / RTE_RETA_GROUP_SIZE;
2055                 sft = i % RTE_RETA_GROUP_SIZE;
2056
2057                 if (!(reta_conf[idx].mask & (1ULL << sft)))
2058                         continue;
2059
2060                 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
2061                 if (!rxq) {
2062                         PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
2063                         return -EINVAL;
2064                 }
2065
2066                 if (BNXT_CHIP_P5(bp)) {
2067                         vnic->rss_table[i * 2] =
2068                                 rxq->rx_ring->rx_ring_struct->fw_ring_id;
2069                         vnic->rss_table[i * 2 + 1] =
2070                                 rxq->cp_ring->cp_ring_struct->fw_ring_id;
2071                 } else {
2072                         vnic->rss_table[i] =
2073                             vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
2074                 }
2075         }
2076
2077         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2078         return rc;
2079 }
2080
2081 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
2082                               struct rte_eth_rss_reta_entry64 *reta_conf,
2083                               uint16_t reta_size)
2084 {
2085         struct bnxt *bp = eth_dev->data->dev_private;
2086         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2087         uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
2088         uint16_t idx, sft, i;
2089         int rc;
2090
2091         rc = is_bnxt_in_error(bp);
2092         if (rc)
2093                 return rc;
2094
2095         if (!vnic)
2096                 return -EINVAL;
2097         if (!vnic->rss_table)
2098                 return -EINVAL;
2099
2100         if (reta_size != tbl_size) {
2101                 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
2102                         "(%d) must equal the size supported by the hardware "
2103                         "(%d)\n", reta_size, tbl_size);
2104                 return -EINVAL;
2105         }
2106
2107         for (idx = 0, i = 0; i < reta_size; i++) {
2108                 idx = i / RTE_RETA_GROUP_SIZE;
2109                 sft = i % RTE_RETA_GROUP_SIZE;
2110
2111                 if (reta_conf[idx].mask & (1ULL << sft)) {
2112                         uint16_t qid;
2113
2114                         if (BNXT_CHIP_P5(bp))
2115                                 qid = bnxt_rss_to_qid(bp,
2116                                                       vnic->rss_table[i * 2]);
2117                         else
2118                                 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2119
2120                         if (qid == INVALID_HW_RING_ID) {
2121                                 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2122                                 return -EINVAL;
2123                         }
2124                         reta_conf[idx].reta[sft] = qid;
2125                 }
2126         }
2127
2128         return 0;
2129 }
2130
2131 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2132                                    struct rte_eth_rss_conf *rss_conf)
2133 {
2134         struct bnxt *bp = eth_dev->data->dev_private;
2135         struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2136         struct bnxt_vnic_info *vnic;
2137         int rc;
2138
2139         rc = is_bnxt_in_error(bp);
2140         if (rc)
2141                 return rc;
2142
2143         /*
2144          * If RSS enablement were different than dev_configure,
2145          * then return -EINVAL
2146          */
2147         if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
2148                 if (!rss_conf->rss_hf)
2149                         PMD_DRV_LOG(ERR, "Hash type NONE\n");
2150         } else {
2151                 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2152                         return -EINVAL;
2153         }
2154
2155         bp->flags |= BNXT_FLAG_UPDATE_HASH;
2156         memcpy(&eth_dev->data->dev_conf.rx_adv_conf.rss_conf,
2157                rss_conf,
2158                sizeof(*rss_conf));
2159
2160         /* Update the default RSS VNIC(s) */
2161         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2162         vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2163         vnic->hash_mode =
2164                 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2165                                             ETH_RSS_LEVEL(rss_conf->rss_hf));
2166
2167         /*
2168          * If hashkey is not specified, use the previously configured
2169          * hashkey
2170          */
2171         if (!rss_conf->rss_key)
2172                 goto rss_config;
2173
2174         if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2175                 PMD_DRV_LOG(ERR,
2176                             "Invalid hashkey length, should be %d bytes\n",
2177                             HW_HASH_KEY_SIZE);
2178                 return -EINVAL;
2179         }
2180         memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2181
2182 rss_config:
2183         rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2184         return rc;
2185 }
2186
2187 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2188                                      struct rte_eth_rss_conf *rss_conf)
2189 {
2190         struct bnxt *bp = eth_dev->data->dev_private;
2191         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2192         int len, rc;
2193         uint32_t hash_types;
2194
2195         rc = is_bnxt_in_error(bp);
2196         if (rc)
2197                 return rc;
2198
2199         /* RSS configuration is the same for all VNICs */
2200         if (vnic && vnic->rss_hash_key) {
2201                 if (rss_conf->rss_key) {
2202                         len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2203                               rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2204                         memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2205                 }
2206
2207                 hash_types = vnic->hash_type;
2208                 rss_conf->rss_hf = 0;
2209                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2210                         rss_conf->rss_hf |= ETH_RSS_IPV4;
2211                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2212                 }
2213                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2214                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2215                         hash_types &=
2216                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2217                 }
2218                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2219                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2220                         hash_types &=
2221                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2222                 }
2223                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2224                         rss_conf->rss_hf |= ETH_RSS_IPV6;
2225                         hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2226                 }
2227                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2228                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2229                         hash_types &=
2230                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2231                 }
2232                 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2233                         rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2234                         hash_types &=
2235                                 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2236                 }
2237
2238                 rss_conf->rss_hf |=
2239                         bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2240
2241                 if (hash_types) {
2242                         PMD_DRV_LOG(ERR,
2243                                 "Unknown RSS config from firmware (%08x), RSS disabled",
2244                                 vnic->hash_type);
2245                         return -ENOTSUP;
2246                 }
2247         } else {
2248                 rss_conf->rss_hf = 0;
2249         }
2250         return 0;
2251 }
2252
2253 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2254                                struct rte_eth_fc_conf *fc_conf)
2255 {
2256         struct bnxt *bp = dev->data->dev_private;
2257         struct rte_eth_link link_info;
2258         int rc;
2259
2260         rc = is_bnxt_in_error(bp);
2261         if (rc)
2262                 return rc;
2263
2264         rc = bnxt_get_hwrm_link_config(bp, &link_info);
2265         if (rc)
2266                 return rc;
2267
2268         memset(fc_conf, 0, sizeof(*fc_conf));
2269         if (bp->link_info->auto_pause)
2270                 fc_conf->autoneg = 1;
2271         switch (bp->link_info->pause) {
2272         case 0:
2273                 fc_conf->mode = RTE_FC_NONE;
2274                 break;
2275         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2276                 fc_conf->mode = RTE_FC_TX_PAUSE;
2277                 break;
2278         case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2279                 fc_conf->mode = RTE_FC_RX_PAUSE;
2280                 break;
2281         case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2282                         HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2283                 fc_conf->mode = RTE_FC_FULL;
2284                 break;
2285         }
2286         return 0;
2287 }
2288
2289 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2290                                struct rte_eth_fc_conf *fc_conf)
2291 {
2292         struct bnxt *bp = dev->data->dev_private;
2293         int rc;
2294
2295         rc = is_bnxt_in_error(bp);
2296         if (rc)
2297                 return rc;
2298
2299         if (!BNXT_SINGLE_PF(bp)) {
2300                 PMD_DRV_LOG(ERR,
2301                             "Flow Control Settings cannot be modified on VF or on shared PF\n");
2302                 return -ENOTSUP;
2303         }
2304
2305         switch (fc_conf->mode) {
2306         case RTE_FC_NONE:
2307                 bp->link_info->auto_pause = 0;
2308                 bp->link_info->force_pause = 0;
2309                 break;
2310         case RTE_FC_RX_PAUSE:
2311                 if (fc_conf->autoneg) {
2312                         bp->link_info->auto_pause =
2313                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2314                         bp->link_info->force_pause = 0;
2315                 } else {
2316                         bp->link_info->auto_pause = 0;
2317                         bp->link_info->force_pause =
2318                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2319                 }
2320                 break;
2321         case RTE_FC_TX_PAUSE:
2322                 if (fc_conf->autoneg) {
2323                         bp->link_info->auto_pause =
2324                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2325                         bp->link_info->force_pause = 0;
2326                 } else {
2327                         bp->link_info->auto_pause = 0;
2328                         bp->link_info->force_pause =
2329                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2330                 }
2331                 break;
2332         case RTE_FC_FULL:
2333                 if (fc_conf->autoneg) {
2334                         bp->link_info->auto_pause =
2335                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2336                                         HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2337                         bp->link_info->force_pause = 0;
2338                 } else {
2339                         bp->link_info->auto_pause = 0;
2340                         bp->link_info->force_pause =
2341                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2342                                         HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2343                 }
2344                 break;
2345         }
2346         return bnxt_set_hwrm_link_config(bp, true);
2347 }
2348
2349 /* Add UDP tunneling port */
2350 static int
2351 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2352                          struct rte_eth_udp_tunnel *udp_tunnel)
2353 {
2354         struct bnxt *bp = eth_dev->data->dev_private;
2355         uint16_t tunnel_type = 0;
2356         int rc = 0;
2357
2358         rc = is_bnxt_in_error(bp);
2359         if (rc)
2360                 return rc;
2361
2362         switch (udp_tunnel->prot_type) {
2363         case RTE_TUNNEL_TYPE_VXLAN:
2364                 if (bp->vxlan_port_cnt) {
2365                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2366                                 udp_tunnel->udp_port);
2367                         if (bp->vxlan_port != udp_tunnel->udp_port) {
2368                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2369                                 return -ENOSPC;
2370                         }
2371                         bp->vxlan_port_cnt++;
2372                         return 0;
2373                 }
2374                 tunnel_type =
2375                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2376                 break;
2377         case RTE_TUNNEL_TYPE_GENEVE:
2378                 if (bp->geneve_port_cnt) {
2379                         PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2380                                 udp_tunnel->udp_port);
2381                         if (bp->geneve_port != udp_tunnel->udp_port) {
2382                                 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2383                                 return -ENOSPC;
2384                         }
2385                         bp->geneve_port_cnt++;
2386                         return 0;
2387                 }
2388                 tunnel_type =
2389                         HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2390                 break;
2391         default:
2392                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2393                 return -ENOTSUP;
2394         }
2395         rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2396                                              tunnel_type);
2397
2398         if (rc != 0)
2399                 return rc;
2400
2401         if (tunnel_type ==
2402             HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN)
2403                 bp->vxlan_port_cnt++;
2404
2405         if (tunnel_type ==
2406             HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE)
2407                 bp->geneve_port_cnt++;
2408
2409         return rc;
2410 }
2411
2412 static int
2413 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2414                          struct rte_eth_udp_tunnel *udp_tunnel)
2415 {
2416         struct bnxt *bp = eth_dev->data->dev_private;
2417         uint16_t tunnel_type = 0;
2418         uint16_t port = 0;
2419         int rc = 0;
2420
2421         rc = is_bnxt_in_error(bp);
2422         if (rc)
2423                 return rc;
2424
2425         switch (udp_tunnel->prot_type) {
2426         case RTE_TUNNEL_TYPE_VXLAN:
2427                 if (!bp->vxlan_port_cnt) {
2428                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2429                         return -EINVAL;
2430                 }
2431                 if (bp->vxlan_port != udp_tunnel->udp_port) {
2432                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2433                                 udp_tunnel->udp_port, bp->vxlan_port);
2434                         return -EINVAL;
2435                 }
2436                 if (--bp->vxlan_port_cnt)
2437                         return 0;
2438
2439                 tunnel_type =
2440                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2441                 port = bp->vxlan_fw_dst_port_id;
2442                 break;
2443         case RTE_TUNNEL_TYPE_GENEVE:
2444                 if (!bp->geneve_port_cnt) {
2445                         PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2446                         return -EINVAL;
2447                 }
2448                 if (bp->geneve_port != udp_tunnel->udp_port) {
2449                         PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2450                                 udp_tunnel->udp_port, bp->geneve_port);
2451                         return -EINVAL;
2452                 }
2453                 if (--bp->geneve_port_cnt)
2454                         return 0;
2455
2456                 tunnel_type =
2457                         HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2458                 port = bp->geneve_fw_dst_port_id;
2459                 break;
2460         default:
2461                 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2462                 return -ENOTSUP;
2463         }
2464
2465         rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2466         return rc;
2467 }
2468
2469 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2470 {
2471         struct bnxt_filter_info *filter;
2472         struct bnxt_vnic_info *vnic;
2473         int rc = 0;
2474         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2475
2476         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2477         filter = STAILQ_FIRST(&vnic->filter);
2478         while (filter) {
2479                 /* Search for this matching MAC+VLAN filter */
2480                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2481                         /* Delete the filter */
2482                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2483                         if (rc)
2484                                 return rc;
2485                         STAILQ_REMOVE(&vnic->filter, filter,
2486                                       bnxt_filter_info, next);
2487                         bnxt_free_filter(bp, filter);
2488                         PMD_DRV_LOG(INFO,
2489                                     "Deleted vlan filter for %d\n",
2490                                     vlan_id);
2491                         return 0;
2492                 }
2493                 filter = STAILQ_NEXT(filter, next);
2494         }
2495         return -ENOENT;
2496 }
2497
2498 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2499 {
2500         struct bnxt_filter_info *filter;
2501         struct bnxt_vnic_info *vnic;
2502         int rc = 0;
2503         uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2504                 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2505         uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2506
2507         /* Implementation notes on the use of VNIC in this command:
2508          *
2509          * By default, these filters belong to default vnic for the function.
2510          * Once these filters are set up, only destination VNIC can be modified.
2511          * If the destination VNIC is not specified in this command,
2512          * then the HWRM shall only create an l2 context id.
2513          */
2514
2515         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2516         filter = STAILQ_FIRST(&vnic->filter);
2517         /* Check if the VLAN has already been added */
2518         while (filter) {
2519                 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2520                         return -EEXIST;
2521
2522                 filter = STAILQ_NEXT(filter, next);
2523         }
2524
2525         /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2526          * command to create MAC+VLAN filter with the right flags, enables set.
2527          */
2528         filter = bnxt_alloc_filter(bp);
2529         if (!filter) {
2530                 PMD_DRV_LOG(ERR,
2531                             "MAC/VLAN filter alloc failed\n");
2532                 return -ENOMEM;
2533         }
2534         /* MAC + VLAN ID filter */
2535         /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2536          * untagged packets are received
2537          *
2538          * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2539          * packets and only the programmed vlan's packets are received
2540          */
2541         filter->l2_ivlan = vlan_id;
2542         filter->l2_ivlan_mask = 0x0FFF;
2543         filter->enables |= en;
2544         filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2545
2546         rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2547         if (rc) {
2548                 /* Free the newly allocated filter as we were
2549                  * not able to create the filter in hardware.
2550                  */
2551                 bnxt_free_filter(bp, filter);
2552                 return rc;
2553         }
2554
2555         filter->mac_index = 0;
2556         /* Add this new filter to the list */
2557         if (vlan_id == 0)
2558                 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2559         else
2560                 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2561
2562         PMD_DRV_LOG(INFO,
2563                     "Added Vlan filter for %d\n", vlan_id);
2564         return rc;
2565 }
2566
2567 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2568                 uint16_t vlan_id, int on)
2569 {
2570         struct bnxt *bp = eth_dev->data->dev_private;
2571         int rc;
2572
2573         rc = is_bnxt_in_error(bp);
2574         if (rc)
2575                 return rc;
2576
2577         if (!eth_dev->data->dev_started) {
2578                 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2579                 return -EINVAL;
2580         }
2581
2582         /* These operations apply to ALL existing MAC/VLAN filters */
2583         if (on)
2584                 return bnxt_add_vlan_filter(bp, vlan_id);
2585         else
2586                 return bnxt_del_vlan_filter(bp, vlan_id);
2587 }
2588
2589 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2590                                     struct bnxt_vnic_info *vnic)
2591 {
2592         struct bnxt_filter_info *filter;
2593         int rc;
2594
2595         filter = STAILQ_FIRST(&vnic->filter);
2596         while (filter) {
2597                 if (filter->mac_index == 0 &&
2598                     !memcmp(filter->l2_addr, bp->mac_addr,
2599                             RTE_ETHER_ADDR_LEN)) {
2600                         rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2601                         if (!rc) {
2602                                 STAILQ_REMOVE(&vnic->filter, filter,
2603                                               bnxt_filter_info, next);
2604                                 bnxt_free_filter(bp, filter);
2605                         }
2606                         return rc;
2607                 }
2608                 filter = STAILQ_NEXT(filter, next);
2609         }
2610         return 0;
2611 }
2612
2613 static int
2614 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2615 {
2616         struct bnxt_vnic_info *vnic;
2617         unsigned int i;
2618         int rc;
2619
2620         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2621         if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2622                 /* Remove any VLAN filters programmed */
2623                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2624                         bnxt_del_vlan_filter(bp, i);
2625
2626                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2627                 if (rc)
2628                         return rc;
2629         } else {
2630                 /* Default filter will allow packets that match the
2631                  * dest mac. So, it has to be deleted, otherwise, we
2632                  * will endup receiving vlan packets for which the
2633                  * filter is not programmed, when hw-vlan-filter
2634                  * configuration is ON
2635                  */
2636                 bnxt_del_dflt_mac_filter(bp, vnic);
2637                 /* This filter will allow only untagged packets */
2638                 bnxt_add_vlan_filter(bp, 0);
2639         }
2640         PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2641                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2642
2643         return 0;
2644 }
2645
2646 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2647 {
2648         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2649         unsigned int i;
2650         int rc;
2651
2652         /* Destroy vnic filters and vnic */
2653         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2654             DEV_RX_OFFLOAD_VLAN_FILTER) {
2655                 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2656                         bnxt_del_vlan_filter(bp, i);
2657         }
2658         bnxt_del_dflt_mac_filter(bp, vnic);
2659
2660         rc = bnxt_hwrm_vnic_ctx_free(bp, vnic);
2661         if (rc)
2662                 return rc;
2663
2664         rc = bnxt_hwrm_vnic_free(bp, vnic);
2665         if (rc)
2666                 return rc;
2667
2668         rte_free(vnic->fw_grp_ids);
2669         vnic->fw_grp_ids = NULL;
2670
2671         vnic->rx_queue_cnt = 0;
2672
2673         return 0;
2674 }
2675
2676 static int
2677 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2678 {
2679         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2680         int rc;
2681
2682         /* Destroy, recreate and reconfigure the default vnic */
2683         rc = bnxt_free_one_vnic(bp, 0);
2684         if (rc)
2685                 return rc;
2686
2687         /* default vnic 0 */
2688         rc = bnxt_setup_one_vnic(bp, 0);
2689         if (rc)
2690                 return rc;
2691
2692         if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2693             DEV_RX_OFFLOAD_VLAN_FILTER) {
2694                 rc = bnxt_add_vlan_filter(bp, 0);
2695                 if (rc)
2696                         return rc;
2697                 rc = bnxt_restore_vlan_filters(bp);
2698                 if (rc)
2699                         return rc;
2700         } else {
2701                 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2702                 if (rc)
2703                         return rc;
2704         }
2705
2706         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2707         if (rc)
2708                 return rc;
2709
2710         PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2711                     !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2712
2713         return rc;
2714 }
2715
2716 static int
2717 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2718 {
2719         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2720         struct bnxt *bp = dev->data->dev_private;
2721         int rc;
2722
2723         rc = is_bnxt_in_error(bp);
2724         if (rc)
2725                 return rc;
2726
2727         /* Filter settings will get applied when port is started */
2728         if (!dev->data->dev_started)
2729                 return 0;
2730
2731         if (mask & ETH_VLAN_FILTER_MASK) {
2732                 /* Enable or disable VLAN filtering */
2733                 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2734                 if (rc)
2735                         return rc;
2736         }
2737
2738         if (mask & ETH_VLAN_STRIP_MASK) {
2739                 /* Enable or disable VLAN stripping */
2740                 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2741                 if (rc)
2742                         return rc;
2743         }
2744
2745         if (mask & ETH_VLAN_EXTEND_MASK) {
2746                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2747                         PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2748                 else
2749                         PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2750         }
2751
2752         return 0;
2753 }
2754
2755 static int
2756 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2757                       uint16_t tpid)
2758 {
2759         struct bnxt *bp = dev->data->dev_private;
2760         int qinq = dev->data->dev_conf.rxmode.offloads &
2761                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2762
2763         if (vlan_type != ETH_VLAN_TYPE_INNER &&
2764             vlan_type != ETH_VLAN_TYPE_OUTER) {
2765                 PMD_DRV_LOG(ERR,
2766                             "Unsupported vlan type.");
2767                 return -EINVAL;
2768         }
2769         if (!qinq) {
2770                 PMD_DRV_LOG(ERR,
2771                             "QinQ not enabled. Needs to be ON as we can "
2772                             "accelerate only outer vlan\n");
2773                 return -EINVAL;
2774         }
2775
2776         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2777                 switch (tpid) {
2778                 case RTE_ETHER_TYPE_QINQ:
2779                         bp->outer_tpid_bd =
2780                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2781                                 break;
2782                 case RTE_ETHER_TYPE_VLAN:
2783                         bp->outer_tpid_bd =
2784                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2785                                 break;
2786                 case RTE_ETHER_TYPE_QINQ1:
2787                         bp->outer_tpid_bd =
2788                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2789                                 break;
2790                 case RTE_ETHER_TYPE_QINQ2:
2791                         bp->outer_tpid_bd =
2792                                 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2793                                 break;
2794                 case RTE_ETHER_TYPE_QINQ3:
2795                         bp->outer_tpid_bd =
2796                                  TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2797                                 break;
2798                 default:
2799                         PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2800                         return -EINVAL;
2801                 }
2802                 bp->outer_tpid_bd |= tpid;
2803                 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2804         } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2805                 PMD_DRV_LOG(ERR,
2806                             "Can accelerate only outer vlan in QinQ\n");
2807                 return -EINVAL;
2808         }
2809
2810         return 0;
2811 }
2812
2813 static int
2814 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2815                              struct rte_ether_addr *addr)
2816 {
2817         struct bnxt *bp = dev->data->dev_private;
2818         /* Default Filter is tied to VNIC 0 */
2819         struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2820         int rc;
2821
2822         rc = is_bnxt_in_error(bp);
2823         if (rc)
2824                 return rc;
2825
2826         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2827                 return -EPERM;
2828
2829         if (rte_is_zero_ether_addr(addr))
2830                 return -EINVAL;
2831
2832         /* Filter settings will get applied when port is started */
2833         if (!dev->data->dev_started)
2834                 return 0;
2835
2836         /* Check if the requested MAC is already added */
2837         if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2838                 return 0;
2839
2840         /* Destroy filter and re-create it */
2841         bnxt_del_dflt_mac_filter(bp, vnic);
2842
2843         memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2844         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2845                 /* This filter will allow only untagged packets */
2846                 rc = bnxt_add_vlan_filter(bp, 0);
2847         } else {
2848                 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2849         }
2850
2851         PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2852         return rc;
2853 }
2854
2855 static int
2856 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2857                           struct rte_ether_addr *mc_addr_set,
2858                           uint32_t nb_mc_addr)
2859 {
2860         struct bnxt *bp = eth_dev->data->dev_private;
2861         char *mc_addr_list = (char *)mc_addr_set;
2862         struct bnxt_vnic_info *vnic;
2863         uint32_t off = 0, i = 0;
2864         int rc;
2865
2866         rc = is_bnxt_in_error(bp);
2867         if (rc)
2868                 return rc;
2869
2870         vnic = BNXT_GET_DEFAULT_VNIC(bp);
2871
2872         if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2873                 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2874                 goto allmulti;
2875         }
2876
2877         /* TODO Check for Duplicate mcast addresses */
2878         vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2879         for (i = 0; i < nb_mc_addr; i++) {
2880                 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2881                         RTE_ETHER_ADDR_LEN);
2882                 off += RTE_ETHER_ADDR_LEN;
2883         }
2884
2885         vnic->mc_addr_cnt = i;
2886         if (vnic->mc_addr_cnt)
2887                 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2888         else
2889                 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2890
2891 allmulti:
2892         return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2893 }
2894
2895 static int
2896 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2897 {
2898         struct bnxt *bp = dev->data->dev_private;
2899         uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2900         uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2901         uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2902         uint8_t fw_rsvd = bp->fw_ver & 0xff;
2903         int ret;
2904
2905         ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2906                         fw_major, fw_minor, fw_updt, fw_rsvd);
2907         if (ret < 0)
2908                 return -EINVAL;
2909
2910         ret += 1; /* add the size of '\0' */
2911         if (fw_size < (size_t)ret)
2912                 return ret;
2913         else
2914                 return 0;
2915 }
2916
2917 static void
2918 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2919         struct rte_eth_rxq_info *qinfo)
2920 {
2921         struct bnxt *bp = dev->data->dev_private;
2922         struct bnxt_rx_queue *rxq;
2923
2924         if (is_bnxt_in_error(bp))
2925                 return;
2926
2927         rxq = dev->data->rx_queues[queue_id];
2928
2929         qinfo->mp = rxq->mb_pool;
2930         qinfo->scattered_rx = dev->data->scattered_rx;
2931         qinfo->nb_desc = rxq->nb_rx_desc;
2932
2933         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2934         qinfo->conf.rx_drop_en = rxq->drop_en;
2935         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2936         qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2937 }
2938
2939 static void
2940 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2941         struct rte_eth_txq_info *qinfo)
2942 {
2943         struct bnxt *bp = dev->data->dev_private;
2944         struct bnxt_tx_queue *txq;
2945
2946         if (is_bnxt_in_error(bp))
2947                 return;
2948
2949         txq = dev->data->tx_queues[queue_id];
2950
2951         qinfo->nb_desc = txq->nb_tx_desc;
2952
2953         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2954         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2955         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2956
2957         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2958         qinfo->conf.tx_rs_thresh = 0;
2959         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2960         qinfo->conf.offloads = txq->offloads;
2961 }
2962
2963 static const struct {
2964         eth_rx_burst_t pkt_burst;
2965         const char *info;
2966 } bnxt_rx_burst_info[] = {
2967         {bnxt_recv_pkts,                "Scalar"},
2968 #if defined(RTE_ARCH_X86)
2969         {bnxt_recv_pkts_vec,            "Vector SSE"},
2970 #endif
2971 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
2972         {bnxt_recv_pkts_vec_avx2,       "Vector AVX2"},
2973 #endif
2974 #if defined(RTE_ARCH_ARM64)
2975         {bnxt_recv_pkts_vec,            "Vector Neon"},
2976 #endif
2977 };
2978
2979 static int
2980 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2981                        struct rte_eth_burst_mode *mode)
2982 {
2983         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2984         size_t i;
2985
2986         for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2987                 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2988                         snprintf(mode->info, sizeof(mode->info), "%s",
2989                                  bnxt_rx_burst_info[i].info);
2990                         return 0;
2991                 }
2992         }
2993
2994         return -EINVAL;
2995 }
2996
2997 static const struct {
2998         eth_tx_burst_t pkt_burst;
2999         const char *info;
3000 } bnxt_tx_burst_info[] = {
3001         {bnxt_xmit_pkts,                "Scalar"},
3002 #if defined(RTE_ARCH_X86)
3003         {bnxt_xmit_pkts_vec,            "Vector SSE"},
3004 #endif
3005 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT)
3006         {bnxt_xmit_pkts_vec_avx2,       "Vector AVX2"},
3007 #endif
3008 #if defined(RTE_ARCH_ARM64)
3009         {bnxt_xmit_pkts_vec,            "Vector Neon"},
3010 #endif
3011 };
3012
3013 static int
3014 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3015                        struct rte_eth_burst_mode *mode)
3016 {
3017         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3018         size_t i;
3019
3020         for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
3021                 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
3022                         snprintf(mode->info, sizeof(mode->info), "%s",
3023                                  bnxt_tx_burst_info[i].info);
3024                         return 0;
3025                 }
3026         }
3027
3028         return -EINVAL;
3029 }
3030
3031 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
3032 {
3033         struct bnxt *bp = eth_dev->data->dev_private;
3034         uint32_t new_pkt_size;
3035         uint32_t rc = 0;
3036         uint32_t i;
3037
3038         rc = is_bnxt_in_error(bp);
3039         if (rc)
3040                 return rc;
3041
3042         /* Exit if receive queues are not configured yet */
3043         if (!eth_dev->data->nb_rx_queues)
3044                 return rc;
3045
3046         new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
3047                        VLAN_TAG_SIZE * BNXT_NUM_VLANS;
3048
3049         /*
3050          * Disallow any MTU change that would require scattered receive support
3051          * if it is not already enabled.
3052          */
3053         if (eth_dev->data->dev_started &&
3054             !eth_dev->data->scattered_rx &&
3055             (new_pkt_size >
3056              eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3057                 PMD_DRV_LOG(ERR,
3058                             "MTU change would require scattered rx support. ");
3059                 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
3060                 return -EINVAL;
3061         }
3062
3063         if (new_mtu > RTE_ETHER_MTU) {
3064                 bp->flags |= BNXT_FLAG_JUMBO;
3065                 bp->eth_dev->data->dev_conf.rxmode.offloads |=
3066                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3067         } else {
3068                 bp->eth_dev->data->dev_conf.rxmode.offloads &=
3069                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3070                 bp->flags &= ~BNXT_FLAG_JUMBO;
3071         }
3072
3073         /* Is there a change in mtu setting? */
3074         if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
3075                 return rc;
3076
3077         for (i = 0; i < bp->nr_vnics; i++) {
3078                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3079                 uint16_t size = 0;
3080
3081                 vnic->mru = BNXT_VNIC_MRU(new_mtu);
3082                 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
3083                 if (rc)
3084                         break;
3085
3086                 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
3087                 size -= RTE_PKTMBUF_HEADROOM;
3088
3089                 if (size < new_mtu) {
3090                         rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
3091                         if (rc)
3092                                 return rc;
3093                 }
3094         }
3095
3096         if (!rc)
3097                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
3098
3099         if (bnxt_hwrm_config_host_mtu(bp))
3100                 PMD_DRV_LOG(WARNING, "Failed to configure host MTU\n");
3101
3102         PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
3103
3104         return rc;
3105 }
3106
3107 static int
3108 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
3109 {
3110         struct bnxt *bp = dev->data->dev_private;
3111         uint16_t vlan = bp->vlan;
3112         int rc;
3113
3114         rc = is_bnxt_in_error(bp);
3115         if (rc)
3116                 return rc;
3117
3118         if (!BNXT_SINGLE_PF(bp)) {
3119                 PMD_DRV_LOG(ERR, "PVID cannot be modified on VF or on shared PF\n");
3120                 return -ENOTSUP;
3121         }
3122         bp->vlan = on ? pvid : 0;
3123
3124         rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
3125         if (rc)
3126                 bp->vlan = vlan;
3127         return rc;
3128 }
3129
3130 static int
3131 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
3132 {
3133         struct bnxt *bp = dev->data->dev_private;
3134         int rc;
3135
3136         rc = is_bnxt_in_error(bp);
3137         if (rc)
3138                 return rc;
3139
3140         return bnxt_hwrm_port_led_cfg(bp, true);
3141 }
3142
3143 static int
3144 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3145 {
3146         struct bnxt *bp = dev->data->dev_private;
3147         int rc;
3148
3149         rc = is_bnxt_in_error(bp);
3150         if (rc)
3151                 return rc;
3152
3153         return bnxt_hwrm_port_led_cfg(bp, false);
3154 }
3155
3156 static uint32_t
3157 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3158 {
3159         struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3160         struct bnxt_cp_ring_info *cpr;
3161         uint32_t desc = 0, raw_cons, cp_ring_size;
3162         struct bnxt_rx_queue *rxq;
3163         struct rx_pkt_cmpl *rxcmp;
3164         int rc;
3165
3166         rc = is_bnxt_in_error(bp);
3167         if (rc)
3168                 return rc;
3169
3170         rxq = dev->data->rx_queues[rx_queue_id];
3171         cpr = rxq->cp_ring;
3172         raw_cons = cpr->cp_raw_cons;
3173         cp_ring_size = cpr->cp_ring_struct->ring_size;
3174
3175         while (1) {
3176                 uint32_t agg_cnt, cons, cmpl_type;
3177
3178                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3179                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3180
3181                 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3182                         break;
3183
3184                 cmpl_type = CMP_TYPE(rxcmp);
3185
3186                 switch (cmpl_type) {
3187                 case CMPL_BASE_TYPE_RX_L2:
3188                 case CMPL_BASE_TYPE_RX_L2_V2:
3189                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3190                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3191                         desc++;
3192                         break;
3193
3194                 case CMPL_BASE_TYPE_RX_TPA_END:
3195                         if (BNXT_CHIP_P5(rxq->bp)) {
3196                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3197
3198                                 p5_tpa_end = (void *)rxcmp;
3199                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3200                         } else {
3201                                 struct rx_tpa_end_cmpl *tpa_end;
3202
3203                                 tpa_end = (void *)rxcmp;
3204                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3205                         }
3206
3207                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3208                         desc++;
3209                         break;
3210
3211                 default:
3212                         raw_cons += CMP_LEN(cmpl_type);
3213                 }
3214         }
3215
3216         return desc;
3217 }
3218
3219 static int
3220 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3221 {
3222         struct bnxt_rx_queue *rxq = rx_queue;
3223         struct bnxt_cp_ring_info *cpr;
3224         struct bnxt_rx_ring_info *rxr;
3225         uint32_t desc, raw_cons, cp_ring_size;
3226         struct bnxt *bp = rxq->bp;
3227         struct rx_pkt_cmpl *rxcmp;
3228         int rc;
3229
3230         rc = is_bnxt_in_error(bp);
3231         if (rc)
3232                 return rc;
3233
3234         if (offset >= rxq->nb_rx_desc)
3235                 return -EINVAL;
3236
3237         rxr = rxq->rx_ring;
3238         cpr = rxq->cp_ring;
3239         cp_ring_size = cpr->cp_ring_struct->ring_size;
3240
3241         /*
3242          * For the vector receive case, the completion at the requested
3243          * offset can be indexed directly.
3244          */
3245 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3246         if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3247                 struct rx_pkt_cmpl *rxcmp;
3248                 uint32_t cons;
3249
3250                 /* Check status of completion descriptor. */
3251                 raw_cons = cpr->cp_raw_cons +
3252                            offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3253                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3254                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3255
3256                 if (bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3257                         return RTE_ETH_RX_DESC_DONE;
3258
3259                 /* Check whether rx desc has an mbuf attached. */
3260                 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3261                 if (cons >= rxq->rxrearm_start &&
3262                     cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3263                         return RTE_ETH_RX_DESC_UNAVAIL;
3264                 }
3265
3266                 return RTE_ETH_RX_DESC_AVAIL;
3267         }
3268 #endif
3269
3270         /*
3271          * For the non-vector receive case, scan the completion ring to
3272          * locate the completion descriptor for the requested offset.
3273          */
3274         raw_cons = cpr->cp_raw_cons;
3275         desc = 0;
3276         while (1) {
3277                 uint32_t agg_cnt, cons, cmpl_type;
3278
3279                 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3280                 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3281
3282                 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size))
3283                         break;
3284
3285                 cmpl_type = CMP_TYPE(rxcmp);
3286
3287                 switch (cmpl_type) {
3288                 case CMPL_BASE_TYPE_RX_L2:
3289                 case CMPL_BASE_TYPE_RX_L2_V2:
3290                         if (desc == offset) {
3291                                 cons = rxcmp->opaque;
3292                                 if (rxr->rx_buf_ring[cons])
3293                                         return RTE_ETH_RX_DESC_DONE;
3294                                 else
3295                                         return RTE_ETH_RX_DESC_UNAVAIL;
3296                         }
3297                         agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3298                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3299                         desc++;
3300                         break;
3301
3302                 case CMPL_BASE_TYPE_RX_TPA_END:
3303                         if (desc == offset)
3304                                 return RTE_ETH_RX_DESC_DONE;
3305
3306                         if (BNXT_CHIP_P5(rxq->bp)) {
3307                                 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3308
3309                                 p5_tpa_end = (void *)rxcmp;
3310                                 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3311                         } else {
3312                                 struct rx_tpa_end_cmpl *tpa_end;
3313
3314                                 tpa_end = (void *)rxcmp;
3315                                 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3316                         }
3317
3318                         raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3319                         desc++;
3320                         break;
3321
3322                 default:
3323                         raw_cons += CMP_LEN(cmpl_type);
3324                 }
3325         }
3326
3327         return RTE_ETH_RX_DESC_AVAIL;
3328 }
3329
3330 static int
3331 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3332 {
3333         struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3334         struct bnxt_cp_ring_info *cpr = txq->cp_ring;
3335         uint32_t ring_mask, raw_cons, nb_tx_pkts = 0;
3336         struct cmpl_base *cp_desc_ring;
3337         int rc;
3338
3339         rc = is_bnxt_in_error(txq->bp);
3340         if (rc)
3341                 return rc;
3342
3343         if (offset >= txq->nb_tx_desc)
3344                 return -EINVAL;
3345
3346         /* Return "desc done" if descriptor is available for use. */
3347         if (bnxt_tx_bds_in_hw(txq) <= offset)
3348                 return RTE_ETH_TX_DESC_DONE;
3349
3350         raw_cons = cpr->cp_raw_cons;
3351         cp_desc_ring = cpr->cp_desc_ring;
3352         ring_mask = cpr->cp_ring_struct->ring_mask;
3353
3354         /* Check to see if hw has posted a completion for the descriptor. */
3355         while (1) {
3356                 struct tx_cmpl *txcmp;
3357                 uint32_t cons;
3358
3359                 cons = RING_CMPL(ring_mask, raw_cons);
3360                 txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
3361
3362                 if (!bnxt_cpr_cmp_valid(txcmp, raw_cons, ring_mask + 1))
3363                         break;
3364
3365                 if (CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2)
3366                         nb_tx_pkts += rte_le_to_cpu_32(txcmp->opaque);
3367
3368                 if (nb_tx_pkts > offset)
3369                         return RTE_ETH_TX_DESC_DONE;
3370
3371                 raw_cons = NEXT_RAW_CMP(raw_cons);
3372         }
3373
3374         /* Descriptor is pending transmit, not yet completed by hardware. */
3375         return RTE_ETH_TX_DESC_FULL;
3376 }
3377
3378 int
3379 bnxt_flow_ops_get_op(struct rte_eth_dev *dev,
3380                      const struct rte_flow_ops **ops)
3381 {
3382         struct bnxt *bp = dev->data->dev_private;
3383         int ret = 0;
3384
3385         if (!bp)
3386                 return -EIO;
3387
3388         if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3389                 struct bnxt_representor *vfr = dev->data->dev_private;
3390                 bp = vfr->parent_dev->data->dev_private;
3391                 /* parent is deleted while children are still valid */
3392                 if (!bp) {
3393                         PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n",
3394                                     dev->data->port_id);
3395                         return -EIO;
3396                 }
3397         }
3398
3399         ret = is_bnxt_in_error(bp);
3400         if (ret)
3401                 return ret;
3402
3403         /* PMD supports thread-safe flow operations.  rte_flow API
3404          * functions can avoid mutex for multi-thread safety.
3405          */
3406         dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3407
3408         if (BNXT_TRUFLOW_EN(bp))
3409                 *ops = &bnxt_ulp_rte_flow_ops;
3410         else
3411                 *ops = &bnxt_flow_ops;
3412
3413         return ret;
3414 }
3415
3416 static const uint32_t *
3417 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3418 {
3419         static const uint32_t ptypes[] = {
3420                 RTE_PTYPE_L2_ETHER_VLAN,
3421                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3422                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3423                 RTE_PTYPE_L4_ICMP,
3424                 RTE_PTYPE_L4_TCP,
3425                 RTE_PTYPE_L4_UDP,
3426                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3427                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3428                 RTE_PTYPE_INNER_L4_ICMP,
3429                 RTE_PTYPE_INNER_L4_TCP,
3430                 RTE_PTYPE_INNER_L4_UDP,
3431                 RTE_PTYPE_UNKNOWN
3432         };
3433
3434         if (!dev->rx_pkt_burst)
3435                 return NULL;
3436
3437         return ptypes;
3438 }
3439
3440 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3441                          int reg_win)
3442 {
3443         uint32_t reg_base = *reg_arr & 0xfffff000;
3444         uint32_t win_off;
3445         int i;
3446
3447         for (i = 0; i < count; i++) {
3448                 if ((reg_arr[i] & 0xfffff000) != reg_base)
3449                         return -ERANGE;
3450         }
3451         win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3452         rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3453         return 0;
3454 }
3455
3456 static int bnxt_map_ptp_regs(struct bnxt *bp)
3457 {
3458         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3459         uint32_t *reg_arr;
3460         int rc, i;
3461
3462         reg_arr = ptp->rx_regs;
3463         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3464         if (rc)
3465                 return rc;
3466
3467         reg_arr = ptp->tx_regs;
3468         rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3469         if (rc)
3470                 return rc;
3471
3472         for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3473                 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3474
3475         for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3476                 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3477
3478         return 0;
3479 }
3480
3481 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3482 {
3483         rte_write32(0, (uint8_t *)bp->bar0 +
3484                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3485         rte_write32(0, (uint8_t *)bp->bar0 +
3486                          BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3487 }
3488
3489 static uint64_t bnxt_cc_read(struct bnxt *bp)
3490 {
3491         uint64_t ns;
3492
3493         ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3494                               BNXT_GRCPF_REG_SYNC_TIME));
3495         ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3496                                           BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3497         return ns;
3498 }
3499
3500 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3501 {
3502         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3503         uint32_t fifo;
3504
3505         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3506                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3507         if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3508                 return -EAGAIN;
3509
3510         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3511                                 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3512         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3513                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3514         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3515                                 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3516         rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]);
3517
3518         return 0;
3519 }
3520
3521 static int bnxt_clr_rx_ts(struct bnxt *bp, uint64_t *last_ts)
3522 {
3523         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3524         struct bnxt_pf_info *pf = bp->pf;
3525         uint16_t port_id;
3526         int i = 0;
3527         uint32_t fifo;
3528
3529         if (!ptp || (bp->flags & BNXT_FLAG_CHIP_P5))
3530                 return -EINVAL;
3531
3532         port_id = pf->port_id;
3533         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3534                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3535         while ((fifo & BNXT_PTP_RX_FIFO_PENDING) && (i < BNXT_PTP_RX_PND_CNT)) {
3536                 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3537                             ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3538                 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3539                                         ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3540                 *last_ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3541                                         ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3542                 *last_ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3543                                         ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3544                 i++;
3545         }
3546
3547         if (i >= BNXT_PTP_RX_PND_CNT)
3548                 return -EBUSY;
3549
3550         return 0;
3551 }
3552
3553 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3554 {
3555         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3556         struct bnxt_pf_info *pf = bp->pf;
3557         uint16_t port_id;
3558         uint32_t fifo;
3559
3560         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3561                                 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3562         if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3563                 return -EAGAIN;
3564
3565         port_id = pf->port_id;
3566         rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3567                ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3568
3569         fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3570                                    ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3571         if (fifo & BNXT_PTP_RX_FIFO_PENDING)
3572                 return bnxt_clr_rx_ts(bp, ts);
3573
3574         *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3575                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3576         *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3577                                 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3578
3579         return 0;
3580 }
3581
3582 static int
3583 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3584 {
3585         uint64_t ns;
3586         struct bnxt *bp = dev->data->dev_private;
3587         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3588
3589         if (!ptp)
3590                 return -ENOTSUP;
3591
3592         ns = rte_timespec_to_ns(ts);
3593         /* Set the timecounters to a new value. */
3594         ptp->tc.nsec = ns;
3595         ptp->tx_tstamp_tc.nsec = ns;
3596         ptp->rx_tstamp_tc.nsec = ns;
3597
3598         return 0;
3599 }
3600
3601 static int
3602 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3603 {
3604         struct bnxt *bp = dev->data->dev_private;
3605         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3606         uint64_t ns, systime_cycles = 0;
3607         int rc = 0;
3608
3609         if (!ptp)
3610                 return -ENOTSUP;
3611
3612         if (BNXT_CHIP_P5(bp))
3613                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3614                                              &systime_cycles);
3615         else
3616                 systime_cycles = bnxt_cc_read(bp);
3617
3618         ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3619         *ts = rte_ns_to_timespec(ns);
3620
3621         return rc;
3622 }
3623 static int
3624 bnxt_timesync_enable(struct rte_eth_dev *dev)
3625 {
3626         struct bnxt *bp = dev->data->dev_private;
3627         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3628         uint32_t shift = 0;
3629         int rc;
3630
3631         if (!ptp)
3632                 return -ENOTSUP;
3633
3634         ptp->rx_filter = 1;
3635         ptp->tx_tstamp_en = 1;
3636         ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3637
3638         rc = bnxt_hwrm_ptp_cfg(bp);
3639         if (rc)
3640                 return rc;
3641
3642         memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3643         memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3644         memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3645
3646         ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3647         ptp->tc.cc_shift = shift;
3648         ptp->tc.nsec_mask = (1ULL << shift) - 1;
3649
3650         ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3651         ptp->rx_tstamp_tc.cc_shift = shift;
3652         ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3653
3654         ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3655         ptp->tx_tstamp_tc.cc_shift = shift;
3656         ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3657
3658         if (!BNXT_CHIP_P5(bp))
3659                 bnxt_map_ptp_regs(bp);
3660         else
3661                 rc = bnxt_ptp_start(bp);
3662
3663         return rc;
3664 }
3665
3666 static int
3667 bnxt_timesync_disable(struct rte_eth_dev *dev)
3668 {
3669         struct bnxt *bp = dev->data->dev_private;
3670         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3671
3672         if (!ptp)
3673                 return -ENOTSUP;
3674
3675         ptp->rx_filter = 0;
3676         ptp->tx_tstamp_en = 0;
3677         ptp->rxctl = 0;
3678
3679         bnxt_hwrm_ptp_cfg(bp);
3680
3681         if (!BNXT_CHIP_P5(bp))
3682                 bnxt_unmap_ptp_regs(bp);
3683         else
3684                 bnxt_ptp_stop(bp);
3685
3686         return 0;
3687 }
3688
3689 static int
3690 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3691                                  struct timespec *timestamp,
3692                                  uint32_t flags __rte_unused)
3693 {
3694         struct bnxt *bp = dev->data->dev_private;
3695         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3696         uint64_t rx_tstamp_cycles = 0;
3697         uint64_t ns;
3698
3699         if (!ptp)
3700                 return -ENOTSUP;
3701
3702         if (BNXT_CHIP_P5(bp))
3703                 rx_tstamp_cycles = ptp->rx_timestamp;
3704         else
3705                 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3706
3707         ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3708         *timestamp = rte_ns_to_timespec(ns);
3709         return  0;
3710 }
3711
3712 static int
3713 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3714                                  struct timespec *timestamp)
3715 {
3716         struct bnxt *bp = dev->data->dev_private;
3717         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3718         uint64_t tx_tstamp_cycles = 0;
3719         uint64_t ns;
3720         int rc = 0;
3721
3722         if (!ptp)
3723                 return -ENOTSUP;
3724
3725         if (BNXT_CHIP_P5(bp))
3726                 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3727                                              &tx_tstamp_cycles);
3728         else
3729                 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3730
3731         ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3732         *timestamp = rte_ns_to_timespec(ns);
3733
3734         return rc;
3735 }
3736
3737 static int
3738 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3739 {
3740         struct bnxt *bp = dev->data->dev_private;
3741         struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3742
3743         if (!ptp)
3744                 return -ENOTSUP;
3745
3746         ptp->tc.nsec += delta;
3747         ptp->tx_tstamp_tc.nsec += delta;
3748         ptp->rx_tstamp_tc.nsec += delta;
3749
3750         return 0;
3751 }
3752
3753 static int
3754 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3755 {
3756         struct bnxt *bp = dev->data->dev_private;
3757         int rc;
3758         uint32_t dir_entries;
3759         uint32_t entry_length;
3760
3761         rc = is_bnxt_in_error(bp);
3762         if (rc)
3763                 return rc;
3764
3765         PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3766                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3767                     bp->pdev->addr.devid, bp->pdev->addr.function);
3768
3769         rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3770         if (rc != 0)
3771                 return rc;
3772
3773         return dir_entries * entry_length;
3774 }
3775
3776 static int
3777 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3778                 struct rte_dev_eeprom_info *in_eeprom)
3779 {
3780         struct bnxt *bp = dev->data->dev_private;
3781         uint32_t index;
3782         uint32_t offset;
3783         int rc;
3784
3785         rc = is_bnxt_in_error(bp);
3786         if (rc)
3787                 return rc;
3788
3789         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3790                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3791                     bp->pdev->addr.devid, bp->pdev->addr.function,
3792                     in_eeprom->offset, in_eeprom->length);
3793
3794         if (in_eeprom->offset == 0) /* special offset value to get directory */
3795                 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3796                                                 in_eeprom->data);
3797
3798         index = in_eeprom->offset >> 24;
3799         offset = in_eeprom->offset & 0xffffff;
3800
3801         if (index != 0)
3802                 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3803                                            in_eeprom->length, in_eeprom->data);
3804
3805         return 0;
3806 }
3807
3808 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3809 {
3810         switch (dir_type) {
3811         case BNX_DIR_TYPE_CHIMP_PATCH:
3812         case BNX_DIR_TYPE_BOOTCODE:
3813         case BNX_DIR_TYPE_BOOTCODE_2:
3814         case BNX_DIR_TYPE_APE_FW:
3815         case BNX_DIR_TYPE_APE_PATCH:
3816         case BNX_DIR_TYPE_KONG_FW:
3817         case BNX_DIR_TYPE_KONG_PATCH:
3818         case BNX_DIR_TYPE_BONO_FW:
3819         case BNX_DIR_TYPE_BONO_PATCH:
3820                 /* FALLTHROUGH */
3821                 return true;
3822         }
3823
3824         return false;
3825 }
3826
3827 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3828 {
3829         switch (dir_type) {
3830         case BNX_DIR_TYPE_AVS:
3831         case BNX_DIR_TYPE_EXP_ROM_MBA:
3832         case BNX_DIR_TYPE_PCIE:
3833         case BNX_DIR_TYPE_TSCF_UCODE:
3834         case BNX_DIR_TYPE_EXT_PHY:
3835         case BNX_DIR_TYPE_CCM:
3836         case BNX_DIR_TYPE_ISCSI_BOOT:
3837         case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3838         case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3839                 /* FALLTHROUGH */
3840                 return true;
3841         }
3842
3843         return false;
3844 }
3845
3846 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3847 {
3848         return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3849                 bnxt_dir_type_is_other_exec_format(dir_type);
3850 }
3851
3852 static int
3853 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3854                 struct rte_dev_eeprom_info *in_eeprom)
3855 {
3856         struct bnxt *bp = dev->data->dev_private;
3857         uint8_t index, dir_op;
3858         uint16_t type, ext, ordinal, attr;
3859         int rc;
3860
3861         rc = is_bnxt_in_error(bp);
3862         if (rc)
3863                 return rc;
3864
3865         PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3866                     bp->pdev->addr.domain, bp->pdev->addr.bus,
3867                     bp->pdev->addr.devid, bp->pdev->addr.function,
3868                     in_eeprom->offset, in_eeprom->length);
3869
3870         if (!BNXT_PF(bp)) {
3871                 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3872                 return -EINVAL;
3873         }
3874
3875         type = in_eeprom->magic >> 16;
3876
3877         if (type == 0xffff) { /* special value for directory operations */
3878                 index = in_eeprom->magic & 0xff;
3879                 dir_op = in_eeprom->magic >> 8;
3880                 if (index == 0)
3881                         return -EINVAL;
3882                 switch (dir_op) {
3883                 case 0x0e: /* erase */
3884                         if (in_eeprom->offset != ~in_eeprom->magic)
3885                                 return -EINVAL;
3886                         return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3887                 default:
3888                         return -EINVAL;
3889                 }
3890         }
3891
3892         /* Create or re-write an NVM item: */
3893         if (bnxt_dir_type_is_executable(type) == true)
3894                 return -EOPNOTSUPP;
3895         ext = in_eeprom->magic & 0xffff;
3896         ordinal = in_eeprom->offset >> 16;
3897         attr = in_eeprom->offset & 0xffff;
3898
3899         return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3900                                      in_eeprom->data, in_eeprom->length);
3901 }
3902
3903 static int bnxt_get_module_info(struct rte_eth_dev *dev,
3904                                 struct rte_eth_dev_module_info *modinfo)
3905 {
3906         uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3907         struct bnxt *bp = dev->data->dev_private;
3908         int rc;
3909
3910         /* No point in going further if phy status indicates
3911          * module is not inserted or if it is powered down or
3912          * if it is of type 10GBase-T
3913          */
3914         if (bp->link_info->module_status >
3915             HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG) {
3916                 PMD_DRV_LOG(NOTICE, "Port %u : Module is not inserted or is powered down\n",
3917                             dev->data->port_id);
3918                 return -ENOTSUP;
3919         }
3920
3921         /* This feature is not supported in older firmware versions */
3922         if (bp->hwrm_spec_code < 0x10202) {
3923                 PMD_DRV_LOG(NOTICE, "Port %u : Feature is not supported in older firmware\n",
3924                             dev->data->port_id);
3925                 return -ENOTSUP;
3926         }
3927
3928         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3929                                                    SFF_DIAG_SUPPORT_OFFSET + 1,
3930                                                    module_info);
3931
3932         if (rc)
3933                 return rc;
3934
3935         switch (module_info[0]) {
3936         case SFF_MODULE_ID_SFP:
3937                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
3938                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
3939                 if (module_info[SFF_DIAG_SUPPORT_OFFSET] == 0)
3940                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3941                 break;
3942         case SFF_MODULE_ID_QSFP:
3943         case SFF_MODULE_ID_QSFP_PLUS:
3944                 modinfo->type = RTE_ETH_MODULE_SFF_8436;
3945                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN;
3946                 break;
3947         case SFF_MODULE_ID_QSFP28:
3948                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
3949                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN;
3950                 if (module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK)
3951                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_LEN;
3952                 break;
3953         default:
3954                 PMD_DRV_LOG(NOTICE, "Port %u : Unsupported module\n", dev->data->port_id);
3955                 return -ENOTSUP;
3956         }
3957
3958         PMD_DRV_LOG(INFO, "Port %u : modinfo->type = %d modinfo->eeprom_len = %d\n",
3959                     dev->data->port_id, modinfo->type, modinfo->eeprom_len);
3960
3961         return 0;
3962 }
3963
3964 static int bnxt_get_module_eeprom(struct rte_eth_dev *dev,
3965                                   struct rte_dev_eeprom_info *info)
3966 {
3967         uint8_t pg_addr[5] = { I2C_DEV_ADDR_A0, I2C_DEV_ADDR_A0 };
3968         uint32_t offset = info->offset, length = info->length;
3969         uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1];
3970         struct bnxt *bp = dev->data->dev_private;
3971         uint8_t *data = info->data;
3972         uint8_t page = offset >> 7;
3973         uint8_t max_pages = 2;
3974         uint8_t opt_pages;
3975         int rc;
3976
3977         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0,
3978                                                    SFF_DIAG_SUPPORT_OFFSET + 1,
3979                                                    module_info);
3980         if (rc)
3981                 return rc;
3982
3983         switch (module_info[0]) {
3984         case SFF_MODULE_ID_SFP:
3985                 module_info[SFF_DIAG_SUPPORT_OFFSET] = 0;
3986                 if (module_info[SFF_DIAG_SUPPORT_OFFSET]) {
3987                         pg_addr[2] = I2C_DEV_ADDR_A2;
3988                         pg_addr[3] = I2C_DEV_ADDR_A2;
3989                         max_pages = 4;
3990                 }
3991                 break;
3992         case SFF_MODULE_ID_QSFP28:
3993                 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0,
3994                                                            SFF8636_OPT_PAGES_OFFSET,
3995                                                            1, &opt_pages);
3996                 if (rc)
3997                         return rc;
3998
3999                 if (opt_pages & SFF8636_PAGE1_MASK) {
4000                         pg_addr[2] = I2C_DEV_ADDR_A0;
4001                         max_pages = 3;
4002                 }
4003                 if (opt_pages & SFF8636_PAGE2_MASK) {
4004                         pg_addr[3] = I2C_DEV_ADDR_A0;
4005                         max_pages = 4;
4006                 }
4007                 if (~module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK) {
4008                         pg_addr[4] = I2C_DEV_ADDR_A0;
4009                         max_pages = 5;
4010                 }
4011                 break;
4012         default:
4013                 break;
4014         }
4015
4016         memset(data, 0, length);
4017
4018         offset &= 0xff;
4019         while (length && page < max_pages) {
4020                 uint8_t raw_page = page ? page - 1 : 0;
4021                 uint16_t chunk;
4022
4023                 if (pg_addr[page] == I2C_DEV_ADDR_A2)
4024                         raw_page = 0;
4025                 else if (page)
4026                         offset |= 0x80;
4027                 chunk = RTE_MIN(length, 256 - offset);
4028
4029                 if (pg_addr[page]) {
4030                         rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, pg_addr[page],
4031                                                                    raw_page, offset,
4032                                                                    chunk, data);
4033                         if (rc)
4034                                 return rc;
4035                 }
4036
4037                 data += chunk;
4038                 length -= chunk;
4039                 offset = 0;
4040                 page += 1 + (chunk > 128);
4041         }
4042
4043         return length ? -EINVAL : 0;
4044 }
4045
4046 /*
4047  * Initialization
4048  */
4049
4050 static const struct eth_dev_ops bnxt_dev_ops = {
4051         .dev_infos_get = bnxt_dev_info_get_op,
4052         .dev_close = bnxt_dev_close_op,
4053         .dev_configure = bnxt_dev_configure_op,
4054         .dev_start = bnxt_dev_start_op,
4055         .dev_stop = bnxt_dev_stop_op,
4056         .dev_set_link_up = bnxt_dev_set_link_up_op,
4057         .dev_set_link_down = bnxt_dev_set_link_down_op,
4058         .stats_get = bnxt_stats_get_op,
4059         .stats_reset = bnxt_stats_reset_op,
4060         .rx_queue_setup = bnxt_rx_queue_setup_op,
4061         .rx_queue_release = bnxt_rx_queue_release_op,
4062         .tx_queue_setup = bnxt_tx_queue_setup_op,
4063         .tx_queue_release = bnxt_tx_queue_release_op,
4064         .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
4065         .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
4066         .reta_update = bnxt_reta_update_op,
4067         .reta_query = bnxt_reta_query_op,
4068         .rss_hash_update = bnxt_rss_hash_update_op,
4069         .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
4070         .link_update = bnxt_link_update_op,
4071         .promiscuous_enable = bnxt_promiscuous_enable_op,
4072         .promiscuous_disable = bnxt_promiscuous_disable_op,
4073         .allmulticast_enable = bnxt_allmulticast_enable_op,
4074         .allmulticast_disable = bnxt_allmulticast_disable_op,
4075         .mac_addr_add = bnxt_mac_addr_add_op,
4076         .mac_addr_remove = bnxt_mac_addr_remove_op,
4077         .flow_ctrl_get = bnxt_flow_ctrl_get_op,
4078         .flow_ctrl_set = bnxt_flow_ctrl_set_op,
4079         .udp_tunnel_port_add  = bnxt_udp_tunnel_port_add_op,
4080         .udp_tunnel_port_del  = bnxt_udp_tunnel_port_del_op,
4081         .vlan_filter_set = bnxt_vlan_filter_set_op,
4082         .vlan_offload_set = bnxt_vlan_offload_set_op,
4083         .vlan_tpid_set = bnxt_vlan_tpid_set_op,
4084         .vlan_pvid_set = bnxt_vlan_pvid_set_op,
4085         .mtu_set = bnxt_mtu_set_op,
4086         .mac_addr_set = bnxt_set_default_mac_addr_op,
4087         .xstats_get = bnxt_dev_xstats_get_op,
4088         .xstats_get_names = bnxt_dev_xstats_get_names_op,
4089         .xstats_reset = bnxt_dev_xstats_reset_op,
4090         .fw_version_get = bnxt_fw_version_get,
4091         .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
4092         .rxq_info_get = bnxt_rxq_info_get_op,
4093         .txq_info_get = bnxt_txq_info_get_op,
4094         .rx_burst_mode_get = bnxt_rx_burst_mode_get,
4095         .tx_burst_mode_get = bnxt_tx_burst_mode_get,
4096         .dev_led_on = bnxt_dev_led_on_op,
4097         .dev_led_off = bnxt_dev_led_off_op,
4098         .rx_queue_start = bnxt_rx_queue_start,
4099         .rx_queue_stop = bnxt_rx_queue_stop,
4100         .tx_queue_start = bnxt_tx_queue_start,
4101         .tx_queue_stop = bnxt_tx_queue_stop,
4102         .flow_ops_get = bnxt_flow_ops_get_op,
4103         .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
4104         .get_eeprom_length    = bnxt_get_eeprom_length_op,
4105         .get_eeprom           = bnxt_get_eeprom_op,
4106         .set_eeprom           = bnxt_set_eeprom_op,
4107         .get_module_info = bnxt_get_module_info,
4108         .get_module_eeprom = bnxt_get_module_eeprom,
4109         .timesync_enable      = bnxt_timesync_enable,
4110         .timesync_disable     = bnxt_timesync_disable,
4111         .timesync_read_time   = bnxt_timesync_read_time,
4112         .timesync_write_time   = bnxt_timesync_write_time,
4113         .timesync_adjust_time = bnxt_timesync_adjust_time,
4114         .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
4115         .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
4116 };
4117
4118 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
4119 {
4120         uint32_t offset;
4121
4122         /* Only pre-map the reset GRC registers using window 3 */
4123         rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
4124                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
4125
4126         offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
4127
4128         return offset;
4129 }
4130
4131 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
4132 {
4133         struct bnxt_error_recovery_info *info = bp->recovery_info;
4134         uint32_t reg_base = 0xffffffff;
4135         int i;
4136
4137         /* Only pre-map the monitoring GRC registers using window 2 */
4138         for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
4139                 uint32_t reg = info->status_regs[i];
4140
4141                 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
4142                         continue;
4143
4144                 if (reg_base == 0xffffffff)
4145                         reg_base = reg & 0xfffff000;
4146                 if ((reg & 0xfffff000) != reg_base)
4147                         return -ERANGE;
4148
4149                 /* Use mask 0xffc as the Lower 2 bits indicates
4150                  * address space location
4151                  */
4152                 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
4153                                                 (reg & 0xffc);
4154         }
4155
4156         if (reg_base == 0xffffffff)
4157                 return 0;
4158
4159         rte_write32(reg_base, (uint8_t *)bp->bar0 +
4160                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4161
4162         return 0;
4163 }
4164
4165 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
4166 {
4167         struct bnxt_error_recovery_info *info = bp->recovery_info;
4168         uint32_t delay = info->delay_after_reset[index];
4169         uint32_t val = info->reset_reg_val[index];
4170         uint32_t reg = info->reset_reg[index];
4171         uint32_t type, offset;
4172         int ret;
4173
4174         type = BNXT_FW_STATUS_REG_TYPE(reg);
4175         offset = BNXT_FW_STATUS_REG_OFF(reg);
4176
4177         switch (type) {
4178         case BNXT_FW_STATUS_REG_TYPE_CFG:
4179                 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
4180                 if (ret < 0) {
4181                         PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x",
4182                                     val, offset);
4183                         return;
4184                 }
4185                 break;
4186         case BNXT_FW_STATUS_REG_TYPE_GRC:
4187                 offset = bnxt_map_reset_regs(bp, offset);
4188                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4189                 break;
4190         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4191                 rte_write32(val, (uint8_t *)bp->bar0 + offset);
4192                 break;
4193         }
4194         /* wait on a specific interval of time until core reset is complete */
4195         if (delay)
4196                 rte_delay_ms(delay);
4197 }
4198
4199 static void bnxt_dev_cleanup(struct bnxt *bp)
4200 {
4201         bp->eth_dev->data->dev_link.link_status = 0;
4202         bp->link_info->link_up = 0;
4203         if (bp->eth_dev->data->dev_started)
4204                 bnxt_dev_stop(bp->eth_dev);
4205
4206         bnxt_uninit_resources(bp, true);
4207 }
4208
4209 static int
4210 bnxt_check_fw_reset_done(struct bnxt *bp)
4211 {
4212         int timeout = bp->fw_reset_max_msecs;
4213         uint16_t val = 0;
4214         int rc;
4215
4216         do {
4217                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4218                 if (rc < 0) {
4219                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4220                         return rc;
4221                 }
4222                 if (val != 0xffff)
4223                         break;
4224                 rte_delay_ms(1);
4225         } while (timeout--);
4226
4227         if (val == 0xffff) {
4228                 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
4229                 return -1;
4230         }
4231
4232         return 0;
4233 }
4234
4235 static int bnxt_restore_vlan_filters(struct bnxt *bp)
4236 {
4237         struct rte_eth_dev *dev = bp->eth_dev;
4238         struct rte_vlan_filter_conf *vfc;
4239         int vidx, vbit, rc;
4240         uint16_t vlan_id;
4241
4242         for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
4243                 vfc = &dev->data->vlan_filter_conf;
4244                 vidx = vlan_id / 64;
4245                 vbit = vlan_id % 64;
4246
4247                 /* Each bit corresponds to a VLAN id */
4248                 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
4249                         rc = bnxt_add_vlan_filter(bp, vlan_id);
4250                         if (rc)
4251                                 return rc;
4252                 }
4253         }
4254
4255         return 0;
4256 }
4257
4258 static int bnxt_restore_mac_filters(struct bnxt *bp)
4259 {
4260         struct rte_eth_dev *dev = bp->eth_dev;
4261         struct rte_eth_dev_info dev_info;
4262         struct rte_ether_addr *addr;
4263         uint64_t pool_mask;
4264         uint32_t pool = 0;
4265         uint32_t i;
4266         int rc;
4267
4268         if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
4269                 return 0;
4270
4271         rc = bnxt_dev_info_get_op(dev, &dev_info);
4272         if (rc)
4273                 return rc;
4274
4275         /* replay MAC address configuration */
4276         for (i = 1; i < dev_info.max_mac_addrs; i++) {
4277                 addr = &dev->data->mac_addrs[i];
4278
4279                 /* skip zero address */
4280                 if (rte_is_zero_ether_addr(addr))
4281                         continue;
4282
4283                 pool = 0;
4284                 pool_mask = dev->data->mac_pool_sel[i];
4285
4286                 do {
4287                         if (pool_mask & 1ULL) {
4288                                 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
4289                                 if (rc)
4290                                         return rc;
4291                         }
4292                         pool_mask >>= 1;
4293                         pool++;
4294                 } while (pool_mask);
4295         }
4296
4297         return 0;
4298 }
4299
4300 static int bnxt_restore_filters(struct bnxt *bp)
4301 {
4302         struct rte_eth_dev *dev = bp->eth_dev;
4303         int ret = 0;
4304
4305         if (dev->data->all_multicast) {
4306                 ret = bnxt_allmulticast_enable_op(dev);
4307                 if (ret)
4308                         return ret;
4309         }
4310         if (dev->data->promiscuous) {
4311                 ret = bnxt_promiscuous_enable_op(dev);
4312                 if (ret)
4313                         return ret;
4314         }
4315
4316         ret = bnxt_restore_mac_filters(bp);
4317         if (ret)
4318                 return ret;
4319
4320         ret = bnxt_restore_vlan_filters(bp);
4321         /* TODO restore other filters as well */
4322         return ret;
4323 }
4324
4325 static int bnxt_check_fw_ready(struct bnxt *bp)
4326 {
4327         int timeout = bp->fw_reset_max_msecs;
4328         int rc = 0;
4329
4330         do {
4331                 rc = bnxt_hwrm_poll_ver_get(bp);
4332                 if (rc == 0)
4333                         break;
4334                 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4335                 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4336         } while (rc && timeout > 0);
4337
4338         if (rc)
4339                 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4340
4341         return rc;
4342 }
4343
4344 static void bnxt_dev_recover(void *arg)
4345 {
4346         struct bnxt *bp = arg;
4347         int rc = 0;
4348
4349         pthread_mutex_lock(&bp->err_recovery_lock);
4350
4351         if (!bp->fw_reset_min_msecs) {
4352                 rc = bnxt_check_fw_reset_done(bp);
4353                 if (rc)
4354                         goto err;
4355         }
4356
4357         /* Clear Error flag so that device re-init should happen */
4358         bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4359
4360         rc = bnxt_check_fw_ready(bp);
4361         if (rc)
4362                 goto err;
4363
4364         rc = bnxt_init_resources(bp, true);
4365         if (rc) {
4366                 PMD_DRV_LOG(ERR,
4367                             "Failed to initialize resources after reset\n");
4368                 goto err;
4369         }
4370         /* clear reset flag as the device is initialized now */
4371         bp->flags &= ~BNXT_FLAG_FW_RESET;
4372
4373         rc = bnxt_dev_start_op(bp->eth_dev);
4374         if (rc) {
4375                 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4376                 goto err_start;
4377         }
4378
4379         rc = bnxt_restore_filters(bp);
4380         if (rc)
4381                 goto err_start;
4382
4383         PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4384         pthread_mutex_unlock(&bp->err_recovery_lock);
4385
4386         return;
4387 err_start:
4388         bnxt_dev_stop(bp->eth_dev);
4389 err:
4390         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4391         bnxt_uninit_resources(bp, false);
4392         if (bp->eth_dev->data->dev_conf.intr_conf.rmv)
4393                 rte_eth_dev_callback_process(bp->eth_dev,
4394                                              RTE_ETH_EVENT_INTR_RMV,
4395                                              NULL);
4396         pthread_mutex_unlock(&bp->err_recovery_lock);
4397         PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4398 }
4399
4400 void bnxt_dev_reset_and_resume(void *arg)
4401 {
4402         struct bnxt *bp = arg;
4403         uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4404         uint16_t val = 0;
4405         int rc;
4406
4407         bnxt_dev_cleanup(bp);
4408
4409         bnxt_wait_for_device_shutdown(bp);
4410
4411         /* During some fatal firmware error conditions, the PCI config space
4412          * register 0x2e which normally contains the subsystem ID will become
4413          * 0xffff. This register will revert back to the normal value after
4414          * the chip has completed core reset. If we detect this condition,
4415          * we can poll this config register immediately for the value to revert.
4416          */
4417         if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4418                 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4419                 if (rc < 0) {
4420                         PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4421                         return;
4422                 }
4423                 if (val == 0xffff) {
4424                         bp->fw_reset_min_msecs = 0;
4425                         us = 1;
4426                 }
4427         }
4428
4429         rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4430         if (rc)
4431                 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4432 }
4433
4434 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4435 {
4436         struct bnxt_error_recovery_info *info = bp->recovery_info;
4437         uint32_t reg = info->status_regs[index];
4438         uint32_t type, offset, val = 0;
4439         int ret = 0;
4440
4441         type = BNXT_FW_STATUS_REG_TYPE(reg);
4442         offset = BNXT_FW_STATUS_REG_OFF(reg);
4443
4444         switch (type) {
4445         case BNXT_FW_STATUS_REG_TYPE_CFG:
4446                 ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4447                 if (ret < 0)
4448                         PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x",
4449                                     offset);
4450                 break;
4451         case BNXT_FW_STATUS_REG_TYPE_GRC:
4452                 offset = info->mapped_status_regs[index];
4453                 /* FALLTHROUGH */
4454         case BNXT_FW_STATUS_REG_TYPE_BAR0:
4455                 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4456                                        offset));
4457                 break;
4458         }
4459
4460         return val;
4461 }
4462
4463 static int bnxt_fw_reset_all(struct bnxt *bp)
4464 {
4465         struct bnxt_error_recovery_info *info = bp->recovery_info;
4466         uint32_t i;
4467         int rc = 0;
4468
4469         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4470                 /* Reset through primary function driver */
4471                 for (i = 0; i < info->reg_array_cnt; i++)
4472                         bnxt_write_fw_reset_reg(bp, i);
4473                 /* Wait for time specified by FW after triggering reset */
4474                 rte_delay_ms(info->primary_func_wait_period_after_reset);
4475         } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4476                 /* Reset with the help of Kong processor */
4477                 rc = bnxt_hwrm_fw_reset(bp);
4478                 if (rc)
4479                         PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4480         }
4481
4482         return rc;
4483 }
4484
4485 static void bnxt_fw_reset_cb(void *arg)
4486 {
4487         struct bnxt *bp = arg;
4488         struct bnxt_error_recovery_info *info = bp->recovery_info;
4489         int rc = 0;
4490
4491         /* Only Primary function can do FW reset */
4492         if (bnxt_is_primary_func(bp) &&
4493             bnxt_is_recovery_enabled(bp)) {
4494                 rc = bnxt_fw_reset_all(bp);
4495                 if (rc) {
4496                         PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4497                         return;
4498                 }
4499         }
4500
4501         /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4502          * EXCEPTION_FATAL_ASYNC event to all the functions
4503          * (including MASTER FUNC). After receiving this Async, all the active
4504          * drivers should treat this case as FW initiated recovery
4505          */
4506         if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4507                 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4508                 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4509
4510                 /* To recover from error */
4511                 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4512                                   (void *)bp);
4513         }
4514 }
4515
4516 /* Driver should poll FW heartbeat, reset_counter with the frequency
4517  * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4518  * When the driver detects heartbeat stop or change in reset_counter,
4519  * it has to trigger a reset to recover from the error condition.
4520  * A “primary function” is the function who will have the privilege to
4521  * initiate the chimp reset. The primary function will be elected by the
4522  * firmware and will be notified through async message.
4523  */
4524 static void bnxt_check_fw_health(void *arg)
4525 {
4526         struct bnxt *bp = arg;
4527         struct bnxt_error_recovery_info *info = bp->recovery_info;
4528         uint32_t val = 0, wait_msec;
4529
4530         if (!info || !bnxt_is_recovery_enabled(bp) ||
4531             is_bnxt_in_error(bp))
4532                 return;
4533
4534         val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4535         if (val == info->last_heart_beat)
4536                 goto reset;
4537
4538         info->last_heart_beat = val;
4539
4540         val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4541         if (val != info->last_reset_counter)
4542                 goto reset;
4543
4544         info->last_reset_counter = val;
4545
4546         rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4547                           bnxt_check_fw_health, (void *)bp);
4548
4549         return;
4550 reset:
4551         /* Stop DMA to/from device */
4552         bp->flags |= BNXT_FLAG_FATAL_ERROR;
4553         bp->flags |= BNXT_FLAG_FW_RESET;
4554
4555         bnxt_stop_rxtx(bp);
4556
4557         PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4558
4559         if (bnxt_is_primary_func(bp))
4560                 wait_msec = info->primary_func_wait_period;
4561         else
4562                 wait_msec = info->normal_func_wait_period;
4563
4564         rte_eal_alarm_set(US_PER_MS * wait_msec,
4565                           bnxt_fw_reset_cb, (void *)bp);
4566 }
4567
4568 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4569 {
4570         uint32_t polling_freq;
4571
4572         pthread_mutex_lock(&bp->health_check_lock);
4573
4574         if (!bnxt_is_recovery_enabled(bp))
4575                 goto done;
4576
4577         if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4578                 goto done;
4579
4580         polling_freq = bp->recovery_info->driver_polling_freq;
4581
4582         rte_eal_alarm_set(US_PER_MS * polling_freq,
4583                           bnxt_check_fw_health, (void *)bp);
4584         bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4585
4586 done:
4587         pthread_mutex_unlock(&bp->health_check_lock);
4588 }
4589
4590 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4591 {
4592         rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4593         bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4594 }
4595
4596 static bool bnxt_vf_pciid(uint16_t device_id)
4597 {
4598         switch (device_id) {
4599         case BROADCOM_DEV_ID_57304_VF:
4600         case BROADCOM_DEV_ID_57406_VF:
4601         case BROADCOM_DEV_ID_5731X_VF:
4602         case BROADCOM_DEV_ID_5741X_VF:
4603         case BROADCOM_DEV_ID_57414_VF:
4604         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4605         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4606         case BROADCOM_DEV_ID_58802_VF:
4607         case BROADCOM_DEV_ID_57500_VF1:
4608         case BROADCOM_DEV_ID_57500_VF2:
4609         case BROADCOM_DEV_ID_58818_VF:
4610                 /* FALLTHROUGH */
4611                 return true;
4612         default:
4613                 return false;
4614         }
4615 }
4616
4617 /* Phase 5 device */
4618 static bool bnxt_p5_device(uint16_t device_id)
4619 {
4620         switch (device_id) {
4621         case BROADCOM_DEV_ID_57508:
4622         case BROADCOM_DEV_ID_57504:
4623         case BROADCOM_DEV_ID_57502:
4624         case BROADCOM_DEV_ID_57508_MF1:
4625         case BROADCOM_DEV_ID_57504_MF1:
4626         case BROADCOM_DEV_ID_57502_MF1:
4627         case BROADCOM_DEV_ID_57508_MF2:
4628         case BROADCOM_DEV_ID_57504_MF2:
4629         case BROADCOM_DEV_ID_57502_MF2:
4630         case BROADCOM_DEV_ID_57500_VF1:
4631         case BROADCOM_DEV_ID_57500_VF2:
4632         case BROADCOM_DEV_ID_58812:
4633         case BROADCOM_DEV_ID_58814:
4634         case BROADCOM_DEV_ID_58818:
4635         case BROADCOM_DEV_ID_58818_VF:
4636                 /* FALLTHROUGH */
4637                 return true;
4638         default:
4639                 return false;
4640         }
4641 }
4642
4643 bool bnxt_stratus_device(struct bnxt *bp)
4644 {
4645         uint16_t device_id = bp->pdev->id.device_id;
4646
4647         switch (device_id) {
4648         case BROADCOM_DEV_ID_STRATUS_NIC:
4649         case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4650         case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4651                 /* FALLTHROUGH */
4652                 return true;
4653         default:
4654                 return false;
4655         }
4656 }
4657
4658 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4659 {
4660         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4661         struct bnxt *bp = eth_dev->data->dev_private;
4662
4663         /* enable device (incl. PCI PM wakeup), and bus-mastering */
4664         bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4665         bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4666         if (!bp->bar0 || !bp->doorbell_base) {
4667                 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4668                 return -ENODEV;
4669         }
4670
4671         bp->eth_dev = eth_dev;
4672         bp->pdev = pci_dev;
4673
4674         return 0;
4675 }
4676
4677 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4678                                   struct bnxt_ctx_pg_info *ctx_pg,
4679                                   uint32_t mem_size,
4680                                   const char *suffix,
4681                                   uint16_t idx)
4682 {
4683         struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4684         const struct rte_memzone *mz = NULL;
4685         char mz_name[RTE_MEMZONE_NAMESIZE];
4686         rte_iova_t mz_phys_addr;
4687         uint64_t valid_bits = 0;
4688         uint32_t sz;
4689         int i;
4690
4691         if (!mem_size)
4692                 return 0;
4693
4694         rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4695                          BNXT_PAGE_SIZE;
4696         rmem->page_size = BNXT_PAGE_SIZE;
4697         rmem->pg_arr = ctx_pg->ctx_pg_arr;
4698         rmem->dma_arr = ctx_pg->ctx_dma_arr;
4699         rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4700
4701         valid_bits = PTU_PTE_VALID;
4702
4703         if (rmem->nr_pages > 1) {
4704                 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4705                          "bnxt_ctx_pg_tbl%s_%x_%d",
4706                          suffix, idx, bp->eth_dev->data->port_id);
4707                 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4708                 mz = rte_memzone_lookup(mz_name);
4709                 if (!mz) {
4710                         mz = rte_memzone_reserve_aligned(mz_name,
4711                                                 rmem->nr_pages * 8,
4712                                                 bp->eth_dev->device->numa_node,
4713                                                 RTE_MEMZONE_2MB |
4714                                                 RTE_MEMZONE_SIZE_HINT_ONLY |
4715                                                 RTE_MEMZONE_IOVA_CONTIG,
4716                                                 BNXT_PAGE_SIZE);
4717                         if (mz == NULL)
4718                                 return -ENOMEM;
4719                 }
4720
4721                 memset(mz->addr, 0, mz->len);
4722                 mz_phys_addr = mz->iova;
4723
4724                 rmem->pg_tbl = mz->addr;
4725                 rmem->pg_tbl_map = mz_phys_addr;
4726                 rmem->pg_tbl_mz = mz;
4727         }
4728
4729         snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4730                  suffix, idx, bp->eth_dev->data->port_id);
4731         mz = rte_memzone_lookup(mz_name);
4732         if (!mz) {
4733                 mz = rte_memzone_reserve_aligned(mz_name,
4734                                                  mem_size,
4735                                                  bp->eth_dev->device->numa_node,
4736                                                  RTE_MEMZONE_1GB |
4737                                                  RTE_MEMZONE_SIZE_HINT_ONLY |
4738                                                  RTE_MEMZONE_IOVA_CONTIG,
4739                                                  BNXT_PAGE_SIZE);
4740                 if (mz == NULL)
4741                         return -ENOMEM;
4742         }
4743
4744         memset(mz->addr, 0, mz->len);
4745         mz_phys_addr = mz->iova;
4746
4747         for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4748                 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4749                 rmem->dma_arr[i] = mz_phys_addr + sz;
4750
4751                 if (rmem->nr_pages > 1) {
4752                         if (i == rmem->nr_pages - 2 &&
4753                             (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4754                                 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4755                         else if (i == rmem->nr_pages - 1 &&
4756                                  (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4757                                 valid_bits |= PTU_PTE_LAST;
4758
4759                         rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4760                                                            valid_bits);
4761                 }
4762         }
4763
4764         rmem->mz = mz;
4765         if (rmem->vmem_size)
4766                 rmem->vmem = (void **)mz->addr;
4767         rmem->dma_arr[0] = mz_phys_addr;
4768         return 0;
4769 }
4770
4771 static void bnxt_free_ctx_mem(struct bnxt *bp)
4772 {
4773         int i;
4774
4775         if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4776                 return;
4777
4778         bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4779         rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4780         rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4781         rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4782         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4783         rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4784         rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4785         rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4786         rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4787         rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4788         rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4789
4790         for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4791                 if (bp->ctx->tqm_mem[i])
4792                         rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4793         }
4794
4795         rte_free(bp->ctx);
4796         bp->ctx = NULL;
4797 }
4798
4799 #define bnxt_roundup(x, y)   ((((x) + ((y) - 1)) / (y)) * (y))
4800
4801 #define min_t(type, x, y) ({                    \
4802         type __min1 = (x);                      \
4803         type __min2 = (y);                      \
4804         __min1 < __min2 ? __min1 : __min2; })
4805
4806 #define max_t(type, x, y) ({                    \
4807         type __max1 = (x);                      \
4808         type __max2 = (y);                      \
4809         __max1 > __max2 ? __max1 : __max2; })
4810
4811 #define clamp_t(type, _x, min, max)     min_t(type, max_t(type, _x, min), max)
4812
4813 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4814 {
4815         struct bnxt_ctx_pg_info *ctx_pg;
4816         struct bnxt_ctx_mem_info *ctx;
4817         uint32_t mem_size, ena, entries;
4818         uint32_t entries_sp, min;
4819         int i, rc;
4820
4821         rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4822         if (rc) {
4823                 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4824                 return rc;
4825         }
4826         ctx = bp->ctx;
4827         if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4828                 return 0;
4829
4830         ctx_pg = &ctx->qp_mem;
4831         ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4832         if (ctx->qp_entry_size) {
4833                 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4834                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4835                 if (rc)
4836                         return rc;
4837         }
4838
4839         ctx_pg = &ctx->srq_mem;
4840         ctx_pg->entries = ctx->srq_max_l2_entries;
4841         if (ctx->srq_entry_size) {
4842                 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4843                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4844                 if (rc)
4845                         return rc;
4846         }
4847
4848         ctx_pg = &ctx->cq_mem;
4849         ctx_pg->entries = ctx->cq_max_l2_entries;
4850         if (ctx->cq_entry_size) {
4851                 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4852                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4853                 if (rc)
4854                         return rc;
4855         }
4856
4857         ctx_pg = &ctx->vnic_mem;
4858         ctx_pg->entries = ctx->vnic_max_vnic_entries +
4859                 ctx->vnic_max_ring_table_entries;
4860         if (ctx->vnic_entry_size) {
4861                 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4862                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4863                 if (rc)
4864                         return rc;
4865         }
4866
4867         ctx_pg = &ctx->stat_mem;
4868         ctx_pg->entries = ctx->stat_max_entries;
4869         if (ctx->stat_entry_size) {
4870                 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4871                 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4872                 if (rc)
4873                         return rc;
4874         }
4875
4876         min = ctx->tqm_min_entries_per_ring;
4877
4878         entries_sp = ctx->qp_max_l2_entries +
4879                      ctx->vnic_max_vnic_entries +
4880                      2 * ctx->qp_min_qp1_entries + min;
4881         entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4882
4883         entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4884         entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4885         entries = clamp_t(uint32_t, entries, min,
4886                           ctx->tqm_max_entries_per_ring);
4887         for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4888                 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4889                  * i > 8 is other ext rings.
4890                  */
4891                 ctx_pg = ctx->tqm_mem[i];
4892                 ctx_pg->entries = i ? entries : entries_sp;
4893                 if (ctx->tqm_entry_size) {
4894                         mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4895                         rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4896                                                     "tqm_mem", i);
4897                         if (rc)
4898                                 return rc;
4899                 }
4900                 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4901                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4902                 else
4903                         ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4904         }
4905
4906         ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4907         rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4908         if (rc)
4909                 PMD_DRV_LOG(ERR,
4910                             "Failed to configure context mem: rc = %d\n", rc);
4911         else
4912                 ctx->flags |= BNXT_CTX_FLAG_INITED;
4913
4914         return rc;
4915 }
4916
4917 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4918 {
4919         struct rte_pci_device *pci_dev = bp->pdev;
4920         char mz_name[RTE_MEMZONE_NAMESIZE];
4921         const struct rte_memzone *mz = NULL;
4922         uint32_t total_alloc_len;
4923         rte_iova_t mz_phys_addr;
4924
4925         if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4926                 return 0;
4927
4928         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4929                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4930                  pci_dev->addr.bus, pci_dev->addr.devid,
4931                  pci_dev->addr.function, "rx_port_stats");
4932         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4933         mz = rte_memzone_lookup(mz_name);
4934         total_alloc_len =
4935                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4936                                        sizeof(struct rx_port_stats_ext) + 512);
4937         if (!mz) {
4938                 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4939                                          SOCKET_ID_ANY,
4940                                          RTE_MEMZONE_2MB |
4941                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4942                                          RTE_MEMZONE_IOVA_CONTIG);
4943                 if (mz == NULL)
4944                         return -ENOMEM;
4945         }
4946         memset(mz->addr, 0, mz->len);
4947         mz_phys_addr = mz->iova;
4948
4949         bp->rx_mem_zone = (const void *)mz;
4950         bp->hw_rx_port_stats = mz->addr;
4951         bp->hw_rx_port_stats_map = mz_phys_addr;
4952
4953         snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4954                  "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4955                  pci_dev->addr.bus, pci_dev->addr.devid,
4956                  pci_dev->addr.function, "tx_port_stats");
4957         mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4958         mz = rte_memzone_lookup(mz_name);
4959         total_alloc_len =
4960                 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4961                                        sizeof(struct tx_port_stats_ext) + 512);
4962         if (!mz) {
4963                 mz = rte_memzone_reserve(mz_name,
4964                                          total_alloc_len,
4965                                          SOCKET_ID_ANY,
4966                                          RTE_MEMZONE_2MB |
4967                                          RTE_MEMZONE_SIZE_HINT_ONLY |
4968                                          RTE_MEMZONE_IOVA_CONTIG);
4969                 if (mz == NULL)
4970                         return -ENOMEM;
4971         }
4972         memset(mz->addr, 0, mz->len);
4973         mz_phys_addr = mz->iova;
4974
4975         bp->tx_mem_zone = (const void *)mz;
4976         bp->hw_tx_port_stats = mz->addr;
4977         bp->hw_tx_port_stats_map = mz_phys_addr;
4978         bp->flags |= BNXT_FLAG_PORT_STATS;
4979
4980         /* Display extended statistics if FW supports it */
4981         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4982             bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4983             !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4984                 return 0;
4985
4986         bp->hw_rx_port_stats_ext = (void *)
4987                 ((uint8_t *)bp->hw_rx_port_stats +
4988                  sizeof(struct rx_port_stats));
4989         bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4990                 sizeof(struct rx_port_stats);
4991         bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4992
4993         if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4994             bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4995                 bp->hw_tx_port_stats_ext = (void *)
4996                         ((uint8_t *)bp->hw_tx_port_stats +
4997                          sizeof(struct tx_port_stats));
4998                 bp->hw_tx_port_stats_ext_map =
4999                         bp->hw_tx_port_stats_map +
5000                         sizeof(struct tx_port_stats);
5001                 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
5002         }
5003
5004         return 0;
5005 }
5006
5007 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
5008 {
5009         struct bnxt *bp = eth_dev->data->dev_private;
5010         int rc = 0;
5011
5012         eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
5013                                                RTE_ETHER_ADDR_LEN *
5014                                                bp->max_l2_ctx,
5015                                                0);
5016         if (eth_dev->data->mac_addrs == NULL) {
5017                 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
5018                 return -ENOMEM;
5019         }
5020
5021         if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
5022                 if (BNXT_PF(bp))
5023                         return -EINVAL;
5024
5025                 /* Generate a random MAC address, if none was assigned by PF */
5026                 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
5027                 bnxt_eth_hw_addr_random(bp->mac_addr);
5028                 PMD_DRV_LOG(INFO,
5029                             "Assign random MAC:" RTE_ETHER_ADDR_PRT_FMT "\n",
5030                             bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
5031                             bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
5032
5033                 rc = bnxt_hwrm_set_mac(bp);
5034                 if (rc)
5035                         return rc;
5036         }
5037
5038         /* Copy the permanent MAC from the FUNC_QCAPS response */
5039         memcpy(&eth_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
5040
5041         return rc;
5042 }
5043
5044 static int bnxt_restore_dflt_mac(struct bnxt *bp)
5045 {
5046         int rc = 0;
5047
5048         /* MAC is already configured in FW */
5049         if (BNXT_HAS_DFLT_MAC_SET(bp))
5050                 return 0;
5051
5052         /* Restore the old MAC configured */
5053         rc = bnxt_hwrm_set_mac(bp);
5054         if (rc)
5055                 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
5056
5057         return rc;
5058 }
5059
5060 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
5061 {
5062         if (!BNXT_PF(bp))
5063                 return;
5064
5065         memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
5066
5067         if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
5068                 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
5069         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
5070         BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
5071         BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
5072         BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
5073 }
5074
5075 struct bnxt *
5076 bnxt_get_bp(uint16_t port)
5077 {
5078         struct bnxt *bp;
5079         struct rte_eth_dev *dev;
5080
5081         if (!rte_eth_dev_is_valid_port(port)) {
5082                 PMD_DRV_LOG(ERR, "Invalid port %d\n", port);
5083                 return NULL;
5084         }
5085
5086         dev = &rte_eth_devices[port];
5087         if (!is_bnxt_supported(dev)) {
5088                 PMD_DRV_LOG(ERR, "Device %d not supported\n", port);
5089                 return NULL;
5090         }
5091
5092         bp = (struct bnxt *)dev->data->dev_private;
5093         if (!BNXT_TRUFLOW_EN(bp)) {
5094                 PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n");
5095                 return NULL;
5096         }
5097
5098         return bp;
5099 }
5100
5101 uint16_t
5102 bnxt_get_svif(uint16_t port_id, bool func_svif,
5103               enum bnxt_ulp_intf_type type)
5104 {
5105         struct rte_eth_dev *eth_dev;
5106         struct bnxt *bp;
5107
5108         eth_dev = &rte_eth_devices[port_id];
5109         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5110                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5111                 if (!vfr)
5112                         return 0;
5113
5114                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5115                         return vfr->svif;
5116
5117                 eth_dev = vfr->parent_dev;
5118         }
5119
5120         bp = eth_dev->data->dev_private;
5121
5122         return func_svif ? bp->func_svif : bp->port_svif;
5123 }
5124
5125 void
5126 bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type,
5127                    uint8_t *mac, uint8_t *parent_mac)
5128 {
5129         struct rte_eth_dev *eth_dev;
5130         struct bnxt *bp;
5131
5132         if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF &&
5133             type != BNXT_ULP_INTF_TYPE_PF)
5134                 return;
5135
5136         eth_dev = &rte_eth_devices[port];
5137         bp = eth_dev->data->dev_private;
5138         memcpy(mac, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5139
5140         if (type == BNXT_ULP_INTF_TYPE_TRUSTED_VF)
5141                 memcpy(parent_mac, bp->parent->mac_addr, RTE_ETHER_ADDR_LEN);
5142 }
5143
5144 uint16_t
5145 bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5146 {
5147         struct rte_eth_dev *eth_dev;
5148         struct bnxt *bp;
5149
5150         if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF)
5151                 return 0;
5152
5153         eth_dev = &rte_eth_devices[port];
5154         bp = eth_dev->data->dev_private;
5155
5156         return bp->parent->vnic;
5157 }
5158 uint16_t
5159 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
5160 {
5161         struct rte_eth_dev *eth_dev;
5162         struct bnxt_vnic_info *vnic;
5163         struct bnxt *bp;
5164
5165         eth_dev = &rte_eth_devices[port];
5166         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5167                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5168                 if (!vfr)
5169                         return 0;
5170
5171                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5172                         return vfr->dflt_vnic_id;
5173
5174                 eth_dev = vfr->parent_dev;
5175         }
5176
5177         bp = eth_dev->data->dev_private;
5178
5179         vnic = BNXT_GET_DEFAULT_VNIC(bp);
5180
5181         return vnic->fw_vnic_id;
5182 }
5183
5184 uint16_t
5185 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
5186 {
5187         struct rte_eth_dev *eth_dev;
5188         struct bnxt *bp;
5189
5190         eth_dev = &rte_eth_devices[port];
5191         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5192                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5193                 if (!vfr)
5194                         return 0;
5195
5196                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5197                         return vfr->fw_fid;
5198
5199                 eth_dev = vfr->parent_dev;
5200         }
5201
5202         bp = eth_dev->data->dev_private;
5203
5204         return bp->fw_fid;
5205 }
5206
5207 enum bnxt_ulp_intf_type
5208 bnxt_get_interface_type(uint16_t port)
5209 {
5210         struct rte_eth_dev *eth_dev;
5211         struct bnxt *bp;
5212
5213         eth_dev = &rte_eth_devices[port];
5214         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
5215                 return BNXT_ULP_INTF_TYPE_VF_REP;
5216
5217         bp = eth_dev->data->dev_private;
5218         if (BNXT_PF(bp))
5219                 return BNXT_ULP_INTF_TYPE_PF;
5220         else if (BNXT_VF_IS_TRUSTED(bp))
5221                 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
5222         else if (BNXT_VF(bp))
5223                 return BNXT_ULP_INTF_TYPE_VF;
5224
5225         return BNXT_ULP_INTF_TYPE_INVALID;
5226 }
5227
5228 uint16_t
5229 bnxt_get_phy_port_id(uint16_t port_id)
5230 {
5231         struct bnxt_representor *vfr;
5232         struct rte_eth_dev *eth_dev;
5233         struct bnxt *bp;
5234
5235         eth_dev = &rte_eth_devices[port_id];
5236         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5237                 vfr = eth_dev->data->dev_private;
5238                 if (!vfr)
5239                         return 0;
5240
5241                 eth_dev = vfr->parent_dev;
5242         }
5243
5244         bp = eth_dev->data->dev_private;
5245
5246         return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
5247 }
5248
5249 uint16_t
5250 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
5251 {
5252         struct rte_eth_dev *eth_dev;
5253         struct bnxt *bp;
5254
5255         eth_dev = &rte_eth_devices[port_id];
5256         if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
5257                 struct bnxt_representor *vfr = eth_dev->data->dev_private;
5258                 if (!vfr)
5259                         return 0;
5260
5261                 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
5262                         return vfr->fw_fid - 1;
5263
5264                 eth_dev = vfr->parent_dev;
5265         }
5266
5267         bp = eth_dev->data->dev_private;
5268
5269         return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
5270 }
5271
5272 uint16_t
5273 bnxt_get_vport(uint16_t port_id)
5274 {
5275         return (1 << bnxt_get_phy_port_id(port_id));
5276 }
5277
5278 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
5279 {
5280         struct bnxt_error_recovery_info *info = bp->recovery_info;
5281
5282         if (info) {
5283                 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
5284                         memset(info, 0, sizeof(*info));
5285                 return;
5286         }
5287
5288         if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5289                 return;
5290
5291         info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5292                            sizeof(*info), 0);
5293         if (!info)
5294                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5295
5296         bp->recovery_info = info;
5297 }
5298
5299 static void bnxt_check_fw_status(struct bnxt *bp)
5300 {
5301         uint32_t fw_status;
5302
5303         if (!(bp->recovery_info &&
5304               (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
5305                 return;
5306
5307         fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
5308         if (fw_status != BNXT_FW_STATUS_HEALTHY)
5309                 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
5310                             fw_status);
5311 }
5312
5313 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
5314 {
5315         struct bnxt_error_recovery_info *info = bp->recovery_info;
5316         uint32_t status_loc;
5317         uint32_t sig_ver;
5318
5319         rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
5320                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5321         sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5322                                    BNXT_GRCP_WINDOW_2_BASE +
5323                                    offsetof(struct hcomm_status,
5324                                             sig_ver)));
5325         /* If the signature is absent, then FW does not support this feature */
5326         if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
5327             HCOMM_STATUS_SIGNATURE_VAL)
5328                 return 0;
5329
5330         if (!info) {
5331                 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
5332                                    sizeof(*info), 0);
5333                 if (!info)
5334                         return -ENOMEM;
5335                 bp->recovery_info = info;
5336         } else {
5337                 memset(info, 0, sizeof(*info));
5338         }
5339
5340         status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
5341                                       BNXT_GRCP_WINDOW_2_BASE +
5342                                       offsetof(struct hcomm_status,
5343                                                fw_status_loc)));
5344
5345         /* Only pre-map the FW health status GRC register */
5346         if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
5347                 return 0;
5348
5349         info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
5350         info->mapped_status_regs[BNXT_FW_STATUS_REG] =
5351                 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
5352
5353         rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
5354                     BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
5355
5356         bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
5357
5358         return 0;
5359 }
5360
5361 /* This function gets the FW version along with the
5362  * capabilities(MAX and current) of the function, vnic,
5363  * error recovery, phy and other chip related info
5364  */
5365 static int bnxt_get_config(struct bnxt *bp)
5366 {
5367         uint16_t mtu;
5368         int rc = 0;
5369
5370         bp->fw_cap = 0;
5371
5372         rc = bnxt_map_hcomm_fw_status_reg(bp);
5373         if (rc)
5374                 return rc;
5375
5376         rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
5377         if (rc) {
5378                 bnxt_check_fw_status(bp);
5379                 return rc;
5380         }
5381
5382         rc = bnxt_hwrm_func_reset(bp);
5383         if (rc)
5384                 return -EIO;
5385
5386         rc = bnxt_hwrm_vnic_qcaps(bp);
5387         if (rc)
5388                 return rc;
5389
5390         rc = bnxt_hwrm_queue_qportcfg(bp);
5391         if (rc)
5392                 return rc;
5393
5394         /* Get the MAX capabilities for this function.
5395          * This function also allocates context memory for TQM rings and
5396          * informs the firmware about this allocated backing store memory.
5397          */
5398         rc = bnxt_hwrm_func_qcaps(bp);
5399         if (rc)
5400                 return rc;
5401
5402         rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5403         if (rc)
5404                 return rc;
5405
5406         rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5407         if (rc)
5408                 return rc;
5409
5410         bnxt_hwrm_port_mac_qcfg(bp);
5411
5412         bnxt_hwrm_parent_pf_qcfg(bp);
5413
5414         bnxt_hwrm_port_phy_qcaps(bp);
5415
5416         bnxt_alloc_error_recovery_info(bp);
5417         /* Get the adapter error recovery support info */
5418         rc = bnxt_hwrm_error_recovery_qcfg(bp);
5419         if (rc)
5420                 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5421
5422         bnxt_hwrm_port_led_qcaps(bp);
5423
5424         return 0;
5425 }
5426
5427 static int
5428 bnxt_init_locks(struct bnxt *bp)
5429 {
5430         int err;
5431
5432         err = pthread_mutex_init(&bp->flow_lock, NULL);
5433         if (err) {
5434                 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5435                 return err;
5436         }
5437
5438         err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5439         if (err) {
5440                 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5441                 return err;
5442         }
5443
5444         err = pthread_mutex_init(&bp->health_check_lock, NULL);
5445         if (err) {
5446                 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5447                 return err;
5448         }
5449
5450         err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5451         if (err)
5452                 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5453
5454         return err;
5455 }
5456
5457 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5458 {
5459         int rc = 0;
5460
5461         rc = bnxt_get_config(bp);
5462         if (rc)
5463                 return rc;
5464
5465         if (!reconfig_dev) {
5466                 rc = bnxt_setup_mac_addr(bp->eth_dev);
5467                 if (rc)
5468                         return rc;
5469         } else {
5470                 rc = bnxt_restore_dflt_mac(bp);
5471                 if (rc)
5472                         return rc;
5473         }
5474
5475         bnxt_config_vf_req_fwd(bp);
5476
5477         rc = bnxt_hwrm_func_driver_register(bp);
5478         if (rc) {
5479                 PMD_DRV_LOG(ERR, "Failed to register driver");
5480                 return -EBUSY;
5481         }
5482
5483         if (BNXT_PF(bp)) {
5484                 if (bp->pdev->max_vfs) {
5485                         rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5486                         if (rc) {
5487                                 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5488                                 return rc;
5489                         }
5490                 } else {
5491                         rc = bnxt_hwrm_allocate_pf_only(bp);
5492                         if (rc) {
5493                                 PMD_DRV_LOG(ERR,
5494                                             "Failed to allocate PF resources");
5495                                 return rc;
5496                         }
5497                 }
5498         }
5499
5500         rc = bnxt_alloc_mem(bp, reconfig_dev);
5501         if (rc)
5502                 return rc;
5503
5504         rc = bnxt_setup_int(bp);
5505         if (rc)
5506                 return rc;
5507
5508         rc = bnxt_request_int(bp);
5509         if (rc)
5510                 return rc;
5511
5512         rc = bnxt_init_ctx_mem(bp);
5513         if (rc) {
5514                 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5515                 return rc;
5516         }
5517
5518         return 0;
5519 }
5520
5521 static int
5522 bnxt_parse_devarg_accum_stats(__rte_unused const char *key,
5523                               const char *value, void *opaque_arg)
5524 {
5525         struct bnxt *bp = opaque_arg;
5526         unsigned long accum_stats;
5527         char *end = NULL;
5528
5529         if (!value || !opaque_arg) {
5530                 PMD_DRV_LOG(ERR,
5531                             "Invalid parameter passed to accum-stats devargs.\n");
5532                 return -EINVAL;
5533         }
5534
5535         accum_stats = strtoul(value, &end, 10);
5536         if (end == NULL || *end != '\0' ||
5537             (accum_stats == ULONG_MAX && errno == ERANGE)) {
5538                 PMD_DRV_LOG(ERR,
5539                             "Invalid parameter passed to accum-stats devargs.\n");
5540                 return -EINVAL;
5541         }
5542
5543         if (BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)) {
5544                 PMD_DRV_LOG(ERR,
5545                             "Invalid value passed to accum-stats devargs.\n");
5546                 return -EINVAL;
5547         }
5548
5549         if (accum_stats) {
5550                 bp->flags2 |= BNXT_FLAGS2_ACCUM_STATS_EN;
5551                 PMD_DRV_LOG(INFO, "Host-based accum-stats feature enabled.\n");
5552         } else {
5553                 bp->flags2 &= ~BNXT_FLAGS2_ACCUM_STATS_EN;
5554                 PMD_DRV_LOG(INFO, "Host-based accum-stats feature disabled.\n");
5555         }
5556
5557         return 0;
5558 }
5559
5560 static int
5561 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5562                              const char *value, void *opaque_arg)
5563 {
5564         struct bnxt *bp = opaque_arg;
5565         unsigned long flow_xstat;
5566         char *end = NULL;
5567
5568         if (!value || !opaque_arg) {
5569                 PMD_DRV_LOG(ERR,
5570                             "Invalid parameter passed to flow_xstat devarg.\n");
5571                 return -EINVAL;
5572         }
5573
5574         flow_xstat = strtoul(value, &end, 10);
5575         if (end == NULL || *end != '\0' ||
5576             (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5577                 PMD_DRV_LOG(ERR,
5578                             "Invalid parameter passed to flow_xstat devarg.\n");
5579                 return -EINVAL;
5580         }
5581
5582         if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5583                 PMD_DRV_LOG(ERR,
5584                             "Invalid value passed to flow_xstat devarg.\n");
5585                 return -EINVAL;
5586         }
5587
5588         bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5589         if (BNXT_FLOW_XSTATS_EN(bp))
5590                 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5591
5592         return 0;
5593 }
5594
5595 static int
5596 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5597                                         const char *value, void *opaque_arg)
5598 {
5599         struct bnxt *bp = opaque_arg;
5600         unsigned long max_num_kflows;
5601         char *end = NULL;
5602
5603         if (!value || !opaque_arg) {
5604                 PMD_DRV_LOG(ERR,
5605                         "Invalid parameter passed to max_num_kflows devarg.\n");
5606                 return -EINVAL;
5607         }
5608
5609         max_num_kflows = strtoul(value, &end, 10);
5610         if (end == NULL || *end != '\0' ||
5611                 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5612                 PMD_DRV_LOG(ERR,
5613                         "Invalid parameter passed to max_num_kflows devarg.\n");
5614                 return -EINVAL;
5615         }
5616
5617         if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5618                 PMD_DRV_LOG(ERR,
5619                         "Invalid value passed to max_num_kflows devarg.\n");
5620                 return -EINVAL;
5621         }
5622
5623         bp->max_num_kflows = max_num_kflows;
5624         if (bp->max_num_kflows)
5625                 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5626                                 max_num_kflows);
5627
5628         return 0;
5629 }
5630
5631 static int
5632 bnxt_parse_devarg_app_id(__rte_unused const char *key,
5633                                  const char *value, void *opaque_arg)
5634 {
5635         struct bnxt *bp = opaque_arg;
5636         unsigned long app_id;
5637         char *end = NULL;
5638
5639         if (!value || !opaque_arg) {
5640                 PMD_DRV_LOG(ERR,
5641                             "Invalid parameter passed to app-id "
5642                             "devargs.\n");
5643                 return -EINVAL;
5644         }
5645
5646         app_id = strtoul(value, &end, 10);
5647         if (end == NULL || *end != '\0' ||
5648             (app_id == ULONG_MAX && errno == ERANGE)) {
5649                 PMD_DRV_LOG(ERR,
5650                             "Invalid parameter passed to app_id "
5651                             "devargs.\n");
5652                 return -EINVAL;
5653         }
5654
5655         if (BNXT_DEVARG_APP_ID_INVALID(app_id)) {
5656                 PMD_DRV_LOG(ERR, "Invalid app-id(%d) devargs.\n",
5657                             (uint16_t)app_id);
5658                 return -EINVAL;
5659         }
5660
5661         bp->app_id = app_id;
5662         PMD_DRV_LOG(INFO, "app-id=%d feature enabled.\n", (uint16_t)app_id);
5663
5664         return 0;
5665 }
5666
5667 static int
5668 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5669                             const char *value, void *opaque_arg)
5670 {
5671         struct bnxt_representor *vfr_bp = opaque_arg;
5672         unsigned long rep_is_pf;
5673         char *end = NULL;
5674
5675         if (!value || !opaque_arg) {
5676                 PMD_DRV_LOG(ERR,
5677                             "Invalid parameter passed to rep_is_pf devargs.\n");
5678                 return -EINVAL;
5679         }
5680
5681         rep_is_pf = strtoul(value, &end, 10);
5682         if (end == NULL || *end != '\0' ||
5683             (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5684                 PMD_DRV_LOG(ERR,
5685                             "Invalid parameter passed to rep_is_pf devargs.\n");
5686                 return -EINVAL;
5687         }
5688
5689         if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5690                 PMD_DRV_LOG(ERR,
5691                             "Invalid value passed to rep_is_pf devargs.\n");
5692                 return -EINVAL;
5693         }
5694
5695         vfr_bp->flags |= rep_is_pf;
5696         if (BNXT_REP_PF(vfr_bp))
5697                 PMD_DRV_LOG(INFO, "PF representor\n");
5698         else
5699                 PMD_DRV_LOG(INFO, "VF representor\n");
5700
5701         return 0;
5702 }
5703
5704 static int
5705 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5706                                const char *value, void *opaque_arg)
5707 {
5708         struct bnxt_representor *vfr_bp = opaque_arg;
5709         unsigned long rep_based_pf;
5710         char *end = NULL;
5711
5712         if (!value || !opaque_arg) {
5713                 PMD_DRV_LOG(ERR,
5714                             "Invalid parameter passed to rep_based_pf "
5715                             "devargs.\n");
5716                 return -EINVAL;
5717         }
5718
5719         rep_based_pf = strtoul(value, &end, 10);
5720         if (end == NULL || *end != '\0' ||
5721             (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5722                 PMD_DRV_LOG(ERR,
5723                             "Invalid parameter passed to rep_based_pf "
5724                             "devargs.\n");
5725                 return -EINVAL;
5726         }
5727
5728         if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5729                 PMD_DRV_LOG(ERR,
5730                             "Invalid value passed to rep_based_pf devargs.\n");
5731                 return -EINVAL;
5732         }
5733
5734         vfr_bp->rep_based_pf = rep_based_pf;
5735         vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5736
5737         PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5738
5739         return 0;
5740 }
5741
5742 static int
5743 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5744                             const char *value, void *opaque_arg)
5745 {
5746         struct bnxt_representor *vfr_bp = opaque_arg;
5747         unsigned long rep_q_r2f;
5748         char *end = NULL;
5749
5750         if (!value || !opaque_arg) {
5751                 PMD_DRV_LOG(ERR,
5752                             "Invalid parameter passed to rep_q_r2f "
5753                             "devargs.\n");
5754                 return -EINVAL;
5755         }
5756
5757         rep_q_r2f = strtoul(value, &end, 10);
5758         if (end == NULL || *end != '\0' ||
5759             (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5760                 PMD_DRV_LOG(ERR,
5761                             "Invalid parameter passed to rep_q_r2f "
5762                             "devargs.\n");
5763                 return -EINVAL;
5764         }
5765
5766         if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5767                 PMD_DRV_LOG(ERR,
5768                             "Invalid value passed to rep_q_r2f devargs.\n");
5769                 return -EINVAL;
5770         }
5771
5772         vfr_bp->rep_q_r2f = rep_q_r2f;
5773         vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5774         PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5775
5776         return 0;
5777 }
5778
5779 static int
5780 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5781                             const char *value, void *opaque_arg)
5782 {
5783         struct bnxt_representor *vfr_bp = opaque_arg;
5784         unsigned long rep_q_f2r;
5785         char *end = NULL;
5786
5787         if (!value || !opaque_arg) {
5788                 PMD_DRV_LOG(ERR,
5789                             "Invalid parameter passed to rep_q_f2r "
5790                             "devargs.\n");
5791                 return -EINVAL;
5792         }
5793
5794         rep_q_f2r = strtoul(value, &end, 10);
5795         if (end == NULL || *end != '\0' ||
5796             (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5797                 PMD_DRV_LOG(ERR,
5798                             "Invalid parameter passed to rep_q_f2r "
5799                             "devargs.\n");
5800                 return -EINVAL;
5801         }
5802
5803         if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5804                 PMD_DRV_LOG(ERR,
5805                             "Invalid value passed to rep_q_f2r devargs.\n");
5806                 return -EINVAL;
5807         }
5808
5809         vfr_bp->rep_q_f2r = rep_q_f2r;
5810         vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5811         PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5812
5813         return 0;
5814 }
5815
5816 static int
5817 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5818                              const char *value, void *opaque_arg)
5819 {
5820         struct bnxt_representor *vfr_bp = opaque_arg;
5821         unsigned long rep_fc_r2f;
5822         char *end = NULL;
5823
5824         if (!value || !opaque_arg) {
5825                 PMD_DRV_LOG(ERR,
5826                             "Invalid parameter passed to rep_fc_r2f "
5827                             "devargs.\n");
5828                 return -EINVAL;
5829         }
5830
5831         rep_fc_r2f = strtoul(value, &end, 10);
5832         if (end == NULL || *end != '\0' ||
5833             (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5834                 PMD_DRV_LOG(ERR,
5835                             "Invalid parameter passed to rep_fc_r2f "
5836                             "devargs.\n");
5837                 return -EINVAL;
5838         }
5839
5840         if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5841                 PMD_DRV_LOG(ERR,
5842                             "Invalid value passed to rep_fc_r2f devargs.\n");
5843                 return -EINVAL;
5844         }
5845
5846         vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5847         vfr_bp->rep_fc_r2f = rep_fc_r2f;
5848         PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5849
5850         return 0;
5851 }
5852
5853 static int
5854 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5855                              const char *value, void *opaque_arg)
5856 {
5857         struct bnxt_representor *vfr_bp = opaque_arg;
5858         unsigned long rep_fc_f2r;
5859         char *end = NULL;
5860
5861         if (!value || !opaque_arg) {
5862                 PMD_DRV_LOG(ERR,
5863                             "Invalid parameter passed to rep_fc_f2r "
5864                             "devargs.\n");
5865                 return -EINVAL;
5866         }
5867
5868         rep_fc_f2r = strtoul(value, &end, 10);
5869         if (end == NULL || *end != '\0' ||
5870             (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5871                 PMD_DRV_LOG(ERR,
5872                             "Invalid parameter passed to rep_fc_f2r "
5873                             "devargs.\n");
5874                 return -EINVAL;
5875         }
5876
5877         if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5878                 PMD_DRV_LOG(ERR,
5879                             "Invalid value passed to rep_fc_f2r devargs.\n");
5880                 return -EINVAL;
5881         }
5882
5883         vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5884         vfr_bp->rep_fc_f2r = rep_fc_f2r;
5885         PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5886
5887         return 0;
5888 }
5889
5890 static int
5891 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5892 {
5893         struct rte_kvargs *kvlist;
5894         int ret;
5895
5896         if (devargs == NULL)
5897                 return 0;
5898
5899         kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5900         if (kvlist == NULL)
5901                 return -EINVAL;
5902
5903         /*
5904          * Handler for "flow_xstat" devarg.
5905          * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5906          */
5907         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5908                                  bnxt_parse_devarg_flow_xstat, bp);
5909         if (ret)
5910                 goto err;
5911
5912         /*
5913          * Handler for "accum-stats" devarg.
5914          * Invoked as for ex: "-a 0000:00:0d.0,accum-stats=1"
5915          */
5916         rte_kvargs_process(kvlist, BNXT_DEVARG_ACCUM_STATS,
5917                            bnxt_parse_devarg_accum_stats, bp);
5918         /*
5919          * Handler for "max_num_kflows" devarg.
5920          * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5921          */
5922         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5923                                  bnxt_parse_devarg_max_num_kflows, bp);
5924         if (ret)
5925                 goto err;
5926
5927 err:
5928         /*
5929          * Handler for "app-id" devarg.
5930          * Invoked as for ex: "-a 000:00:0d.0,app-id=1"
5931          */
5932         rte_kvargs_process(kvlist, BNXT_DEVARG_APP_ID,
5933                            bnxt_parse_devarg_app_id, bp);
5934
5935         rte_kvargs_free(kvlist);
5936         return ret;
5937 }
5938
5939 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5940 {
5941         int rc = 0;
5942
5943         if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5944                 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5945                 if (rc)
5946                         PMD_DRV_LOG(ERR,
5947                                     "Failed to alloc switch domain: %d\n", rc);
5948                 else
5949                         PMD_DRV_LOG(INFO,
5950                                     "Switch domain allocated %d\n",
5951                                     bp->switch_domain_id);
5952         }
5953
5954         return rc;
5955 }
5956
5957 /* Allocate and initialize various fields in bnxt struct that
5958  * need to be allocated/destroyed only once in the lifetime of the driver
5959  */
5960 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5961 {
5962         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5963         struct bnxt *bp = eth_dev->data->dev_private;
5964         int rc = 0;
5965
5966         bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5967
5968         if (bnxt_vf_pciid(pci_dev->id.device_id))
5969                 bp->flags |= BNXT_FLAG_VF;
5970
5971         if (bnxt_p5_device(pci_dev->id.device_id))
5972                 bp->flags |= BNXT_FLAG_CHIP_P5;
5973
5974         if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5975             pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5976             pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5977             pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5978                 bp->flags |= BNXT_FLAG_STINGRAY;
5979
5980         if (BNXT_TRUFLOW_EN(bp)) {
5981                 /* extra mbuf field is required to store CFA code from mark */
5982                 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5983                         .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5984                         .size = sizeof(bnxt_cfa_code_dynfield_t),
5985                         .align = __alignof__(bnxt_cfa_code_dynfield_t),
5986                 };
5987                 bnxt_cfa_code_dynfield_offset =
5988                         rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5989                 if (bnxt_cfa_code_dynfield_offset < 0) {
5990                         PMD_DRV_LOG(ERR,
5991                             "Failed to register mbuf field for TruFlow mark\n");
5992                         return -rte_errno;
5993                 }
5994         }
5995
5996         rc = bnxt_map_pci_bars(eth_dev);
5997         if (rc) {
5998                 PMD_DRV_LOG(ERR,
5999                             "Failed to initialize board rc: %x\n", rc);
6000                 return rc;
6001         }
6002
6003         rc = bnxt_alloc_pf_info(bp);
6004         if (rc)
6005                 return rc;
6006
6007         rc = bnxt_alloc_link_info(bp);
6008         if (rc)
6009                 return rc;
6010
6011         rc = bnxt_alloc_parent_info(bp);
6012         if (rc)
6013                 return rc;
6014
6015         rc = bnxt_alloc_hwrm_resources(bp);
6016         if (rc) {
6017                 PMD_DRV_LOG(ERR,
6018                             "Failed to allocate response buffer rc: %x\n", rc);
6019                 return rc;
6020         }
6021         rc = bnxt_alloc_leds_info(bp);
6022         if (rc)
6023                 return rc;
6024
6025         rc = bnxt_alloc_cos_queues(bp);
6026         if (rc)
6027                 return rc;
6028
6029         rc = bnxt_init_locks(bp);
6030         if (rc)
6031                 return rc;
6032
6033         rc = bnxt_alloc_switch_domain(bp);
6034         if (rc)
6035                 return rc;
6036
6037         return rc;
6038 }
6039
6040 static int
6041 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
6042 {
6043         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
6044         static int version_printed;
6045         struct bnxt *bp;
6046         int rc;
6047
6048         if (version_printed++ == 0)
6049                 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
6050
6051         eth_dev->dev_ops = &bnxt_dev_ops;
6052         eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
6053         eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
6054         eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
6055         eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
6056         eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
6057
6058         /*
6059          * For secondary processes, we don't initialise any further
6060          * as primary has already done this work.
6061          */
6062         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6063                 return 0;
6064
6065         rte_eth_copy_pci_info(eth_dev, pci_dev);
6066         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
6067
6068         bp = eth_dev->data->dev_private;
6069
6070         /* Parse dev arguments passed on when starting the DPDK application. */
6071         rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs);
6072         if (rc)
6073                 goto error_free;
6074
6075         rc = bnxt_drv_init(eth_dev);
6076         if (rc)
6077                 goto error_free;
6078
6079         rc = bnxt_init_resources(bp, false);
6080         if (rc)
6081                 goto error_free;
6082
6083         rc = bnxt_alloc_stats_mem(bp);
6084         if (rc)
6085                 goto error_free;
6086
6087         PMD_DRV_LOG(INFO,
6088                     "Found %s device at mem %" PRIX64 ", node addr %pM\n",
6089                     DRV_MODULE_NAME,
6090                     pci_dev->mem_resource[0].phys_addr,
6091                     pci_dev->mem_resource[0].addr);
6092
6093         return 0;
6094
6095 error_free:
6096         bnxt_dev_uninit(eth_dev);
6097         return rc;
6098 }
6099
6100
6101 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
6102 {
6103         if (!ctx)
6104                 return;
6105
6106         if (ctx->va)
6107                 rte_free(ctx->va);
6108
6109         ctx->va = NULL;
6110         ctx->dma = RTE_BAD_IOVA;
6111         ctx->ctx_id = BNXT_CTX_VAL_INVAL;
6112 }
6113
6114 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
6115 {
6116         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
6117                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6118                                   bp->flow_stat->rx_fc_out_tbl.ctx_id,
6119                                   bp->flow_stat->max_fc,
6120                                   false);
6121
6122         bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
6123                                   CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
6124                                   bp->flow_stat->tx_fc_out_tbl.ctx_id,
6125                                   bp->flow_stat->max_fc,
6126                                   false);
6127
6128         if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6129                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
6130         bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6131
6132         if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6133                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
6134         bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6135
6136         if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6137                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
6138         bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6139
6140         if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
6141                 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
6142         bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
6143 }
6144
6145 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
6146 {
6147         bnxt_unregister_fc_ctx_mem(bp);
6148
6149         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
6150         bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
6151         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
6152         bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
6153 }
6154
6155 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
6156 {
6157         if (BNXT_FLOW_XSTATS_EN(bp))
6158                 bnxt_uninit_fc_ctx_mem(bp);
6159 }
6160
6161 static void
6162 bnxt_free_error_recovery_info(struct bnxt *bp)
6163 {
6164         rte_free(bp->recovery_info);
6165         bp->recovery_info = NULL;
6166         bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
6167 }
6168
6169 static int
6170 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
6171 {
6172         int rc;
6173
6174         bnxt_free_int(bp);
6175         bnxt_free_mem(bp, reconfig_dev);
6176
6177         bnxt_hwrm_func_buf_unrgtr(bp);
6178         if (bp->pf != NULL) {
6179                 rte_free(bp->pf->vf_req_buf);
6180                 bp->pf->vf_req_buf = NULL;
6181         }
6182
6183         rc = bnxt_hwrm_func_driver_unregister(bp);
6184         bp->flags &= ~BNXT_FLAG_REGISTERED;
6185         bnxt_free_ctx_mem(bp);
6186         if (!reconfig_dev) {
6187                 bnxt_free_hwrm_resources(bp);
6188                 bnxt_free_error_recovery_info(bp);
6189         }
6190
6191         bnxt_uninit_ctx_mem(bp);
6192
6193         bnxt_free_flow_stats_info(bp);
6194         if (bp->rep_info != NULL)
6195                 bnxt_free_switch_domain(bp);
6196         bnxt_free_rep_info(bp);
6197         rte_free(bp->ptp_cfg);
6198         bp->ptp_cfg = NULL;
6199         return rc;
6200 }
6201
6202 static int
6203 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
6204 {
6205         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
6206                 return -EPERM;
6207
6208         PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
6209
6210         if (eth_dev->state != RTE_ETH_DEV_UNUSED)
6211                 bnxt_dev_close_op(eth_dev);
6212
6213         return 0;
6214 }
6215
6216 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
6217 {
6218         struct bnxt *bp = eth_dev->data->dev_private;
6219         struct rte_eth_dev *vf_rep_eth_dev;
6220         int ret = 0, i;
6221
6222         if (!bp)
6223                 return -EINVAL;
6224
6225         for (i = 0; i < bp->num_reps; i++) {
6226                 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
6227                 if (!vf_rep_eth_dev)
6228                         continue;
6229                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
6230                             vf_rep_eth_dev->data->port_id);
6231                 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
6232         }
6233         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
6234                     eth_dev->data->port_id);
6235         ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
6236
6237         return ret;
6238 }
6239
6240 static void bnxt_free_rep_info(struct bnxt *bp)
6241 {
6242         rte_free(bp->rep_info);
6243         bp->rep_info = NULL;
6244         rte_free(bp->cfa_code_map);
6245         bp->cfa_code_map = NULL;
6246 }
6247
6248 static int bnxt_init_rep_info(struct bnxt *bp)
6249 {
6250         int i = 0, rc;
6251
6252         if (bp->rep_info)
6253                 return 0;
6254
6255         bp->rep_info = rte_zmalloc("bnxt_rep_info",
6256                                    sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
6257                                    0);
6258         if (!bp->rep_info) {
6259                 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
6260                 return -ENOMEM;
6261         }
6262         bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
6263                                        sizeof(*bp->cfa_code_map) *
6264                                        BNXT_MAX_CFA_CODE, 0);
6265         if (!bp->cfa_code_map) {
6266                 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
6267                 bnxt_free_rep_info(bp);
6268                 return -ENOMEM;
6269         }
6270
6271         for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
6272                 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
6273
6274         rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
6275         if (rc) {
6276                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
6277                 bnxt_free_rep_info(bp);
6278                 return rc;
6279         }
6280
6281         rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
6282         if (rc) {
6283                 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
6284                 bnxt_free_rep_info(bp);
6285                 return rc;
6286         }
6287
6288         return rc;
6289 }
6290
6291 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
6292                                struct rte_eth_devargs *eth_da,
6293                                struct rte_eth_dev *backing_eth_dev,
6294                                const char *dev_args)
6295 {
6296         struct rte_eth_dev *vf_rep_eth_dev;
6297         char name[RTE_ETH_NAME_MAX_LEN];
6298         struct bnxt *backing_bp;
6299         uint16_t num_rep;
6300         int i, ret = 0;
6301         struct rte_kvargs *kvlist = NULL;
6302
6303         if (eth_da->type == RTE_ETH_REPRESENTOR_NONE)
6304                 return 0;
6305         if (eth_da->type != RTE_ETH_REPRESENTOR_VF) {
6306                 PMD_DRV_LOG(ERR, "unsupported representor type %d\n",
6307                             eth_da->type);
6308                 return -ENOTSUP;
6309         }
6310         num_rep = eth_da->nb_representor_ports;
6311         if (num_rep > BNXT_MAX_VF_REPS) {
6312                 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
6313                             num_rep, BNXT_MAX_VF_REPS);
6314                 return -EINVAL;
6315         }
6316
6317         if (num_rep >= RTE_MAX_ETHPORTS) {
6318                 PMD_DRV_LOG(ERR,
6319                             "nb_representor_ports = %d > %d MAX ETHPORTS\n",
6320                             num_rep, RTE_MAX_ETHPORTS);
6321                 return -EINVAL;
6322         }
6323
6324         backing_bp = backing_eth_dev->data->dev_private;
6325
6326         if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
6327                 PMD_DRV_LOG(ERR,
6328                             "Not a PF or trusted VF. No Representor support\n");
6329                 /* Returning an error is not an option.
6330                  * Applications are not handling this correctly
6331                  */
6332                 return 0;
6333         }
6334
6335         if (bnxt_init_rep_info(backing_bp))
6336                 return 0;
6337
6338         for (i = 0; i < num_rep; i++) {
6339                 struct bnxt_representor representor = {
6340                         .vf_id = eth_da->representor_ports[i],
6341                         .switch_domain_id = backing_bp->switch_domain_id,
6342                         .parent_dev = backing_eth_dev
6343                 };
6344
6345                 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
6346                         PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
6347                                     representor.vf_id, BNXT_MAX_VF_REPS);
6348                         continue;
6349                 }
6350
6351                 /* representor port net_bdf_port */
6352                 snprintf(name, sizeof(name), "net_%s_representor_%d",
6353                          pci_dev->device.name, eth_da->representor_ports[i]);
6354
6355                 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
6356                 if (kvlist) {
6357                         /*
6358                          * Handler for "rep_is_pf" devarg.
6359                          * Invoked as for ex: "-a 000:00:0d.0,
6360                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6361                          */
6362                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
6363                                                  bnxt_parse_devarg_rep_is_pf,
6364                                                  (void *)&representor);
6365                         if (ret) {
6366                                 ret = -EINVAL;
6367                                 goto err;
6368                         }
6369                         /*
6370                          * Handler for "rep_based_pf" devarg.
6371                          * Invoked as for ex: "-a 000:00:0d.0,
6372                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6373                          */
6374                         ret = rte_kvargs_process(kvlist,
6375                                                  BNXT_DEVARG_REP_BASED_PF,
6376                                                  bnxt_parse_devarg_rep_based_pf,
6377                                                  (void *)&representor);
6378                         if (ret) {
6379                                 ret = -EINVAL;
6380                                 goto err;
6381                         }
6382                         /*
6383                          * Handler for "rep_based_pf" devarg.
6384                          * Invoked as for ex: "-a 000:00:0d.0,
6385                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6386                          */
6387                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
6388                                                  bnxt_parse_devarg_rep_q_r2f,
6389                                                  (void *)&representor);
6390                         if (ret) {
6391                                 ret = -EINVAL;
6392                                 goto err;
6393                         }
6394                         /*
6395                          * Handler for "rep_based_pf" devarg.
6396                          * Invoked as for ex: "-a 000:00:0d.0,
6397                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6398                          */
6399                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
6400                                                  bnxt_parse_devarg_rep_q_f2r,
6401                                                  (void *)&representor);
6402                         if (ret) {
6403                                 ret = -EINVAL;
6404                                 goto err;
6405                         }
6406                         /*
6407                          * Handler for "rep_based_pf" devarg.
6408                          * Invoked as for ex: "-a 000:00:0d.0,
6409                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6410                          */
6411                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
6412                                                  bnxt_parse_devarg_rep_fc_r2f,
6413                                                  (void *)&representor);
6414                         if (ret) {
6415                                 ret = -EINVAL;
6416                                 goto err;
6417                         }
6418                         /*
6419                          * Handler for "rep_based_pf" devarg.
6420                          * Invoked as for ex: "-a 000:00:0d.0,
6421                          * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
6422                          */
6423                         ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
6424                                                  bnxt_parse_devarg_rep_fc_f2r,
6425                                                  (void *)&representor);
6426                         if (ret) {
6427                                 ret = -EINVAL;
6428                                 goto err;
6429                         }
6430                 }
6431
6432                 ret = rte_eth_dev_create(&pci_dev->device, name,
6433                                          sizeof(struct bnxt_representor),
6434                                          NULL, NULL,
6435                                          bnxt_representor_init,
6436                                          &representor);
6437                 if (ret) {
6438                         PMD_DRV_LOG(ERR, "failed to create bnxt vf "
6439                                     "representor %s.", name);
6440                         goto err;
6441                 }
6442
6443                 vf_rep_eth_dev = rte_eth_dev_allocated(name);
6444                 if (!vf_rep_eth_dev) {
6445                         PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
6446                                     " for VF-Rep: %s.", name);
6447                         ret = -ENODEV;
6448                         goto err;
6449                 }
6450
6451                 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6452                             backing_eth_dev->data->port_id);
6453                 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6454                                                          vf_rep_eth_dev;
6455                 backing_bp->num_reps++;
6456
6457         }
6458
6459         rte_kvargs_free(kvlist);
6460         return 0;
6461
6462 err:
6463         /* If num_rep > 1, then rollback already created
6464          * ports, since we'll be failing the probe anyway
6465          */
6466         if (num_rep > 1)
6467                 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6468         rte_errno = -ret;
6469         rte_kvargs_free(kvlist);
6470
6471         return ret;
6472 }
6473
6474 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6475                           struct rte_pci_device *pci_dev)
6476 {
6477         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6478         struct rte_eth_dev *backing_eth_dev;
6479         uint16_t num_rep;
6480         int ret = 0;
6481
6482         if (pci_dev->device.devargs) {
6483                 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6484                                             &eth_da);
6485                 if (ret)
6486                         return ret;
6487         }
6488
6489         num_rep = eth_da.nb_representor_ports;
6490         PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6491                     num_rep);
6492
6493         /* We could come here after first level of probe is already invoked
6494          * as part of an application bringup(OVS-DPDK vswitchd), so first check
6495          * for already allocated eth_dev for the backing device (PF/Trusted VF)
6496          */
6497         backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6498         if (backing_eth_dev == NULL) {
6499                 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6500                                          sizeof(struct bnxt),
6501                                          eth_dev_pci_specific_init, pci_dev,
6502                                          bnxt_dev_init, NULL);
6503
6504                 if (ret || !num_rep)
6505                         return ret;
6506
6507                 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6508         }
6509         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6510                     backing_eth_dev->data->port_id);
6511
6512         if (!num_rep)
6513                 return ret;
6514
6515         /* probe representor ports now */
6516         ret = bnxt_rep_port_probe(pci_dev, &eth_da, backing_eth_dev,
6517                                   pci_dev->device.devargs->args);
6518
6519         return ret;
6520 }
6521
6522 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6523 {
6524         struct rte_eth_dev *eth_dev;
6525
6526         eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6527         if (!eth_dev)
6528                 return 0; /* Invoked typically only by OVS-DPDK, by the
6529                            * time it comes here the eth_dev is already
6530                            * deleted by rte_eth_dev_close(), so returning
6531                            * +ve value will at least help in proper cleanup
6532                            */
6533
6534         PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6535         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6536                 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6537                         return rte_eth_dev_destroy(eth_dev,
6538                                                    bnxt_representor_uninit);
6539                 else
6540                         return rte_eth_dev_destroy(eth_dev,
6541                                                    bnxt_dev_uninit);
6542         } else {
6543                 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6544         }
6545 }
6546
6547 static struct rte_pci_driver bnxt_rte_pmd = {
6548         .id_table = bnxt_pci_id_map,
6549         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6550                         RTE_PCI_DRV_INTR_RMV |
6551                         RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6552                                                   * and OVS-DPDK
6553                                                   */
6554         .probe = bnxt_pci_probe,
6555         .remove = bnxt_pci_remove,
6556 };
6557
6558 static bool
6559 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6560 {
6561         if (strcmp(dev->device->driver->name, drv->driver.name))
6562                 return false;
6563
6564         return true;
6565 }
6566
6567 bool is_bnxt_supported(struct rte_eth_dev *dev)
6568 {
6569         return is_device_supported(dev, &bnxt_rte_pmd);
6570 }
6571
6572 RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE);
6573 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6574 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6575 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");