1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2021 Broadcom
10 #include <ethdev_driver.h>
11 #include <ethdev_pci.h>
12 #include <rte_malloc.h>
13 #include <rte_cycles.h>
14 #include <rte_alarm.h>
15 #include <rte_kvargs.h>
19 #include "bnxt_filter.h"
20 #include "bnxt_hwrm.h"
22 #include "bnxt_reps.h"
23 #include "bnxt_ring.h"
26 #include "bnxt_stats.h"
29 #include "bnxt_vnic.h"
30 #include "hsi_struct_def_dpdk.h"
31 #include "bnxt_nvm_defs.h"
32 #include "bnxt_tf_common.h"
33 #include "ulp_flow_db.h"
34 #include "rte_pmd_bnxt.h"
36 #define DRV_MODULE_NAME "bnxt"
37 static const char bnxt_version[] =
38 "Broadcom NetXtreme driver " DRV_MODULE_NAME;
41 * The set of PCI devices this driver supports
43 static const struct rte_pci_id bnxt_pci_id_map[] = {
44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) },
48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) },
49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) },
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) },
51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) },
52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) },
53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) },
54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) },
55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) },
56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) },
57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) },
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) },
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) },
66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) },
67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) },
68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) },
69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) },
70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) },
71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) },
72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) },
73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) },
74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) },
75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) },
76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) },
77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) },
78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) },
79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) },
80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) },
81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) },
82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) },
83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) },
84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) },
85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) },
86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) },
87 { .vendor_id = 0, /* sentinel */ },
90 #define BNXT_DEVARG_TRUFLOW "host-based-truflow"
91 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat"
92 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows"
93 #define BNXT_DEVARG_REPRESENTOR "representor"
94 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf"
95 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf"
96 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f"
97 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r"
98 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f"
99 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r"
101 static const char *const bnxt_dev_args[] = {
102 BNXT_DEVARG_REPRESENTOR,
104 BNXT_DEVARG_FLOW_XSTAT,
105 BNXT_DEVARG_MAX_NUM_KFLOWS,
106 BNXT_DEVARG_REP_BASED_PF,
107 BNXT_DEVARG_REP_IS_PF,
108 BNXT_DEVARG_REP_Q_R2F,
109 BNXT_DEVARG_REP_Q_F2R,
110 BNXT_DEVARG_REP_FC_R2F,
111 BNXT_DEVARG_REP_FC_F2R,
116 * truflow == false to disable the feature
117 * truflow == true to enable the feature
119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1)
122 * flow_xstat == false to disable the feature
123 * flow_xstat == true to enable the feature
125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1)
128 * rep_is_pf == false to indicate VF representor
129 * rep_is_pf == true to indicate PF representor
131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1)
134 * rep_based_pf == Physical index of the PF
136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15)
138 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction
140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3)
143 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction
145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3)
148 * rep_fc_r2f == Flow control for the representor to endpoint direction
150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1)
153 * rep_fc_f2r == Flow control for the endpoint to representor direction
155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1)
157 int bnxt_cfa_code_dynfield_offset = -1;
160 * max_num_kflows must be >= 32
161 * and must be a power-of-2 supported value
162 * return: 1 -> invalid
165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows)
167 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows))
172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
176 static void bnxt_cancel_fw_health_check(struct bnxt *bp);
177 static int bnxt_restore_vlan_filters(struct bnxt *bp);
178 static void bnxt_dev_recover(void *arg);
179 static void bnxt_free_error_recovery_info(struct bnxt *bp);
180 static void bnxt_free_rep_info(struct bnxt *bp);
182 int is_bnxt_in_error(struct bnxt *bp)
184 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
186 if (bp->flags & BNXT_FLAG_FW_RESET)
192 /***********************/
195 * High level utility functions
198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
200 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings,
201 BNXT_RSS_TBL_SIZE_P5);
203 if (!BNXT_CHIP_P5(bp))
206 return RTE_ALIGN_MUL_CEIL(num_rss_rings,
207 BNXT_RSS_ENTRIES_PER_CTX_P5) /
208 BNXT_RSS_ENTRIES_PER_CTX_P5;
211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp)
213 if (!BNXT_CHIP_P5(bp))
214 return HW_HASH_INDEX_SIZE;
216 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5;
219 static void bnxt_free_parent_info(struct bnxt *bp)
221 rte_free(bp->parent);
224 static void bnxt_free_pf_info(struct bnxt *bp)
229 static void bnxt_free_link_info(struct bnxt *bp)
231 rte_free(bp->link_info);
234 static void bnxt_free_leds_info(struct bnxt *bp)
243 static void bnxt_free_flow_stats_info(struct bnxt *bp)
245 rte_free(bp->flow_stat);
246 bp->flow_stat = NULL;
249 static void bnxt_free_cos_queues(struct bnxt *bp)
251 rte_free(bp->rx_cos_queue);
252 rte_free(bp->tx_cos_queue);
255 static void bnxt_free_mem(struct bnxt *bp, bool reconfig)
257 bnxt_free_filter_mem(bp);
258 bnxt_free_vnic_attributes(bp);
259 bnxt_free_vnic_mem(bp);
261 /* tx/rx rings are configured as part of *_queue_setup callbacks.
262 * If the number of rings change across fw update,
263 * we don't have much choice except to warn the user.
267 bnxt_free_tx_rings(bp);
268 bnxt_free_rx_rings(bp);
270 bnxt_free_async_cp_ring(bp);
271 bnxt_free_rxtx_nq_ring(bp);
273 rte_free(bp->grp_info);
277 static int bnxt_alloc_parent_info(struct bnxt *bp)
279 bp->parent = rte_zmalloc("bnxt_parent_info",
280 sizeof(struct bnxt_parent_info), 0);
281 if (bp->parent == NULL)
287 static int bnxt_alloc_pf_info(struct bnxt *bp)
289 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0);
296 static int bnxt_alloc_link_info(struct bnxt *bp)
299 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0);
300 if (bp->link_info == NULL)
306 static int bnxt_alloc_leds_info(struct bnxt *bp)
311 bp->leds = rte_zmalloc("bnxt_leds",
312 BNXT_MAX_LED * sizeof(struct bnxt_led_info),
314 if (bp->leds == NULL)
320 static int bnxt_alloc_cos_queues(struct bnxt *bp)
323 rte_zmalloc("bnxt_rx_cosq",
324 BNXT_COS_QUEUE_COUNT *
325 sizeof(struct bnxt_cos_queue_info),
327 if (bp->rx_cos_queue == NULL)
331 rte_zmalloc("bnxt_tx_cosq",
332 BNXT_COS_QUEUE_COUNT *
333 sizeof(struct bnxt_cos_queue_info),
335 if (bp->tx_cos_queue == NULL)
341 static int bnxt_alloc_flow_stats_info(struct bnxt *bp)
343 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat",
344 sizeof(struct bnxt_flow_stat_info), 0);
345 if (bp->flow_stat == NULL)
351 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
355 rc = bnxt_alloc_ring_grps(bp);
359 rc = bnxt_alloc_async_ring_struct(bp);
363 rc = bnxt_alloc_vnic_mem(bp);
367 rc = bnxt_alloc_vnic_attributes(bp);
371 rc = bnxt_alloc_filter_mem(bp);
375 rc = bnxt_alloc_async_cp_ring(bp);
379 rc = bnxt_alloc_rxtx_nq_ring(bp);
383 if (BNXT_FLOW_XSTATS_EN(bp)) {
384 rc = bnxt_alloc_flow_stats_info(bp);
392 bnxt_free_mem(bp, reconfig);
396 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id)
398 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
399 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
400 uint64_t rx_offloads = dev_conf->rxmode.offloads;
401 struct bnxt_rx_queue *rxq;
405 rc = bnxt_vnic_grp_alloc(bp, vnic);
409 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
410 vnic_id, vnic, vnic->fw_grp_ids);
412 rc = bnxt_hwrm_vnic_alloc(bp, vnic);
416 /* Alloc RSS context only if RSS mode is enabled */
417 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) {
418 int j, nr_ctxs = bnxt_rss_ctxts(bp);
420 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) {
421 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n",
422 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5);
424 "Only queues 0-%d will be in RSS table\n",
425 BNXT_RSS_TBL_SIZE_P5 - 1);
429 for (j = 0; j < nr_ctxs; j++) {
430 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j);
436 "HWRM vnic %d ctx %d alloc failure rc: %x\n",
440 vnic->num_lb_ctxts = nr_ctxs;
444 * Firmware sets pf pair in default vnic cfg. If the VLAN strip
445 * setting is not available at this time, it will not be
446 * configured correctly in the CFA.
448 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
449 vnic->vlan_strip = true;
451 vnic->vlan_strip = false;
453 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
457 rc = bnxt_set_hwrm_vnic_filters(bp, vnic);
461 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
462 rxq = bp->eth_dev->data->rx_queues[j];
465 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n",
466 j, rxq->vnic, rxq->vnic->fw_grp_ids);
468 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start)
469 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
471 vnic->rx_queue_cnt++;
474 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt);
476 rc = bnxt_vnic_rss_configure(bp, vnic);
480 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
482 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO)
483 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1);
485 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0);
489 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n",
494 static int bnxt_register_fc_ctx_mem(struct bnxt *bp)
498 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma,
499 &bp->flow_stat->rx_fc_in_tbl.ctx_id);
504 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p"
505 " rx_fc_in_tbl.ctx_id = %d\n",
506 bp->flow_stat->rx_fc_in_tbl.va,
507 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma),
508 bp->flow_stat->rx_fc_in_tbl.ctx_id);
510 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma,
511 &bp->flow_stat->rx_fc_out_tbl.ctx_id);
516 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p"
517 " rx_fc_out_tbl.ctx_id = %d\n",
518 bp->flow_stat->rx_fc_out_tbl.va,
519 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma),
520 bp->flow_stat->rx_fc_out_tbl.ctx_id);
522 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma,
523 &bp->flow_stat->tx_fc_in_tbl.ctx_id);
528 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p"
529 " tx_fc_in_tbl.ctx_id = %d\n",
530 bp->flow_stat->tx_fc_in_tbl.va,
531 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma),
532 bp->flow_stat->tx_fc_in_tbl.ctx_id);
534 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma,
535 &bp->flow_stat->tx_fc_out_tbl.ctx_id);
540 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p"
541 " tx_fc_out_tbl.ctx_id = %d\n",
542 bp->flow_stat->tx_fc_out_tbl.va,
543 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma),
544 bp->flow_stat->tx_fc_out_tbl.ctx_id);
546 memset(bp->flow_stat->rx_fc_out_tbl.va,
548 bp->flow_stat->rx_fc_out_tbl.size);
549 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
550 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
551 bp->flow_stat->rx_fc_out_tbl.ctx_id,
552 bp->flow_stat->max_fc,
557 memset(bp->flow_stat->tx_fc_out_tbl.va,
559 bp->flow_stat->tx_fc_out_tbl.size);
560 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
561 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
562 bp->flow_stat->tx_fc_out_tbl.ctx_id,
563 bp->flow_stat->max_fc,
569 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size,
570 struct bnxt_ctx_mem_buf_info *ctx)
575 ctx->va = rte_zmalloc(type, size, 0);
578 rte_mem_lock_page(ctx->va);
580 ctx->dma = rte_mem_virt2iova(ctx->va);
581 if (ctx->dma == RTE_BAD_IOVA)
587 static int bnxt_init_fc_ctx_mem(struct bnxt *bp)
589 struct rte_pci_device *pdev = bp->pdev;
590 char type[RTE_MEMZONE_NAMESIZE];
594 max_fc = bp->flow_stat->max_fc;
596 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
597 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
598 /* 4 bytes for each counter-id */
599 rc = bnxt_alloc_ctx_mem_buf(type,
601 &bp->flow_stat->rx_fc_in_tbl);
605 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
606 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
607 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
608 rc = bnxt_alloc_ctx_mem_buf(type,
610 &bp->flow_stat->rx_fc_out_tbl);
614 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain,
615 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
616 /* 4 bytes for each counter-id */
617 rc = bnxt_alloc_ctx_mem_buf(type,
619 &bp->flow_stat->tx_fc_in_tbl);
623 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain,
624 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
625 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */
626 rc = bnxt_alloc_ctx_mem_buf(type,
628 &bp->flow_stat->tx_fc_out_tbl);
632 rc = bnxt_register_fc_ctx_mem(bp);
637 static int bnxt_init_ctx_mem(struct bnxt *bp)
641 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) ||
642 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) ||
643 !BNXT_FLOW_XSTATS_EN(bp))
646 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc);
650 rc = bnxt_init_fc_ctx_mem(bp);
655 static int bnxt_update_phy_setting(struct bnxt *bp)
657 struct rte_eth_link new;
660 rc = bnxt_get_hwrm_link_config(bp, &new);
662 PMD_DRV_LOG(ERR, "Failed to get link settings\n");
667 * On BCM957508-N2100 adapters, FW will not allow any user other
668 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call
669 * always returns link up. Force phy update always in that case.
671 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) {
672 rc = bnxt_set_hwrm_link_config(bp, true);
674 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n");
682 static int bnxt_start_nic(struct bnxt *bp)
684 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev);
685 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
686 uint32_t intr_vector = 0;
687 uint32_t queue_id, base = BNXT_MISC_VEC_ID;
688 uint32_t vec = BNXT_MISC_VEC_ID;
692 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) {
693 bp->eth_dev->data->dev_conf.rxmode.offloads |=
694 DEV_RX_OFFLOAD_JUMBO_FRAME;
695 bp->flags |= BNXT_FLAG_JUMBO;
697 bp->eth_dev->data->dev_conf.rxmode.offloads &=
698 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
699 bp->flags &= ~BNXT_FLAG_JUMBO;
702 /* THOR does not support ring groups.
703 * But we will use the array to save RSS context IDs.
705 if (BNXT_CHIP_P5(bp))
706 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5;
708 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp);
710 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc);
714 rc = bnxt_alloc_hwrm_rings(bp);
716 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc);
720 rc = bnxt_alloc_all_hwrm_ring_grps(bp);
722 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc);
726 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
729 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
730 if (bp->rx_cos_queue[i].id != 0xff) {
731 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
735 "Num pools more than FW profile\n");
739 vnic->cos_queue_id = bp->rx_cos_queue[i].id;
745 rc = bnxt_mq_rx_configure(bp);
747 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
752 rc = bnxt_setup_one_vnic(bp, 0);
755 /* VNIC configuration */
756 if (BNXT_RFS_NEEDS_VNIC(bp)) {
757 for (i = 1; i < bp->nr_vnics; i++) {
758 rc = bnxt_setup_one_vnic(bp, i);
764 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL);
767 "HWRM cfa l2 rx mask failure rc: %x\n", rc);
771 /* check and configure queue intr-vector mapping */
772 if ((rte_intr_cap_multiple(intr_handle) ||
773 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) &&
774 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) {
775 intr_vector = bp->eth_dev->data->nb_rx_queues;
776 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector);
777 if (intr_vector > bp->rx_cp_nr_rings) {
778 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
782 rc = rte_intr_efd_enable(intr_handle, intr_vector);
787 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
788 intr_handle->intr_vec =
789 rte_zmalloc("intr_vec",
790 bp->eth_dev->data->nb_rx_queues *
792 if (intr_handle->intr_vec == NULL) {
793 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues"
794 " intr_vec", bp->eth_dev->data->nb_rx_queues);
798 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p "
799 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n",
800 intr_handle->intr_vec, intr_handle->nb_efd,
801 intr_handle->max_intr);
802 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues;
804 intr_handle->intr_vec[queue_id] =
805 vec + BNXT_RX_VEC_START;
806 if (vec < base + intr_handle->nb_efd - 1)
811 /* enable uio/vfio intr/eventfd mapping */
812 rc = rte_intr_enable(intr_handle);
813 #ifndef RTE_EXEC_ENV_FREEBSD
814 /* In FreeBSD OS, nic_uio driver does not support interrupts */
819 rc = bnxt_update_phy_setting(bp);
823 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0);
825 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n");
830 rte_free(intr_handle->intr_vec);
832 rte_intr_efd_disable(intr_handle);
834 /* Some of the error status returned by FW may not be from errno.h */
841 static int bnxt_shutdown_nic(struct bnxt *bp)
843 bnxt_free_all_hwrm_resources(bp);
844 bnxt_free_all_filters(bp);
845 bnxt_free_all_vnics(bp);
850 * Device configuration and status function
853 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp)
855 uint32_t link_speed = bp->link_info->support_speeds;
856 uint32_t speed_capa = 0;
858 /* If PAM4 is configured, use PAM4 supported speed */
859 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0)
860 link_speed = bp->link_info->support_pam4_speeds;
862 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB)
863 speed_capa |= ETH_LINK_SPEED_100M;
864 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD)
865 speed_capa |= ETH_LINK_SPEED_100M_HD;
866 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB)
867 speed_capa |= ETH_LINK_SPEED_1G;
868 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB)
869 speed_capa |= ETH_LINK_SPEED_2_5G;
870 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB)
871 speed_capa |= ETH_LINK_SPEED_10G;
872 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB)
873 speed_capa |= ETH_LINK_SPEED_20G;
874 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB)
875 speed_capa |= ETH_LINK_SPEED_25G;
876 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB)
877 speed_capa |= ETH_LINK_SPEED_40G;
878 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB)
879 speed_capa |= ETH_LINK_SPEED_50G;
880 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB)
881 speed_capa |= ETH_LINK_SPEED_100G;
882 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G)
883 speed_capa |= ETH_LINK_SPEED_50G;
884 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G)
885 speed_capa |= ETH_LINK_SPEED_100G;
886 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G)
887 speed_capa |= ETH_LINK_SPEED_200G;
889 if (bp->link_info->auto_mode ==
890 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE)
891 speed_capa |= ETH_LINK_SPEED_FIXED;
893 speed_capa |= ETH_LINK_SPEED_AUTONEG;
898 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
899 struct rte_eth_dev_info *dev_info)
901 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
902 struct bnxt *bp = eth_dev->data->dev_private;
903 uint16_t max_vnics, i, j, vpool, vrxq;
904 unsigned int max_rx_rings;
907 rc = is_bnxt_in_error(bp);
912 dev_info->max_mac_addrs = bp->max_l2_ctx;
913 dev_info->max_hash_mac_addrs = 0;
915 /* PF/VF specifics */
917 dev_info->max_vfs = pdev->max_vfs;
919 max_rx_rings = bnxt_max_rings(bp);
920 /* For the sake of symmetry, max_rx_queues = max_tx_queues */
921 dev_info->max_rx_queues = max_rx_rings;
922 dev_info->max_tx_queues = max_rx_rings;
923 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp);
924 dev_info->hash_key_size = 40;
925 max_vnics = bp->max_vnics;
928 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
929 dev_info->max_mtu = BNXT_MAX_MTU;
931 /* Fast path specifics */
932 dev_info->min_rx_bufsize = 1;
933 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
935 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
936 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
937 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP;
938 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
939 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT |
940 dev_info->tx_queue_offload_capa;
941 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT;
943 dev_info->speed_capa = bnxt_get_speed_capabilities(bp);
946 dev_info->default_rxconf = (struct rte_eth_rxconf) {
952 .rx_free_thresh = 32,
953 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN,
956 dev_info->default_txconf = (struct rte_eth_txconf) {
962 .tx_free_thresh = 32,
965 eth_dev->data->dev_conf.intr_conf.lsc = 1;
967 eth_dev->data->dev_conf.intr_conf.rxq = 1;
968 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
969 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC;
970 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC;
971 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC;
973 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
974 dev_info->switch_info.name = eth_dev->device->name;
975 dev_info->switch_info.domain_id = bp->switch_domain_id;
976 dev_info->switch_info.port_id =
977 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF :
978 BNXT_SWITCH_PORT_ID_TRUSTED_VF;
984 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim
985 * need further investigation.
989 vpool = 64; /* ETH_64_POOLS */
990 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */
991 for (i = 0; i < 4; vpool >>= 1, i++) {
992 if (max_vnics > vpool) {
993 for (j = 0; j < 5; vrxq >>= 1, j++) {
994 if (dev_info->max_rx_queues > vrxq) {
1000 /* Not enough resources to support VMDq */
1004 /* Not enough resources to support VMDq */
1008 dev_info->max_vmdq_pools = vpool;
1009 dev_info->vmdq_queue_num = vrxq;
1011 dev_info->vmdq_pool_base = 0;
1012 dev_info->vmdq_queue_base = 0;
1017 /* Configure the device based on the configuration provided */
1018 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
1020 struct bnxt *bp = eth_dev->data->dev_private;
1021 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1024 bp->rx_queues = (void *)eth_dev->data->rx_queues;
1025 bp->tx_queues = (void *)eth_dev->data->tx_queues;
1026 bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
1027 bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
1029 rc = is_bnxt_in_error(bp);
1033 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) {
1034 rc = bnxt_hwrm_check_vf_rings(bp);
1036 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n");
1040 /* If a resource has already been allocated - in this case
1041 * it is the async completion ring, free it. Reallocate it after
1042 * resource reservation. This will ensure the resource counts
1043 * are calculated correctly.
1046 pthread_mutex_lock(&bp->def_cp_lock);
1048 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1049 bnxt_disable_int(bp);
1050 bnxt_free_cp_ring(bp, bp->async_cp_ring);
1053 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
1055 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
1056 pthread_mutex_unlock(&bp->def_cp_lock);
1060 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
1061 rc = bnxt_alloc_async_cp_ring(bp);
1063 pthread_mutex_unlock(&bp->def_cp_lock);
1066 bnxt_enable_int(bp);
1069 pthread_mutex_unlock(&bp->def_cp_lock);
1072 /* Inherit new configurations */
1073 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings ||
1074 eth_dev->data->nb_tx_queues > bp->max_tx_rings ||
1075 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues
1076 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings ||
1077 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues >
1079 goto resource_error;
1081 if (BNXT_HAS_RING_GRPS(bp) &&
1082 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps)
1083 goto resource_error;
1085 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) &&
1086 bp->max_vnics < eth_dev->data->nb_rx_queues)
1087 goto resource_error;
1089 bp->rx_cp_nr_rings = bp->rx_nr_rings;
1090 bp->tx_cp_nr_rings = bp->tx_nr_rings;
1092 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1093 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1094 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads;
1096 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1097 eth_dev->data->mtu =
1098 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1099 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE *
1101 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
1107 "Insufficient resources to support requested config\n");
1109 "Num Queues Requested: Tx %d, Rx %d\n",
1110 eth_dev->data->nb_tx_queues,
1111 eth_dev->data->nb_rx_queues);
1113 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n",
1114 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings,
1115 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics);
1119 void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
1121 struct rte_eth_link *link = ð_dev->data->dev_link;
1123 if (link->link_status)
1124 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n",
1125 eth_dev->data->port_id,
1126 (uint32_t)link->link_speed,
1127 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ?
1128 ("full-duplex") : ("half-duplex\n"));
1130 PMD_DRV_LOG(INFO, "Port %d Link Down\n",
1131 eth_dev->data->port_id);
1135 * Determine whether the current configuration requires support for scattered
1136 * receive; return 1 if scattered receive is required and 0 if not.
1138 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
1143 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
1146 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO)
1149 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1150 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
1152 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
1153 RTE_PKTMBUF_HEADROOM);
1154 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
1160 static eth_rx_burst_t
1161 bnxt_receive_function(struct rte_eth_dev *eth_dev)
1163 struct bnxt *bp = eth_dev->data->dev_private;
1165 /* Disable vector mode RX for Stingray2 for now */
1166 if (BNXT_CHIP_SR2(bp)) {
1167 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1168 return bnxt_recv_pkts;
1171 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1172 #ifndef RTE_LIBRTE_IEEE1588
1174 * Vector mode receive can be enabled only if scatter rx is not
1175 * in use and rx offloads are limited to VLAN stripping and
1178 if (!eth_dev->data->scattered_rx &&
1179 !(eth_dev->data->dev_conf.rxmode.offloads &
1180 ~(DEV_RX_OFFLOAD_VLAN_STRIP |
1181 DEV_RX_OFFLOAD_KEEP_CRC |
1182 DEV_RX_OFFLOAD_JUMBO_FRAME |
1183 DEV_RX_OFFLOAD_IPV4_CKSUM |
1184 DEV_RX_OFFLOAD_UDP_CKSUM |
1185 DEV_RX_OFFLOAD_TCP_CKSUM |
1186 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1187 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
1188 DEV_RX_OFFLOAD_RSS_HASH |
1189 DEV_RX_OFFLOAD_VLAN_FILTER)) &&
1190 !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) &&
1191 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1192 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
1193 eth_dev->data->port_id);
1194 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE;
1195 return bnxt_recv_pkts_vec;
1197 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
1198 eth_dev->data->port_id);
1200 "Port %d scatter: %d rx offload: %" PRIX64 "\n",
1201 eth_dev->data->port_id,
1202 eth_dev->data->scattered_rx,
1203 eth_dev->data->dev_conf.rxmode.offloads);
1206 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1207 return bnxt_recv_pkts;
1210 static eth_tx_burst_t
1211 bnxt_transmit_function(struct rte_eth_dev *eth_dev)
1213 struct bnxt *bp = eth_dev->data->dev_private;
1215 /* Disable vector mode TX for Stingray2 for now */
1216 if (BNXT_CHIP_SR2(bp))
1217 return bnxt_xmit_pkts;
1219 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
1220 #ifndef RTE_LIBRTE_IEEE1588
1221 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads;
1224 * Vector mode transmit can be enabled only if not using scatter rx
1227 if (!eth_dev->data->scattered_rx &&
1228 !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
1229 !BNXT_TRUFLOW_EN(bp) &&
1230 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
1231 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
1232 eth_dev->data->port_id);
1233 return bnxt_xmit_pkts_vec;
1235 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
1236 eth_dev->data->port_id);
1238 "Port %d scatter: %d tx offload: %" PRIX64 "\n",
1239 eth_dev->data->port_id,
1240 eth_dev->data->scattered_rx,
1244 return bnxt_xmit_pkts;
1247 static int bnxt_handle_if_change_status(struct bnxt *bp)
1251 /* Since fw has undergone a reset and lost all contexts,
1252 * set fatal flag to not issue hwrm during cleanup
1254 bp->flags |= BNXT_FLAG_FATAL_ERROR;
1255 bnxt_uninit_resources(bp, true);
1257 /* clear fatal flag so that re-init happens */
1258 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
1259 rc = bnxt_init_resources(bp, true);
1261 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
1266 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev)
1268 struct bnxt *bp = eth_dev->data->dev_private;
1271 if (!bp->link_info->link_up)
1272 rc = bnxt_set_hwrm_link_config(bp, true);
1274 eth_dev->data->dev_link.link_status = 1;
1276 bnxt_print_link_info(eth_dev);
1280 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
1282 struct bnxt *bp = eth_dev->data->dev_private;
1284 eth_dev->data->dev_link.link_status = 0;
1285 bnxt_set_hwrm_link_config(bp, false);
1286 bp->link_info->link_up = 0;
1291 static void bnxt_free_switch_domain(struct bnxt *bp)
1295 if (bp->switch_domain_id) {
1296 rc = rte_eth_switch_domain_free(bp->switch_domain_id);
1298 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n",
1299 bp->switch_domain_id, rc);
1303 static void bnxt_ptp_get_current_time(void *arg)
1305 struct bnxt *bp = arg;
1306 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1309 rc = is_bnxt_in_error(bp);
1316 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1317 &ptp->current_time);
1319 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1321 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n");
1322 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1326 static int bnxt_schedule_ptp_alarm(struct bnxt *bp)
1328 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
1331 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED)
1334 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
1335 &ptp->current_time);
1337 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp);
1341 static void bnxt_cancel_ptp_alarm(struct bnxt *bp)
1343 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) {
1344 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp);
1345 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1349 static void bnxt_ptp_stop(struct bnxt *bp)
1351 bnxt_cancel_ptp_alarm(bp);
1352 bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1355 static int bnxt_ptp_start(struct bnxt *bp)
1359 rc = bnxt_schedule_ptp_alarm(bp);
1361 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n");
1363 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED;
1364 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED;
1370 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev)
1372 struct bnxt *bp = eth_dev->data->dev_private;
1373 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1374 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1375 struct rte_eth_link link;
1378 eth_dev->data->dev_started = 0;
1379 eth_dev->data->scattered_rx = 0;
1381 /* Prevent crashes when queues are still in use */
1382 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts;
1383 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts;
1385 bnxt_disable_int(bp);
1387 /* disable uio/vfio intr/eventfd mapping */
1388 rte_intr_disable(intr_handle);
1390 /* Stop the child representors for this device */
1391 ret = bnxt_rep_stop_all(bp);
1395 /* delete the bnxt ULP port details */
1396 bnxt_ulp_port_deinit(bp);
1398 bnxt_cancel_fw_health_check(bp);
1400 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1401 bnxt_cancel_ptp_alarm(bp);
1403 /* Do not bring link down during reset recovery */
1404 if (!is_bnxt_in_error(bp)) {
1405 bnxt_dev_set_link_down_op(eth_dev);
1406 /* Wait for link to be reset */
1407 if (BNXT_SINGLE_PF(bp))
1409 /* clear the recorded link status */
1410 memset(&link, 0, sizeof(link));
1411 rte_eth_linkstatus_set(eth_dev, &link);
1414 /* Clean queue intr-vector mapping */
1415 rte_intr_efd_disable(intr_handle);
1416 if (intr_handle->intr_vec != NULL) {
1417 rte_free(intr_handle->intr_vec);
1418 intr_handle->intr_vec = NULL;
1421 bnxt_hwrm_port_clr_stats(bp);
1422 bnxt_free_tx_mbufs(bp);
1423 bnxt_free_rx_mbufs(bp);
1424 /* Process any remaining notifications in default completion queue */
1425 bnxt_int_handler(eth_dev);
1426 bnxt_shutdown_nic(bp);
1427 bnxt_hwrm_if_change(bp, false);
1429 rte_free(bp->mark_table);
1430 bp->mark_table = NULL;
1432 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
1433 bp->rx_cosq_cnt = 0;
1434 /* All filters are deleted on a port stop. */
1435 if (BNXT_FLOW_XSTATS_EN(bp))
1436 bp->flow_stat->flow_count = 0;
1441 /* Unload the driver, release resources */
1442 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev)
1444 struct bnxt *bp = eth_dev->data->dev_private;
1446 pthread_mutex_lock(&bp->err_recovery_lock);
1447 if (bp->flags & BNXT_FLAG_FW_RESET) {
1449 "Adapter recovering from error..Please retry\n");
1450 pthread_mutex_unlock(&bp->err_recovery_lock);
1453 pthread_mutex_unlock(&bp->err_recovery_lock);
1455 return bnxt_dev_stop(eth_dev);
1458 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
1460 struct bnxt *bp = eth_dev->data->dev_private;
1461 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1463 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT;
1465 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) {
1466 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n");
1470 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS)
1472 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n",
1473 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS);
1476 rc = bnxt_hwrm_if_change(bp, true);
1477 if (rc == 0 || rc != -EAGAIN)
1480 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL);
1481 } while (retry_cnt--);
1486 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) {
1487 rc = bnxt_handle_if_change_status(bp);
1492 bnxt_enable_int(bp);
1494 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
1496 rc = bnxt_start_nic(bp);
1500 eth_dev->data->dev_started = 1;
1502 bnxt_link_update_op(eth_dev, 1);
1504 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1505 vlan_mask |= ETH_VLAN_FILTER_MASK;
1506 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1507 vlan_mask |= ETH_VLAN_STRIP_MASK;
1508 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask);
1512 /* Initialize bnxt ULP port details */
1513 rc = bnxt_ulp_port_init(bp);
1517 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
1518 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
1520 bnxt_schedule_fw_health_check(bp);
1522 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp))
1523 bnxt_schedule_ptp_alarm(bp);
1528 bnxt_dev_stop(eth_dev);
1533 bnxt_uninit_locks(struct bnxt *bp)
1535 pthread_mutex_destroy(&bp->flow_lock);
1536 pthread_mutex_destroy(&bp->def_cp_lock);
1537 pthread_mutex_destroy(&bp->health_check_lock);
1538 pthread_mutex_destroy(&bp->err_recovery_lock);
1540 pthread_mutex_destroy(&bp->rep_info->vfr_lock);
1541 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock);
1545 static void bnxt_drv_uninit(struct bnxt *bp)
1547 bnxt_free_switch_domain(bp);
1548 bnxt_free_leds_info(bp);
1549 bnxt_free_cos_queues(bp);
1550 bnxt_free_link_info(bp);
1551 bnxt_free_pf_info(bp);
1552 bnxt_free_parent_info(bp);
1553 bnxt_uninit_locks(bp);
1555 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone);
1556 bp->tx_mem_zone = NULL;
1557 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone);
1558 bp->rx_mem_zone = NULL;
1560 bnxt_free_vf_info(bp);
1562 rte_free(bp->grp_info);
1563 bp->grp_info = NULL;
1566 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev)
1568 struct bnxt *bp = eth_dev->data->dev_private;
1571 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1574 pthread_mutex_lock(&bp->err_recovery_lock);
1575 if (bp->flags & BNXT_FLAG_FW_RESET) {
1577 "Adapter recovering from error...Please retry\n");
1578 pthread_mutex_unlock(&bp->err_recovery_lock);
1581 pthread_mutex_unlock(&bp->err_recovery_lock);
1583 /* cancel the recovery handler before remove dev */
1584 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp);
1585 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp);
1586 bnxt_cancel_fc_thread(bp);
1588 if (eth_dev->data->dev_started)
1589 ret = bnxt_dev_stop(eth_dev);
1591 bnxt_uninit_resources(bp, false);
1593 bnxt_drv_uninit(bp);
1598 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev,
1601 struct bnxt *bp = eth_dev->data->dev_private;
1602 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index];
1603 struct bnxt_vnic_info *vnic;
1604 struct bnxt_filter_info *filter, *temp_filter;
1607 if (is_bnxt_in_error(bp))
1611 * Loop through all VNICs from the specified filter flow pools to
1612 * remove the corresponding MAC addr filter
1614 for (i = 0; i < bp->nr_vnics; i++) {
1615 if (!(pool_mask & (1ULL << i)))
1618 vnic = &bp->vnic_info[i];
1619 filter = STAILQ_FIRST(&vnic->filter);
1621 temp_filter = STAILQ_NEXT(filter, next);
1622 if (filter->mac_index == index) {
1623 STAILQ_REMOVE(&vnic->filter, filter,
1624 bnxt_filter_info, next);
1625 bnxt_hwrm_clear_l2_filter(bp, filter);
1626 bnxt_free_filter(bp, filter);
1628 filter = temp_filter;
1633 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1634 struct rte_ether_addr *mac_addr, uint32_t index,
1637 struct bnxt_filter_info *filter;
1640 /* Attach requested MAC address to the new l2_filter */
1641 STAILQ_FOREACH(filter, &vnic->filter, next) {
1642 if (filter->mac_index == index) {
1644 "MAC addr already existed for pool %d\n",
1650 filter = bnxt_alloc_filter(bp);
1652 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
1656 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
1657 * if the MAC that's been programmed now is a different one, then,
1658 * copy that addr to filter->l2_addr
1661 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
1662 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
1664 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
1666 filter->mac_index = index;
1667 if (filter->mac_index == 0)
1668 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
1670 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
1672 bnxt_free_filter(bp, filter);
1678 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
1679 struct rte_ether_addr *mac_addr,
1680 uint32_t index, uint32_t pool)
1682 struct bnxt *bp = eth_dev->data->dev_private;
1683 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool];
1686 rc = is_bnxt_in_error(bp);
1690 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) {
1691 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n");
1696 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool);
1700 /* Filter settings will get applied when port is started */
1701 if (!eth_dev->data->dev_started)
1704 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool);
1709 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete)
1712 struct bnxt *bp = eth_dev->data->dev_private;
1713 struct rte_eth_link new;
1714 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT :
1715 BNXT_MIN_LINK_WAIT_CNT;
1717 rc = is_bnxt_in_error(bp);
1721 memset(&new, 0, sizeof(new));
1723 /* Retrieve link info from hardware */
1724 rc = bnxt_get_hwrm_link_config(bp, &new);
1726 new.link_speed = ETH_LINK_SPEED_100M;
1727 new.link_duplex = ETH_LINK_FULL_DUPLEX;
1729 "Failed to retrieve link rc = 0x%x!\n", rc);
1733 if (!wait_to_complete || new.link_status)
1736 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL);
1739 /* Only single function PF can bring phy down.
1740 * When port is stopped, report link down for VF/MH/NPAR functions.
1742 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started)
1743 memset(&new, 0, sizeof(new));
1746 /* Timed out or success */
1747 if (new.link_status != eth_dev->data->dev_link.link_status ||
1748 new.link_speed != eth_dev->data->dev_link.link_speed) {
1749 rte_eth_linkstatus_set(eth_dev, &new);
1751 rte_eth_dev_callback_process(eth_dev,
1752 RTE_ETH_EVENT_INTR_LSC,
1755 bnxt_print_link_info(eth_dev);
1761 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev)
1763 struct bnxt *bp = eth_dev->data->dev_private;
1764 struct bnxt_vnic_info *vnic;
1768 rc = is_bnxt_in_error(bp);
1772 /* Filter settings will get applied when port is started */
1773 if (!eth_dev->data->dev_started)
1776 if (bp->vnic_info == NULL)
1779 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1781 old_flags = vnic->flags;
1782 vnic->flags |= BNXT_VNIC_INFO_PROMISC;
1783 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1785 vnic->flags = old_flags;
1790 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev)
1792 struct bnxt *bp = eth_dev->data->dev_private;
1793 struct bnxt_vnic_info *vnic;
1797 rc = is_bnxt_in_error(bp);
1801 /* Filter settings will get applied when port is started */
1802 if (!eth_dev->data->dev_started)
1805 if (bp->vnic_info == NULL)
1808 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1810 old_flags = vnic->flags;
1811 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
1812 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1814 vnic->flags = old_flags;
1819 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev)
1821 struct bnxt *bp = eth_dev->data->dev_private;
1822 struct bnxt_vnic_info *vnic;
1826 rc = is_bnxt_in_error(bp);
1830 /* Filter settings will get applied when port is started */
1831 if (!eth_dev->data->dev_started)
1834 if (bp->vnic_info == NULL)
1837 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1839 old_flags = vnic->flags;
1840 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
1841 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1843 vnic->flags = old_flags;
1848 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
1850 struct bnxt *bp = eth_dev->data->dev_private;
1851 struct bnxt_vnic_info *vnic;
1855 rc = is_bnxt_in_error(bp);
1859 /* Filter settings will get applied when port is started */
1860 if (!eth_dev->data->dev_started)
1863 if (bp->vnic_info == NULL)
1866 vnic = BNXT_GET_DEFAULT_VNIC(bp);
1868 old_flags = vnic->flags;
1869 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
1870 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
1872 vnic->flags = old_flags;
1877 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */
1878 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
1880 if (qid >= bp->rx_nr_rings)
1883 return bp->eth_dev->data->rx_queues[qid];
1886 /* Return rxq corresponding to a given rss table ring/group ID. */
1887 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
1889 struct bnxt_rx_queue *rxq;
1892 if (!BNXT_HAS_RING_GRPS(bp)) {
1893 for (i = 0; i < bp->rx_nr_rings; i++) {
1894 rxq = bp->eth_dev->data->rx_queues[i];
1895 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr)
1899 for (i = 0; i < bp->rx_nr_rings; i++) {
1900 if (bp->grp_info[i].fw_grp_id == fwr)
1905 return INVALID_HW_RING_ID;
1908 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
1909 struct rte_eth_rss_reta_entry64 *reta_conf,
1912 struct bnxt *bp = eth_dev->data->dev_private;
1913 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
1914 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1915 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1919 rc = is_bnxt_in_error(bp);
1923 if (!vnic->rss_table)
1926 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
1929 if (reta_size != tbl_size) {
1930 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1931 "(%d) must equal the size supported by the hardware "
1932 "(%d)\n", reta_size, tbl_size);
1936 for (i = 0; i < reta_size; i++) {
1937 struct bnxt_rx_queue *rxq;
1939 idx = i / RTE_RETA_GROUP_SIZE;
1940 sft = i % RTE_RETA_GROUP_SIZE;
1942 if (!(reta_conf[idx].mask & (1ULL << sft)))
1945 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
1947 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
1951 if (BNXT_CHIP_P5(bp)) {
1952 vnic->rss_table[i * 2] =
1953 rxq->rx_ring->rx_ring_struct->fw_ring_id;
1954 vnic->rss_table[i * 2 + 1] =
1955 rxq->cp_ring->cp_ring_struct->fw_ring_id;
1957 vnic->rss_table[i] =
1958 vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
1962 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
1966 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
1967 struct rte_eth_rss_reta_entry64 *reta_conf,
1970 struct bnxt *bp = eth_dev->data->dev_private;
1971 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
1972 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp);
1973 uint16_t idx, sft, i;
1976 rc = is_bnxt_in_error(bp);
1980 /* Retrieve from the default VNIC */
1983 if (!vnic->rss_table)
1986 if (reta_size != tbl_size) {
1987 PMD_DRV_LOG(ERR, "The configured hash table lookup size "
1988 "(%d) must equal the size supported by the hardware "
1989 "(%d)\n", reta_size, tbl_size);
1993 for (idx = 0, i = 0; i < reta_size; i++) {
1994 idx = i / RTE_RETA_GROUP_SIZE;
1995 sft = i % RTE_RETA_GROUP_SIZE;
1997 if (reta_conf[idx].mask & (1ULL << sft)) {
2000 if (BNXT_CHIP_P5(bp))
2001 qid = bnxt_rss_to_qid(bp,
2002 vnic->rss_table[i * 2]);
2004 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
2006 if (qid == INVALID_HW_RING_ID) {
2007 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
2010 reta_conf[idx].reta[sft] = qid;
2017 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev,
2018 struct rte_eth_rss_conf *rss_conf)
2020 struct bnxt *bp = eth_dev->data->dev_private;
2021 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2022 struct bnxt_vnic_info *vnic;
2025 rc = is_bnxt_in_error(bp);
2030 * If RSS enablement were different than dev_configure,
2031 * then return -EINVAL
2033 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
2034 if (!rss_conf->rss_hf)
2035 PMD_DRV_LOG(ERR, "Hash type NONE\n");
2037 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT)
2041 bp->flags |= BNXT_FLAG_UPDATE_HASH;
2042 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf,
2046 /* Update the default RSS VNIC(s) */
2047 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2048 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
2050 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf,
2051 ETH_RSS_LEVEL(rss_conf->rss_hf));
2054 * If hashkey is not specified, use the previously configured
2057 if (!rss_conf->rss_key)
2060 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
2062 "Invalid hashkey length, should be 16 bytes\n");
2065 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
2068 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic);
2072 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev,
2073 struct rte_eth_rss_conf *rss_conf)
2075 struct bnxt *bp = eth_dev->data->dev_private;
2076 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2078 uint32_t hash_types;
2080 rc = is_bnxt_in_error(bp);
2084 /* RSS configuration is the same for all VNICs */
2085 if (vnic && vnic->rss_hash_key) {
2086 if (rss_conf->rss_key) {
2087 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ?
2088 rss_conf->rss_key_len : HW_HASH_KEY_SIZE;
2089 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len);
2092 hash_types = vnic->hash_type;
2093 rss_conf->rss_hf = 0;
2094 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) {
2095 rss_conf->rss_hf |= ETH_RSS_IPV4;
2096 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
2098 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) {
2099 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2101 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
2103 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) {
2104 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2106 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
2108 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) {
2109 rss_conf->rss_hf |= ETH_RSS_IPV6;
2110 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
2112 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) {
2113 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2115 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
2117 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) {
2118 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2120 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
2124 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode);
2128 "Unknown RSS config from firmware (%08x), RSS disabled",
2133 rss_conf->rss_hf = 0;
2138 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev,
2139 struct rte_eth_fc_conf *fc_conf)
2141 struct bnxt *bp = dev->data->dev_private;
2142 struct rte_eth_link link_info;
2145 rc = is_bnxt_in_error(bp);
2149 rc = bnxt_get_hwrm_link_config(bp, &link_info);
2153 memset(fc_conf, 0, sizeof(*fc_conf));
2154 if (bp->link_info->auto_pause)
2155 fc_conf->autoneg = 1;
2156 switch (bp->link_info->pause) {
2158 fc_conf->mode = RTE_FC_NONE;
2160 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX:
2161 fc_conf->mode = RTE_FC_TX_PAUSE;
2163 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX:
2164 fc_conf->mode = RTE_FC_RX_PAUSE;
2166 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX |
2167 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX):
2168 fc_conf->mode = RTE_FC_FULL;
2174 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev,
2175 struct rte_eth_fc_conf *fc_conf)
2177 struct bnxt *bp = dev->data->dev_private;
2180 rc = is_bnxt_in_error(bp);
2184 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2185 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n");
2189 switch (fc_conf->mode) {
2191 bp->link_info->auto_pause = 0;
2192 bp->link_info->force_pause = 0;
2194 case RTE_FC_RX_PAUSE:
2195 if (fc_conf->autoneg) {
2196 bp->link_info->auto_pause =
2197 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2198 bp->link_info->force_pause = 0;
2200 bp->link_info->auto_pause = 0;
2201 bp->link_info->force_pause =
2202 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2205 case RTE_FC_TX_PAUSE:
2206 if (fc_conf->autoneg) {
2207 bp->link_info->auto_pause =
2208 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX;
2209 bp->link_info->force_pause = 0;
2211 bp->link_info->auto_pause = 0;
2212 bp->link_info->force_pause =
2213 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX;
2217 if (fc_conf->autoneg) {
2218 bp->link_info->auto_pause =
2219 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX |
2220 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX;
2221 bp->link_info->force_pause = 0;
2223 bp->link_info->auto_pause = 0;
2224 bp->link_info->force_pause =
2225 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX |
2226 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX;
2230 return bnxt_set_hwrm_link_config(bp, true);
2233 /* Add UDP tunneling port */
2235 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev,
2236 struct rte_eth_udp_tunnel *udp_tunnel)
2238 struct bnxt *bp = eth_dev->data->dev_private;
2239 uint16_t tunnel_type = 0;
2242 rc = is_bnxt_in_error(bp);
2246 switch (udp_tunnel->prot_type) {
2247 case RTE_TUNNEL_TYPE_VXLAN:
2248 if (bp->vxlan_port_cnt) {
2249 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2250 udp_tunnel->udp_port);
2251 if (bp->vxlan_port != udp_tunnel->udp_port) {
2252 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2255 bp->vxlan_port_cnt++;
2259 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN;
2260 bp->vxlan_port_cnt++;
2262 case RTE_TUNNEL_TYPE_GENEVE:
2263 if (bp->geneve_port_cnt) {
2264 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n",
2265 udp_tunnel->udp_port);
2266 if (bp->geneve_port != udp_tunnel->udp_port) {
2267 PMD_DRV_LOG(ERR, "Only one port allowed\n");
2270 bp->geneve_port_cnt++;
2274 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE;
2275 bp->geneve_port_cnt++;
2278 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2281 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port,
2287 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev,
2288 struct rte_eth_udp_tunnel *udp_tunnel)
2290 struct bnxt *bp = eth_dev->data->dev_private;
2291 uint16_t tunnel_type = 0;
2295 rc = is_bnxt_in_error(bp);
2299 switch (udp_tunnel->prot_type) {
2300 case RTE_TUNNEL_TYPE_VXLAN:
2301 if (!bp->vxlan_port_cnt) {
2302 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2305 if (bp->vxlan_port != udp_tunnel->udp_port) {
2306 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2307 udp_tunnel->udp_port, bp->vxlan_port);
2310 if (--bp->vxlan_port_cnt)
2314 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN;
2315 port = bp->vxlan_fw_dst_port_id;
2317 case RTE_TUNNEL_TYPE_GENEVE:
2318 if (!bp->geneve_port_cnt) {
2319 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n");
2322 if (bp->geneve_port != udp_tunnel->udp_port) {
2323 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n",
2324 udp_tunnel->udp_port, bp->geneve_port);
2327 if (--bp->geneve_port_cnt)
2331 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE;
2332 port = bp->geneve_fw_dst_port_id;
2335 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n");
2339 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type);
2343 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2345 struct bnxt_filter_info *filter;
2346 struct bnxt_vnic_info *vnic;
2348 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2350 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2351 filter = STAILQ_FIRST(&vnic->filter);
2353 /* Search for this matching MAC+VLAN filter */
2354 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) {
2355 /* Delete the filter */
2356 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2359 STAILQ_REMOVE(&vnic->filter, filter,
2360 bnxt_filter_info, next);
2361 bnxt_free_filter(bp, filter);
2363 "Deleted vlan filter for %d\n",
2367 filter = STAILQ_NEXT(filter, next);
2372 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id)
2374 struct bnxt_filter_info *filter;
2375 struct bnxt_vnic_info *vnic;
2377 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
2378 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
2379 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN;
2381 /* Implementation notes on the use of VNIC in this command:
2383 * By default, these filters belong to default vnic for the function.
2384 * Once these filters are set up, only destination VNIC can be modified.
2385 * If the destination VNIC is not specified in this command,
2386 * then the HWRM shall only create an l2 context id.
2389 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2390 filter = STAILQ_FIRST(&vnic->filter);
2391 /* Check if the VLAN has already been added */
2393 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id))
2396 filter = STAILQ_NEXT(filter, next);
2399 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC
2400 * command to create MAC+VLAN filter with the right flags, enables set.
2402 filter = bnxt_alloc_filter(bp);
2405 "MAC/VLAN filter alloc failed\n");
2408 /* MAC + VLAN ID filter */
2409 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
2410 * untagged packets are received
2412 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
2413 * packets and only the programmed vlan's packets are received
2415 filter->l2_ivlan = vlan_id;
2416 filter->l2_ivlan_mask = 0x0FFF;
2417 filter->enables |= en;
2418 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
2420 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
2422 /* Free the newly allocated filter as we were
2423 * not able to create the filter in hardware.
2425 bnxt_free_filter(bp, filter);
2429 filter->mac_index = 0;
2430 /* Add this new filter to the list */
2432 STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
2434 STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
2437 "Added Vlan filter for %d\n", vlan_id);
2441 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev,
2442 uint16_t vlan_id, int on)
2444 struct bnxt *bp = eth_dev->data->dev_private;
2447 rc = is_bnxt_in_error(bp);
2451 if (!eth_dev->data->dev_started) {
2452 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n");
2456 /* These operations apply to ALL existing MAC/VLAN filters */
2458 return bnxt_add_vlan_filter(bp, vlan_id);
2460 return bnxt_del_vlan_filter(bp, vlan_id);
2463 static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
2464 struct bnxt_vnic_info *vnic)
2466 struct bnxt_filter_info *filter;
2469 filter = STAILQ_FIRST(&vnic->filter);
2471 if (filter->mac_index == 0 &&
2472 !memcmp(filter->l2_addr, bp->mac_addr,
2473 RTE_ETHER_ADDR_LEN)) {
2474 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2476 STAILQ_REMOVE(&vnic->filter, filter,
2477 bnxt_filter_info, next);
2478 bnxt_free_filter(bp, filter);
2482 filter = STAILQ_NEXT(filter, next);
2488 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads)
2490 struct bnxt_vnic_info *vnic;
2494 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2495 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
2496 /* Remove any VLAN filters programmed */
2497 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2498 bnxt_del_vlan_filter(bp, i);
2500 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2504 /* Default filter will allow packets that match the
2505 * dest mac. So, it has to be deleted, otherwise, we
2506 * will endup receiving vlan packets for which the
2507 * filter is not programmed, when hw-vlan-filter
2508 * configuration is ON
2510 bnxt_del_dflt_mac_filter(bp, vnic);
2511 /* This filter will allow only untagged packets */
2512 bnxt_add_vlan_filter(bp, 0);
2514 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
2515 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
2520 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id)
2522 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2526 /* Destroy vnic filters and vnic */
2527 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2528 DEV_RX_OFFLOAD_VLAN_FILTER) {
2529 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++)
2530 bnxt_del_vlan_filter(bp, i);
2532 bnxt_del_dflt_mac_filter(bp, vnic);
2534 rc = bnxt_hwrm_vnic_free(bp, vnic);
2538 rte_free(vnic->fw_grp_ids);
2539 vnic->fw_grp_ids = NULL;
2541 vnic->rx_queue_cnt = 0;
2547 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads)
2549 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2552 /* Destroy, recreate and reconfigure the default vnic */
2553 rc = bnxt_free_one_vnic(bp, 0);
2557 /* default vnic 0 */
2558 rc = bnxt_setup_one_vnic(bp, 0);
2562 if (bp->eth_dev->data->dev_conf.rxmode.offloads &
2563 DEV_RX_OFFLOAD_VLAN_FILTER) {
2564 rc = bnxt_add_vlan_filter(bp, 0);
2567 rc = bnxt_restore_vlan_filters(bp);
2571 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0);
2576 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2580 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n",
2581 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
2587 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
2589 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
2590 struct bnxt *bp = dev->data->dev_private;
2593 rc = is_bnxt_in_error(bp);
2597 /* Filter settings will get applied when port is started */
2598 if (!dev->data->dev_started)
2601 if (mask & ETH_VLAN_FILTER_MASK) {
2602 /* Enable or disable VLAN filtering */
2603 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads);
2608 if (mask & ETH_VLAN_STRIP_MASK) {
2609 /* Enable or disable VLAN stripping */
2610 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads);
2615 if (mask & ETH_VLAN_EXTEND_MASK) {
2616 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2617 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
2619 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
2626 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
2629 struct bnxt *bp = dev->data->dev_private;
2630 int qinq = dev->data->dev_conf.rxmode.offloads &
2631 DEV_RX_OFFLOAD_VLAN_EXTEND;
2633 if (vlan_type != ETH_VLAN_TYPE_INNER &&
2634 vlan_type != ETH_VLAN_TYPE_OUTER) {
2636 "Unsupported vlan type.");
2641 "QinQ not enabled. Needs to be ON as we can "
2642 "accelerate only outer vlan\n");
2646 if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2648 case RTE_ETHER_TYPE_QINQ:
2650 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
2652 case RTE_ETHER_TYPE_VLAN:
2654 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
2656 case RTE_ETHER_TYPE_QINQ1:
2658 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
2660 case RTE_ETHER_TYPE_QINQ2:
2662 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
2664 case RTE_ETHER_TYPE_QINQ3:
2666 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
2669 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
2672 bp->outer_tpid_bd |= tpid;
2673 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
2674 } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
2676 "Can accelerate only outer vlan in QinQ\n");
2684 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
2685 struct rte_ether_addr *addr)
2687 struct bnxt *bp = dev->data->dev_private;
2688 /* Default Filter is tied to VNIC 0 */
2689 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp);
2692 rc = is_bnxt_in_error(bp);
2696 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
2699 if (rte_is_zero_ether_addr(addr))
2702 /* Filter settings will get applied when port is started */
2703 if (!dev->data->dev_started)
2706 /* Check if the requested MAC is already added */
2707 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0)
2710 /* Destroy filter and re-create it */
2711 bnxt_del_dflt_mac_filter(bp, vnic);
2713 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
2714 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
2715 /* This filter will allow only untagged packets */
2716 rc = bnxt_add_vlan_filter(bp, 0);
2718 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0);
2721 PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
2726 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev,
2727 struct rte_ether_addr *mc_addr_set,
2728 uint32_t nb_mc_addr)
2730 struct bnxt *bp = eth_dev->data->dev_private;
2731 char *mc_addr_list = (char *)mc_addr_set;
2732 struct bnxt_vnic_info *vnic;
2733 uint32_t off = 0, i = 0;
2736 rc = is_bnxt_in_error(bp);
2740 vnic = BNXT_GET_DEFAULT_VNIC(bp);
2742 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
2743 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
2747 /* TODO Check for Duplicate mcast addresses */
2748 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
2749 for (i = 0; i < nb_mc_addr; i++) {
2750 memcpy(vnic->mc_list + off, &mc_addr_list[i],
2751 RTE_ETHER_ADDR_LEN);
2752 off += RTE_ETHER_ADDR_LEN;
2755 vnic->mc_addr_cnt = i;
2756 if (vnic->mc_addr_cnt)
2757 vnic->flags |= BNXT_VNIC_INFO_MCAST;
2759 vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
2762 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
2766 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2768 struct bnxt *bp = dev->data->dev_private;
2769 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff;
2770 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff;
2771 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff;
2772 uint8_t fw_rsvd = bp->fw_ver & 0xff;
2775 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d",
2776 fw_major, fw_minor, fw_updt, fw_rsvd);
2778 ret += 1; /* add the size of '\0' */
2779 if (fw_size < (uint32_t)ret)
2786 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2787 struct rte_eth_rxq_info *qinfo)
2789 struct bnxt *bp = dev->data->dev_private;
2790 struct bnxt_rx_queue *rxq;
2792 if (is_bnxt_in_error(bp))
2795 rxq = dev->data->rx_queues[queue_id];
2797 qinfo->mp = rxq->mb_pool;
2798 qinfo->scattered_rx = dev->data->scattered_rx;
2799 qinfo->nb_desc = rxq->nb_rx_desc;
2801 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2802 qinfo->conf.rx_drop_en = rxq->drop_en;
2803 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2804 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
2808 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
2809 struct rte_eth_txq_info *qinfo)
2811 struct bnxt *bp = dev->data->dev_private;
2812 struct bnxt_tx_queue *txq;
2814 if (is_bnxt_in_error(bp))
2817 txq = dev->data->tx_queues[queue_id];
2819 qinfo->nb_desc = txq->nb_tx_desc;
2821 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2822 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2823 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2825 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2826 qinfo->conf.tx_rs_thresh = 0;
2827 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2828 qinfo->conf.offloads = txq->offloads;
2831 static const struct {
2832 eth_rx_burst_t pkt_burst;
2834 } bnxt_rx_burst_info[] = {
2835 {bnxt_recv_pkts, "Scalar"},
2836 #if defined(RTE_ARCH_X86)
2837 {bnxt_recv_pkts_vec, "Vector SSE"},
2838 #elif defined(RTE_ARCH_ARM64)
2839 {bnxt_recv_pkts_vec, "Vector Neon"},
2844 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2845 struct rte_eth_burst_mode *mode)
2847 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2850 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) {
2851 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) {
2852 snprintf(mode->info, sizeof(mode->info), "%s",
2853 bnxt_rx_burst_info[i].info);
2861 static const struct {
2862 eth_tx_burst_t pkt_burst;
2864 } bnxt_tx_burst_info[] = {
2865 {bnxt_xmit_pkts, "Scalar"},
2866 #if defined(RTE_ARCH_X86)
2867 {bnxt_xmit_pkts_vec, "Vector SSE"},
2868 #elif defined(RTE_ARCH_ARM64)
2869 {bnxt_xmit_pkts_vec, "Vector Neon"},
2874 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2875 struct rte_eth_burst_mode *mode)
2877 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2880 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) {
2881 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) {
2882 snprintf(mode->info, sizeof(mode->info), "%s",
2883 bnxt_tx_burst_info[i].info);
2891 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
2893 struct bnxt *bp = eth_dev->data->dev_private;
2894 uint32_t new_pkt_size;
2898 rc = is_bnxt_in_error(bp);
2902 /* Exit if receive queues are not configured yet */
2903 if (!eth_dev->data->nb_rx_queues)
2906 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
2907 VLAN_TAG_SIZE * BNXT_NUM_VLANS;
2910 * Disallow any MTU change that would require scattered receive support
2911 * if it is not already enabled.
2913 if (eth_dev->data->dev_started &&
2914 !eth_dev->data->scattered_rx &&
2916 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
2918 "MTU change would require scattered rx support. ");
2919 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
2923 if (new_mtu > RTE_ETHER_MTU) {
2924 bp->flags |= BNXT_FLAG_JUMBO;
2925 bp->eth_dev->data->dev_conf.rxmode.offloads |=
2926 DEV_RX_OFFLOAD_JUMBO_FRAME;
2928 bp->eth_dev->data->dev_conf.rxmode.offloads &=
2929 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2930 bp->flags &= ~BNXT_FLAG_JUMBO;
2933 /* Is there a change in mtu setting? */
2934 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size)
2937 for (i = 0; i < bp->nr_vnics; i++) {
2938 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2941 vnic->mru = BNXT_VNIC_MRU(new_mtu);
2942 rc = bnxt_hwrm_vnic_cfg(bp, vnic);
2946 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2947 size -= RTE_PKTMBUF_HEADROOM;
2949 if (size < new_mtu) {
2950 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic);
2957 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
2959 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
2965 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on)
2967 struct bnxt *bp = dev->data->dev_private;
2968 uint16_t vlan = bp->vlan;
2971 rc = is_bnxt_in_error(bp);
2975 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) {
2977 "PVID cannot be modified for this function\n");
2980 bp->vlan = on ? pvid : 0;
2982 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0);
2989 bnxt_dev_led_on_op(struct rte_eth_dev *dev)
2991 struct bnxt *bp = dev->data->dev_private;
2994 rc = is_bnxt_in_error(bp);
2998 return bnxt_hwrm_port_led_cfg(bp, true);
3002 bnxt_dev_led_off_op(struct rte_eth_dev *dev)
3004 struct bnxt *bp = dev->data->dev_private;
3007 rc = is_bnxt_in_error(bp);
3011 return bnxt_hwrm_port_led_cfg(bp, false);
3015 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3017 struct bnxt *bp = (struct bnxt *)dev->data->dev_private;
3018 struct bnxt_cp_ring_info *cpr;
3019 uint32_t desc = 0, raw_cons;
3020 struct bnxt_rx_queue *rxq;
3021 struct rx_pkt_cmpl *rxcmp;
3024 rc = is_bnxt_in_error(bp);
3028 rxq = dev->data->rx_queues[rx_queue_id];
3030 raw_cons = cpr->cp_raw_cons;
3033 uint32_t agg_cnt, cons, cmpl_type;
3035 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3036 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3038 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3041 cmpl_type = CMP_TYPE(rxcmp);
3043 switch (cmpl_type) {
3044 case CMPL_BASE_TYPE_RX_L2:
3045 case CMPL_BASE_TYPE_RX_L2_V2:
3046 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3047 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3051 case CMPL_BASE_TYPE_RX_TPA_END:
3052 if (BNXT_CHIP_P5(rxq->bp)) {
3053 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3055 p5_tpa_end = (void *)rxcmp;
3056 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3058 struct rx_tpa_end_cmpl *tpa_end;
3060 tpa_end = (void *)rxcmp;
3061 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3064 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3069 raw_cons += CMP_LEN(cmpl_type);
3077 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset)
3079 struct bnxt_rx_queue *rxq = rx_queue;
3080 struct bnxt_cp_ring_info *cpr;
3081 struct bnxt_rx_ring_info *rxr;
3082 uint32_t desc, raw_cons;
3083 struct bnxt *bp = rxq->bp;
3084 struct rx_pkt_cmpl *rxcmp;
3087 rc = is_bnxt_in_error(bp);
3091 if (offset >= rxq->nb_rx_desc)
3098 * For the vector receive case, the completion at the requested
3099 * offset can be indexed directly.
3101 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)
3102 if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) {
3103 struct rx_pkt_cmpl *rxcmp;
3106 /* Check status of completion descriptor. */
3107 raw_cons = cpr->cp_raw_cons +
3108 offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2);
3109 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3110 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3112 if (CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3113 return RTE_ETH_RX_DESC_DONE;
3115 /* Check whether rx desc has an mbuf attached. */
3116 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2);
3117 if (cons >= rxq->rxrearm_start &&
3118 cons < rxq->rxrearm_start + rxq->rxrearm_nb) {
3119 return RTE_ETH_RX_DESC_UNAVAIL;
3122 return RTE_ETH_RX_DESC_AVAIL;
3127 * For the non-vector receive case, scan the completion ring to
3128 * locate the completion descriptor for the requested offset.
3130 raw_cons = cpr->cp_raw_cons;
3133 uint32_t agg_cnt, cons, cmpl_type;
3135 cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
3136 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3138 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
3141 cmpl_type = CMP_TYPE(rxcmp);
3143 switch (cmpl_type) {
3144 case CMPL_BASE_TYPE_RX_L2:
3145 case CMPL_BASE_TYPE_RX_L2_V2:
3146 if (desc == offset) {
3147 cons = rxcmp->opaque;
3148 if (rxr->rx_buf_ring[cons])
3149 return RTE_ETH_RX_DESC_DONE;
3151 return RTE_ETH_RX_DESC_UNAVAIL;
3153 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp);
3154 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3158 case CMPL_BASE_TYPE_RX_TPA_END:
3160 return RTE_ETH_RX_DESC_DONE;
3162 if (BNXT_CHIP_P5(rxq->bp)) {
3163 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end;
3165 p5_tpa_end = (void *)rxcmp;
3166 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end);
3168 struct rx_tpa_end_cmpl *tpa_end;
3170 tpa_end = (void *)rxcmp;
3171 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end);
3174 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt;
3179 raw_cons += CMP_LEN(cmpl_type);
3183 return RTE_ETH_RX_DESC_AVAIL;
3187 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset)
3189 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue;
3190 struct bnxt_tx_ring_info *txr;
3191 struct bnxt_cp_ring_info *cpr;
3192 struct bnxt_sw_tx_bd *tx_buf;
3193 struct tx_pkt_cmpl *txcmp;
3194 uint32_t cons, cp_cons;
3200 rc = is_bnxt_in_error(txq->bp);
3207 if (offset >= txq->nb_tx_desc)
3210 cons = RING_CMP(cpr->cp_ring_struct, offset);
3211 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
3212 cp_cons = cpr->cp_raw_cons;
3214 if (cons > cp_cons) {
3215 if (CMPL_VALID(txcmp, cpr->valid))
3216 return RTE_ETH_TX_DESC_UNAVAIL;
3218 if (CMPL_VALID(txcmp, !cpr->valid))
3219 return RTE_ETH_TX_DESC_UNAVAIL;
3221 tx_buf = &txr->tx_buf_ring[cons];
3222 if (tx_buf->mbuf == NULL)
3223 return RTE_ETH_TX_DESC_DONE;
3225 return RTE_ETH_TX_DESC_FULL;
3229 bnxt_filter_ctrl_op(struct rte_eth_dev *dev,
3230 enum rte_filter_type filter_type,
3231 enum rte_filter_op filter_op, void *arg)
3233 struct bnxt *bp = dev->data->dev_private;
3239 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) {
3240 struct bnxt_representor *vfr = dev->data->dev_private;
3241 bp = vfr->parent_dev->data->dev_private;
3242 /* parent is deleted while children are still valid */
3244 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error %d:%d\n",
3252 ret = is_bnxt_in_error(bp);
3256 switch (filter_type) {
3257 case RTE_ETH_FILTER_GENERIC:
3258 if (filter_op != RTE_ETH_FILTER_GET)
3261 /* PMD supports thread-safe flow operations. rte_flow API
3262 * functions can avoid mutex for multi-thread safety.
3264 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
3266 if (BNXT_TRUFLOW_EN(bp))
3267 *(const void **)arg = &bnxt_ulp_rte_flow_ops;
3269 *(const void **)arg = &bnxt_flow_ops;
3273 "Filter type (%d) not supported", filter_type);
3280 static const uint32_t *
3281 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
3283 static const uint32_t ptypes[] = {
3284 RTE_PTYPE_L2_ETHER_VLAN,
3285 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
3286 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
3290 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
3291 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
3292 RTE_PTYPE_INNER_L4_ICMP,
3293 RTE_PTYPE_INNER_L4_TCP,
3294 RTE_PTYPE_INNER_L4_UDP,
3298 if (!dev->rx_pkt_burst)
3304 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
3307 uint32_t reg_base = *reg_arr & 0xfffff000;
3311 for (i = 0; i < count; i++) {
3312 if ((reg_arr[i] & 0xfffff000) != reg_base)
3315 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
3316 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off);
3320 static int bnxt_map_ptp_regs(struct bnxt *bp)
3322 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3326 reg_arr = ptp->rx_regs;
3327 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5);
3331 reg_arr = ptp->tx_regs;
3332 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6);
3336 for (i = 0; i < BNXT_PTP_RX_REGS; i++)
3337 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff);
3339 for (i = 0; i < BNXT_PTP_TX_REGS; i++)
3340 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff);
3345 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
3347 rte_write32(0, (uint8_t *)bp->bar0 +
3348 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16);
3349 rte_write32(0, (uint8_t *)bp->bar0 +
3350 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20);
3353 static uint64_t bnxt_cc_read(struct bnxt *bp)
3357 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3358 BNXT_GRCPF_REG_SYNC_TIME));
3359 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3360 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32;
3364 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts)
3366 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3369 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3370 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3371 if (fifo & BNXT_PTP_TX_FIFO_EMPTY)
3374 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3375 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO]));
3376 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3377 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L]));
3378 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3379 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32;
3384 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts)
3386 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3387 struct bnxt_pf_info *pf = bp->pf;
3394 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3395 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3396 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING))
3399 port_id = pf->port_id;
3400 rte_write32(1 << port_id, (uint8_t *)bp->bar0 +
3401 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]);
3403 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3404 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO]));
3405 if (fifo & BNXT_PTP_RX_FIFO_PENDING) {
3406 /* bnxt_clr_rx_ts(bp); TBD */
3410 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3411 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L]));
3412 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
3413 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32;
3419 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3422 struct bnxt *bp = dev->data->dev_private;
3423 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3428 ns = rte_timespec_to_ns(ts);
3429 /* Set the timecounters to a new value. */
3436 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3438 struct bnxt *bp = dev->data->dev_private;
3439 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3440 uint64_t ns, systime_cycles = 0;
3446 if (BNXT_CHIP_P5(bp))
3447 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
3450 systime_cycles = bnxt_cc_read(bp);
3452 ns = rte_timecounter_update(&ptp->tc, systime_cycles);
3453 *ts = rte_ns_to_timespec(ns);
3458 bnxt_timesync_enable(struct rte_eth_dev *dev)
3460 struct bnxt *bp = dev->data->dev_private;
3461 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3469 ptp->tx_tstamp_en = 1;
3470 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
3472 rc = bnxt_hwrm_ptp_cfg(bp);
3476 memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
3477 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3478 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3480 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3481 ptp->tc.cc_shift = shift;
3482 ptp->tc.nsec_mask = (1ULL << shift) - 1;
3484 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3485 ptp->rx_tstamp_tc.cc_shift = shift;
3486 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3488 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK;
3489 ptp->tx_tstamp_tc.cc_shift = shift;
3490 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3492 if (!BNXT_CHIP_P5(bp))
3493 bnxt_map_ptp_regs(bp);
3495 rc = bnxt_ptp_start(bp);
3501 bnxt_timesync_disable(struct rte_eth_dev *dev)
3503 struct bnxt *bp = dev->data->dev_private;
3504 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3510 ptp->tx_tstamp_en = 0;
3513 bnxt_hwrm_ptp_cfg(bp);
3515 if (!BNXT_CHIP_P5(bp))
3516 bnxt_unmap_ptp_regs(bp);
3524 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3525 struct timespec *timestamp,
3526 uint32_t flags __rte_unused)
3528 struct bnxt *bp = dev->data->dev_private;
3529 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3530 uint64_t rx_tstamp_cycles = 0;
3536 if (BNXT_CHIP_P5(bp))
3537 rx_tstamp_cycles = ptp->rx_timestamp;
3539 bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
3541 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
3542 *timestamp = rte_ns_to_timespec(ns);
3547 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3548 struct timespec *timestamp)
3550 struct bnxt *bp = dev->data->dev_private;
3551 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3552 uint64_t tx_tstamp_cycles = 0;
3559 if (BNXT_CHIP_P5(bp))
3560 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
3563 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
3565 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
3566 *timestamp = rte_ns_to_timespec(ns);
3572 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3574 struct bnxt *bp = dev->data->dev_private;
3575 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
3580 ptp->tc.nsec += delta;
3586 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev)
3588 struct bnxt *bp = dev->data->dev_private;
3590 uint32_t dir_entries;
3591 uint32_t entry_length;
3593 rc = is_bnxt_in_error(bp);
3597 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n",
3598 bp->pdev->addr.domain, bp->pdev->addr.bus,
3599 bp->pdev->addr.devid, bp->pdev->addr.function);
3601 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
3605 return dir_entries * entry_length;
3609 bnxt_get_eeprom_op(struct rte_eth_dev *dev,
3610 struct rte_dev_eeprom_info *in_eeprom)
3612 struct bnxt *bp = dev->data->dev_private;
3617 rc = is_bnxt_in_error(bp);
3621 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3622 bp->pdev->addr.domain, bp->pdev->addr.bus,
3623 bp->pdev->addr.devid, bp->pdev->addr.function,
3624 in_eeprom->offset, in_eeprom->length);
3626 if (in_eeprom->offset == 0) /* special offset value to get directory */
3627 return bnxt_get_nvram_directory(bp, in_eeprom->length,
3630 index = in_eeprom->offset >> 24;
3631 offset = in_eeprom->offset & 0xffffff;
3634 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset,
3635 in_eeprom->length, in_eeprom->data);
3640 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type)
3643 case BNX_DIR_TYPE_CHIMP_PATCH:
3644 case BNX_DIR_TYPE_BOOTCODE:
3645 case BNX_DIR_TYPE_BOOTCODE_2:
3646 case BNX_DIR_TYPE_APE_FW:
3647 case BNX_DIR_TYPE_APE_PATCH:
3648 case BNX_DIR_TYPE_KONG_FW:
3649 case BNX_DIR_TYPE_KONG_PATCH:
3650 case BNX_DIR_TYPE_BONO_FW:
3651 case BNX_DIR_TYPE_BONO_PATCH:
3659 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type)
3662 case BNX_DIR_TYPE_AVS:
3663 case BNX_DIR_TYPE_EXP_ROM_MBA:
3664 case BNX_DIR_TYPE_PCIE:
3665 case BNX_DIR_TYPE_TSCF_UCODE:
3666 case BNX_DIR_TYPE_EXT_PHY:
3667 case BNX_DIR_TYPE_CCM:
3668 case BNX_DIR_TYPE_ISCSI_BOOT:
3669 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6:
3670 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6:
3678 static bool bnxt_dir_type_is_executable(uint16_t dir_type)
3680 return bnxt_dir_type_is_ape_bin_format(dir_type) ||
3681 bnxt_dir_type_is_other_exec_format(dir_type);
3685 bnxt_set_eeprom_op(struct rte_eth_dev *dev,
3686 struct rte_dev_eeprom_info *in_eeprom)
3688 struct bnxt *bp = dev->data->dev_private;
3689 uint8_t index, dir_op;
3690 uint16_t type, ext, ordinal, attr;
3693 rc = is_bnxt_in_error(bp);
3697 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n",
3698 bp->pdev->addr.domain, bp->pdev->addr.bus,
3699 bp->pdev->addr.devid, bp->pdev->addr.function,
3700 in_eeprom->offset, in_eeprom->length);
3703 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n");
3707 type = in_eeprom->magic >> 16;
3709 if (type == 0xffff) { /* special value for directory operations */
3710 index = in_eeprom->magic & 0xff;
3711 dir_op = in_eeprom->magic >> 8;
3715 case 0x0e: /* erase */
3716 if (in_eeprom->offset != ~in_eeprom->magic)
3718 return bnxt_hwrm_erase_nvram_directory(bp, index - 1);
3724 /* Create or re-write an NVM item: */
3725 if (bnxt_dir_type_is_executable(type) == true)
3727 ext = in_eeprom->magic & 0xffff;
3728 ordinal = in_eeprom->offset >> 16;
3729 attr = in_eeprom->offset & 0xffff;
3731 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr,
3732 in_eeprom->data, in_eeprom->length);
3739 static const struct eth_dev_ops bnxt_dev_ops = {
3740 .dev_infos_get = bnxt_dev_info_get_op,
3741 .dev_close = bnxt_dev_close_op,
3742 .dev_configure = bnxt_dev_configure_op,
3743 .dev_start = bnxt_dev_start_op,
3744 .dev_stop = bnxt_dev_stop_op,
3745 .dev_set_link_up = bnxt_dev_set_link_up_op,
3746 .dev_set_link_down = bnxt_dev_set_link_down_op,
3747 .stats_get = bnxt_stats_get_op,
3748 .stats_reset = bnxt_stats_reset_op,
3749 .rx_queue_setup = bnxt_rx_queue_setup_op,
3750 .rx_queue_release = bnxt_rx_queue_release_op,
3751 .tx_queue_setup = bnxt_tx_queue_setup_op,
3752 .tx_queue_release = bnxt_tx_queue_release_op,
3753 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op,
3754 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op,
3755 .reta_update = bnxt_reta_update_op,
3756 .reta_query = bnxt_reta_query_op,
3757 .rss_hash_update = bnxt_rss_hash_update_op,
3758 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op,
3759 .link_update = bnxt_link_update_op,
3760 .promiscuous_enable = bnxt_promiscuous_enable_op,
3761 .promiscuous_disable = bnxt_promiscuous_disable_op,
3762 .allmulticast_enable = bnxt_allmulticast_enable_op,
3763 .allmulticast_disable = bnxt_allmulticast_disable_op,
3764 .mac_addr_add = bnxt_mac_addr_add_op,
3765 .mac_addr_remove = bnxt_mac_addr_remove_op,
3766 .flow_ctrl_get = bnxt_flow_ctrl_get_op,
3767 .flow_ctrl_set = bnxt_flow_ctrl_set_op,
3768 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op,
3769 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
3770 .vlan_filter_set = bnxt_vlan_filter_set_op,
3771 .vlan_offload_set = bnxt_vlan_offload_set_op,
3772 .vlan_tpid_set = bnxt_vlan_tpid_set_op,
3773 .vlan_pvid_set = bnxt_vlan_pvid_set_op,
3774 .mtu_set = bnxt_mtu_set_op,
3775 .mac_addr_set = bnxt_set_default_mac_addr_op,
3776 .xstats_get = bnxt_dev_xstats_get_op,
3777 .xstats_get_names = bnxt_dev_xstats_get_names_op,
3778 .xstats_reset = bnxt_dev_xstats_reset_op,
3779 .fw_version_get = bnxt_fw_version_get,
3780 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op,
3781 .rxq_info_get = bnxt_rxq_info_get_op,
3782 .txq_info_get = bnxt_txq_info_get_op,
3783 .rx_burst_mode_get = bnxt_rx_burst_mode_get,
3784 .tx_burst_mode_get = bnxt_tx_burst_mode_get,
3785 .dev_led_on = bnxt_dev_led_on_op,
3786 .dev_led_off = bnxt_dev_led_off_op,
3787 .rx_queue_start = bnxt_rx_queue_start,
3788 .rx_queue_stop = bnxt_rx_queue_stop,
3789 .tx_queue_start = bnxt_tx_queue_start,
3790 .tx_queue_stop = bnxt_tx_queue_stop,
3791 .filter_ctrl = bnxt_filter_ctrl_op,
3792 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op,
3793 .get_eeprom_length = bnxt_get_eeprom_length_op,
3794 .get_eeprom = bnxt_get_eeprom_op,
3795 .set_eeprom = bnxt_set_eeprom_op,
3796 .timesync_enable = bnxt_timesync_enable,
3797 .timesync_disable = bnxt_timesync_disable,
3798 .timesync_read_time = bnxt_timesync_read_time,
3799 .timesync_write_time = bnxt_timesync_write_time,
3800 .timesync_adjust_time = bnxt_timesync_adjust_time,
3801 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp,
3802 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
3805 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
3809 /* Only pre-map the reset GRC registers using window 3 */
3810 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
3811 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
3813 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
3818 int bnxt_map_fw_health_status_regs(struct bnxt *bp)
3820 struct bnxt_error_recovery_info *info = bp->recovery_info;
3821 uint32_t reg_base = 0xffffffff;
3824 /* Only pre-map the monitoring GRC registers using window 2 */
3825 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
3826 uint32_t reg = info->status_regs[i];
3828 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
3831 if (reg_base == 0xffffffff)
3832 reg_base = reg & 0xfffff000;
3833 if ((reg & 0xfffff000) != reg_base)
3836 /* Use mask 0xffc as the Lower 2 bits indicates
3837 * address space location
3839 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
3843 if (reg_base == 0xffffffff)
3846 rte_write32(reg_base, (uint8_t *)bp->bar0 +
3847 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
3852 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
3854 struct bnxt_error_recovery_info *info = bp->recovery_info;
3855 uint32_t delay = info->delay_after_reset[index];
3856 uint32_t val = info->reset_reg_val[index];
3857 uint32_t reg = info->reset_reg[index];
3858 uint32_t type, offset;
3860 type = BNXT_FW_STATUS_REG_TYPE(reg);
3861 offset = BNXT_FW_STATUS_REG_OFF(reg);
3864 case BNXT_FW_STATUS_REG_TYPE_CFG:
3865 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
3867 case BNXT_FW_STATUS_REG_TYPE_GRC:
3868 offset = bnxt_map_reset_regs(bp, offset);
3869 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3871 case BNXT_FW_STATUS_REG_TYPE_BAR0:
3872 rte_write32(val, (uint8_t *)bp->bar0 + offset);
3875 /* wait on a specific interval of time until core reset is complete */
3877 rte_delay_ms(delay);
3880 static void bnxt_dev_cleanup(struct bnxt *bp)
3882 bp->eth_dev->data->dev_link.link_status = 0;
3883 bp->link_info->link_up = 0;
3884 if (bp->eth_dev->data->dev_started)
3885 bnxt_dev_stop(bp->eth_dev);
3887 bnxt_uninit_resources(bp, true);
3891 bnxt_check_fw_reset_done(struct bnxt *bp)
3893 int timeout = bp->fw_reset_max_msecs;
3898 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
3900 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
3906 } while (timeout--);
3908 if (val == 0xffff) {
3909 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n");
3916 static int bnxt_restore_vlan_filters(struct bnxt *bp)
3918 struct rte_eth_dev *dev = bp->eth_dev;
3919 struct rte_vlan_filter_conf *vfc;
3923 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) {
3924 vfc = &dev->data->vlan_filter_conf;
3925 vidx = vlan_id / 64;
3926 vbit = vlan_id % 64;
3928 /* Each bit corresponds to a VLAN id */
3929 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) {
3930 rc = bnxt_add_vlan_filter(bp, vlan_id);
3939 static int bnxt_restore_mac_filters(struct bnxt *bp)
3941 struct rte_eth_dev *dev = bp->eth_dev;
3942 struct rte_eth_dev_info dev_info;
3943 struct rte_ether_addr *addr;
3949 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp))
3952 rc = bnxt_dev_info_get_op(dev, &dev_info);
3956 /* replay MAC address configuration */
3957 for (i = 1; i < dev_info.max_mac_addrs; i++) {
3958 addr = &dev->data->mac_addrs[i];
3960 /* skip zero address */
3961 if (rte_is_zero_ether_addr(addr))
3965 pool_mask = dev->data->mac_pool_sel[i];
3968 if (pool_mask & 1ULL) {
3969 rc = bnxt_mac_addr_add_op(dev, addr, i, pool);
3975 } while (pool_mask);
3981 static int bnxt_restore_filters(struct bnxt *bp)
3983 struct rte_eth_dev *dev = bp->eth_dev;
3986 if (dev->data->all_multicast) {
3987 ret = bnxt_allmulticast_enable_op(dev);
3991 if (dev->data->promiscuous) {
3992 ret = bnxt_promiscuous_enable_op(dev);
3997 ret = bnxt_restore_mac_filters(bp);
4001 ret = bnxt_restore_vlan_filters(bp);
4002 /* TODO restore other filters as well */
4006 static int bnxt_check_fw_ready(struct bnxt *bp)
4008 int timeout = bp->fw_reset_max_msecs;
4012 rc = bnxt_hwrm_poll_ver_get(bp);
4015 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL);
4016 timeout -= BNXT_FW_READY_WAIT_INTERVAL;
4017 } while (rc && timeout > 0);
4020 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n");
4025 static void bnxt_dev_recover(void *arg)
4027 struct bnxt *bp = arg;
4030 pthread_mutex_lock(&bp->err_recovery_lock);
4032 if (!bp->fw_reset_min_msecs) {
4033 rc = bnxt_check_fw_reset_done(bp);
4038 /* Clear Error flag so that device re-init should happen */
4039 bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
4041 rc = bnxt_check_fw_ready(bp);
4045 rc = bnxt_init_resources(bp, true);
4048 "Failed to initialize resources after reset\n");
4051 /* clear reset flag as the device is initialized now */
4052 bp->flags &= ~BNXT_FLAG_FW_RESET;
4054 rc = bnxt_dev_start_op(bp->eth_dev);
4056 PMD_DRV_LOG(ERR, "Failed to start port after reset\n");
4060 rc = bnxt_restore_filters(bp);
4064 PMD_DRV_LOG(INFO, "Recovered from FW reset\n");
4065 pthread_mutex_unlock(&bp->err_recovery_lock);
4069 bnxt_dev_stop(bp->eth_dev);
4071 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4072 bnxt_uninit_resources(bp, false);
4073 pthread_mutex_unlock(&bp->err_recovery_lock);
4074 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n");
4077 void bnxt_dev_reset_and_resume(void *arg)
4079 struct bnxt *bp = arg;
4080 uint32_t us = US_PER_MS * bp->fw_reset_min_msecs;
4084 bnxt_dev_cleanup(bp);
4086 bnxt_wait_for_device_shutdown(bp);
4088 /* During some fatal firmware error conditions, the PCI config space
4089 * register 0x2e which normally contains the subsystem ID will become
4090 * 0xffff. This register will revert back to the normal value after
4091 * the chip has completed core reset. If we detect this condition,
4092 * we can poll this config register immediately for the value to revert.
4094 if (bp->flags & BNXT_FLAG_FATAL_ERROR) {
4095 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET);
4097 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET);
4100 if (val == 0xffff) {
4101 bp->fw_reset_min_msecs = 0;
4106 rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp);
4108 PMD_DRV_LOG(ERR, "Error setting recovery alarm");
4111 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
4113 struct bnxt_error_recovery_info *info = bp->recovery_info;
4114 uint32_t reg = info->status_regs[index];
4115 uint32_t type, offset, val = 0;
4117 type = BNXT_FW_STATUS_REG_TYPE(reg);
4118 offset = BNXT_FW_STATUS_REG_OFF(reg);
4121 case BNXT_FW_STATUS_REG_TYPE_CFG:
4122 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
4124 case BNXT_FW_STATUS_REG_TYPE_GRC:
4125 offset = info->mapped_status_regs[index];
4127 case BNXT_FW_STATUS_REG_TYPE_BAR0:
4128 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4136 static int bnxt_fw_reset_all(struct bnxt *bp)
4138 struct bnxt_error_recovery_info *info = bp->recovery_info;
4142 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4143 /* Reset through master function driver */
4144 for (i = 0; i < info->reg_array_cnt; i++)
4145 bnxt_write_fw_reset_reg(bp, i);
4146 /* Wait for time specified by FW after triggering reset */
4147 rte_delay_ms(info->master_func_wait_period_after_reset);
4148 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
4149 /* Reset with the help of Kong processor */
4150 rc = bnxt_hwrm_fw_reset(bp);
4152 PMD_DRV_LOG(ERR, "Failed to reset FW\n");
4158 static void bnxt_fw_reset_cb(void *arg)
4160 struct bnxt *bp = arg;
4161 struct bnxt_error_recovery_info *info = bp->recovery_info;
4164 /* Only Master function can do FW reset */
4165 if (bnxt_is_master_func(bp) &&
4166 bnxt_is_recovery_enabled(bp)) {
4167 rc = bnxt_fw_reset_all(bp);
4169 PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
4174 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
4175 * EXCEPTION_FATAL_ASYNC event to all the functions
4176 * (including MASTER FUNC). After receiving this Async, all the active
4177 * drivers should treat this case as FW initiated recovery
4179 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
4180 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
4181 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
4183 /* To recover from error */
4184 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
4189 /* Driver should poll FW heartbeat, reset_counter with the frequency
4190 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
4191 * When the driver detects heartbeat stop or change in reset_counter,
4192 * it has to trigger a reset to recover from the error condition.
4193 * A “master PF” is the function who will have the privilege to
4194 * initiate the chimp reset. The master PF will be elected by the
4195 * firmware and will be notified through async message.
4197 static void bnxt_check_fw_health(void *arg)
4199 struct bnxt *bp = arg;
4200 struct bnxt_error_recovery_info *info = bp->recovery_info;
4201 uint32_t val = 0, wait_msec;
4203 if (!info || !bnxt_is_recovery_enabled(bp) ||
4204 is_bnxt_in_error(bp))
4207 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
4208 if (val == info->last_heart_beat)
4211 info->last_heart_beat = val;
4213 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
4214 if (val != info->last_reset_counter)
4217 info->last_reset_counter = val;
4219 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
4220 bnxt_check_fw_health, (void *)bp);
4224 /* Stop DMA to/from device */
4225 bp->flags |= BNXT_FLAG_FATAL_ERROR;
4226 bp->flags |= BNXT_FLAG_FW_RESET;
4228 PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
4230 if (bnxt_is_master_func(bp))
4231 wait_msec = info->master_func_wait_period;
4233 wait_msec = info->normal_func_wait_period;
4235 rte_eal_alarm_set(US_PER_MS * wait_msec,
4236 bnxt_fw_reset_cb, (void *)bp);
4239 void bnxt_schedule_fw_health_check(struct bnxt *bp)
4241 uint32_t polling_freq;
4243 pthread_mutex_lock(&bp->health_check_lock);
4245 if (!bnxt_is_recovery_enabled(bp))
4248 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
4251 polling_freq = bp->recovery_info->driver_polling_freq;
4253 rte_eal_alarm_set(US_PER_MS * polling_freq,
4254 bnxt_check_fw_health, (void *)bp);
4255 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4258 pthread_mutex_unlock(&bp->health_check_lock);
4261 static void bnxt_cancel_fw_health_check(struct bnxt *bp)
4263 if (!bnxt_is_recovery_enabled(bp))
4266 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
4267 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
4270 static bool bnxt_vf_pciid(uint16_t device_id)
4272 switch (device_id) {
4273 case BROADCOM_DEV_ID_57304_VF:
4274 case BROADCOM_DEV_ID_57406_VF:
4275 case BROADCOM_DEV_ID_5731X_VF:
4276 case BROADCOM_DEV_ID_5741X_VF:
4277 case BROADCOM_DEV_ID_57414_VF:
4278 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4279 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4280 case BROADCOM_DEV_ID_58802_VF:
4281 case BROADCOM_DEV_ID_57500_VF1:
4282 case BROADCOM_DEV_ID_57500_VF2:
4283 case BROADCOM_DEV_ID_58818_VF:
4291 /* Phase 5 device */
4292 static bool bnxt_p5_device(uint16_t device_id)
4294 switch (device_id) {
4295 case BROADCOM_DEV_ID_57508:
4296 case BROADCOM_DEV_ID_57504:
4297 case BROADCOM_DEV_ID_57502:
4298 case BROADCOM_DEV_ID_57508_MF1:
4299 case BROADCOM_DEV_ID_57504_MF1:
4300 case BROADCOM_DEV_ID_57502_MF1:
4301 case BROADCOM_DEV_ID_57508_MF2:
4302 case BROADCOM_DEV_ID_57504_MF2:
4303 case BROADCOM_DEV_ID_57502_MF2:
4304 case BROADCOM_DEV_ID_57500_VF1:
4305 case BROADCOM_DEV_ID_57500_VF2:
4306 case BROADCOM_DEV_ID_58812:
4307 case BROADCOM_DEV_ID_58814:
4308 case BROADCOM_DEV_ID_58818:
4309 case BROADCOM_DEV_ID_58818_VF:
4317 bool bnxt_stratus_device(struct bnxt *bp)
4319 uint16_t device_id = bp->pdev->id.device_id;
4321 switch (device_id) {
4322 case BROADCOM_DEV_ID_STRATUS_NIC:
4323 case BROADCOM_DEV_ID_STRATUS_NIC_VF1:
4324 case BROADCOM_DEV_ID_STRATUS_NIC_VF2:
4332 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev)
4334 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
4335 struct bnxt *bp = eth_dev->data->dev_private;
4337 /* enable device (incl. PCI PM wakeup), and bus-mastering */
4338 bp->bar0 = (void *)pci_dev->mem_resource[0].addr;
4339 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr;
4340 if (!bp->bar0 || !bp->doorbell_base) {
4341 PMD_DRV_LOG(ERR, "Unable to access Hardware\n");
4345 bp->eth_dev = eth_dev;
4351 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
4352 struct bnxt_ctx_pg_info *ctx_pg,
4357 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
4358 const struct rte_memzone *mz = NULL;
4359 char mz_name[RTE_MEMZONE_NAMESIZE];
4360 rte_iova_t mz_phys_addr;
4361 uint64_t valid_bits = 0;
4368 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) /
4370 rmem->page_size = BNXT_PAGE_SIZE;
4371 rmem->pg_arr = ctx_pg->ctx_pg_arr;
4372 rmem->dma_arr = ctx_pg->ctx_dma_arr;
4373 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
4375 valid_bits = PTU_PTE_VALID;
4377 if (rmem->nr_pages > 1) {
4378 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4379 "bnxt_ctx_pg_tbl%s_%x_%d",
4380 suffix, idx, bp->eth_dev->data->port_id);
4381 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4382 mz = rte_memzone_lookup(mz_name);
4384 mz = rte_memzone_reserve_aligned(mz_name,
4388 RTE_MEMZONE_SIZE_HINT_ONLY |
4389 RTE_MEMZONE_IOVA_CONTIG,
4395 memset(mz->addr, 0, mz->len);
4396 mz_phys_addr = mz->iova;
4398 rmem->pg_tbl = mz->addr;
4399 rmem->pg_tbl_map = mz_phys_addr;
4400 rmem->pg_tbl_mz = mz;
4403 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d",
4404 suffix, idx, bp->eth_dev->data->port_id);
4405 mz = rte_memzone_lookup(mz_name);
4407 mz = rte_memzone_reserve_aligned(mz_name,
4411 RTE_MEMZONE_SIZE_HINT_ONLY |
4412 RTE_MEMZONE_IOVA_CONTIG,
4418 memset(mz->addr, 0, mz->len);
4419 mz_phys_addr = mz->iova;
4421 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) {
4422 rmem->pg_arr[i] = ((char *)mz->addr) + sz;
4423 rmem->dma_arr[i] = mz_phys_addr + sz;
4425 if (rmem->nr_pages > 1) {
4426 if (i == rmem->nr_pages - 2 &&
4427 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4428 valid_bits |= PTU_PTE_NEXT_TO_LAST;
4429 else if (i == rmem->nr_pages - 1 &&
4430 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
4431 valid_bits |= PTU_PTE_LAST;
4433 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] |
4439 if (rmem->vmem_size)
4440 rmem->vmem = (void **)mz->addr;
4441 rmem->dma_arr[0] = mz_phys_addr;
4445 static void bnxt_free_ctx_mem(struct bnxt *bp)
4449 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED))
4452 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED;
4453 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz);
4454 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz);
4455 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz);
4456 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz);
4457 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz);
4458 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz);
4459 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz);
4460 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz);
4461 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz);
4462 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz);
4464 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) {
4465 if (bp->ctx->tqm_mem[i])
4466 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz);
4473 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
4475 #define min_t(type, x, y) ({ \
4476 type __min1 = (x); \
4477 type __min2 = (y); \
4478 __min1 < __min2 ? __min1 : __min2; })
4480 #define max_t(type, x, y) ({ \
4481 type __max1 = (x); \
4482 type __max2 = (y); \
4483 __max1 > __max2 ? __max1 : __max2; })
4485 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
4487 int bnxt_alloc_ctx_mem(struct bnxt *bp)
4489 struct bnxt_ctx_pg_info *ctx_pg;
4490 struct bnxt_ctx_mem_info *ctx;
4491 uint32_t mem_size, ena, entries;
4492 uint32_t entries_sp, min;
4495 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
4497 PMD_DRV_LOG(ERR, "Query context mem capability failed\n");
4501 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
4504 ctx_pg = &ctx->qp_mem;
4505 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
4506 if (ctx->qp_entry_size) {
4507 mem_size = ctx->qp_entry_size * ctx_pg->entries;
4508 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0);
4513 ctx_pg = &ctx->srq_mem;
4514 ctx_pg->entries = ctx->srq_max_l2_entries;
4515 if (ctx->srq_entry_size) {
4516 mem_size = ctx->srq_entry_size * ctx_pg->entries;
4517 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0);
4522 ctx_pg = &ctx->cq_mem;
4523 ctx_pg->entries = ctx->cq_max_l2_entries;
4524 if (ctx->cq_entry_size) {
4525 mem_size = ctx->cq_entry_size * ctx_pg->entries;
4526 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0);
4531 ctx_pg = &ctx->vnic_mem;
4532 ctx_pg->entries = ctx->vnic_max_vnic_entries +
4533 ctx->vnic_max_ring_table_entries;
4534 if (ctx->vnic_entry_size) {
4535 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
4536 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0);
4541 ctx_pg = &ctx->stat_mem;
4542 ctx_pg->entries = ctx->stat_max_entries;
4543 if (ctx->stat_entry_size) {
4544 mem_size = ctx->stat_entry_size * ctx_pg->entries;
4545 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0);
4550 min = ctx->tqm_min_entries_per_ring;
4552 entries_sp = ctx->qp_max_l2_entries +
4553 ctx->vnic_max_vnic_entries +
4554 2 * ctx->qp_min_qp1_entries + min;
4555 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple);
4557 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries;
4558 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
4559 entries = clamp_t(uint32_t, entries, min,
4560 ctx->tqm_max_entries_per_ring);
4561 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
4562 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7.
4563 * i > 8 is other ext rings.
4565 ctx_pg = ctx->tqm_mem[i];
4566 ctx_pg->entries = i ? entries : entries_sp;
4567 if (ctx->tqm_entry_size) {
4568 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
4569 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size,
4574 if (i < BNXT_MAX_TQM_LEGACY_RINGS)
4575 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i;
4577 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8;
4580 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES;
4581 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
4584 "Failed to configure context mem: rc = %d\n", rc);
4586 ctx->flags |= BNXT_CTX_FLAG_INITED;
4591 static int bnxt_alloc_stats_mem(struct bnxt *bp)
4593 struct rte_pci_device *pci_dev = bp->pdev;
4594 char mz_name[RTE_MEMZONE_NAMESIZE];
4595 const struct rte_memzone *mz = NULL;
4596 uint32_t total_alloc_len;
4597 rte_iova_t mz_phys_addr;
4599 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2)
4602 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4603 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4604 pci_dev->addr.bus, pci_dev->addr.devid,
4605 pci_dev->addr.function, "rx_port_stats");
4606 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4607 mz = rte_memzone_lookup(mz_name);
4609 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) +
4610 sizeof(struct rx_port_stats_ext) + 512);
4612 mz = rte_memzone_reserve(mz_name, total_alloc_len,
4615 RTE_MEMZONE_SIZE_HINT_ONLY |
4616 RTE_MEMZONE_IOVA_CONTIG);
4620 memset(mz->addr, 0, mz->len);
4621 mz_phys_addr = mz->iova;
4623 bp->rx_mem_zone = (const void *)mz;
4624 bp->hw_rx_port_stats = mz->addr;
4625 bp->hw_rx_port_stats_map = mz_phys_addr;
4627 snprintf(mz_name, RTE_MEMZONE_NAMESIZE,
4628 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain,
4629 pci_dev->addr.bus, pci_dev->addr.devid,
4630 pci_dev->addr.function, "tx_port_stats");
4631 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0;
4632 mz = rte_memzone_lookup(mz_name);
4634 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) +
4635 sizeof(struct tx_port_stats_ext) + 512);
4637 mz = rte_memzone_reserve(mz_name,
4641 RTE_MEMZONE_SIZE_HINT_ONLY |
4642 RTE_MEMZONE_IOVA_CONTIG);
4646 memset(mz->addr, 0, mz->len);
4647 mz_phys_addr = mz->iova;
4649 bp->tx_mem_zone = (const void *)mz;
4650 bp->hw_tx_port_stats = mz->addr;
4651 bp->hw_tx_port_stats_map = mz_phys_addr;
4652 bp->flags |= BNXT_FLAG_PORT_STATS;
4654 /* Display extended statistics if FW supports it */
4655 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 ||
4656 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 ||
4657 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED))
4660 bp->hw_rx_port_stats_ext = (void *)
4661 ((uint8_t *)bp->hw_rx_port_stats +
4662 sizeof(struct rx_port_stats));
4663 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map +
4664 sizeof(struct rx_port_stats);
4665 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS;
4667 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 ||
4668 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) {
4669 bp->hw_tx_port_stats_ext = (void *)
4670 ((uint8_t *)bp->hw_tx_port_stats +
4671 sizeof(struct tx_port_stats));
4672 bp->hw_tx_port_stats_ext_map =
4673 bp->hw_tx_port_stats_map +
4674 sizeof(struct tx_port_stats);
4675 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS;
4681 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev)
4683 struct bnxt *bp = eth_dev->data->dev_private;
4686 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl",
4687 RTE_ETHER_ADDR_LEN *
4690 if (eth_dev->data->mac_addrs == NULL) {
4691 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n");
4695 if (!BNXT_HAS_DFLT_MAC_SET(bp)) {
4699 /* Generate a random MAC address, if none was assigned by PF */
4700 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n");
4701 bnxt_eth_hw_addr_random(bp->mac_addr);
4703 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n",
4704 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2],
4705 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]);
4707 rc = bnxt_hwrm_set_mac(bp);
4712 /* Copy the permanent MAC from the FUNC_QCAPS response */
4713 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN);
4718 static int bnxt_restore_dflt_mac(struct bnxt *bp)
4722 /* MAC is already configured in FW */
4723 if (BNXT_HAS_DFLT_MAC_SET(bp))
4726 /* Restore the old MAC configured */
4727 rc = bnxt_hwrm_set_mac(bp);
4729 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n");
4734 static void bnxt_config_vf_req_fwd(struct bnxt *bp)
4739 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd));
4741 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN))
4742 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG);
4743 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG);
4744 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG);
4745 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC);
4746 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD);
4750 bnxt_get_svif(uint16_t port_id, bool func_svif,
4751 enum bnxt_ulp_intf_type type)
4753 struct rte_eth_dev *eth_dev;
4756 eth_dev = &rte_eth_devices[port_id];
4757 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4758 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4762 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4765 eth_dev = vfr->parent_dev;
4768 bp = eth_dev->data->dev_private;
4770 return func_svif ? bp->func_svif : bp->port_svif;
4774 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type)
4776 struct rte_eth_dev *eth_dev;
4777 struct bnxt_vnic_info *vnic;
4780 eth_dev = &rte_eth_devices[port];
4781 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4782 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4786 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4787 return vfr->dflt_vnic_id;
4789 eth_dev = vfr->parent_dev;
4792 bp = eth_dev->data->dev_private;
4794 vnic = BNXT_GET_DEFAULT_VNIC(bp);
4796 return vnic->fw_vnic_id;
4800 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type)
4802 struct rte_eth_dev *eth_dev;
4805 eth_dev = &rte_eth_devices[port];
4806 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4807 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4811 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4814 eth_dev = vfr->parent_dev;
4817 bp = eth_dev->data->dev_private;
4822 enum bnxt_ulp_intf_type
4823 bnxt_get_interface_type(uint16_t port)
4825 struct rte_eth_dev *eth_dev;
4828 eth_dev = &rte_eth_devices[port];
4829 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev))
4830 return BNXT_ULP_INTF_TYPE_VF_REP;
4832 bp = eth_dev->data->dev_private;
4834 return BNXT_ULP_INTF_TYPE_PF;
4835 else if (BNXT_VF_IS_TRUSTED(bp))
4836 return BNXT_ULP_INTF_TYPE_TRUSTED_VF;
4837 else if (BNXT_VF(bp))
4838 return BNXT_ULP_INTF_TYPE_VF;
4840 return BNXT_ULP_INTF_TYPE_INVALID;
4844 bnxt_get_phy_port_id(uint16_t port_id)
4846 struct bnxt_representor *vfr;
4847 struct rte_eth_dev *eth_dev;
4850 eth_dev = &rte_eth_devices[port_id];
4851 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4852 vfr = eth_dev->data->dev_private;
4856 eth_dev = vfr->parent_dev;
4859 bp = eth_dev->data->dev_private;
4861 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id;
4865 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type)
4867 struct rte_eth_dev *eth_dev;
4870 eth_dev = &rte_eth_devices[port_id];
4871 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) {
4872 struct bnxt_representor *vfr = eth_dev->data->dev_private;
4876 if (type == BNXT_ULP_INTF_TYPE_VF_REP)
4877 return vfr->fw_fid - 1;
4879 eth_dev = vfr->parent_dev;
4882 bp = eth_dev->data->dev_private;
4884 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1;
4888 bnxt_get_vport(uint16_t port_id)
4890 return (1 << bnxt_get_phy_port_id(port_id));
4893 static void bnxt_alloc_error_recovery_info(struct bnxt *bp)
4895 struct bnxt_error_recovery_info *info = bp->recovery_info;
4898 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))
4899 memset(info, 0, sizeof(*info));
4903 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4906 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4909 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
4911 bp->recovery_info = info;
4914 static void bnxt_check_fw_status(struct bnxt *bp)
4918 if (!(bp->recovery_info &&
4919 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)))
4922 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG);
4923 if (fw_status != BNXT_FW_STATUS_HEALTHY)
4924 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n",
4928 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp)
4930 struct bnxt_error_recovery_info *info = bp->recovery_info;
4931 uint32_t status_loc;
4934 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 +
4935 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4936 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4937 BNXT_GRCP_WINDOW_2_BASE +
4938 offsetof(struct hcomm_status,
4940 /* If the signature is absent, then FW does not support this feature */
4941 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) !=
4942 HCOMM_STATUS_SIGNATURE_VAL)
4946 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg",
4950 bp->recovery_info = info;
4952 memset(info, 0, sizeof(*info));
4955 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
4956 BNXT_GRCP_WINDOW_2_BASE +
4957 offsetof(struct hcomm_status,
4960 /* Only pre-map the FW health status GRC register */
4961 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC)
4964 info->status_regs[BNXT_FW_STATUS_REG] = status_loc;
4965 info->mapped_status_regs[BNXT_FW_STATUS_REG] =
4966 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK);
4968 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 +
4969 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
4971 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS;
4976 /* This function gets the FW version along with the
4977 * capabilities(MAX and current) of the function, vnic,
4978 * error recovery, phy and other chip related info
4980 static int bnxt_get_config(struct bnxt *bp)
4987 rc = bnxt_map_hcomm_fw_status_reg(bp);
4991 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT);
4993 bnxt_check_fw_status(bp);
4997 rc = bnxt_hwrm_func_reset(bp);
5001 rc = bnxt_hwrm_vnic_qcaps(bp);
5005 rc = bnxt_hwrm_queue_qportcfg(bp);
5009 /* Get the MAX capabilities for this function.
5010 * This function also allocates context memory for TQM rings and
5011 * informs the firmware about this allocated backing store memory.
5013 rc = bnxt_hwrm_func_qcaps(bp);
5017 rc = bnxt_hwrm_func_qcfg(bp, &mtu);
5021 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
5025 bnxt_hwrm_port_mac_qcfg(bp);
5027 bnxt_hwrm_parent_pf_qcfg(bp);
5029 bnxt_hwrm_port_phy_qcaps(bp);
5031 bnxt_alloc_error_recovery_info(bp);
5032 /* Get the adapter error recovery support info */
5033 rc = bnxt_hwrm_error_recovery_qcfg(bp);
5035 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5037 bnxt_hwrm_port_led_qcaps(bp);
5043 bnxt_init_locks(struct bnxt *bp)
5047 err = pthread_mutex_init(&bp->flow_lock, NULL);
5049 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
5053 err = pthread_mutex_init(&bp->def_cp_lock, NULL);
5055 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
5059 err = pthread_mutex_init(&bp->health_check_lock, NULL);
5061 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n");
5065 err = pthread_mutex_init(&bp->err_recovery_lock, NULL);
5067 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n");
5072 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
5076 rc = bnxt_get_config(bp);
5080 if (!reconfig_dev) {
5081 rc = bnxt_setup_mac_addr(bp->eth_dev);
5085 rc = bnxt_restore_dflt_mac(bp);
5090 bnxt_config_vf_req_fwd(bp);
5092 rc = bnxt_hwrm_func_driver_register(bp);
5094 PMD_DRV_LOG(ERR, "Failed to register driver");
5099 if (bp->pdev->max_vfs) {
5100 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs);
5102 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n");
5106 rc = bnxt_hwrm_allocate_pf_only(bp);
5109 "Failed to allocate PF resources");
5115 rc = bnxt_alloc_mem(bp, reconfig_dev);
5119 rc = bnxt_setup_int(bp);
5123 rc = bnxt_request_int(bp);
5127 rc = bnxt_init_ctx_mem(bp);
5129 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n");
5137 bnxt_parse_devarg_truflow(__rte_unused const char *key,
5138 const char *value, void *opaque_arg)
5140 struct bnxt *bp = opaque_arg;
5141 unsigned long truflow;
5144 if (!value || !opaque_arg) {
5146 "Invalid parameter passed to truflow devargs.\n");
5150 truflow = strtoul(value, &end, 10);
5151 if (end == NULL || *end != '\0' ||
5152 (truflow == ULONG_MAX && errno == ERANGE)) {
5154 "Invalid parameter passed to truflow devargs.\n");
5158 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) {
5160 "Invalid value passed to truflow devargs.\n");
5165 bp->flags |= BNXT_FLAG_TRUFLOW_EN;
5166 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n");
5168 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN;
5169 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n");
5176 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key,
5177 const char *value, void *opaque_arg)
5179 struct bnxt *bp = opaque_arg;
5180 unsigned long flow_xstat;
5183 if (!value || !opaque_arg) {
5185 "Invalid parameter passed to flow_xstat devarg.\n");
5189 flow_xstat = strtoul(value, &end, 10);
5190 if (end == NULL || *end != '\0' ||
5191 (flow_xstat == ULONG_MAX && errno == ERANGE)) {
5193 "Invalid parameter passed to flow_xstat devarg.\n");
5197 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) {
5199 "Invalid value passed to flow_xstat devarg.\n");
5203 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN;
5204 if (BNXT_FLOW_XSTATS_EN(bp))
5205 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n");
5211 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key,
5212 const char *value, void *opaque_arg)
5214 struct bnxt *bp = opaque_arg;
5215 unsigned long max_num_kflows;
5218 if (!value || !opaque_arg) {
5220 "Invalid parameter passed to max_num_kflows devarg.\n");
5224 max_num_kflows = strtoul(value, &end, 10);
5225 if (end == NULL || *end != '\0' ||
5226 (max_num_kflows == ULONG_MAX && errno == ERANGE)) {
5228 "Invalid parameter passed to max_num_kflows devarg.\n");
5232 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) {
5234 "Invalid value passed to max_num_kflows devarg.\n");
5238 bp->max_num_kflows = max_num_kflows;
5239 if (bp->max_num_kflows)
5240 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n",
5247 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key,
5248 const char *value, void *opaque_arg)
5250 struct bnxt_representor *vfr_bp = opaque_arg;
5251 unsigned long rep_is_pf;
5254 if (!value || !opaque_arg) {
5256 "Invalid parameter passed to rep_is_pf devargs.\n");
5260 rep_is_pf = strtoul(value, &end, 10);
5261 if (end == NULL || *end != '\0' ||
5262 (rep_is_pf == ULONG_MAX && errno == ERANGE)) {
5264 "Invalid parameter passed to rep_is_pf devargs.\n");
5268 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) {
5270 "Invalid value passed to rep_is_pf devargs.\n");
5274 vfr_bp->flags |= rep_is_pf;
5275 if (BNXT_REP_PF(vfr_bp))
5276 PMD_DRV_LOG(INFO, "PF representor\n");
5278 PMD_DRV_LOG(INFO, "VF representor\n");
5284 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key,
5285 const char *value, void *opaque_arg)
5287 struct bnxt_representor *vfr_bp = opaque_arg;
5288 unsigned long rep_based_pf;
5291 if (!value || !opaque_arg) {
5293 "Invalid parameter passed to rep_based_pf "
5298 rep_based_pf = strtoul(value, &end, 10);
5299 if (end == NULL || *end != '\0' ||
5300 (rep_based_pf == ULONG_MAX && errno == ERANGE)) {
5302 "Invalid parameter passed to rep_based_pf "
5307 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) {
5309 "Invalid value passed to rep_based_pf devargs.\n");
5313 vfr_bp->rep_based_pf = rep_based_pf;
5314 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID;
5316 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf);
5322 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key,
5323 const char *value, void *opaque_arg)
5325 struct bnxt_representor *vfr_bp = opaque_arg;
5326 unsigned long rep_q_r2f;
5329 if (!value || !opaque_arg) {
5331 "Invalid parameter passed to rep_q_r2f "
5336 rep_q_r2f = strtoul(value, &end, 10);
5337 if (end == NULL || *end != '\0' ||
5338 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) {
5340 "Invalid parameter passed to rep_q_r2f "
5345 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) {
5347 "Invalid value passed to rep_q_r2f devargs.\n");
5351 vfr_bp->rep_q_r2f = rep_q_r2f;
5352 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID;
5353 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f);
5359 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key,
5360 const char *value, void *opaque_arg)
5362 struct bnxt_representor *vfr_bp = opaque_arg;
5363 unsigned long rep_q_f2r;
5366 if (!value || !opaque_arg) {
5368 "Invalid parameter passed to rep_q_f2r "
5373 rep_q_f2r = strtoul(value, &end, 10);
5374 if (end == NULL || *end != '\0' ||
5375 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) {
5377 "Invalid parameter passed to rep_q_f2r "
5382 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) {
5384 "Invalid value passed to rep_q_f2r devargs.\n");
5388 vfr_bp->rep_q_f2r = rep_q_f2r;
5389 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID;
5390 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r);
5396 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key,
5397 const char *value, void *opaque_arg)
5399 struct bnxt_representor *vfr_bp = opaque_arg;
5400 unsigned long rep_fc_r2f;
5403 if (!value || !opaque_arg) {
5405 "Invalid parameter passed to rep_fc_r2f "
5410 rep_fc_r2f = strtoul(value, &end, 10);
5411 if (end == NULL || *end != '\0' ||
5412 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) {
5414 "Invalid parameter passed to rep_fc_r2f "
5419 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) {
5421 "Invalid value passed to rep_fc_r2f devargs.\n");
5425 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID;
5426 vfr_bp->rep_fc_r2f = rep_fc_r2f;
5427 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f);
5433 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key,
5434 const char *value, void *opaque_arg)
5436 struct bnxt_representor *vfr_bp = opaque_arg;
5437 unsigned long rep_fc_f2r;
5440 if (!value || !opaque_arg) {
5442 "Invalid parameter passed to rep_fc_f2r "
5447 rep_fc_f2r = strtoul(value, &end, 10);
5448 if (end == NULL || *end != '\0' ||
5449 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) {
5451 "Invalid parameter passed to rep_fc_f2r "
5456 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) {
5458 "Invalid value passed to rep_fc_f2r devargs.\n");
5462 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID;
5463 vfr_bp->rep_fc_f2r = rep_fc_f2r;
5464 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r);
5470 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs)
5472 struct rte_kvargs *kvlist;
5474 if (devargs == NULL)
5477 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args);
5482 * Handler for "truflow" devarg.
5483 * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1"
5485 rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW,
5486 bnxt_parse_devarg_truflow, bp);
5489 * Handler for "flow_xstat" devarg.
5490 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1"
5492 rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT,
5493 bnxt_parse_devarg_flow_xstat, bp);
5496 * Handler for "max_num_kflows" devarg.
5497 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32"
5499 rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS,
5500 bnxt_parse_devarg_max_num_kflows, bp);
5502 rte_kvargs_free(kvlist);
5505 static int bnxt_alloc_switch_domain(struct bnxt *bp)
5509 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) {
5510 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id);
5513 "Failed to alloc switch domain: %d\n", rc);
5516 "Switch domain allocated %d\n",
5517 bp->switch_domain_id);
5523 /* Allocate and initialize various fields in bnxt struct that
5524 * need to be allocated/destroyed only once in the lifetime of the driver
5526 static int bnxt_drv_init(struct rte_eth_dev *eth_dev)
5528 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5529 struct bnxt *bp = eth_dev->data->dev_private;
5532 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE;
5534 if (bnxt_vf_pciid(pci_dev->id.device_id))
5535 bp->flags |= BNXT_FLAG_VF;
5537 if (bnxt_p5_device(pci_dev->id.device_id))
5538 bp->flags |= BNXT_FLAG_CHIP_P5;
5540 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 ||
5541 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 ||
5542 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 ||
5543 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF)
5544 bp->flags |= BNXT_FLAG_STINGRAY;
5546 if (BNXT_TRUFLOW_EN(bp)) {
5547 /* extra mbuf field is required to store CFA code from mark */
5548 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = {
5549 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME,
5550 .size = sizeof(bnxt_cfa_code_dynfield_t),
5551 .align = __alignof__(bnxt_cfa_code_dynfield_t),
5553 bnxt_cfa_code_dynfield_offset =
5554 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc);
5555 if (bnxt_cfa_code_dynfield_offset < 0) {
5557 "Failed to register mbuf field for TruFlow mark\n");
5562 rc = bnxt_map_pci_bars(eth_dev);
5565 "Failed to initialize board rc: %x\n", rc);
5569 rc = bnxt_alloc_pf_info(bp);
5573 rc = bnxt_alloc_link_info(bp);
5577 rc = bnxt_alloc_parent_info(bp);
5581 rc = bnxt_alloc_hwrm_resources(bp);
5584 "Failed to allocate hwrm resource rc: %x\n", rc);
5587 rc = bnxt_alloc_leds_info(bp);
5591 rc = bnxt_alloc_cos_queues(bp);
5595 rc = bnxt_init_locks(bp);
5599 rc = bnxt_alloc_switch_domain(bp);
5607 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused)
5609 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
5610 static int version_printed;
5614 if (version_printed++ == 0)
5615 PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
5617 eth_dev->dev_ops = &bnxt_dev_ops;
5618 eth_dev->rx_queue_count = bnxt_rx_queue_count_op;
5619 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op;
5620 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op;
5621 eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
5622 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
5625 * For secondary processes, we don't initialise any further
5626 * as primary has already done this work.
5628 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5631 rte_eth_copy_pci_info(eth_dev, pci_dev);
5632 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
5634 bp = eth_dev->data->dev_private;
5636 /* Parse dev arguments passed on when starting the DPDK application. */
5637 bnxt_parse_dev_args(bp, pci_dev->device.devargs);
5639 rc = bnxt_drv_init(eth_dev);
5643 rc = bnxt_init_resources(bp, false);
5647 rc = bnxt_alloc_stats_mem(bp);
5652 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n",
5653 pci_dev->mem_resource[0].phys_addr,
5654 pci_dev->mem_resource[0].addr);
5659 bnxt_dev_uninit(eth_dev);
5664 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx)
5673 ctx->dma = RTE_BAD_IOVA;
5674 ctx->ctx_id = BNXT_CTX_VAL_INVAL;
5677 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp)
5679 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX,
5680 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5681 bp->flow_stat->rx_fc_out_tbl.ctx_id,
5682 bp->flow_stat->max_fc,
5685 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX,
5686 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC,
5687 bp->flow_stat->tx_fc_out_tbl.ctx_id,
5688 bp->flow_stat->max_fc,
5691 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5692 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id);
5693 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5695 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5696 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id);
5697 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5699 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5700 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id);
5701 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5703 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL)
5704 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id);
5705 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL;
5708 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp)
5710 bnxt_unregister_fc_ctx_mem(bp);
5712 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl);
5713 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl);
5714 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl);
5715 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl);
5718 static void bnxt_uninit_ctx_mem(struct bnxt *bp)
5720 if (BNXT_FLOW_XSTATS_EN(bp))
5721 bnxt_uninit_fc_ctx_mem(bp);
5725 bnxt_free_error_recovery_info(struct bnxt *bp)
5727 rte_free(bp->recovery_info);
5728 bp->recovery_info = NULL;
5729 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
5733 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
5738 bnxt_free_mem(bp, reconfig_dev);
5740 bnxt_hwrm_func_buf_unrgtr(bp);
5741 rte_free(bp->pf->vf_req_buf);
5743 rc = bnxt_hwrm_func_driver_unregister(bp, 0);
5744 bp->flags &= ~BNXT_FLAG_REGISTERED;
5745 bnxt_free_ctx_mem(bp);
5746 if (!reconfig_dev) {
5747 bnxt_free_hwrm_resources(bp);
5748 bnxt_free_error_recovery_info(bp);
5751 bnxt_uninit_ctx_mem(bp);
5753 bnxt_free_flow_stats_info(bp);
5754 bnxt_free_rep_info(bp);
5755 rte_free(bp->ptp_cfg);
5761 bnxt_dev_uninit(struct rte_eth_dev *eth_dev)
5763 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5766 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n");
5768 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
5769 bnxt_dev_close_op(eth_dev);
5774 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev)
5776 struct bnxt *bp = eth_dev->data->dev_private;
5777 struct rte_eth_dev *vf_rep_eth_dev;
5783 for (i = 0; i < bp->num_reps; i++) {
5784 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev;
5785 if (!vf_rep_eth_dev)
5787 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n",
5788 vf_rep_eth_dev->data->port_id);
5789 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit);
5791 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n",
5792 eth_dev->data->port_id);
5793 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit);
5798 static void bnxt_free_rep_info(struct bnxt *bp)
5800 rte_free(bp->rep_info);
5801 bp->rep_info = NULL;
5802 rte_free(bp->cfa_code_map);
5803 bp->cfa_code_map = NULL;
5806 static int bnxt_init_rep_info(struct bnxt *bp)
5813 bp->rep_info = rte_zmalloc("bnxt_rep_info",
5814 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS,
5816 if (!bp->rep_info) {
5817 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n");
5820 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map",
5821 sizeof(*bp->cfa_code_map) *
5822 BNXT_MAX_CFA_CODE, 0);
5823 if (!bp->cfa_code_map) {
5824 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n");
5825 bnxt_free_rep_info(bp);
5829 for (i = 0; i < BNXT_MAX_CFA_CODE; i++)
5830 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID;
5832 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL);
5834 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n");
5835 bnxt_free_rep_info(bp);
5839 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL);
5841 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n");
5842 bnxt_free_rep_info(bp);
5849 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev,
5850 struct rte_eth_devargs *eth_da,
5851 struct rte_eth_dev *backing_eth_dev,
5852 const char *dev_args)
5854 struct rte_eth_dev *vf_rep_eth_dev;
5855 char name[RTE_ETH_NAME_MAX_LEN];
5856 struct bnxt *backing_bp;
5859 struct rte_kvargs *kvlist = NULL;
5861 num_rep = eth_da->nb_representor_ports;
5862 if (num_rep > BNXT_MAX_VF_REPS) {
5863 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n",
5864 num_rep, BNXT_MAX_VF_REPS);
5868 if (num_rep >= RTE_MAX_ETHPORTS) {
5870 "nb_representor_ports = %d > %d MAX ETHPORTS\n",
5871 num_rep, RTE_MAX_ETHPORTS);
5875 backing_bp = backing_eth_dev->data->dev_private;
5877 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) {
5879 "Not a PF or trusted VF. No Representor support\n");
5880 /* Returning an error is not an option.
5881 * Applications are not handling this correctly
5886 if (bnxt_init_rep_info(backing_bp))
5889 for (i = 0; i < num_rep; i++) {
5890 struct bnxt_representor representor = {
5891 .vf_id = eth_da->representor_ports[i],
5892 .switch_domain_id = backing_bp->switch_domain_id,
5893 .parent_dev = backing_eth_dev
5896 if (representor.vf_id >= BNXT_MAX_VF_REPS) {
5897 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n",
5898 representor.vf_id, BNXT_MAX_VF_REPS);
5902 /* representor port net_bdf_port */
5903 snprintf(name, sizeof(name), "net_%s_representor_%d",
5904 pci_dev->device.name, eth_da->representor_ports[i]);
5906 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args);
5909 * Handler for "rep_is_pf" devarg.
5910 * Invoked as for ex: "-a 000:00:0d.0,
5911 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5913 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF,
5914 bnxt_parse_devarg_rep_is_pf,
5915 (void *)&representor);
5921 * Handler for "rep_based_pf" devarg.
5922 * Invoked as for ex: "-a 000:00:0d.0,
5923 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5925 ret = rte_kvargs_process(kvlist,
5926 BNXT_DEVARG_REP_BASED_PF,
5927 bnxt_parse_devarg_rep_based_pf,
5928 (void *)&representor);
5934 * Handler for "rep_based_pf" devarg.
5935 * Invoked as for ex: "-a 000:00:0d.0,
5936 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5938 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F,
5939 bnxt_parse_devarg_rep_q_r2f,
5940 (void *)&representor);
5946 * Handler for "rep_based_pf" devarg.
5947 * Invoked as for ex: "-a 000:00:0d.0,
5948 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5950 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R,
5951 bnxt_parse_devarg_rep_q_f2r,
5952 (void *)&representor);
5958 * Handler for "rep_based_pf" devarg.
5959 * Invoked as for ex: "-a 000:00:0d.0,
5960 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5962 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F,
5963 bnxt_parse_devarg_rep_fc_r2f,
5964 (void *)&representor);
5970 * Handler for "rep_based_pf" devarg.
5971 * Invoked as for ex: "-a 000:00:0d.0,
5972 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>"
5974 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R,
5975 bnxt_parse_devarg_rep_fc_f2r,
5976 (void *)&representor);
5983 ret = rte_eth_dev_create(&pci_dev->device, name,
5984 sizeof(struct bnxt_representor),
5986 bnxt_representor_init,
5989 PMD_DRV_LOG(ERR, "failed to create bnxt vf "
5990 "representor %s.", name);
5994 vf_rep_eth_dev = rte_eth_dev_allocated(name);
5995 if (!vf_rep_eth_dev) {
5996 PMD_DRV_LOG(ERR, "Failed to find the eth_dev"
5997 " for VF-Rep: %s.", name);
6002 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n",
6003 backing_eth_dev->data->port_id);
6004 backing_bp->rep_info[representor.vf_id].vfr_eth_dev =
6006 backing_bp->num_reps++;
6010 rte_kvargs_free(kvlist);
6014 /* If num_rep > 1, then rollback already created
6015 * ports, since we'll be failing the probe anyway
6018 bnxt_pci_remove_dev_with_reps(backing_eth_dev);
6020 rte_kvargs_free(kvlist);
6025 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
6026 struct rte_pci_device *pci_dev)
6028 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
6029 struct rte_eth_dev *backing_eth_dev;
6033 if (pci_dev->device.devargs) {
6034 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args,
6040 num_rep = eth_da.nb_representor_ports;
6041 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n",
6044 /* We could come here after first level of probe is already invoked
6045 * as part of an application bringup(OVS-DPDK vswitchd), so first check
6046 * for already allocated eth_dev for the backing device (PF/Trusted VF)
6048 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6049 if (backing_eth_dev == NULL) {
6050 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
6051 sizeof(struct bnxt),
6052 eth_dev_pci_specific_init, pci_dev,
6053 bnxt_dev_init, NULL);
6055 if (ret || !num_rep)
6058 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6060 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n",
6061 backing_eth_dev->data->port_id);
6066 /* probe representor ports now */
6067 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev,
6068 pci_dev->device.devargs->args);
6073 static int bnxt_pci_remove(struct rte_pci_device *pci_dev)
6075 struct rte_eth_dev *eth_dev;
6077 eth_dev = rte_eth_dev_allocated(pci_dev->device.name);
6079 return 0; /* Invoked typically only by OVS-DPDK, by the
6080 * time it comes here the eth_dev is already
6081 * deleted by rte_eth_dev_close(), so returning
6082 * +ve value will at least help in proper cleanup
6085 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id);
6086 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
6087 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
6088 return rte_eth_dev_destroy(eth_dev,
6089 bnxt_representor_uninit);
6091 return rte_eth_dev_destroy(eth_dev,
6094 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
6098 static struct rte_pci_driver bnxt_rte_pmd = {
6099 .id_table = bnxt_pci_id_map,
6100 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
6101 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs
6104 .probe = bnxt_pci_probe,
6105 .remove = bnxt_pci_remove,
6109 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
6111 if (strcmp(dev->device->driver->name, drv->driver.name))
6117 bool is_bnxt_supported(struct rte_eth_dev *dev)
6119 return is_device_supported(dev, &bnxt_rte_pmd);
6122 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE);
6123 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd);
6124 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map);
6125 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci");